From ca5845684388e564495ea0108091a580d8a8e419 Mon Sep 17 00:00:00 2001 From: xym <565000561@qq.com> Date: Mon, 15 May 2023 11:59:06 +0800 Subject: [PATCH] =?UTF-8?q?[bsp][rt1061]=20=E6=96=B0=E5=A2=9E=E9=A3=9E?= =?UTF-8?q?=E5=87=8C=20ok1061-s=20=E5=BC=80=E5=8F=91=E6=9D=BF=20bsp=20(#74?= =?UTF-8?q?68)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/imxrt/imxrt1061-forlinx-OK1061-S/.config | 1012 + bsp/imxrt/imxrt1061-forlinx-OK1061-S/Kconfig | 16 + .../imxrt1061-forlinx-OK1061-S/README.md | 126 + .../imxrt1061-forlinx-OK1061-S/SConscript | 14 + .../imxrt1061-forlinx-OK1061-S/SConstruct | 71 + .../applications/SConscript | 22 + .../applications/main.c | 31 + .../imxrt1061-forlinx-OK1061-S/board/Kconfig | 99 + .../board/MCUX_Config/MCUX_Config.mex | 495 + .../board/MCUX_Config/clock_config.c | 458 + .../board/MCUX_Config/clock_config.h | 116 + .../board/MCUX_Config/pin_mux.c | 64 + .../board/MCUX_Config/pin_mux.h | 57 + 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0000000000..a5ab062292 --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/.config @@ -0,0 +1,1012 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_SMALL_MEM is not set +# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set +CONFIG_RT_USING_MEMHEAP_AS_HEAP=y +CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x50001 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_USING_CACHE=y +CONFIG_RT_USING_HW_ATOMIC=y +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_FPU=y +CONFIG_ARCH_ARM_CORTEX_M7=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_UKAL is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects +# +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# +CONFIG_SOC_IMXRT1060_SERIES=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_IMXRT1061CVL5A=y + +# +# On-chip Peripheral Drivers +# +# CONFIG_BSP_USING_DMA is not set +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_CAN is not set +CONFIG_BSP_USING_LPUART=y +CONFIG_BSP_USING_LPUART1=y +# CONFIG_BSP_LPUART1_RX_USING_DMA is not set +# CONFIG_BSP_LPUART1_TX_USING_DMA is not set +# CONFIG_BSP_USING_LPUART4 is not set +# CONFIG_BSP_USING_HWTIMER is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_RTC is not set + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_RGB is not set +# CONFIG_BSP_USING_MPU6050 is not set +# CONFIG_BSP_USING_AP3216C is not set +# CONFIG_BSP_USING_EEPROM is not set +# CONFIG_BSP_USING_RS232 is not set +# CONFIG_BSP_USING_RS485 is not set + +# +# Board extended module Drivers +# diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/Kconfig b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/Kconfig new file mode 100644 index 0000000000..c9221717cb --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/Kconfig @@ -0,0 +1,16 @@ +mainmenu "RT-Thread Configuration" + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/README.md b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/README.md new file mode 100644 index 0000000000..b4483d593b --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/README.md @@ -0,0 +1,126 @@ +# OK1061-S å¼€å‘æ¿ BSP 说明 + +## 简介 + +本文档为 RT-Thread å¼€å‘团队为飞凌 OK1061-S å¼€å‘æ¿æ供的 BSP (æ¿çº§æ”¯æŒåŒ…) 说明。 + +主è¦å†…容如下： + +- å¼€å‘æ¿èµ„æºä»‹ç» +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开å‘者å¯ä»¥å¿«é€Ÿåœ°ä¸Šæ‰‹è¯¥ BSP，将 RT-Thread è¿è¡Œåœ¨å¼€å‘æ¿ä¸Šã€‚在进阶使用指å—章节，将会介ç»æ›´å¤šé«˜çº§åŠŸèƒ½ï¼Œå¸®åŠ©å¼€å‘者利用 RT-Thread 驱动更多æ¿è½½èµ„æºã€‚ + +## å¼€å‘æ¿ä»‹ç» + + +OK1061-S å¼€å‘æ¿åŸºäºŽ NXP å…¬å¸ i.MX RT1061 跨界处ç†å™¨è®¾è®¡ï¼Œæ­è½½ ARM Cortex -M7 内核，集微控制器的低功耗ã€æ˜“用性与应用处ç†å™¨çš„高性能ã€é«˜æ‰©å±•æ€§äºŽä¸€ä½“。底æ¿+核心æ¿åˆ†ç¦»ç»“构，采用邮票孔å°è£…设计，核心æ¿ä½“积å°å·§ä»…30×30×3mm，引脚数é‡100PIN，间è·1.0mm，方便嵌入å„ç§å°ºå¯¸çš„设备中。 + + +è¿è¡Œé¢‘率 528MHz(商业级为600MHz)，1MB片上SRAM多达 512KB å¯é…置为紧耦åˆå­˜å‚¨å™¨ (TCM)，QSPI-Nor Flash 支æŒå®¹é‡4MB。底æ¿+核心æ¿åˆ†ç¦»ç»“构，采用邮票孔å°è£…设计，核心æ¿ä½“积å°å·§ä»…30×30×3mm，引脚数é‡100PIN，间è·1.0mm，方便嵌入å„ç§å°ºå¯¸çš„设备中。为了更大é™åº¦å‘挥CPU特性，核心æ¿å¼•å‡ºCPU大部分功能，åŒæ—¶é…备了一系列特别适åˆå®žæ—¶åº”用的功能，例如高速GPIO ã€CAN-FD，以åŠåŒæ­¥å¹¶è¡Œ NAND/NOR/PSRAM 控制器。工业级设计核心æ¿ï¼Œè¿è¡Œæ¸©å®½ -40℃~+85℃；为了更加方便客户评估使用，OK1061-Så¼€å‘æ¿å¼•å‡ºUARTã€Ethernet*2ã€USBã€CANã€CAN FDã€HS_GPIOã€PWMã€ADC等丰富外设功能；支æŒè£¸æœºï¼ŒFreeRTOS等实时系统。 + + +å¼€å‘æ¿å¤–观如下图所示： + +
+ +
+ + +该开å‘æ¿å¸¸ç”¨**æ¿è½½èµ„æº**如下： + +- MCU：MIMXRT1061CVL5B，主频 600MHz，1024KB RAM(512 KB å¯é…置为 TCM) +- 外部 FLASHï¼šåž‹å· 25Q32JVSIQ，4MB +- 常用接å£ï¼šRS232ã€SD å¡æŽ¥å£ã€ä»¥å¤ªç½‘接å£ã€USB Hostã€USB OTGç­‰ +- 调试接å£ï¼šSWD + +å¼€å‘æ¿æ›´å¤šè¯¦ç»†ä¿¡æ¯è¯·å‚è€ƒé£žå‡ŒåµŒå…¥å¼ [OK1061-S å¼€å‘æ¿](https://www.forlinx.com/product/rs1061-45.html)。 + +## å¤–è®¾æ”¯æŒ + +本 BSP ç›®å‰å¯¹å¤–设的支æŒæƒ…况如下： + +| **æ¿è½½å¤–设** | **支æŒæƒ…况** | **备注** | +| :---------- | :----: | :----------------------- | +| RS232 | æ”¯æŒ | UART1 | +| LED | æ”¯æŒ | | +| Ethernet | æš‚ä¸æ”¯æŒ | | +| SD å¡ | æš‚ä¸æ”¯æŒ | | +| EEPROM | æš‚ä¸æ”¯æŒ | | +| **片上外设** | **支æŒæƒ…况** | **备注** | +| GPIO | æ”¯æŒ | | +| UART | æ”¯æŒ | UART1ã€UART2 | +| SPI | æš‚ä¸æ”¯æŒ | å³å°†æ”¯æŒ | +| IIC | æš‚ä¸æ”¯æŒ | å³å°†æ”¯æŒ | +| ADC | æš‚ä¸æ”¯æŒ | å³å°†æ”¯æŒ | +| RTC | æš‚ä¸æ”¯æŒ | å³å°†æ”¯æŒ | +| PWM | æš‚ä¸æ”¯æŒ | å³å°†æ”¯æŒ | +| CAN | æš‚ä¸æ”¯æŒ | å³å°†æ”¯æŒ | + + +## Keil IDE 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，éµå¾ªç®€å•çš„步骤å³å¯å°† RT-Thread æ“作系统è¿è¡Œåœ¨è¯¥å¼€å‘æ¿ä¸Šï¼Œçœ‹åˆ°å®žéªŒæ•ˆæžœ 。 + +- 进阶使用 + + 本章节是为需è¦åœ¨ RT-Thread æ“作系统上使用更多开å‘æ¿èµ„æºçš„å¼€å‘者准备的。通过使用 ENV 工具对 BSP 进行é…置，å¯ä»¥å¼€å¯æ›´å¤šæ¿è½½èµ„æºï¼Œå®žçŽ°æ›´å¤šé«˜çº§åŠŸèƒ½ã€‚ + + +### 快速上手 + +本 BSP 为开å‘者æä¾› MDK5 å’Œ IAR å·¥ç¨‹ï¼Œå¹¶ä¸”æ”¯æŒ GCC å¼€å‘环境。下é¢ä»¥ MDK5 å¼€å‘环境为例，介ç»å¦‚何将系统è¿è¡Œèµ·æ¥ã€‚ + +#### 硬件连接 + +使用数æ®çº¿è¿žæŽ¥å¼€å‘æ¿åˆ° PC，打开电æºå¼€å…³ã€‚ + +#### 编译下载 + +首先需è¦å°†éœ€è¦å°† RT1061 çš„ FLASH 下载算法（board目录下的 MIMXRT_QSPIFLASH.FLM 文件）拷è´åˆ° `MDK 安装路径/ARM/Flash` 文件夹中。åŒå‡» `project.uvprojx` 文件，打开 MDK5 工程，在调试选项里 `Flash Download` 一æ ä¸­æŒ‰ç…§ä¸‹å›¾æ‰€ç¤ºé€‰æ‹©ä¸‹è½½ç®—法并ä¿å­˜è®¾ç½®ï¼š + +
+ +
+ +编译工程，工程默认é…置使用 CMSIS-DAP 下载程åºï¼Œåœ¨é€šè¿‡ CMSIS-DAP 连接开å‘æ¿çš„基础上，点击下载按钮å³å¯ä¸‹è½½ç¨‹åºåˆ°å¼€å‘æ¿ã€‚ + +#### è¿è¡Œç»“æžœ + +下载程åºæˆåŠŸä¹‹åŽï¼Œç³»ç»Ÿä¼šè‡ªåŠ¨è¿è¡Œï¼Œè§‚察开å‘æ¿ä¸Š LED çš„è¿è¡Œæ•ˆæžœï¼Œè“色 LED 会周期性闪çƒã€‚ + +连接开å‘æ¿å¯¹åº”串å£åˆ° PC , 在终端工具里打开相应的串å£ï¼ˆ115200-8-1-N），å¤ä½è®¾å¤‡åŽï¼Œå¯ä»¥çœ‹åˆ° RT-Thread 的输出信æ¯: + +```bash + \ | / +- RT - Thread Operating System + / | \ 5.0.1 build May 9 2023 15:35:22 + 2006 - 2022 Copyright by RT-Thread team +msh > +``` +### 进阶使用 + +æ­¤ BSP 默认åªå¼€å¯äº† GPIO å’Œ ä¸²å£ 1 的功能，如果需使用更多高级外设功能，需è¦åˆ©ç”¨ ENV 工具对 BSP 进行é…置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入 `menuconfig` 命令é…置工程，é…置好之åŽä¿å­˜é€€å‡ºã€‚ + +3. 输入 `pkgs --update` 命令更新软件包。 + +4. 输入 `scons --target=mdk5/iar` 命令é‡æ–°ç”Ÿæˆå·¥ç¨‹ã€‚ + +本章节更多详细的介ç»è¯·å‚考 [IMXRT系列BSP外设驱动使用教程](../docs/IMXRT系列BSP外设驱动使用教程.md)。 + + + +## è”ç³»äººä¿¡æ¯ + +维护人: + +- [xym-ee](https://github.com/xym-ee) \ No newline at end of file diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/SConscript b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/SConscript new file mode 100644 index 0000000000..c7ef7659ec --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/SConstruct b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/SConstruct new file mode 100644 index 0000000000..7f4f6a70b1 --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/SConstruct @@ -0,0 +1,71 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT +DefaultEnvironment(tools=[]) +if rtconfig.PLATFORM == 'armcc': + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + # overwrite cflags, because cflags has '--C99' + CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES') +else: + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +imxrt_library = 'MIMXRT1061' +rtconfig.BSP_LIBRARY_TYPE = imxrt_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, imxrt_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/applications/SConscript b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/applications/SConscript new file mode 100644 index 0000000000..050054c59f --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/applications/SConscript @@ -0,0 +1,22 @@ +import rtconfig +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +# add for startup script +if rtconfig.PLATFORM in ['gcc']: + CPPDEFINES = ['__START=entry'] +else: + CPPDEFINES = [] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/applications/main.c b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/applications/main.c new file mode 100644 index 0000000000..a56af5624f --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/applications/main.c @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-05-09 xym-ee first version + */ + +#include +#include +#include + +/* defined the LED pin: GPIO1_IO9 */ +#define LED0_PIN GET_PIN(1,9) + +int main(void) +{ + /* set LED0 pin mode to output */ + rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED0_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED0_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} + diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/Kconfig b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/Kconfig new file mode 100644 index 0000000000..a6f58ea8fa --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/Kconfig @@ -0,0 +1,99 @@ +menu "Hardware Drivers Config" + +config SOC_IMXRT1061CVL5A + bool + select SOC_IMXRT1060_SERIES + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + + config BSP_USING_DMA + bool "Enable DMA" + default n + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_LPUART + bool "Enable UART" + select RT_USING_SERIAL + default y + + if BSP_USING_LPUART + config BSP_USING_LPUART1 + bool "Enable LPUART1" + default y + + config BSP_LPUART1_RX_USING_DMA + bool "Enable LPUART1 RX DMA" + depends on BSP_USING_LPUART1 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART1_RX_DMA_CHANNEL + depends on BSP_LPUART1_RX_USING_DMA + int "Set LPUART1 RX DMA channel (0-32)" + default 0 + + config BSP_LPUART1_TX_USING_DMA + bool "Enable LPUART1 TX DMA" + depends on BSP_USING_LPUART1 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART1_TX_DMA_CHANNEL + depends on BSP_LPUART1_TX_USING_DMA + int "Set LPUART1 TX DMA channel (0-32)" + default 1 + + config BSP_USING_LPUART2 + bool "Enable LPUART2" + default n + + config BSP_LPUART2_RX_USING_DMA + bool "Enable LPUART2 RX DMA" + depends on BSP_USING_LPUART2 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART2_RX_DMA_CHANNEL + depends on BSP_LPUART2_RX_USING_DMA + int "Set LPUART2 RX DMA channel (0-32)" + default 2 + + config BSP_LPUART2_TX_USING_DMA + bool "Enable LPUART2 TX DMA" + depends on BSP_USING_LPUART2 + select BSP_USING_DMA + select RT_SERIAL_USING_DMA + default n + + config BSP_LPUART2_TX_DMA_CHANNEL + depends on BSP_LPUART2_TX_USING_DMA + int "Set LPUART2 TX DMA channel (0-32)" + default 3 + endif + +endmenu + +menu "Onboard Peripheral Drivers" + + config BSP_USING_RS232 + bool "Enable RS232" + select BSP_USING_LPUART1 + default n + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/MCUX_Config/MCUX_Config.mex b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/MCUX_Config/MCUX_Config.mex new file mode 100644 index 0000000000..371b35d144 --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/MCUX_Config/MCUX_Config.mex @@ -0,0 +1,495 @@ + + + + MIMXRT1061xxxxB + MIMXRT1061CVL5B + A + ksdk2_0 + + + + + + + false + false + false + true + false + + + + + + + + + 13.0.2 + + + + + + + + + + + Configures pin routing and optionally pin electrical features. + + false + core0 + true + + + + + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + 13.0.2 + + + + + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + INPUT + + + + + true + + + + + OUTPUT + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + + + + + N/A + + + + + + + + true + + + + + 2.5.1 + + + + + true + + + + + 2.2.0 + + + + + + 13.0.2 + + + + + + + + + 0 + + + + + true + + + + + true + + + + + 0 + + + + + true + + + + + true + + + + + 0 + + + + + true + + + + + true + + + + + 0 + + + + + true + + + + + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + N/A + + + + + + + \ No newline at end of file diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/MCUX_Config/clock_config.c b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/MCUX_Config/clock_config.c new file mode 100644 index 0000000000..ea155af64d --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/MCUX_Config/clock_config.c @@ -0,0 +1,458 @@ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. + * + * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. + * + * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v11.0 +processor: MIMXRT1061xxxxB +package_id: MIMXRT1061CVL5B +mcu_data: ksdk2_0 +processor_version: 13.0.2 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "clock_config.h" +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} +- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz} +- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CLK_24M.outFreq, value: 24 MHz} +- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz} +- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} +- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} +- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 264 MHz} +- {id: FLEXSPI_CLK_ROOT.outFreq, value: 2880/11 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} +- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} +- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} +- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} +- {id: LVDS1_CLK.outFreq, value: 1.2 GHz} +- {id: MQS_MCLK.outFreq, value: 1080/17 MHz} +- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} +- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} +- {id: SAI1_MCLK3.outFreq, value: 30 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI2_MCLK3.outFreq, value: 30 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} +- {id: SAI3_MCLK3.outFreq, value: 30 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} +- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} +- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} +- {id: UART_CLK_ROOT.outFreq, value: 80 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} +settings: +- {id: CCM.AHB_PODF.scale, value: '1', locked: true} +- {id: CCM.ARM_PODF.scale, value: '2', locked: true} +- {id: CCM.FLEXSPI_PODF.scale, value: '1', locked: true} +- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} +- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} +- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} +- {id: CCM.SEMC_PODF.scale, value: '8'} +- {id: CCM.TRACE_PODF.scale, value: '3', locked: true} +- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} +- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} +- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} +- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} +- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} +- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} +- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} +- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} +- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} +- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} +- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} +- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} +- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} +- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} +- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} +- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} +- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} +- {id: CCM_ANALOG.PLL4.denom, value: '50'} +- {id: CCM_ANALOG.PLL4.div, value: '47'} +- {id: CCM_ANALOG.PLL5.denom, value: '1'} +- {id: CCM_ANALOG.PLL5.div, value: '40'} +- {id: CCM_ANALOG.PLL5.num, value: '0'} +- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} +- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} +sources: +- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ + .numerator = 0, /* 30 bit numerator of fractional loop divider */ + .denominator = 1, /* 30 bit denominator of fractional loop divider */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = + { + .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ + .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ + }; +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /* Init RTC OSC clock frequency. */ + CLOCK_SetRtcXtalFreq(32768U); + /* Enable 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 0); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 3); +#endif + /* Disable Flexspi2 clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi2); + /* Set FLEXSPI2_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1); + /* Set Flexspi2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexspi2Mux, 3); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 2); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 2); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can3); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + CLOCK_DisableClock(kCLOCK_Can3S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. + * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ +#ifndef SKIP_SYSCLK_INIT +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." +#endif + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. + * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); + /* Disable Usb1 PLL output for USBPHY1. */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* DeInit Video PLL. */ + CLOCK_DeinitVideoPll(); + /* Bypass Video PLL. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; + /* Set divider for Video PLL. */ + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); + /* Enable Video PLL output. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Set Enet2 output divider. */ + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); + /* Enable Enet2 output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* DeInit Usb2 PLL. */ + CLOCK_DeinitUsb2Pll(); + /* Bypass Usb2 PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); + /* Enable Usb2 PLL output. */ + CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; + /* Set ENET2 Ref clock source. */ + IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} + diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/MCUX_Config/clock_config.h b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/MCUX_Config/clock_config.h new file mode 100644 index 0000000000..17ad8f5e50 --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/MCUX_Config/clock_config.h @@ -0,0 +1,116 @@ +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 264000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 261818181UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/MCUX_Config/pin_mux.c b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/MCUX_Config/pin_mux.c new file mode 100644 index 0000000000..cb59c47123 --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/MCUX_Config/pin_mux.c @@ -0,0 +1,64 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v13.1 +processor: MIMXRT1061xxxxB +package_id: MIMXRT1061CVL5B +mcu_data: ksdk2_0 +processor_version: 13.0.2 +pin_labels: +- {pin_num: G11, pin_signal: GPIO_AD_B0_03, label: BSP_BEEP} +- {pin_num: L13, pin_signal: GPIO_AD_B1_10, label: BSP_RS485_RE, identifier: CSI_D7} +- {pin_num: J13, pin_signal: GPIO_AD_B1_11, label: BSP_DS18B20, identifier: CSI_D6} +- {pin_num: K12, pin_signal: GPIO_AD_B1_05, label: BSP_AP3216C_INT, identifier: CSI_MCLK} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "fsl_iomuxc.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'false', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12} + - {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13} + - {pin_num: L11, peripheral: LPUART2, signal: TX, pin_signal: GPIO_AD_B1_02} + - {pin_num: M12, peripheral: LPUART2, signal: RX, pin_signal: GPIO_AD_B1_03} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_02_LPUART2_TX, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_03_LPUART2_RX, 0U); +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/MCUX_Config/pin_mux.h b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/MCUX_Config/pin_mux.h new file mode 100644 index 0000000000..646bd5c065 --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/MCUX_Config/pin_mux.h @@ -0,0 +1,57 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/MIMXRT_QSPIFLASH.FLM b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/MIMXRT_QSPIFLASH.FLM new file mode 100644 index 0000000000000000000000000000000000000000..097d6c449bcfec59f95b4f6f0d4a62d85351bf39 GIT binary patch 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zq)%6p`p1Uj_1Vu9a#!GQZ!Gi*XtfoAa2vlg&6)LQjG>(k*9WwpspL*Q&KX;&!|-3L zT_!%$|K&@Mb6TJGF4%_41j3y;XO?rysf?kW4Yv*Gl^SPpH_uXkqaDXwJ9z|R{W0|~ z;)mabb@MNo +#include +#include "board.h" +#include "pin_mux.h" + +#ifdef BSP_USING_DMA +#include "fsl_dmamux.h" +#include "fsl_edma.h" +#endif + +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +/* MPU configuration. */ +static void BOARD_ConfigMPU(void) +{ + /* Disable I cache and D cache */ + SCB_DisableICache(); + SCB_DisableDCache(); + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* Region 0 setting */ + MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 1 setting */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + + /* Region 2 setting */ + // spi flash: normal type, cacheable, no bufferable, no shareable + MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 3 setting */ + MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + + /* Region 4 setting */ + MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 5 setting */ + MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 6 setting */ + MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + +#if defined(BSP_USING_SDRAM) + /* Region 7 setting */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); + + /* Region 8 setting */ + MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 1, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); +#endif + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable I cache and D cache */ + SCB_EnableDCache(); + SCB_EnableICache(); +} + + +/* This is the timer interrupt service routine. */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#ifdef BSP_USING_DMA +void imxrt_dma_init(void) +{ + edma_config_t config; + + DMAMUX_Init(DMAMUX); + EDMA_GetDefaultConfig(&config); + EDMA_Init(DMA0, &config); +} +#endif + +void rt_hw_board_init() +{ + BOARD_ConfigMPU(); + BOARD_InitPins(); + BOARD_BootClockRUN(); + + NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + +#ifdef BSP_USING_DMA + imxrt_dma_init(); +#endif + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/board.h b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/board.h new file mode 100644 index 0000000000..52da9ab37b --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/board.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2023-05-09 xym-ee port to this bsp + */ + +// <<< Use Configuration Wizard in Context Menu >>> +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "fsl_common.h" +#include "clock_config.h" +#include "drv_gpio.h" + +#ifdef __CC_ARM +extern int Image$$RTT_HEAP$$ZI$$Base; +extern int Image$$RTT_HEAP$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RTT_HEAP$$ZI$$Base) +#define HEAP_END (&Image$$RTT_HEAP$$ZI$$Limit) + +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +extern void __RTT_HEAP_END; +#define HEAP_END (&__RTT_HEAP_END) + +#else +extern int heap_start; +extern int heap_end; +#define HEAP_BEGIN (&heap_start) +#define HEAP_END (&heap_end) +#endif + +#define HEAP_SIZE ((uint32_t)HEAP_END - (uint32_t)HEAP_BEGIN) + +void rt_hw_board_init(void); + +#endif + diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/evkmimxrt1060.mac b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/evkmimxrt1060.mac new file mode 100644 index 0000000000..b932afa896 --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/evkmimxrt1060.mac @@ -0,0 +1,87 @@ +/* + * Copyright 2018 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +_load_dcdc_trim() +{ + __var ocotp_base; + __var ocotp_fuse_bank0_base; + __var dcdc_base; + __var reg; + __var trim_value; + __var dcdc_trim_loaded; + __var index; + + ocotp_base = 0x401F4000; + ocotp_fuse_bank0_base = 0x401F4000 + 0x400; + dcdc_base = 0x40080000; + + dcdc_trim_loaded = 0; + + reg = __readMemory32(ocotp_fuse_bank0_base + 0x90, "Memory"); + if (reg & (1<<10)) + { + // DCDC: REG0->VBG_TRM + trim_value = (reg & (0x1F << 11)) >> 11; + reg = (__readMemory32(dcdc_base + 0x4, "Memory") & ~(0x1F << 24)) | (trim_value << 24); + __writeMemory32(reg, dcdc_base + 0x4, "Memory"); + dcdc_trim_loaded = 1; + } + + reg = __readMemory32(ocotp_fuse_bank0_base + 0x80, "Memory"); + if (reg & (1<<30)) + { + index = (reg & (3 << 28)) >> 28; + if (index < 4) + { + // DCDC: REG3->TRG + reg = (__readMemory32(dcdc_base + 0xC, "Memory") & ~(0x1F)) | (0xF + index); + __writeMemory32(reg, dcdc_base + 0xC, "Memory"); + dcdc_trim_loaded = 1; + } + } + + if (dcdc_trim_loaded) + { + // delay 1ms for dcdc to get stable + __delay(1); + __message "DCDC trim value loaded.\n"; + } + +} + +execUserPreload() +{ + _load_dcdc_trim(); +} + +execUserReset() +{ + _load_dcdc_trim(); +} + diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/linker_scripts/link.icf b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/linker_scripts/link.icf new file mode 100644 index 0000000000..973266af05 --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/linker_scripts/link.icf @@ -0,0 +1,94 @@ +/* +** ################################################################### +** Processors: MIMXRT1062CVJ5A +** MIMXRT1062CVL5A +** MIMXRT1062DVJ6A +** MIMXRT1062DVL6A +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1060RM Rev. B, 07/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b180801 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x60002000; +define symbol m_interrupts_end = 0x600023FF; + +define symbol m_text_start = 0x60002400; +define symbol m_text_end = 0x607FFFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2001FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x202BFFFF; + +define exported symbol m_boot_hdr_conf_start = 0x60000000; +define symbol m_boot_hdr_ivt_start = 0x60001000; +define symbol m_boot_hdr_boot_data_start = 0x60001020; +define symbol m_boot_hdr_dcd_data_start = 0x60001030; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; +define exported symbol __RTT_HEAP_END = m_data2_end; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; +place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; +place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; +place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; + +keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; + +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in DATA_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; + diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/linker_scripts/link.lds b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/linker_scripts/link.lds new file mode 100644 index 0000000000..1e11ddc014 --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/linker_scripts/link.lds @@ -0,0 +1,298 @@ +/* +** ################################################################### +** Processors: MIMXRT1052CVJ5B +** MIMXRT1052CVL5B +** MIMXRT1052DVJ6B +** MIMXRT1052DVL6B +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1050RM Rev.1, 03/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b180509 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** The Clear BSD License +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without +** modification, are permitted (subject to the limitations in the +** disclaimer below) provided that the following conditions are met: +** +** * Redistributions of source code must retain the above copyright +** notice, this list of conditions and the following disclaimer. +** +** * Redistributions in binary form must reproduce the above copyright +** notice, this list of conditions and the following disclaimer in the +** documentation and/or other materials provided with the distribution. +** +** * Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from +** this software without specific prior written permission. +** +** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE +** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN +** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_flash_config (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x01FFDC00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x00040000 +} + +/* Define output sections */ +SECTIONS +{ + .flash_config : + { + . = ALIGN(4); + __FLASH_BASE = .; + KEEP(* (.boot_hdr.conf)) /* flash config section */ + . = ALIGN(4); + } > m_flash_config + + ivt_begin = ORIGIN(m_flash_config) + LENGTH(m_flash_config); + + .ivt : AT(ivt_begin) + { + . = ALIGN(4); + KEEP(* (.boot_hdr.ivt)) /* ivt section */ + KEEP(* (.boot_hdr.boot_data)) /* boot section */ + KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ + . = ALIGN(4); + } > m_ivt + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + stack_start = .; + . += STACK_SIZE; + stack_end = .; + __StackTop = .; + } > m_data + + .RTT_HEAP : + { + heap_start = .; + . = ALIGN(8); + } > m_data + + PROVIDE(heap_end = ORIGIN(m_data) + LENGTH(m_data)); + + /* Initializes stack on the end of block */ + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/linker_scripts/link.sct b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/linker_scripts/link.sct new file mode 100644 index 0000000000..ca86cca30b --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/board/linker_scripts/link.sct @@ -0,0 +1,88 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MIMXRT1062CVJ5A +** MIMXRT1062CVL5A +** MIMXRT1062DVJ6A +** MIMXRT1062DVL6A +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1060RM Rev. B, 07/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b180819 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_flash_config_start 0x60000000 +#define m_flash_config_size 0x00001000 + +#define m_ivt_start 0x60001000 +#define m_ivt_size 0x00001000 + +#define m_interrupts_start 0x60002000 +#define m_interrupts_size 0x00000400 + +#define m_text_start 0x60002400 +#define m_text_size 0x003FDC00 + +#define m_data_start 0x20200000 +#define m_data_size 0x00100000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK)) + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region + RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address + * (.boot_hdr.conf, +FIRST) + } + + RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address + * (.boot_hdr.ivt, +FIRST) + * (.boot_hdr.boot_data) + * (.boot_hdr.dcd_data) + } +#else +LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region +#endif + VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + * (NonCacheable.init) + * (NonCacheable) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down + RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{} +} diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/figures/board.png b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/figures/board.png new file mode 100644 index 0000000000000000000000000000000000000000..b28a14b2c37f5af4d8730c5172d9abf7cae4633c GIT binary patch literal 273155 zcmV)KK)Sz)P)j{ z{{Q!V|6fpR4c=;RwV$u{@}a{o?LTyJb^!n^c+~bf$z)=1us@&4t{)q_^X)gkd87T? zFMjPyU;XCjNFTKvu0Z5<0})B3UDs_j+W+VO_HXX_g}dLRuB)}i=l<$%XD-gAQ^~IH zd%i~?K?p;wnr`RgANs|6-}?)1QrADV_LjkVtNpySTD?)oUzXckyll&s1dBB~osQ>L zTOEJ3(kOQUSoqI>{@1_%JHPoRjr#8QeXP+6O9Qz?A}+Y9G+LZT5J3@&3v<)!hWqzF z@z9&p^$mC2^Xkm(+pfIQabiM=PP+p%;ye;jv{J5G44yvl)SJ}xPpy%E=>vGHz199- ztx~COzI@&IhK=!9JWi-aS`lc)6QI~9x9W@M67^Q=&6_g;2}&rbHPBEhp`ic}7`Fgv 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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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1 + board\board.c + + + drv_common.c + 1 + ..\libraries\drivers\drv_common.c + + + drv_gpio.c + 1 + ..\libraries\drivers\drv_gpio.c + + + drv_uart.c + 1 + ..\libraries\drivers\drv_uart.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + components.c + 1 + ..\..\..\src\components.c + + + device.c + 1 + ..\..\..\src\device.c + + + idle.c + 1 + ..\..\..\src\idle.c + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + irq.c + 1 + ..\..\..\src\irq.c + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + memheap.c + 1 + ..\..\..\src\memheap.c + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + object.c + 1 + ..\..\..\src\object.c + + + scheduler_up.c + 1 + ..\..\..\src\scheduler_up.c + + + thread.c + 1 + ..\..\..\src\thread.c + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + Libraries + + + fsl_os_abstraction_rtthread.c + 1 + ..\libraries\MIMXRT1061\MIMXRT1061\drivers\fsl_os_abstraction_rtthread.c + + + fsl_xbara.c + 1 + ..\libraries\MIMXRT1061\MIMXRT1061\drivers\fsl_xbara.c + + + fsl_clock.c + 1 + ..\libraries\MIMXRT1061\MIMXRT1061\drivers\fsl_clock.c + + + fsl_xbarb.c + 1 + ..\libraries\MIMXRT1061\MIMXRT1061\drivers\fsl_xbarb.c + + + system_MIMXRT1061.c + 1 + ..\libraries\MIMXRT1061\MIMXRT1061\system_MIMXRT1061.c + + + fsl_cache.c + 1 + ..\libraries\MIMXRT1061\MIMXRT1061\drivers\fsl_cache.c + + + startup_MIMXRT1061.s + 2 + ..\libraries\MIMXRT1061\MIMXRT1061\arm\startup_MIMXRT1061.s + + + fsl_gpio.c + 1 + ..\libraries\MIMXRT1061\MIMXRT1061\drivers\fsl_gpio.c + + + fsl_lpuart.c + 1 + ..\libraries\MIMXRT1061\MIMXRT1061\drivers\fsl_lpuart.c + + + generic_list.c + 1 + ..\libraries\MIMXRT1061\MIMXRT1061\drivers\generic_list.c + + + fsl_common.c + 1 + ..\libraries\MIMXRT1061\MIMXRT1061\drivers\fsl_common.c + + + + + + + + + + + + + + diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/rtconfig.h b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/rtconfig.h new file mode 100644 index 0000000000..dbd9175da9 --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/rtconfig.h @@ -0,0 +1,247 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_MEMHEAP_AS_HEAP +#define RT_USING_MEMHEAP_AUTO_BINDING +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x50001 +#define RT_USING_CACHE +#define RT_USING_HW_ATOMIC +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_FPU +#define ARCH_ARM_CORTEX_M7 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* DFS: device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* touch drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +#define SOC_IMXRT1060_SERIES + +/* Hardware Drivers Config */ + +#define SOC_IMXRT1061CVL5A + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_LPUART +#define BSP_USING_LPUART1 + +/* Onboard Peripheral Drivers */ + + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/rtconfig.py b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/rtconfig.py new file mode 100644 index 0000000000..60d2a9fc13 --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/rtconfig.py @@ -0,0 +1,162 @@ +import os +import sys + +# toolchains options +ARCH='arm' +CPU='cortex-m7' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT -eentry' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + else: + CFLAGS += ' -O2 -Os' + + POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + '.fp.sp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '\ARM\ARMCC\lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board\linker_scripts\link.sct"' + + CFLAGS += ' --diag_suppress=66,1296,186,6134' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + + POST_ACTION = 'fromelf -z $TARGET' + # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D__FPU_PRESENT' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=' + CPU + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU + AFLAGS += ' --fpu None' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + + \ No newline at end of file diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/template.ewd b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/template.ewd new file mode 100644 index 0000000000..5a43f3b38f --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/template.ewd @@ -0,0 +1,1546 @@ + + + 3 + + rtthread + + ARM + + 1 + + C-SPY + 2 + + 32 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + IJET_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + 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$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/template.ewp b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/template.ewp new file mode 100644 index 0000000000..114ff40205 --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/template.ewp @@ -0,0 +1,1074 @@ + + + 3 + + rtthread + + ARM + + 1 + + General + 3 + + 35 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 37 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 11 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 27 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/template.ewt b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/template.ewt new file mode 100644 index 0000000000..2909739da7 --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/template.ewt @@ -0,0 +1,1426 @@ + + + 3 + + rtthread + + ARM + + 1 + + C-STAT + 516 + + 516 + + 0 + + 1 + 600 + 0 + 2 + 0 + 1 + 100 + rtthread/C-STAT + + + 2.4.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + RuntimeChecking + 0 + + 2 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/template.eww b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/template.uvoptx b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/template.uvoptx new file mode 100644 index 0000000000..f01acb7062 --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/template.uvoptx @@ -0,0 +1,184 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + .\flexspi_nor.ini + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC8000 -FD20000000 -FF0MIMXRT106x_QSPI_4KB_SEC -FL0800000 -FS060000000 -FP0($$Device:MIMXRT1061CVL5A$arm\MIMXRT106x_QSPI_4KB_SEC.FLM) + + + 0 + CMSIS_AGDI + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC8000 -FD20000000 -FF0MIMXRT106x_QSPI_4KB_SEC -FL0800000 -FS060000000 -FP0($$Device:MIMXRT1061CVL5A$arm\MIMXRT106x_QSPI_4KB_SEC.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 10000000 + + + + + diff --git a/bsp/imxrt/imxrt1061-forlinx-OK1061-S/template.uvprojx b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/template.uvprojx new file mode 100644 index 0000000000..18acfcc224 --- /dev/null +++ b/bsp/imxrt/imxrt1061-forlinx-OK1061-S/template.uvprojx @@ -0,0 +1,392 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + MIMXRT1061CVL5A + NXP + NXP.MIMXRT1061_DFP.16.0.0 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20000000,0x020000) IRAM2(0x00000000,0x020000) IROM(0x00200000,0x020000) XRAM(0x20280000,0x040000) XRAM2(0x20200000,0x080000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC8000 -FN1 -FF0MIMXRT106x_QSPI_4KB_SEC -FS060000000 -FL0800000 -FP0($$Device:MIMXRT1061CVL5A$arm\MIMXRT106x_QSPI_4KB_SEC.FLM)) + 0 + $$Device:MIMXRT1061CVL5A$fsl_device_registers.h + + + + + + + + + + $$Device:MIMXRT1061CVL5A$MIMXRT1061.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 0 + 0 + 0 + 1 + 1 + 1 + 0 + 3 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x200000 + 0x20000 + + + 1 + 0x20280000 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x200000 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x20280000 + 0x40000 + + + 1 + 0x20200000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x20000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186 + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + .\board\linker_scripts\link.sct + + + + + 6314 + + + + + + + + + + + + + diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/arm_common_tables.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/arm_common_tables.h new file mode 100644 index 0000000000..dfea7460e9 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/arm_const_structs.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/arm_const_structs.h new file mode 100644 index 0000000000..80a3e8bbe7 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/arm_math.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/arm_math.h new file mode 100644 index 0000000000..62f87bec87 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/arm_math.h @@ -0,0 +1,7160 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP LibraryU + * @version V1.5.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. + * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK version 5.14.0.0 + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. + * + * - ARM_MATH_ARMV8MxL: + * + * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library + * on Armv8-M Mainline target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. + * + * - __DSP_PRESENT: + * + * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2015 Arm Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM33) + #include "core_cm33.h" + #define ARM_MATH_DSP +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MBL) + #include "core_armv8mbl.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_ARMV8MML) + #include "core_armv8mml.h" + #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) + #define ARM_MATH_DSP + #endif +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE __attribute__((always_inline)) + +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) + #define CMSIS_INLINE + +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED + #define CMSIS_INLINE + +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if !defined (ARM_MATH_DSP) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif /* !defined (ARM_MATH_DSP) */ + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA for M3 and M0 processors + */ + CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] S points to an instance of the floating-point FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * The function implements the forward Park transform. + * + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { + +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined(__GNUC__) + *pOut = __builtin_sqrtf(in); +#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#else + #error Unknown compiler +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/cmsis_armcc.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000000..093d35b9e5 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,870 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/cmsis_armclang.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000000..5c4c20e877 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1877 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/cmsis_compiler.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000000..94212eb87a --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/cmsis_gcc.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000000..5d0f07e8ac --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2088 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.3 + * @date 16. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/cmsis_iccarm.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000000..edcaee3d4a --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,913 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.5 + * @date 10. January 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/cmsis_version.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000000..660f612aa3 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_armv8mbl.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000000..47a39893ac --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1896 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_armv8mml.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000000..0951a1f781 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2960 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm0.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000000..a3f1b9ac33 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm0.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm0plus.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000000..f8f30c3496 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1023 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm23.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000000..7d1d478af2 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm23.h @@ -0,0 +1,1899 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm3.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000..a2c0d08057 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm3.h @@ -0,0 +1,1933 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm33.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000000..b1efbcae7c --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm33.h @@ -0,0 +1,2963 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_PCS_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm4.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000000..a11a3817a2 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm4.h @@ -0,0 +1,2118 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm7.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000000..1fe53bf012 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_cm7.h @@ -0,0 +1,2660 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.0.5 + * @date 08. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ + +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + register uint32_t ccsidr; + register uint32_t sets; + register uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */ + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += (uint32_t)linesize; + op_size -= linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_dsp.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_dsp.h new file mode 100644 index 0000000000..6c21a47d80 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_dsp.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file cmsis_xcc.h + * @brief CMSIS DSP Core Peripheral Access Layer Header File + * @version V1.0 + * @date 20. January 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CORE_DSP_H_GENERIC +#define __CORE_DSP_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +#define __STATIC_INLINE static inline + +#define __BKPT(value) do {} while(0) +#define __NOP() do {} while(0) + +#define NVIC_SetPriorityGrouping(value) do {} while(0) +#define NVIC_GetPriorityGrouping() do {} while(0) +#define NVIC_EnableIRQ(value) do {} while(0) +#define NVIC_GetEnableIRQ(value) do {} while(0) +#define NVIC_DisableIRQ(value) do {} while(0) +#define NVIC_GetPendingIRQ(value) do {} while(0) +#define NVIC_SetPendingIRQ(value) do {} while(0) +#define NVIC_ClearPendingIRQ(value) do {} while(0) +#define NVIC_GetActive(value) do {} while(0) + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_DSP_H_GENERIC */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_sc000.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000000..9aab5e5b3e --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_sc000.h @@ -0,0 +1,1016 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_sc300.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000000..a569ef2ace --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/core_sc300.h @@ -0,0 +1,1903 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.3 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1U]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/mpu_armv7.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000000..aa180c9e59 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,197 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) + +#define ARM_MPU_AP_NONE 0U +#define ARM_MPU_AP_PRIV 1U +#define ARM_MPU_AP_URO 2U +#define ARM_MPU_AP_FULL 3U +#define ARM_MPU_AP_PRO 5U +#define ARM_MPU_AP_RO 6U + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (MPU_RASR_ENABLE_Msk)) + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/mpu_armv8.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000000..0ccfc74fe5 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,333 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Pos) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/tz_context.h b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/tz_context.h new file mode 100644 index 0000000000..0d09749f3a --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/imxrt/libraries/MIMXRT1061/CMSIS/LICENSE.txt b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/LICENSE.txt new file mode 100644 index 0000000000..8dada3edaf --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/CMSIS/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright {yyyy} {name of copyright owner} + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/MIMXRT1061.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/MIMXRT1061.h new file mode 100644 index 0000000000..2caac6addb --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/MIMXRT1061.h @@ -0,0 +1,42797 @@ +/* +** ################################################################### +** Processors: MIMXRT1061CVJ5A +** MIMXRT1061CVL5A +** MIMXRT1061DVJ6A +** MIMXRT1061DVL6A +** +** Compilers: Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3 +** Version: rev. 1.2, 2019-04-29 +** Build: b190429 +** +** Abstract: +** CMSIS Peripheral Access Layer for MIMXRT1061 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 0.1 (2017-01-10) +** Initial version. +** - rev. 1.0 (2018-11-16) +** Update header files to align with IMXRT1060RM Rev.0. +** - rev. 1.1 (2018-11-27) +** Update header files to align with IMXRT1060RM Rev.1. +** - rev. 1.2 (2019-04-29) +** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module. +** +** ################################################################### +*/ + +/*! + * @file MIMXRT1061.h + * @version 1.2 + * @date 2019-04-29 + * @brief CMSIS Peripheral Access Layer for MIMXRT1061 + * + * CMSIS Peripheral Access Layer for MIMXRT1061 + */ + +#ifndef _MIMXRT1061_H_ +#define _MIMXRT1061_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0002U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 174 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */ + + /* Device specific interrupts */ + DMA0_DMA16_IRQn = 0, /**< DMA channel 0/16 transfer complete */ + DMA1_DMA17_IRQn = 1, /**< DMA channel 1/17 transfer complete */ + DMA2_DMA18_IRQn = 2, /**< DMA channel 2/18 transfer complete */ + DMA3_DMA19_IRQn = 3, /**< DMA channel 3/19 transfer complete */ + DMA4_DMA20_IRQn = 4, /**< DMA channel 4/20 transfer complete */ + DMA5_DMA21_IRQn = 5, /**< DMA channel 5/21 transfer complete */ + DMA6_DMA22_IRQn = 6, /**< DMA channel 6/22 transfer complete */ + DMA7_DMA23_IRQn = 7, /**< DMA channel 7/23 transfer complete */ + DMA8_DMA24_IRQn = 8, /**< DMA channel 8/24 transfer complete */ + DMA9_DMA25_IRQn = 9, /**< DMA channel 9/25 transfer complete */ + DMA10_DMA26_IRQn = 10, /**< DMA channel 10/26 transfer complete */ + DMA11_DMA27_IRQn = 11, /**< DMA channel 11/27 transfer complete */ + DMA12_DMA28_IRQn = 12, /**< DMA channel 12/28 transfer complete */ + DMA13_DMA29_IRQn = 13, /**< DMA channel 13/29 transfer complete */ + DMA14_DMA30_IRQn = 14, /**< DMA channel 14/30 transfer complete */ + DMA15_DMA31_IRQn = 15, /**< DMA channel 15/31 transfer complete */ + DMA_ERROR_IRQn = 16, /**< DMA error interrupt channels 0-15 / 16-31 */ + CTI0_ERROR_IRQn = 17, /**< CTI0_Error */ + CTI1_ERROR_IRQn = 18, /**< CTI1_Error */ + CORE_IRQn = 19, /**< CorePlatform exception IRQ */ + LPUART1_IRQn = 20, /**< LPUART1 TX interrupt and RX interrupt */ + LPUART2_IRQn = 21, /**< LPUART2 TX interrupt and RX interrupt */ + LPUART3_IRQn = 22, /**< LPUART3 TX interrupt and RX interrupt */ + LPUART4_IRQn = 23, /**< LPUART4 TX interrupt and RX interrupt */ + LPUART5_IRQn = 24, /**< LPUART5 TX interrupt and RX interrupt */ + LPUART6_IRQn = 25, /**< LPUART6 TX interrupt and RX interrupt */ + LPUART7_IRQn = 26, /**< LPUART7 TX interrupt and RX interrupt */ + LPUART8_IRQn = 27, /**< LPUART8 TX interrupt and RX interrupt */ + LPI2C1_IRQn = 28, /**< LPI2C1 interrupt */ + LPI2C2_IRQn = 29, /**< LPI2C2 interrupt */ + LPI2C3_IRQn = 30, /**< LPI2C3 interrupt */ + LPI2C4_IRQn = 31, /**< LPI2C4 interrupt */ + LPSPI1_IRQn = 32, /**< LPSPI1 single interrupt vector for all sources */ + LPSPI2_IRQn = 33, /**< LPSPI2 single interrupt vector for all sources */ + LPSPI3_IRQn = 34, /**< LPSPI3 single interrupt vector for all sources */ + LPSPI4_IRQn = 35, /**< LPSPI4 single interrupt vector for all sources */ + CAN1_IRQn = 36, /**< CAN1 interrupt */ + CAN2_IRQn = 37, /**< CAN2 interrupt */ + FLEXRAM_IRQn = 38, /**< FlexRAM address out of range Or access hit IRQ */ + KPP_IRQn = 39, /**< Keypad nterrupt */ + TSC_DIG_IRQn = 40, /**< TSC interrupt */ + GPR_IRQ_IRQn = 41, /**< GPR interrupt */ + Reserved58_IRQn = 42, /**< Reserved interrupt */ + Reserved59_IRQn = 43, /**< Reserved interrupt */ + Reserved60_IRQn = 44, /**< Reserved interrupt */ + WDOG2_IRQn = 45, /**< WDOG2 interrupt */ + SNVS_HP_WRAPPER_IRQn = 46, /**< SRTC Consolidated Interrupt. Non TZ */ + SNVS_HP_WRAPPER_TZ_IRQn = 47, /**< SRTC Security Interrupt. TZ */ + SNVS_LP_WRAPPER_IRQn = 48, /**< ON-OFF button press shorter than 5 secs (pulse event) */ + CSU_IRQn = 49, /**< CSU interrupt */ + DCP_IRQn = 50, /**< DCP_IRQ interrupt */ + DCP_VMI_IRQn = 51, /**< DCP_VMI_IRQ interrupt */ + Reserved68_IRQn = 52, /**< Reserved interrupt */ + TRNG_IRQn = 53, /**< TRNG interrupt */ + SJC_IRQn = 54, /**< SJC interrupt */ + BEE_IRQn = 55, /**< BEE interrupt */ + SAI1_IRQn = 56, /**< SAI1 interrupt */ + SAI2_IRQn = 57, /**< SAI1 interrupt */ + SAI3_RX_IRQn = 58, /**< SAI3 interrupt */ + SAI3_TX_IRQn = 59, /**< SAI3 interrupt */ + SPDIF_IRQn = 60, /**< SPDIF interrupt */ + PMU_EVENT_IRQn = 61, /**< Brown-out event interrupt */ + Reserved78_IRQn = 62, /**< Reserved interrupt */ + TEMP_LOW_HIGH_IRQn = 63, /**< TempSensor low/high interrupt */ + TEMP_PANIC_IRQn = 64, /**< TempSensor panic interrupt */ + USB_PHY1_IRQn = 65, /**< USBPHY (UTMI0), Interrupt */ + USB_PHY2_IRQn = 66, /**< USBPHY (UTMI1), Interrupt */ + ADC1_IRQn = 67, /**< ADC1 interrupt */ + ADC2_IRQn = 68, /**< ADC2 interrupt */ + DCDC_IRQn = 69, /**< DCDC interrupt */ + Reserved86_IRQn = 70, /**< Reserved interrupt */ + Reserved87_IRQn = 71, /**< Reserved interrupt */ + GPIO1_INT0_IRQn = 72, /**< Active HIGH Interrupt from INT0 from GPIO */ + GPIO1_INT1_IRQn = 73, /**< Active HIGH Interrupt from INT1 from GPIO */ + GPIO1_INT2_IRQn = 74, /**< Active HIGH Interrupt from INT2 from GPIO */ + GPIO1_INT3_IRQn = 75, /**< Active HIGH Interrupt from INT3 from GPIO */ + GPIO1_INT4_IRQn = 76, /**< Active HIGH Interrupt from INT4 from GPIO */ + GPIO1_INT5_IRQn = 77, /**< Active HIGH Interrupt from INT5 from GPIO */ + GPIO1_INT6_IRQn = 78, /**< Active HIGH Interrupt from INT6 from GPIO */ + GPIO1_INT7_IRQn = 79, /**< Active HIGH Interrupt from INT7 from GPIO */ + GPIO1_Combined_0_15_IRQn = 80, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */ + GPIO1_Combined_16_31_IRQn = 81, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */ + GPIO2_Combined_0_15_IRQn = 82, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */ + GPIO2_Combined_16_31_IRQn = 83, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */ + GPIO3_Combined_0_15_IRQn = 84, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */ + GPIO3_Combined_16_31_IRQn = 85, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */ + GPIO4_Combined_0_15_IRQn = 86, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */ + GPIO4_Combined_16_31_IRQn = 87, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */ + GPIO5_Combined_0_15_IRQn = 88, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */ + GPIO5_Combined_16_31_IRQn = 89, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */ + FLEXIO1_IRQn = 90, /**< FLEXIO1 interrupt */ + FLEXIO2_IRQn = 91, /**< FLEXIO2 interrupt */ + WDOG1_IRQn = 92, /**< WDOG1 interrupt */ + RTWDOG_IRQn = 93, /**< RTWDOG interrupt */ + EWM_IRQn = 94, /**< EWM interrupt */ + CCM_1_IRQn = 95, /**< CCM IRQ1 interrupt */ + CCM_2_IRQn = 96, /**< CCM IRQ2 interrupt */ + GPC_IRQn = 97, /**< GPC interrupt */ + SRC_IRQn = 98, /**< SRC interrupt */ + Reserved115_IRQn = 99, /**< Reserved interrupt */ + GPT1_IRQn = 100, /**< GPT1 interrupt */ + GPT2_IRQn = 101, /**< GPT2 interrupt */ + PWM1_0_IRQn = 102, /**< PWM1 capture 0, compare 0, or reload 0 interrupt */ + PWM1_1_IRQn = 103, /**< PWM1 capture 1, compare 1, or reload 0 interrupt */ + PWM1_2_IRQn = 104, /**< PWM1 capture 2, compare 2, or reload 0 interrupt */ + PWM1_3_IRQn = 105, /**< PWM1 capture 3, compare 3, or reload 0 interrupt */ + PWM1_FAULT_IRQn = 106, /**< PWM1 fault or reload error interrupt */ + FLEXSPI2_IRQn = 107, /**< FlexSPI2 interrupt */ + FLEXSPI_IRQn = 108, /**< FlexSPI0 interrupt */ + SEMC_IRQn = 109, /**< Reserved interrupt */ + USDHC1_IRQn = 110, /**< USDHC1 interrupt */ + USDHC2_IRQn = 111, /**< USDHC2 interrupt */ + USB_OTG2_IRQn = 112, /**< USBO2 USB OTG2 */ + USB_OTG1_IRQn = 113, /**< USBO2 USB OTG1 */ + ENET_IRQn = 114, /**< ENET interrupt */ + ENET_1588_Timer_IRQn = 115, /**< ENET_1588_Timer interrupt */ + XBAR1_IRQ_0_1_IRQn = 116, /**< XBAR1 interrupt */ + XBAR1_IRQ_2_3_IRQn = 117, /**< XBAR1 interrupt */ + ADC_ETC_IRQ0_IRQn = 118, /**< ADCETC IRQ0 interrupt */ + ADC_ETC_IRQ1_IRQn = 119, /**< ADCETC IRQ1 interrupt */ + ADC_ETC_IRQ2_IRQn = 120, /**< ADCETC IRQ2 interrupt */ + ADC_ETC_ERROR_IRQ_IRQn = 121, /**< ADCETC Error IRQ interrupt */ + PIT_IRQn = 122, /**< PIT interrupt */ + ACMP1_IRQn = 123, /**< ACMP interrupt */ + ACMP2_IRQn = 124, /**< ACMP interrupt */ + ACMP3_IRQn = 125, /**< ACMP interrupt */ + ACMP4_IRQn = 126, /**< ACMP interrupt */ + Reserved143_IRQn = 127, /**< Reserved interrupt */ + Reserved144_IRQn = 128, /**< Reserved interrupt */ + ENC1_IRQn = 129, /**< ENC1 interrupt */ + ENC2_IRQn = 130, /**< ENC2 interrupt */ + ENC3_IRQn = 131, /**< ENC3 interrupt */ + ENC4_IRQn = 132, /**< ENC4 interrupt */ + TMR1_IRQn = 133, /**< TMR1 interrupt */ + TMR2_IRQn = 134, /**< TMR2 interrupt */ + TMR3_IRQn = 135, /**< TMR3 interrupt */ + TMR4_IRQn = 136, /**< TMR4 interrupt */ + PWM2_0_IRQn = 137, /**< PWM2 capture 0, compare 0, or reload 0 interrupt */ + PWM2_1_IRQn = 138, /**< PWM2 capture 1, compare 1, or reload 0 interrupt */ + PWM2_2_IRQn = 139, /**< PWM2 capture 2, compare 2, or reload 0 interrupt */ + PWM2_3_IRQn = 140, /**< PWM2 capture 3, compare 3, or reload 0 interrupt */ + PWM2_FAULT_IRQn = 141, /**< PWM2 fault or reload error interrupt */ + PWM3_0_IRQn = 142, /**< PWM3 capture 0, compare 0, or reload 0 interrupt */ + PWM3_1_IRQn = 143, /**< PWM3 capture 1, compare 1, or reload 0 interrupt */ + PWM3_2_IRQn = 144, /**< PWM3 capture 2, compare 2, or reload 0 interrupt */ + PWM3_3_IRQn = 145, /**< PWM3 capture 3, compare 3, or reload 0 interrupt */ + PWM3_FAULT_IRQn = 146, /**< PWM3 fault or reload error interrupt */ + PWM4_0_IRQn = 147, /**< PWM4 capture 0, compare 0, or reload 0 interrupt */ + PWM4_1_IRQn = 148, /**< PWM4 capture 1, compare 1, or reload 0 interrupt */ + PWM4_2_IRQn = 149, /**< PWM4 capture 2, compare 2, or reload 0 interrupt */ + PWM4_3_IRQn = 150, /**< PWM4 capture 3, compare 3, or reload 0 interrupt */ + PWM4_FAULT_IRQn = 151, /**< PWM4 fault or reload error interrupt */ + ENET2_IRQn = 152, /**< ENET2 interrupt */ + ENET2_1588_Timer_IRQn = 153, /**< ENET2_1588_Timer interrupt */ + CAN3_IRQn = 154, /**< CAN3 interrupt */ + Reserved171_IRQn = 155, /**< Reserved interrupt */ + FLEXIO3_IRQn = 156, /**< FLEXIO3 interrupt */ + GPIO6_7_8_9_IRQn = 157 /**< GPIO6, GPIO7, GPIO8, GPIO9 interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M7 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */ +#define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */ +#define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ + +#include "core_cm7.h" /* Core Peripheral Access Layer */ +#include "system_MIMXRT1061.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup edma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 Request0 and Request1 */ + kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 Request0 and Request1 */ + kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */ + kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */ + kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */ + kDmaRequestMuxLPUART3Rx = 5|0x100U, /**< LPUART3 Receive */ + kDmaRequestMuxLPUART5Tx = 6|0x100U, /**< LPUART5 Transmit */ + kDmaRequestMuxLPUART5Rx = 7|0x100U, /**< LPUART5 Receive */ + kDmaRequestMuxLPUART7Tx = 8|0x100U, /**< LPUART7 Transmit */ + kDmaRequestMuxLPUART7Rx = 9|0x100U, /**< LPUART7 Receive */ + kDmaRequestMuxCAN3 = 11|0x100U, /**< CAN3 */ + kDmaRequestMuxLPSPI1Rx = 13|0x100U, /**< LPSPI1 Receive */ + kDmaRequestMuxLPSPI1Tx = 14|0x100U, /**< LPSPI1 Transmit */ + kDmaRequestMuxLPSPI3Rx = 15|0x100U, /**< LPSPI3 Receive */ + kDmaRequestMuxLPSPI3Tx = 16|0x100U, /**< LPSPI3 Transmit */ + kDmaRequestMuxLPI2C1 = 17|0x100U, /**< LPI2C1 */ + kDmaRequestMuxLPI2C3 = 18|0x100U, /**< LPI2C3 */ + kDmaRequestMuxSai1Rx = 19|0x100U, /**< SAI1 Receive */ + kDmaRequestMuxSai1Tx = 20|0x100U, /**< SAI1 Transmit */ + kDmaRequestMuxSai2Rx = 21|0x100U, /**< SAI2 Receive */ + kDmaRequestMuxSai2Tx = 22|0x100U, /**< SAI2 Transmit */ + kDmaRequestMuxADC_ETC = 23|0x100U, /**< ADC_ETC */ + kDmaRequestMuxADC1 = 24|0x100U, /**< ADC1 */ + kDmaRequestMuxACMP1 = 25|0x100U, /**< ACMP1 */ + kDmaRequestMuxACMP3 = 26|0x100U, /**< ACMP3 */ + kDmaRequestMuxFlexSPIRx = 28|0x100U, /**< FlexSPI Receive */ + kDmaRequestMuxFlexSPITx = 29|0x100U, /**< FlexSPI Transmit */ + kDmaRequestMuxXBAR1Request0 = 30|0x100U, /**< XBAR1 Request 0 */ + kDmaRequestMuxXBAR1Request1 = 31|0x100U, /**< XBAR1 Request 1 */ + kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U, /**< FlexPWM1 Capture sub-module0 */ + kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U, /**< FlexPWM1 Capture sub-module1 */ + kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U, /**< FlexPWM1 Capture sub-module2 */ + kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U, /**< FlexPWM1 Capture sub-module3 */ + kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U, /**< FlexPWM1 Value sub-module0 */ + kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U, /**< FlexPWM1 Value sub-module1 */ + kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U, /**< FlexPWM1 Value sub-module2 */ + kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U, /**< FlexPWM1 Value sub-module3 */ + kDmaRequestMuxFlexPWM3CaptureSub0 = 40|0x100U, /**< FlexPWM3 Capture sub-module0 */ + kDmaRequestMuxFlexPWM3CaptureSub1 = 41|0x100U, /**< FlexPWM3 Capture sub-module1 */ + kDmaRequestMuxFlexPWM3CaptureSub2 = 42|0x100U, /**< FlexPWM3 Capture sub-module2 */ + kDmaRequestMuxFlexPWM3CaptureSub3 = 43|0x100U, /**< FlexPWM3 Capture sub-module3 */ + kDmaRequestMuxFlexPWM3ValueSub0 = 44|0x100U, /**< FlexPWM3 Value sub-module0 */ + kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U, /**< FlexPWM3 Value sub-module1 */ + kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U, /**< FlexPWM3 Value sub-module2 */ + kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U, /**< FlexPWM3 Value sub-module3 */ + kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, /**< TMR1 Capture timer 0 */ + kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U, /**< TMR1 Capture timer 1 */ + kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, /**< TMR1 Capture timer 2 */ + kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, /**< TMR1 Capture timer 3 */ + kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< TMR1 cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< TMR1 cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< TMR1 cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< TMR1 cmpld1 in timer 3 or cmpld2 in timer 2 */ + kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, /**< TMR3 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 57|0x100U, /**< TMR3 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 58|0x100U, /**< TMR3 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U, /**< TMR3 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */ + kDmaRequestMuxFlexSPI2Rx = 60|0x100U, /**< FlexSPI2 Receive */ + kDmaRequestMuxFlexSPI2Tx = 61|0x100U, /**< FlexSPI2 Transmit */ + kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 Request2 and Request3 */ + kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 Request2 and Request3 */ + kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */ + kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */ + kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */ + kDmaRequestMuxLPUART4Rx = 69|0x100U, /**< LPUART4 Receive */ + kDmaRequestMuxLPUART6Tx = 70|0x100U, /**< LPUART6 Transmit */ + kDmaRequestMuxLPUART6Rx = 71|0x100U, /**< LPUART6 Receive */ + kDmaRequestMuxLPUART8Tx = 72|0x100U, /**< LPUART8 Transmit */ + kDmaRequestMuxLPUART8Rx = 73|0x100U, /**< LPUART8 Receive */ + kDmaRequestMuxLPSPI2Rx = 77|0x100U, /**< LPSPI2 Receive */ + kDmaRequestMuxLPSPI2Tx = 78|0x100U, /**< LPSPI2 Transmit */ + kDmaRequestMuxLPSPI4Rx = 79|0x100U, /**< LPSPI4 Receive */ + kDmaRequestMuxLPSPI4Tx = 80|0x100U, /**< LPSPI4 Transmit */ + kDmaRequestMuxLPI2C2 = 81|0x100U, /**< LPI2C2 */ + kDmaRequestMuxLPI2C4 = 82|0x100U, /**< LPI2C4 */ + kDmaRequestMuxSai3Rx = 83|0x100U, /**< SAI3 Receive */ + kDmaRequestMuxSai3Tx = 84|0x100U, /**< SAI3 Transmit */ + kDmaRequestMuxSpdifRx = 85|0x100U, /**< SPDIF Receive */ + kDmaRequestMuxSpdifTx = 86|0x100U, /**< SPDIF Transmit */ + kDmaRequestMuxADC2 = 88|0x100U, /**< ADC2 */ + kDmaRequestMuxACMP2 = 89|0x100U, /**< ACMP2 */ + kDmaRequestMuxACMP4 = 90|0x100U, /**< ACMP4 */ + kDmaRequestMuxEnetTimer0 = 92|0x100U, /**< ENET Timer0 */ + kDmaRequestMuxEnetTimer1 = 93|0x100U, /**< ENET Timer1 */ + kDmaRequestMuxXBAR1Request2 = 94|0x100U, /**< XBAR1 Request 2 */ + kDmaRequestMuxXBAR1Request3 = 95|0x100U, /**< XBAR1 Request 3 */ + kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U, /**< FlexPWM2 Capture sub-module0 */ + kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U, /**< FlexPWM2 Capture sub-module1 */ + kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U, /**< FlexPWM2 Capture sub-module2 */ + kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U, /**< FlexPWM2 Capture sub-module3 */ + kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U, /**< FlexPWM2 Value sub-module0 */ + kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U, /**< FlexPWM2 Value sub-module1 */ + kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U, /**< FlexPWM2 Value sub-module2 */ + kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U, /**< FlexPWM2 Value sub-module3 */ + kDmaRequestMuxFlexPWM4CaptureSub0 = 104|0x100U, /**< FlexPWM4 Capture sub-module0 */ + kDmaRequestMuxFlexPWM4CaptureSub1 = 105|0x100U, /**< FlexPWM4 Capture sub-module1 */ + kDmaRequestMuxFlexPWM4CaptureSub2 = 106|0x100U, /**< FlexPWM4 Capture sub-module2 */ + kDmaRequestMuxFlexPWM4CaptureSub3 = 107|0x100U, /**< FlexPWM4 Capture sub-module3 */ + kDmaRequestMuxFlexPWM4ValueSub0 = 108|0x100U, /**< FlexPWM4 Value sub-module0 */ + kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U, /**< FlexPWM4 Value sub-module1 */ + kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U, /**< FlexPWM4 Value sub-module2 */ + kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U, /**< FlexPWM4 Value sub-module3 */ + kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U, /**< TMR2 Capture timer 0 */ + kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U, /**< TMR2 Capture timer 1 */ + kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U, /**< TMR2 Capture timer 2 */ + kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U, /**< TMR2 Capture timer 3 */ + kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< TMR2 cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< TMR2 cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< TMR2 cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< TMR2 cmpld1 in timer 3 or cmpld2 in timer 2 */ + kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, /**< TMR4 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */ + kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 121|0x100U, /**< TMR4 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */ + kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 122|0x100U, /**< TMR4 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */ + kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 123|0x100U, /**< TMR4 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */ + kDmaRequestMuxEnet2Timer0 = 124|0x100U, /**< ENET2 Timer0 */ + kDmaRequestMuxEnet2Timer1 = 125|0x100U, /**< ENET2 Timer1 */ +} dma_request_source_t; + +/* @} */ + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_mux_ctl_pad +{ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */ +} iomuxc_sw_mux_ctl_pad_t; + +/* @} */ + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD_1 + * + * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD_1 collections. + */ +typedef enum _iomuxc_sw_mux_ctl_pad_1 +{ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_00 = 14U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_01 = 15U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_02 = 16U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_03 = 17U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_04 = 18U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_05 = 19U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_06 = 20U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ + kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_07 = 21U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */ +} iomuxc_sw_mux_ctl_pad_1_t; + +/* @} */ + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD + * + * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections. + */ +typedef enum _iomuxc_sw_pad_ctl_pad +{ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */ +} iomuxc_sw_pad_ctl_pad_t; + +/* @} */ + +/*! + * @addtogroup iomuxc_pads + * @{ */ + +/******************************************************************************* + * Definitions +*******************************************************************************/ + +/*! + * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD_1 + * + * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD_1 collections. + */ +typedef enum _iomuxc_sw_pad_ctl_pad_1 +{ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_00 = 14U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_01 = 15U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_02 = 16U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_03 = 17U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_04 = 18U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_05 = 19U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_06 = 20U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ + kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_07 = 21U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */ +} iomuxc_sw_pad_ctl_pad_1_t; + +/* @} */ + +/*! + * @brief Enumeration for the IOMUXC select input + * + * Defines the enumeration for the IOMUXC select input collections. + */ +typedef enum _iomuxc_select_input +{ + kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */ + kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U, /**< IOMUXC select input index */ + kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U, /**< IOMUXC select input index */ + kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U, /**< IOMUXC select input index */ + kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U, /**< IOMUXC select input index */ + kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U, /**< IOMUXC select input index */ + kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U, /**< IOMUXC select input index */ + kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U, /**< IOMUXC select input index */ + kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U, /**< IOMUXC select input index */ + kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U, /**< IOMUXC select input index */ + kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U, /**< IOMUXC select input index */ + kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U, /**< IOMUXC select input index */ + kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U, /**< IOMUXC select input index */ + kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U, /**< IOMUXC select input index */ + kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U, /**< IOMUXC select input index */ + kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U, /**< IOMUXC select input index */ + kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U, /**< IOMUXC select input index */ + kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT = 44U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT = 45U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT = 46U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT = 47U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT = 48U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT = 49U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT = 50U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT = 51U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT = 52U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT = 53U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U, /**< IOMUXC select input index */ + kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U, /**< IOMUXC select input index */ + kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U, /**< IOMUXC select input index */ + kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U, /**< IOMUXC select input index */ + kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U, /**< IOMUXC select input index */ + kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U, /**< IOMUXC select input index */ + kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U, /**< IOMUXC select input index */ + kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U, /**< IOMUXC select input index */ + kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U, /**< IOMUXC select input index */ + kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U, /**< IOMUXC select input index */ + kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U, /**< IOMUXC select input index */ + kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U, /**< IOMUXC select input index */ + kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U, /**< IOMUXC select input index */ + kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U, /**< IOMUXC select input index */ + kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U, /**< IOMUXC select input index */ + kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U, /**< IOMUXC select input index */ + kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U, /**< IOMUXC select input index */ + kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U, /**< IOMUXC select input index */ + kIOMUXC_NMI_SELECT_INPUT = 93U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U, /**< IOMUXC select input index */ + kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U, /**< IOMUXC select input index */ + kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U, /**< IOMUXC select input index */ + kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U, /**< IOMUXC select input index */ + kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U, /**< IOMUXC select input index */ + kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U, /**< IOMUXC select input index */ + kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U, /**< IOMUXC select input index */ + kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U, /**< IOMUXC select input index */ + kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN02_SELECT_INPUT = 134U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN03_SELECT_INPUT = 135U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN04_SELECT_INPUT = 136U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN05_SELECT_INPUT = 137U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN06_SELECT_INPUT = 138U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN07_SELECT_INPUT = 139U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN08_SELECT_INPUT = 140U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN09_SELECT_INPUT = 141U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN17_SELECT_INPUT = 142U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN18_SELECT_INPUT = 143U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN20_SELECT_INPUT = 144U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN22_SELECT_INPUT = 145U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN23_SELECT_INPUT = 146U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN24_SELECT_INPUT = 147U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN14_SELECT_INPUT = 148U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN15_SELECT_INPUT = 149U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN16_SELECT_INPUT = 150U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN25_SELECT_INPUT = 151U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN19_SELECT_INPUT = 152U, /**< IOMUXC select input index */ + kIOMUXC_XBAR1_IN21_SELECT_INPUT = 153U, /**< IOMUXC select input index */ +} iomuxc_select_input_t; + +/*! + * @brief Enumeration for the IOMUXC select input + * + * Defines the enumeration for the IOMUXC select input collections. + */ +typedef enum _iomuxc_select_input_1 +{ + kIOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT = 0U, /**< IOMUXC select input index */ + kIOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT = 1U, /**< IOMUXC select input index */ + kIOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_0 = 2U, /**< IOMUXC select input index */ + kIOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_1 = 3U, /**< IOMUXC select input index */ + kIOMUXC_ENET2_IPP_IND_MAC0_RXEN_SELECT_INPUT = 4U, /**< IOMUXC select input index */ + kIOMUXC_ENET2_IPP_IND_MAC0_RXERR_SELECT_INPUT = 5U, /**< IOMUXC select input index */ + kIOMUXC_ENET2_IPP_IND_MAC0_TIMER_SELECT_INPUT_0 = 6U, /**< IOMUXC select input index */ + kIOMUXC_ENET2_IPP_IND_MAC0_TXCLK_SELECT_INPUT = 7U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT = 8U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT = 9U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT = 10U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT = 11U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT = 12U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT0_SELECT_INPUT = 13U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT1_SELECT_INPUT = 14U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT2_SELECT_INPUT = 15U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT3_SELECT_INPUT = 16U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT = 17U, /**< IOMUXC select input index */ + kIOMUXC_FLEXSPI2_IPP_IND_SCK_FB_SELECT_INPUT = 18U, /**< IOMUXC select input index */ + kIOMUXC_GPT1_IPP_IND_CAPIN1_SELECT_INPUT = 19U, /**< IOMUXC select input index */ + kIOMUXC_GPT1_IPP_IND_CAPIN2_SELECT_INPUT = 20U, /**< IOMUXC select input index */ + kIOMUXC_GPT1_IPP_IND_CLKIN_SELECT_INPUT = 21U, /**< IOMUXC select input index */ + kIOMUXC_GPT2_IPP_IND_CAPIN1_SELECT_INPUT = 22U, /**< IOMUXC select input index */ + kIOMUXC_GPT2_IPP_IND_CAPIN2_SELECT_INPUT = 23U, /**< IOMUXC select input index */ + kIOMUXC_GPT2_IPP_IND_CLKIN_SELECT_INPUT = 24U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 = 25U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 26U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 27U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 28U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 29U, /**< IOMUXC select input index */ + kIOMUXC_SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 30U, /**< IOMUXC select input index */ + kIOMUXC_SEMC_I_IPP_IND_DQS4_SELECT_INPUT = 31U, /**< IOMUXC select input index */ + kIOMUXC_CANFD_IPP_IND_CANRX_SELECT_INPUT = 32U, /**< IOMUXC select input index */ +} iomuxc_select_input_1_t; + +typedef enum _xbar_input_signal +{ + kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */ + kXBARA1_InputLogicHigh = 1|0x100U, /**< LOGIC_HIGH output assigned to XBARA1_IN1 input. */ + kXBARA1_InputIomuxXbarIn02 = 2|0x100U, /**< IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */ + kXBARA1_InputIomuxXbarIn03 = 3|0x100U, /**< IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */ + kXBARA1_InputIomuxXbarInout04 = 4|0x100U, /**< IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */ + kXBARA1_InputIomuxXbarInout05 = 5|0x100U, /**< IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */ + kXBARA1_InputIomuxXbarInout06 = 6|0x100U, /**< IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */ + kXBARA1_InputIomuxXbarInout07 = 7|0x100U, /**< IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */ + kXBARA1_InputIomuxXbarInout08 = 8|0x100U, /**< IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */ + kXBARA1_InputIomuxXbarInout09 = 9|0x100U, /**< IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */ + kXBARA1_InputIomuxXbarInout10 = 10|0x100U, /**< IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */ + kXBARA1_InputIomuxXbarInout11 = 11|0x100U, /**< IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */ + kXBARA1_InputIomuxXbarInout12 = 12|0x100U, /**< IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */ + kXBARA1_InputIomuxXbarInout13 = 13|0x100U, /**< IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */ + kXBARA1_InputIomuxXbarInout14 = 14|0x100U, /**< IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */ + kXBARA1_InputIomuxXbarInout15 = 15|0x100U, /**< IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */ + kXBARA1_InputIomuxXbarInout16 = 16|0x100U, /**< IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */ + kXBARA1_InputIomuxXbarInout17 = 17|0x100U, /**< IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */ + kXBARA1_InputIomuxXbarInout18 = 18|0x100U, /**< IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */ + kXBARA1_InputIomuxXbarInout19 = 19|0x100U, /**< IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */ + kXBARA1_InputIomuxXbarIn20 = 20|0x100U, /**< IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */ + kXBARA1_InputIomuxXbarIn21 = 21|0x100U, /**< IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */ + kXBARA1_InputIomuxXbarIn22 = 22|0x100U, /**< IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */ + kXBARA1_InputIomuxXbarIn23 = 23|0x100U, /**< IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */ + kXBARA1_InputIomuxXbarIn24 = 24|0x100U, /**< IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */ + kXBARA1_InputIomuxXbarIn25 = 25|0x100U, /**< IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */ + kXBARA1_InputAcmp1Out = 26|0x100U, /**< ACMP1_OUT output assigned to XBARA1_IN26 input. */ + kXBARA1_InputAcmp2Out = 27|0x100U, /**< ACMP2_OUT output assigned to XBARA1_IN27 input. */ + kXBARA1_InputAcmp3Out = 28|0x100U, /**< ACMP3_OUT output assigned to XBARA1_IN28 input. */ + kXBARA1_InputAcmp4Out = 29|0x100U, /**< ACMP4_OUT output assigned to XBARA1_IN29 input. */ + kXBARA1_InputRESERVED30 = 30|0x100U, /**< XBARA1_IN30 input is reserved. */ + kXBARA1_InputRESERVED31 = 31|0x100U, /**< XBARA1_IN31 input is reserved. */ + kXBARA1_InputQtimer3Tmr0Output = 32|0x100U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */ + kXBARA1_InputQtimer3Tmr1Output = 33|0x100U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */ + kXBARA1_InputQtimer3Tmr2Output = 34|0x100U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */ + kXBARA1_InputQtimer3Tmr3Output = 35|0x100U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */ + kXBARA1_InputQtimer4Tmr0Output = 36|0x100U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */ + kXBARA1_InputQtimer4Tmr1Output = 37|0x100U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */ + kXBARA1_InputQtimer4Tmr2Output = 38|0x100U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */ + kXBARA1_InputQtimer4Tmr3Output = 39|0x100U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */ + kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */ + kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */ + kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */ + kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */ + kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */ + kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */ + kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */ + kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */ + kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 48|0x100U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */ + kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 49|0x100U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */ + kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 50|0x100U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */ + kXBARA1_InputFlexpwm3Pwm4OutTrig01 = 51|0x100U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */ + kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 52|0x100U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */ + kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 53|0x100U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */ + kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 54|0x100U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */ + kXBARA1_InputFlexpwm4Pwm4OutTrig01 = 55|0x100U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */ + kXBARA1_InputPitTrigger0 = 56|0x100U, /**< PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */ + kXBARA1_InputPitTrigger1 = 57|0x100U, /**< PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */ + kXBARA1_InputPitTrigger2 = 58|0x100U, /**< PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */ + kXBARA1_InputPitTrigger3 = 59|0x100U, /**< PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */ + kXBARA1_InputEnc1PosMatch = 60|0x100U, /**< ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */ + kXBARA1_InputEnc2PosMatch = 61|0x100U, /**< ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */ + kXBARA1_InputEnc3PosMatch = 62|0x100U, /**< ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */ + kXBARA1_InputEnc4PosMatch = 63|0x100U, /**< ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */ + kXBARA1_InputDmaDone0 = 64|0x100U, /**< DMA_DONE0 output assigned to XBARA1_IN64 input. */ + kXBARA1_InputDmaDone1 = 65|0x100U, /**< DMA_DONE1 output assigned to XBARA1_IN65 input. */ + kXBARA1_InputDmaDone2 = 66|0x100U, /**< DMA_DONE2 output assigned to XBARA1_IN66 input. */ + kXBARA1_InputDmaDone3 = 67|0x100U, /**< DMA_DONE3 output assigned to XBARA1_IN67 input. */ + kXBARA1_InputDmaDone4 = 68|0x100U, /**< DMA_DONE4 output assigned to XBARA1_IN68 input. */ + kXBARA1_InputDmaDone5 = 69|0x100U, /**< DMA_DONE5 output assigned to XBARA1_IN69 input. */ + kXBARA1_InputDmaDone6 = 70|0x100U, /**< DMA_DONE6 output assigned to XBARA1_IN70 input. */ + kXBARA1_InputDmaDone7 = 71|0x100U, /**< DMA_DONE7 output assigned to XBARA1_IN71 input. */ + kXBARA1_InputAoi1Out0 = 72|0x100U, /**< AOI1_OUT0 output assigned to XBARA1_IN72 input. */ + kXBARA1_InputAoi1Out1 = 73|0x100U, /**< AOI1_OUT1 output assigned to XBARA1_IN73 input. */ + kXBARA1_InputAoi1Out2 = 74|0x100U, /**< AOI1_OUT2 output assigned to XBARA1_IN74 input. */ + kXBARA1_InputAoi1Out3 = 75|0x100U, /**< AOI1_OUT3 output assigned to XBARA1_IN75 input. */ + kXBARA1_InputAoi2Out0 = 76|0x100U, /**< AOI2_OUT0 output assigned to XBARA1_IN76 input. */ + kXBARA1_InputAoi2Out1 = 77|0x100U, /**< AOI2_OUT1 output assigned to XBARA1_IN77 input. */ + kXBARA1_InputAoi2Out2 = 78|0x100U, /**< AOI2_OUT2 output assigned to XBARA1_IN78 input. */ + kXBARA1_InputAoi2Out3 = 79|0x100U, /**< AOI2_OUT3 output assigned to XBARA1_IN79 input. */ + kXBARA1_InputAdcEtcXbar0Coco0 = 80|0x100U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */ + kXBARA1_InputAdcEtcXbar0Coco1 = 81|0x100U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */ + kXBARA1_InputAdcEtcXbar0Coco2 = 82|0x100U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */ + kXBARA1_InputAdcEtcXbar0Coco3 = 83|0x100U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */ + kXBARA1_InputAdcEtcXbar1Coco0 = 84|0x100U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */ + kXBARA1_InputAdcEtcXbar1Coco1 = 85|0x100U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */ + kXBARA1_InputAdcEtcXbar1Coco2 = 86|0x100U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */ + kXBARA1_InputAdcEtcXbar1Coco3 = 87|0x100U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */ + kXBARB2_InputLogicLow = 0|0x200U, /**< LOGIC_LOW output assigned to XBARB2_IN0 input. */ + kXBARB2_InputLogicHigh = 1|0x200U, /**< LOGIC_HIGH output assigned to XBARB2_IN1 input. */ + kXBARB2_InputRESERVED2 = 2|0x200U, /**< XBARB2_IN2 input is reserved. */ + kXBARB2_InputRESERVED3 = 3|0x200U, /**< XBARB2_IN3 input is reserved. */ + kXBARB2_InputRESERVED4 = 4|0x200U, /**< XBARB2_IN4 input is reserved. */ + kXBARB2_InputRESERVED5 = 5|0x200U, /**< XBARB2_IN5 input is reserved. */ + kXBARB2_InputAcmp1Out = 6|0x200U, /**< ACMP1_OUT output assigned to XBARB2_IN6 input. */ + kXBARB2_InputAcmp2Out = 7|0x200U, /**< ACMP2_OUT output assigned to XBARB2_IN7 input. */ + kXBARB2_InputAcmp3Out = 8|0x200U, /**< ACMP3_OUT output assigned to XBARB2_IN8 input. */ + kXBARB2_InputAcmp4Out = 9|0x200U, /**< ACMP4_OUT output assigned to XBARB2_IN9 input. */ + kXBARB2_InputRESERVED10 = 10|0x200U, /**< XBARB2_IN10 input is reserved. */ + kXBARB2_InputRESERVED11 = 11|0x200U, /**< XBARB2_IN11 input is reserved. */ + kXBARB2_InputQtimer3Tmr0Output = 12|0x200U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */ + kXBARB2_InputQtimer3Tmr1Output = 13|0x200U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */ + kXBARB2_InputQtimer3Tmr2Output = 14|0x200U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */ + kXBARB2_InputQtimer3Tmr3Output = 15|0x200U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */ + kXBARB2_InputQtimer4Tmr0Output = 16|0x200U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */ + kXBARB2_InputQtimer4Tmr1Output = 17|0x200U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */ + kXBARB2_InputQtimer4Tmr2Output = 18|0x200U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */ + kXBARB2_InputQtimer4Tmr3Output = 19|0x200U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */ + kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */ + kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */ + kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */ + kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */ + kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */ + kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */ + kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */ + kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */ + kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 28|0x200U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */ + kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 29|0x200U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */ + kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 30|0x200U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */ + kXBARB2_InputFlexpwm3Pwm4OutTrig01 = 31|0x200U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */ + kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 32|0x200U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */ + kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 33|0x200U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */ + kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 34|0x200U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */ + kXBARB2_InputFlexpwm4Pwm4OutTrig01 = 35|0x200U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */ + kXBARB2_InputPitTrigger0 = 36|0x200U, /**< PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */ + kXBARB2_InputPitTrigger1 = 37|0x200U, /**< PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */ + kXBARB2_InputAdcEtcXbar0Coco0 = 38|0x200U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */ + kXBARB2_InputAdcEtcXbar0Coco1 = 39|0x200U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */ + kXBARB2_InputAdcEtcXbar0Coco2 = 40|0x200U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */ + kXBARB2_InputAdcEtcXbar0Coco3 = 41|0x200U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */ + kXBARB2_InputAdcEtcXbar1Coco0 = 42|0x200U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */ + kXBARB2_InputAdcEtcXbar1Coco1 = 43|0x200U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */ + kXBARB2_InputAdcEtcXbar1Coco2 = 44|0x200U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */ + kXBARB2_InputAdcEtcXbar1Coco3 = 45|0x200U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */ + kXBARB2_InputEnc1PosMatch = 46|0x200U, /**< ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */ + kXBARB2_InputEnc2PosMatch = 47|0x200U, /**< ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */ + kXBARB2_InputEnc3PosMatch = 48|0x200U, /**< ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */ + kXBARB2_InputEnc4PosMatch = 49|0x200U, /**< ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */ + kXBARB2_InputDmaDone0 = 50|0x200U, /**< DMA_DONE0 output assigned to XBARB2_IN50 input. */ + kXBARB2_InputDmaDone1 = 51|0x200U, /**< DMA_DONE1 output assigned to XBARB2_IN51 input. */ + kXBARB2_InputDmaDone2 = 52|0x200U, /**< DMA_DONE2 output assigned to XBARB2_IN52 input. */ + kXBARB2_InputDmaDone3 = 53|0x200U, /**< DMA_DONE3 output assigned to XBARB2_IN53 input. */ + kXBARB2_InputDmaDone4 = 54|0x200U, /**< DMA_DONE4 output assigned to XBARB2_IN54 input. */ + kXBARB2_InputDmaDone5 = 55|0x200U, /**< DMA_DONE5 output assigned to XBARB2_IN55 input. */ + kXBARB2_InputDmaDone6 = 56|0x200U, /**< DMA_DONE6 output assigned to XBARB2_IN56 input. */ + kXBARB2_InputDmaDone7 = 57|0x200U, /**< DMA_DONE7 output assigned to XBARB2_IN57 input. */ + kXBARB3_InputLogicLow = 0|0x300U, /**< LOGIC_LOW output assigned to XBARB3_IN0 input. */ + kXBARB3_InputLogicHigh = 1|0x300U, /**< LOGIC_HIGH output assigned to XBARB3_IN1 input. */ + kXBARB3_InputRESERVED2 = 2|0x300U, /**< XBARB3_IN2 input is reserved. */ + kXBARB3_InputRESERVED3 = 3|0x300U, /**< XBARB3_IN3 input is reserved. */ + kXBARB3_InputRESERVED4 = 4|0x300U, /**< XBARB3_IN4 input is reserved. */ + kXBARB3_InputRESERVED5 = 5|0x300U, /**< XBARB3_IN5 input is reserved. */ + kXBARB3_InputAcmp1Out = 6|0x300U, /**< ACMP1_OUT output assigned to XBARB3_IN6 input. */ + kXBARB3_InputAcmp2Out = 7|0x300U, /**< ACMP2_OUT output assigned to XBARB3_IN7 input. */ + kXBARB3_InputAcmp3Out = 8|0x300U, /**< ACMP3_OUT output assigned to XBARB3_IN8 input. */ + kXBARB3_InputAcmp4Out = 9|0x300U, /**< ACMP4_OUT output assigned to XBARB3_IN9 input. */ + kXBARB3_InputRESERVED10 = 10|0x300U, /**< XBARB3_IN10 input is reserved. */ + kXBARB3_InputRESERVED11 = 11|0x300U, /**< XBARB3_IN11 input is reserved. */ + kXBARB3_InputQtimer3Tmr0Output = 12|0x300U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */ + kXBARB3_InputQtimer3Tmr1Output = 13|0x300U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */ + kXBARB3_InputQtimer3Tmr2Output = 14|0x300U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */ + kXBARB3_InputQtimer3Tmr3Output = 15|0x300U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */ + kXBARB3_InputQtimer4Tmr0Output = 16|0x300U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */ + kXBARB3_InputQtimer4Tmr1Output = 17|0x300U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */ + kXBARB3_InputQtimer4Tmr2Output = 18|0x300U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */ + kXBARB3_InputQtimer4Tmr3Output = 19|0x300U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */ + kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 20|0x300U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */ + kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 21|0x300U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */ + kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 22|0x300U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */ + kXBARB3_InputFlexpwm1Pwm4OutTrig01 = 23|0x300U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */ + kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 24|0x300U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */ + kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 25|0x300U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */ + kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 26|0x300U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */ + kXBARB3_InputFlexpwm2Pwm4OutTrig01 = 27|0x300U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */ + kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 28|0x300U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */ + kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 29|0x300U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */ + kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 30|0x300U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */ + kXBARB3_InputFlexpwm3Pwm4OutTrig01 = 31|0x300U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */ + kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 32|0x300U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */ + kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 33|0x300U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */ + kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 34|0x300U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */ + kXBARB3_InputFlexpwm4Pwm4OutTrig01 = 35|0x300U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */ + kXBARB3_InputPitTrigger0 = 36|0x300U, /**< PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */ + kXBARB3_InputPitTrigger1 = 37|0x300U, /**< PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */ + kXBARB3_InputAdcEtcXbar0Coco0 = 38|0x300U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */ + kXBARB3_InputAdcEtcXbar0Coco1 = 39|0x300U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */ + kXBARB3_InputAdcEtcXbar0Coco2 = 40|0x300U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */ + kXBARB3_InputAdcEtcXbar0Coco3 = 41|0x300U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */ + kXBARB3_InputAdcEtcXbar1Coco0 = 42|0x300U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */ + kXBARB3_InputAdcEtcXbar1Coco1 = 43|0x300U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */ + kXBARB3_InputAdcEtcXbar1Coco2 = 44|0x300U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */ + kXBARB3_InputAdcEtcXbar1Coco3 = 45|0x300U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */ + kXBARB3_InputEnc1PosMatch = 46|0x300U, /**< ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */ + kXBARB3_InputEnc2PosMatch = 47|0x300U, /**< ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */ + kXBARB3_InputEnc3PosMatch = 48|0x300U, /**< ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */ + kXBARB3_InputEnc4PosMatch = 49|0x300U, /**< ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */ + kXBARB3_InputDmaDone0 = 50|0x300U, /**< DMA_DONE0 output assigned to XBARB3_IN50 input. */ + kXBARB3_InputDmaDone1 = 51|0x300U, /**< DMA_DONE1 output assigned to XBARB3_IN51 input. */ + kXBARB3_InputDmaDone2 = 52|0x300U, /**< DMA_DONE2 output assigned to XBARB3_IN52 input. */ + kXBARB3_InputDmaDone3 = 53|0x300U, /**< DMA_DONE3 output assigned to XBARB3_IN53 input. */ + kXBARB3_InputDmaDone4 = 54|0x300U, /**< DMA_DONE4 output assigned to XBARB3_IN54 input. */ + kXBARB3_InputDmaDone5 = 55|0x300U, /**< DMA_DONE5 output assigned to XBARB3_IN55 input. */ + kXBARB3_InputDmaDone6 = 56|0x300U, /**< DMA_DONE6 output assigned to XBARB3_IN56 input. */ + kXBARB3_InputDmaDone7 = 57|0x300U, /**< DMA_DONE7 output assigned to XBARB3_IN57 input. */ +} xbar_input_signal_t; + +typedef enum _xbar_output_signal +{ + kXBARA1_OutputDmaChMuxReq30 = 0|0x100U, /**< XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */ + kXBARA1_OutputDmaChMuxReq31 = 1|0x100U, /**< XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */ + kXBARA1_OutputDmaChMuxReq94 = 2|0x100U, /**< XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */ + kXBARA1_OutputDmaChMuxReq95 = 3|0x100U, /**< XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */ + kXBARA1_OutputIomuxXbarInout04 = 4|0x100U, /**< XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */ + kXBARA1_OutputIomuxXbarInout05 = 5|0x100U, /**< XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */ + kXBARA1_OutputIomuxXbarInout06 = 6|0x100U, /**< XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */ + kXBARA1_OutputIomuxXbarInout07 = 7|0x100U, /**< XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */ + kXBARA1_OutputIomuxXbarInout08 = 8|0x100U, /**< XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */ + kXBARA1_OutputIomuxXbarInout09 = 9|0x100U, /**< XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */ + kXBARA1_OutputIomuxXbarInout10 = 10|0x100U, /**< XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */ + kXBARA1_OutputIomuxXbarInout11 = 11|0x100U, /**< XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */ + kXBARA1_OutputIomuxXbarInout12 = 12|0x100U, /**< XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */ + kXBARA1_OutputIomuxXbarInout13 = 13|0x100U, /**< XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */ + kXBARA1_OutputIomuxXbarInout14 = 14|0x100U, /**< XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */ + kXBARA1_OutputIomuxXbarInout15 = 15|0x100U, /**< XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */ + kXBARA1_OutputIomuxXbarInout16 = 16|0x100U, /**< XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */ + kXBARA1_OutputIomuxXbarInout17 = 17|0x100U, /**< XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */ + kXBARA1_OutputIomuxXbarInout18 = 18|0x100U, /**< XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */ + kXBARA1_OutputIomuxXbarInout19 = 19|0x100U, /**< XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */ + kXBARA1_OutputAcmp1Sample = 20|0x100U, /**< XBARA1_OUT20 output assigned to ACMP1_SAMPLE */ + kXBARA1_OutputAcmp2Sample = 21|0x100U, /**< XBARA1_OUT21 output assigned to ACMP2_SAMPLE */ + kXBARA1_OutputAcmp3Sample = 22|0x100U, /**< XBARA1_OUT22 output assigned to ACMP3_SAMPLE */ + kXBARA1_OutputAcmp4Sample = 23|0x100U, /**< XBARA1_OUT23 output assigned to ACMP4_SAMPLE */ + kXBARA1_OutputRESERVED24 = 24|0x100U, /**< XBARA1_OUT24 output is reserved. */ + kXBARA1_OutputRESERVED25 = 25|0x100U, /**< XBARA1_OUT25 output is reserved. */ + kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U, /**< XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */ + kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U, /**< XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */ + kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U, /**< XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */ + kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U, /**< XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */ + kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U, /**< XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */ + kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U, /**< XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */ + kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U, /**< XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */ + kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U, /**< XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U, /**< XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */ + kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U, /**< XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */ + kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U, /**< XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */ + kXBARA1_OutputFlexpwm1234Fault2 = 37|0x100U, /**< XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */ + kXBARA1_OutputFlexpwm1234Fault3 = 38|0x100U, /**< XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */ + kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U, /**< XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */ + kXBARA1_OutputFlexpwm234Exta0 = 40|0x100U, /**< XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */ + kXBARA1_OutputFlexpwm234Exta1 = 41|0x100U, /**< XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */ + kXBARA1_OutputFlexpwm234Exta2 = 42|0x100U, /**< XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */ + kXBARA1_OutputFlexpwm234Exta3 = 43|0x100U, /**< XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */ + kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U, /**< XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */ + kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U, /**< XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */ + kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U, /**< XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */ + kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U, /**< XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm234ExtClk = 48|0x100U, /**< XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */ + kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U, /**< XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */ + kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U, /**< XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */ + kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U, /**< XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */ + kXBARA1_OutputFlexpwm3ExtSync0 = 52|0x100U, /**< XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */ + kXBARA1_OutputFlexpwm3ExtSync1 = 53|0x100U, /**< XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */ + kXBARA1_OutputFlexpwm3ExtSync2 = 54|0x100U, /**< XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */ + kXBARA1_OutputFlexpwm3ExtSync3 = 55|0x100U, /**< XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm3Fault0 = 56|0x100U, /**< XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */ + kXBARA1_OutputFlexpwm3Fault1 = 57|0x100U, /**< XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */ + kXBARA1_OutputFlexpwm3ExtForce = 58|0x100U, /**< XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */ + kXBARA1_OutputFlexpwm4ExtSync0 = 59|0x100U, /**< XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */ + kXBARA1_OutputFlexpwm4ExtSync1 = 60|0x100U, /**< XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */ + kXBARA1_OutputFlexpwm4ExtSync2 = 61|0x100U, /**< XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */ + kXBARA1_OutputFlexpwm4ExtSync3 = 62|0x100U, /**< XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm4Fault0 = 63|0x100U, /**< XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */ + kXBARA1_OutputFlexpwm4Fault1 = 64|0x100U, /**< XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */ + kXBARA1_OutputFlexpwm4ExtForce = 65|0x100U, /**< XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */ + kXBARA1_OutputEnc1PhaseAInput = 66|0x100U, /**< XBARA1_OUT66 output assigned to ENC1_PHASE_A_INPUT */ + kXBARA1_OutputEnc1PhaseBInput = 67|0x100U, /**< XBARA1_OUT67 output assigned to ENC1_PHASE_B_INPUT */ + kXBARA1_OutputEnc1Index = 68|0x100U, /**< XBARA1_OUT68 output assigned to ENC1_INDEX */ + kXBARA1_OutputEnc1Home = 69|0x100U, /**< XBARA1_OUT69 output assigned to ENC1_HOME */ + kXBARA1_OutputEnc1Trigger = 70|0x100U, /**< XBARA1_OUT70 output assigned to ENC1_TRIGGER */ + kXBARA1_OutputEnc2PhaseAInput = 71|0x100U, /**< XBARA1_OUT71 output assigned to ENC2_PHASE_A_INPUT */ + kXBARA1_OutputEnc2PhaseBInput = 72|0x100U, /**< XBARA1_OUT72 output assigned to ENC2_PHASE_B_INPUT */ + kXBARA1_OutputEnc2Index = 73|0x100U, /**< XBARA1_OUT73 output assigned to ENC2_INDEX */ + kXBARA1_OutputEnc2Home = 74|0x100U, /**< XBARA1_OUT74 output assigned to ENC2_HOME */ + kXBARA1_OutputEnc2Trigger = 75|0x100U, /**< XBARA1_OUT75 output assigned to ENC2_TRIGGER */ + kXBARA1_OutputEnc3PhaseAInput = 76|0x100U, /**< XBARA1_OUT76 output assigned to ENC3_PHASE_A_INPUT */ + kXBARA1_OutputEnc3PhaseBInput = 77|0x100U, /**< XBARA1_OUT77 output assigned to ENC3_PHASE_B_INPUT */ + kXBARA1_OutputEnc3Index = 78|0x100U, /**< XBARA1_OUT78 output assigned to ENC3_INDEX */ + kXBARA1_OutputEnc3Home = 79|0x100U, /**< XBARA1_OUT79 output assigned to ENC3_HOME */ + kXBARA1_OutputEnc3Trigger = 80|0x100U, /**< XBARA1_OUT80 output assigned to ENC3_TRIGGER */ + kXBARA1_OutputEnc4PhaseAInput = 81|0x100U, /**< XBARA1_OUT81 output assigned to ENC4_PHASE_A_INPUT */ + kXBARA1_OutputEnc4PhaseBInput = 82|0x100U, /**< XBARA1_OUT82 output assigned to ENC4_PHASE_B_INPUT */ + kXBARA1_OutputEnc4Index = 83|0x100U, /**< XBARA1_OUT83 output assigned to ENC4_INDEX */ + kXBARA1_OutputEnc4Home = 84|0x100U, /**< XBARA1_OUT84 output assigned to ENC4_HOME */ + kXBARA1_OutputEnc4Trigger = 85|0x100U, /**< XBARA1_OUT85 output assigned to ENC4_TRIGGER */ + kXBARA1_OutputQtimer1Tmr0Input = 86|0x100U, /**< XBARA1_OUT86 output assigned to QTIMER1_TMR0_INPUT */ + kXBARA1_OutputQtimer1Tmr1Input = 87|0x100U, /**< XBARA1_OUT87 output assigned to QTIMER1_TMR1_INPUT */ + kXBARA1_OutputQtimer1Tmr2Input = 88|0x100U, /**< XBARA1_OUT88 output assigned to QTIMER1_TMR2_INPUT */ + kXBARA1_OutputQtimer1Tmr3Input = 89|0x100U, /**< XBARA1_OUT89 output assigned to QTIMER1_TMR3_INPUT */ + kXBARA1_OutputQtimer2Tmr0Input = 90|0x100U, /**< XBARA1_OUT90 output assigned to QTIMER2_TMR0_INPUT */ + kXBARA1_OutputQtimer2Tmr1Input = 91|0x100U, /**< XBARA1_OUT91 output assigned to QTIMER2_TMR1_INPUT */ + kXBARA1_OutputQtimer2Tmr2Input = 92|0x100U, /**< XBARA1_OUT92 output assigned to QTIMER2_TMR2_INPUT */ + kXBARA1_OutputQtimer2Tmr3Input = 93|0x100U, /**< XBARA1_OUT93 output assigned to QTIMER2_TMR3_INPUT */ + kXBARA1_OutputQtimer3Tmr0Input = 94|0x100U, /**< XBARA1_OUT94 output assigned to QTIMER3_TMR0_INPUT */ + kXBARA1_OutputQtimer3Tmr1Input = 95|0x100U, /**< XBARA1_OUT95 output assigned to QTIMER3_TMR1_INPUT */ + kXBARA1_OutputQtimer3Tmr2Input = 96|0x100U, /**< XBARA1_OUT96 output assigned to QTIMER3_TMR2_INPUT */ + kXBARA1_OutputQtimer3Tmr3Input = 97|0x100U, /**< XBARA1_OUT97 output assigned to QTIMER3_TMR3_INPUT */ + kXBARA1_OutputQtimer4Tmr0Input = 98|0x100U, /**< XBARA1_OUT98 output assigned to QTIMER4_TMR0_INPUT */ + kXBARA1_OutputQtimer4Tmr1Input = 99|0x100U, /**< XBARA1_OUT99 output assigned to QTIMER4_TMR1_INPUT */ + kXBARA1_OutputQtimer4Tmr2Input = 100|0x100U, /**< XBARA1_OUT100 output assigned to QTIMER4_TMR2_INPUT */ + kXBARA1_OutputQtimer4Tmr3Input = 101|0x100U, /**< XBARA1_OUT101 output assigned to QTIMER4_TMR3_INPUT */ + kXBARA1_OutputEwmEwmIn = 102|0x100U, /**< XBARA1_OUT102 output assigned to EWM_EWM_IN */ + kXBARA1_OutputAdcEtcXbar0Trig0 = 103|0x100U, /**< XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */ + kXBARA1_OutputAdcEtcXbar0Trig1 = 104|0x100U, /**< XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */ + kXBARA1_OutputAdcEtcXbar0Trig2 = 105|0x100U, /**< XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */ + kXBARA1_OutputAdcEtcXbar0Trig3 = 106|0x100U, /**< XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */ + kXBARA1_OutputAdcEtcXbar1Trig0 = 107|0x100U, /**< XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */ + kXBARA1_OutputAdcEtcXbar1Trig1 = 108|0x100U, /**< XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */ + kXBARA1_OutputAdcEtcXbar1Trig2 = 109|0x100U, /**< XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */ + kXBARA1_OutputAdcEtcXbar1Trig3 = 110|0x100U, /**< XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */ + kXBARA1_OutputLpi2c1TrgInput = 111|0x100U, /**< XBARA1_OUT111 output assigned to LPI2C1_TRG_INPUT */ + kXBARA1_OutputLpi2c2TrgInput = 112|0x100U, /**< XBARA1_OUT112 output assigned to LPI2C2_TRG_INPUT */ + kXBARA1_OutputLpi2c3TrgInput = 113|0x100U, /**< XBARA1_OUT113 output assigned to LPI2C3_TRG_INPUT */ + kXBARA1_OutputLpi2c4TrgInput = 114|0x100U, /**< XBARA1_OUT114 output assigned to LPI2C4_TRG_INPUT */ + kXBARA1_OutputLpspi1TrgInput = 115|0x100U, /**< XBARA1_OUT115 output assigned to LPSPI1_TRG_INPUT */ + kXBARA1_OutputLpspi2TrgInput = 116|0x100U, /**< XBARA1_OUT116 output assigned to LPSPI2_TRG_INPUT */ + kXBARA1_OutputLpspi3TrgInput = 117|0x100U, /**< XBARA1_OUT117 output assigned to LPSPI3_TRG_INPUT */ + kXBARA1_OutputLpspi4TrgInput = 118|0x100U, /**< XBARA1_OUT118 output assigned to LPSPI4_TRG_INPUT */ + kXBARA1_OutputLpuart1TrgInput = 119|0x100U, /**< XBARA1_OUT119 output assigned to LPUART1_TRG_INPUT */ + kXBARA1_OutputLpuart2TrgInput = 120|0x100U, /**< XBARA1_OUT120 output assigned to LPUART2_TRG_INPUT */ + kXBARA1_OutputLpuart3TrgInput = 121|0x100U, /**< XBARA1_OUT121 output assigned to LPUART3_TRG_INPUT */ + kXBARA1_OutputLpuart4TrgInput = 122|0x100U, /**< XBARA1_OUT122 output assigned to LPUART4_TRG_INPUT */ + kXBARA1_OutputLpuart5TrgInput = 123|0x100U, /**< XBARA1_OUT123 output assigned to LPUART5_TRG_INPUT */ + kXBARA1_OutputLpuart6TrgInput = 124|0x100U, /**< XBARA1_OUT124 output assigned to LPUART6_TRG_INPUT */ + kXBARA1_OutputLpuart7TrgInput = 125|0x100U, /**< XBARA1_OUT125 output assigned to LPUART7_TRG_INPUT */ + kXBARA1_OutputLpuart8TrgInput = 126|0x100U, /**< XBARA1_OUT126 output assigned to LPUART8_TRG_INPUT */ + kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U, /**< XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */ + kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U, /**< XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */ + kXBARA1_OutputFlexio2TriggerIn0 = 129|0x100U, /**< XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */ + kXBARA1_OutputFlexio2TriggerIn1 = 130|0x100U, /**< XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */ + kXBARB2_OutputAoi1In00 = 0|0x200U, /**< XBARB2_OUT0 output assigned to AOI1_IN00 */ + kXBARB2_OutputAoi1In01 = 1|0x200U, /**< XBARB2_OUT1 output assigned to AOI1_IN01 */ + kXBARB2_OutputAoi1In02 = 2|0x200U, /**< XBARB2_OUT2 output assigned to AOI1_IN02 */ + kXBARB2_OutputAoi1In03 = 3|0x200U, /**< XBARB2_OUT3 output assigned to AOI1_IN03 */ + kXBARB2_OutputAoi1In04 = 4|0x200U, /**< XBARB2_OUT4 output assigned to AOI1_IN04 */ + kXBARB2_OutputAoi1In05 = 5|0x200U, /**< XBARB2_OUT5 output assigned to AOI1_IN05 */ + kXBARB2_OutputAoi1In06 = 6|0x200U, /**< XBARB2_OUT6 output assigned to AOI1_IN06 */ + kXBARB2_OutputAoi1In07 = 7|0x200U, /**< XBARB2_OUT7 output assigned to AOI1_IN07 */ + kXBARB2_OutputAoi1In08 = 8|0x200U, /**< XBARB2_OUT8 output assigned to AOI1_IN08 */ + kXBARB2_OutputAoi1In09 = 9|0x200U, /**< XBARB2_OUT9 output assigned to AOI1_IN09 */ + kXBARB2_OutputAoi1In10 = 10|0x200U, /**< XBARB2_OUT10 output assigned to AOI1_IN10 */ + kXBARB2_OutputAoi1In11 = 11|0x200U, /**< XBARB2_OUT11 output assigned to AOI1_IN11 */ + kXBARB2_OutputAoi1In12 = 12|0x200U, /**< XBARB2_OUT12 output assigned to AOI1_IN12 */ + kXBARB2_OutputAoi1In13 = 13|0x200U, /**< XBARB2_OUT13 output assigned to AOI1_IN13 */ + kXBARB2_OutputAoi1In14 = 14|0x200U, /**< XBARB2_OUT14 output assigned to AOI1_IN14 */ + kXBARB2_OutputAoi1In15 = 15|0x200U, /**< XBARB2_OUT15 output assigned to AOI1_IN15 */ + kXBARB3_OutputAoi2In00 = 0|0x300U, /**< XBARB3_OUT0 output assigned to AOI2_IN00 */ + kXBARB3_OutputAoi2In01 = 1|0x300U, /**< XBARB3_OUT1 output assigned to AOI2_IN01 */ + kXBARB3_OutputAoi2In02 = 2|0x300U, /**< XBARB3_OUT2 output assigned to AOI2_IN02 */ + kXBARB3_OutputAoi2In03 = 3|0x300U, /**< XBARB3_OUT3 output assigned to AOI2_IN03 */ + kXBARB3_OutputAoi2In04 = 4|0x300U, /**< XBARB3_OUT4 output assigned to AOI2_IN04 */ + kXBARB3_OutputAoi2In05 = 5|0x300U, /**< XBARB3_OUT5 output assigned to AOI2_IN05 */ + kXBARB3_OutputAoi2In06 = 6|0x300U, /**< XBARB3_OUT6 output assigned to AOI2_IN06 */ + kXBARB3_OutputAoi2In07 = 7|0x300U, /**< XBARB3_OUT7 output assigned to AOI2_IN07 */ + kXBARB3_OutputAoi2In08 = 8|0x300U, /**< XBARB3_OUT8 output assigned to AOI2_IN08 */ + kXBARB3_OutputAoi2In09 = 9|0x300U, /**< XBARB3_OUT9 output assigned to AOI2_IN09 */ + kXBARB3_OutputAoi2In10 = 10|0x300U, /**< XBARB3_OUT10 output assigned to AOI2_IN10 */ + kXBARB3_OutputAoi2In11 = 11|0x300U, /**< XBARB3_OUT11 output assigned to AOI2_IN11 */ + kXBARB3_OutputAoi2In12 = 12|0x300U, /**< XBARB3_OUT12 output assigned to AOI2_IN12 */ + kXBARB3_OutputAoi2In13 = 13|0x300U, /**< XBARB3_OUT13 output assigned to AOI2_IN13 */ + kXBARB3_OutputAoi2In14 = 14|0x300U, /**< XBARB3_OUT14 output assigned to AOI2_IN14 */ + kXBARB3_OutputAoi2In15 = 15|0x300U, /**< XBARB3_OUT15 output assigned to AOI2_IN15 */ +} xbar_output_signal_t; + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__CWCC__) + #pragma push + #pragma cpp_extensions on +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t HC[8]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */ + __I uint32_t HS; /**< Status register for HW triggers, offset: 0x20 */ + __I uint32_t R[8]; /**< Data result register for HW triggers, array offset: 0x24, array step: 0x4 */ + __IO uint32_t CFG; /**< Configuration register, offset: 0x44 */ + __IO uint32_t GC; /**< General control register, offset: 0x48 */ + __IO uint32_t GS; /**< General status register, offset: 0x4C */ + __IO uint32_t CV; /**< Compare value register, offset: 0x50 */ + __IO uint32_t OFS; /**< Offset correction value register, offset: 0x54 */ + __IO uint32_t CAL; /**< Calibration value register, offset: 0x58 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name HC - Control register for hardware triggers */ +/*! @{ */ +#define ADC_HC_ADCH_MASK (0x1FU) +#define ADC_HC_ADCH_SHIFT (0U) +/*! ADCH - Input Channel Select + * 0b10000..External channel selection from ADC_ETC + * 0b11000..Reserved. + * 0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + * 0b11010..Reserved. + * 0b11011..Reserved. + * 0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion. + */ +#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK) +#define ADC_HC_AIEN_MASK (0x80U) +#define ADC_HC_AIEN_SHIFT (7U) +/*! AIEN - Conversion Complete Interrupt Enable/Disable Control + * 0b1..Conversion complete interrupt enabled + * 0b0..Conversion complete interrupt disabled + */ +#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK) +/*! @} */ + +/* The count of ADC_HC */ +#define ADC_HC_COUNT (8U) + +/*! @name HS - Status register for HW triggers */ +/*! @{ */ +#define ADC_HS_COCO0_MASK (0x1U) +#define ADC_HS_COCO0_SHIFT (0U) +#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK) +/*! @} */ + +/*! @name R - Data result register for HW triggers */ +/*! @{ */ +#define ADC_R_CDATA_MASK (0xFFFU) +#define ADC_R_CDATA_SHIFT (0U) +#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK) +/*! @} */ + +/* The count of ADC_R */ +#define ADC_R_COUNT (8U) + +/*! @name CFG - Configuration register */ +/*! @{ */ +#define ADC_CFG_ADICLK_MASK (0x3U) +#define ADC_CFG_ADICLK_SHIFT (0U) +/*! ADICLK - Input Clock Select + * 0b00..IPG clock + * 0b01..IPG clock divided by 2 + * 0b10..Reserved + * 0b11..Asynchronous clock (ADACK) + */ +#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK) +#define ADC_CFG_MODE_MASK (0xCU) +#define ADC_CFG_MODE_SHIFT (2U) +/*! MODE - Conversion Mode Selection + * 0b00..8-bit conversion + * 0b01..10-bit conversion + * 0b10..12-bit conversion + * 0b11..Reserved + */ +#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK) +#define ADC_CFG_ADLSMP_MASK (0x10U) +#define ADC_CFG_ADLSMP_SHIFT (4U) +/*! ADLSMP - Long Sample Time Configuration + * 0b0..Short sample mode. + * 0b1..Long sample mode. + */ +#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK) +#define ADC_CFG_ADIV_MASK (0x60U) +#define ADC_CFG_ADIV_SHIFT (5U) +/*! ADIV - Clock Divide Select + * 0b00..Input clock + * 0b01..Input clock / 2 + * 0b10..Input clock / 4 + * 0b11..Input clock / 8 + */ +#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK) +#define ADC_CFG_ADLPC_MASK (0x80U) +#define ADC_CFG_ADLPC_SHIFT (7U) +/*! ADLPC - Low-Power Configuration + * 0b0..ADC hard block not in low power mode. + * 0b1..ADC hard block in low power mode. + */ +#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK) +#define ADC_CFG_ADSTS_MASK (0x300U) +#define ADC_CFG_ADSTS_SHIFT (8U) +/*! ADSTS + * 0b00..Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b + * 0b01..Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b + * 0b10..Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b + * 0b11..Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b + */ +#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK) +#define ADC_CFG_ADHSC_MASK (0x400U) +#define ADC_CFG_ADHSC_SHIFT (10U) +/*! ADHSC - High Speed Configuration + * 0b0..Normal conversion selected. + * 0b1..High speed conversion selected. + */ +#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK) +#define ADC_CFG_REFSEL_MASK (0x1800U) +#define ADC_CFG_REFSEL_SHIFT (11U) +/*! REFSEL - Voltage Reference Selection + * 0b00..Selects VREFH/VREFL as reference voltage. + * 0b01..Reserved + * 0b10..Reserved + * 0b11..Reserved + */ +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) +#define ADC_CFG_ADTRG_MASK (0x2000U) +#define ADC_CFG_ADTRG_SHIFT (13U) +/*! ADTRG - Conversion Trigger Select + * 0b0..Software trigger selected + * 0b1..Hardware trigger selected + */ +#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK) +#define ADC_CFG_AVGS_MASK (0xC000U) +#define ADC_CFG_AVGS_SHIFT (14U) +/*! AVGS - Hardware Average select + * 0b00..4 samples averaged + * 0b01..8 samples averaged + * 0b10..16 samples averaged + * 0b11..32 samples averaged + */ +#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK) +#define ADC_CFG_OVWREN_MASK (0x10000U) +#define ADC_CFG_OVWREN_SHIFT (16U) +/*! OVWREN - Data Overwrite Enable + * 0b1..Enable the overwriting. + * 0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data. + */ +#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK) +/*! @} */ + +/*! @name GC - General control register */ +/*! @{ */ +#define ADC_GC_ADACKEN_MASK (0x1U) +#define ADC_GC_ADACKEN_SHIFT (0U) +/*! ADACKEN - Asynchronous clock output enable + * 0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. + * 0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC + */ +#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK) +#define ADC_GC_DMAEN_MASK (0x2U) +#define ADC_GC_DMAEN_SHIFT (1U) +/*! DMAEN - DMA Enable + * 0b0..DMA disabled (default) + * 0b1..DMA enabled + */ +#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK) +#define ADC_GC_ACREN_MASK (0x4U) +#define ADC_GC_ACREN_SHIFT (2U) +/*! ACREN - Compare Function Range Enable + * 0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared. + * 0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared. + */ +#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK) +#define ADC_GC_ACFGT_MASK (0x8U) +#define ADC_GC_ACFGT_SHIFT (3U) +/*! ACFGT - Compare Function Greater Than Enable + * 0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" + * functionality based on the values placed in the ADC_CV register. + * 0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" + * functionality based on the values placed in the ADC_CV registers. + */ +#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK) +#define ADC_GC_ACFE_MASK (0x10U) +#define ADC_GC_ACFE_SHIFT (4U) +/*! ACFE - Compare Function Enable + * 0b0..Compare function disabled + * 0b1..Compare function enabled + */ +#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK) +#define ADC_GC_AVGE_MASK (0x20U) +#define ADC_GC_AVGE_SHIFT (5U) +/*! AVGE - Hardware average enable + * 0b0..Hardware average function disabled + * 0b1..Hardware average function enabled + */ +#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK) +#define ADC_GC_ADCO_MASK (0x40U) +#define ADC_GC_ADCO_SHIFT (6U) +/*! ADCO - Continuous Conversion Enable + * 0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + */ +#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK) +#define ADC_GC_CAL_MASK (0x80U) +#define ADC_GC_CAL_SHIFT (7U) +#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK) +/*! @} */ + +/*! @name GS - General status register */ +/*! @{ */ +#define ADC_GS_ADACT_MASK (0x1U) +#define ADC_GS_ADACT_SHIFT (0U) +/*! ADACT - Conversion Active + * 0b0..Conversion not in progress. + * 0b1..Conversion in progress. + */ +#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK) +#define ADC_GS_CALF_MASK (0x2U) +#define ADC_GS_CALF_SHIFT (1U) +/*! CALF - Calibration Failed Flag + * 0b0..Calibration completed normally. + * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed. + */ +#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK) +#define ADC_GS_AWKST_MASK (0x4U) +#define ADC_GS_AWKST_SHIFT (2U) +/*! AWKST - Asynchronous wakeup interrupt status + * 0b1..Asynchronous wake up interrupt occurred in stop mode. + * 0b0..No asynchronous interrupt. + */ +#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK) +/*! @} */ + +/*! @name CV - Compare value register */ +/*! @{ */ +#define ADC_CV_CV1_MASK (0xFFFU) +#define ADC_CV_CV1_SHIFT (0U) +#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK) +#define ADC_CV_CV2_MASK (0xFFF0000U) +#define ADC_CV_CV2_SHIFT (16U) +#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK) +/*! @} */ + +/*! @name OFS - Offset correction value register */ +/*! @{ */ +#define ADC_OFS_OFS_MASK (0xFFFU) +#define ADC_OFS_OFS_SHIFT (0U) +#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) +#define ADC_OFS_SIGN_MASK (0x1000U) +#define ADC_OFS_SIGN_SHIFT (12U) +/*! SIGN - Sign bit + * 0b0..The offset value is added with the raw result + * 0b1..The offset value is subtracted from the raw converted value + */ +#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK) +/*! @} */ + +/*! @name CAL - Calibration value register */ +/*! @{ */ +#define ADC_CAL_CAL_CODE_MASK (0xFU) +#define ADC_CAL_CAL_CODE_SHIFT (0U) +#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x400C4000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Peripheral ADC2 base address */ +#define ADC2_BASE (0x400C8000u) +/** Peripheral ADC2 base pointer */ +#define ADC2 ((ADC_Type *)ADC2_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ADC_ETC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer + * @{ + */ + +/** ADC_ETC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< ADC_ETC Global Control Register, offset: 0x0 */ + __IO uint32_t DONE0_1_IRQ; /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */ + __IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */ + __IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */ + struct { /* offset: 0x10, array step: 0x28 */ + __IO uint32_t TRIGn_CTRL; /**< ETC_TRIG0 Control Register..ETC_TRIG7 Control Register, array offset: 0x10, array step: 0x28 */ + __IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register, array offset: 0x14, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */ + __IO uint32_t TRIGn_CHAIN_7_6; /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_1_0; /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_3_2; /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_5_4; /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */ + __I uint32_t TRIGn_RESULT_7_6; /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */ + } TRIG[8]; +} ADC_ETC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC_ETC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks + * @{ + */ + +/*! @name CTRL - ADC_ETC Global Control Register */ +/*! @{ */ +#define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU) +#define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U) +#define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK) +#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U) +#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U) +#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK) +#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U) +#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U) +#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK) +#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U) +#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U) +#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK) +#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U) +#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U) +#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK) +#define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U) +#define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U) +#define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK) +#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U) +#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U) +#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK) +#define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U) +#define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U) +#define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK) +#define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U) +#define ADC_ETC_CTRL_SOFTRST_SHIFT (31U) +#define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK) +/*! @} */ + +/*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */ +/*! @{ */ +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U) +#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U) +#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U) +#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U) +#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U) +#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U) +#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U) +#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U) +#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK) +/*! @} */ + +/*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */ +/*! @{ */ +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U) +#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK) +/*! @} */ + +/*! @name DMA_CTRL - ETC DMA control Register */ +/*! @{ */ +#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) +#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U) +#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U) +#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U) +#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U) +#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U) +#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U) +#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U) +#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U) +#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U) +#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U) +#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U) +#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U) +#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U) +#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U) +#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U) +#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK) +#define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U) +#define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U) +#define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U) +#define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U) +#define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U) +#define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U) +#define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U) +#define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U) +#define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U) +#define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U) +#define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U) +#define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U) +#define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U) +#define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U) +#define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK) +#define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U) +#define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U) +#define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK) +/*! @} */ + +/*! @name TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG7 Control Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U) +#define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U) +#define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK) +#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U) +#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U) +#define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK) +#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U) +#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U) +#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK) +#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U) +#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U) +#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK) +#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U) +#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U) +#define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CTRL */ +#define ADC_ETC_TRIGn_CTRL_COUNT (8U) + +/*! @name TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU) +#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U) +#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK) +#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U) +#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U) +#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_COUNTER */ +#define ADC_ETC_TRIGn_COUNTER_COUNT (8U) + +/*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_1_0 */ +#define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U) + +/*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_3_2 */ +#define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U) + +/*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_5_4 */ +#define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U) + +/*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U) +#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U) +#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U) +#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U) +#define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_CHAIN_7_6 */ +#define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U) + +/*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_1_0 */ +#define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U) + +/*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_3_2 */ +#define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U) + +/*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_5_4 */ +#define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U) + +/*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */ +/*! @{ */ +#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U) +#define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK) +/*! @} */ + +/* The count of ADC_ETC_TRIGn_RESULT_7_6 */ +#define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U) + + +/*! + * @} + */ /* end of group ADC_ETC_Register_Masks */ + + +/* ADC_ETC - Peripheral instance base addresses */ +/** Peripheral ADC_ETC base address */ +#define ADC_ETC_BASE (0x403B0000u) +/** Peripheral ADC_ETC base pointer */ +#define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE) +/** Array initializer of ADC_ETC peripheral base addresses */ +#define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE } +/** Array initializer of ADC_ETC peripheral base pointers */ +#define ADC_ETC_BASE_PTRS { ADC_ETC } +/** Interrupt vectors for the ADC_ETC peripheral type */ +#define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } } +#define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn } + +/*! + * @} + */ /* end of group ADC_ETC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer + * @{ + */ + +/** AIPSTZ - Register Layout Typedef */ +typedef struct { + __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ + uint8_t RESERVED_0[60]; + __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */ + __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */ + __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */ + __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */ + __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */ +} AIPSTZ_Type; + +/* ---------------------------------------------------------------------------- + -- AIPSTZ Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks + * @{ + */ + +/*! @name MPR - Master Priviledge Registers */ +/*! @{ */ +#define AIPSTZ_MPR_MPROT5_MASK (0xF00U) +#define AIPSTZ_MPR_MPROT5_SHIFT (8U) +/*! MPROT5 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) +#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U) +#define AIPSTZ_MPR_MPROT3_SHIFT (16U) +/*! MPROT3 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) +#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U) +#define AIPSTZ_MPR_MPROT2_SHIFT (20U) +/*! MPROT2 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) +#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U) +#define AIPSTZ_MPR_MPROT1_SHIFT (24U) +/*! MPROT1 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) +#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) +#define AIPSTZ_MPR_MPROT0_SHIFT (28U) +/*! MPROT0 + * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + * 0bxx0x..This master is not trusted for write accesses. + * 0bxx1x..This master is trusted for write accesses. + * 0bx0xx..This master is not trusted for read accesses. + * 0bx1xx..This master is trusted for read accesses. + * 0b1xxx..Write accesses from this master are allowed to be buffered + */ +#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) +/*! @} */ + +/*! @name OPACR - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR_OPAC7_MASK (0xFU) +#define AIPSTZ_OPACR_OPAC7_SHIFT (0U) +/*! OPAC7 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) +#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U) +#define AIPSTZ_OPACR_OPAC6_SHIFT (4U) +/*! OPAC6 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK) +#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U) +#define AIPSTZ_OPACR_OPAC5_SHIFT (8U) +/*! OPAC5 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK) +#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U) +#define AIPSTZ_OPACR_OPAC4_SHIFT (12U) +/*! OPAC4 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK) +#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U) +#define AIPSTZ_OPACR_OPAC3_SHIFT (16U) +/*! OPAC3 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK) +#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U) +#define AIPSTZ_OPACR_OPAC2_SHIFT (20U) +/*! OPAC2 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK) +#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U) +#define AIPSTZ_OPACR_OPAC1_SHIFT (24U) +/*! OPAC1 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK) +#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U) +#define AIPSTZ_OPACR_OPAC0_SHIFT (28U) +/*! OPAC0 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK) +/*! @} */ + +/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU) +#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U) +/*! OPAC15 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK) +#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U) +#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U) +/*! OPAC14 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK) +#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U) +#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U) +/*! OPAC13 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK) +#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U) +#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U) +/*! OPAC12 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK) +#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U) +#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U) +/*! OPAC11 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK) +#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U) +#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U) +/*! OPAC10 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK) +#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U) +#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U) +/*! OPAC9 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK) +#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U) +#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U) +/*! OPAC8 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK) +/*! @} */ + +/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU) +#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U) +/*! OPAC23 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK) +#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U) +#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U) +/*! OPAC22 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK) +#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U) +#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U) +/*! OPAC21 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK) +#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U) +#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U) +/*! OPAC20 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK) +#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U) +#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U) +/*! OPAC19 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK) +#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U) +#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U) +/*! OPAC18 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK) +#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U) +#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U) +/*! OPAC17 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK) +#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U) +#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U) +/*! OPAC16 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK) +/*! @} */ + +/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU) +#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U) +/*! OPAC31 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK) +#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U) +#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U) +/*! OPAC30 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK) +#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U) +#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U) +/*! OPAC29 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK) +#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U) +#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U) +/*! OPAC28 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK) +#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U) +#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U) +/*! OPAC27 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK) +#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U) +#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U) +/*! OPAC26 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK) +#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U) +#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U) +/*! OPAC25 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK) +#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U) +#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U) +/*! OPAC24 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK) +/*! @} */ + +/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */ +/*! @{ */ +#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U) +#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U) +/*! OPAC33 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK) +#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U) +#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U) +/*! OPAC32 + * 0bxxx0..Accesses from an untrusted master are allowed. + * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, + * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + * 0bxx0x..This peripheral allows write accesses. + * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an + * error response and no peripheral access is initiated on the IPS bus. + * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. + * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must + * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must + * be set. If not, the access is terminated with an error response and no peripheral access is initiated + * on the IPS bus. + * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. + */ +#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group AIPSTZ_Register_Masks */ + + +/* AIPSTZ - Peripheral instance base addresses */ +/** Peripheral AIPSTZ1 base address */ +#define AIPSTZ1_BASE (0x4007C000u) +/** Peripheral AIPSTZ1 base pointer */ +#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE) +/** Peripheral AIPSTZ2 base address */ +#define AIPSTZ2_BASE (0x4017C000u) +/** Peripheral AIPSTZ2 base pointer */ +#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE) +/** Peripheral AIPSTZ3 base address */ +#define AIPSTZ3_BASE (0x4027C000u) +/** Peripheral AIPSTZ3 base pointer */ +#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE) +/** Peripheral AIPSTZ4 base address */ +#define AIPSTZ4_BASE (0x4037C000u) +/** Peripheral AIPSTZ4 base pointer */ +#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE) +/** Array initializer of AIPSTZ peripheral base addresses */ +#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE } +/** Array initializer of AIPSTZ peripheral base pointers */ +#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 } + +/*! + * @} + */ /* end of group AIPSTZ_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AOI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer + * @{ + */ + +/** AOI - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x4 */ + __IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */ + __IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */ + } BFCRT[4]; +} AOI_Type; + +/* ---------------------------------------------------------------------------- + -- AOI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AOI_Register_Masks AOI Register Masks + * @{ + */ + +/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */ +/*! @{ */ +#define AOI_BFCRT01_PT1_DC_MASK (0x3U) +#define AOI_BFCRT01_PT1_DC_SHIFT (0U) +/*! PT1_DC - Product term 1, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK) +#define AOI_BFCRT01_PT1_CC_MASK (0xCU) +#define AOI_BFCRT01_PT1_CC_SHIFT (2U) +/*! PT1_CC - Product term 1, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK) +#define AOI_BFCRT01_PT1_BC_MASK (0x30U) +#define AOI_BFCRT01_PT1_BC_SHIFT (4U) +/*! PT1_BC - Product term 1, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK) +#define AOI_BFCRT01_PT1_AC_MASK (0xC0U) +#define AOI_BFCRT01_PT1_AC_SHIFT (6U) +/*! PT1_AC - Product term 1, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK) +#define AOI_BFCRT01_PT0_DC_MASK (0x300U) +#define AOI_BFCRT01_PT0_DC_SHIFT (8U) +/*! PT0_DC - Product term 0, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK) +#define AOI_BFCRT01_PT0_CC_MASK (0xC00U) +#define AOI_BFCRT01_PT0_CC_SHIFT (10U) +/*! PT0_CC - Product term 0, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK) +#define AOI_BFCRT01_PT0_BC_MASK (0x3000U) +#define AOI_BFCRT01_PT0_BC_SHIFT (12U) +/*! PT0_BC - Product term 0, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK) +#define AOI_BFCRT01_PT0_AC_MASK (0xC000U) +#define AOI_BFCRT01_PT0_AC_SHIFT (14U) +/*! PT0_AC - Product term 0, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK) +/*! @} */ + +/* The count of AOI_BFCRT01 */ +#define AOI_BFCRT01_COUNT (4U) + +/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */ +/*! @{ */ +#define AOI_BFCRT23_PT3_DC_MASK (0x3U) +#define AOI_BFCRT23_PT3_DC_SHIFT (0U) +/*! PT3_DC - Product term 3, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK) +#define AOI_BFCRT23_PT3_CC_MASK (0xCU) +#define AOI_BFCRT23_PT3_CC_SHIFT (2U) +/*! PT3_CC - Product term 3, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK) +#define AOI_BFCRT23_PT3_BC_MASK (0x30U) +#define AOI_BFCRT23_PT3_BC_SHIFT (4U) +/*! PT3_BC - Product term 3, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK) +#define AOI_BFCRT23_PT3_AC_MASK (0xC0U) +#define AOI_BFCRT23_PT3_AC_SHIFT (6U) +/*! PT3_AC - Product term 3, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK) +#define AOI_BFCRT23_PT2_DC_MASK (0x300U) +#define AOI_BFCRT23_PT2_DC_SHIFT (8U) +/*! PT2_DC - Product term 2, D input configuration + * 0b00..Force the D input in this product term to a logical zero + * 0b01..Pass the D input in this product term + * 0b10..Complement the D input in this product term + * 0b11..Force the D input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK) +#define AOI_BFCRT23_PT2_CC_MASK (0xC00U) +#define AOI_BFCRT23_PT2_CC_SHIFT (10U) +/*! PT2_CC - Product term 2, C input configuration + * 0b00..Force the C input in this product term to a logical zero + * 0b01..Pass the C input in this product term + * 0b10..Complement the C input in this product term + * 0b11..Force the C input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK) +#define AOI_BFCRT23_PT2_BC_MASK (0x3000U) +#define AOI_BFCRT23_PT2_BC_SHIFT (12U) +/*! PT2_BC - Product term 2, B input configuration + * 0b00..Force the B input in this product term to a logical zero + * 0b01..Pass the B input in this product term + * 0b10..Complement the B input in this product term + * 0b11..Force the B input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK) +#define AOI_BFCRT23_PT2_AC_MASK (0xC000U) +#define AOI_BFCRT23_PT2_AC_SHIFT (14U) +/*! PT2_AC - Product term 2, A input configuration + * 0b00..Force the A input in this product term to a logical zero + * 0b01..Pass the A input in this product term + * 0b10..Complement the A input in this product term + * 0b11..Force the A input in this product term to a logical one + */ +#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK) +/*! @} */ + +/* The count of AOI_BFCRT23 */ +#define AOI_BFCRT23_COUNT (4U) + + +/*! + * @} + */ /* end of group AOI_Register_Masks */ + + +/* AOI - Peripheral instance base addresses */ +/** Peripheral AOI1 base address */ +#define AOI1_BASE (0x403B4000u) +/** Peripheral AOI1 base pointer */ +#define AOI1 ((AOI_Type *)AOI1_BASE) +/** Peripheral AOI2 base address */ +#define AOI2_BASE (0x403B8000u) +/** Peripheral AOI2 base pointer */ +#define AOI2 ((AOI_Type *)AOI2_BASE) +/** Array initializer of AOI peripheral base addresses */ +#define AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE } +/** Array initializer of AOI peripheral base pointers */ +#define AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 } + +/*! + * @} + */ /* end of group AOI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- BEE Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BEE_Peripheral_Access_Layer BEE Peripheral Access Layer + * @{ + */ + +/** BEE - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< BEE Control Register, offset: 0x0 */ + __IO uint32_t ADDR_OFFSET0; /**< , offset: 0x4 */ + __IO uint32_t ADDR_OFFSET1; /**< , offset: 0x8 */ + __IO uint32_t AES_KEY0_W0; /**< , offset: 0xC */ + __IO uint32_t AES_KEY0_W1; /**< , offset: 0x10 */ + __IO uint32_t AES_KEY0_W2; /**< , offset: 0x14 */ + __IO uint32_t AES_KEY0_W3; /**< , offset: 0x18 */ + __IO uint32_t STATUS; /**< , offset: 0x1C */ + __O uint32_t CTR_NONCE0_W0; /**< , offset: 0x20 */ + __O uint32_t CTR_NONCE0_W1; /**< , offset: 0x24 */ + __O uint32_t CTR_NONCE0_W2; /**< , offset: 0x28 */ + __O uint32_t CTR_NONCE0_W3; /**< , offset: 0x2C */ + __O uint32_t CTR_NONCE1_W0; /**< , offset: 0x30 */ + __O uint32_t CTR_NONCE1_W1; /**< , offset: 0x34 */ + __O uint32_t CTR_NONCE1_W2; /**< , offset: 0x38 */ + __O uint32_t CTR_NONCE1_W3; /**< , offset: 0x3C */ + __IO uint32_t REGION1_TOP; /**< , offset: 0x40 */ + __IO uint32_t REGION1_BOT; /**< , offset: 0x44 */ +} BEE_Type; + +/* ---------------------------------------------------------------------------- + -- BEE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BEE_Register_Masks BEE Register Masks + * @{ + */ + +/*! @name CTRL - BEE Control Register */ +/*! @{ */ +#define BEE_CTRL_BEE_ENABLE_MASK (0x1U) +#define BEE_CTRL_BEE_ENABLE_SHIFT (0U) +/*! BEE_ENABLE + * 0b0..Disable BEE + * 0b1..Enable BEE + */ +#define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK) +#define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U) +#define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U) +#define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK) +#define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U) +#define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U) +#define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK) +#define BEE_CTRL_KEY_VALID_MASK (0x10U) +#define BEE_CTRL_KEY_VALID_SHIFT (4U) +#define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK) +#define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U) +#define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U) +/*! KEY_REGION_SEL + * 0b0..Load AES key for region0 + * 0b1..Load AES key for region1 + */ +#define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK) +#define BEE_CTRL_AC_PROT_EN_MASK (0x40U) +#define BEE_CTRL_AC_PROT_EN_SHIFT (6U) +#define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK) +#define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U) +#define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U) +/*! LITTLE_ENDIAN + * 0b0..The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8, + * B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to + * Byte0 to Byte15. + * 0b1..The input and output data of AES core is not swapped. + */ +#define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U) +#define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U) +#define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U) +#define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U) +/*! CTRL_AES_MODE_R0 + * 0b0..ECB + * 0b1..CTR + */ +#define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U) +#define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U) +#define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U) +#define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U) +/*! CTRL_AES_MODE_R1 + * 0b0..ECB + * 0b1..CTR + */ +#define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK) +#define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U) +#define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U) +#define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK) +#define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U) +#define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U) +#define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK) +#define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U) +#define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U) +#define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK) +#define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U) +#define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U) +#define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK) +#define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U) +#define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U) +#define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK) +#define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U) +#define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U) +#define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK) +#define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U) +#define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U) +#define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK) +#define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U) +#define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U) +#define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U) +#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U) +#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U) +#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U) +#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK) +#define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U) +#define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U) +#define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK) +#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U) +#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U) +#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK) +#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U) +#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U) +#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK) +#define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U) +#define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U) +#define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK) +/*! @} */ + +/*! @name ADDR_OFFSET0 - */ +/*! @{ */ +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U) +#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK) +/*! @} */ + +/*! @name ADDR_OFFSET1 - */ +/*! @{ */ +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U) +#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK) +/*! @} */ + +/*! @name AES_KEY0_W0 - */ +/*! @{ */ +#define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W0_KEY0_SHIFT (0U) +#define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK) +/*! @} */ + +/*! @name AES_KEY0_W1 - */ +/*! @{ */ +#define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W1_KEY1_SHIFT (0U) +#define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK) +/*! @} */ + +/*! @name AES_KEY0_W2 - */ +/*! @{ */ +#define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W2_KEY2_SHIFT (0U) +#define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK) +/*! @} */ + +/*! @name AES_KEY0_W3 - */ +/*! @{ */ +#define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU) +#define BEE_AES_KEY0_W3_KEY3_SHIFT (0U) +#define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK) +/*! @} */ + +/*! @name STATUS - */ +/*! @{ */ +#define BEE_STATUS_IRQ_VEC_MASK (0xFFU) +#define BEE_STATUS_IRQ_VEC_SHIFT (0U) +#define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK) +#define BEE_STATUS_BEE_IDLE_MASK (0x100U) +#define BEE_STATUS_BEE_IDLE_SHIFT (8U) +#define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W0 - */ +/*! @{ */ +#define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U) +#define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W1 - */ +/*! @{ */ +#define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U) +#define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W2 - */ +/*! @{ */ +#define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U) +#define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK) +/*! @} */ + +/*! @name CTR_NONCE0_W3 - */ +/*! @{ */ +#define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U) +#define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W0 - */ +/*! @{ */ +#define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U) +#define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W1 - */ +/*! @{ */ +#define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U) +#define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W2 - */ +/*! @{ */ +#define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U) +#define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK) +/*! @} */ + +/*! @name CTR_NONCE1_W3 - */ +/*! @{ */ +#define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU) +#define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U) +#define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK) +/*! @} */ + +/*! @name REGION1_TOP - */ +/*! @{ */ +#define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU) +#define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U) +#define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK) +/*! @} */ + +/*! @name REGION1_BOT - */ +/*! @{ */ +#define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU) +#define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U) +#define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group BEE_Register_Masks */ + + +/* BEE - Peripheral instance base addresses */ +/** Peripheral BEE base address */ +#define BEE_BASE (0x403EC000u) +/** Peripheral BEE base pointer */ +#define BEE ((BEE_Type *)BEE_BASE) +/** Array initializer of BEE peripheral base addresses */ +#define BEE_BASE_ADDRS { BEE_BASE } +/** Array initializer of BEE peripheral base pointers */ +#define BEE_BASE_PTRS { BEE } + +/*! + * @} + */ /* end of group BEE_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1 Register..Control 1 register, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free Running Timer Register..Free Running Timer, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register..Rx 14 Mask register, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register..Rx 15 Mask register, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter Register..Error Counter, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1 Register..Error and Status 1 register, offset: 0x20 */ + __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register..Interrupt Masks 2 register, offset: 0x24 */ + __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register..Interrupt Masks 1 register, offset: 0x28 */ + __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register..Interrupt Flags 2 register, offset: 0x2C */ + __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register..Interrupt Flags 1 register, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2 Register..Control 2 register, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2 Register..Error and Status 2 register, offset: 0x38 */ + uint8_t RESERVED_1[8]; + __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register..Legacy Rx FIFO Global Mask register, offset: 0x48 */ + __I uint32_t RXFIR; /**< Rx FIFO Information Register..Legacy Rx FIFO Information Register, offset: 0x4C */ + __IO uint32_t CBT; /**< CAN Bit Timing Register, offset: 0x50 */ + uint8_t RESERVED_2[4]; + __I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */ + __I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */ + uint8_t RESERVED_3[32]; + union { /* offset: 0x80 */ + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD[2]; /**< Message Buffer 0 WORD_8B Register..Message Buffer 63 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */ + } MB_8B[64]; + struct { /* offset: 0x80, array step: 0x18 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 41 CS Register, array offset: 0x80, array step: 0x18 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 41 ID Register, array offset: 0x84, array step: 0x18 */ + __IO uint32_t WORD[4]; /**< Message Buffer 0 WORD_16B Register..Message Buffer 41 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */ + } MB_16B[42]; + struct { /* offset: 0x80, array step: 0x28 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 23 CS Register, array offset: 0x80, array step: 0x28 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 23 ID Register, array offset: 0x84, array step: 0x28 */ + __IO uint32_t WORD[8]; /**< Message Buffer 0 WORD_32B Register..Message Buffer 23 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */ + } MB_32B[24]; + struct { /* offset: 0x80, array step: 0x48 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 13 CS Register, array offset: 0x80, array step: 0x48 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 13 ID Register, array offset: 0x84, array step: 0x48 */ + __IO uint32_t WORD[16]; /**< Message Buffer 0 WORD_64B Register..Message Buffer 13 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */ + } MB_64B[14]; + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */ + __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */ + } MB[64]; + }; + uint8_t RESERVED_4[1024]; + __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_5[96]; + __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */ + uint8_t RESERVED_6[524]; + __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */ + __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */ + __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN bit Timing, offset: 0xBF8 */ + __IO uint32_t ETDC; /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */ + __IO uint32_t FDCTRL; /**< CAN FD Control Register, offset: 0xC00 */ + __IO uint32_t FDCBT; /**< CAN FD Bit Timing Register, offset: 0xC04 */ + __I uint32_t FDCRC; /**< CAN FD CRC Register, offset: 0xC08 */ + __IO uint32_t ERFCR; /**< Enhanced Rx FIFO Control Register, offset: 0xC0C */ + __IO uint32_t ERFIER; /**< Enhanced Rx FIFO Interrupt Enable register, offset: 0xC10 */ + __IO uint32_t ERFSR; /**< Enhanced Rx FIFO Status Register, offset: 0xC14 */ + uint8_t RESERVED_7[24]; + __I uint32_t HR_TIME_STAMP[64]; /**< High Resolution Time Stamp, array offset: 0xC30, array step: 0x4 */ + uint8_t RESERVED_8[8912]; + __IO uint32_t ERFFEL[128]; /**< Enhanced Rx FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration Register */ +/*! @{ */ +#define CAN_MCR_MAXMB_MASK (0x7FU) +#define CAN_MCR_MAXMB_SHIFT (0U) +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) +#define CAN_MCR_IDAM_MASK (0x300U) +#define CAN_MCR_IDAM_SHIFT (8U) +/*! IDAM - ID Acceptance Mode + * 0b00..Format A One full ID (standard or extended) per ID filter Table element. + * 0b01..Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element. + * 0b10..Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element. + * 0b11..Format D All frames rejected. + */ +#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) +#define CAN_MCR_FDEN_MASK (0x800U) +#define CAN_MCR_FDEN_SHIFT (11U) +/*! FDEN - CAN FD operation enable + * 0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats. + * 0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format. + */ +#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) +#define CAN_MCR_AEN_MASK (0x1000U) +#define CAN_MCR_AEN_SHIFT (12U) +/*! AEN - Abort Enable + * 0b1..Abort enabled + * 0b0..Abort disabled + */ +#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) +#define CAN_MCR_LPRIOEN_MASK (0x2000U) +#define CAN_MCR_LPRIOEN_SHIFT (13U) +/*! LPRIOEN - Local Priority Enable + * 0b1..Local Priority enabled + * 0b0..Local Priority disabled + */ +#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) +#define CAN_MCR_DMA_MASK (0x8000U) +#define CAN_MCR_DMA_SHIFT (15U) +/*! DMA - DMA Enable + * 0b0..DMA feature for Legacy RX FIFO or Enhanced Rx FIFO are disabled. + * 0b1..DMA feature for Legacy RX FIFO or Enhanced Rx FIFO are enabled. + */ +#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) +#define CAN_MCR_IRMQ_MASK (0x10000U) +#define CAN_MCR_IRMQ_SHIFT (16U) +/*! IRMQ - Individual Rx Masking And Queue Enable + * 0b1..Individual Rx masking and queue feature are enabled. + * 0b0..Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY. + */ +#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) +#define CAN_MCR_SRXDIS_MASK (0x20000U) +#define CAN_MCR_SRXDIS_SHIFT (17U) +/*! SRXDIS - Self Reception Disable + * 0b1..Self reception disabled + * 0b0..Self reception enabled + */ +#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) +#define CAN_MCR_DOZE_MASK (0x40000U) +#define CAN_MCR_DOZE_SHIFT (18U) +/*! DOZE - Doze Mode Enable + * 0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested. + * 0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested. + */ +#define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK) +#define CAN_MCR_WAKSRC_MASK (0x80000U) +#define CAN_MCR_WAKSRC_SHIFT (19U) +/*! WAKSRC - Wake Up Source + * 0b1..FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus + * 0b0..FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus. + */ +#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) +#define CAN_MCR_LPMACK_MASK (0x100000U) +#define CAN_MCR_LPMACK_SHIFT (20U) +/*! LPMACK - Low-Power Mode Acknowledge + * 0b1..FLEXCAN is either in Disable Mode, or Stop mode + * 0b0..FLEXCAN not in any of the low power modes + */ +#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) +#define CAN_MCR_WRNEN_MASK (0x200000U) +#define CAN_MCR_WRNEN_SHIFT (21U) +/*! WRNEN - Warning Interrupt Enable + * 0b1..TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96. + * 0b0..TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters. + */ +#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) +#define CAN_MCR_SLFWAK_MASK (0x400000U) +#define CAN_MCR_SLFWAK_SHIFT (22U) +/*! SLFWAK - Self Wake Up + * 0b1..FLEXCAN Self Wake Up feature is enabled + * 0b0..FLEXCAN Self Wake Up feature is disabled + */ +#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) +#define CAN_MCR_SUPV_MASK (0x800000U) +#define CAN_MCR_SUPV_SHIFT (23U) +/*! SUPV - Supervisor Mode + * 0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access + * behaves as though the access was done to an unimplemented register location + * 0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses + */ +#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) +#define CAN_MCR_FRZACK_MASK (0x1000000U) +#define CAN_MCR_FRZACK_SHIFT (24U) +/*! FRZACK - Freeze Mode Acknowledge + * 0b1..FLEXCAN in Freeze Mode, prescaler stopped + * 0b0..FLEXCAN not in Freeze Mode, prescaler running + */ +#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) +#define CAN_MCR_SOFTRST_MASK (0x2000000U) +#define CAN_MCR_SOFTRST_SHIFT (25U) +/*! SOFTRST - Soft Reset + * 0b1..Reset the registers + * 0b0..No reset request + */ +#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) +#define CAN_MCR_WAKMSK_MASK (0x4000000U) +#define CAN_MCR_WAKMSK_SHIFT (26U) +/*! WAKMSK - Wake Up Interrupt Mask + * 0b1..Wake Up Interrupt is enabled + * 0b0..Wake Up Interrupt is disabled + */ +#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) +#define CAN_MCR_NOTRDY_MASK (0x8000000U) +#define CAN_MCR_NOTRDY_SHIFT (27U) +/*! NOTRDY - FlexCAN Not Ready + * 0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode + * 0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode + */ +#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) +#define CAN_MCR_HALT_MASK (0x10000000U) +#define CAN_MCR_HALT_SHIFT (28U) +/*! HALT - Halt FlexCAN + * 0b1..Enters Freeze Mode if the FRZ bit is asserted. + * 0b0..No Freeze Mode request. + */ +#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) +#define CAN_MCR_RFEN_MASK (0x20000000U) +#define CAN_MCR_RFEN_SHIFT (29U) +/*! RFEN - Legacy Rx FIFO Enable + * 0b1..FIFO enabled + * 0b0..FIFO not enabled + */ +#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) +#define CAN_MCR_FRZ_MASK (0x40000000U) +#define CAN_MCR_FRZ_SHIFT (30U) +/*! FRZ - Freeze Enable + * 0b1..Enabled to enter Freeze Mode + * 0b0..Not enabled to enter Freeze Mode + */ +#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) +#define CAN_MCR_MDIS_MASK (0x80000000U) +#define CAN_MCR_MDIS_SHIFT (31U) +/*! MDIS - Module Disable + * 0b1..Disable the FLEXCAN module + * 0b0..Enable the FLEXCAN module + */ +#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) +/*! @} */ + +/*! @name CTRL1 - Control 1 Register..Control 1 register */ +/*! @{ */ +#define CAN_CTRL1_PROPSEG_MASK (0x7U) +#define CAN_CTRL1_PROPSEG_SHIFT (0U) +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) +#define CAN_CTRL1_LOM_MASK (0x8U) +#define CAN_CTRL1_LOM_SHIFT (3U) +/*! LOM - Listen-Only Mode + * 0b1..FLEXCAN module operates in Listen Only Mode + * 0b0..Listen Only Mode is deactivated + */ +#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) +#define CAN_CTRL1_LBUF_MASK (0x10U) +#define CAN_CTRL1_LBUF_SHIFT (4U) +/*! LBUF - Lowest Buffer Transmitted First + * 0b1..Lowest number buffer is transmitted first + * 0b0..Buffer with highest priority is transmitted first + */ +#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) +#define CAN_CTRL1_TSYN_MASK (0x20U) +#define CAN_CTRL1_TSYN_SHIFT (5U) +/*! TSYN - Timer Sync + * 0b1..Timer Sync feature enabled + * 0b0..Timer Sync feature disabled + */ +#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) +#define CAN_CTRL1_BOFFREC_MASK (0x40U) +#define CAN_CTRL1_BOFFREC_SHIFT (6U) +/*! BOFFREC - Bus Off Recovery + * 0b1..Automatic recovering from Bus Off state disabled + * 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B + */ +#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) +#define CAN_CTRL1_SMP_MASK (0x80U) +#define CAN_CTRL1_SMP_SHIFT (7U) +/*! SMP - CAN Bit Sampling + * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 + * preceding samples, a majority rule is used + * 0b0..Just one sample is used to determine the bit value + */ +#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) +#define CAN_CTRL1_RWRNMSK_MASK (0x400U) +#define CAN_CTRL1_RWRNMSK_SHIFT (10U) +/*! RWRNMSK - Rx Warning Interrupt Mask + * 0b1..Rx Warning Interrupt enabled + * 0b0..Rx Warning Interrupt disabled + */ +#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) +#define CAN_CTRL1_TWRNMSK_MASK (0x800U) +#define CAN_CTRL1_TWRNMSK_SHIFT (11U) +/*! TWRNMSK - Tx Warning Interrupt Mask + * 0b1..Tx Warning Interrupt enabled + * 0b0..Tx Warning Interrupt disabled + */ +#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) +#define CAN_CTRL1_LPB_MASK (0x1000U) +#define CAN_CTRL1_LPB_SHIFT (12U) +/*! LPB - Loop Back Mode + * 0b1..Loop Back enabled + * 0b0..Loop Back disabled + */ +#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) +#define CAN_CTRL1_CLKSRC_MASK (0x2000U) +#define CAN_CTRL1_CLKSRC_SHIFT (13U) +/*! CLKSRC - CAN Engine Clock Source + * 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. + * 0b1..The CAN engine clock source is the peripheral clock. + */ +#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK) +#define CAN_CTRL1_ERRMSK_MASK (0x4000U) +#define CAN_CTRL1_ERRMSK_SHIFT (14U) +/*! ERRMSK - Error Interrupt Mask + * 0b1..Error interrupt enabled + * 0b0..Error interrupt disabled + */ +#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) +#define CAN_CTRL1_BOFFMSK_MASK (0x8000U) +#define CAN_CTRL1_BOFFMSK_SHIFT (15U) +/*! BOFFMSK - Bus Off Interrupt Mask + * 0b1..Bus Off interrupt enabled + * 0b0..Bus Off interrupt disabled + */ +#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) +#define CAN_CTRL1_PSEG2_MASK (0x70000U) +#define CAN_CTRL1_PSEG2_SHIFT (16U) +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) +#define CAN_CTRL1_PSEG1_MASK (0x380000U) +#define CAN_CTRL1_PSEG1_SHIFT (19U) +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) +#define CAN_CTRL1_RJW_MASK (0xC00000U) +#define CAN_CTRL1_RJW_SHIFT (22U) +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) +#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) +#define CAN_CTRL1_PRESDIV_SHIFT (24U) +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) +/*! @} */ + +/*! @name TIMER - Free Running Timer Register..Free Running Timer */ +/*! @{ */ +#define CAN_TIMER_TIMER_MASK (0xFFFFU) +#define CAN_TIMER_TIMER_SHIFT (0U) +#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) +/*! @} */ + +/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */ +/*! @{ */ +#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) +#define CAN_RXMGMASK_MG_SHIFT (0U) +/*! MG - Rx Mailboxes Global Mask Bits + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked against the one received + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ +#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) +/*! @} */ + +/*! @name RX14MASK - Rx Buffer 14 Mask Register..Rx 14 Mask register */ +/*! @{ */ +#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) +#define CAN_RX14MASK_RX14M_SHIFT (0U) +/*! RX14M - Rx Buffer 14 Mask Bits + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ +#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) +/*! @} */ + +/*! @name RX15MASK - Rx Buffer 15 Mask Register..Rx 15 Mask register */ +/*! @{ */ +#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) +#define CAN_RX15MASK_RX15M_SHIFT (0U) +/*! RX15M - Rx Buffer 15 Mask Bits + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ +#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) +/*! @} */ + +/*! @name ECR - Error Counter Register..Error Counter */ +/*! @{ */ +#define CAN_ECR_TXERRCNT_MASK (0xFFU) +#define CAN_ECR_TXERRCNT_SHIFT (0U) +#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) +#define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU) +#define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U) +#define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK) +#define CAN_ECR_RXERRCNT_MASK (0xFF00U) +#define CAN_ECR_RXERRCNT_SHIFT (8U) +#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) +#define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U) +#define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U) +#define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK) +#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) +#define CAN_ECR_TXERRCNT_FAST_SHIFT (16U) +#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK) +#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) +#define CAN_ECR_RXERRCNT_FAST_SHIFT (24U) +#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK) +/*! @} */ + +/*! @name ESR1 - Error and Status 1 Register..Error and Status 1 register */ +/*! @{ */ +#define CAN_ESR1_WAKINT_MASK (0x1U) +#define CAN_ESR1_WAKINT_SHIFT (0U) +/*! WAKINT - Wake-Up Interrupt + * 0b1..Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode + * 0b0..No such occurrence + */ +#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) +#define CAN_ESR1_ERRINT_MASK (0x2U) +#define CAN_ESR1_ERRINT_SHIFT (1U) +/*! ERRINT - Error Interrupt + * 0b1..Indicates setting of any Error Bit in the Error and Status Register + * 0b0..No such occurrence + */ +#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) +#define CAN_ESR1_BOFFINT_MASK (0x4U) +#define CAN_ESR1_BOFFINT_SHIFT (2U) +/*! BOFFINT - Bus Off Interrupt + * 0b1..FLEXCAN module entered 'Bus Off' state + * 0b0..No such occurrence + */ +#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) +#define CAN_ESR1_RX_MASK (0x8U) +#define CAN_ESR1_RX_SHIFT (3U) +/*! RX - FlexCAN In Reception + * 0b1..FLEXCAN is transmitting a message + * 0b0..FLEXCAN is receiving a message + */ +#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) +#define CAN_ESR1_FLTCONF_MASK (0x30U) +#define CAN_ESR1_FLTCONF_SHIFT (4U) +/*! FLTCONF - Fault Confinement State + * 0b00..Error Active + * 0b01..Error Passive + * 0b1x..Bus off + */ +#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) +#define CAN_ESR1_TX_MASK (0x40U) +#define CAN_ESR1_TX_SHIFT (6U) +/*! TX - FlexCAN In Transmission + * 0b1..FLEXCAN is transmitting a message + * 0b0..FLEXCAN is receiving a message + */ +#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) +#define CAN_ESR1_IDLE_MASK (0x80U) +#define CAN_ESR1_IDLE_SHIFT (7U) +/*! IDLE - IDLE + * 0b1..CAN bus is now IDLE + * 0b0..No such occurrence + */ +#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) +#define CAN_ESR1_RXWRN_MASK (0x100U) +#define CAN_ESR1_RXWRN_SHIFT (8U) +/*! RXWRN - Rx Error Warning + * 0b1..Rx_Err_Counter >= 96 + * 0b0..No such occurrence + */ +#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) +#define CAN_ESR1_TXWRN_MASK (0x200U) +#define CAN_ESR1_TXWRN_SHIFT (9U) +/*! TXWRN - TX Error Warning + * 0b1..TX_Err_Counter >= 96 + * 0b0..No such occurrence + */ +#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) +#define CAN_ESR1_STFERR_MASK (0x400U) +#define CAN_ESR1_STFERR_SHIFT (10U) +/*! STFERR - Stuffing Error + * 0b1..A Stuffing Error occurred since last read of this register. + * 0b0..No such occurrence. + */ +#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) +#define CAN_ESR1_FRMERR_MASK (0x800U) +#define CAN_ESR1_FRMERR_SHIFT (11U) +/*! FRMERR - Form Error + * 0b1..A Form Error occurred since last read of this register + * 0b0..No such occurrence + */ +#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) +#define CAN_ESR1_CRCERR_MASK (0x1000U) +#define CAN_ESR1_CRCERR_SHIFT (12U) +/*! CRCERR - Cyclic Redundancy Check Error + * 0b1..A CRC error occurred since last read of this register. + * 0b0..No such occurrence + */ +#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) +#define CAN_ESR1_ACKERR_MASK (0x2000U) +#define CAN_ESR1_ACKERR_SHIFT (13U) +/*! ACKERR - Acknowledge Error + * 0b1..An ACK error occurred since last read of this register + * 0b0..No such occurrence + */ +#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) +#define CAN_ESR1_BIT0ERR_MASK (0x4000U) +#define CAN_ESR1_BIT0ERR_SHIFT (14U) +/*! BIT0ERR - Bit0 Error + * 0b1..At least one bit sent as dominant is received as recessive + * 0b0..No such occurrence + */ +#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) +#define CAN_ESR1_BIT1ERR_MASK (0x8000U) +#define CAN_ESR1_BIT1ERR_SHIFT (15U) +/*! BIT1ERR - Bit1 Error + * 0b1..At least one bit sent as recessive is received as dominant + * 0b0..No such occurrence + */ +#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) +#define CAN_ESR1_RWRNINT_MASK (0x10000U) +#define CAN_ESR1_RWRNINT_SHIFT (16U) +/*! RWRNINT - Rx Warning Interrupt Flag + * 0b1..The Rx error counter transition from < 96 to >= 96 + * 0b0..No such occurrence + */ +#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) +#define CAN_ESR1_TWRNINT_MASK (0x20000U) +#define CAN_ESR1_TWRNINT_SHIFT (17U) +/*! TWRNINT - Tx Warning Interrupt Flag + * 0b1..The Tx error counter transition from < 96 to >= 96 + * 0b0..No such occurrence + */ +#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) +#define CAN_ESR1_SYNCH_MASK (0x40000U) +#define CAN_ESR1_SYNCH_SHIFT (18U) +/*! SYNCH - CAN Synchronization Status + * 0b1..FlexCAN is synchronized to the CAN bus + * 0b0..FlexCAN is not synchronized to the CAN bus + */ +#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) +#define CAN_ESR1_BOFFDONEINT_MASK (0x80000U) +#define CAN_ESR1_BOFFDONEINT_SHIFT (19U) +/*! BOFFDONEINT - Bus Off Done Interrupt + * 0b0..No such occurrence. + * 0b1..FlexCAN module has completed Bus Off process. + */ +#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) +#define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) +#define CAN_ESR1_ERRINT_FAST_SHIFT (20U) +/*! ERRINT_FAST - Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set + * 0b0..No such occurrence. + * 0b1..Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set. + */ +#define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK) +#define CAN_ESR1_ERROVR_MASK (0x200000U) +#define CAN_ESR1_ERROVR_SHIFT (21U) +/*! ERROVR - Error Overrun bit + * 0b0..Overrun has not occurred. + * 0b1..Overrun has occurred. + */ +#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) +#define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) +#define CAN_ESR1_STFERR_FAST_SHIFT (26U) +/*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set + * 0b0..No such occurrence. + * 0b1..A Stuffing Error occurred since last read of this register. + */ +#define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK) +#define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) +#define CAN_ESR1_FRMERR_FAST_SHIFT (27U) +/*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set + * 0b0..No such occurrence. + * 0b1..A Form Error occurred since last read of this register. + */ +#define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK) +#define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) +#define CAN_ESR1_CRCERR_FAST_SHIFT (28U) +/*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set + * 0b0..No such occurrence. + * 0b1..A CRC error occurred since last read of this register. + */ +#define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK) +#define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) +#define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) +/*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set + * 0b0..No such occurrence. + * 0b1..At least one bit sent as dominant is received as recessive. + */ +#define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) +#define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) +#define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) +/*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set + * 0b0..No such occurrence. + * 0b1..At least one bit sent as recessive is received as dominant. + */ +#define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK) +/*! @} */ + +/*! @name IMASK2 - Interrupt Masks 2 Register..Interrupt Masks 2 register */ +/*! @{ */ +#define CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU) +#define CAN_IMASK2_BUF63TO32M_SHIFT (0U) +#define CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK) +#define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU) +#define CAN_IMASK2_BUFHM_SHIFT (0U) +/*! BUFHM + * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled + * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled + */ +#define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK) +/*! @} */ + +/*! @name IMASK1 - Interrupt Masks 1 Register..Interrupt Masks 1 register */ +/*! @{ */ +#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) +#define CAN_IMASK1_BUF31TO0M_SHIFT (0U) +#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK) +#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU) +#define CAN_IMASK1_BUFLM_SHIFT (0U) +/*! BUFLM + * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled + * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled + */ +#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK) +/*! @} */ + +/*! @name IFLAG2 - Interrupt Flags 2 Register..Interrupt Flags 2 register */ +/*! @{ */ +#define CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU) +#define CAN_IFLAG2_BUF63TO32I_SHIFT (0U) +#define CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK) +#define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU) +#define CAN_IFLAG2_BUFHI_SHIFT (0U) +/*! BUFHI + * 0b00000000000000000000000000000001..The corresponding buffer has successfully completed transmission or reception + * 0b00000000000000000000000000000000..No such occurrence + */ +#define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK) +/*! @} */ + +/*! @name IFLAG1 - Interrupt Flags 1 Register..Interrupt Flags 1 register */ +/*! @{ */ +#define CAN_IFLAG1_BUF0I_MASK (0x1U) +#define CAN_IFLAG1_BUF0I_SHIFT (0U) +/*! BUF0I - Buffer MB0 Interrupt Or Clear Legacy FIFO bit + * 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when CAN_MCR[RFEN]=0. + * 0b1..The corresponding buffer has successfully completed transmission or reception when CAN_MCR[RFEN]=0. + */ +#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) +#define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU) +#define CAN_IFLAG1_BUF4TO0I_SHIFT (0U) +/*! BUF4TO0I + * 0b00001..Corresponding MB completed transmission/reception + * 0b00000..No such occurrence + */ +#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK) +#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) +#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) +#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) +#define CAN_IFLAG1_BUF5I_MASK (0x20U) +#define CAN_IFLAG1_BUF5I_SHIFT (5U) +/*! BUF5I - Buffer MB5 Interrupt Or "Frames available in Legacy Rx FIFO" + * 0b1..MB5 completed transmission/reception or frames available in the FIFO + * 0b0..No such occurrence + */ +#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) +#define CAN_IFLAG1_BUF6I_MASK (0x40U) +#define CAN_IFLAG1_BUF6I_SHIFT (6U) +/*! BUF6I - Buffer MB6 Interrupt Or "Legacy Rx FIFO Warning" + * 0b1..MB6 completed transmission/reception or FIFO almost full + * 0b0..No such occurrence + */ +#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) +#define CAN_IFLAG1_BUF7I_MASK (0x80U) +#define CAN_IFLAG1_BUF7I_SHIFT (7U) +/*! BUF7I - Buffer MB7 Interrupt Or "Legacy Rx FIFO Overflow" + * 0b1..MB7 completed transmission/reception or FIFO overflow + * 0b0..No such occurrence + */ +#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) +#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) +#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +/*! BUF31TO8I - Buffer MBi Interrupt + * 0b000000000000000000000001..The corresponding MB has successfully completed transmission or reception + * 0b000000000000000000000000..No such occurrence + */ +#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 Register..Control 2 register */ +/*! @{ */ +#define CAN_CTRL2_TSTAMPCAP_MASK (0xC0U) +#define CAN_CTRL2_TSTAMPCAP_SHIFT (6U) +/*! TSTAMPCAP - Time Stamp Capture Point + * 0b00..The high resolution time stamp capture is disabled + * 0b01..The high resolution time stamp is captured in the end of the CAN frame + * 0b10..The high resolution time stamp is captured in the start of the CAN frame + * 0b11..The high resolution time stamp is captured in the start of frame for classical CAN frames and in res bit for CAN FD frames + */ +#define CAN_CTRL2_TSTAMPCAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TSTAMPCAP_SHIFT)) & CAN_CTRL2_TSTAMPCAP_MASK) +#define CAN_CTRL2_MBTSBASE_MASK (0x300U) +#define CAN_CTRL2_MBTSBASE_SHIFT (8U) +/*! MBTSBASE - Message Buffer Time Stamp Base + * 0b00..Message Buffer Time Stamp base is CAN_TIMER + * 0b01..Message Buffer Time Stamp base is lower 16-bits of high resolution timer + * 0b10..Message Buffer Time Stamp base is upper 16-bits of high resolution timerT + * 0b11..Reserved. + */ +#define CAN_CTRL2_MBTSBASE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MBTSBASE_SHIFT)) & CAN_CTRL2_MBTSBASE_MASK) +#define CAN_CTRL2_EDFLTDIS_MASK (0x800U) +#define CAN_CTRL2_EDFLTDIS_SHIFT (11U) +/*! EDFLTDIS - Edge Filter Disable + * 0b0..Edge Filter is enabled + * 0b1..Edge Filter is disabled + */ +#define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK) +#define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U) +#define CAN_CTRL2_ISOCANFDEN_SHIFT (12U) +/*! ISOCANFDEN - ISO CAN FD Enable + * 0b0..FlexCAN operates using the non-ISO CAN FD protocol. + * 0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1). + */ +#define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) +#define CAN_CTRL2_BTE_MASK (0x2000U) +#define CAN_CTRL2_BTE_SHIFT (13U) +/*! BTE - Bit Timing Expansion enable + * 0b0..CAN Bit timing expansion is disabled. + * 0b1..CAN bit timing expansion is enabled. + */ +#define CAN_CTRL2_BTE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK) +#define CAN_CTRL2_PREXCEN_MASK (0x4000U) +#define CAN_CTRL2_PREXCEN_SHIFT (14U) +/*! PREXCEN - Protocol Exception Enable + * 0b0..Protocol Exception is disabled. + * 0b1..Protocol Exception is enabled. + */ +#define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK) +#define CAN_CTRL2_TIMER_SRC_MASK (0x8000U) +#define CAN_CTRL2_TIMER_SRC_SHIFT (15U) +/*! TIMER_SRC - Timer Source + * 0b0..The Free Running Timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus. + * 0b1..The Free Running Timer is clocked by an external time tick. The period can be either adjusted to be equal + * to the baud rate on the CAN bus, or a different value as required. See the device specific section for + * details about the external time tick. + */ +#define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK) +#define CAN_CTRL2_EACEN_MASK (0x10000U) +#define CAN_CTRL2_EACEN_SHIFT (16U) +/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes + * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within + * the incoming frame. Mask bits do apply. + * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. + */ +#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) +#define CAN_CTRL2_RRS_MASK (0x20000U) +#define CAN_CTRL2_RRS_SHIFT (17U) +/*! RRS - Remote Request Storing + * 0b1..Remote Request Frame is stored + * 0b0..Remote Response Frame is generated + */ +#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) +#define CAN_CTRL2_MRP_MASK (0x40000U) +#define CAN_CTRL2_MRP_SHIFT (18U) +/*! MRP - Mailboxes Reception Priority + * 0b1..Matching starts from Mailboxes and continues on Rx FIFO + * 0b0..Matching starts from Rx FIFO and continues on Mailboxes + */ +#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) +#define CAN_CTRL2_TASD_MASK (0xF80000U) +#define CAN_CTRL2_TASD_SHIFT (19U) +#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) +#define CAN_CTRL2_RFFN_MASK (0xF000000U) +#define CAN_CTRL2_RFFN_SHIFT (24U) +#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) +#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) +#define CAN_CTRL2_WRMFRZ_SHIFT (28U) +/*! WRMFRZ + * 0b1..Enable unrestricted write access to FlexCAN memory + * 0b0..Keep the write access restricted in some regions of FlexCAN memory + */ +#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) +#define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) +#define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) +/*! BOFFDONEMSK - Bus Off Done Interrupt Mask + * 0b0..Bus Off Done interrupt disabled. + * 0b1..Bus Off Done interrupt enabled. + */ +#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) +#define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) +#define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) +/*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames + * 0b0..ERRINT_FAST Error interrupt disabled. + * 0b1..ERRINT_FAST Error interrupt enabled. + */ +#define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK) +/*! @} */ + +/*! @name ESR2 - Error and Status 2 Register..Error and Status 2 register */ +/*! @{ */ +#define CAN_ESR2_IMB_MASK (0x2000U) +#define CAN_ESR2_IMB_SHIFT (13U) +/*! IMB - Inactive Mailbox + * 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. + * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. + */ +#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) +#define CAN_ESR2_VPS_MASK (0x4000U) +#define CAN_ESR2_VPS_SHIFT (14U) +/*! VPS - Valid Priority Status + * 0b1..Contents of IMB and LPTM are valid + * 0b0..Contents of IMB and LPTM are invalid + */ +#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) +#define CAN_ESR2_LPTM_MASK (0x7F0000U) +#define CAN_ESR2_LPTM_SHIFT (16U) +#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) +/*! @} */ + +/*! @name CRCR - CRC Register */ +/*! @{ */ +#define CAN_CRCR_TXCRC_MASK (0x7FFFU) +#define CAN_CRCR_TXCRC_SHIFT (0U) +#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) +#define CAN_CRCR_MBCRC_MASK (0x7F0000U) +#define CAN_CRCR_MBCRC_SHIFT (16U) +#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) +/*! @} */ + +/*! @name RXFGMASK - Rx FIFO Global Mask Register..Legacy Rx FIFO Global Mask register */ +/*! @{ */ +#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) +#define CAN_RXFGMASK_FGM_SHIFT (0U) +/*! FGM - Legacy Rx FIFO Global Mask Bits + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care" + */ +#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) +/*! @} */ + +/*! @name RXFIR - Rx FIFO Information Register..Legacy Rx FIFO Information Register */ +/*! @{ */ +#define CAN_RXFIR_IDHIT_MASK (0x1FFU) +#define CAN_RXFIR_IDHIT_SHIFT (0U) +#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) +/*! @} */ + +/*! @name CBT - CAN Bit Timing Register */ +/*! @{ */ +#define CAN_CBT_EPSEG2_MASK (0x1FU) +#define CAN_CBT_EPSEG2_SHIFT (0U) +#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK) +#define CAN_CBT_EPSEG1_MASK (0x3E0U) +#define CAN_CBT_EPSEG1_SHIFT (5U) +#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK) +#define CAN_CBT_EPROPSEG_MASK (0xFC00U) +#define CAN_CBT_EPROPSEG_SHIFT (10U) +#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK) +#define CAN_CBT_ERJW_MASK (0x1F0000U) +#define CAN_CBT_ERJW_SHIFT (16U) +#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) +#define CAN_CBT_EPRESDIV_MASK (0x7FE00000U) +#define CAN_CBT_EPRESDIV_SHIFT (21U) +#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) +#define CAN_CBT_BTF_MASK (0x80000000U) +#define CAN_CBT_BTF_SHIFT (31U) +/*! BTF - Bit Timing Format Enable + * 0b0..Extended bit time definitions disabled. + * 0b1..Extended bit time definitions enabled. + */ +#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) +/*! @} */ + +/*! @name DBG1 - Debug 1 register */ +/*! @{ */ +#define CAN_DBG1_CFSM_MASK (0x3FU) +#define CAN_DBG1_CFSM_SHIFT (0U) +#define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK) +#define CAN_DBG1_CBN_MASK (0x1F000000U) +#define CAN_DBG1_CBN_SHIFT (24U) +#define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK) +/*! @} */ + +/*! @name DBG2 - Debug 2 register */ +/*! @{ */ +#define CAN_DBG2_RMP_MASK (0x7FU) +#define CAN_DBG2_RMP_SHIFT (0U) +#define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK) +#define CAN_DBG2_MPP_MASK (0x80U) +#define CAN_DBG2_MPP_SHIFT (7U) +/*! MPP - Matching Process in Progress + * 0b0..No matching process ongoing. + * 0b1..Matching process is in progress. + */ +#define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK) +#define CAN_DBG2_TAP_MASK (0x7F00U) +#define CAN_DBG2_TAP_SHIFT (8U) +#define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK) +#define CAN_DBG2_APP_MASK (0x8000U) +#define CAN_DBG2_APP_SHIFT (15U) +/*! APP - Arbitration Process in Progress + * 0b0..No matching process ongoing. + * 0b1..Matching process is in progress. + */ +#define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK) +/*! @} */ + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB8B (64U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB8B (64U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB8B (64U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB8B2 (2U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB16B (42U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB16B (42U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB16B (42U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB16B2 (4U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB32B (24U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB32B (24U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB32B (24U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB32B2 (8U) + +/*! @name CS - Message Buffer 0 CS Register..Message Buffer 13 CS Register */ +/*! @{ */ +#define CAN_CS_TIME_STAMP_MASK (0xFFFFU) +#define CAN_CS_TIME_STAMP_SHIFT (0U) +#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) +#define CAN_CS_DLC_MASK (0xF0000U) +#define CAN_CS_DLC_SHIFT (16U) +#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) +#define CAN_CS_RTR_MASK (0x100000U) +#define CAN_CS_RTR_SHIFT (20U) +#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) +#define CAN_CS_IDE_MASK (0x200000U) +#define CAN_CS_IDE_SHIFT (21U) +#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) +#define CAN_CS_SRR_MASK (0x400000U) +#define CAN_CS_SRR_SHIFT (22U) +#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) +#define CAN_CS_CODE_MASK (0xF000000U) +#define CAN_CS_CODE_SHIFT (24U) +#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) +#define CAN_CS_ESI_MASK (0x20000000U) +#define CAN_CS_ESI_SHIFT (29U) +#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK) +#define CAN_CS_BRS_MASK (0x40000000U) +#define CAN_CS_BRS_SHIFT (30U) +#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK) +#define CAN_CS_EDL_MASK (0x80000000U) +#define CAN_CS_EDL_SHIFT (31U) +#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK) +/*! @} */ + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB64B (14U) + +/*! @name ID - Message Buffer 0 ID Register..Message Buffer 13 ID Register */ +/*! @{ */ +#define CAN_ID_EXT_MASK (0x3FFFFU) +#define CAN_ID_EXT_SHIFT (0U) +#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) +#define CAN_ID_STD_MASK (0x1FFC0000U) +#define CAN_ID_STD_SHIFT (18U) +#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) +#define CAN_ID_PRIO_MASK (0xE0000000U) +#define CAN_ID_PRIO_SHIFT (29U) +#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) +/*! @} */ + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB64B (14U) + +/*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 13 WORD_64B Register */ +/*! @{ */ +#define CAN_WORD_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_3_SHIFT (0U) +#define CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK) +#define CAN_WORD_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_7_SHIFT (0U) +#define CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK) +#define CAN_WORD_DATA_BYTE_11_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_11_SHIFT (0U) +#define CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK) +#define CAN_WORD_DATA_BYTE_15_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_15_SHIFT (0U) +#define CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK) +#define CAN_WORD_DATA_BYTE_19_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_19_SHIFT (0U) +#define CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK) +#define CAN_WORD_DATA_BYTE_23_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_23_SHIFT (0U) +#define CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK) +#define CAN_WORD_DATA_BYTE_27_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_27_SHIFT (0U) +#define CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK) +#define CAN_WORD_DATA_BYTE_31_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_31_SHIFT (0U) +#define CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK) +#define CAN_WORD_DATA_BYTE_35_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_35_SHIFT (0U) +#define CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK) +#define CAN_WORD_DATA_BYTE_39_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_39_SHIFT (0U) +#define CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK) +#define CAN_WORD_DATA_BYTE_43_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_43_SHIFT (0U) +#define CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK) +#define CAN_WORD_DATA_BYTE_47_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_47_SHIFT (0U) +#define CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK) +#define CAN_WORD_DATA_BYTE_51_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_51_SHIFT (0U) +#define CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK) +#define CAN_WORD_DATA_BYTE_55_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_55_SHIFT (0U) +#define CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK) +#define CAN_WORD_DATA_BYTE_59_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_59_SHIFT (0U) +#define CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK) +#define CAN_WORD_DATA_BYTE_63_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_63_SHIFT (0U) +#define CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK) +#define CAN_WORD_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_2_SHIFT (8U) +#define CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK) +#define CAN_WORD_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_6_SHIFT (8U) +#define CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK) +#define CAN_WORD_DATA_BYTE_10_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_10_SHIFT (8U) +#define CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK) +#define CAN_WORD_DATA_BYTE_14_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_14_SHIFT (8U) +#define CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK) +#define CAN_WORD_DATA_BYTE_18_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_18_SHIFT (8U) +#define CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK) +#define CAN_WORD_DATA_BYTE_22_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_22_SHIFT (8U) +#define CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK) +#define CAN_WORD_DATA_BYTE_26_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_26_SHIFT (8U) +#define CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK) +#define CAN_WORD_DATA_BYTE_30_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_30_SHIFT (8U) +#define CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK) +#define CAN_WORD_DATA_BYTE_34_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_34_SHIFT (8U) +#define CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK) +#define CAN_WORD_DATA_BYTE_38_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_38_SHIFT (8U) +#define CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK) +#define CAN_WORD_DATA_BYTE_42_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_42_SHIFT (8U) +#define CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK) +#define CAN_WORD_DATA_BYTE_46_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_46_SHIFT (8U) +#define CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK) +#define CAN_WORD_DATA_BYTE_50_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_50_SHIFT (8U) +#define CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK) +#define CAN_WORD_DATA_BYTE_54_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_54_SHIFT (8U) +#define CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK) +#define CAN_WORD_DATA_BYTE_58_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_58_SHIFT (8U) +#define CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK) +#define CAN_WORD_DATA_BYTE_62_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_62_SHIFT (8U) +#define CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK) +#define CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_1_SHIFT (16U) +#define CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK) +#define CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_5_SHIFT (16U) +#define CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK) +#define CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_9_SHIFT (16U) +#define CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK) +#define CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_13_SHIFT (16U) +#define CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK) +#define CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_17_SHIFT (16U) +#define CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK) +#define CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_21_SHIFT (16U) +#define CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK) +#define CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_25_SHIFT (16U) +#define CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK) +#define CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_29_SHIFT (16U) +#define CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK) +#define CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_33_SHIFT (16U) +#define CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK) +#define CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_37_SHIFT (16U) +#define CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK) +#define CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_41_SHIFT (16U) +#define CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK) +#define CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_45_SHIFT (16U) +#define CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK) +#define CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_49_SHIFT (16U) +#define CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK) +#define CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_53_SHIFT (16U) +#define CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK) +#define CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_57_SHIFT (16U) +#define CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK) +#define CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_61_SHIFT (16U) +#define CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK) +#define CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_0_SHIFT (24U) +#define CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK) +#define CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_4_SHIFT (24U) +#define CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK) +#define CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_8_SHIFT (24U) +#define CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK) +#define CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_12_SHIFT (24U) +#define CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK) +#define CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_16_SHIFT (24U) +#define CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK) +#define CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_20_SHIFT (24U) +#define CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK) +#define CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_24_SHIFT (24U) +#define CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK) +#define CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_28_SHIFT (24U) +#define CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK) +#define CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_32_SHIFT (24U) +#define CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK) +#define CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_36_SHIFT (24U) +#define CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK) +#define CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_40_SHIFT (24U) +#define CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK) +#define CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_44_SHIFT (24U) +#define CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK) +#define CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_48_SHIFT (24U) +#define CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK) +#define CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_52_SHIFT (24U) +#define CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK) +#define CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_56_SHIFT (24U) +#define CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK) +#define CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_60_SHIFT (24U) +#define CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK) +/*! @} */ + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB64B (14U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB64B2 (16U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT (64U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT (64U) + +/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */ +/*! @{ */ +#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) +#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) +#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) +#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) +#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) +#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) +#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) +#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) +/*! @} */ + +/* The count of CAN_WORD0 */ +#define CAN_WORD0_COUNT (64U) + +/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */ +/*! @{ */ +#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) +#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) +#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) +#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) +#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) +#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) +#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) +#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) +/*! @} */ + +/* The count of CAN_WORD1 */ +#define CAN_WORD1_COUNT (64U) + +/*! @name RXIMR - Rx Individual Mask Registers */ +/*! @{ */ +#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) +#define CAN_RXIMR_MI_SHIFT (0U) +/*! MI - Individual Mask Bits + * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked + * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care" + */ +#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) +/*! @} */ + +/* The count of CAN_RXIMR */ +#define CAN_RXIMR_COUNT (64U) + +/*! @name GFWR - Glitch Filter Width Registers */ +/*! @{ */ +#define CAN_GFWR_GFWR_MASK (0xFFU) +#define CAN_GFWR_GFWR_SHIFT (0U) +#define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK) +/*! @} */ + +/*! @name EPRS - Enhanced CAN Bit Timing Prescalers */ +/*! @{ */ +#define CAN_EPRS_ENPRESDIV_MASK (0x3FFU) +#define CAN_EPRS_ENPRESDIV_SHIFT (0U) +#define CAN_EPRS_ENPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK) +#define CAN_EPRS_EDPRESDIV_MASK (0x3FF0000U) +#define CAN_EPRS_EDPRESDIV_SHIFT (16U) +#define CAN_EPRS_EDPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK) +/*! @} */ + +/*! @name ENCBT - Enhanced Nominal CAN Bit Timing */ +/*! @{ */ +#define CAN_ENCBT_NTSEG1_MASK (0xFFU) +#define CAN_ENCBT_NTSEG1_SHIFT (0U) +#define CAN_ENCBT_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK) +#define CAN_ENCBT_NTSEG2_MASK (0x7F000U) +#define CAN_ENCBT_NTSEG2_SHIFT (12U) +#define CAN_ENCBT_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK) +#define CAN_ENCBT_NRJW_MASK (0x1FC00000U) +#define CAN_ENCBT_NRJW_SHIFT (22U) +#define CAN_ENCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK) +/*! @} */ + +/*! @name EDCBT - Enhanced Data Phase CAN bit Timing */ +/*! @{ */ +#define CAN_EDCBT_DTSEG1_MASK (0x1FU) +#define CAN_EDCBT_DTSEG1_SHIFT (0U) +#define CAN_EDCBT_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK) +#define CAN_EDCBT_DTSEG2_MASK (0xF000U) +#define CAN_EDCBT_DTSEG2_SHIFT (12U) +#define CAN_EDCBT_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK) +#define CAN_EDCBT_DRJW_MASK (0x3C00000U) +#define CAN_EDCBT_DRJW_SHIFT (22U) +#define CAN_EDCBT_DRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK) +/*! @} */ + +/*! @name ETDC - Enhanced Transceiver Delay Compensation */ +/*! @{ */ +#define CAN_ETDC_ETDCVAL_MASK (0xFFU) +#define CAN_ETDC_ETDCVAL_SHIFT (0U) +#define CAN_ETDC_ETDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK) +#define CAN_ETDC_ETDCOFF_MASK (0x7F0000U) +#define CAN_ETDC_ETDCOFF_SHIFT (16U) +#define CAN_ETDC_ETDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK) +#define CAN_ETDC_TDMDIS_MASK (0x80000000U) +#define CAN_ETDC_TDMDIS_SHIFT (31U) +/*! TDMDIS - Transceiver Delay Measurement Disable + * 0b0..TDC measurement is enabled + * 0b1..TDC measurement is disabled + */ +#define CAN_ETDC_TDMDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK) +/*! @} */ + +/*! @name FDCTRL - CAN FD Control Register */ +/*! @{ */ +#define CAN_FDCTRL_TDCVAL_MASK (0x3FU) +#define CAN_FDCTRL_TDCVAL_SHIFT (0U) +#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK) +#define CAN_FDCTRL_TDCOFF_MASK (0x1F00U) +#define CAN_FDCTRL_TDCOFF_SHIFT (8U) +#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK) +#define CAN_FDCTRL_TDCFAIL_MASK (0x4000U) +#define CAN_FDCTRL_TDCFAIL_SHIFT (14U) +/*! TDCFAIL - Transceiver Delay Compensation Fail + * 0b0..Measured loop delay is in range. + * 0b1..Measured loop delay is out of range. + */ +#define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK) +#define CAN_FDCTRL_TDCEN_MASK (0x8000U) +#define CAN_FDCTRL_TDCEN_SHIFT (15U) +/*! TDCEN - Transceiver Delay Compensation Enable + * 0b0..TDC is disabled + * 0b1..TDC is enabled + */ +#define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK) +#define CAN_FDCTRL_MBDSR0_MASK (0x30000U) +#define CAN_FDCTRL_MBDSR0_SHIFT (16U) +/*! MBDSR0 - Message Buffer Data Size for Region 0 + * 0b00..Selects 8 bytes per Message Buffer. + * 0b01..Selects 16 bytes per Message Buffer. + * 0b10..Selects 32 bytes per Message Buffer. + * 0b11..Selects 64 bytes per Message Buffer. + */ +#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) +#define CAN_FDCTRL_MBDSR1_MASK (0x180000U) +#define CAN_FDCTRL_MBDSR1_SHIFT (19U) +/*! MBDSR1 - Message Buffer Data Size for Region 1 + * 0b00..Selects 8 bytes per Message Buffer. + * 0b01..Selects 16 bytes per Message Buffer. + * 0b10..Selects 32 bytes per Message Buffer. + * 0b11..Selects 64 bytes per Message Buffer. + */ +#define CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK) +#define CAN_FDCTRL_FDRATE_MASK (0x80000000U) +#define CAN_FDCTRL_FDRATE_SHIFT (31U) +/*! FDRATE - Bit Rate Switch Enable + * 0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect. + * 0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive. + */ +#define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK) +/*! @} */ + +/*! @name FDCBT - CAN FD Bit Timing Register */ +/*! @{ */ +#define CAN_FDCBT_FPSEG2_MASK (0x7U) +#define CAN_FDCBT_FPSEG2_SHIFT (0U) +#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK) +#define CAN_FDCBT_FPSEG1_MASK (0xE0U) +#define CAN_FDCBT_FPSEG1_SHIFT (5U) +#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK) +#define CAN_FDCBT_FPROPSEG_MASK (0x7C00U) +#define CAN_FDCBT_FPROPSEG_SHIFT (10U) +#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK) +#define CAN_FDCBT_FRJW_MASK (0x70000U) +#define CAN_FDCBT_FRJW_SHIFT (16U) +#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK) +#define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U) +#define CAN_FDCBT_FPRESDIV_SHIFT (20U) +#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK) +/*! @} */ + +/*! @name FDCRC - CAN FD CRC Register */ +/*! @{ */ +#define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) +#define CAN_FDCRC_FD_TXCRC_SHIFT (0U) +#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK) +#define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) +#define CAN_FDCRC_FD_MBCRC_SHIFT (24U) +#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) +/*! @} */ + +/*! @name ERFCR - Enhanced Rx FIFO Control Register */ +/*! @{ */ +#define CAN_ERFCR_ERFWM_MASK (0x1FU) +#define CAN_ERFCR_ERFWM_SHIFT (0U) +#define CAN_ERFCR_ERFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK) +#define CAN_ERFCR_NFE_MASK (0x3F00U) +#define CAN_ERFCR_NFE_SHIFT (8U) +#define CAN_ERFCR_NFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK) +#define CAN_ERFCR_NEXIF_MASK (0x7F0000U) +#define CAN_ERFCR_NEXIF_SHIFT (16U) +#define CAN_ERFCR_NEXIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK) +#define CAN_ERFCR_DMALW_MASK (0x7C000000U) +#define CAN_ERFCR_DMALW_SHIFT (26U) +#define CAN_ERFCR_DMALW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK) +#define CAN_ERFCR_ERFEN_MASK (0x80000000U) +#define CAN_ERFCR_ERFEN_SHIFT (31U) +/*! ERFEN - Enhanced Rx FIFO enable + * 0b0..Enhanced Rx FIFO is disabled + * 0b1..Enhanced Rx FIFO is enabled + */ +#define CAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK) +/*! @} */ + +/*! @name ERFIER - Enhanced Rx FIFO Interrupt Enable register */ +/*! @{ */ +#define CAN_ERFIER_ERFDAIE_MASK (0x10000000U) +#define CAN_ERFIER_ERFDAIE_SHIFT (28U) +/*! ERFDAIE - Enhanced Rx FIFO Data Available Interrupt Enable + * 0b0..Enhanced Rx FIFO Data Available Interrupt is disabled + * 0b1..Enhanced Rx FIFO Data Available Interrupt is enabled + */ +#define CAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK) +#define CAN_ERFIER_ERFWMIIE_MASK (0x20000000U) +#define CAN_ERFIER_ERFWMIIE_SHIFT (29U) +/*! ERFWMIIE - Enhanced Rx FIFO Watermark Indication Interrupt Enable + * 0b0..Enhanced Rx FIFO Watermark Interrupt is disabled + * 0b1..Enhanced Rx FIFO Watermark Interrupt is enabled + */ +#define CAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK) +#define CAN_ERFIER_ERFOVFIE_MASK (0x40000000U) +#define CAN_ERFIER_ERFOVFIE_SHIFT (30U) +/*! ERFOVFIE - Enhanced Rx FIFO Overflow Interrupt Enable + * 0b0..Enhanced Rx FIFO Overflow is disabled + * 0b1..Enhanced Rx FIFO Overflow is enabled + */ +#define CAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK) +#define CAN_ERFIER_ERFUFWIE_MASK (0x80000000U) +#define CAN_ERFIER_ERFUFWIE_SHIFT (31U) +/*! ERFUFWIE - Enhanced Rx FIFO Underflow Interrupt Enable + * 0b0..Enhanced Rx FIFO Underflow interrupt is disabled + * 0b1..Enhanced Rx FIFO Underflow interrupt is enabled + */ +#define CAN_ERFIER_ERFUFWIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK) +/*! @} */ + +/*! @name ERFSR - Enhanced Rx FIFO Status Register */ +/*! @{ */ +#define CAN_ERFSR_ERFEL_MASK (0x3FU) +#define CAN_ERFSR_ERFEL_SHIFT (0U) +#define CAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK) +#define CAN_ERFSR_ERFF_MASK (0x10000U) +#define CAN_ERFSR_ERFF_SHIFT (16U) +/*! ERFF - Enhanced Rx FIFO full + * 0b0..Enhanced Rx FIFO is not full + * 0b1..Enhanced Rx FIFO is full + */ +#define CAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK) +#define CAN_ERFSR_ERFE_MASK (0x20000U) +#define CAN_ERFSR_ERFE_SHIFT (17U) +/*! ERFE - Enhanced Rx FIFO empty + * 0b0..Enhanced Rx FIFO is not empty + * 0b1..Enhanced Rx FIFO is empty + */ +#define CAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK) +#define CAN_ERFSR_ERFCLR_MASK (0x8000000U) +#define CAN_ERFSR_ERFCLR_SHIFT (27U) +/*! ERFCLR - Enhanced Rx FIFO Clear + * 0b0..No effect + * 0b1..Clear Enhanced Rx FIFO content + */ +#define CAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK) +#define CAN_ERFSR_ERFDA_MASK (0x10000000U) +#define CAN_ERFSR_ERFDA_SHIFT (28U) +/*! ERFDA - Enhanced Rx FIFO Data Available + * 0b0..No such occurrence + * 0b1..There is at least one message stored in Enhanced Rx FIFO + */ +#define CAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK) +#define CAN_ERFSR_ERFWMI_MASK (0x20000000U) +#define CAN_ERFSR_ERFWMI_SHIFT (29U) +/*! ERFWMI - Enhanced Rx FIFO Watermark Indication + * 0b0..No such occurrence + * 0b1..The number of messages in FIFO is greater than the watermark + */ +#define CAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK) +#define CAN_ERFSR_ERFOVF_MASK (0x40000000U) +#define CAN_ERFSR_ERFOVF_SHIFT (30U) +/*! ERFOVF - Enhanced Rx FIFO Overflow + * 0b0..No such occurrence + * 0b1..Enhanced Rx FIFO overflow + */ +#define CAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK) +#define CAN_ERFSR_ERFUFW_MASK (0x80000000U) +#define CAN_ERFSR_ERFUFW_SHIFT (31U) +/*! ERFUFW - Enhanced Rx FIFO Underflow + * 0b0..No such occurrence + * 0b1..Enhanced Rx FIFO underflow + */ +#define CAN_ERFSR_ERFUFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK) +/*! @} */ + +/*! @name HR_TIME_STAMP - High Resolution Time Stamp */ +/*! @{ */ +#define CAN_HR_TIME_STAMP_TS_MASK (0xFFFFFFFFU) +#define CAN_HR_TIME_STAMP_TS_SHIFT (0U) +#define CAN_HR_TIME_STAMP_TS(x) (((uint32_t)(((uint32_t)(x)) << CAN_HR_TIME_STAMP_TS_SHIFT)) & CAN_HR_TIME_STAMP_TS_MASK) +/*! @} */ + +/* The count of CAN_HR_TIME_STAMP */ +#define CAN_HR_TIME_STAMP_COUNT (64U) + +/*! @name ERFFEL - Enhanced Rx FIFO Filter Element */ +/*! @{ */ +#define CAN_ERFFEL_FEL_MASK (0xFFFFFFFFU) +#define CAN_ERFFEL_FEL_SHIFT (0U) +#define CAN_ERFFEL_FEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK) +/*! @} */ + +/* The count of CAN_ERFFEL */ +#define CAN_ERFFEL_COUNT (128U) + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN1 base address */ +#define CAN1_BASE (0x401D0000u) +/** Peripheral CAN1 base pointer */ +#define CAN1 ((CAN_Type *)CAN1_BASE) +/** Peripheral CAN2 base address */ +#define CAN2_BASE (0x401D4000u) +/** Peripheral CAN2 base pointer */ +#define CAN2 ((CAN_Type *)CAN2_BASE) +/** Peripheral CAN3 base address */ +#define CAN3_BASE (0x401D8000u) +/** Peripheral CAN3 base pointer */ +#define CAN3 ((CAN_Type *)CAN3_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE, CAN3_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2, CAN3 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn } +#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn } +#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn } +#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn } +#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn } +#define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn } + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer + * @{ + */ + +/** CCM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CCR; /**< CCM Control Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __I uint32_t CSR; /**< CCM Status Register, offset: 0x8 */ + __IO uint32_t CCSR; /**< CCM Clock Switcher Register, offset: 0xC */ + __IO uint32_t CACRR; /**< CCM Arm Clock Root Register, offset: 0x10 */ + __IO uint32_t CBCDR; /**< CCM Bus Clock Divider Register, offset: 0x14 */ + __IO uint32_t CBCMR; /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */ + __IO uint32_t CSCMR1; /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */ + __IO uint32_t CSCMR2; /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */ + __IO uint32_t CSCDR1; /**< CCM Serial Clock Divider Register 1, offset: 0x24 */ + __IO uint32_t CS1CDR; /**< CCM Clock Divider Register, offset: 0x28 */ + __IO uint32_t CS2CDR; /**< CCM Clock Divider Register, offset: 0x2C */ + __IO uint32_t CDCDR; /**< CCM D1 Clock Divider Register, offset: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t CSCDR2; /**< CCM Serial Clock Divider Register 2, offset: 0x38 */ + __IO uint32_t CSCDR3; /**< CCM Serial Clock Divider Register 3, offset: 0x3C */ + uint8_t RESERVED_2[8]; + __I uint32_t CDHIPR; /**< CCM Divider Handshake In-Process Register, offset: 0x48 */ + uint8_t RESERVED_3[8]; + __IO uint32_t CLPCR; /**< CCM Low Power Control Register, offset: 0x54 */ + __IO uint32_t CISR; /**< CCM Interrupt Status Register, offset: 0x58 */ + __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */ + __IO uint32_t CCOSR; /**< CCM Clock Output Source Register, offset: 0x60 */ + __IO uint32_t CGPR; /**< CCM General Purpose Register, offset: 0x64 */ + __IO uint32_t CCGR0; /**< CCM Clock Gating Register 0, offset: 0x68 */ + __IO uint32_t CCGR1; /**< CCM Clock Gating Register 1, offset: 0x6C */ + __IO uint32_t CCGR2; /**< CCM Clock Gating Register 2, offset: 0x70 */ + __IO uint32_t CCGR3; /**< CCM Clock Gating Register 3, offset: 0x74 */ + __IO uint32_t CCGR4; /**< CCM Clock Gating Register 4, offset: 0x78 */ + __IO uint32_t CCGR5; /**< CCM Clock Gating Register 5, offset: 0x7C */ + __IO uint32_t CCGR6; /**< CCM Clock Gating Register 6, offset: 0x80 */ + __IO uint32_t CCGR7; /**< CCM Clock Gating Register 7, offset: 0x84 */ + __IO uint32_t CMEOR; /**< CCM Module Enable Overide Register, offset: 0x88 */ +} CCM_Type; + +/* ---------------------------------------------------------------------------- + -- CCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Register_Masks CCM Register Masks + * @{ + */ + +/*! @name CCR - CCM Control Register */ +/*! @{ */ +#define CCM_CCR_OSCNT_MASK (0xFFU) +#define CCM_CCR_OSCNT_SHIFT (0U) +#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK) +#define CCM_CCR_COSC_EN_MASK (0x1000U) +#define CCM_CCR_COSC_EN_SHIFT (12U) +/*! COSC_EN + * 0b0..disable on chip oscillator + * 0b1..enable on chip oscillator + */ +#define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK) +#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U) +#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U) +/*! REG_BYPASS_COUNT + * 0b000000..no delay + * 0b000001..1 CKIL clock period delay + * 0b111111..63 CKIL clock periods delay + */ +#define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK) +#define CCM_CCR_RBC_EN_MASK (0x8000000U) +#define CCM_CCR_RBC_EN_SHIFT (27U) +/*! RBC_EN + * 0b1..REG_BYPASS_COUNTER enabled. + * 0b0..REG_BYPASS_COUNTER disabled + */ +#define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK) +/*! @} */ + +/*! @name CSR - CCM Status Register */ +/*! @{ */ +#define CCM_CSR_REF_EN_B_MASK (0x1U) +#define CCM_CSR_REF_EN_B_SHIFT (0U) +/*! REF_EN_B + * 0b0..value of CCM_REF_EN_B is '0' + * 0b1..value of CCM_REF_EN_B is '1' + */ +#define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK) +#define CCM_CSR_CAMP2_READY_MASK (0x8U) +#define CCM_CSR_CAMP2_READY_SHIFT (3U) +/*! CAMP2_READY + * 0b0..CAMP2 is not ready. + * 0b1..CAMP2 is ready. + */ +#define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK) +#define CCM_CSR_COSC_READY_MASK (0x20U) +#define CCM_CSR_COSC_READY_SHIFT (5U) +/*! COSC_READY + * 0b0..on board oscillator is not ready. + * 0b1..on board oscillator is ready. + */ +#define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK) +/*! @} */ + +/*! @name CCSR - CCM Clock Switcher Register */ +/*! @{ */ +#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U) +#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U) +/*! PLL3_SW_CLK_SEL + * 0b0..pll3_main_clk + * 0b1..pll3 bypass clock + */ +#define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK) +/*! @} */ + +/*! @name CACRR - CCM Arm Clock Root Register */ +/*! @{ */ +#define CCM_CACRR_ARM_PODF_MASK (0x7U) +#define CCM_CACRR_ARM_PODF_SHIFT (0U) +/*! ARM_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK) +/*! @} */ + +/*! @name CBCDR - CCM Bus Clock Divider Register */ +/*! @{ */ +#define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U) +#define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U) +/*! SEMC_CLK_SEL + * 0b0..Periph_clk output will be used as SEMC clock root + * 0b1..SEMC alternative clock will be used as SEMC clock root + */ +#define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK) +#define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U) +#define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U) +/*! SEMC_ALT_CLK_SEL + * 0b0..PLL2 PFD2 will be selected as alternative clock for SEMC root clock + * 0b1..PLL3 PFD1 will be selected as alternative clock for SEMC root clock + */ +#define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) +#define CCM_CBCDR_IPG_PODF_MASK (0x300U) +#define CCM_CBCDR_IPG_PODF_SHIFT (8U) +/*! IPG_PODF + * 0b00..divide by 1 + * 0b01..divide by 2 + * 0b10..divide by 3 + * 0b11..divide by 4 + */ +#define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK) +#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U) +#define CCM_CBCDR_AHB_PODF_SHIFT (10U) +/*! AHB_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK) +#define CCM_CBCDR_SEMC_PODF_MASK (0x70000U) +#define CCM_CBCDR_SEMC_PODF_SHIFT (16U) +/*! SEMC_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK) +#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U) +#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U) +/*! PERIPH_CLK_SEL + * 0b0..derive clock from pre_periph_clk_sel + * 0b1..derive clock from periph_clk2_clk_divided + */ +#define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK) +#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U) +#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U) +/*! PERIPH_CLK2_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) +/*! @} */ + +/*! @name CBCMR - CCM Bus Clock Multiplexer Register */ +/*! @{ */ +#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U) +#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U) +/*! LPSPI_CLK_SEL + * 0b00..derive clock from PLL3 PFD1 clk + * 0b01..derive clock from PLL3 PFD0 + * 0b10..derive clock from PLL2 + * 0b11..derive clock from PLL2 PFD2 + */ +#define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK) +#define CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK (0x300U) +#define CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT (8U) +/*! FLEXSPI2_CLK_SEL + * 0b00..derive clock from PLL2 PFD2 + * 0b01..derive clock from PLL3 PFD0 + * 0b10..derive clock from PLL3 PFD1 + * 0b11..derive clock from PLL2 (pll2_main_clk) + */ +#define CCM_CBCMR_FLEXSPI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT)) & CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK) +#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U) +#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U) +/*! PERIPH_CLK2_SEL + * 0b00..derive clock from pll3_sw_clk + * 0b01..derive clock from osc_clk (pll1_ref_clk) + * 0b10..derive clock from pll2_bypass_clk + * 0b11..reserved + */ +#define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) +#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U) +#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U) +/*! TRACE_CLK_SEL + * 0b00..derive clock from PLL2 + * 0b01..derive clock from PLL2 PFD2 + * 0b10..derive clock from PLL2 PFD0 + * 0b11..derive clock from PLL2 PFD1 + */ +#define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U) +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U) +/*! PRE_PERIPH_CLK_SEL + * 0b00..derive clock from PLL2 + * 0b01..derive clock from PLL2 PFD2 + * 0b10..derive clock from PLL2 PFD0 + * 0b11..derive clock from divided PLL1 + */ +#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) +#define CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U) +#define CCM_CBCMR_LCDIF_PODF_SHIFT (23U) +/*! LCDIF_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK) +#define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U) +#define CCM_CBCMR_LPSPI_PODF_SHIFT (26U) +/*! LPSPI_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK) +#define CCM_CBCMR_FLEXSPI2_PODF_MASK (0xE0000000U) +#define CCM_CBCMR_FLEXSPI2_PODF_SHIFT (29U) +/*! FLEXSPI2_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CBCMR_FLEXSPI2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_FLEXSPI2_PODF_SHIFT)) & CCM_CBCMR_FLEXSPI2_PODF_MASK) +/*! @} */ + +/*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */ +/*! @{ */ +#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU) +#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U) +/*! PERCLK_PODF - Divider for perclk podf. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK) +#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U) +#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U) +/*! PERCLK_CLK_SEL + * 0b0..derive clock from ipg clk root + * 0b1..derive clock from osc_clk + */ +#define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U) +#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U) +/*! SAI1_CLK_SEL + * 0b00..derive clock from PLL3 PFD2 + * 0b01..derive clock from PLL5 + * 0b10..derive clock from PLL4 + * 0b11..Reserved + */ +#define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U) +#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U) +/*! SAI2_CLK_SEL + * 0b00..derive clock from PLL3 PFD2 + * 0b01..derive clock from PLL5 + * 0b10..derive clock from PLL4 + * 0b11..Reserved + */ +#define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK) +#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U) +#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U) +/*! SAI3_CLK_SEL + * 0b00..derive clock from PLL3 PFD2 + * 0b01..derive clock from PLL5 + * 0b10..derive clock from PLL4 + * 0b11..Reserved + */ +#define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK) +#define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U) +#define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U) +/*! USDHC1_CLK_SEL + * 0b0..derive clock from PLL2 PFD2 + * 0b1..derive clock from PLL2 PFD0 + */ +#define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK) +#define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U) +#define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U) +/*! USDHC2_CLK_SEL + * 0b0..derive clock from PLL2 PFD2 + * 0b1..derive clock from PLL2 PFD0 + */ +#define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK) +#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U) +#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U) +/*! FLEXSPI_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK) +#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U) +#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U) +/*! FLEXSPI_CLK_SEL + * 0b00..derive clock from semc_clk_root_pre + * 0b01..derive clock from pll3_sw_clk + * 0b10..derive clock from PLL2 PFD2 + * 0b11..derive clock from PLL3 PFD0 + */ +#define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK) +/*! @} */ + +/*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */ +/*! @{ */ +#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU) +#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U) +/*! CAN_CLK_PODF - Divider for CAN/CANFD clock podf. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK) +#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U) +#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U) +/*! CAN_CLK_SEL + * 0b00..derive clock from pll3_sw_clk divided clock (60M) + * 0b01..derive clock from osc_clk (24M) + * 0b10..derive clock from pll3_sw_clk divided clock (80M) + * 0b11..Disable FlexCAN clock + */ +#define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK) +#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U) +#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U) +/*! FLEXIO2_CLK_SEL + * 0b00..derive clock from PLL4 divided clock + * 0b01..derive clock from PLL3 PFD2 clock + * 0b10..derive clock from PLL5 clock + * 0b11..derive clock from pll3_sw_clk + */ +#define CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK) +/*! @} */ + +/*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */ +/*! @{ */ +#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU) +#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U) +/*! UART_CLK_PODF - Divider for uart clock podf. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK) +#define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U) +#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U) +/*! UART_CLK_SEL + * 0b0..derive clock from pll3_80m + * 0b1..derive clock from osc_clk + */ +#define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK) +#define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U) +#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U) +/*! USDHC1_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK) +#define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U) +#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U) +/*! USDHC2_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK) +#define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U) +#define CCM_CSCDR1_TRACE_PODF_SHIFT (25U) +/*! TRACE_PODF + * 0b00..divide by 1 + * 0b01..divide by 2 + * 0b10..divide by 3 + * 0b11..divide by 4 + */ +#define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK) +/*! @} */ + +/*! @name CS1CDR - CCM Clock Divider Register */ +/*! @{ */ +#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU) +#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U) +/*! SAI1_CLK_PODF - Divider for sai1 clock podf. The input clock to this divider should be lower + * than 300Mhz, the predivider can be used to achieve this. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK) +#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U) +#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U) +/*! SAI1_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK) +#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U) +#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U) +/*! FLEXIO2_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK) +#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U) +#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U) +/*! SAI3_CLK_PODF - Divider for sai3 clock podf. The input clock to this divider should be lower + * than 300Mhz, the predivider can be used to achieve this. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK) +#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U) +#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U) +/*! SAI3_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK) +#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U) +#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U) +/*! FLEXIO2_CLK_PODF - Divider for flexio2/flexio3 clock. Divider should be updated when output clock is gated. + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK) +/*! @} */ + +/*! @name CS2CDR - CCM Clock Divider Register */ +/*! @{ */ +#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU) +#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U) +/*! SAI2_CLK_PODF - Divider for sai2 clock podf. The input clock to this divider should be lower + * than 300Mhz, the predivider can be used to achieve this. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK) +#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U) +#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U) +/*! SAI2_CLK_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK) +/*! @} */ + +/*! @name CDCDR - CCM D1 Clock Divider Register */ +/*! @{ */ +#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U) +#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U) +/*! FLEXIO1_CLK_SEL + * 0b00..derive clock from PLL4 + * 0b01..derive clock from PLL3 PFD2 + * 0b10..derive clock from PLL5 + * 0b11..derive clock from pll3_sw_clk + */ +#define CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK) +#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U) +#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U) +/*! FLEXIO1_CLK_PODF - Divider for flexio1 clock podf. Divider should be updated when output clock is gated. + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK) +#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U) +#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U) +/*! FLEXIO1_CLK_PRED - Divider for flexio1 clock pred. Divider should be updated when output clock is gated. + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK) +#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U) +#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U) +/*! SPDIF0_CLK_SEL + * 0b00..derive clock from PLL4 + * 0b01..derive clock from PLL3 PFD2 + * 0b10..derive clock from PLL5 + * 0b11..derive clock from pll3_sw_clk + */ +#define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK) +#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U) +#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U) +/*! SPDIF0_CLK_PODF - Divider for spdif0 clock podf. Divider should be updated when output clock is gated. + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK) +#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U) +#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U) +/*! SPDIF0_CLK_PRED - Divider for spdif0 clock pred. Divider should be updated when output clock is gated. + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 3 + * 0b011..Divide by 4 + * 0b100..Divide by 5 + * 0b101..Divide by 6 + * 0b110..Divide by 7 + * 0b111..Divide by 8 + */ +#define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK) +/*! @} */ + +/*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */ +/*! @{ */ +#define CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U) +#define CCM_CSCDR2_LCDIF_PRED_SHIFT (12U) +/*! LCDIF_PRED + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK) +#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U) +#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U) +/*! LCDIF_PRE_CLK_SEL + * 0b000..derive clock from PLL2 + * 0b001..derive clock from PLL3 PFD3 + * 0b010..derive clock from PLL5 + * 0b011..derive clock from PLL2 PFD0 + * 0b100..derive clock from PLL2 PFD1 + * 0b101..derive clock from PLL3 PFD1 + */ +#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK) +#define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U) +#define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U) +/*! LPI2C_CLK_SEL + * 0b0..derive clock from pll3_60m + * 0b1..derive clock from osc_clk + */ +#define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK) +#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U) +#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U) +/*! LPI2C_CLK_PODF - Divider for lpi2c clock podf. Divider should be updated when output clock is + * gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used + * to achieve this. + * 0b000000..Divide by 1 + * 0b000001..Divide by 2 + * 0b000010..Divide by 3 + * 0b000011..Divide by 4 + * 0b000100..Divide by 5 + * 0b000101..Divide by 6 + * 0b000110..Divide by 7 + * 0b000111..Divide by 8 + * 0b001000..Divide by 9 + * 0b001001..Divide by 10 + * 0b001010..Divide by 11 + * 0b001011..Divide by 12 + * 0b001100..Divide by 13 + * 0b001101..Divide by 14 + * 0b001110..Divide by 15 + * 0b001111..Divide by 16 + * 0b010000..Divide by 17 + * 0b010001..Divide by 18 + * 0b010010..Divide by 19 + * 0b010011..Divide by 20 + * 0b010100..Divide by 21 + * 0b010101..Divide by 22 + * 0b010110..Divide by 23 + * 0b010111..Divide by 24 + * 0b011000..Divide by 25 + * 0b011001..Divide by 26 + * 0b011010..Divide by 27 + * 0b011011..Divide by 28 + * 0b011100..Divide by 29 + * 0b011101..Divide by 30 + * 0b011110..Divide by 31 + * 0b011111..Divide by 32 + * 0b100000..Divide by 33 + * 0b100001..Divide by 34 + * 0b100010..Divide by 35 + * 0b100011..Divide by 36 + * 0b100100..Divide by 37 + * 0b100101..Divide by 38 + * 0b100110..Divide by 39 + * 0b100111..Divide by 40 + * 0b101000..Divide by 41 + * 0b101001..Divide by 42 + * 0b101010..Divide by 43 + * 0b101011..Divide by 44 + * 0b101100..Divide by 45 + * 0b101101..Divide by 46 + * 0b101110..Divide by 47 + * 0b101111..Divide by 48 + * 0b110000..Divide by 49 + * 0b110001..Divide by 50 + * 0b110010..Divide by 51 + * 0b110011..Divide by 52 + * 0b110100..Divide by 53 + * 0b110101..Divide by 54 + * 0b110110..Divide by 55 + * 0b110111..Divide by 56 + * 0b111000..Divide by 57 + * 0b111001..Divide by 58 + * 0b111010..Divide by 59 + * 0b111011..Divide by 60 + * 0b111100..Divide by 61 + * 0b111101..Divide by 62 + * 0b111110..Divide by 63 + * 0b111111..Divide by 64 + */ +#define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK) +/*! @} */ + +/*! @name CSCDR3 - CCM Serial Clock Divider Register 3 */ +/*! @{ */ +#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U) +#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U) +/*! CSI_CLK_SEL + * 0b00..derive clock from osc_clk (24M) + * 0b01..derive clock from PLL2 PFD2 + * 0b10..derive clock from pll3_120M + * 0b11..derive clock from PLL3 PFD1 + */ +#define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK) +#define CCM_CSCDR3_CSI_PODF_MASK (0x3800U) +#define CCM_CSCDR3_CSI_PODF_SHIFT (11U) +/*! CSI_PODF + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK) +/*! @} */ + +/*! @name CDHIPR - CCM Divider Handshake In-Process Register */ +/*! @{ */ +#define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U) +#define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U) +/*! SEMC_PODF_BUSY + * 0b0..divider is not busy and its value represents the actual division. + * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous + * value of the division factor, and after the handshake the written value of the semc_podf will be applied. + */ +#define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK) +#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U) +#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U) +/*! AHB_PODF_BUSY + * 0b0..divider is not busy and its value represents the actual division. + * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous + * value of the division factor, and after the handshake the written value of the ahb_podf will be applied. + */ +#define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U) +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U) +/*! PERIPH2_CLK_SEL_BUSY + * 0b0..mux is not busy and its value represents the actual division. + * 0b1..mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the + * previous value of select, and after the handshake periph2_clk_sel value will be applied. + */ +#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U) +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U) +/*! PERIPH_CLK_SEL_BUSY + * 0b0..mux is not busy and its value represents the actual division. + * 0b1..mux is busy with handshake process with module. The value read in the periph_clk_sel represents the + * previous value of select, and after the handshake periph_clk_sel value will be applied. + */ +#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK) +#define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U) +#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U) +/*! ARM_PODF_BUSY + * 0b0..divider is not busy and its value represents the actual division. + * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous + * value of the division factor, and after the handshake the written value of the arm_podf will be applied. + */ +#define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK) +/*! @} */ + +/*! @name CLPCR - CCM Low Power Control Register */ +/*! @{ */ +#define CCM_CLPCR_LPM_MASK (0x3U) +#define CCM_CLPCR_LPM_SHIFT (0U) +/*! LPM + * 0b00..Remain in run mode + * 0b01..Transfer to wait mode + * 0b10..Transfer to stop mode + * 0b11..Reserved + */ +#define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U) +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U) +/*! ARM_CLK_DIS_ON_LPM + * 0b0..ARM clock enabled on wait mode. + * 0b1..ARM clock disabled on wait mode. . + */ +#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK) +#define CCM_CLPCR_SBYOS_MASK (0x40U) +#define CCM_CLPCR_SBYOS_SHIFT (6U) +/*! SBYOS + * 0b0..On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain + * asserted - '0' and cosc_pwrdown will remain de asserted - '0') + * 0b1..On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be + * deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will + * be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will + * continue with the exit from the STOP mode process. + */ +#define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK) +#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U) +#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U) +/*! DIS_REF_OSC + * 0b0..external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'. + * 0b1..external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1' + */ +#define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK) +#define CCM_CLPCR_VSTBY_MASK (0x100U) +#define CCM_CLPCR_VSTBY_SHIFT (8U) +/*! VSTBY + * 0b0..Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0') + * 0b1..Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1'). + */ +#define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK) +#define CCM_CLPCR_STBY_COUNT_MASK (0x600U) +#define CCM_CLPCR_STBY_COUNT_SHIFT (9U) +/*! STBY_COUNT + * 0b00..CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles + * 0b01..CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles + * 0b10..CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles + * 0b11..CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles + */ +#define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK) +#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U) +#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U) +/*! COSC_PWRDOWN + * 0b0..On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'. + * 0b1..On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'. + */ +#define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK) +#define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U) +#define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U) +#define CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK) +#define CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U) +#define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U) +#define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK) +#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U) +#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U) +/*! MASK_CORE0_WFI + * 0b0..WFI of core0 is not masked + * 0b1..WFI of core0 is masked + */ +#define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK) +#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U) +#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U) +/*! MASK_SCU_IDLE + * 0b1..SCU IDLE is masked + * 0b0..SCU IDLE is not masked + */ +#define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK) +#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U) +#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U) +/*! MASK_L2CC_IDLE + * 0b1..L2CC IDLE is masked + * 0b0..L2CC IDLE is not masked + */ +#define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK) +/*! @} */ + +/*! @name CISR - CCM Interrupt Status Register */ +/*! @{ */ +#define CCM_CISR_LRF_PLL_MASK (0x1U) +#define CCM_CISR_LRF_PLL_SHIFT (0U) +/*! LRF_PLL + * 0b0..interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs + * 0b1..interrupt generated due to lock ready of all enabled and not bypaseed PLLs + */ +#define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK) +#define CCM_CISR_COSC_READY_MASK (0x40U) +#define CCM_CISR_COSC_READY_SHIFT (6U) +/*! COSC_READY + * 0b0..interrupt is not generated due to on board oscillator ready + * 0b1..interrupt generated due to on board oscillator ready + */ +#define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK) +#define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U) +#define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U) +/*! SEMC_PODF_LOADED + * 0b0..interrupt is not generated due to frequency change of semc_podf + * 0b1..interrupt generated due to frequency change of semc_podf + */ +#define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +/*! PERIPH2_CLK_SEL_LOADED + * 0b0..interrupt is not generated due to frequency change of periph2_clk_sel + * 0b1..interrupt generated due to frequency change of periph2_clk_sel + */ +#define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK) +#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U) +#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U) +/*! AHB_PODF_LOADED + * 0b0..interrupt is not generated due to frequency change of ahb_podf + * 0b1..interrupt generated due to frequency change of ahb_podf + */ +#define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) +#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +/*! PERIPH_CLK_SEL_LOADED + * 0b0..interrupt is not generated due to update of periph_clk_sel. + * 0b1..interrupt generated due to update of periph_clk_sel. + */ +#define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK) +#define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U) +#define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U) +/*! ARM_PODF_LOADED + * 0b0..interrupt is not generated due to frequency change of arm_podf + * 0b1..interrupt generated due to frequency change of arm_podf + */ +#define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK) +/*! @} */ + +/*! @name CIMR - CCM Interrupt Mask Register */ +/*! @{ */ +#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U) +#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U) +/*! MASK_LRF_PLL + * 0b0..don't mask interrupt due to lrf of PLLs - interrupt will be created + * 0b1..mask interrupt due to lrf of PLLs + */ +#define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK) +#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U) +#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U) +/*! MASK_COSC_READY + * 0b0..don't mask interrupt due to on board oscillator ready - interrupt will be created + * 0b1..mask interrupt due to on board oscillator ready + */ +#define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK) +#define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U) +#define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U) +/*! MASK_SEMC_PODF_LOADED + * 0b0..don't mask interrupt due to frequency change of semc_podf - interrupt will be created + * 0b1..mask interrupt due to frequency change of semc_podf + */ +#define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U) +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U) +/*! MASK_PERIPH2_CLK_SEL_LOADED + * 0b0..don't mask interrupt due to update of periph2_clk_sel - interrupt will be created + * 0b1..mask interrupt due to update of periph2_clk_sel + */ +#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK) +#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U) +#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U) +/*! MASK_AHB_PODF_LOADED + * 0b0..don't mask interrupt due to frequency change of ahb_podf - interrupt will be created + * 0b1..mask interrupt due to frequency change of ahb_podf + */ +#define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U) +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U) +/*! MASK_PERIPH_CLK_SEL_LOADED + * 0b0..don't mask interrupt due to update of periph_clk_sel - interrupt will be created + * 0b1..mask interrupt due to update of periph_clk_sel + */ +#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK) +#define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U) +#define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U) +/*! ARM_PODF_LOADED + * 0b0..don't mask interrupt due to frequency change of arm_podf - interrupt will be created + * 0b1..mask interrupt due to frequency change of arm_podf + */ +#define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK) +/*! @} */ + +/*! @name CCOSR - CCM Clock Output Source Register */ +/*! @{ */ +#define CCM_CCOSR_CLKO1_SEL_MASK (0xFU) +#define CCM_CCOSR_CLKO1_SEL_SHIFT (0U) +/*! CLKO1_SEL + * 0b0000..USB1 PLL clock (divided by 2) + * 0b0001..SYS PLL clock (divided by 2) + * 0b0011..VIDEO PLL clock (divided by 2) + * 0b0101..semc_clk_root + * 0b0110..Reserved + * 0b1010..lcdif_pix_clk_root + * 0b1011..ahb_clk_root + * 0b1100..ipg_clk_root + * 0b1101..perclk_root + * 0b1110..ckil_sync_clk_root + * 0b1111..pll4_main_clk + */ +#define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK) +#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U) +#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U) +/*! CLKO1_DIV + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK) +#define CCM_CCOSR_CLKO1_EN_MASK (0x80U) +#define CCM_CCOSR_CLKO1_EN_SHIFT (7U) +/*! CLKO1_EN + * 0b0..CCM_CLKO1 disabled. + * 0b1..CCM_CLKO1 enabled. + */ +#define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK) +#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U) +#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U) +/*! CLK_OUT_SEL + * 0b0..CCM_CLKO1 output drives CCM_CLKO1 clock + * 0b1..CCM_CLKO1 output drives CCM_CLKO2 clock + */ +#define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK) +#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U) +#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U) +/*! CLKO2_SEL + * 0b00011..usdhc1_clk_root + * 0b00110..lpi2c_clk_root + * 0b01011..csi_clk_root + * 0b01110..osc_clk + * 0b10001..usdhc2_clk_root + * 0b10010..sai1_clk_root + * 0b10011..sai2_clk_root + * 0b10100..sai3_clk_root (shared with ADC1 and ADC2 alt_clk root) + * 0b10111..can_clk_root (FlexCAN, shared with CANFD) + * 0b11011..flexspi_clk_root + * 0b11100..uart_clk_root + * 0b11101..spdif0_clk_root + * 0b11111..Reserved + */ +#define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK) +#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U) +#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U) +/*! CLKO2_DIV + * 0b000..divide by 1 + * 0b001..divide by 2 + * 0b010..divide by 3 + * 0b011..divide by 4 + * 0b100..divide by 5 + * 0b101..divide by 6 + * 0b110..divide by 7 + * 0b111..divide by 8 + */ +#define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK) +#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U) +#define CCM_CCOSR_CLKO2_EN_SHIFT (24U) +/*! CLKO2_EN + * 0b0..CCM_CLKO2 disabled. + * 0b1..CCM_CLKO2 enabled. + */ +#define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK) +/*! @} */ + +/*! @name CGPR - CCM General Purpose Register */ +/*! @{ */ +#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U) +#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U) +/*! PMIC_DELAY_SCALER + * 0b0..clock is not divided + * 0b1..clock is divided /8 + */ +#define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U) +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U) +/*! EFUSE_PROG_SUPPLY_GATE + * 0b0..fuse programing supply voltage is gated off to the efuse module + * 0b1..allow fuse programing. + */ +#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK) +#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U) +#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U) +/*! SYS_MEM_DS_CTRL + * 0b00..Disable memory DS mode always + * 0b01..Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled + * 0b1x..enable memory (outside ARM platform) DS mode when system is in STOP mode + */ +#define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK) +#define CCM_CGPR_FPL_MASK (0x10000U) +#define CCM_CGPR_FPL_SHIFT (16U) +/*! FPL - Fast PLL enable. + * 0b0..Engage PLL enable default way. + * 0b1..Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode. + */ +#define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK) +#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U) +#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U) +/*! INT_MEM_CLK_LPM + * 0b0..Disable the clock to the ARM platform memories when entering Low Power Mode + * 0b1..Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low + * Power Modes (WAIT and STOP without power gating) + */ +#define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK) +/*! @} */ + +/*! @name CCGR0 - CCM Clock Gating Register 0 */ +/*! @{ */ +#define CCM_CCGR0_CG0_MASK (0x3U) +#define CCM_CCGR0_CG0_SHIFT (0U) +#define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK) +#define CCM_CCGR0_CG1_MASK (0xCU) +#define CCM_CCGR0_CG1_SHIFT (2U) +#define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK) +#define CCM_CCGR0_CG2_MASK (0x30U) +#define CCM_CCGR0_CG2_SHIFT (4U) +#define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK) +#define CCM_CCGR0_CG3_MASK (0xC0U) +#define CCM_CCGR0_CG3_SHIFT (6U) +#define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK) +#define CCM_CCGR0_CG4_MASK (0x300U) +#define CCM_CCGR0_CG4_SHIFT (8U) +#define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK) +#define CCM_CCGR0_CG5_MASK (0xC00U) +#define CCM_CCGR0_CG5_SHIFT (10U) +#define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK) +#define CCM_CCGR0_CG6_MASK (0x3000U) +#define CCM_CCGR0_CG6_SHIFT (12U) +#define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK) +#define CCM_CCGR0_CG7_MASK (0xC000U) +#define CCM_CCGR0_CG7_SHIFT (14U) +#define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK) +#define CCM_CCGR0_CG8_MASK (0x30000U) +#define CCM_CCGR0_CG8_SHIFT (16U) +#define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK) +#define CCM_CCGR0_CG9_MASK (0xC0000U) +#define CCM_CCGR0_CG9_SHIFT (18U) +#define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK) +#define CCM_CCGR0_CG10_MASK (0x300000U) +#define CCM_CCGR0_CG10_SHIFT (20U) +#define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK) +#define CCM_CCGR0_CG11_MASK (0xC00000U) +#define CCM_CCGR0_CG11_SHIFT (22U) +#define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK) +#define CCM_CCGR0_CG12_MASK (0x3000000U) +#define CCM_CCGR0_CG12_SHIFT (24U) +#define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK) +#define CCM_CCGR0_CG13_MASK (0xC000000U) +#define CCM_CCGR0_CG13_SHIFT (26U) +#define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK) +#define CCM_CCGR0_CG14_MASK (0x30000000U) +#define CCM_CCGR0_CG14_SHIFT (28U) +#define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK) +#define CCM_CCGR0_CG15_MASK (0xC0000000U) +#define CCM_CCGR0_CG15_SHIFT (30U) +#define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK) +/*! @} */ + +/*! @name CCGR1 - CCM Clock Gating Register 1 */ +/*! @{ */ +#define CCM_CCGR1_CG0_MASK (0x3U) +#define CCM_CCGR1_CG0_SHIFT (0U) +#define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK) +#define CCM_CCGR1_CG1_MASK (0xCU) +#define CCM_CCGR1_CG1_SHIFT (2U) +#define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK) +#define CCM_CCGR1_CG2_MASK (0x30U) +#define CCM_CCGR1_CG2_SHIFT (4U) +#define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK) +#define CCM_CCGR1_CG3_MASK (0xC0U) +#define CCM_CCGR1_CG3_SHIFT (6U) +#define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK) +#define CCM_CCGR1_CG4_MASK (0x300U) +#define CCM_CCGR1_CG4_SHIFT (8U) +#define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK) +#define CCM_CCGR1_CG5_MASK (0xC00U) +#define CCM_CCGR1_CG5_SHIFT (10U) +#define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK) +#define CCM_CCGR1_CG6_MASK (0x3000U) +#define CCM_CCGR1_CG6_SHIFT (12U) +#define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK) +#define CCM_CCGR1_CG7_MASK (0xC000U) +#define CCM_CCGR1_CG7_SHIFT (14U) +#define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK) +#define CCM_CCGR1_CG8_MASK (0x30000U) +#define CCM_CCGR1_CG8_SHIFT (16U) +#define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK) +#define CCM_CCGR1_CG9_MASK (0xC0000U) +#define CCM_CCGR1_CG9_SHIFT (18U) +#define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK) +#define CCM_CCGR1_CG10_MASK (0x300000U) +#define CCM_CCGR1_CG10_SHIFT (20U) +#define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK) +#define CCM_CCGR1_CG11_MASK (0xC00000U) +#define CCM_CCGR1_CG11_SHIFT (22U) +#define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK) +#define CCM_CCGR1_CG12_MASK (0x3000000U) +#define CCM_CCGR1_CG12_SHIFT (24U) +#define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK) +#define CCM_CCGR1_CG13_MASK (0xC000000U) +#define CCM_CCGR1_CG13_SHIFT (26U) +#define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK) +#define CCM_CCGR1_CG14_MASK (0x30000000U) +#define CCM_CCGR1_CG14_SHIFT (28U) +#define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK) +#define CCM_CCGR1_CG15_MASK (0xC0000000U) +#define CCM_CCGR1_CG15_SHIFT (30U) +#define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK) +/*! @} */ + +/*! @name CCGR2 - CCM Clock Gating Register 2 */ +/*! @{ */ +#define CCM_CCGR2_CG0_MASK (0x3U) +#define CCM_CCGR2_CG0_SHIFT (0U) +#define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK) +#define CCM_CCGR2_CG1_MASK (0xCU) +#define CCM_CCGR2_CG1_SHIFT (2U) +#define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK) +#define CCM_CCGR2_CG2_MASK (0x30U) +#define CCM_CCGR2_CG2_SHIFT (4U) +#define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK) +#define CCM_CCGR2_CG3_MASK (0xC0U) +#define CCM_CCGR2_CG3_SHIFT (6U) +#define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK) +#define CCM_CCGR2_CG4_MASK (0x300U) +#define CCM_CCGR2_CG4_SHIFT (8U) +#define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK) +#define CCM_CCGR2_CG5_MASK (0xC00U) +#define CCM_CCGR2_CG5_SHIFT (10U) +#define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK) +#define CCM_CCGR2_CG6_MASK (0x3000U) +#define CCM_CCGR2_CG6_SHIFT (12U) +#define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK) +#define CCM_CCGR2_CG7_MASK (0xC000U) +#define CCM_CCGR2_CG7_SHIFT (14U) +#define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK) +#define CCM_CCGR2_CG8_MASK (0x30000U) +#define CCM_CCGR2_CG8_SHIFT (16U) +#define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK) +#define CCM_CCGR2_CG9_MASK (0xC0000U) +#define CCM_CCGR2_CG9_SHIFT (18U) +#define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK) +#define CCM_CCGR2_CG10_MASK (0x300000U) +#define CCM_CCGR2_CG10_SHIFT (20U) +#define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK) +#define CCM_CCGR2_CG11_MASK (0xC00000U) +#define CCM_CCGR2_CG11_SHIFT (22U) +#define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK) +#define CCM_CCGR2_CG12_MASK (0x3000000U) +#define CCM_CCGR2_CG12_SHIFT (24U) +#define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK) +#define CCM_CCGR2_CG13_MASK (0xC000000U) +#define CCM_CCGR2_CG13_SHIFT (26U) +#define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK) +#define CCM_CCGR2_CG14_MASK (0x30000000U) +#define CCM_CCGR2_CG14_SHIFT (28U) +#define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK) +#define CCM_CCGR2_CG15_MASK (0xC0000000U) +#define CCM_CCGR2_CG15_SHIFT (30U) +#define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK) +/*! @} */ + +/*! @name CCGR3 - CCM Clock Gating Register 3 */ +/*! @{ */ +#define CCM_CCGR3_CG0_MASK (0x3U) +#define CCM_CCGR3_CG0_SHIFT (0U) +#define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK) +#define CCM_CCGR3_CG1_MASK (0xCU) +#define CCM_CCGR3_CG1_SHIFT (2U) +#define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK) +#define CCM_CCGR3_CG2_MASK (0x30U) +#define CCM_CCGR3_CG2_SHIFT (4U) +#define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK) +#define CCM_CCGR3_CG3_MASK (0xC0U) +#define CCM_CCGR3_CG3_SHIFT (6U) +#define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK) +#define CCM_CCGR3_CG4_MASK (0x300U) +#define CCM_CCGR3_CG4_SHIFT (8U) +#define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK) +#define CCM_CCGR3_CG5_MASK (0xC00U) +#define CCM_CCGR3_CG5_SHIFT (10U) +#define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK) +#define CCM_CCGR3_CG6_MASK (0x3000U) +#define CCM_CCGR3_CG6_SHIFT (12U) +#define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK) +#define CCM_CCGR3_CG7_MASK (0xC000U) +#define CCM_CCGR3_CG7_SHIFT (14U) +#define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK) +#define CCM_CCGR3_CG8_MASK (0x30000U) +#define CCM_CCGR3_CG8_SHIFT (16U) +#define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK) +#define CCM_CCGR3_CG9_MASK (0xC0000U) +#define CCM_CCGR3_CG9_SHIFT (18U) +#define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK) +#define CCM_CCGR3_CG10_MASK (0x300000U) +#define CCM_CCGR3_CG10_SHIFT (20U) +#define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK) +#define CCM_CCGR3_CG11_MASK (0xC00000U) +#define CCM_CCGR3_CG11_SHIFT (22U) +#define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK) +#define CCM_CCGR3_CG12_MASK (0x3000000U) +#define CCM_CCGR3_CG12_SHIFT (24U) +#define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK) +#define CCM_CCGR3_CG13_MASK (0xC000000U) +#define CCM_CCGR3_CG13_SHIFT (26U) +#define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK) +#define CCM_CCGR3_CG14_MASK (0x30000000U) +#define CCM_CCGR3_CG14_SHIFT (28U) +#define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK) +#define CCM_CCGR3_CG15_MASK (0xC0000000U) +#define CCM_CCGR3_CG15_SHIFT (30U) +#define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK) +/*! @} */ + +/*! @name CCGR4 - CCM Clock Gating Register 4 */ +/*! @{ */ +#define CCM_CCGR4_CG0_MASK (0x3U) +#define CCM_CCGR4_CG0_SHIFT (0U) +#define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK) +#define CCM_CCGR4_CG1_MASK (0xCU) +#define CCM_CCGR4_CG1_SHIFT (2U) +#define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK) +#define CCM_CCGR4_CG2_MASK (0x30U) +#define CCM_CCGR4_CG2_SHIFT (4U) +#define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK) +#define CCM_CCGR4_CG3_MASK (0xC0U) +#define CCM_CCGR4_CG3_SHIFT (6U) +#define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK) +#define CCM_CCGR4_CG4_MASK (0x300U) +#define CCM_CCGR4_CG4_SHIFT (8U) +#define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK) +#define CCM_CCGR4_CG5_MASK (0xC00U) +#define CCM_CCGR4_CG5_SHIFT (10U) +#define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK) +#define CCM_CCGR4_CG6_MASK (0x3000U) +#define CCM_CCGR4_CG6_SHIFT (12U) +#define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK) +#define CCM_CCGR4_CG7_MASK (0xC000U) +#define CCM_CCGR4_CG7_SHIFT (14U) +#define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK) +#define CCM_CCGR4_CG8_MASK (0x30000U) +#define CCM_CCGR4_CG8_SHIFT (16U) +#define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK) +#define CCM_CCGR4_CG9_MASK (0xC0000U) +#define CCM_CCGR4_CG9_SHIFT (18U) +#define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK) +#define CCM_CCGR4_CG10_MASK (0x300000U) +#define CCM_CCGR4_CG10_SHIFT (20U) +#define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK) +#define CCM_CCGR4_CG11_MASK (0xC00000U) +#define CCM_CCGR4_CG11_SHIFT (22U) +#define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK) +#define CCM_CCGR4_CG12_MASK (0x3000000U) +#define CCM_CCGR4_CG12_SHIFT (24U) +#define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK) +#define CCM_CCGR4_CG13_MASK (0xC000000U) +#define CCM_CCGR4_CG13_SHIFT (26U) +#define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK) +#define CCM_CCGR4_CG14_MASK (0x30000000U) +#define CCM_CCGR4_CG14_SHIFT (28U) +#define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK) +#define CCM_CCGR4_CG15_MASK (0xC0000000U) +#define CCM_CCGR4_CG15_SHIFT (30U) +#define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK) +/*! @} */ + +/*! @name CCGR5 - CCM Clock Gating Register 5 */ +/*! @{ */ +#define CCM_CCGR5_CG0_MASK (0x3U) +#define CCM_CCGR5_CG0_SHIFT (0U) +#define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK) +#define CCM_CCGR5_CG1_MASK (0xCU) +#define CCM_CCGR5_CG1_SHIFT (2U) +#define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK) +#define CCM_CCGR5_CG2_MASK (0x30U) +#define CCM_CCGR5_CG2_SHIFT (4U) +#define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK) +#define CCM_CCGR5_CG3_MASK (0xC0U) +#define CCM_CCGR5_CG3_SHIFT (6U) +#define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK) +#define CCM_CCGR5_CG4_MASK (0x300U) +#define CCM_CCGR5_CG4_SHIFT (8U) +#define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK) +#define CCM_CCGR5_CG5_MASK (0xC00U) +#define CCM_CCGR5_CG5_SHIFT (10U) +#define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK) +#define CCM_CCGR5_CG6_MASK (0x3000U) +#define CCM_CCGR5_CG6_SHIFT (12U) +#define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK) +#define CCM_CCGR5_CG7_MASK (0xC000U) +#define CCM_CCGR5_CG7_SHIFT (14U) +#define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK) +#define CCM_CCGR5_CG8_MASK (0x30000U) +#define CCM_CCGR5_CG8_SHIFT (16U) +#define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK) +#define CCM_CCGR5_CG9_MASK (0xC0000U) +#define CCM_CCGR5_CG9_SHIFT (18U) +#define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK) +#define CCM_CCGR5_CG10_MASK (0x300000U) +#define CCM_CCGR5_CG10_SHIFT (20U) +#define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK) +#define CCM_CCGR5_CG11_MASK (0xC00000U) +#define CCM_CCGR5_CG11_SHIFT (22U) +#define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK) +#define CCM_CCGR5_CG12_MASK (0x3000000U) +#define CCM_CCGR5_CG12_SHIFT (24U) +#define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK) +#define CCM_CCGR5_CG13_MASK (0xC000000U) +#define CCM_CCGR5_CG13_SHIFT (26U) +#define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK) +#define CCM_CCGR5_CG14_MASK (0x30000000U) +#define CCM_CCGR5_CG14_SHIFT (28U) +#define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK) +#define CCM_CCGR5_CG15_MASK (0xC0000000U) +#define CCM_CCGR5_CG15_SHIFT (30U) +#define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK) +/*! @} */ + +/*! @name CCGR6 - CCM Clock Gating Register 6 */ +/*! @{ */ +#define CCM_CCGR6_CG0_MASK (0x3U) +#define CCM_CCGR6_CG0_SHIFT (0U) +#define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK) +#define CCM_CCGR6_CG1_MASK (0xCU) +#define CCM_CCGR6_CG1_SHIFT (2U) +#define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK) +#define CCM_CCGR6_CG2_MASK (0x30U) +#define CCM_CCGR6_CG2_SHIFT (4U) +#define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK) +#define CCM_CCGR6_CG3_MASK (0xC0U) +#define CCM_CCGR6_CG3_SHIFT (6U) +#define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK) +#define CCM_CCGR6_CG4_MASK (0x300U) +#define CCM_CCGR6_CG4_SHIFT (8U) +#define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK) +#define CCM_CCGR6_CG5_MASK (0xC00U) +#define CCM_CCGR6_CG5_SHIFT (10U) +#define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK) +#define CCM_CCGR6_CG6_MASK (0x3000U) +#define CCM_CCGR6_CG6_SHIFT (12U) +#define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK) +#define CCM_CCGR6_CG7_MASK (0xC000U) +#define CCM_CCGR6_CG7_SHIFT (14U) +#define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK) +#define CCM_CCGR6_CG8_MASK (0x30000U) +#define CCM_CCGR6_CG8_SHIFT (16U) +#define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK) +#define CCM_CCGR6_CG9_MASK (0xC0000U) +#define CCM_CCGR6_CG9_SHIFT (18U) +#define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK) +#define CCM_CCGR6_CG10_MASK (0x300000U) +#define CCM_CCGR6_CG10_SHIFT (20U) +#define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK) +#define CCM_CCGR6_CG11_MASK (0xC00000U) +#define CCM_CCGR6_CG11_SHIFT (22U) +#define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK) +#define CCM_CCGR6_CG12_MASK (0x3000000U) +#define CCM_CCGR6_CG12_SHIFT (24U) +#define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK) +#define CCM_CCGR6_CG13_MASK (0xC000000U) +#define CCM_CCGR6_CG13_SHIFT (26U) +#define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK) +#define CCM_CCGR6_CG14_MASK (0x30000000U) +#define CCM_CCGR6_CG14_SHIFT (28U) +#define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK) +#define CCM_CCGR6_CG15_MASK (0xC0000000U) +#define CCM_CCGR6_CG15_SHIFT (30U) +#define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK) +/*! @} */ + +/*! @name CCGR7 - CCM Clock Gating Register 7 */ +/*! @{ */ +#define CCM_CCGR7_CG0_MASK (0x3U) +#define CCM_CCGR7_CG0_SHIFT (0U) +#define CCM_CCGR7_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG0_SHIFT)) & CCM_CCGR7_CG0_MASK) +#define CCM_CCGR7_CG1_MASK (0xCU) +#define CCM_CCGR7_CG1_SHIFT (2U) +#define CCM_CCGR7_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG1_SHIFT)) & CCM_CCGR7_CG1_MASK) +#define CCM_CCGR7_CG2_MASK (0x30U) +#define CCM_CCGR7_CG2_SHIFT (4U) +#define CCM_CCGR7_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG2_SHIFT)) & CCM_CCGR7_CG2_MASK) +#define CCM_CCGR7_CG3_MASK (0xC0U) +#define CCM_CCGR7_CG3_SHIFT (6U) +#define CCM_CCGR7_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG3_SHIFT)) & CCM_CCGR7_CG3_MASK) +#define CCM_CCGR7_CG4_MASK (0x300U) +#define CCM_CCGR7_CG4_SHIFT (8U) +#define CCM_CCGR7_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG4_SHIFT)) & CCM_CCGR7_CG4_MASK) +#define CCM_CCGR7_CG5_MASK (0xC00U) +#define CCM_CCGR7_CG5_SHIFT (10U) +#define CCM_CCGR7_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG5_SHIFT)) & CCM_CCGR7_CG5_MASK) +#define CCM_CCGR7_CG6_MASK (0x3000U) +#define CCM_CCGR7_CG6_SHIFT (12U) +#define CCM_CCGR7_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG6_SHIFT)) & CCM_CCGR7_CG6_MASK) +/*! @} */ + +/*! @name CMEOR - CCM Module Enable Overide Register */ +/*! @{ */ +#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U) +#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U) +/*! MOD_EN_OV_GPT + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ +#define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK) +#define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U) +#define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U) +/*! MOD_EN_OV_PIT + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ +#define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK) +#define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U) +#define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U) +/*! MOD_EN_USDHC + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ +#define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK) +#define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U) +#define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U) +/*! MOD_EN_OV_TRNG + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ +#define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK) +#define CCM_CMEOR_MOD_EN_OV_CANFD_CPI_MASK (0x400U) +#define CCM_CMEOR_MOD_EN_OV_CANFD_CPI_SHIFT (10U) +/*! MOD_EN_OV_CANFD_CPI + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ +#define CCM_CMEOR_MOD_EN_OV_CANFD_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CANFD_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CANFD_CPI_MASK) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U) +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U) +/*! MOD_EN_OV_CAN2_CPI + * 0b0..don't override module enable signal + * 0b1..override module enable signal + */ +#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U) +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U) +/*! MOD_EN_OV_CAN1_CPI + * 0b0..don't overide module enable signal + * 0b1..overide module enable signal + */ +#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CCM_Register_Masks */ + + +/* CCM - Peripheral instance base addresses */ +/** Peripheral CCM base address */ +#define CCM_BASE (0x400FC000u) +/** Peripheral CCM base pointer */ +#define CCM ((CCM_Type *)CCM_BASE) +/** Array initializer of CCM peripheral base addresses */ +#define CCM_BASE_ADDRS { CCM_BASE } +/** Array initializer of CCM peripheral base pointers */ +#define CCM_BASE_PTRS { CCM } +/** Interrupt vectors for the CCM peripheral type */ +#define CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn } + +/*! + * @} + */ /* end of group CCM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer + * @{ + */ + +/** CCM_ANALOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t PLL_ARM; /**< Analog ARM PLL control Register, offset: 0x0 */ + __IO uint32_t PLL_ARM_SET; /**< Analog ARM PLL control Register, offset: 0x4 */ + __IO uint32_t PLL_ARM_CLR; /**< Analog ARM PLL control Register, offset: 0x8 */ + __IO uint32_t PLL_ARM_TOG; /**< Analog ARM PLL control Register, offset: 0xC */ + __IO uint32_t PLL_USB1; /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */ + __IO uint32_t PLL_USB1_SET; /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */ + __IO uint32_t PLL_USB1_CLR; /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */ + __IO uint32_t PLL_USB1_TOG; /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */ + __IO uint32_t PLL_USB2; /**< Analog USB2 480MHz PLL Control Register, offset: 0x20 */ + __IO uint32_t PLL_USB2_SET; /**< Analog USB2 480MHz PLL Control Register, offset: 0x24 */ + __IO uint32_t PLL_USB2_CLR; /**< Analog USB2 480MHz PLL Control Register, offset: 0x28 */ + __IO uint32_t PLL_USB2_TOG; /**< Analog USB2 480MHz PLL Control Register, offset: 0x2C */ + __IO uint32_t PLL_SYS; /**< Analog System PLL Control Register, offset: 0x30 */ + __IO uint32_t PLL_SYS_SET; /**< Analog System PLL Control Register, offset: 0x34 */ + __IO uint32_t PLL_SYS_CLR; /**< Analog System PLL Control Register, offset: 0x38 */ + __IO uint32_t PLL_SYS_TOG; /**< Analog System PLL Control Register, offset: 0x3C */ + __IO uint32_t PLL_SYS_SS; /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t PLL_SYS_NUM; /**< Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50 */ + uint8_t RESERVED_1[12]; + __IO uint32_t PLL_SYS_DENOM; /**< Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60 */ + uint8_t RESERVED_2[12]; + __IO uint32_t PLL_AUDIO; /**< Analog Audio PLL control Register, offset: 0x70 */ + __IO uint32_t PLL_AUDIO_SET; /**< Analog Audio PLL control Register, offset: 0x74 */ + __IO uint32_t PLL_AUDIO_CLR; /**< Analog Audio PLL control Register, offset: 0x78 */ + __IO uint32_t PLL_AUDIO_TOG; /**< Analog Audio PLL control Register, offset: 0x7C */ + __IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */ + uint8_t RESERVED_3[12]; + __IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */ + uint8_t RESERVED_4[12]; + __IO uint32_t PLL_VIDEO; /**< Analog Video PLL control Register, offset: 0xA0 */ + __IO uint32_t PLL_VIDEO_SET; /**< Analog Video PLL control Register, offset: 0xA4 */ + __IO uint32_t PLL_VIDEO_CLR; /**< Analog Video PLL control Register, offset: 0xA8 */ + __IO uint32_t PLL_VIDEO_TOG; /**< Analog Video PLL control Register, offset: 0xAC */ + __IO uint32_t PLL_VIDEO_NUM; /**< Numerator of Video PLL Fractional Loop Divider Register, offset: 0xB0 */ + uint8_t RESERVED_5[12]; + __IO uint32_t PLL_VIDEO_DENOM; /**< Denominator of Video PLL Fractional Loop Divider Register, offset: 0xC0 */ + uint8_t RESERVED_6[28]; + __IO uint32_t PLL_ENET; /**< Analog ENET PLL Control Register, offset: 0xE0 */ + __IO uint32_t PLL_ENET_SET; /**< Analog ENET PLL Control Register, offset: 0xE4 */ + __IO uint32_t PLL_ENET_CLR; /**< Analog ENET PLL Control Register, offset: 0xE8 */ + __IO uint32_t PLL_ENET_TOG; /**< Analog ENET PLL Control Register, offset: 0xEC */ + __IO uint32_t PFD_480; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */ + __IO uint32_t PFD_480_SET; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */ + __IO uint32_t PFD_480_CLR; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */ + __IO uint32_t PFD_480_TOG; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */ + __IO uint32_t PFD_528; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */ + __IO uint32_t PFD_528_SET; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */ + __IO uint32_t PFD_528_CLR; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */ + __IO uint32_t PFD_528_TOG; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */ + uint8_t RESERVED_7[64]; + __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ + __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ + __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ + __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ + __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */ + __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */ + __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */ + __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */ + __IO uint32_t MISC2; /**< Miscellaneous Register 2, offset: 0x170 */ + __IO uint32_t MISC2_SET; /**< Miscellaneous Register 2, offset: 0x174 */ + __IO uint32_t MISC2_CLR; /**< Miscellaneous Register 2, offset: 0x178 */ + __IO uint32_t MISC2_TOG; /**< Miscellaneous Register 2, offset: 0x17C */ +} CCM_ANALOG_Type; + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks + * @{ + */ + +/*! @name PLL_ARM - Analog ARM PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ARM_SET - Analog ARM PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ARM_CLR - Analog ARM PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ARM_TOG - Analog ARM PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U) +#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ +#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ +#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ +#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U) +/*! EN_USB_CLKS + * 0b0..PLL outputs for USBPHYn off. + * 0b1..PLL outputs for USBPHYn on. + */ +#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB2 - Analog USB2 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB2_SET - Analog USB2 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x2U) +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (1U) +#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U) +#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U) +#define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U) +#define CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_SET - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_CLR - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_TOG - Analog System PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U) +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + */ +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU) +#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U) +#define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U) +/*! ENABLE - Enable bit + * 0b0..Spread spectrum modulation disabled + * 0b1..Soread spectrum modulation enabled + */ +#define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK) +#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U) +#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U) +#define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK) +/*! @} */ + +/*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK) +/*! @} */ + +/*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK) +/*! @} */ + +/*! @name PLL_AUDIO - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) +/*! @} */ + +/*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) +/*! @} */ + +/*! @name PLL_VIDEO - Analog Video PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_SET - Analog Video PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_CLR - Analog Video PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_TOG - Analog Video PLL control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU) +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U) +/*! POST_DIV_SELECT + * 0b00..Divide by 4. + * 0b01..Divide by 2. + * 0b10..Divide by 1. + * 0b11..Reserved + */ +#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK) +/*! @} */ + +/*! @name PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU) +#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U) +#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK) +/*! @} */ + +/*! @name PLL_ENET - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_SHIFT (2U) +/*! ENET2_DIV_SELECT + * 0b00..25MHz + * 0b01..50MHz + * 0b10..100MHz (not 50% duty cycle) + * 0b11..125MHz + */ +#define CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_ENET2_REF_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ENET_SET - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_SHIFT (2U) +/*! ENET2_DIV_SELECT + * 0b00..25MHz + * 0b01..50MHz + * 0b10..100MHz (not 50% duty cycle) + * 0b11..125MHz + */ +#define CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_SHIFT (2U) +/*! ENET2_DIV_SELECT + * 0b00..25MHz + * 0b01..50MHz + * 0b10..100MHz (not 50% duty cycle) + * 0b11..125MHz + */ +#define CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK) +/*! @} */ + +/*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */ +/*! @{ */ +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U) +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U) +#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_MASK (0xCU) +#define CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_SHIFT (2U) +/*! ENET2_DIV_SELECT + * 0b00..25MHz + * 0b01..50MHz + * 0b10..100MHz (not 50% duty cycle) + * 0b11..125MHz + */ +#define CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U) +#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U) +#define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U) +/*! BYPASS_CLK_SRC + * 0b00..Select the 24MHz oscillator as source. + * 0b01..Select the CLK1_N / CLK1_P as source. + * 0b10..Reserved1 + * 0b11..Reserved2 + */ +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_MASK (0x100000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_SHIFT (20U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U) +#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U) +#define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK) +/*! @} */ + +/*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */ +/*! @{ */ +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU) +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U) +#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U) +#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U) +#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U) +#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK) +/*! @} */ + +/*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except RTC powered down on stop mode assertion. + * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog + * bandgap together with the rest analog is powered down. + * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down. + */ +#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK) +#define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except RTC powered down on stop mode assertion. + * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog + * bandgap together with the rest analog is powered down. + * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down. + */ +#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except RTC powered down on stop mode assertion. + * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog + * bandgap together with the rest analog is powered down. + * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down. + */ +#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) +#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except RTC powered down on stop mode assertion. + * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog + * bandgap together with the rest analog is powered down. + * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down. + */ +#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U) +#define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) +#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) +#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK) +/*! @} */ + +/*! @name MISC1 - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_SET - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_CLR - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_TOG - Miscellaneous Register 1 */ +/*! @{ */ +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U) +#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U) +#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U) +#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) +#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC2 - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_PLL3_DISABLE_MASK (0x80U) +#define CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT (7U) +/*! PLL3_DISABLE + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ +#define CCM_ANALOG_MISC2_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_PLL3_DISABLE_MASK) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_SET - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK (0x80U) +#define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT (7U) +/*! PLL3_DISABLE + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ +#define CCM_ANALOG_MISC2_SET_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_CLR - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK (0x80U) +#define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT (7U) +/*! PLL3_DISABLE + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ +#define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_TOG - Miscellaneous Register 2 */ +/*! @{ */ +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) +#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U) +#define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U) +#define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK (0x80U) +#define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT (7U) +/*! PLL3_DISABLE + * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + * 0b1..PLL3 can be disabled when the SoC is not in any low power mode + */ +#define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) +#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U) +#define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U) +#define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) +#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U) +#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U) +#define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U) +#define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CCM_ANALOG_Register_Masks */ + + +/* CCM_ANALOG - Peripheral instance base addresses */ +/** Peripheral CCM_ANALOG base address */ +#define CCM_ANALOG_BASE (0x400D8000u) +/** Peripheral CCM_ANALOG base pointer */ +#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE) +/** Array initializer of CCM_ANALOG peripheral base addresses */ +#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE } +/** Array initializer of CCM_ANALOG peripheral base pointers */ +#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG } + +/*! + * @} + */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer + * @{ + */ + +/** CMP - Register Layout Typedef */ +typedef struct { + __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ + __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ + __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ + __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ + __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ + __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ +} CMP_Type; + +/* ---------------------------------------------------------------------------- + -- CMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMP_Register_Masks CMP Register Masks + * @{ + */ + +/*! @name CR0 - CMP Control Register 0 */ +/*! @{ */ +#define CMP_CR0_HYSTCTR_MASK (0x3U) +#define CMP_CR0_HYSTCTR_SHIFT (0U) +/*! HYSTCTR - Comparator hard block hysteresis control + * 0b00..Level 0 + * 0b01..Level 1 + * 0b10..Level 2 + * 0b11..Level 3 + */ +#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) +#define CMP_CR0_FILTER_CNT_MASK (0x70U) +#define CMP_CR0_FILTER_CNT_SHIFT (4U) +/*! FILTER_CNT - Filter Sample Count + * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. + * 0b001..One sample must agree. The comparator output is simply sampled. + * 0b010..2 consecutive samples must agree. + * 0b011..3 consecutive samples must agree. + * 0b100..4 consecutive samples must agree. + * 0b101..5 consecutive samples must agree. + * 0b110..6 consecutive samples must agree. + * 0b111..7 consecutive samples must agree. + */ +#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) +/*! @} */ + +/*! @name CR1 - CMP Control Register 1 */ +/*! @{ */ +#define CMP_CR1_EN_MASK (0x1U) +#define CMP_CR1_EN_SHIFT (0U) +/*! EN - Comparator Module Enable + * 0b0..Analog Comparator is disabled. + * 0b1..Analog Comparator is enabled. + */ +#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) +#define CMP_CR1_OPE_MASK (0x2U) +#define CMP_CR1_OPE_SHIFT (1U) +/*! OPE - Comparator Output Pin Enable + * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. + * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the + * associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this + * bit has no effect. + */ +#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) +#define CMP_CR1_COS_MASK (0x4U) +#define CMP_CR1_COS_SHIFT (2U) +/*! COS - Comparator Output Select + * 0b0..Set the filtered comparator output (CMPO) to equal COUT. + * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA. + */ +#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) +#define CMP_CR1_INV_MASK (0x8U) +#define CMP_CR1_INV_SHIFT (3U) +/*! INV - Comparator INVERT + * 0b0..Does not invert the comparator output. + * 0b1..Inverts the comparator output. + */ +#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) +#define CMP_CR1_PMODE_MASK (0x10U) +#define CMP_CR1_PMODE_SHIFT (4U) +/*! PMODE - Power Mode Select + * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. + * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. + */ +#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) +#define CMP_CR1_WE_MASK (0x40U) +#define CMP_CR1_WE_SHIFT (6U) +/*! WE - Windowing Enable + * 0b0..Windowing mode is not selected. + * 0b1..Windowing mode is selected. + */ +#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) +#define CMP_CR1_SE_MASK (0x80U) +#define CMP_CR1_SE_SHIFT (7U) +/*! SE - Sample Enable + * 0b0..Sampling mode is not selected. + * 0b1..Sampling mode is selected. + */ +#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) +/*! @} */ + +/*! @name FPR - CMP Filter Period Register */ +/*! @{ */ +#define CMP_FPR_FILT_PER_MASK (0xFFU) +#define CMP_FPR_FILT_PER_SHIFT (0U) +#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) +/*! @} */ + +/*! @name SCR - CMP Status and Control Register */ +/*! @{ */ +#define CMP_SCR_COUT_MASK (0x1U) +#define CMP_SCR_COUT_SHIFT (0U) +#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) +#define CMP_SCR_CFF_MASK (0x2U) +#define CMP_SCR_CFF_SHIFT (1U) +/*! CFF - Analog Comparator Flag Falling + * 0b0..Falling-edge on COUT has not been detected. + * 0b1..Falling-edge on COUT has occurred. + */ +#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) +#define CMP_SCR_CFR_MASK (0x4U) +#define CMP_SCR_CFR_SHIFT (2U) +/*! CFR - Analog Comparator Flag Rising + * 0b0..Rising-edge on COUT has not been detected. + * 0b1..Rising-edge on COUT has occurred. + */ +#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) +#define CMP_SCR_IEF_MASK (0x8U) +#define CMP_SCR_IEF_SHIFT (3U) +/*! IEF - Comparator Interrupt Enable Falling + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) +#define CMP_SCR_IER_MASK (0x10U) +#define CMP_SCR_IER_SHIFT (4U) +/*! IER - Comparator Interrupt Enable Rising + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. + */ +#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) +#define CMP_SCR_DMAEN_MASK (0x40U) +#define CMP_SCR_DMAEN_SHIFT (6U) +/*! DMAEN - DMA Enable Control + * 0b0..DMA is disabled. + * 0b1..DMA is enabled. + */ +#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) +/*! @} */ + +/*! @name DACCR - DAC Control Register */ +/*! @{ */ +#define CMP_DACCR_VOSEL_MASK (0x3FU) +#define CMP_DACCR_VOSEL_SHIFT (0U) +#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) +#define CMP_DACCR_VRSEL_MASK (0x40U) +#define CMP_DACCR_VRSEL_SHIFT (6U) +/*! VRSEL - Supply Voltage Reference Source Select + * 0b0..Vin1 is selected as resistor ladder network supply reference. + * 0b1..Vin2 is selected as resistor ladder network supply reference. + */ +#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) +#define CMP_DACCR_DACEN_MASK (0x80U) +#define CMP_DACCR_DACEN_SHIFT (7U) +/*! DACEN - DAC Enable + * 0b0..DAC is disabled. + * 0b1..DAC is enabled. + */ +#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) +/*! @} */ + +/*! @name MUXCR - MUX Control Register */ +/*! @{ */ +#define CMP_MUXCR_MSEL_MASK (0x7U) +#define CMP_MUXCR_MSEL_SHIFT (0U) +/*! MSEL - Minus Input Mux Control + * 0b000..IN0 + * 0b001..IN1 + * 0b010..IN2 + * 0b011..IN3 + * 0b100..IN4 + * 0b101..IN5 + * 0b110..IN6 + * 0b111..IN7 + */ +#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) +#define CMP_MUXCR_PSEL_MASK (0x38U) +#define CMP_MUXCR_PSEL_SHIFT (3U) +/*! PSEL - Plus Input Mux Control + * 0b000..IN0 + * 0b001..IN1 + * 0b010..IN2 + * 0b011..IN3 + * 0b100..IN4 + * 0b101..IN5 + * 0b110..IN6 + * 0b111..IN7 + */ +#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CMP_Register_Masks */ + + +/* CMP - Peripheral instance base addresses */ +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x40094000u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((CMP_Type *)CMP1_BASE) +/** Peripheral CMP2 base address */ +#define CMP2_BASE (0x40094008u) +/** Peripheral CMP2 base pointer */ +#define CMP2 ((CMP_Type *)CMP2_BASE) +/** Peripheral CMP3 base address */ +#define CMP3_BASE (0x40094010u) +/** Peripheral CMP3 base pointer */ +#define CMP3 ((CMP_Type *)CMP3_BASE) +/** Peripheral CMP4 base address */ +#define CMP4_BASE (0x40094018u) +/** Peripheral CMP4 base pointer */ +#define CMP4 ((CMP_Type *)CMP4_BASE) +/** Array initializer of CMP peripheral base addresses */ +#define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE } +/** Array initializer of CMP peripheral base pointers */ +#define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 } +/** Interrupt vectors for the CMP peripheral type */ +#define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn } + +/*! + * @} + */ /* end of group CMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CSU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSU_Peripheral_Access_Layer CSU Peripheral Access Layer + * @{ + */ + +/** CSU - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSL[32]; /**< Config security level register, array offset: 0x0, array step: 0x4 */ + uint8_t RESERVED_0[384]; + __IO uint32_t HP0; /**< HP0 register, offset: 0x200 */ + uint8_t RESERVED_1[20]; + __IO uint32_t SA; /**< Secure access register, offset: 0x218 */ + uint8_t RESERVED_2[316]; + __IO uint32_t HPCONTROL0; /**< HPCONTROL0 register, offset: 0x358 */ +} CSU_Type; + +/* ---------------------------------------------------------------------------- + -- CSU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSU_Register_Masks CSU Register Masks + * @{ + */ + +/*! @name CSL - Config security level register */ +/*! @{ */ +#define CSU_CSL_SUR_S2_MASK (0x1U) +#define CSU_CSL_SUR_S2_SHIFT (0U) +/*! SUR_S2 + * 0b0..The secure user read access is disabled for the second slave. + * 0b1..The secure user read access is enabled for the second slave. + */ +#define CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK) +#define CSU_CSL_SSR_S2_MASK (0x2U) +#define CSU_CSL_SSR_S2_SHIFT (1U) +/*! SSR_S2 + * 0b0..The secure supervisor read access is disabled for the second slave. + * 0b1..The secure supervisor read access is enabled for the second slave. + */ +#define CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK) +#define CSU_CSL_NUR_S2_MASK (0x4U) +#define CSU_CSL_NUR_S2_SHIFT (2U) +/*! NUR_S2 + * 0b0..The non-secure user read access is disabled for the second slave. + * 0b1..The non-secure user read access is enabled for the second slave. + */ +#define CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK) +#define CSU_CSL_NSR_S2_MASK (0x8U) +#define CSU_CSL_NSR_S2_SHIFT (3U) +/*! NSR_S2 + * 0b0..The non-secure supervisor read access is disabled for the second slave. + * 0b1..The non-secure supervisor read access is enabled for the second slave. + */ +#define CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK) +#define CSU_CSL_SUW_S2_MASK (0x10U) +#define CSU_CSL_SUW_S2_SHIFT (4U) +/*! SUW_S2 + * 0b0..The secure user write access is disabled for the second slave. + * 0b1..The secure user write access is enabled for the second slave. + */ +#define CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK) +#define CSU_CSL_SSW_S2_MASK (0x20U) +#define CSU_CSL_SSW_S2_SHIFT (5U) +/*! SSW_S2 + * 0b0..The secure supervisor write access is disabled for the second slave. + * 0b1..The secure supervisor write access is enabled for the second slave. + */ +#define CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK) +#define CSU_CSL_NUW_S2_MASK (0x40U) +#define CSU_CSL_NUW_S2_SHIFT (6U) +/*! NUW_S2 + * 0b0..The non-secure user write access is disabled for the second slave. + * 0b1..The non-secure user write access is enabled for the second slave. + */ +#define CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK) +#define CSU_CSL_NSW_S2_MASK (0x80U) +#define CSU_CSL_NSW_S2_SHIFT (7U) +/*! NSW_S2 + * 0b0..The non-secure supervisor write access is disabled for the second slave. + * 0b1..The non-secure supervisor write access is enabled for the second slave. + */ +#define CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK) +#define CSU_CSL_LOCK_S2_MASK (0x100U) +#define CSU_CSL_LOCK_S2_SHIFT (8U) +/*! LOCK_S2 + * 0b0..Not locked. Bits 7-0 can be written by the software. + * 0b1..Bits 7-0 are locked and cannot be written by the software + */ +#define CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK) +#define CSU_CSL_SUR_S1_MASK (0x10000U) +#define CSU_CSL_SUR_S1_SHIFT (16U) +/*! SUR_S1 + * 0b0..The secure user read access is disabled for the first slave. + * 0b1..The secure user read access is enabled for the first slave. + */ +#define CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK) +#define CSU_CSL_SSR_S1_MASK (0x20000U) +#define CSU_CSL_SSR_S1_SHIFT (17U) +/*! SSR_S1 + * 0b0..The secure supervisor read access is disabled for the first slave. + * 0b1..The secure supervisor read access is enabled for the first slave. + */ +#define CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK) +#define CSU_CSL_NUR_S1_MASK (0x40000U) +#define CSU_CSL_NUR_S1_SHIFT (18U) +/*! NUR_S1 + * 0b0..The non-secure user read access is disabled for the first slave. + * 0b1..The non-secure user read access is enabled for the first slave. + */ +#define CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK) +#define CSU_CSL_NSR_S1_MASK (0x80000U) +#define CSU_CSL_NSR_S1_SHIFT (19U) +/*! NSR_S1 + * 0b0..The non-secure supervisor read access is disabled for the first slave. + * 0b1..The non-secure supervisor read access is enabled for the first slave. + */ +#define CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK) +#define CSU_CSL_SUW_S1_MASK (0x100000U) +#define CSU_CSL_SUW_S1_SHIFT (20U) +/*! SUW_S1 + * 0b0..The secure user write access is disabled for the first slave. + * 0b1..The secure user write access is enabled for the first slave. + */ +#define CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK) +#define CSU_CSL_SSW_S1_MASK (0x200000U) +#define CSU_CSL_SSW_S1_SHIFT (21U) +/*! SSW_S1 + * 0b0..The secure supervisor write access is disabled for the first slave. + * 0b1..The secure supervisor write access is enabled for the first slave. + */ +#define CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK) +#define CSU_CSL_NUW_S1_MASK (0x400000U) +#define CSU_CSL_NUW_S1_SHIFT (22U) +/*! NUW_S1 + * 0b0..The non-secure user write access is disabled for the first slave. + * 0b1..The non-secure user write access is enabled for the first slave. + */ +#define CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK) +#define CSU_CSL_NSW_S1_MASK (0x800000U) +#define CSU_CSL_NSW_S1_SHIFT (23U) +/*! NSW_S1 + * 0b0..The non-secure supervisor write access is disabled for the first slave. + * 0b1..The non-secure supervisor write access is enabled for the first slave + */ +#define CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK) +#define CSU_CSL_LOCK_S1_MASK (0x1000000U) +#define CSU_CSL_LOCK_S1_SHIFT (24U) +/*! LOCK_S1 + * 0b0..Not locked. The bits 16-23 can be written by the software. + * 0b1..The bits 16-23 are locked and can't be written by the software. + */ +#define CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK) +/*! @} */ + +/* The count of CSU_CSL */ +#define CSU_CSL_COUNT (32U) + +/*! @name HP0 - HP0 register */ +/*! @{ */ +#define CSU_HP0_HP_DMA_MASK (0x4U) +#define CSU_HP0_HP_DMA_SHIFT (2U) +/*! HP_DMA + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK) +#define CSU_HP0_L_DMA_MASK (0x8U) +#define CSU_HP0_L_DMA_SHIFT (3U) +/*! L_DMA + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK) +#define CSU_HP0_HP_LCDIF_MASK (0x10U) +#define CSU_HP0_HP_LCDIF_SHIFT (4U) +/*! HP_LCDIF + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK) +#define CSU_HP0_L_LCDIF_MASK (0x20U) +#define CSU_HP0_L_LCDIF_SHIFT (5U) +/*! L_LCDIF + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK) +#define CSU_HP0_HP_CSI_MASK (0x40U) +#define CSU_HP0_HP_CSI_SHIFT (6U) +/*! HP_CSI + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK) +#define CSU_HP0_L_CSI_MASK (0x80U) +#define CSU_HP0_L_CSI_SHIFT (7U) +/*! L_CSI + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK) +#define CSU_HP0_HP_PXP_MASK (0x100U) +#define CSU_HP0_HP_PXP_SHIFT (8U) +/*! HP_PXP + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK) +#define CSU_HP0_L_PXP_MASK (0x200U) +#define CSU_HP0_L_PXP_SHIFT (9U) +/*! L_PXP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK) +#define CSU_HP0_HP_DCP_MASK (0x400U) +#define CSU_HP0_HP_DCP_SHIFT (10U) +/*! HP_DCP + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK) +#define CSU_HP0_L_DCP_MASK (0x800U) +#define CSU_HP0_L_DCP_SHIFT (11U) +/*! L_DCP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit cannot be written by the software. + */ +#define CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK) +#define CSU_HP0_HP_ENET_MASK (0x4000U) +#define CSU_HP0_HP_ENET_SHIFT (14U) +/*! HP_ENET + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK) +#define CSU_HP0_L_ENET_MASK (0x8000U) +#define CSU_HP0_L_ENET_SHIFT (15U) +/*! L_ENET + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK) +#define CSU_HP0_HP_USDHC1_MASK (0x10000U) +#define CSU_HP0_HP_USDHC1_SHIFT (16U) +/*! HP_USDHC1 + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK) +#define CSU_HP0_L_USDHC1_MASK (0x20000U) +#define CSU_HP0_L_USDHC1_SHIFT (17U) +/*! L_USDHC1 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK) +#define CSU_HP0_HP_USDHC2_MASK (0x40000U) +#define CSU_HP0_HP_USDHC2_SHIFT (18U) +/*! HP_USDHC2 + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK) +#define CSU_HP0_L_USDHC2_MASK (0x80000U) +#define CSU_HP0_L_USDHC2_SHIFT (19U) +/*! L_USDHC2 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK) +#define CSU_HP0_HP_TPSMP_MASK (0x100000U) +#define CSU_HP0_HP_TPSMP_SHIFT (20U) +/*! HP_TPSMP + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK) +#define CSU_HP0_L_TPSMP_MASK (0x200000U) +#define CSU_HP0_L_TPSMP_SHIFT (21U) +/*! L_TPSMP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK) +#define CSU_HP0_HP_USB_MASK (0x400000U) +#define CSU_HP0_HP_USB_SHIFT (22U) +/*! HP_USB + * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master. + */ +#define CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK) +#define CSU_HP0_L_USB_MASK (0x800000U) +#define CSU_HP0_L_USB_SHIFT (23U) +/*! L_USB + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK) +/*! @} */ + +/*! @name SA - Secure access register */ +/*! @{ */ +#define CSU_SA_NSA_DMA_MASK (0x4U) +#define CSU_SA_NSA_DMA_SHIFT (2U) +/*! NSA_DMA - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK) +#define CSU_SA_L_DMA_MASK (0x8U) +#define CSU_SA_L_DMA_SHIFT (3U) +/*! L_DMA + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK) +#define CSU_SA_NSA_LCDIF_MASK (0x10U) +#define CSU_SA_NSA_LCDIF_SHIFT (4U) +/*! NSA_LCDIF - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK) +#define CSU_SA_L_LCDIF_MASK (0x20U) +#define CSU_SA_L_LCDIF_SHIFT (5U) +/*! L_LCDIF + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK) +#define CSU_SA_NSA_CSI_MASK (0x40U) +#define CSU_SA_NSA_CSI_SHIFT (6U) +/*! NSA_CSI - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK) +#define CSU_SA_L_CSI_MASK (0x80U) +#define CSU_SA_L_CSI_SHIFT (7U) +/*! L_CSI + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK) +#define CSU_SA_NSA_PXP_MASK (0x100U) +#define CSU_SA_NSA_PXP_SHIFT (8U) +/*! NSA_PXP - Non-Secure Access Policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK) +#define CSU_SA_L_PXP_MASK (0x200U) +#define CSU_SA_L_PXP_SHIFT (9U) +/*! L_PXP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK) +#define CSU_SA_NSA_DCP_MASK (0x400U) +#define CSU_SA_NSA_DCP_SHIFT (10U) +/*! NSA_DCP - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK) +#define CSU_SA_L_DCP_MASK (0x800U) +#define CSU_SA_L_DCP_SHIFT (11U) +/*! L_DCP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK) +#define CSU_SA_NSA_ENET_MASK (0x4000U) +#define CSU_SA_NSA_ENET_SHIFT (14U) +/*! NSA_ENET - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK) +#define CSU_SA_L_ENET_MASK (0x8000U) +#define CSU_SA_L_ENET_SHIFT (15U) +/*! L_ENET + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK) +#define CSU_SA_NSA_USDHC1_MASK (0x10000U) +#define CSU_SA_NSA_USDHC1_SHIFT (16U) +/*! NSA_USDHC1 - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK) +#define CSU_SA_L_USDHC1_MASK (0x20000U) +#define CSU_SA_L_USDHC1_SHIFT (17U) +/*! L_USDHC1 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK) +#define CSU_SA_NSA_USDHC2_MASK (0x40000U) +#define CSU_SA_NSA_USDHC2_SHIFT (18U) +/*! NSA_USDHC2 - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK) +#define CSU_SA_L_USDHC2_MASK (0x80000U) +#define CSU_SA_L_USDHC2_SHIFT (19U) +/*! L_USDHC2 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK) +#define CSU_SA_NSA_TPSMP_MASK (0x100000U) +#define CSU_SA_NSA_TPSMP_SHIFT (20U) +/*! NSA_TPSMP - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK) +#define CSU_SA_L_TPSMP_MASK (0x200000U) +#define CSU_SA_L_TPSMP_SHIFT (21U) +/*! L_TPSMP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK) +#define CSU_SA_NSA_USB_MASK (0x400000U) +#define CSU_SA_NSA_USB_SHIFT (22U) +/*! NSA_USB - Non-secure access policy indicator bit + * 0b0..Secure access for the corresponding type-1 master + * 0b1..Non-secure access for the corresponding type-1 master + */ +#define CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK) +#define CSU_SA_L_USB_MASK (0x800000U) +#define CSU_SA_L_USB_SHIFT (23U) +/*! L_USB + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK) +/*! @} */ + +/*! @name HPCONTROL0 - HPCONTROL0 register */ +/*! @{ */ +#define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U) +#define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U) +/*! HPC_DMA + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK) +#define CSU_HPCONTROL0_L_DMA_MASK (0x8U) +#define CSU_HPCONTROL0_L_DMA_SHIFT (3U) +/*! L_DMA + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK) +#define CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U) +#define CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U) +/*! HPC_LCDIF + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK) +#define CSU_HPCONTROL0_L_LCDIF_MASK (0x20U) +#define CSU_HPCONTROL0_L_LCDIF_SHIFT (5U) +/*! L_LCDIF + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK) +#define CSU_HPCONTROL0_HPC_CSI_MASK (0x40U) +#define CSU_HPCONTROL0_HPC_CSI_SHIFT (6U) +/*! HPC_CSI + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK) +#define CSU_HPCONTROL0_L_CSI_MASK (0x80U) +#define CSU_HPCONTROL0_L_CSI_SHIFT (7U) +/*! L_CSI + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK) +#define CSU_HPCONTROL0_HPC_PXP_MASK (0x100U) +#define CSU_HPCONTROL0_HPC_PXP_SHIFT (8U) +/*! HPC_PXP + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK) +#define CSU_HPCONTROL0_L_PXP_MASK (0x200U) +#define CSU_HPCONTROL0_L_PXP_SHIFT (9U) +/*! L_PXP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK) +#define CSU_HPCONTROL0_HPC_DCP_MASK (0x400U) +#define CSU_HPCONTROL0_HPC_DCP_SHIFT (10U) +/*! HPC_DCP + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK) +#define CSU_HPCONTROL0_L_DCP_MASK (0x800U) +#define CSU_HPCONTROL0_L_DCP_SHIFT (11U) +/*! L_DCP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK) +#define CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U) +#define CSU_HPCONTROL0_HPC_ENET_SHIFT (14U) +/*! HPC_ENET + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK) +#define CSU_HPCONTROL0_L_ENET_MASK (0x8000U) +#define CSU_HPCONTROL0_L_ENET_SHIFT (15U) +/*! L_ENET + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK) +#define CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U) +#define CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U) +/*! HPC_USDHC1 + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK) +#define CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U) +#define CSU_HPCONTROL0_L_USDHC1_SHIFT (17U) +/*! L_USDHC1 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK) +#define CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U) +#define CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U) +/*! HPC_USDHC2 + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK) +#define CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U) +#define CSU_HPCONTROL0_L_USDHC2_SHIFT (19U) +/*! L_USDHC2 + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK) +#define CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U) +#define CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U) +/*! HPC_TPSMP + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK) +#define CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U) +#define CSU_HPCONTROL0_L_TPSMP_SHIFT (21U) +/*! L_TPSMP + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK) +#define CSU_HPCONTROL0_HPC_USB_MASK (0x400000U) +#define CSU_HPCONTROL0_HPC_USB_SHIFT (22U) +/*! HPC_USB + * 0b0..User mode for the corresponding master + * 0b1..Supervisor mode for the corresponding master + */ +#define CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK) +#define CSU_HPCONTROL0_L_USB_MASK (0x800000U) +#define CSU_HPCONTROL0_L_USB_SHIFT (23U) +/*! L_USB + * 0b0..No lock-the adjacent (next lower) bit can be written by the software. + * 0b1..Lock-the adjacent (next lower) bit can't be written by the software. + */ +#define CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CSU_Register_Masks */ + + +/* CSU - Peripheral instance base addresses */ +/** Peripheral CSU base address */ +#define CSU_BASE (0x400DC000u) +/** Peripheral CSU base pointer */ +#define CSU ((CSU_Type *)CSU_BASE) +/** Array initializer of CSU peripheral base addresses */ +#define CSU_BASE_ADDRS { CSU_BASE } +/** Array initializer of CSU peripheral base pointers */ +#define CSU_BASE_PTRS { CSU } + +/*! + * @} + */ /* end of group CSU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DCDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer + * @{ + */ + +/** DCDC - Register Layout Typedef */ +typedef struct { + __IO uint32_t REG0; /**< DCDC Register 0, offset: 0x0 */ + __IO uint32_t REG1; /**< DCDC Register 1, offset: 0x4 */ + __IO uint32_t REG2; /**< DCDC Register 2, offset: 0x8 */ + __IO uint32_t REG3; /**< DCDC Register 3, offset: 0xC */ +} DCDC_Type; + +/* ---------------------------------------------------------------------------- + -- DCDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCDC_Register_Masks DCDC Register Masks + * @{ + */ + +/*! @name REG0 - DCDC Register 0 */ +/*! @{ */ +#define DCDC_REG0_PWD_ZCD_MASK (0x1U) +#define DCDC_REG0_PWD_ZCD_SHIFT (0U) +#define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK) +#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) +#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U) +#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK) +#define DCDC_REG0_SEL_CLK_MASK (0x4U) +#define DCDC_REG0_SEL_CLK_SHIFT (2U) +#define DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK) +#define DCDC_REG0_PWD_OSC_INT_MASK (0x8U) +#define DCDC_REG0_PWD_OSC_INT_SHIFT (3U) +#define DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK) +#define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U) +#define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U) +#define DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK) +#define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U) +#define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U) +#define DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK) +#define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U) +#define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U) +#define DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK) +#define DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U) +#define DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U) +#define DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK) +#define DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U) +#define DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U) +#define DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK) +#define DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U) +#define DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U) +#define DCDC_REG0_ADJ_POSLIMIT_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK) +#define DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U) +#define DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U) +#define DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK) +#define DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U) +#define DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U) +#define DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK) +#define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U) +#define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U) +#define DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK) +#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U) +#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U) +#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK) +#define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U) +#define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U) +#define DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK) +#define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U) +#define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U) +#define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK) +#define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U) +#define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U) +#define DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK) +#define DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U) +#define DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U) +#define DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK) +#define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U) +#define DCDC_REG0_XTAL_24M_OK_SHIFT (29U) +#define DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK) +#define DCDC_REG0_STS_DC_OK_MASK (0x80000000U) +#define DCDC_REG0_STS_DC_OK_SHIFT (31U) +#define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK) +/*! @} */ + +/*! @name REG1 - DCDC Register 1 */ +/*! @{ */ +#define DCDC_REG1_REG_FBK_SEL_MASK (0x180U) +#define DCDC_REG1_REG_FBK_SEL_SHIFT (7U) +#define DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK) +#define DCDC_REG1_REG_RLOAD_SW_MASK (0x200U) +#define DCDC_REG1_REG_RLOAD_SW_SHIFT (9U) +#define DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK) +#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U) +#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U) +#define DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK) +#define DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U) +#define DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U) +#define DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK) +#define DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U) +#define DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U) +#define DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK) +#define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U) +#define DCDC_REG1_VBG_TRIM_SHIFT (24U) +#define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK) +/*! @} */ + +/*! @name REG2 - DCDC Register 2 */ +/*! @{ */ +#define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U) +#define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U) +#define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK) +#define DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU) +#define DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U) +#define DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK) +#define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U) +#define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U) +#define DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK) +#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U) +#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U) +#define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK) +#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U) +#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U) +#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK) +#define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U) +#define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U) +#define DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK) +#define DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U) +#define DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U) +#define DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK) +#define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U) +#define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U) +#define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK) +/*! @} */ + +/*! @name REG3 - DCDC Register 3 */ +/*! @{ */ +#define DCDC_REG3_TRG_MASK (0x1FU) +#define DCDC_REG3_TRG_SHIFT (0U) +#define DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK) +#define DCDC_REG3_TARGET_LP_MASK (0x700U) +#define DCDC_REG3_TARGET_LP_SHIFT (8U) +#define DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK) +#define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) +#define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U) +#define DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK) +#define DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U) +#define DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U) +#define DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK) +#define DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U) +#define DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U) +#define DCDC_REG3_MISC_DISABLEFET_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK) +#define DCDC_REG3_DISABLE_STEP_MASK (0x40000000U) +#define DCDC_REG3_DISABLE_STEP_SHIFT (30U) +#define DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DCDC_Register_Masks */ + + +/* DCDC - Peripheral instance base addresses */ +/** Peripheral DCDC base address */ +#define DCDC_BASE (0x40080000u) +/** Peripheral DCDC base pointer */ +#define DCDC ((DCDC_Type *)DCDC_BASE) +/** Array initializer of DCDC peripheral base addresses */ +#define DCDC_BASE_ADDRS { DCDC_BASE } +/** Array initializer of DCDC peripheral base pointers */ +#define DCDC_BASE_PTRS { DCDC } +/** Interrupt vectors for the DCDC peripheral type */ +#define DCDC_IRQS { DCDC_IRQn } + +/*! + * @} + */ /* end of group DCDC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DCP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCP_Peripheral_Access_Layer DCP Peripheral Access Layer + * @{ + */ + +/** DCP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DCP control register 0, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< DCP control register 0, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< DCP control register 0, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< DCP control register 0, offset: 0xC */ + __IO uint32_t STAT; /**< DCP status register, offset: 0x10 */ + __IO uint32_t STAT_SET; /**< DCP status register, offset: 0x14 */ + __IO uint32_t STAT_CLR; /**< DCP status register, offset: 0x18 */ + __IO uint32_t STAT_TOG; /**< DCP status register, offset: 0x1C */ + __IO uint32_t CHANNELCTRL; /**< DCP channel control register, offset: 0x20 */ + __IO uint32_t CHANNELCTRL_SET; /**< DCP channel control register, offset: 0x24 */ + __IO uint32_t CHANNELCTRL_CLR; /**< DCP channel control register, offset: 0x28 */ + __IO uint32_t CHANNELCTRL_TOG; /**< DCP channel control register, offset: 0x2C */ + __IO uint32_t CAPABILITY0; /**< DCP capability 0 register, offset: 0x30 */ + uint8_t RESERVED_0[12]; + __I uint32_t CAPABILITY1; /**< DCP capability 1 register, offset: 0x40 */ + uint8_t RESERVED_1[12]; + __IO uint32_t CONTEXT; /**< DCP context buffer pointer, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t KEY; /**< DCP key index, offset: 0x60 */ + uint8_t RESERVED_3[12]; + __IO uint32_t KEYDATA; /**< DCP key data, offset: 0x70 */ + uint8_t RESERVED_4[12]; + __I uint32_t PACKET0; /**< DCP work packet 0 status register, offset: 0x80 */ + uint8_t RESERVED_5[12]; + __I uint32_t PACKET1; /**< DCP work packet 1 status register, offset: 0x90 */ + uint8_t RESERVED_6[12]; + __I uint32_t PACKET2; /**< DCP work packet 2 status register, offset: 0xA0 */ + uint8_t RESERVED_7[12]; + __I uint32_t PACKET3; /**< DCP work packet 3 status register, offset: 0xB0 */ + uint8_t RESERVED_8[12]; + __I uint32_t PACKET4; /**< DCP work packet 4 status register, offset: 0xC0 */ + uint8_t RESERVED_9[12]; + __I uint32_t PACKET5; /**< DCP work packet 5 status register, offset: 0xD0 */ + uint8_t RESERVED_10[12]; + __I uint32_t PACKET6; /**< DCP work packet 6 status register, offset: 0xE0 */ + uint8_t RESERVED_11[28]; + __IO uint32_t CH0CMDPTR; /**< DCP channel 0 command pointer address register, offset: 0x100 */ + uint8_t RESERVED_12[12]; + __IO uint32_t CH0SEMA; /**< DCP channel 0 semaphore register, offset: 0x110 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CH0STAT; /**< DCP channel 0 status register, offset: 0x120 */ + __IO uint32_t CH0STAT_SET; /**< DCP channel 0 status register, offset: 0x124 */ + __IO uint32_t CH0STAT_CLR; /**< DCP channel 0 status register, offset: 0x128 */ + __IO uint32_t CH0STAT_TOG; /**< DCP channel 0 status register, offset: 0x12C */ + __IO uint32_t CH0OPTS; /**< DCP channel 0 options register, offset: 0x130 */ + __IO uint32_t CH0OPTS_SET; /**< DCP channel 0 options register, offset: 0x134 */ + __IO uint32_t CH0OPTS_CLR; /**< DCP channel 0 options register, offset: 0x138 */ + __IO uint32_t CH0OPTS_TOG; /**< DCP channel 0 options register, offset: 0x13C */ + __IO uint32_t CH1CMDPTR; /**< DCP channel 1 command pointer address register, offset: 0x140 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CH1SEMA; /**< DCP channel 1 semaphore register, offset: 0x150 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CH1STAT; /**< DCP channel 1 status register, offset: 0x160 */ + __IO uint32_t CH1STAT_SET; /**< DCP channel 1 status register, offset: 0x164 */ + __IO uint32_t CH1STAT_CLR; /**< DCP channel 1 status register, offset: 0x168 */ + __IO uint32_t CH1STAT_TOG; /**< DCP channel 1 status register, offset: 0x16C */ + __IO uint32_t CH1OPTS; /**< DCP channel 1 options register, offset: 0x170 */ + __IO uint32_t CH1OPTS_SET; /**< DCP channel 1 options register, offset: 0x174 */ + __IO uint32_t CH1OPTS_CLR; /**< DCP channel 1 options register, offset: 0x178 */ + __IO uint32_t CH1OPTS_TOG; /**< DCP channel 1 options register, offset: 0x17C */ + __IO uint32_t CH2CMDPTR; /**< DCP channel 2 command pointer address register, offset: 0x180 */ + uint8_t RESERVED_16[12]; + __IO uint32_t CH2SEMA; /**< DCP channel 2 semaphore register, offset: 0x190 */ + uint8_t RESERVED_17[12]; + __IO uint32_t CH2STAT; /**< DCP channel 2 status register, offset: 0x1A0 */ + __IO uint32_t CH2STAT_SET; /**< DCP channel 2 status register, offset: 0x1A4 */ + __IO uint32_t CH2STAT_CLR; /**< DCP channel 2 status register, offset: 0x1A8 */ + __IO uint32_t CH2STAT_TOG; /**< DCP channel 2 status register, offset: 0x1AC */ + __IO uint32_t CH2OPTS; /**< DCP channel 2 options register, offset: 0x1B0 */ + __IO uint32_t CH2OPTS_SET; /**< DCP channel 2 options register, offset: 0x1B4 */ + __IO uint32_t CH2OPTS_CLR; /**< DCP channel 2 options register, offset: 0x1B8 */ + __IO uint32_t CH2OPTS_TOG; /**< DCP channel 2 options register, offset: 0x1BC */ + __IO uint32_t CH3CMDPTR; /**< DCP channel 3 command pointer address register, offset: 0x1C0 */ + uint8_t RESERVED_18[12]; + __IO uint32_t CH3SEMA; /**< DCP channel 3 semaphore register, offset: 0x1D0 */ + uint8_t RESERVED_19[12]; + __IO uint32_t CH3STAT; /**< DCP channel 3 status register, offset: 0x1E0 */ + __IO uint32_t CH3STAT_SET; /**< DCP channel 3 status register, offset: 0x1E4 */ + __IO uint32_t CH3STAT_CLR; /**< DCP channel 3 status register, offset: 0x1E8 */ + __IO uint32_t CH3STAT_TOG; /**< DCP channel 3 status register, offset: 0x1EC */ + __IO uint32_t CH3OPTS; /**< DCP channel 3 options register, offset: 0x1F0 */ + __IO uint32_t CH3OPTS_SET; /**< DCP channel 3 options register, offset: 0x1F4 */ + __IO uint32_t CH3OPTS_CLR; /**< DCP channel 3 options register, offset: 0x1F8 */ + __IO uint32_t CH3OPTS_TOG; /**< DCP channel 3 options register, offset: 0x1FC */ + uint8_t RESERVED_20[512]; + __IO uint32_t DBGSELECT; /**< DCP debug select register, offset: 0x400 */ + uint8_t RESERVED_21[12]; + __I uint32_t DBGDATA; /**< DCP debug data register, offset: 0x410 */ + uint8_t RESERVED_22[12]; + __IO uint32_t PAGETABLE; /**< DCP page table register, offset: 0x420 */ + uint8_t RESERVED_23[12]; + __I uint32_t VERSION; /**< DCP version register, offset: 0x430 */ +} DCP_Type; + +/* ---------------------------------------------------------------------------- + -- DCP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCP_Register_Masks DCP Register Masks + * @{ + */ + +/*! @name CTRL - DCP control register 0 */ +/*! @{ */ +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) +/*! CHANNEL_INTERRUPT_ENABLE + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) +#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) +#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U) +#define DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U) +#define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK) +#define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U) +#define DCP_CTRL_PRESENT_SHA_SHIFT (28U) +/*! PRESENT_SHA + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK) +#define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U) +#define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U) +/*! PRESENT_CRYPTO + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK) +#define DCP_CTRL_CLKGATE_MASK (0x40000000U) +#define DCP_CTRL_CLKGATE_SHIFT (30U) +#define DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK) +#define DCP_CTRL_SFTRST_MASK (0x80000000U) +#define DCP_CTRL_SFTRST_SHIFT (31U) +#define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - DCP control register 0 */ +/*! @{ */ +#define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) +#define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) +/*! CHANNEL_INTERRUPT_ENABLE + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) +#define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) +#define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) +#define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) +#define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK) +#define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK (0x400000U) +#define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT (22U) +#define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK) +#define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK (0x800000U) +#define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT (23U) +#define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK) +#define DCP_CTRL_SET_PRESENT_SHA_MASK (0x10000000U) +#define DCP_CTRL_SET_PRESENT_SHA_SHIFT (28U) +/*! PRESENT_SHA + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_SET_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_SHA_SHIFT)) & DCP_CTRL_SET_PRESENT_SHA_MASK) +#define DCP_CTRL_SET_PRESENT_CRYPTO_MASK (0x20000000U) +#define DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT (29U) +/*! PRESENT_CRYPTO + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_SET_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_SET_PRESENT_CRYPTO_MASK) +#define DCP_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define DCP_CTRL_SET_CLKGATE_SHIFT (30U) +#define DCP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CLKGATE_SHIFT)) & DCP_CTRL_SET_CLKGATE_MASK) +#define DCP_CTRL_SET_SFTRST_MASK (0x80000000U) +#define DCP_CTRL_SET_SFTRST_SHIFT (31U) +#define DCP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_SFTRST_SHIFT)) & DCP_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - DCP control register 0 */ +/*! @{ */ +#define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) +#define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) +/*! CHANNEL_INTERRUPT_ENABLE + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) +#define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) +#define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) +#define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) +#define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK) +#define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK (0x400000U) +#define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT (22U) +#define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK) +#define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK (0x800000U) +#define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT (23U) +#define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK) +#define DCP_CTRL_CLR_PRESENT_SHA_MASK (0x10000000U) +#define DCP_CTRL_CLR_PRESENT_SHA_SHIFT (28U) +/*! PRESENT_SHA + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_CLR_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_SHA_SHIFT)) & DCP_CTRL_CLR_PRESENT_SHA_MASK) +#define DCP_CTRL_CLR_PRESENT_CRYPTO_MASK (0x20000000U) +#define DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT (29U) +/*! PRESENT_CRYPTO + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_CLR_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_CLR_PRESENT_CRYPTO_MASK) +#define DCP_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define DCP_CTRL_CLR_CLKGATE_SHIFT (30U) +#define DCP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CLKGATE_SHIFT)) & DCP_CTRL_CLR_CLKGATE_MASK) +#define DCP_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define DCP_CTRL_CLR_SFTRST_SHIFT (31U) +#define DCP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_SFTRST_SHIFT)) & DCP_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - DCP control register 0 */ +/*! @{ */ +#define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU) +#define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U) +/*! CHANNEL_INTERRUPT_ENABLE + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U) +#define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U) +#define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK) +#define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U) +#define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT (21U) +#define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK) +#define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK (0x400000U) +#define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT (22U) +#define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK) +#define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK (0x800000U) +#define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT (23U) +#define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK) +#define DCP_CTRL_TOG_PRESENT_SHA_MASK (0x10000000U) +#define DCP_CTRL_TOG_PRESENT_SHA_SHIFT (28U) +/*! PRESENT_SHA + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_TOG_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_SHA_SHIFT)) & DCP_CTRL_TOG_PRESENT_SHA_MASK) +#define DCP_CTRL_TOG_PRESENT_CRYPTO_MASK (0x20000000U) +#define DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT (29U) +/*! PRESENT_CRYPTO + * 0b1..Present + * 0b0..Absent + */ +#define DCP_CTRL_TOG_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_TOG_PRESENT_CRYPTO_MASK) +#define DCP_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define DCP_CTRL_TOG_CLKGATE_SHIFT (30U) +#define DCP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CLKGATE_SHIFT)) & DCP_CTRL_TOG_CLKGATE_MASK) +#define DCP_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define DCP_CTRL_TOG_SFTRST_SHIFT (31U) +#define DCP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_SFTRST_SHIFT)) & DCP_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STAT - DCP status register */ +/*! @{ */ +#define DCP_STAT_IRQ_MASK (0xFU) +#define DCP_STAT_IRQ_SHIFT (0U) +#define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK) +#define DCP_STAT_RSVD_IRQ_MASK (0x100U) +#define DCP_STAT_RSVD_IRQ_SHIFT (8U) +#define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK) +#define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U) +#define DCP_STAT_READY_CHANNELS_SHIFT (16U) +/*! READY_CHANNELS + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK) +#define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U) +#define DCP_STAT_CUR_CHANNEL_SHIFT (24U) +/*! CUR_CHANNEL + * 0b0000..None + * 0b0001..CH0 + * 0b0010..CH1 + * 0b0011..CH2 + * 0b0100..CH3 + */ +#define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK) +#define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U) +#define DCP_STAT_OTP_KEY_READY_SHIFT (28U) +#define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK) +/*! @} */ + +/*! @name STAT_SET - DCP status register */ +/*! @{ */ +#define DCP_STAT_SET_IRQ_MASK (0xFU) +#define DCP_STAT_SET_IRQ_SHIFT (0U) +#define DCP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_IRQ_SHIFT)) & DCP_STAT_SET_IRQ_MASK) +#define DCP_STAT_SET_RSVD_IRQ_MASK (0x100U) +#define DCP_STAT_SET_RSVD_IRQ_SHIFT (8U) +#define DCP_STAT_SET_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_RSVD_IRQ_SHIFT)) & DCP_STAT_SET_RSVD_IRQ_MASK) +#define DCP_STAT_SET_READY_CHANNELS_MASK (0xFF0000U) +#define DCP_STAT_SET_READY_CHANNELS_SHIFT (16U) +/*! READY_CHANNELS + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_STAT_SET_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_READY_CHANNELS_SHIFT)) & DCP_STAT_SET_READY_CHANNELS_MASK) +#define DCP_STAT_SET_CUR_CHANNEL_MASK (0xF000000U) +#define DCP_STAT_SET_CUR_CHANNEL_SHIFT (24U) +/*! CUR_CHANNEL + * 0b0000..None + * 0b0001..CH0 + * 0b0010..CH1 + * 0b0011..CH2 + * 0b0100..CH3 + */ +#define DCP_STAT_SET_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_CUR_CHANNEL_SHIFT)) & DCP_STAT_SET_CUR_CHANNEL_MASK) +#define DCP_STAT_SET_OTP_KEY_READY_MASK (0x10000000U) +#define DCP_STAT_SET_OTP_KEY_READY_SHIFT (28U) +#define DCP_STAT_SET_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_OTP_KEY_READY_SHIFT)) & DCP_STAT_SET_OTP_KEY_READY_MASK) +/*! @} */ + +/*! @name STAT_CLR - DCP status register */ +/*! @{ */ +#define DCP_STAT_CLR_IRQ_MASK (0xFU) +#define DCP_STAT_CLR_IRQ_SHIFT (0U) +#define DCP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_IRQ_SHIFT)) & DCP_STAT_CLR_IRQ_MASK) +#define DCP_STAT_CLR_RSVD_IRQ_MASK (0x100U) +#define DCP_STAT_CLR_RSVD_IRQ_SHIFT (8U) +#define DCP_STAT_CLR_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_RSVD_IRQ_SHIFT)) & DCP_STAT_CLR_RSVD_IRQ_MASK) +#define DCP_STAT_CLR_READY_CHANNELS_MASK (0xFF0000U) +#define DCP_STAT_CLR_READY_CHANNELS_SHIFT (16U) +/*! READY_CHANNELS + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_STAT_CLR_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_READY_CHANNELS_SHIFT)) & DCP_STAT_CLR_READY_CHANNELS_MASK) +#define DCP_STAT_CLR_CUR_CHANNEL_MASK (0xF000000U) +#define DCP_STAT_CLR_CUR_CHANNEL_SHIFT (24U) +/*! CUR_CHANNEL + * 0b0000..None + * 0b0001..CH0 + * 0b0010..CH1 + * 0b0011..CH2 + * 0b0100..CH3 + */ +#define DCP_STAT_CLR_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_CUR_CHANNEL_SHIFT)) & DCP_STAT_CLR_CUR_CHANNEL_MASK) +#define DCP_STAT_CLR_OTP_KEY_READY_MASK (0x10000000U) +#define DCP_STAT_CLR_OTP_KEY_READY_SHIFT (28U) +#define DCP_STAT_CLR_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_OTP_KEY_READY_SHIFT)) & DCP_STAT_CLR_OTP_KEY_READY_MASK) +/*! @} */ + +/*! @name STAT_TOG - DCP status register */ +/*! @{ */ +#define DCP_STAT_TOG_IRQ_MASK (0xFU) +#define DCP_STAT_TOG_IRQ_SHIFT (0U) +#define DCP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_IRQ_SHIFT)) & DCP_STAT_TOG_IRQ_MASK) +#define DCP_STAT_TOG_RSVD_IRQ_MASK (0x100U) +#define DCP_STAT_TOG_RSVD_IRQ_SHIFT (8U) +#define DCP_STAT_TOG_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_RSVD_IRQ_SHIFT)) & DCP_STAT_TOG_RSVD_IRQ_MASK) +#define DCP_STAT_TOG_READY_CHANNELS_MASK (0xFF0000U) +#define DCP_STAT_TOG_READY_CHANNELS_SHIFT (16U) +/*! READY_CHANNELS + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_STAT_TOG_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_READY_CHANNELS_SHIFT)) & DCP_STAT_TOG_READY_CHANNELS_MASK) +#define DCP_STAT_TOG_CUR_CHANNEL_MASK (0xF000000U) +#define DCP_STAT_TOG_CUR_CHANNEL_SHIFT (24U) +/*! CUR_CHANNEL + * 0b0000..None + * 0b0001..CH0 + * 0b0010..CH1 + * 0b0011..CH2 + * 0b0100..CH3 + */ +#define DCP_STAT_TOG_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_CUR_CHANNEL_SHIFT)) & DCP_STAT_TOG_CUR_CHANNEL_MASK) +#define DCP_STAT_TOG_OTP_KEY_READY_MASK (0x10000000U) +#define DCP_STAT_TOG_OTP_KEY_READY_SHIFT (28U) +#define DCP_STAT_TOG_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_OTP_KEY_READY_SHIFT)) & DCP_STAT_TOG_OTP_KEY_READY_MASK) +/*! @} */ + +/*! @name CHANNELCTRL - DCP channel control register */ +/*! @{ */ +#define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU) +#define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U) +/*! ENABLE_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U) +/*! HIGH_PRIORITY_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U) +#define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK) +#define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U) +#define DCP_CHANNELCTRL_RSVD_SHIFT (17U) +#define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK) +/*! @} */ + +/*! @name CHANNELCTRL_SET - DCP channel control register */ +/*! @{ */ +#define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK (0xFFU) +#define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT (0U) +/*! ENABLE_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK) +#define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) +#define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT (8U) +/*! HIGH_PRIORITY_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK) +#define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK (0x10000U) +#define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT (16U) +#define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK) +#define DCP_CHANNELCTRL_SET_RSVD_MASK (0xFFFE0000U) +#define DCP_CHANNELCTRL_SET_RSVD_SHIFT (17U) +#define DCP_CHANNELCTRL_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_RSVD_SHIFT)) & DCP_CHANNELCTRL_SET_RSVD_MASK) +/*! @} */ + +/*! @name CHANNELCTRL_CLR - DCP channel control register */ +/*! @{ */ +#define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK (0xFFU) +#define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT (0U) +/*! ENABLE_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK) +#define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) +#define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT (8U) +/*! HIGH_PRIORITY_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK) +#define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK (0x10000U) +#define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT (16U) +#define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK) +#define DCP_CHANNELCTRL_CLR_RSVD_MASK (0xFFFE0000U) +#define DCP_CHANNELCTRL_CLR_RSVD_SHIFT (17U) +#define DCP_CHANNELCTRL_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_RSVD_SHIFT)) & DCP_CHANNELCTRL_CLR_RSVD_MASK) +/*! @} */ + +/*! @name CHANNELCTRL_TOG - DCP channel control register */ +/*! @{ */ +#define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK (0xFFU) +#define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT (0U) +/*! ENABLE_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK) +#define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U) +#define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT (8U) +/*! HIGH_PRIORITY_CHANNEL + * 0b00000001..CH0 + * 0b00000010..CH1 + * 0b00000100..CH2 + * 0b00001000..CH3 + */ +#define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK) +#define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK (0x10000U) +#define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT (16U) +#define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK) +#define DCP_CHANNELCTRL_TOG_RSVD_MASK (0xFFFE0000U) +#define DCP_CHANNELCTRL_TOG_RSVD_SHIFT (17U) +#define DCP_CHANNELCTRL_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_RSVD_SHIFT)) & DCP_CHANNELCTRL_TOG_RSVD_MASK) +/*! @} */ + +/*! @name CAPABILITY0 - DCP capability 0 register */ +/*! @{ */ +#define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU) +#define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U) +#define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK) +#define DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U) +#define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U) +#define DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK) +#define DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U) +#define DCP_CAPABILITY0_RSVD_SHIFT (12U) +#define DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U) +#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK) +#define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U) +#define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U) +#define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK) +/*! @} */ + +/*! @name CAPABILITY1 - DCP capability 1 register */ +/*! @{ */ +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU) +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U) +/*! CIPHER_ALGORITHMS + * 0b0000000000000001..AES128 + */ +#define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK) +#define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U) +#define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U) +/*! HASH_ALGORITHMS + * 0b0000000000000001..SHA1 + * 0b0000000000000010..CRC32 + * 0b0000000000000100..SHA256 + */ +#define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK) +/*! @} */ + +/*! @name CONTEXT - DCP context buffer pointer */ +/*! @{ */ +#define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CONTEXT_ADDR_SHIFT (0U) +#define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK) +/*! @} */ + +/*! @name KEY - DCP key index */ +/*! @{ */ +#define DCP_KEY_SUBWORD_MASK (0x3U) +#define DCP_KEY_SUBWORD_SHIFT (0U) +#define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK) +#define DCP_KEY_RSVD_SUBWORD_MASK (0xCU) +#define DCP_KEY_RSVD_SUBWORD_SHIFT (2U) +#define DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK) +#define DCP_KEY_INDEX_MASK (0x30U) +#define DCP_KEY_INDEX_SHIFT (4U) +#define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK) +#define DCP_KEY_RSVD_INDEX_MASK (0xC0U) +#define DCP_KEY_RSVD_INDEX_SHIFT (6U) +#define DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK) +#define DCP_KEY_RSVD_MASK (0xFFFFFF00U) +#define DCP_KEY_RSVD_SHIFT (8U) +#define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK) +/*! @} */ + +/*! @name KEYDATA - DCP key data */ +/*! @{ */ +#define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU) +#define DCP_KEYDATA_DATA_SHIFT (0U) +#define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK) +/*! @} */ + +/*! @name PACKET0 - DCP work packet 0 status register */ +/*! @{ */ +#define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET0_ADDR_SHIFT (0U) +#define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK) +/*! @} */ + +/*! @name PACKET1 - DCP work packet 1 status register */ +/*! @{ */ +#define DCP_PACKET1_INTERRUPT_MASK (0x1U) +#define DCP_PACKET1_INTERRUPT_SHIFT (0U) +#define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK) +#define DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U) +#define DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U) +#define DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK) +#define DCP_PACKET1_CHAIN_MASK (0x4U) +#define DCP_PACKET1_CHAIN_SHIFT (2U) +#define DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK) +#define DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U) +#define DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U) +#define DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK) +#define DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U) +#define DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U) +#define DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK) +#define DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U) +#define DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U) +#define DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK) +#define DCP_PACKET1_ENABLE_HASH_MASK (0x40U) +#define DCP_PACKET1_ENABLE_HASH_SHIFT (6U) +#define DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK) +#define DCP_PACKET1_ENABLE_BLIT_MASK (0x80U) +#define DCP_PACKET1_ENABLE_BLIT_SHIFT (7U) +#define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK) +#define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U) +#define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U) +/*! CIPHER_ENCRYPT + * 0b1..ENCRYPT + * 0b0..DECRYPT + */ +#define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK) +#define DCP_PACKET1_CIPHER_INIT_MASK (0x200U) +#define DCP_PACKET1_CIPHER_INIT_SHIFT (9U) +#define DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK) +#define DCP_PACKET1_OTP_KEY_MASK (0x400U) +#define DCP_PACKET1_OTP_KEY_SHIFT (10U) +#define DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK) +#define DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U) +#define DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U) +#define DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK) +#define DCP_PACKET1_HASH_INIT_MASK (0x1000U) +#define DCP_PACKET1_HASH_INIT_SHIFT (12U) +#define DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK) +#define DCP_PACKET1_HASH_TERM_MASK (0x2000U) +#define DCP_PACKET1_HASH_TERM_SHIFT (13U) +#define DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK) +#define DCP_PACKET1_CHECK_HASH_MASK (0x4000U) +#define DCP_PACKET1_CHECK_HASH_SHIFT (14U) +#define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK) +#define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U) +#define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U) +/*! HASH_OUTPUT + * 0b0..INPUT + * 0b1..OUTPUT + */ +#define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK) +#define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U) +#define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U) +#define DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK) +#define DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U) +#define DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U) +#define DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK) +#define DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U) +#define DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U) +#define DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK) +#define DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U) +#define DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U) +#define DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK) +#define DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U) +#define DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U) +#define DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK) +#define DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U) +#define DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U) +#define DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK) +#define DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U) +#define DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U) +#define DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK) +#define DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U) +#define DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U) +#define DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK) +#define DCP_PACKET1_TAG_MASK (0xFF000000U) +#define DCP_PACKET1_TAG_SHIFT (24U) +#define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK) +/*! @} */ + +/*! @name PACKET2 - DCP work packet 2 status register */ +/*! @{ */ +#define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU) +#define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U) +/*! CIPHER_SELECT + * 0b0000..AES128 + */ +#define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK) +#define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U) +#define DCP_PACKET2_CIPHER_MODE_SHIFT (4U) +/*! CIPHER_MODE + * 0b0000..ECB + * 0b0001..CBC + */ +#define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK) +#define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U) +#define DCP_PACKET2_KEY_SELECT_SHIFT (8U) +/*! KEY_SELECT + * 0b00000000..KEY0 + * 0b00000001..KEY1 + * 0b00000010..KEY2 + * 0b00000011..KEY3 + * 0b11111110..UNIQUE_KEY + * 0b11111111..OTP_KEY + */ +#define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK) +#define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U) +#define DCP_PACKET2_HASH_SELECT_SHIFT (16U) +/*! HASH_SELECT + * 0b0000..SHA1 + * 0b0001..CRC32 + * 0b0010..SHA256 + */ +#define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK) +#define DCP_PACKET2_RSVD_MASK (0xF00000U) +#define DCP_PACKET2_RSVD_SHIFT (20U) +#define DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK) +#define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U) +#define DCP_PACKET2_CIPHER_CFG_SHIFT (24U) +#define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK) +/*! @} */ + +/*! @name PACKET3 - DCP work packet 3 status register */ +/*! @{ */ +#define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET3_ADDR_SHIFT (0U) +#define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK) +/*! @} */ + +/*! @name PACKET4 - DCP work packet 4 status register */ +/*! @{ */ +#define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET4_ADDR_SHIFT (0U) +#define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK) +/*! @} */ + +/*! @name PACKET5 - DCP work packet 5 status register */ +/*! @{ */ +#define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU) +#define DCP_PACKET5_COUNT_SHIFT (0U) +#define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK) +/*! @} */ + +/*! @name PACKET6 - DCP work packet 6 status register */ +/*! @{ */ +#define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU) +#define DCP_PACKET6_ADDR_SHIFT (0U) +#define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK) +/*! @} */ + +/*! @name CH0CMDPTR - DCP channel 0 command pointer address register */ +/*! @{ */ +#define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH0CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH0SEMA - DCP channel 0 semaphore register */ +/*! @{ */ +#define DCP_CH0SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH0SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK) +#define DCP_CH0SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH0SEMA_VALUE_SHIFT (16U) +#define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH0STAT - DCP channel 0 status register */ +/*! @{ */ +#define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK) +#define DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK) +#define DCP_CH0STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH0STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK) +#define DCP_CH0STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH0STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK) +#define DCP_CH0STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH0STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK) +#define DCP_CH0STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH0STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK) +#define DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH0STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error signalled because the next pointer is 0x00000000 + * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set + * 0b00000011..Error signalled because an error is reported reading/writing the context buffer + * 0b00000100..Error signalled because an error is reported reading/writing the payload + * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + */ +#define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK) +#define DCP_CH0STAT_TAG_MASK (0xFF000000U) +#define DCP_CH0STAT_TAG_SHIFT (24U) +#define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK) +/*! @} */ + +/*! @name CH0STAT_SET - DCP channel 0 status register */ +/*! @{ */ +#define DCP_CH0STAT_SET_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH0STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_SET_RSVD_COMPLETE_MASK) +#define DCP_CH0STAT_SET_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH0STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_SET_HASH_MISMATCH_MASK) +#define DCP_CH0STAT_SET_ERROR_SETUP_MASK (0x4U) +#define DCP_CH0STAT_SET_ERROR_SETUP_SHIFT (2U) +#define DCP_CH0STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_SET_ERROR_SETUP_MASK) +#define DCP_CH0STAT_SET_ERROR_PACKET_MASK (0x8U) +#define DCP_CH0STAT_SET_ERROR_PACKET_SHIFT (3U) +#define DCP_CH0STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_SET_ERROR_PACKET_MASK) +#define DCP_CH0STAT_SET_ERROR_SRC_MASK (0x10U) +#define DCP_CH0STAT_SET_ERROR_SRC_SHIFT (4U) +#define DCP_CH0STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH0STAT_SET_ERROR_SRC_MASK) +#define DCP_CH0STAT_SET_ERROR_DST_MASK (0x20U) +#define DCP_CH0STAT_SET_ERROR_DST_SHIFT (5U) +#define DCP_CH0STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_DST_SHIFT)) & DCP_CH0STAT_SET_ERROR_DST_MASK) +#define DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH0STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK) +#define DCP_CH0STAT_SET_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH0STAT_SET_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error signalled because the next pointer is 0x00000000 + * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set + * 0b00000011..Error signalled because an error is reported reading/writing the context buffer + * 0b00000100..Error signalled because an error is reported reading/writing the payload + * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + */ +#define DCP_CH0STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH0STAT_SET_ERROR_CODE_MASK) +#define DCP_CH0STAT_SET_TAG_MASK (0xFF000000U) +#define DCP_CH0STAT_SET_TAG_SHIFT (24U) +#define DCP_CH0STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_TAG_SHIFT)) & DCP_CH0STAT_SET_TAG_MASK) +/*! @} */ + +/*! @name CH0STAT_CLR - DCP channel 0 status register */ +/*! @{ */ +#define DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH0STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK) +#define DCP_CH0STAT_CLR_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH0STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_CLR_HASH_MISMATCH_MASK) +#define DCP_CH0STAT_CLR_ERROR_SETUP_MASK (0x4U) +#define DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT (2U) +#define DCP_CH0STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SETUP_MASK) +#define DCP_CH0STAT_CLR_ERROR_PACKET_MASK (0x8U) +#define DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT (3U) +#define DCP_CH0STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PACKET_MASK) +#define DCP_CH0STAT_CLR_ERROR_SRC_MASK (0x10U) +#define DCP_CH0STAT_CLR_ERROR_SRC_SHIFT (4U) +#define DCP_CH0STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SRC_MASK) +#define DCP_CH0STAT_CLR_ERROR_DST_MASK (0x20U) +#define DCP_CH0STAT_CLR_ERROR_DST_SHIFT (5U) +#define DCP_CH0STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH0STAT_CLR_ERROR_DST_MASK) +#define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH0STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK) +#define DCP_CH0STAT_CLR_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH0STAT_CLR_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error signalled because the next pointer is 0x00000000 + * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set + * 0b00000011..Error signalled because an error is reported reading/writing the context buffer + * 0b00000100..Error signalled because an error is reported reading/writing the payload + * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + */ +#define DCP_CH0STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH0STAT_CLR_ERROR_CODE_MASK) +#define DCP_CH0STAT_CLR_TAG_MASK (0xFF000000U) +#define DCP_CH0STAT_CLR_TAG_SHIFT (24U) +#define DCP_CH0STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_TAG_SHIFT)) & DCP_CH0STAT_CLR_TAG_MASK) +/*! @} */ + +/*! @name CH0STAT_TOG - DCP channel 0 status register */ +/*! @{ */ +#define DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH0STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK) +#define DCP_CH0STAT_TOG_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH0STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_TOG_HASH_MISMATCH_MASK) +#define DCP_CH0STAT_TOG_ERROR_SETUP_MASK (0x4U) +#define DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT (2U) +#define DCP_CH0STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SETUP_MASK) +#define DCP_CH0STAT_TOG_ERROR_PACKET_MASK (0x8U) +#define DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT (3U) +#define DCP_CH0STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PACKET_MASK) +#define DCP_CH0STAT_TOG_ERROR_SRC_MASK (0x10U) +#define DCP_CH0STAT_TOG_ERROR_SRC_SHIFT (4U) +#define DCP_CH0STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SRC_MASK) +#define DCP_CH0STAT_TOG_ERROR_DST_MASK (0x20U) +#define DCP_CH0STAT_TOG_ERROR_DST_SHIFT (5U) +#define DCP_CH0STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH0STAT_TOG_ERROR_DST_MASK) +#define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH0STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK) +#define DCP_CH0STAT_TOG_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH0STAT_TOG_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error signalled because the next pointer is 0x00000000 + * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set + * 0b00000011..Error signalled because an error is reported reading/writing the context buffer + * 0b00000100..Error signalled because an error is reported reading/writing the payload + * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + */ +#define DCP_CH0STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH0STAT_TOG_ERROR_CODE_MASK) +#define DCP_CH0STAT_TOG_TAG_MASK (0xFF000000U) +#define DCP_CH0STAT_TOG_TAG_SHIFT (24U) +#define DCP_CH0STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_TAG_SHIFT)) & DCP_CH0STAT_TOG_TAG_MASK) +/*! @} */ + +/*! @name CH0OPTS - DCP channel 0 options register */ +/*! @{ */ +#define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH0OPTS_RSVD_SHIFT (16U) +#define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK) +/*! @} */ + +/*! @name CH0OPTS_SET - DCP channel 0 options register */ +/*! @{ */ +#define DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH0OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK) +#define DCP_CH0OPTS_SET_RSVD_MASK (0xFFFF0000U) +#define DCP_CH0OPTS_SET_RSVD_SHIFT (16U) +#define DCP_CH0OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RSVD_SHIFT)) & DCP_CH0OPTS_SET_RSVD_MASK) +/*! @} */ + +/*! @name CH0OPTS_CLR - DCP channel 0 options register */ +/*! @{ */ +#define DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH0OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK) +#define DCP_CH0OPTS_CLR_RSVD_MASK (0xFFFF0000U) +#define DCP_CH0OPTS_CLR_RSVD_SHIFT (16U) +#define DCP_CH0OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RSVD_SHIFT)) & DCP_CH0OPTS_CLR_RSVD_MASK) +/*! @} */ + +/*! @name CH0OPTS_TOG - DCP channel 0 options register */ +/*! @{ */ +#define DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH0OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK) +#define DCP_CH0OPTS_TOG_RSVD_MASK (0xFFFF0000U) +#define DCP_CH0OPTS_TOG_RSVD_SHIFT (16U) +#define DCP_CH0OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RSVD_SHIFT)) & DCP_CH0OPTS_TOG_RSVD_MASK) +/*! @} */ + +/*! @name CH1CMDPTR - DCP channel 1 command pointer address register */ +/*! @{ */ +#define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH1CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH1SEMA - DCP channel 1 semaphore register */ +/*! @{ */ +#define DCP_CH1SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH1SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK) +#define DCP_CH1SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH1SEMA_VALUE_SHIFT (16U) +#define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH1STAT - DCP channel 1 status register */ +/*! @{ */ +#define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK) +#define DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK) +#define DCP_CH1STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH1STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK) +#define DCP_CH1STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH1STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK) +#define DCP_CH1STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH1STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK) +#define DCP_CH1STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH1STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK) +#define DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH1STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported when reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK) +#define DCP_CH1STAT_TAG_MASK (0xFF000000U) +#define DCP_CH1STAT_TAG_SHIFT (24U) +#define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK) +/*! @} */ + +/*! @name CH1STAT_SET - DCP channel 1 status register */ +/*! @{ */ +#define DCP_CH1STAT_SET_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH1STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_SET_RSVD_COMPLETE_MASK) +#define DCP_CH1STAT_SET_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH1STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_SET_HASH_MISMATCH_MASK) +#define DCP_CH1STAT_SET_ERROR_SETUP_MASK (0x4U) +#define DCP_CH1STAT_SET_ERROR_SETUP_SHIFT (2U) +#define DCP_CH1STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_SET_ERROR_SETUP_MASK) +#define DCP_CH1STAT_SET_ERROR_PACKET_MASK (0x8U) +#define DCP_CH1STAT_SET_ERROR_PACKET_SHIFT (3U) +#define DCP_CH1STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_SET_ERROR_PACKET_MASK) +#define DCP_CH1STAT_SET_ERROR_SRC_MASK (0x10U) +#define DCP_CH1STAT_SET_ERROR_SRC_SHIFT (4U) +#define DCP_CH1STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH1STAT_SET_ERROR_SRC_MASK) +#define DCP_CH1STAT_SET_ERROR_DST_MASK (0x20U) +#define DCP_CH1STAT_SET_ERROR_DST_SHIFT (5U) +#define DCP_CH1STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_DST_SHIFT)) & DCP_CH1STAT_SET_ERROR_DST_MASK) +#define DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH1STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK) +#define DCP_CH1STAT_SET_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH1STAT_SET_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported when reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH1STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH1STAT_SET_ERROR_CODE_MASK) +#define DCP_CH1STAT_SET_TAG_MASK (0xFF000000U) +#define DCP_CH1STAT_SET_TAG_SHIFT (24U) +#define DCP_CH1STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_TAG_SHIFT)) & DCP_CH1STAT_SET_TAG_MASK) +/*! @} */ + +/*! @name CH1STAT_CLR - DCP channel 1 status register */ +/*! @{ */ +#define DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH1STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK) +#define DCP_CH1STAT_CLR_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH1STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_CLR_HASH_MISMATCH_MASK) +#define DCP_CH1STAT_CLR_ERROR_SETUP_MASK (0x4U) +#define DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT (2U) +#define DCP_CH1STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SETUP_MASK) +#define DCP_CH1STAT_CLR_ERROR_PACKET_MASK (0x8U) +#define DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT (3U) +#define DCP_CH1STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PACKET_MASK) +#define DCP_CH1STAT_CLR_ERROR_SRC_MASK (0x10U) +#define DCP_CH1STAT_CLR_ERROR_SRC_SHIFT (4U) +#define DCP_CH1STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SRC_MASK) +#define DCP_CH1STAT_CLR_ERROR_DST_MASK (0x20U) +#define DCP_CH1STAT_CLR_ERROR_DST_SHIFT (5U) +#define DCP_CH1STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH1STAT_CLR_ERROR_DST_MASK) +#define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH1STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK) +#define DCP_CH1STAT_CLR_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH1STAT_CLR_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported when reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH1STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH1STAT_CLR_ERROR_CODE_MASK) +#define DCP_CH1STAT_CLR_TAG_MASK (0xFF000000U) +#define DCP_CH1STAT_CLR_TAG_SHIFT (24U) +#define DCP_CH1STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_TAG_SHIFT)) & DCP_CH1STAT_CLR_TAG_MASK) +/*! @} */ + +/*! @name CH1STAT_TOG - DCP channel 1 status register */ +/*! @{ */ +#define DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH1STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK) +#define DCP_CH1STAT_TOG_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH1STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_TOG_HASH_MISMATCH_MASK) +#define DCP_CH1STAT_TOG_ERROR_SETUP_MASK (0x4U) +#define DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT (2U) +#define DCP_CH1STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SETUP_MASK) +#define DCP_CH1STAT_TOG_ERROR_PACKET_MASK (0x8U) +#define DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT (3U) +#define DCP_CH1STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PACKET_MASK) +#define DCP_CH1STAT_TOG_ERROR_SRC_MASK (0x10U) +#define DCP_CH1STAT_TOG_ERROR_SRC_SHIFT (4U) +#define DCP_CH1STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SRC_MASK) +#define DCP_CH1STAT_TOG_ERROR_DST_MASK (0x20U) +#define DCP_CH1STAT_TOG_ERROR_DST_SHIFT (5U) +#define DCP_CH1STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH1STAT_TOG_ERROR_DST_MASK) +#define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH1STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK) +#define DCP_CH1STAT_TOG_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH1STAT_TOG_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported when reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH1STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH1STAT_TOG_ERROR_CODE_MASK) +#define DCP_CH1STAT_TOG_TAG_MASK (0xFF000000U) +#define DCP_CH1STAT_TOG_TAG_SHIFT (24U) +#define DCP_CH1STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_TAG_SHIFT)) & DCP_CH1STAT_TOG_TAG_MASK) +/*! @} */ + +/*! @name CH1OPTS - DCP channel 1 options register */ +/*! @{ */ +#define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH1OPTS_RSVD_SHIFT (16U) +#define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK) +/*! @} */ + +/*! @name CH1OPTS_SET - DCP channel 1 options register */ +/*! @{ */ +#define DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH1OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK) +#define DCP_CH1OPTS_SET_RSVD_MASK (0xFFFF0000U) +#define DCP_CH1OPTS_SET_RSVD_SHIFT (16U) +#define DCP_CH1OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RSVD_SHIFT)) & DCP_CH1OPTS_SET_RSVD_MASK) +/*! @} */ + +/*! @name CH1OPTS_CLR - DCP channel 1 options register */ +/*! @{ */ +#define DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH1OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK) +#define DCP_CH1OPTS_CLR_RSVD_MASK (0xFFFF0000U) +#define DCP_CH1OPTS_CLR_RSVD_SHIFT (16U) +#define DCP_CH1OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RSVD_SHIFT)) & DCP_CH1OPTS_CLR_RSVD_MASK) +/*! @} */ + +/*! @name CH1OPTS_TOG - DCP channel 1 options register */ +/*! @{ */ +#define DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH1OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK) +#define DCP_CH1OPTS_TOG_RSVD_MASK (0xFFFF0000U) +#define DCP_CH1OPTS_TOG_RSVD_SHIFT (16U) +#define DCP_CH1OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RSVD_SHIFT)) & DCP_CH1OPTS_TOG_RSVD_MASK) +/*! @} */ + +/*! @name CH2CMDPTR - DCP channel 2 command pointer address register */ +/*! @{ */ +#define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH2CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH2SEMA - DCP channel 2 semaphore register */ +/*! @{ */ +#define DCP_CH2SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH2SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK) +#define DCP_CH2SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH2SEMA_VALUE_SHIFT (16U) +#define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH2STAT - DCP channel 2 status register */ +/*! @{ */ +#define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK) +#define DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK) +#define DCP_CH2STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH2STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK) +#define DCP_CH2STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH2STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK) +#define DCP_CH2STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH2STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK) +#define DCP_CH2STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH2STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK) +#define DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH2STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + */ +#define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK) +#define DCP_CH2STAT_TAG_MASK (0xFF000000U) +#define DCP_CH2STAT_TAG_SHIFT (24U) +#define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK) +/*! @} */ + +/*! @name CH2STAT_SET - DCP channel 2 status register */ +/*! @{ */ +#define DCP_CH2STAT_SET_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH2STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_SET_RSVD_COMPLETE_MASK) +#define DCP_CH2STAT_SET_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH2STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_SET_HASH_MISMATCH_MASK) +#define DCP_CH2STAT_SET_ERROR_SETUP_MASK (0x4U) +#define DCP_CH2STAT_SET_ERROR_SETUP_SHIFT (2U) +#define DCP_CH2STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_SET_ERROR_SETUP_MASK) +#define DCP_CH2STAT_SET_ERROR_PACKET_MASK (0x8U) +#define DCP_CH2STAT_SET_ERROR_PACKET_SHIFT (3U) +#define DCP_CH2STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_SET_ERROR_PACKET_MASK) +#define DCP_CH2STAT_SET_ERROR_SRC_MASK (0x10U) +#define DCP_CH2STAT_SET_ERROR_SRC_SHIFT (4U) +#define DCP_CH2STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH2STAT_SET_ERROR_SRC_MASK) +#define DCP_CH2STAT_SET_ERROR_DST_MASK (0x20U) +#define DCP_CH2STAT_SET_ERROR_DST_SHIFT (5U) +#define DCP_CH2STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_DST_SHIFT)) & DCP_CH2STAT_SET_ERROR_DST_MASK) +#define DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH2STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK) +#define DCP_CH2STAT_SET_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH2STAT_SET_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + */ +#define DCP_CH2STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH2STAT_SET_ERROR_CODE_MASK) +#define DCP_CH2STAT_SET_TAG_MASK (0xFF000000U) +#define DCP_CH2STAT_SET_TAG_SHIFT (24U) +#define DCP_CH2STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_TAG_SHIFT)) & DCP_CH2STAT_SET_TAG_MASK) +/*! @} */ + +/*! @name CH2STAT_CLR - DCP channel 2 status register */ +/*! @{ */ +#define DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH2STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK) +#define DCP_CH2STAT_CLR_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH2STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_CLR_HASH_MISMATCH_MASK) +#define DCP_CH2STAT_CLR_ERROR_SETUP_MASK (0x4U) +#define DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT (2U) +#define DCP_CH2STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SETUP_MASK) +#define DCP_CH2STAT_CLR_ERROR_PACKET_MASK (0x8U) +#define DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT (3U) +#define DCP_CH2STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PACKET_MASK) +#define DCP_CH2STAT_CLR_ERROR_SRC_MASK (0x10U) +#define DCP_CH2STAT_CLR_ERROR_SRC_SHIFT (4U) +#define DCP_CH2STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SRC_MASK) +#define DCP_CH2STAT_CLR_ERROR_DST_MASK (0x20U) +#define DCP_CH2STAT_CLR_ERROR_DST_SHIFT (5U) +#define DCP_CH2STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH2STAT_CLR_ERROR_DST_MASK) +#define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH2STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK) +#define DCP_CH2STAT_CLR_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH2STAT_CLR_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + */ +#define DCP_CH2STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH2STAT_CLR_ERROR_CODE_MASK) +#define DCP_CH2STAT_CLR_TAG_MASK (0xFF000000U) +#define DCP_CH2STAT_CLR_TAG_SHIFT (24U) +#define DCP_CH2STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_TAG_SHIFT)) & DCP_CH2STAT_CLR_TAG_MASK) +/*! @} */ + +/*! @name CH2STAT_TOG - DCP channel 2 status register */ +/*! @{ */ +#define DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH2STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK) +#define DCP_CH2STAT_TOG_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH2STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_TOG_HASH_MISMATCH_MASK) +#define DCP_CH2STAT_TOG_ERROR_SETUP_MASK (0x4U) +#define DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT (2U) +#define DCP_CH2STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SETUP_MASK) +#define DCP_CH2STAT_TOG_ERROR_PACKET_MASK (0x8U) +#define DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT (3U) +#define DCP_CH2STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PACKET_MASK) +#define DCP_CH2STAT_TOG_ERROR_SRC_MASK (0x10U) +#define DCP_CH2STAT_TOG_ERROR_SRC_SHIFT (4U) +#define DCP_CH2STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SRC_MASK) +#define DCP_CH2STAT_TOG_ERROR_DST_MASK (0x20U) +#define DCP_CH2STAT_TOG_ERROR_DST_SHIFT (5U) +#define DCP_CH2STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH2STAT_TOG_ERROR_DST_MASK) +#define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH2STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK) +#define DCP_CH2STAT_TOG_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH2STAT_TOG_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + */ +#define DCP_CH2STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH2STAT_TOG_ERROR_CODE_MASK) +#define DCP_CH2STAT_TOG_TAG_MASK (0xFF000000U) +#define DCP_CH2STAT_TOG_TAG_SHIFT (24U) +#define DCP_CH2STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_TAG_SHIFT)) & DCP_CH2STAT_TOG_TAG_MASK) +/*! @} */ + +/*! @name CH2OPTS - DCP channel 2 options register */ +/*! @{ */ +#define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH2OPTS_RSVD_SHIFT (16U) +#define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK) +/*! @} */ + +/*! @name CH2OPTS_SET - DCP channel 2 options register */ +/*! @{ */ +#define DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH2OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK) +#define DCP_CH2OPTS_SET_RSVD_MASK (0xFFFF0000U) +#define DCP_CH2OPTS_SET_RSVD_SHIFT (16U) +#define DCP_CH2OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RSVD_SHIFT)) & DCP_CH2OPTS_SET_RSVD_MASK) +/*! @} */ + +/*! @name CH2OPTS_CLR - DCP channel 2 options register */ +/*! @{ */ +#define DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH2OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK) +#define DCP_CH2OPTS_CLR_RSVD_MASK (0xFFFF0000U) +#define DCP_CH2OPTS_CLR_RSVD_SHIFT (16U) +#define DCP_CH2OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RSVD_SHIFT)) & DCP_CH2OPTS_CLR_RSVD_MASK) +/*! @} */ + +/*! @name CH2OPTS_TOG - DCP channel 2 options register */ +/*! @{ */ +#define DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH2OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK) +#define DCP_CH2OPTS_TOG_RSVD_MASK (0xFFFF0000U) +#define DCP_CH2OPTS_TOG_RSVD_SHIFT (16U) +#define DCP_CH2OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RSVD_SHIFT)) & DCP_CH2OPTS_TOG_RSVD_MASK) +/*! @} */ + +/*! @name CH3CMDPTR - DCP channel 3 command pointer address register */ +/*! @{ */ +#define DCP_CH3CMDPTR_ADDR_MASK (0xFFFFFFFFU) +#define DCP_CH3CMDPTR_ADDR_SHIFT (0U) +#define DCP_CH3CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3CMDPTR_ADDR_SHIFT)) & DCP_CH3CMDPTR_ADDR_MASK) +/*! @} */ + +/*! @name CH3SEMA - DCP channel 3 semaphore register */ +/*! @{ */ +#define DCP_CH3SEMA_INCREMENT_MASK (0xFFU) +#define DCP_CH3SEMA_INCREMENT_SHIFT (0U) +#define DCP_CH3SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_INCREMENT_SHIFT)) & DCP_CH3SEMA_INCREMENT_MASK) +#define DCP_CH3SEMA_VALUE_MASK (0xFF0000U) +#define DCP_CH3SEMA_VALUE_SHIFT (16U) +#define DCP_CH3SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3SEMA_VALUE_SHIFT)) & DCP_CH3SEMA_VALUE_MASK) +/*! @} */ + +/*! @name CH3STAT - DCP channel 3 status register */ +/*! @{ */ +#define DCP_CH3STAT_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH3STAT_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH3STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_RSVD_COMPLETE_MASK) +#define DCP_CH3STAT_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH3STAT_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH3STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_HASH_MISMATCH_MASK) +#define DCP_CH3STAT_ERROR_SETUP_MASK (0x4U) +#define DCP_CH3STAT_ERROR_SETUP_SHIFT (2U) +#define DCP_CH3STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_ERROR_SETUP_MASK) +#define DCP_CH3STAT_ERROR_PACKET_MASK (0x8U) +#define DCP_CH3STAT_ERROR_PACKET_SHIFT (3U) +#define DCP_CH3STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_ERROR_PACKET_MASK) +#define DCP_CH3STAT_ERROR_SRC_MASK (0x10U) +#define DCP_CH3STAT_ERROR_SRC_SHIFT (4U) +#define DCP_CH3STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_SRC_SHIFT)) & DCP_CH3STAT_ERROR_SRC_MASK) +#define DCP_CH3STAT_ERROR_DST_MASK (0x20U) +#define DCP_CH3STAT_ERROR_DST_SHIFT (5U) +#define DCP_CH3STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_DST_SHIFT)) & DCP_CH3STAT_ERROR_DST_MASK) +#define DCP_CH3STAT_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH3STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_ERROR_PAGEFAULT_MASK) +#define DCP_CH3STAT_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH3STAT_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH3STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_ERROR_CODE_SHIFT)) & DCP_CH3STAT_ERROR_CODE_MASK) +#define DCP_CH3STAT_TAG_MASK (0xFF000000U) +#define DCP_CH3STAT_TAG_SHIFT (24U) +#define DCP_CH3STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TAG_SHIFT)) & DCP_CH3STAT_TAG_MASK) +/*! @} */ + +/*! @name CH3STAT_SET - DCP channel 3 status register */ +/*! @{ */ +#define DCP_CH3STAT_SET_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH3STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_SET_RSVD_COMPLETE_MASK) +#define DCP_CH3STAT_SET_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH3STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_SET_HASH_MISMATCH_MASK) +#define DCP_CH3STAT_SET_ERROR_SETUP_MASK (0x4U) +#define DCP_CH3STAT_SET_ERROR_SETUP_SHIFT (2U) +#define DCP_CH3STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_SET_ERROR_SETUP_MASK) +#define DCP_CH3STAT_SET_ERROR_PACKET_MASK (0x8U) +#define DCP_CH3STAT_SET_ERROR_PACKET_SHIFT (3U) +#define DCP_CH3STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_SET_ERROR_PACKET_MASK) +#define DCP_CH3STAT_SET_ERROR_SRC_MASK (0x10U) +#define DCP_CH3STAT_SET_ERROR_SRC_SHIFT (4U) +#define DCP_CH3STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH3STAT_SET_ERROR_SRC_MASK) +#define DCP_CH3STAT_SET_ERROR_DST_MASK (0x20U) +#define DCP_CH3STAT_SET_ERROR_DST_SHIFT (5U) +#define DCP_CH3STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_DST_SHIFT)) & DCP_CH3STAT_SET_ERROR_DST_MASK) +#define DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH3STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_SET_ERROR_PAGEFAULT_MASK) +#define DCP_CH3STAT_SET_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH3STAT_SET_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH3STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH3STAT_SET_ERROR_CODE_MASK) +#define DCP_CH3STAT_SET_TAG_MASK (0xFF000000U) +#define DCP_CH3STAT_SET_TAG_SHIFT (24U) +#define DCP_CH3STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_SET_TAG_SHIFT)) & DCP_CH3STAT_SET_TAG_MASK) +/*! @} */ + +/*! @name CH3STAT_CLR - DCP channel 3 status register */ +/*! @{ */ +#define DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH3STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_CLR_RSVD_COMPLETE_MASK) +#define DCP_CH3STAT_CLR_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH3STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_CLR_HASH_MISMATCH_MASK) +#define DCP_CH3STAT_CLR_ERROR_SETUP_MASK (0x4U) +#define DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT (2U) +#define DCP_CH3STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SETUP_MASK) +#define DCP_CH3STAT_CLR_ERROR_PACKET_MASK (0x8U) +#define DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT (3U) +#define DCP_CH3STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PACKET_MASK) +#define DCP_CH3STAT_CLR_ERROR_SRC_MASK (0x10U) +#define DCP_CH3STAT_CLR_ERROR_SRC_SHIFT (4U) +#define DCP_CH3STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH3STAT_CLR_ERROR_SRC_MASK) +#define DCP_CH3STAT_CLR_ERROR_DST_MASK (0x20U) +#define DCP_CH3STAT_CLR_ERROR_DST_SHIFT (5U) +#define DCP_CH3STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH3STAT_CLR_ERROR_DST_MASK) +#define DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH3STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_CLR_ERROR_PAGEFAULT_MASK) +#define DCP_CH3STAT_CLR_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH3STAT_CLR_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH3STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH3STAT_CLR_ERROR_CODE_MASK) +#define DCP_CH3STAT_CLR_TAG_MASK (0xFF000000U) +#define DCP_CH3STAT_CLR_TAG_SHIFT (24U) +#define DCP_CH3STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_CLR_TAG_SHIFT)) & DCP_CH3STAT_CLR_TAG_MASK) +/*! @} */ + +/*! @name CH3STAT_TOG - DCP channel 3 status register */ +/*! @{ */ +#define DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK (0x1U) +#define DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT (0U) +#define DCP_CH3STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH3STAT_TOG_RSVD_COMPLETE_MASK) +#define DCP_CH3STAT_TOG_HASH_MISMATCH_MASK (0x2U) +#define DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT (1U) +#define DCP_CH3STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH3STAT_TOG_HASH_MISMATCH_MASK) +#define DCP_CH3STAT_TOG_ERROR_SETUP_MASK (0x4U) +#define DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT (2U) +#define DCP_CH3STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SETUP_MASK) +#define DCP_CH3STAT_TOG_ERROR_PACKET_MASK (0x8U) +#define DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT (3U) +#define DCP_CH3STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PACKET_MASK) +#define DCP_CH3STAT_TOG_ERROR_SRC_MASK (0x10U) +#define DCP_CH3STAT_TOG_ERROR_SRC_SHIFT (4U) +#define DCP_CH3STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH3STAT_TOG_ERROR_SRC_MASK) +#define DCP_CH3STAT_TOG_ERROR_DST_MASK (0x20U) +#define DCP_CH3STAT_TOG_ERROR_DST_SHIFT (5U) +#define DCP_CH3STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH3STAT_TOG_ERROR_DST_MASK) +#define DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U) +#define DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U) +#define DCP_CH3STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH3STAT_TOG_ERROR_PAGEFAULT_MASK) +#define DCP_CH3STAT_TOG_ERROR_CODE_MASK (0xFF0000U) +#define DCP_CH3STAT_TOG_ERROR_CODE_SHIFT (16U) +/*! ERROR_CODE + * 0b00000001..Error is signalled because the next pointer is 0x00000000. + * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer. + * 0b00000100..Error is signalled because an error was reported while reading/writing the payload. + * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + */ +#define DCP_CH3STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH3STAT_TOG_ERROR_CODE_MASK) +#define DCP_CH3STAT_TOG_TAG_MASK (0xFF000000U) +#define DCP_CH3STAT_TOG_TAG_SHIFT (24U) +#define DCP_CH3STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3STAT_TOG_TAG_SHIFT)) & DCP_CH3STAT_TOG_TAG_MASK) +/*! @} */ + +/*! @name CH3OPTS - DCP channel 3 options register */ +/*! @{ */ +#define DCP_CH3OPTS_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH3OPTS_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH3OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_RECOVERY_TIMER_MASK) +#define DCP_CH3OPTS_RSVD_MASK (0xFFFF0000U) +#define DCP_CH3OPTS_RSVD_SHIFT (16U) +#define DCP_CH3OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_RSVD_SHIFT)) & DCP_CH3OPTS_RSVD_MASK) +/*! @} */ + +/*! @name CH3OPTS_SET - DCP channel 3 options register */ +/*! @{ */ +#define DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH3OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_SET_RECOVERY_TIMER_MASK) +#define DCP_CH3OPTS_SET_RSVD_MASK (0xFFFF0000U) +#define DCP_CH3OPTS_SET_RSVD_SHIFT (16U) +#define DCP_CH3OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_SET_RSVD_SHIFT)) & DCP_CH3OPTS_SET_RSVD_MASK) +/*! @} */ + +/*! @name CH3OPTS_CLR - DCP channel 3 options register */ +/*! @{ */ +#define DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH3OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_CLR_RECOVERY_TIMER_MASK) +#define DCP_CH3OPTS_CLR_RSVD_MASK (0xFFFF0000U) +#define DCP_CH3OPTS_CLR_RSVD_SHIFT (16U) +#define DCP_CH3OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_CLR_RSVD_SHIFT)) & DCP_CH3OPTS_CLR_RSVD_MASK) +/*! @} */ + +/*! @name CH3OPTS_TOG - DCP channel 3 options register */ +/*! @{ */ +#define DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU) +#define DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT (0U) +#define DCP_CH3OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH3OPTS_TOG_RECOVERY_TIMER_MASK) +#define DCP_CH3OPTS_TOG_RSVD_MASK (0xFFFF0000U) +#define DCP_CH3OPTS_TOG_RSVD_SHIFT (16U) +#define DCP_CH3OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH3OPTS_TOG_RSVD_SHIFT)) & DCP_CH3OPTS_TOG_RSVD_MASK) +/*! @} */ + +/*! @name DBGSELECT - DCP debug select register */ +/*! @{ */ +#define DCP_DBGSELECT_INDEX_MASK (0xFFU) +#define DCP_DBGSELECT_INDEX_SHIFT (0U) +/*! INDEX + * 0b00000001..CONTROL + * 0b00010000..OTPKEY0 + * 0b00010001..OTPKEY1 + * 0b00010010..OTPKEY2 + * 0b00010011..OTPKEY3 + */ +#define DCP_DBGSELECT_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_INDEX_SHIFT)) & DCP_DBGSELECT_INDEX_MASK) +#define DCP_DBGSELECT_RSVD_MASK (0xFFFFFF00U) +#define DCP_DBGSELECT_RSVD_SHIFT (8U) +#define DCP_DBGSELECT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGSELECT_RSVD_SHIFT)) & DCP_DBGSELECT_RSVD_MASK) +/*! @} */ + +/*! @name DBGDATA - DCP debug data register */ +/*! @{ */ +#define DCP_DBGDATA_DATA_MASK (0xFFFFFFFFU) +#define DCP_DBGDATA_DATA_SHIFT (0U) +#define DCP_DBGDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_DBGDATA_DATA_SHIFT)) & DCP_DBGDATA_DATA_MASK) +/*! @} */ + +/*! @name PAGETABLE - DCP page table register */ +/*! @{ */ +#define DCP_PAGETABLE_ENABLE_MASK (0x1U) +#define DCP_PAGETABLE_ENABLE_SHIFT (0U) +#define DCP_PAGETABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_ENABLE_SHIFT)) & DCP_PAGETABLE_ENABLE_MASK) +#define DCP_PAGETABLE_FLUSH_MASK (0x2U) +#define DCP_PAGETABLE_FLUSH_SHIFT (1U) +#define DCP_PAGETABLE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_FLUSH_SHIFT)) & DCP_PAGETABLE_FLUSH_MASK) +#define DCP_PAGETABLE_BASE_MASK (0xFFFFFFFCU) +#define DCP_PAGETABLE_BASE_SHIFT (2U) +#define DCP_PAGETABLE_BASE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PAGETABLE_BASE_SHIFT)) & DCP_PAGETABLE_BASE_MASK) +/*! @} */ + +/*! @name VERSION - DCP version register */ +/*! @{ */ +#define DCP_VERSION_STEP_MASK (0xFFFFU) +#define DCP_VERSION_STEP_SHIFT (0U) +#define DCP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_STEP_SHIFT)) & DCP_VERSION_STEP_MASK) +#define DCP_VERSION_MINOR_MASK (0xFF0000U) +#define DCP_VERSION_MINOR_SHIFT (16U) +#define DCP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MINOR_SHIFT)) & DCP_VERSION_MINOR_MASK) +#define DCP_VERSION_MAJOR_MASK (0xFF000000U) +#define DCP_VERSION_MAJOR_SHIFT (24U) +#define DCP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DCP_VERSION_MAJOR_SHIFT)) & DCP_VERSION_MAJOR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DCP_Register_Masks */ + + +/* DCP - Peripheral instance base addresses */ +/** Peripheral DCP base address */ +#define DCP_BASE (0x402FC000u) +/** Peripheral DCP base pointer */ +#define DCP ((DCP_Type *)DCP_BASE) +/** Array initializer of DCP peripheral base addresses */ +#define DCP_BASE_ADDRS { DCP_BASE } +/** Array initializer of DCP peripheral base pointers */ +#define DCP_BASE_PTRS { DCP } +/** Interrupt vectors for the DCP peripheral type */ +#define DCP_IRQS { DCP_IRQn } +#define DCP_VMI_IRQS { DCP_VMI_IRQn } + +/*! + * @} + */ /* end of group DCP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control Register, offset: 0x0 */ + __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ + uint8_t RESERVED_1[4]; + __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ + __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ + __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ + __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ + __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ + __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ + __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ + __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ + __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ + uint8_t RESERVED_2[4]; + __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ + uint8_t RESERVED_4[4]; + __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ + uint8_t RESERVED_5[12]; + __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */ + uint8_t RESERVED_6[184]; + __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ + __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ + __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ + __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ + __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */ + __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */ + __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */ + __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */ + __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */ + __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */ + __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */ + __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */ + __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */ + __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */ + __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */ + __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */ + __IO uint8_t DCHPRI19; /**< Channel n Priority Register, offset: 0x110 */ + __IO uint8_t DCHPRI18; /**< Channel n Priority Register, offset: 0x111 */ + __IO uint8_t DCHPRI17; /**< Channel n Priority Register, offset: 0x112 */ + __IO uint8_t DCHPRI16; /**< Channel n Priority Register, offset: 0x113 */ + __IO uint8_t DCHPRI23; /**< Channel n Priority Register, offset: 0x114 */ + __IO uint8_t DCHPRI22; /**< Channel n Priority Register, offset: 0x115 */ + __IO uint8_t DCHPRI21; /**< Channel n Priority Register, offset: 0x116 */ + __IO uint8_t DCHPRI20; /**< Channel n Priority Register, offset: 0x117 */ + __IO uint8_t DCHPRI27; /**< Channel n Priority Register, offset: 0x118 */ + __IO uint8_t DCHPRI26; /**< Channel n Priority Register, offset: 0x119 */ + __IO uint8_t DCHPRI25; /**< Channel n Priority Register, offset: 0x11A */ + __IO uint8_t DCHPRI24; /**< Channel n Priority Register, offset: 0x11B */ + __IO uint8_t DCHPRI31; /**< Channel n Priority Register, offset: 0x11C */ + __IO uint8_t DCHPRI30; /**< Channel n Priority Register, offset: 0x11D */ + __IO uint8_t DCHPRI29; /**< Channel n Priority Register, offset: 0x11E */ + __IO uint8_t DCHPRI28; /**< Channel n Priority Register, offset: 0x11F */ + uint8_t RESERVED_7[3808]; + struct { /* offset: 0x1000, array step: 0x20 */ + __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ + __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ + __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ + union { /* offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */ + }; + __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ + __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ + __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ + union { /* offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ + }; + __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ + __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ + union { /* offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ + }; + } TCD[32]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CR - Control Register */ +/*! @{ */ +#define DMA_CR_EDBG_MASK (0x2U) +#define DMA_CR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..When in debug mode, the DMA continues to operate. + * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to + * complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. + */ +#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) +#define DMA_CR_ERCA_MASK (0x4U) +#define DMA_CR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Fixed priority arbitration is used for channel selection within each group. + * 0b1..Round robin arbitration is used for channel selection within each group. + */ +#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) +#define DMA_CR_ERGA_MASK (0x8U) +#define DMA_CR_ERGA_SHIFT (3U) +/*! ERGA - Enable Round Robin Group Arbitration + * 0b0..Fixed priority arbitration is used for selection among the groups. + * 0b1..Round robin arbitration is used for selection among the groups. + */ +#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK) +#define DMA_CR_HOE_MASK (0x10U) +#define DMA_CR_HOE_SHIFT (4U) +/*! HOE - Halt On Error + * 0b0..Normal operation + * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. + */ +#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) +#define DMA_CR_HALT_MASK (0x20U) +#define DMA_CR_HALT_SHIFT (5U) +/*! HALT - Halt DMA Operations + * 0b0..Normal operation + * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. + */ +#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) +#define DMA_CR_CLM_MASK (0x40U) +#define DMA_CR_CLM_SHIFT (6U) +/*! CLM - Continuous Link Mode + * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again. + * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated + * again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel + * link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the + * next minor loop. + */ +#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) +#define DMA_CR_EMLM_MASK (0x80U) +#define DMA_CR_EMLM_SHIFT (7U) +/*! EMLM - Enable Minor Loop Mapping + * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. + * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES + * field. The individual enable fields allow the minor loop offset to be applied to the source address, the + * destination address, or both. The NBYTES field is reduced when either offset is enabled. + */ +#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) +#define DMA_CR_GRP0PRI_MASK (0x100U) +#define DMA_CR_GRP0PRI_SHIFT (8U) +#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK) +#define DMA_CR_GRP1PRI_MASK (0x400U) +#define DMA_CR_GRP1PRI_SHIFT (10U) +#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK) +#define DMA_CR_ECX_MASK (0x10000U) +#define DMA_CR_ECX_SHIFT (16U) +/*! ECX - Error Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and + * force the minor loop to finish. The cancel takes effect after the last write of the current read/write + * sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX + * treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an + * optional error interrupt. + */ +#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) +#define DMA_CR_CX_MASK (0x20000U) +#define DMA_CR_CX_SHIFT (17U) +/*! CX - Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The + * cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after + * the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. + */ +#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) +#define DMA_CR_ACTIVE_MASK (0x80000000U) +#define DMA_CR_ACTIVE_SHIFT (31U) +/*! ACTIVE - DMA Active Status + * 0b0..eDMA is idle. + * 0b1..eDMA is executing a channel. + */ +#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) +/*! @} */ + +/*! @name ES - Error Status Register */ +/*! @{ */ +#define DMA_ES_DBE_MASK (0x1U) +#define DMA_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..The last recorded error was a bus error on a destination write + */ +#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) +#define DMA_ES_SBE_MASK (0x2U) +#define DMA_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..The last recorded error was a bus error on a source read + */ +#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) +#define DMA_ES_SGE_MASK (0x4U) +#define DMA_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is + * checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is + * enabled. TCDn_DLASTSGA is not on a 32 byte boundary. + */ +#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) +#define DMA_ES_NCE_MASK (0x8U) +#define DMA_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. + * TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, + * or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] + */ +#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) +#define DMA_ES_DOE_MASK (0x10U) +#define DMA_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. + */ +#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) +#define DMA_ES_DAE_MASK (0x20U) +#define DMA_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. + */ +#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) +#define DMA_ES_SOE_MASK (0x40U) +#define DMA_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. + */ +#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) +#define DMA_ES_SAE_MASK (0x80U) +#define DMA_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error. + * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. + */ +#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) +#define DMA_ES_ERRCHN_MASK (0x1F00U) +#define DMA_ES_ERRCHN_SHIFT (8U) +#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) +#define DMA_ES_CPE_MASK (0x4000U) +#define DMA_ES_CPE_SHIFT (14U) +/*! CPE - Channel Priority Error + * 0b0..No channel priority error + * 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel + * priorities within a group are not unique. + */ +#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) +#define DMA_ES_GPE_MASK (0x8000U) +#define DMA_ES_GPE_SHIFT (15U) +/*! GPE - Group Priority Error + * 0b0..No group priority error + * 0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique. + */ +#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK) +#define DMA_ES_ECX_MASK (0x10000U) +#define DMA_ES_ECX_SHIFT (16U) +/*! ECX - Transfer Canceled + * 0b0..No canceled transfers + * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input + */ +#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) +#define DMA_ES_VLD_MASK (0x80000000U) +#define DMA_ES_VLD_SHIFT (31U) +/*! VLD - VLD + * 0b0..No ERR bits are set. + * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared. + */ +#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) +/*! @} */ + +/*! @name ERQ - Enable Request Register */ +/*! @{ */ +#define DMA_ERQ_ERQ0_MASK (0x1U) +#define DMA_ERQ_ERQ0_SHIFT (0U) +/*! ERQ0 - Enable DMA Request 0 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) +#define DMA_ERQ_ERQ1_MASK (0x2U) +#define DMA_ERQ_ERQ1_SHIFT (1U) +/*! ERQ1 - Enable DMA Request 1 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) +#define DMA_ERQ_ERQ2_MASK (0x4U) +#define DMA_ERQ_ERQ2_SHIFT (2U) +/*! ERQ2 - Enable DMA Request 2 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) +#define DMA_ERQ_ERQ3_MASK (0x8U) +#define DMA_ERQ_ERQ3_SHIFT (3U) +/*! ERQ3 - Enable DMA Request 3 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) +#define DMA_ERQ_ERQ4_MASK (0x10U) +#define DMA_ERQ_ERQ4_SHIFT (4U) +/*! ERQ4 - Enable DMA Request 4 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) +#define DMA_ERQ_ERQ5_MASK (0x20U) +#define DMA_ERQ_ERQ5_SHIFT (5U) +/*! ERQ5 - Enable DMA Request 5 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) +#define DMA_ERQ_ERQ6_MASK (0x40U) +#define DMA_ERQ_ERQ6_SHIFT (6U) +/*! ERQ6 - Enable DMA Request 6 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) +#define DMA_ERQ_ERQ7_MASK (0x80U) +#define DMA_ERQ_ERQ7_SHIFT (7U) +/*! ERQ7 - Enable DMA Request 7 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) +#define DMA_ERQ_ERQ8_MASK (0x100U) +#define DMA_ERQ_ERQ8_SHIFT (8U) +/*! ERQ8 - Enable DMA Request 8 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) +#define DMA_ERQ_ERQ9_MASK (0x200U) +#define DMA_ERQ_ERQ9_SHIFT (9U) +/*! ERQ9 - Enable DMA Request 9 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) +#define DMA_ERQ_ERQ10_MASK (0x400U) +#define DMA_ERQ_ERQ10_SHIFT (10U) +/*! ERQ10 - Enable DMA Request 10 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) +#define DMA_ERQ_ERQ11_MASK (0x800U) +#define DMA_ERQ_ERQ11_SHIFT (11U) +/*! ERQ11 - Enable DMA Request 11 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) +#define DMA_ERQ_ERQ12_MASK (0x1000U) +#define DMA_ERQ_ERQ12_SHIFT (12U) +/*! ERQ12 - Enable DMA Request 12 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) +#define DMA_ERQ_ERQ13_MASK (0x2000U) +#define DMA_ERQ_ERQ13_SHIFT (13U) +/*! ERQ13 - Enable DMA Request 13 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) +#define DMA_ERQ_ERQ14_MASK (0x4000U) +#define DMA_ERQ_ERQ14_SHIFT (14U) +/*! ERQ14 - Enable DMA Request 14 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) +#define DMA_ERQ_ERQ15_MASK (0x8000U) +#define DMA_ERQ_ERQ15_SHIFT (15U) +/*! ERQ15 - Enable DMA Request 15 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) +#define DMA_ERQ_ERQ16_MASK (0x10000U) +#define DMA_ERQ_ERQ16_SHIFT (16U) +/*! ERQ16 - Enable DMA Request 16 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK) +#define DMA_ERQ_ERQ17_MASK (0x20000U) +#define DMA_ERQ_ERQ17_SHIFT (17U) +/*! ERQ17 - Enable DMA Request 17 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK) +#define DMA_ERQ_ERQ18_MASK (0x40000U) +#define DMA_ERQ_ERQ18_SHIFT (18U) +/*! ERQ18 - Enable DMA Request 18 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK) +#define DMA_ERQ_ERQ19_MASK (0x80000U) +#define DMA_ERQ_ERQ19_SHIFT (19U) +/*! ERQ19 - Enable DMA Request 19 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK) +#define DMA_ERQ_ERQ20_MASK (0x100000U) +#define DMA_ERQ_ERQ20_SHIFT (20U) +/*! ERQ20 - Enable DMA Request 20 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK) +#define DMA_ERQ_ERQ21_MASK (0x200000U) +#define DMA_ERQ_ERQ21_SHIFT (21U) +/*! ERQ21 - Enable DMA Request 21 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK) +#define DMA_ERQ_ERQ22_MASK (0x400000U) +#define DMA_ERQ_ERQ22_SHIFT (22U) +/*! ERQ22 - Enable DMA Request 22 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK) +#define DMA_ERQ_ERQ23_MASK (0x800000U) +#define DMA_ERQ_ERQ23_SHIFT (23U) +/*! ERQ23 - Enable DMA Request 23 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK) +#define DMA_ERQ_ERQ24_MASK (0x1000000U) +#define DMA_ERQ_ERQ24_SHIFT (24U) +/*! ERQ24 - Enable DMA Request 24 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK) +#define DMA_ERQ_ERQ25_MASK (0x2000000U) +#define DMA_ERQ_ERQ25_SHIFT (25U) +/*! ERQ25 - Enable DMA Request 25 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK) +#define DMA_ERQ_ERQ26_MASK (0x4000000U) +#define DMA_ERQ_ERQ26_SHIFT (26U) +/*! ERQ26 - Enable DMA Request 26 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK) +#define DMA_ERQ_ERQ27_MASK (0x8000000U) +#define DMA_ERQ_ERQ27_SHIFT (27U) +/*! ERQ27 - Enable DMA Request 27 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK) +#define DMA_ERQ_ERQ28_MASK (0x10000000U) +#define DMA_ERQ_ERQ28_SHIFT (28U) +/*! ERQ28 - Enable DMA Request 28 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK) +#define DMA_ERQ_ERQ29_MASK (0x20000000U) +#define DMA_ERQ_ERQ29_SHIFT (29U) +/*! ERQ29 - Enable DMA Request 29 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK) +#define DMA_ERQ_ERQ30_MASK (0x40000000U) +#define DMA_ERQ_ERQ30_SHIFT (30U) +/*! ERQ30 - Enable DMA Request 30 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK) +#define DMA_ERQ_ERQ31_MASK (0x80000000U) +#define DMA_ERQ_ERQ31_SHIFT (31U) +/*! ERQ31 - Enable DMA Request 31 + * 0b0..The DMA request signal for the corresponding channel is disabled + * 0b1..The DMA request signal for the corresponding channel is enabled + */ +#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK) +/*! @} */ + +/*! @name EEI - Enable Error Interrupt Register */ +/*! @{ */ +#define DMA_EEI_EEI0_MASK (0x1U) +#define DMA_EEI_EEI0_SHIFT (0U) +/*! EEI0 - Enable Error Interrupt 0 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) +#define DMA_EEI_EEI1_MASK (0x2U) +#define DMA_EEI_EEI1_SHIFT (1U) +/*! EEI1 - Enable Error Interrupt 1 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) +#define DMA_EEI_EEI2_MASK (0x4U) +#define DMA_EEI_EEI2_SHIFT (2U) +/*! EEI2 - Enable Error Interrupt 2 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) +#define DMA_EEI_EEI3_MASK (0x8U) +#define DMA_EEI_EEI3_SHIFT (3U) +/*! EEI3 - Enable Error Interrupt 3 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) +#define DMA_EEI_EEI4_MASK (0x10U) +#define DMA_EEI_EEI4_SHIFT (4U) +/*! EEI4 - Enable Error Interrupt 4 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) +#define DMA_EEI_EEI5_MASK (0x20U) +#define DMA_EEI_EEI5_SHIFT (5U) +/*! EEI5 - Enable Error Interrupt 5 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) +#define DMA_EEI_EEI6_MASK (0x40U) +#define DMA_EEI_EEI6_SHIFT (6U) +/*! EEI6 - Enable Error Interrupt 6 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) +#define DMA_EEI_EEI7_MASK (0x80U) +#define DMA_EEI_EEI7_SHIFT (7U) +/*! EEI7 - Enable Error Interrupt 7 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) +#define DMA_EEI_EEI8_MASK (0x100U) +#define DMA_EEI_EEI8_SHIFT (8U) +/*! EEI8 - Enable Error Interrupt 8 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) +#define DMA_EEI_EEI9_MASK (0x200U) +#define DMA_EEI_EEI9_SHIFT (9U) +/*! EEI9 - Enable Error Interrupt 9 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) +#define DMA_EEI_EEI10_MASK (0x400U) +#define DMA_EEI_EEI10_SHIFT (10U) +/*! EEI10 - Enable Error Interrupt 10 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) +#define DMA_EEI_EEI11_MASK (0x800U) +#define DMA_EEI_EEI11_SHIFT (11U) +/*! EEI11 - Enable Error Interrupt 11 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) +#define DMA_EEI_EEI12_MASK (0x1000U) +#define DMA_EEI_EEI12_SHIFT (12U) +/*! EEI12 - Enable Error Interrupt 12 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) +#define DMA_EEI_EEI13_MASK (0x2000U) +#define DMA_EEI_EEI13_SHIFT (13U) +/*! EEI13 - Enable Error Interrupt 13 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) +#define DMA_EEI_EEI14_MASK (0x4000U) +#define DMA_EEI_EEI14_SHIFT (14U) +/*! EEI14 - Enable Error Interrupt 14 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) +#define DMA_EEI_EEI15_MASK (0x8000U) +#define DMA_EEI_EEI15_SHIFT (15U) +/*! EEI15 - Enable Error Interrupt 15 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) +#define DMA_EEI_EEI16_MASK (0x10000U) +#define DMA_EEI_EEI16_SHIFT (16U) +/*! EEI16 - Enable Error Interrupt 16 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK) +#define DMA_EEI_EEI17_MASK (0x20000U) +#define DMA_EEI_EEI17_SHIFT (17U) +/*! EEI17 - Enable Error Interrupt 17 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK) +#define DMA_EEI_EEI18_MASK (0x40000U) +#define DMA_EEI_EEI18_SHIFT (18U) +/*! EEI18 - Enable Error Interrupt 18 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK) +#define DMA_EEI_EEI19_MASK (0x80000U) +#define DMA_EEI_EEI19_SHIFT (19U) +/*! EEI19 - Enable Error Interrupt 19 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK) +#define DMA_EEI_EEI20_MASK (0x100000U) +#define DMA_EEI_EEI20_SHIFT (20U) +/*! EEI20 - Enable Error Interrupt 20 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK) +#define DMA_EEI_EEI21_MASK (0x200000U) +#define DMA_EEI_EEI21_SHIFT (21U) +/*! EEI21 - Enable Error Interrupt 21 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK) +#define DMA_EEI_EEI22_MASK (0x400000U) +#define DMA_EEI_EEI22_SHIFT (22U) +/*! EEI22 - Enable Error Interrupt 22 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK) +#define DMA_EEI_EEI23_MASK (0x800000U) +#define DMA_EEI_EEI23_SHIFT (23U) +/*! EEI23 - Enable Error Interrupt 23 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK) +#define DMA_EEI_EEI24_MASK (0x1000000U) +#define DMA_EEI_EEI24_SHIFT (24U) +/*! EEI24 - Enable Error Interrupt 24 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK) +#define DMA_EEI_EEI25_MASK (0x2000000U) +#define DMA_EEI_EEI25_SHIFT (25U) +/*! EEI25 - Enable Error Interrupt 25 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK) +#define DMA_EEI_EEI26_MASK (0x4000000U) +#define DMA_EEI_EEI26_SHIFT (26U) +/*! EEI26 - Enable Error Interrupt 26 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK) +#define DMA_EEI_EEI27_MASK (0x8000000U) +#define DMA_EEI_EEI27_SHIFT (27U) +/*! EEI27 - Enable Error Interrupt 27 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK) +#define DMA_EEI_EEI28_MASK (0x10000000U) +#define DMA_EEI_EEI28_SHIFT (28U) +/*! EEI28 - Enable Error Interrupt 28 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK) +#define DMA_EEI_EEI29_MASK (0x20000000U) +#define DMA_EEI_EEI29_SHIFT (29U) +/*! EEI29 - Enable Error Interrupt 29 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK) +#define DMA_EEI_EEI30_MASK (0x40000000U) +#define DMA_EEI_EEI30_SHIFT (30U) +/*! EEI30 - Enable Error Interrupt 30 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK) +#define DMA_EEI_EEI31_MASK (0x80000000U) +#define DMA_EEI_EEI31_SHIFT (31U) +/*! EEI31 - Enable Error Interrupt 31 + * 0b0..The error signal for corresponding channel does not generate an error interrupt + * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request + */ +#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK) +/*! @} */ + +/*! @name CEEI - Clear Enable Error Interrupt Register */ +/*! @{ */ +#define DMA_CEEI_CEEI_MASK (0x1FU) +#define DMA_CEEI_CEEI_SHIFT (0U) +#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) +#define DMA_CEEI_CAEE_MASK (0x40U) +#define DMA_CEEI_CAEE_SHIFT (6U) +/*! CAEE - Clear All Enable Error Interrupts + * 0b0..Clear only the EEI bit specified in the CEEI field + * 0b1..Clear all bits in EEI + */ +#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) +#define DMA_CEEI_NOP_MASK (0x80U) +#define DMA_CEEI_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) +/*! @} */ + +/*! @name SEEI - Set Enable Error Interrupt Register */ +/*! @{ */ +#define DMA_SEEI_SEEI_MASK (0x1FU) +#define DMA_SEEI_SEEI_SHIFT (0U) +#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) +#define DMA_SEEI_SAEE_MASK (0x40U) +#define DMA_SEEI_SAEE_SHIFT (6U) +/*! SAEE - Sets All Enable Error Interrupts + * 0b0..Set only the EEI bit specified in the SEEI field. + * 0b1..Sets all bits in EEI + */ +#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) +#define DMA_SEEI_NOP_MASK (0x80U) +#define DMA_SEEI_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) +/*! @} */ + +/*! @name CERQ - Clear Enable Request Register */ +/*! @{ */ +#define DMA_CERQ_CERQ_MASK (0x1FU) +#define DMA_CERQ_CERQ_SHIFT (0U) +#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) +#define DMA_CERQ_CAER_MASK (0x40U) +#define DMA_CERQ_CAER_SHIFT (6U) +/*! CAER - Clear All Enable Requests + * 0b0..Clear only the ERQ bit specified in the CERQ field + * 0b1..Clear all bits in ERQ + */ +#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) +#define DMA_CERQ_NOP_MASK (0x80U) +#define DMA_CERQ_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) +/*! @} */ + +/*! @name SERQ - Set Enable Request Register */ +/*! @{ */ +#define DMA_SERQ_SERQ_MASK (0x1FU) +#define DMA_SERQ_SERQ_SHIFT (0U) +#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) +#define DMA_SERQ_SAER_MASK (0x40U) +#define DMA_SERQ_SAER_SHIFT (6U) +/*! SAER - Set All Enable Requests + * 0b0..Set only the ERQ bit specified in the SERQ field + * 0b1..Set all bits in ERQ + */ +#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) +#define DMA_SERQ_NOP_MASK (0x80U) +#define DMA_SERQ_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) +/*! @} */ + +/*! @name CDNE - Clear DONE Status Bit Register */ +/*! @{ */ +#define DMA_CDNE_CDNE_MASK (0x1FU) +#define DMA_CDNE_CDNE_SHIFT (0U) +#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) +#define DMA_CDNE_CADN_MASK (0x40U) +#define DMA_CDNE_CADN_SHIFT (6U) +/*! CADN - Clears All DONE Bits + * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field + * 0b1..Clears all bits in TCDn_CSR[DONE] + */ +#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) +#define DMA_CDNE_NOP_MASK (0x80U) +#define DMA_CDNE_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) +/*! @} */ + +/*! @name SSRT - Set START Bit Register */ +/*! @{ */ +#define DMA_SSRT_SSRT_MASK (0x1FU) +#define DMA_SSRT_SSRT_SHIFT (0U) +#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) +#define DMA_SSRT_SAST_MASK (0x40U) +#define DMA_SSRT_SAST_SHIFT (6U) +/*! SAST - Set All START Bits (activates all channels) + * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field + * 0b1..Set all bits in TCDn_CSR[START] + */ +#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) +#define DMA_SSRT_NOP_MASK (0x80U) +#define DMA_SSRT_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) +/*! @} */ + +/*! @name CERR - Clear Error Register */ +/*! @{ */ +#define DMA_CERR_CERR_MASK (0x1FU) +#define DMA_CERR_CERR_SHIFT (0U) +#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) +#define DMA_CERR_CAEI_MASK (0x40U) +#define DMA_CERR_CAEI_SHIFT (6U) +/*! CAEI - Clear All Error Indicators + * 0b0..Clear only the ERR bit specified in the CERR field + * 0b1..Clear all bits in ERR + */ +#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) +#define DMA_CERR_NOP_MASK (0x80U) +#define DMA_CERR_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) +/*! @} */ + +/*! @name CINT - Clear Interrupt Request Register */ +/*! @{ */ +#define DMA_CINT_CINT_MASK (0x1FU) +#define DMA_CINT_CINT_SHIFT (0U) +#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) +#define DMA_CINT_CAIR_MASK (0x40U) +#define DMA_CINT_CAIR_SHIFT (6U) +/*! CAIR - Clear All Interrupt Requests + * 0b0..Clear only the INT bit specified in the CINT field + * 0b1..Clear all bits in INT + */ +#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) +#define DMA_CINT_NOP_MASK (0x80U) +#define DMA_CINT_NOP_SHIFT (7U) +/*! NOP - No Op enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other bits in this register + */ +#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) +/*! @} */ + +/*! @name INT - Interrupt Request Register */ +/*! @{ */ +#define DMA_INT_INT0_MASK (0x1U) +#define DMA_INT_INT0_SHIFT (0U) +/*! INT0 - Interrupt Request 0 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) +#define DMA_INT_INT1_MASK (0x2U) +#define DMA_INT_INT1_SHIFT (1U) +/*! INT1 - Interrupt Request 1 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) +#define DMA_INT_INT2_MASK (0x4U) +#define DMA_INT_INT2_SHIFT (2U) +/*! INT2 - Interrupt Request 2 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) +#define DMA_INT_INT3_MASK (0x8U) +#define DMA_INT_INT3_SHIFT (3U) +/*! INT3 - Interrupt Request 3 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) +#define DMA_INT_INT4_MASK (0x10U) +#define DMA_INT_INT4_SHIFT (4U) +/*! INT4 - Interrupt Request 4 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) +#define DMA_INT_INT5_MASK (0x20U) +#define DMA_INT_INT5_SHIFT (5U) +/*! INT5 - Interrupt Request 5 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) +#define DMA_INT_INT6_MASK (0x40U) +#define DMA_INT_INT6_SHIFT (6U) +/*! INT6 - Interrupt Request 6 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) +#define DMA_INT_INT7_MASK (0x80U) +#define DMA_INT_INT7_SHIFT (7U) +/*! INT7 - Interrupt Request 7 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) +#define DMA_INT_INT8_MASK (0x100U) +#define DMA_INT_INT8_SHIFT (8U) +/*! INT8 - Interrupt Request 8 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) +#define DMA_INT_INT9_MASK (0x200U) +#define DMA_INT_INT9_SHIFT (9U) +/*! INT9 - Interrupt Request 9 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) +#define DMA_INT_INT10_MASK (0x400U) +#define DMA_INT_INT10_SHIFT (10U) +/*! INT10 - Interrupt Request 10 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) +#define DMA_INT_INT11_MASK (0x800U) +#define DMA_INT_INT11_SHIFT (11U) +/*! INT11 - Interrupt Request 11 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) +#define DMA_INT_INT12_MASK (0x1000U) +#define DMA_INT_INT12_SHIFT (12U) +/*! INT12 - Interrupt Request 12 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) +#define DMA_INT_INT13_MASK (0x2000U) +#define DMA_INT_INT13_SHIFT (13U) +/*! INT13 - Interrupt Request 13 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) +#define DMA_INT_INT14_MASK (0x4000U) +#define DMA_INT_INT14_SHIFT (14U) +/*! INT14 - Interrupt Request 14 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) +#define DMA_INT_INT15_MASK (0x8000U) +#define DMA_INT_INT15_SHIFT (15U) +/*! INT15 - Interrupt Request 15 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) +#define DMA_INT_INT16_MASK (0x10000U) +#define DMA_INT_INT16_SHIFT (16U) +/*! INT16 - Interrupt Request 16 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK) +#define DMA_INT_INT17_MASK (0x20000U) +#define DMA_INT_INT17_SHIFT (17U) +/*! INT17 - Interrupt Request 17 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK) +#define DMA_INT_INT18_MASK (0x40000U) +#define DMA_INT_INT18_SHIFT (18U) +/*! INT18 - Interrupt Request 18 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK) +#define DMA_INT_INT19_MASK (0x80000U) +#define DMA_INT_INT19_SHIFT (19U) +/*! INT19 - Interrupt Request 19 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK) +#define DMA_INT_INT20_MASK (0x100000U) +#define DMA_INT_INT20_SHIFT (20U) +/*! INT20 - Interrupt Request 20 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK) +#define DMA_INT_INT21_MASK (0x200000U) +#define DMA_INT_INT21_SHIFT (21U) +/*! INT21 - Interrupt Request 21 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK) +#define DMA_INT_INT22_MASK (0x400000U) +#define DMA_INT_INT22_SHIFT (22U) +/*! INT22 - Interrupt Request 22 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK) +#define DMA_INT_INT23_MASK (0x800000U) +#define DMA_INT_INT23_SHIFT (23U) +/*! INT23 - Interrupt Request 23 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK) +#define DMA_INT_INT24_MASK (0x1000000U) +#define DMA_INT_INT24_SHIFT (24U) +/*! INT24 - Interrupt Request 24 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK) +#define DMA_INT_INT25_MASK (0x2000000U) +#define DMA_INT_INT25_SHIFT (25U) +/*! INT25 - Interrupt Request 25 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK) +#define DMA_INT_INT26_MASK (0x4000000U) +#define DMA_INT_INT26_SHIFT (26U) +/*! INT26 - Interrupt Request 26 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK) +#define DMA_INT_INT27_MASK (0x8000000U) +#define DMA_INT_INT27_SHIFT (27U) +/*! INT27 - Interrupt Request 27 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK) +#define DMA_INT_INT28_MASK (0x10000000U) +#define DMA_INT_INT28_SHIFT (28U) +/*! INT28 - Interrupt Request 28 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK) +#define DMA_INT_INT29_MASK (0x20000000U) +#define DMA_INT_INT29_SHIFT (29U) +/*! INT29 - Interrupt Request 29 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK) +#define DMA_INT_INT30_MASK (0x40000000U) +#define DMA_INT_INT30_SHIFT (30U) +/*! INT30 - Interrupt Request 30 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK) +#define DMA_INT_INT31_MASK (0x80000000U) +#define DMA_INT_INT31_SHIFT (31U) +/*! INT31 - Interrupt Request 31 + * 0b0..The interrupt request for corresponding channel is cleared + * 0b1..The interrupt request for corresponding channel is active + */ +#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK) +/*! @} */ + +/*! @name ERR - Error Register */ +/*! @{ */ +#define DMA_ERR_ERR0_MASK (0x1U) +#define DMA_ERR_ERR0_SHIFT (0U) +/*! ERR0 - Error In Channel 0 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) +#define DMA_ERR_ERR1_MASK (0x2U) +#define DMA_ERR_ERR1_SHIFT (1U) +/*! ERR1 - Error In Channel 1 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) +#define DMA_ERR_ERR2_MASK (0x4U) +#define DMA_ERR_ERR2_SHIFT (2U) +/*! ERR2 - Error In Channel 2 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) +#define DMA_ERR_ERR3_MASK (0x8U) +#define DMA_ERR_ERR3_SHIFT (3U) +/*! ERR3 - Error In Channel 3 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) +#define DMA_ERR_ERR4_MASK (0x10U) +#define DMA_ERR_ERR4_SHIFT (4U) +/*! ERR4 - Error In Channel 4 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) +#define DMA_ERR_ERR5_MASK (0x20U) +#define DMA_ERR_ERR5_SHIFT (5U) +/*! ERR5 - Error In Channel 5 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) +#define DMA_ERR_ERR6_MASK (0x40U) +#define DMA_ERR_ERR6_SHIFT (6U) +/*! ERR6 - Error In Channel 6 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) +#define DMA_ERR_ERR7_MASK (0x80U) +#define DMA_ERR_ERR7_SHIFT (7U) +/*! ERR7 - Error In Channel 7 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) +#define DMA_ERR_ERR8_MASK (0x100U) +#define DMA_ERR_ERR8_SHIFT (8U) +/*! ERR8 - Error In Channel 8 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) +#define DMA_ERR_ERR9_MASK (0x200U) +#define DMA_ERR_ERR9_SHIFT (9U) +/*! ERR9 - Error In Channel 9 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) +#define DMA_ERR_ERR10_MASK (0x400U) +#define DMA_ERR_ERR10_SHIFT (10U) +/*! ERR10 - Error In Channel 10 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) +#define DMA_ERR_ERR11_MASK (0x800U) +#define DMA_ERR_ERR11_SHIFT (11U) +/*! ERR11 - Error In Channel 11 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) +#define DMA_ERR_ERR12_MASK (0x1000U) +#define DMA_ERR_ERR12_SHIFT (12U) +/*! ERR12 - Error In Channel 12 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) +#define DMA_ERR_ERR13_MASK (0x2000U) +#define DMA_ERR_ERR13_SHIFT (13U) +/*! ERR13 - Error In Channel 13 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) +#define DMA_ERR_ERR14_MASK (0x4000U) +#define DMA_ERR_ERR14_SHIFT (14U) +/*! ERR14 - Error In Channel 14 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) +#define DMA_ERR_ERR15_MASK (0x8000U) +#define DMA_ERR_ERR15_SHIFT (15U) +/*! ERR15 - Error In Channel 15 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) +#define DMA_ERR_ERR16_MASK (0x10000U) +#define DMA_ERR_ERR16_SHIFT (16U) +/*! ERR16 - Error In Channel 16 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK) +#define DMA_ERR_ERR17_MASK (0x20000U) +#define DMA_ERR_ERR17_SHIFT (17U) +/*! ERR17 - Error In Channel 17 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK) +#define DMA_ERR_ERR18_MASK (0x40000U) +#define DMA_ERR_ERR18_SHIFT (18U) +/*! ERR18 - Error In Channel 18 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK) +#define DMA_ERR_ERR19_MASK (0x80000U) +#define DMA_ERR_ERR19_SHIFT (19U) +/*! ERR19 - Error In Channel 19 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK) +#define DMA_ERR_ERR20_MASK (0x100000U) +#define DMA_ERR_ERR20_SHIFT (20U) +/*! ERR20 - Error In Channel 20 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK) +#define DMA_ERR_ERR21_MASK (0x200000U) +#define DMA_ERR_ERR21_SHIFT (21U) +/*! ERR21 - Error In Channel 21 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK) +#define DMA_ERR_ERR22_MASK (0x400000U) +#define DMA_ERR_ERR22_SHIFT (22U) +/*! ERR22 - Error In Channel 22 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK) +#define DMA_ERR_ERR23_MASK (0x800000U) +#define DMA_ERR_ERR23_SHIFT (23U) +/*! ERR23 - Error In Channel 23 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK) +#define DMA_ERR_ERR24_MASK (0x1000000U) +#define DMA_ERR_ERR24_SHIFT (24U) +/*! ERR24 - Error In Channel 24 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK) +#define DMA_ERR_ERR25_MASK (0x2000000U) +#define DMA_ERR_ERR25_SHIFT (25U) +/*! ERR25 - Error In Channel 25 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK) +#define DMA_ERR_ERR26_MASK (0x4000000U) +#define DMA_ERR_ERR26_SHIFT (26U) +/*! ERR26 - Error In Channel 26 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK) +#define DMA_ERR_ERR27_MASK (0x8000000U) +#define DMA_ERR_ERR27_SHIFT (27U) +/*! ERR27 - Error In Channel 27 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK) +#define DMA_ERR_ERR28_MASK (0x10000000U) +#define DMA_ERR_ERR28_SHIFT (28U) +/*! ERR28 - Error In Channel 28 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK) +#define DMA_ERR_ERR29_MASK (0x20000000U) +#define DMA_ERR_ERR29_SHIFT (29U) +/*! ERR29 - Error In Channel 29 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK) +#define DMA_ERR_ERR30_MASK (0x40000000U) +#define DMA_ERR_ERR30_SHIFT (30U) +/*! ERR30 - Error In Channel 30 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK) +#define DMA_ERR_ERR31_MASK (0x80000000U) +#define DMA_ERR_ERR31_SHIFT (31U) +/*! ERR31 - Error In Channel 31 + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK) +/*! @} */ + +/*! @name HRS - Hardware Request Status Register */ +/*! @{ */ +#define DMA_HRS_HRS0_MASK (0x1U) +#define DMA_HRS_HRS0_SHIFT (0U) +/*! HRS0 - Hardware Request Status Channel 0 + * 0b0..A hardware service request for channel 0 is not present + * 0b1..A hardware service request for channel 0 is present + */ +#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) +#define DMA_HRS_HRS1_MASK (0x2U) +#define DMA_HRS_HRS1_SHIFT (1U) +/*! HRS1 - Hardware Request Status Channel 1 + * 0b0..A hardware service request for channel 1 is not present + * 0b1..A hardware service request for channel 1 is present + */ +#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) +#define DMA_HRS_HRS2_MASK (0x4U) +#define DMA_HRS_HRS2_SHIFT (2U) +/*! HRS2 - Hardware Request Status Channel 2 + * 0b0..A hardware service request for channel 2 is not present + * 0b1..A hardware service request for channel 2 is present + */ +#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) +#define DMA_HRS_HRS3_MASK (0x8U) +#define DMA_HRS_HRS3_SHIFT (3U) +/*! HRS3 - Hardware Request Status Channel 3 + * 0b0..A hardware service request for channel 3 is not present + * 0b1..A hardware service request for channel 3 is present + */ +#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) +#define DMA_HRS_HRS4_MASK (0x10U) +#define DMA_HRS_HRS4_SHIFT (4U) +/*! HRS4 - Hardware Request Status Channel 4 + * 0b0..A hardware service request for channel 4 is not present + * 0b1..A hardware service request for channel 4 is present + */ +#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) +#define DMA_HRS_HRS5_MASK (0x20U) +#define DMA_HRS_HRS5_SHIFT (5U) +/*! HRS5 - Hardware Request Status Channel 5 + * 0b0..A hardware service request for channel 5 is not present + * 0b1..A hardware service request for channel 5 is present + */ +#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) +#define DMA_HRS_HRS6_MASK (0x40U) +#define DMA_HRS_HRS6_SHIFT (6U) +/*! HRS6 - Hardware Request Status Channel 6 + * 0b0..A hardware service request for channel 6 is not present + * 0b1..A hardware service request for channel 6 is present + */ +#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) +#define DMA_HRS_HRS7_MASK (0x80U) +#define DMA_HRS_HRS7_SHIFT (7U) +/*! HRS7 - Hardware Request Status Channel 7 + * 0b0..A hardware service request for channel 7 is not present + * 0b1..A hardware service request for channel 7 is present + */ +#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) +#define DMA_HRS_HRS8_MASK (0x100U) +#define DMA_HRS_HRS8_SHIFT (8U) +/*! HRS8 - Hardware Request Status Channel 8 + * 0b0..A hardware service request for channel 8 is not present + * 0b1..A hardware service request for channel 8 is present + */ +#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) +#define DMA_HRS_HRS9_MASK (0x200U) +#define DMA_HRS_HRS9_SHIFT (9U) +/*! HRS9 - Hardware Request Status Channel 9 + * 0b0..A hardware service request for channel 9 is not present + * 0b1..A hardware service request for channel 9 is present + */ +#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) +#define DMA_HRS_HRS10_MASK (0x400U) +#define DMA_HRS_HRS10_SHIFT (10U) +/*! HRS10 - Hardware Request Status Channel 10 + * 0b0..A hardware service request for channel 10 is not present + * 0b1..A hardware service request for channel 10 is present + */ +#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) +#define DMA_HRS_HRS11_MASK (0x800U) +#define DMA_HRS_HRS11_SHIFT (11U) +/*! HRS11 - Hardware Request Status Channel 11 + * 0b0..A hardware service request for channel 11 is not present + * 0b1..A hardware service request for channel 11 is present + */ +#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) +#define DMA_HRS_HRS12_MASK (0x1000U) +#define DMA_HRS_HRS12_SHIFT (12U) +/*! HRS12 - Hardware Request Status Channel 12 + * 0b0..A hardware service request for channel 12 is not present + * 0b1..A hardware service request for channel 12 is present + */ +#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) +#define DMA_HRS_HRS13_MASK (0x2000U) +#define DMA_HRS_HRS13_SHIFT (13U) +/*! HRS13 - Hardware Request Status Channel 13 + * 0b0..A hardware service request for channel 13 is not present + * 0b1..A hardware service request for channel 13 is present + */ +#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) +#define DMA_HRS_HRS14_MASK (0x4000U) +#define DMA_HRS_HRS14_SHIFT (14U) +/*! HRS14 - Hardware Request Status Channel 14 + * 0b0..A hardware service request for channel 14 is not present + * 0b1..A hardware service request for channel 14 is present + */ +#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) +#define DMA_HRS_HRS15_MASK (0x8000U) +#define DMA_HRS_HRS15_SHIFT (15U) +/*! HRS15 - Hardware Request Status Channel 15 + * 0b0..A hardware service request for channel 15 is not present + * 0b1..A hardware service request for channel 15 is present + */ +#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) +#define DMA_HRS_HRS16_MASK (0x10000U) +#define DMA_HRS_HRS16_SHIFT (16U) +/*! HRS16 - Hardware Request Status Channel 16 + * 0b0..A hardware service request for channel 16 is not present + * 0b1..A hardware service request for channel 16 is present + */ +#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK) +#define DMA_HRS_HRS17_MASK (0x20000U) +#define DMA_HRS_HRS17_SHIFT (17U) +/*! HRS17 - Hardware Request Status Channel 17 + * 0b0..A hardware service request for channel 17 is not present + * 0b1..A hardware service request for channel 17 is present + */ +#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK) +#define DMA_HRS_HRS18_MASK (0x40000U) +#define DMA_HRS_HRS18_SHIFT (18U) +/*! HRS18 - Hardware Request Status Channel 18 + * 0b0..A hardware service request for channel 18 is not present + * 0b1..A hardware service request for channel 18 is present + */ +#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK) +#define DMA_HRS_HRS19_MASK (0x80000U) +#define DMA_HRS_HRS19_SHIFT (19U) +/*! HRS19 - Hardware Request Status Channel 19 + * 0b0..A hardware service request for channel 19 is not present + * 0b1..A hardware service request for channel 19 is present + */ +#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK) +#define DMA_HRS_HRS20_MASK (0x100000U) +#define DMA_HRS_HRS20_SHIFT (20U) +/*! HRS20 - Hardware Request Status Channel 20 + * 0b0..A hardware service request for channel 20 is not present + * 0b1..A hardware service request for channel 20 is present + */ +#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK) +#define DMA_HRS_HRS21_MASK (0x200000U) +#define DMA_HRS_HRS21_SHIFT (21U) +/*! HRS21 - Hardware Request Status Channel 21 + * 0b0..A hardware service request for channel 21 is not present + * 0b1..A hardware service request for channel 21 is present + */ +#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK) +#define DMA_HRS_HRS22_MASK (0x400000U) +#define DMA_HRS_HRS22_SHIFT (22U) +/*! HRS22 - Hardware Request Status Channel 22 + * 0b0..A hardware service request for channel 22 is not present + * 0b1..A hardware service request for channel 22 is present + */ +#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK) +#define DMA_HRS_HRS23_MASK (0x800000U) +#define DMA_HRS_HRS23_SHIFT (23U) +/*! HRS23 - Hardware Request Status Channel 23 + * 0b0..A hardware service request for channel 23 is not present + * 0b1..A hardware service request for channel 23 is present + */ +#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK) +#define DMA_HRS_HRS24_MASK (0x1000000U) +#define DMA_HRS_HRS24_SHIFT (24U) +/*! HRS24 - Hardware Request Status Channel 24 + * 0b0..A hardware service request for channel 24 is not present + * 0b1..A hardware service request for channel 24 is present + */ +#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK) +#define DMA_HRS_HRS25_MASK (0x2000000U) +#define DMA_HRS_HRS25_SHIFT (25U) +/*! HRS25 - Hardware Request Status Channel 25 + * 0b0..A hardware service request for channel 25 is not present + * 0b1..A hardware service request for channel 25 is present + */ +#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK) +#define DMA_HRS_HRS26_MASK (0x4000000U) +#define DMA_HRS_HRS26_SHIFT (26U) +/*! HRS26 - Hardware Request Status Channel 26 + * 0b0..A hardware service request for channel 26 is not present + * 0b1..A hardware service request for channel 26 is present + */ +#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK) +#define DMA_HRS_HRS27_MASK (0x8000000U) +#define DMA_HRS_HRS27_SHIFT (27U) +/*! HRS27 - Hardware Request Status Channel 27 + * 0b0..A hardware service request for channel 27 is not present + * 0b1..A hardware service request for channel 27 is present + */ +#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK) +#define DMA_HRS_HRS28_MASK (0x10000000U) +#define DMA_HRS_HRS28_SHIFT (28U) +/*! HRS28 - Hardware Request Status Channel 28 + * 0b0..A hardware service request for channel 28 is not present + * 0b1..A hardware service request for channel 28 is present + */ +#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK) +#define DMA_HRS_HRS29_MASK (0x20000000U) +#define DMA_HRS_HRS29_SHIFT (29U) +/*! HRS29 - Hardware Request Status Channel 29 + * 0b0..A hardware service request for channel 29 is not preset + * 0b1..A hardware service request for channel 29 is present + */ +#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK) +#define DMA_HRS_HRS30_MASK (0x40000000U) +#define DMA_HRS_HRS30_SHIFT (30U) +/*! HRS30 - Hardware Request Status Channel 30 + * 0b0..A hardware service request for channel 30 is not present + * 0b1..A hardware service request for channel 30 is present + */ +#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK) +#define DMA_HRS_HRS31_MASK (0x80000000U) +#define DMA_HRS_HRS31_SHIFT (31U) +/*! HRS31 - Hardware Request Status Channel 31 + * 0b0..A hardware service request for channel 31 is not present + * 0b1..A hardware service request for channel 31 is present + */ +#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK) +/*! @} */ + +/*! @name EARS - Enable Asynchronous Request in Stop Register */ +/*! @{ */ +#define DMA_EARS_EDREQ_0_MASK (0x1U) +#define DMA_EARS_EDREQ_0_SHIFT (0U) +/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. + * 0b0..Disable asynchronous DMA request for channel 0. + * 0b1..Enable asynchronous DMA request for channel 0. + */ +#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) +#define DMA_EARS_EDREQ_1_MASK (0x2U) +#define DMA_EARS_EDREQ_1_SHIFT (1U) +/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. + * 0b0..Disable asynchronous DMA request for channel 1 + * 0b1..Enable asynchronous DMA request for channel 1. + */ +#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) +#define DMA_EARS_EDREQ_2_MASK (0x4U) +#define DMA_EARS_EDREQ_2_SHIFT (2U) +/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. + * 0b0..Disable asynchronous DMA request for channel 2. + * 0b1..Enable asynchronous DMA request for channel 2. + */ +#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) +#define DMA_EARS_EDREQ_3_MASK (0x8U) +#define DMA_EARS_EDREQ_3_SHIFT (3U) +/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. + * 0b0..Disable asynchronous DMA request for channel 3. + * 0b1..Enable asynchronous DMA request for channel 3. + */ +#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) +#define DMA_EARS_EDREQ_4_MASK (0x10U) +#define DMA_EARS_EDREQ_4_SHIFT (4U) +/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4 + * 0b0..Disable asynchronous DMA request for channel 4. + * 0b1..Enable asynchronous DMA request for channel 4. + */ +#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) +#define DMA_EARS_EDREQ_5_MASK (0x20U) +#define DMA_EARS_EDREQ_5_SHIFT (5U) +/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5 + * 0b0..Disable asynchronous DMA request for channel 5. + * 0b1..Enable asynchronous DMA request for channel 5. + */ +#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) +#define DMA_EARS_EDREQ_6_MASK (0x40U) +#define DMA_EARS_EDREQ_6_SHIFT (6U) +/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6 + * 0b0..Disable asynchronous DMA request for channel 6. + * 0b1..Enable asynchronous DMA request for channel 6. + */ +#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) +#define DMA_EARS_EDREQ_7_MASK (0x80U) +#define DMA_EARS_EDREQ_7_SHIFT (7U) +/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7 + * 0b0..Disable asynchronous DMA request for channel 7. + * 0b1..Enable asynchronous DMA request for channel 7. + */ +#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) +#define DMA_EARS_EDREQ_8_MASK (0x100U) +#define DMA_EARS_EDREQ_8_SHIFT (8U) +/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8 + * 0b0..Disable asynchronous DMA request for channel 8. + * 0b1..Enable asynchronous DMA request for channel 8. + */ +#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK) +#define DMA_EARS_EDREQ_9_MASK (0x200U) +#define DMA_EARS_EDREQ_9_SHIFT (9U) +/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9 + * 0b0..Disable asynchronous DMA request for channel 9. + * 0b1..Enable asynchronous DMA request for channel 9. + */ +#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK) +#define DMA_EARS_EDREQ_10_MASK (0x400U) +#define DMA_EARS_EDREQ_10_SHIFT (10U) +/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10 + * 0b0..Disable asynchronous DMA request for channel 10. + * 0b1..Enable asynchronous DMA request for channel 10. + */ +#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK) +#define DMA_EARS_EDREQ_11_MASK (0x800U) +#define DMA_EARS_EDREQ_11_SHIFT (11U) +/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11 + * 0b0..Disable asynchronous DMA request for channel 11. + * 0b1..Enable asynchronous DMA request for channel 11. + */ +#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK) +#define DMA_EARS_EDREQ_12_MASK (0x1000U) +#define DMA_EARS_EDREQ_12_SHIFT (12U) +/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12 + * 0b0..Disable asynchronous DMA request for channel 12. + * 0b1..Enable asynchronous DMA request for channel 12. + */ +#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK) +#define DMA_EARS_EDREQ_13_MASK (0x2000U) +#define DMA_EARS_EDREQ_13_SHIFT (13U) +/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13 + * 0b0..Disable asynchronous DMA request for channel 13. + * 0b1..Enable asynchronous DMA request for channel 13. + */ +#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK) +#define DMA_EARS_EDREQ_14_MASK (0x4000U) +#define DMA_EARS_EDREQ_14_SHIFT (14U) +/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14 + * 0b0..Disable asynchronous DMA request for channel 14. + * 0b1..Enable asynchronous DMA request for channel 14. + */ +#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK) +#define DMA_EARS_EDREQ_15_MASK (0x8000U) +#define DMA_EARS_EDREQ_15_SHIFT (15U) +/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15 + * 0b0..Disable asynchronous DMA request for channel 15. + * 0b1..Enable asynchronous DMA request for channel 15. + */ +#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK) +#define DMA_EARS_EDREQ_16_MASK (0x10000U) +#define DMA_EARS_EDREQ_16_SHIFT (16U) +/*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16 + * 0b0..Disable asynchronous DMA request for channel 16 + * 0b1..Enable asynchronous DMA request for channel 16 + */ +#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK) +#define DMA_EARS_EDREQ_17_MASK (0x20000U) +#define DMA_EARS_EDREQ_17_SHIFT (17U) +/*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17 + * 0b0..Disable asynchronous DMA request for channel 17 + * 0b1..Enable asynchronous DMA request for channel 17 + */ +#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK) +#define DMA_EARS_EDREQ_18_MASK (0x40000U) +#define DMA_EARS_EDREQ_18_SHIFT (18U) +/*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18 + * 0b0..Disable asynchronous DMA request for channel 18 + * 0b1..Enable asynchronous DMA request for channel 18 + */ +#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK) +#define DMA_EARS_EDREQ_19_MASK (0x80000U) +#define DMA_EARS_EDREQ_19_SHIFT (19U) +/*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19 + * 0b0..Disable asynchronous DMA request for channel 19 + * 0b1..Enable asynchronous DMA request for channel 19 + */ +#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK) +#define DMA_EARS_EDREQ_20_MASK (0x100000U) +#define DMA_EARS_EDREQ_20_SHIFT (20U) +/*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20 + * 0b0..Disable asynchronous DMA request for channel 20 + * 0b1..Enable asynchronous DMA request for channel 20 + */ +#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK) +#define DMA_EARS_EDREQ_21_MASK (0x200000U) +#define DMA_EARS_EDREQ_21_SHIFT (21U) +/*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21 + * 0b0..Disable asynchronous DMA request for channel 21 + * 0b1..Enable asynchronous DMA request for channel 21 + */ +#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK) +#define DMA_EARS_EDREQ_22_MASK (0x400000U) +#define DMA_EARS_EDREQ_22_SHIFT (22U) +/*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22 + * 0b0..Disable asynchronous DMA request for channel 22 + * 0b1..Enable asynchronous DMA request for channel 22 + */ +#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK) +#define DMA_EARS_EDREQ_23_MASK (0x800000U) +#define DMA_EARS_EDREQ_23_SHIFT (23U) +/*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23 + * 0b0..Disable asynchronous DMA request for channel 23 + * 0b1..Enable asynchronous DMA request for channel 23 + */ +#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK) +#define DMA_EARS_EDREQ_24_MASK (0x1000000U) +#define DMA_EARS_EDREQ_24_SHIFT (24U) +/*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24 + * 0b0..Disable asynchronous DMA request for channel 24 + * 0b1..Enable asynchronous DMA request for channel 24 + */ +#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK) +#define DMA_EARS_EDREQ_25_MASK (0x2000000U) +#define DMA_EARS_EDREQ_25_SHIFT (25U) +/*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25 + * 0b0..Disable asynchronous DMA request for channel 25 + * 0b1..Enable asynchronous DMA request for channel 25 + */ +#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK) +#define DMA_EARS_EDREQ_26_MASK (0x4000000U) +#define DMA_EARS_EDREQ_26_SHIFT (26U) +/*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26 + * 0b0..Disable asynchronous DMA request for channel 26 + * 0b1..Enable asynchronous DMA request for channel 26 + */ +#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK) +#define DMA_EARS_EDREQ_27_MASK (0x8000000U) +#define DMA_EARS_EDREQ_27_SHIFT (27U) +/*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27 + * 0b0..Disable asynchronous DMA request for channel 27 + * 0b1..Enable asynchronous DMA request for channel 27 + */ +#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK) +#define DMA_EARS_EDREQ_28_MASK (0x10000000U) +#define DMA_EARS_EDREQ_28_SHIFT (28U) +/*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28 + * 0b0..Disable asynchronous DMA request for channel 28 + * 0b1..Enable asynchronous DMA request for channel 28 + */ +#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK) +#define DMA_EARS_EDREQ_29_MASK (0x20000000U) +#define DMA_EARS_EDREQ_29_SHIFT (29U) +/*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29 + * 0b0..Disable asynchronous DMA request for channel 29 + * 0b1..Enable asynchronous DMA request for channel 29 + */ +#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK) +#define DMA_EARS_EDREQ_30_MASK (0x40000000U) +#define DMA_EARS_EDREQ_30_SHIFT (30U) +/*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30 + * 0b0..Disable asynchronous DMA request for channel 30 + * 0b1..Enable asynchronous DMA request for channel 30 + */ +#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK) +#define DMA_EARS_EDREQ_31_MASK (0x80000000U) +#define DMA_EARS_EDREQ_31_SHIFT (31U) +/*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31 + * 0b0..Disable asynchronous DMA request for channel 31 + * 0b1..Enable asynchronous DMA request for channel 31 + */ +#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK) +/*! @} */ + +/*! @name DCHPRI3 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI3_CHPRI_MASK (0xFU) +#define DMA_DCHPRI3_CHPRI_SHIFT (0U) +#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) +#define DMA_DCHPRI3_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI3_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK) +#define DMA_DCHPRI3_DPA_MASK (0x40U) +#define DMA_DCHPRI3_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) +#define DMA_DCHPRI3_ECP_MASK (0x80U) +#define DMA_DCHPRI3_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI2 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI2_CHPRI_MASK (0xFU) +#define DMA_DCHPRI2_CHPRI_SHIFT (0U) +#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) +#define DMA_DCHPRI2_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI2_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK) +#define DMA_DCHPRI2_DPA_MASK (0x40U) +#define DMA_DCHPRI2_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) +#define DMA_DCHPRI2_ECP_MASK (0x80U) +#define DMA_DCHPRI2_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI1 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI1_CHPRI_MASK (0xFU) +#define DMA_DCHPRI1_CHPRI_SHIFT (0U) +#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) +#define DMA_DCHPRI1_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI1_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK) +#define DMA_DCHPRI1_DPA_MASK (0x40U) +#define DMA_DCHPRI1_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) +#define DMA_DCHPRI1_ECP_MASK (0x80U) +#define DMA_DCHPRI1_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI0 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI0_CHPRI_MASK (0xFU) +#define DMA_DCHPRI0_CHPRI_SHIFT (0U) +#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) +#define DMA_DCHPRI0_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI0_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK) +#define DMA_DCHPRI0_DPA_MASK (0x40U) +#define DMA_DCHPRI0_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) +#define DMA_DCHPRI0_ECP_MASK (0x80U) +#define DMA_DCHPRI0_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI7 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI7_CHPRI_MASK (0xFU) +#define DMA_DCHPRI7_CHPRI_SHIFT (0U) +#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) +#define DMA_DCHPRI7_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI7_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK) +#define DMA_DCHPRI7_DPA_MASK (0x40U) +#define DMA_DCHPRI7_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) +#define DMA_DCHPRI7_ECP_MASK (0x80U) +#define DMA_DCHPRI7_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI6 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI6_CHPRI_MASK (0xFU) +#define DMA_DCHPRI6_CHPRI_SHIFT (0U) +#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) +#define DMA_DCHPRI6_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI6_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK) +#define DMA_DCHPRI6_DPA_MASK (0x40U) +#define DMA_DCHPRI6_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) +#define DMA_DCHPRI6_ECP_MASK (0x80U) +#define DMA_DCHPRI6_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI5 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI5_CHPRI_MASK (0xFU) +#define DMA_DCHPRI5_CHPRI_SHIFT (0U) +#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) +#define DMA_DCHPRI5_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI5_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK) +#define DMA_DCHPRI5_DPA_MASK (0x40U) +#define DMA_DCHPRI5_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) +#define DMA_DCHPRI5_ECP_MASK (0x80U) +#define DMA_DCHPRI5_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI4 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI4_CHPRI_MASK (0xFU) +#define DMA_DCHPRI4_CHPRI_SHIFT (0U) +#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) +#define DMA_DCHPRI4_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI4_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK) +#define DMA_DCHPRI4_DPA_MASK (0x40U) +#define DMA_DCHPRI4_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) +#define DMA_DCHPRI4_ECP_MASK (0x80U) +#define DMA_DCHPRI4_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI11 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI11_CHPRI_MASK (0xFU) +#define DMA_DCHPRI11_CHPRI_SHIFT (0U) +#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) +#define DMA_DCHPRI11_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI11_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK) +#define DMA_DCHPRI11_DPA_MASK (0x40U) +#define DMA_DCHPRI11_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) +#define DMA_DCHPRI11_ECP_MASK (0x80U) +#define DMA_DCHPRI11_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI10 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI10_CHPRI_MASK (0xFU) +#define DMA_DCHPRI10_CHPRI_SHIFT (0U) +#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) +#define DMA_DCHPRI10_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI10_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK) +#define DMA_DCHPRI10_DPA_MASK (0x40U) +#define DMA_DCHPRI10_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) +#define DMA_DCHPRI10_ECP_MASK (0x80U) +#define DMA_DCHPRI10_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI9 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI9_CHPRI_MASK (0xFU) +#define DMA_DCHPRI9_CHPRI_SHIFT (0U) +#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) +#define DMA_DCHPRI9_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI9_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK) +#define DMA_DCHPRI9_DPA_MASK (0x40U) +#define DMA_DCHPRI9_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) +#define DMA_DCHPRI9_ECP_MASK (0x80U) +#define DMA_DCHPRI9_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI8 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI8_CHPRI_MASK (0xFU) +#define DMA_DCHPRI8_CHPRI_SHIFT (0U) +#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) +#define DMA_DCHPRI8_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI8_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK) +#define DMA_DCHPRI8_DPA_MASK (0x40U) +#define DMA_DCHPRI8_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) +#define DMA_DCHPRI8_ECP_MASK (0x80U) +#define DMA_DCHPRI8_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI15 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI15_CHPRI_MASK (0xFU) +#define DMA_DCHPRI15_CHPRI_SHIFT (0U) +#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) +#define DMA_DCHPRI15_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI15_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK) +#define DMA_DCHPRI15_DPA_MASK (0x40U) +#define DMA_DCHPRI15_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) +#define DMA_DCHPRI15_ECP_MASK (0x80U) +#define DMA_DCHPRI15_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI14 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI14_CHPRI_MASK (0xFU) +#define DMA_DCHPRI14_CHPRI_SHIFT (0U) +#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) +#define DMA_DCHPRI14_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI14_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK) +#define DMA_DCHPRI14_DPA_MASK (0x40U) +#define DMA_DCHPRI14_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) +#define DMA_DCHPRI14_ECP_MASK (0x80U) +#define DMA_DCHPRI14_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI13 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI13_CHPRI_MASK (0xFU) +#define DMA_DCHPRI13_CHPRI_SHIFT (0U) +#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) +#define DMA_DCHPRI13_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI13_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK) +#define DMA_DCHPRI13_DPA_MASK (0x40U) +#define DMA_DCHPRI13_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) +#define DMA_DCHPRI13_ECP_MASK (0x80U) +#define DMA_DCHPRI13_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI12 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI12_CHPRI_MASK (0xFU) +#define DMA_DCHPRI12_CHPRI_SHIFT (0U) +#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) +#define DMA_DCHPRI12_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI12_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK) +#define DMA_DCHPRI12_DPA_MASK (0x40U) +#define DMA_DCHPRI12_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) +#define DMA_DCHPRI12_ECP_MASK (0x80U) +#define DMA_DCHPRI12_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI19 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI19_CHPRI_MASK (0xFU) +#define DMA_DCHPRI19_CHPRI_SHIFT (0U) +#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK) +#define DMA_DCHPRI19_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI19_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK) +#define DMA_DCHPRI19_DPA_MASK (0x40U) +#define DMA_DCHPRI19_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK) +#define DMA_DCHPRI19_ECP_MASK (0x80U) +#define DMA_DCHPRI19_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI18 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI18_CHPRI_MASK (0xFU) +#define DMA_DCHPRI18_CHPRI_SHIFT (0U) +#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK) +#define DMA_DCHPRI18_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI18_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK) +#define DMA_DCHPRI18_DPA_MASK (0x40U) +#define DMA_DCHPRI18_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK) +#define DMA_DCHPRI18_ECP_MASK (0x80U) +#define DMA_DCHPRI18_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI17 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI17_CHPRI_MASK (0xFU) +#define DMA_DCHPRI17_CHPRI_SHIFT (0U) +#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK) +#define DMA_DCHPRI17_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI17_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK) +#define DMA_DCHPRI17_DPA_MASK (0x40U) +#define DMA_DCHPRI17_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK) +#define DMA_DCHPRI17_ECP_MASK (0x80U) +#define DMA_DCHPRI17_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI16 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI16_CHPRI_MASK (0xFU) +#define DMA_DCHPRI16_CHPRI_SHIFT (0U) +#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK) +#define DMA_DCHPRI16_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI16_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK) +#define DMA_DCHPRI16_DPA_MASK (0x40U) +#define DMA_DCHPRI16_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK) +#define DMA_DCHPRI16_ECP_MASK (0x80U) +#define DMA_DCHPRI16_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI23 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI23_CHPRI_MASK (0xFU) +#define DMA_DCHPRI23_CHPRI_SHIFT (0U) +#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK) +#define DMA_DCHPRI23_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI23_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK) +#define DMA_DCHPRI23_DPA_MASK (0x40U) +#define DMA_DCHPRI23_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK) +#define DMA_DCHPRI23_ECP_MASK (0x80U) +#define DMA_DCHPRI23_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI22 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI22_CHPRI_MASK (0xFU) +#define DMA_DCHPRI22_CHPRI_SHIFT (0U) +#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK) +#define DMA_DCHPRI22_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI22_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK) +#define DMA_DCHPRI22_DPA_MASK (0x40U) +#define DMA_DCHPRI22_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK) +#define DMA_DCHPRI22_ECP_MASK (0x80U) +#define DMA_DCHPRI22_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI21 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI21_CHPRI_MASK (0xFU) +#define DMA_DCHPRI21_CHPRI_SHIFT (0U) +#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK) +#define DMA_DCHPRI21_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI21_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK) +#define DMA_DCHPRI21_DPA_MASK (0x40U) +#define DMA_DCHPRI21_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK) +#define DMA_DCHPRI21_ECP_MASK (0x80U) +#define DMA_DCHPRI21_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI20 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI20_CHPRI_MASK (0xFU) +#define DMA_DCHPRI20_CHPRI_SHIFT (0U) +#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK) +#define DMA_DCHPRI20_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI20_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK) +#define DMA_DCHPRI20_DPA_MASK (0x40U) +#define DMA_DCHPRI20_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK) +#define DMA_DCHPRI20_ECP_MASK (0x80U) +#define DMA_DCHPRI20_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI27 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI27_CHPRI_MASK (0xFU) +#define DMA_DCHPRI27_CHPRI_SHIFT (0U) +#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK) +#define DMA_DCHPRI27_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI27_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK) +#define DMA_DCHPRI27_DPA_MASK (0x40U) +#define DMA_DCHPRI27_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK) +#define DMA_DCHPRI27_ECP_MASK (0x80U) +#define DMA_DCHPRI27_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI26 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI26_CHPRI_MASK (0xFU) +#define DMA_DCHPRI26_CHPRI_SHIFT (0U) +#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK) +#define DMA_DCHPRI26_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI26_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK) +#define DMA_DCHPRI26_DPA_MASK (0x40U) +#define DMA_DCHPRI26_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK) +#define DMA_DCHPRI26_ECP_MASK (0x80U) +#define DMA_DCHPRI26_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI25 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI25_CHPRI_MASK (0xFU) +#define DMA_DCHPRI25_CHPRI_SHIFT (0U) +#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK) +#define DMA_DCHPRI25_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI25_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK) +#define DMA_DCHPRI25_DPA_MASK (0x40U) +#define DMA_DCHPRI25_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK) +#define DMA_DCHPRI25_ECP_MASK (0x80U) +#define DMA_DCHPRI25_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI24 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI24_CHPRI_MASK (0xFU) +#define DMA_DCHPRI24_CHPRI_SHIFT (0U) +#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK) +#define DMA_DCHPRI24_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI24_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK) +#define DMA_DCHPRI24_DPA_MASK (0x40U) +#define DMA_DCHPRI24_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK) +#define DMA_DCHPRI24_ECP_MASK (0x80U) +#define DMA_DCHPRI24_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI31 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI31_CHPRI_MASK (0xFU) +#define DMA_DCHPRI31_CHPRI_SHIFT (0U) +#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK) +#define DMA_DCHPRI31_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI31_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK) +#define DMA_DCHPRI31_DPA_MASK (0x40U) +#define DMA_DCHPRI31_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK) +#define DMA_DCHPRI31_ECP_MASK (0x80U) +#define DMA_DCHPRI31_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI30 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI30_CHPRI_MASK (0xFU) +#define DMA_DCHPRI30_CHPRI_SHIFT (0U) +#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK) +#define DMA_DCHPRI30_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI30_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK) +#define DMA_DCHPRI30_DPA_MASK (0x40U) +#define DMA_DCHPRI30_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK) +#define DMA_DCHPRI30_ECP_MASK (0x80U) +#define DMA_DCHPRI30_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI29 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI29_CHPRI_MASK (0xFU) +#define DMA_DCHPRI29_CHPRI_SHIFT (0U) +#define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK) +#define DMA_DCHPRI29_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI29_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK) +#define DMA_DCHPRI29_DPA_MASK (0x40U) +#define DMA_DCHPRI29_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK) +#define DMA_DCHPRI29_ECP_MASK (0x80U) +#define DMA_DCHPRI29_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI28 - Channel n Priority Register */ +/*! @{ */ +#define DMA_DCHPRI28_CHPRI_MASK (0xFU) +#define DMA_DCHPRI28_CHPRI_SHIFT (0U) +#define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK) +#define DMA_DCHPRI28_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI28_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK) +#define DMA_DCHPRI28_DPA_MASK (0x40U) +#define DMA_DCHPRI28_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel. + * 0b1..Channel n cannot suspend any channel, regardless of channel priority. + */ +#define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK) +#define DMA_DCHPRI28_ECP_MASK (0x80U) +#define DMA_DCHPRI28_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request. + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel. + */ +#define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK) +/*! @} */ + +/*! @name SADDR - TCD Source Address */ +/*! @{ */ +#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) +#define DMA_SADDR_SADDR_SHIFT (0U) +#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) +/*! @} */ + +/* The count of DMA_SADDR */ +#define DMA_SADDR_COUNT (32U) + +/*! @name SOFF - TCD Signed Source Address Offset */ +/*! @{ */ +#define DMA_SOFF_SOFF_MASK (0xFFFFU) +#define DMA_SOFF_SOFF_SHIFT (0U) +#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) +/*! @} */ + +/* The count of DMA_SOFF */ +#define DMA_SOFF_COUNT (32U) + +/*! @name ATTR - TCD Transfer Attributes */ +/*! @{ */ +#define DMA_ATTR_DSIZE_MASK (0x7U) +#define DMA_ATTR_DSIZE_SHIFT (0U) +#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) +#define DMA_ATTR_DMOD_MASK (0xF8U) +#define DMA_ATTR_DMOD_SHIFT (3U) +#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) +#define DMA_ATTR_SSIZE_MASK (0x700U) +#define DMA_ATTR_SSIZE_SHIFT (8U) +/*! SSIZE - Source data transfer size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..64-bit + * 0b100..Reserved + * 0b101..32-byte burst (4 beats of 64 bits) + * 0b110..Reserved + * 0b111..Reserved + */ +#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) +#define DMA_ATTR_SMOD_MASK (0xF800U) +#define DMA_ATTR_SMOD_SHIFT (11U) +/*! SMOD - Source Address Modulo + * 0b00000..Source address modulo feature is disabled + * 0b00001-0b11111..This value defines a specific address range specified to be the value after SADDR + SOFF + * calculation is performed on the original register value. Setting this field provides the ability + * to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the + * queue should start at a 0-modulo-size address and the SMOD field should be set to the + * appropriate value for the queue, freezing the desired number of upper address bits. The value + * programmed into this field specifies the number of lower address bits allowed to change. For a + * circular queue application, the SOFF is typically set to the transfer size to implement + * post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + */ +#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) +/*! @} */ + +/* The count of DMA_ATTR */ +#define DMA_ATTR_COUNT (32U) + +/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ +/*! @{ */ +#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) +#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) +/*! @} */ + +/* The count of DMA_NBYTES_MLNO */ +#define DMA_NBYTES_MLNO_COUNT (32U) + +/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ +/*! @{ */ +#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) +#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ +#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) +#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ +#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_NBYTES_MLOFFNO */ +#define DMA_NBYTES_MLOFFNO_COUNT (32U) + +/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ +/*! @{ */ +#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) +#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) +#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) +#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ +#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ +#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_NBYTES_MLOFFYES */ +#define DMA_NBYTES_MLOFFYES_COUNT (32U) + +/*! @name SLAST - TCD Last Source Address Adjustment */ +/*! @{ */ +#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) +#define DMA_SLAST_SLAST_SHIFT (0U) +#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) +/*! @} */ + +/* The count of DMA_SLAST */ +#define DMA_SLAST_COUNT (32U) + +/*! @name DADDR - TCD Destination Address */ +/*! @{ */ +#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) +#define DMA_DADDR_DADDR_SHIFT (0U) +#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) +/*! @} */ + +/* The count of DMA_DADDR */ +#define DMA_DADDR_COUNT (32U) + +/*! @name DOFF - TCD Signed Destination Address Offset */ +/*! @{ */ +#define DMA_DOFF_DOFF_MASK (0xFFFFU) +#define DMA_DOFF_DOFF_SHIFT (0U) +#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) +/*! @} */ + +/* The count of DMA_DOFF */ +#define DMA_DOFF_COUNT (32U) + +/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @{ */ +#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define DMA_CITER_ELINKNO_CITER_SHIFT (0U) +#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) +#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_CITER_ELINKNO */ +#define DMA_CITER_ELINKNO_COUNT (32U) + +/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @{ */ +#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define DMA_CITER_ELINKYES_CITER_SHIFT (0U) +#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) +#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) +#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) +#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_CITER_ELINKYES */ +#define DMA_CITER_ELINKYES_COUNT (32U) + +/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ +/*! @{ */ +#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) +#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) +#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) +/*! @} */ + +/* The count of DMA_DLAST_SGA */ +#define DMA_DLAST_SGA_COUNT (32U) + +/*! @name CSR - TCD Control and Status */ +/*! @{ */ +#define DMA_CSR_START_MASK (0x1U) +#define DMA_CSR_START_SHIFT (0U) +/*! START - Channel Start + * 0b0..The channel is not explicitly started. + * 0b1..The channel is explicitly started via a software initiated service request. + */ +#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) +#define DMA_CSR_INTMAJOR_MASK (0x2U) +#define DMA_CSR_INTMAJOR_SHIFT (1U) +/*! INTMAJOR - Enable an interrupt when major iteration count completes. + * 0b0..The end-of-major loop interrupt is disabled. + * 0b1..The end-of-major loop interrupt is enabled. + */ +#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) +#define DMA_CSR_INTHALF_MASK (0x4U) +#define DMA_CSR_INTHALF_SHIFT (2U) +/*! INTHALF - Enable an interrupt when major counter is half complete. + * 0b0..The half-point interrupt is disabled. + * 0b1..The half-point interrupt is enabled. + */ +#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) +#define DMA_CSR_DREQ_MASK (0x8U) +#define DMA_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable Request + * 0b0..The channel's ERQ bit is not affected. + * 0b1..The channel's ERQ bit is cleared when the major loop is complete. + */ +#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) +#define DMA_CSR_ESG_MASK (0x10U) +#define DMA_CSR_ESG_SHIFT (4U) +/*! ESG - Enable Scatter/Gather Processing + * 0b0..The current channel's TCD is normal format. + * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer + * to the next TCD to be loaded into this channel after the major loop completes its execution. + */ +#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) +#define DMA_CSR_MAJORELINK_MASK (0x20U) +#define DMA_CSR_MAJORELINK_SHIFT (5U) +/*! MAJORELINK - Enable channel-to-channel linking on major loop complete + * 0b0..The channel-to-channel linking is disabled. + * 0b1..The channel-to-channel linking is enabled. + */ +#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) +#define DMA_CSR_ACTIVE_MASK (0x40U) +#define DMA_CSR_ACTIVE_SHIFT (6U) +#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) +#define DMA_CSR_DONE_MASK (0x80U) +#define DMA_CSR_DONE_SHIFT (7U) +#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) +#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U) +#define DMA_CSR_MAJORLINKCH_SHIFT (8U) +#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) +#define DMA_CSR_BWC_MASK (0xC000U) +#define DMA_CSR_BWC_SHIFT (14U) +/*! BWC - Bandwidth Control + * 0b00..No eDMA engine stalls. + * 0b01..Reserved + * 0b10..eDMA engine stalls for 4 cycles after each R/W. + * 0b11..eDMA engine stalls for 8 cycles after each R/W. + */ +#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) +/*! @} */ + +/* The count of DMA_CSR */ +#define DMA_CSR_COUNT (32U) + +/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @{ */ +#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define DMA_BITER_ELINKNO_BITER_SHIFT (0U) +#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) +#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_BITER_ELINKNO */ +#define DMA_BITER_ELINKNO_COUNT (32U) + +/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @{ */ +#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) +#define DMA_BITER_ELINKYES_BITER_SHIFT (0U) +#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) +#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) +#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) +#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..The channel-to-channel linking is disabled + * 0b1..The channel-to-channel linking is enabled + */ +#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_BITER_ELINKYES */ +#define DMA_BITER_ELINKYES_COUNT (32U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x400E8000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } } +#define DMA_ERROR_IRQS { DMA_ERROR_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMAMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer + * @{ + */ + +/** DMAMUX - Register Layout Typedef */ +typedef struct { + __IO uint32_t CHCFG[32]; /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */ +} DMAMUX_Type; + +/* ---------------------------------------------------------------------------- + -- DMAMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks + * @{ + */ + +/*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */ +/*! @{ */ +#define DMAMUX_CHCFG_SOURCE_MASK (0x7FU) +#define DMAMUX_CHCFG_SOURCE_SHIFT (0U) +#define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) +#define DMAMUX_CHCFG_A_ON_MASK (0x20000000U) +#define DMAMUX_CHCFG_A_ON_SHIFT (29U) +/*! A_ON - DMA Channel Always Enable + * 0b0..DMA Channel Always ON function is disabled + * 0b1..DMA Channel Always ON function is enabled + */ +#define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK) +#define DMAMUX_CHCFG_TRIG_MASK (0x40000000U) +#define DMAMUX_CHCFG_TRIG_SHIFT (30U) +/*! TRIG - DMA Channel Trigger Enable + * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the + * specified source to the DMA channel. (Normal mode) + * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. + */ +#define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) +#define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) +#define DMAMUX_CHCFG_ENBL_SHIFT (31U) +/*! ENBL - DMA Mux Channel Enable + * 0b0..DMA Mux channel is disabled + * 0b1..DMA Mux channel is enabled + */ +#define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) +/*! @} */ + +/* The count of DMAMUX_CHCFG */ +#define DMAMUX_CHCFG_COUNT (32U) + + +/*! + * @} + */ /* end of group DMAMUX_Register_Masks */ + + +/* DMAMUX - Peripheral instance base addresses */ +/** Peripheral DMAMUX base address */ +#define DMAMUX_BASE (0x400EC000u) +/** Peripheral DMAMUX base pointer */ +#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) +/** Array initializer of DMAMUX peripheral base addresses */ +#define DMAMUX_BASE_ADDRS { DMAMUX_BASE } +/** Array initializer of DMAMUX peripheral base pointers */ +#define DMAMUX_BASE_PTRS { DMAMUX } + +/*! + * @} + */ /* end of group DMAMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENC_Peripheral_Access_Layer ENC Peripheral Access Layer + * @{ + */ + +/** ENC - Register Layout Typedef */ +typedef struct { + __IO uint16_t CTRL; /**< Control Register, offset: 0x0 */ + __IO uint16_t FILT; /**< Input Filter Register, offset: 0x2 */ + __IO uint16_t WTR; /**< Watchdog Timeout Register, offset: 0x4 */ + __IO uint16_t POSD; /**< Position Difference Counter Register, offset: 0x6 */ + __I uint16_t POSDH; /**< Position Difference Hold Register, offset: 0x8 */ + __IO uint16_t REV; /**< Revolution Counter Register, offset: 0xA */ + __I uint16_t REVH; /**< Revolution Hold Register, offset: 0xC */ + __IO uint16_t UPOS; /**< Upper Position Counter Register, offset: 0xE */ + __IO uint16_t LPOS; /**< Lower Position Counter Register, offset: 0x10 */ + __I uint16_t UPOSH; /**< Upper Position Hold Register, offset: 0x12 */ + __I uint16_t LPOSH; /**< Lower Position Hold Register, offset: 0x14 */ + __IO uint16_t UINIT; /**< Upper Initialization Register, offset: 0x16 */ + __IO uint16_t LINIT; /**< Lower Initialization Register, offset: 0x18 */ + __I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */ + __IO uint16_t TST; /**< Test Register, offset: 0x1C */ + __IO uint16_t CTRL2; /**< Control 2 Register, offset: 0x1E */ + __IO uint16_t UMOD; /**< Upper Modulus Register, offset: 0x20 */ + __IO uint16_t LMOD; /**< Lower Modulus Register, offset: 0x22 */ + __IO uint16_t UCOMP; /**< Upper Position Compare Register, offset: 0x24 */ + __IO uint16_t LCOMP; /**< Lower Position Compare Register, offset: 0x26 */ +} ENC_Type; + +/* ---------------------------------------------------------------------------- + -- ENC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENC_Register_Masks ENC Register Masks + * @{ + */ + +/*! @name CTRL - Control Register */ +/*! @{ */ +#define ENC_CTRL_CMPIE_MASK (0x1U) +#define ENC_CTRL_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enable + * 0b0..Compare interrupt is disabled + * 0b1..Compare interrupt is enabled + */ +#define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK) +#define ENC_CTRL_CMPIRQ_MASK (0x2U) +#define ENC_CTRL_CMPIRQ_SHIFT (1U) +/*! CMPIRQ - Compare Interrupt Request + * 0b0..No match has occurred + * 0b1..COMP match has occurred + */ +#define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK) +#define ENC_CTRL_WDE_MASK (0x4U) +#define ENC_CTRL_WDE_SHIFT (2U) +/*! WDE - Watchdog Enable + * 0b0..Watchdog timer is disabled + * 0b1..Watchdog timer is enabled + */ +#define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK) +#define ENC_CTRL_DIE_MASK (0x8U) +#define ENC_CTRL_DIE_SHIFT (3U) +/*! DIE - Watchdog Timeout Interrupt Enable + * 0b0..Watchdog timer interrupt is disabled + * 0b1..Watchdog timer interrupt is enabled + */ +#define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK) +#define ENC_CTRL_DIRQ_MASK (0x10U) +#define ENC_CTRL_DIRQ_SHIFT (4U) +/*! DIRQ - Watchdog Timeout Interrupt Request + * 0b0..No interrupt has occurred + * 0b1..Watchdog timeout interrupt has occurred + */ +#define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK) +#define ENC_CTRL_XNE_MASK (0x20U) +#define ENC_CTRL_XNE_SHIFT (5U) +/*! XNE - Use Negative Edge of INDEX Pulse + * 0b0..Use positive transition edge of INDEX pulse + * 0b1..Use negative transition edge of INDEX pulse + */ +#define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK) +#define ENC_CTRL_XIP_MASK (0x40U) +#define ENC_CTRL_XIP_SHIFT (6U) +/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..INDEX pulse initializes the position counter + */ +#define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK) +#define ENC_CTRL_XIE_MASK (0x80U) +#define ENC_CTRL_XIE_SHIFT (7U) +/*! XIE - INDEX Pulse Interrupt Enable + * 0b0..INDEX pulse interrupt is disabled + * 0b1..INDEX pulse interrupt is enabled + */ +#define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK) +#define ENC_CTRL_XIRQ_MASK (0x100U) +#define ENC_CTRL_XIRQ_SHIFT (8U) +/*! XIRQ - INDEX Pulse Interrupt Request + * 0b0..No interrupt has occurred + * 0b1..INDEX pulse interrupt has occurred + */ +#define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK) +#define ENC_CTRL_PH1_MASK (0x200U) +#define ENC_CTRL_PH1_SHIFT (9U) +/*! PH1 - Enable Signal Phase Count Mode + * 0b0..Use standard quadrature decoder where PHASEA and PHASEB represent a two phase quadrature signal. + * 0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The + * PHASEB input and the REV bit control the counter direction. If CTRL[REV] = 0, PHASEB = 0, then count up If + * CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down If CTRL[REV] = 1, + * PHASEB = 1, then count up + */ +#define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK) +#define ENC_CTRL_REV_MASK (0x400U) +#define ENC_CTRL_REV_SHIFT (10U) +/*! REV - Enable Reverse Direction Counting + * 0b0..Count normally + * 0b1..Count in the reverse direction + */ +#define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK) +#define ENC_CTRL_SWIP_MASK (0x800U) +#define ENC_CTRL_SWIP_SHIFT (11U) +/*! SWIP - Software Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..Initialize position counter + */ +#define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK) +#define ENC_CTRL_HNE_MASK (0x1000U) +#define ENC_CTRL_HNE_SHIFT (12U) +/*! HNE - Use Negative Edge of HOME Input + * 0b0..Use positive going edge-to-trigger initialization of position counters UPOS and LPOS + * 0b1..Use negative going edge-to-trigger initialization of position counters UPOS and LPOS + */ +#define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK) +#define ENC_CTRL_HIP_MASK (0x2000U) +#define ENC_CTRL_HIP_SHIFT (13U) +/*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..HOME signal initializes the position counter + */ +#define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK) +#define ENC_CTRL_HIE_MASK (0x4000U) +#define ENC_CTRL_HIE_SHIFT (14U) +/*! HIE - HOME Interrupt Enable + * 0b0..Disable HOME interrupts + * 0b1..Enable HOME interrupts + */ +#define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK) +#define ENC_CTRL_HIRQ_MASK (0x8000U) +#define ENC_CTRL_HIRQ_SHIFT (15U) +/*! HIRQ - HOME Signal Transition Interrupt Request + * 0b0..No interrupt + * 0b1..HOME signal transition interrupt request + */ +#define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK) +/*! @} */ + +/*! @name FILT - Input Filter Register */ +/*! @{ */ +#define ENC_FILT_FILT_PER_MASK (0xFFU) +#define ENC_FILT_FILT_PER_SHIFT (0U) +#define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK) +#define ENC_FILT_FILT_CNT_MASK (0x700U) +#define ENC_FILT_FILT_CNT_SHIFT (8U) +#define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK) +/*! @} */ + +/*! @name WTR - Watchdog Timeout Register */ +/*! @{ */ +#define ENC_WTR_WDOG_MASK (0xFFFFU) +#define ENC_WTR_WDOG_SHIFT (0U) +#define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK) +/*! @} */ + +/*! @name POSD - Position Difference Counter Register */ +/*! @{ */ +#define ENC_POSD_POSD_MASK (0xFFFFU) +#define ENC_POSD_POSD_SHIFT (0U) +#define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK) +/*! @} */ + +/*! @name POSDH - Position Difference Hold Register */ +/*! @{ */ +#define ENC_POSDH_POSDH_MASK (0xFFFFU) +#define ENC_POSDH_POSDH_SHIFT (0U) +#define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK) +/*! @} */ + +/*! @name REV - Revolution Counter Register */ +/*! @{ */ +#define ENC_REV_REV_MASK (0xFFFFU) +#define ENC_REV_REV_SHIFT (0U) +#define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK) +/*! @} */ + +/*! @name REVH - Revolution Hold Register */ +/*! @{ */ +#define ENC_REVH_REVH_MASK (0xFFFFU) +#define ENC_REVH_REVH_SHIFT (0U) +#define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK) +/*! @} */ + +/*! @name UPOS - Upper Position Counter Register */ +/*! @{ */ +#define ENC_UPOS_POS_MASK (0xFFFFU) +#define ENC_UPOS_POS_SHIFT (0U) +#define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK) +/*! @} */ + +/*! @name LPOS - Lower Position Counter Register */ +/*! @{ */ +#define ENC_LPOS_POS_MASK (0xFFFFU) +#define ENC_LPOS_POS_SHIFT (0U) +#define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK) +/*! @} */ + +/*! @name UPOSH - Upper Position Hold Register */ +/*! @{ */ +#define ENC_UPOSH_POSH_MASK (0xFFFFU) +#define ENC_UPOSH_POSH_SHIFT (0U) +#define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK) +/*! @} */ + +/*! @name LPOSH - Lower Position Hold Register */ +/*! @{ */ +#define ENC_LPOSH_POSH_MASK (0xFFFFU) +#define ENC_LPOSH_POSH_SHIFT (0U) +#define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK) +/*! @} */ + +/*! @name UINIT - Upper Initialization Register */ +/*! @{ */ +#define ENC_UINIT_INIT_MASK (0xFFFFU) +#define ENC_UINIT_INIT_SHIFT (0U) +#define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK) +/*! @} */ + +/*! @name LINIT - Lower Initialization Register */ +/*! @{ */ +#define ENC_LINIT_INIT_MASK (0xFFFFU) +#define ENC_LINIT_INIT_SHIFT (0U) +#define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK) +/*! @} */ + +/*! @name IMR - Input Monitor Register */ +/*! @{ */ +#define ENC_IMR_HOME_MASK (0x1U) +#define ENC_IMR_HOME_SHIFT (0U) +#define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK) +#define ENC_IMR_INDEX_MASK (0x2U) +#define ENC_IMR_INDEX_SHIFT (1U) +#define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK) +#define ENC_IMR_PHB_MASK (0x4U) +#define ENC_IMR_PHB_SHIFT (2U) +#define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK) +#define ENC_IMR_PHA_MASK (0x8U) +#define ENC_IMR_PHA_SHIFT (3U) +#define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK) +#define ENC_IMR_FHOM_MASK (0x10U) +#define ENC_IMR_FHOM_SHIFT (4U) +#define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK) +#define ENC_IMR_FIND_MASK (0x20U) +#define ENC_IMR_FIND_SHIFT (5U) +#define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK) +#define ENC_IMR_FPHB_MASK (0x40U) +#define ENC_IMR_FPHB_SHIFT (6U) +#define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK) +#define ENC_IMR_FPHA_MASK (0x80U) +#define ENC_IMR_FPHA_SHIFT (7U) +#define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK) +/*! @} */ + +/*! @name TST - Test Register */ +/*! @{ */ +#define ENC_TST_TEST_COUNT_MASK (0xFFU) +#define ENC_TST_TEST_COUNT_SHIFT (0U) +#define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK) +#define ENC_TST_TEST_PERIOD_MASK (0x1F00U) +#define ENC_TST_TEST_PERIOD_SHIFT (8U) +#define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK) +#define ENC_TST_QDN_MASK (0x2000U) +#define ENC_TST_QDN_SHIFT (13U) +/*! QDN - Quadrature Decoder Negative Signal + * 0b0..Leaves quadrature decoder signal in a positive direction + * 0b1..Generates a negative quadrature decoder signal + */ +#define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK) +#define ENC_TST_TCE_MASK (0x4000U) +#define ENC_TST_TCE_SHIFT (14U) +/*! TCE - Test Counter Enable + * 0b0..Test count is not enabled + * 0b1..Test count is enabled + */ +#define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK) +#define ENC_TST_TEN_MASK (0x8000U) +#define ENC_TST_TEN_SHIFT (15U) +/*! TEN - Test Mode Enable + * 0b0..Test module is not enabled + * 0b1..Test module is enabled + */ +#define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ +#define ENC_CTRL2_UPDHLD_MASK (0x1U) +#define ENC_CTRL2_UPDHLD_SHIFT (0U) +/*! UPDHLD - Update Hold Registers + * 0b0..Disable updates of hold registers on rising edge of TRIGGER + * 0b1..Enable updates of hold registers on rising edge of TRIGGER + */ +#define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK) +#define ENC_CTRL2_UPDPOS_MASK (0x2U) +#define ENC_CTRL2_UPDPOS_SHIFT (1U) +/*! UPDPOS - Update Position Registers + * 0b0..No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER + * 0b1..Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER + */ +#define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK) +#define ENC_CTRL2_MOD_MASK (0x4U) +#define ENC_CTRL2_MOD_SHIFT (2U) +/*! MOD - Enable Modulo Counting + * 0b0..Disable modulo counting + * 0b1..Enable modulo counting + */ +#define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK) +#define ENC_CTRL2_DIR_MASK (0x8U) +#define ENC_CTRL2_DIR_SHIFT (3U) +/*! DIR - Count Direction Flag + * 0b0..Last count was in the down direction + * 0b1..Last count was in the up direction + */ +#define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK) +#define ENC_CTRL2_RUIE_MASK (0x10U) +#define ENC_CTRL2_RUIE_SHIFT (4U) +/*! RUIE - Roll-under Interrupt Enable + * 0b0..Roll-under interrupt is disabled + * 0b1..Roll-under interrupt is enabled + */ +#define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK) +#define ENC_CTRL2_RUIRQ_MASK (0x20U) +#define ENC_CTRL2_RUIRQ_SHIFT (5U) +/*! RUIRQ - Roll-under Interrupt Request + * 0b0..No roll-under has occurred + * 0b1..Roll-under has occurred + */ +#define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK) +#define ENC_CTRL2_ROIE_MASK (0x40U) +#define ENC_CTRL2_ROIE_SHIFT (6U) +/*! ROIE - Roll-over Interrupt Enable + * 0b0..Roll-over interrupt is disabled + * 0b1..Roll-over interrupt is enabled + */ +#define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK) +#define ENC_CTRL2_ROIRQ_MASK (0x80U) +#define ENC_CTRL2_ROIRQ_SHIFT (7U) +/*! ROIRQ - Roll-over Interrupt Request + * 0b0..No roll-over has occurred + * 0b1..Roll-over has occurred + */ +#define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK) +#define ENC_CTRL2_REVMOD_MASK (0x100U) +#define ENC_CTRL2_REVMOD_SHIFT (8U) +/*! REVMOD - Revolution Counter Modulus Enable + * 0b0..Use INDEX pulse to increment/decrement revolution counter (REV). + * 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV). + */ +#define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK) +#define ENC_CTRL2_OUTCTL_MASK (0x200U) +#define ENC_CTRL2_OUTCTL_SHIFT (9U) +/*! OUTCTL - Output Control + * 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP). + * 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read. + */ +#define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK) +#define ENC_CTRL2_SABIE_MASK (0x400U) +#define ENC_CTRL2_SABIE_SHIFT (10U) +/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable + * 0b0..Simultaneous PHASEA and PHASEB change interrupt disabled. + * 0b1..Simultaneous PHASEA and PHASEB change interrupt enabled. + */ +#define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK) +#define ENC_CTRL2_SABIRQ_MASK (0x800U) +#define ENC_CTRL2_SABIRQ_SHIFT (11U) +/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request + * 0b0..No simultaneous change of PHASEA and PHASEB has occurred. + * 0b1..A simultaneous change of PHASEA and PHASEB has occurred. + */ +#define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK) +/*! @} */ + +/*! @name UMOD - Upper Modulus Register */ +/*! @{ */ +#define ENC_UMOD_MOD_MASK (0xFFFFU) +#define ENC_UMOD_MOD_SHIFT (0U) +#define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK) +/*! @} */ + +/*! @name LMOD - Lower Modulus Register */ +/*! @{ */ +#define ENC_LMOD_MOD_MASK (0xFFFFU) +#define ENC_LMOD_MOD_SHIFT (0U) +#define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK) +/*! @} */ + +/*! @name UCOMP - Upper Position Compare Register */ +/*! @{ */ +#define ENC_UCOMP_COMP_MASK (0xFFFFU) +#define ENC_UCOMP_COMP_SHIFT (0U) +#define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK) +/*! @} */ + +/*! @name LCOMP - Lower Position Compare Register */ +/*! @{ */ +#define ENC_LCOMP_COMP_MASK (0xFFFFU) +#define ENC_LCOMP_COMP_SHIFT (0U) +#define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ENC_Register_Masks */ + + +/* ENC - Peripheral instance base addresses */ +/** Peripheral ENC1 base address */ +#define ENC1_BASE (0x403C8000u) +/** Peripheral ENC1 base pointer */ +#define ENC1 ((ENC_Type *)ENC1_BASE) +/** Peripheral ENC2 base address */ +#define ENC2_BASE (0x403CC000u) +/** Peripheral ENC2 base pointer */ +#define ENC2 ((ENC_Type *)ENC2_BASE) +/** Peripheral ENC3 base address */ +#define ENC3_BASE (0x403D0000u) +/** Peripheral ENC3 base pointer */ +#define ENC3 ((ENC_Type *)ENC3_BASE) +/** Peripheral ENC4 base address */ +#define ENC4_BASE (0x403D4000u) +/** Peripheral ENC4 base pointer */ +#define ENC4 ((ENC_Type *)ENC4_BASE) +/** Array initializer of ENC peripheral base addresses */ +#define ENC_BASE_ADDRS { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE } +/** Array initializer of ENC peripheral base pointers */ +#define ENC_BASE_PTRS { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 } +/** Interrupt vectors for the ENC peripheral type */ +#define ENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } +#define ENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } +#define ENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } +#define ENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } +#define ENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn } + +/*! + * @} + */ /* end of group ENC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ENET Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer + * @{ + */ + +/** ENET - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4]; + __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */ + __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */ + __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */ + uint8_t RESERVED_2[12]; + __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */ + uint8_t RESERVED_3[24]; + __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */ + __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */ + uint8_t RESERVED_4[28]; + __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */ + uint8_t RESERVED_5[28]; + __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */ + uint8_t RESERVED_6[60]; + __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */ + uint8_t RESERVED_7[28]; + __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */ + __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */ + __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */ + __IO uint32_t TXIC; /**< Transmit Interrupt Coalescing Register, offset: 0xF0 */ + uint8_t RESERVED_8[12]; + __IO uint32_t RXIC; /**< Receive Interrupt Coalescing Register, offset: 0x100 */ + uint8_t RESERVED_9[20]; + __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */ + __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */ + __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */ + __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */ + uint8_t RESERVED_10[28]; + __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */ + uint8_t RESERVED_11[56]; + __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */ + __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */ + __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */ + uint8_t RESERVED_12[4]; + __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */ + __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */ + __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */ + __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */ + __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */ + __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */ + __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */ + __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */ + __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */ + __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */ + uint8_t RESERVED_14[56]; + uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */ + __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ + __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ + __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ + __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */ + __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */ + __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */ + __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */ + __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */ + __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */ + __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */ + __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */ + __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */ + __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */ + __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */ + __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */ + __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */ + __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */ + uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */ + __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */ + __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */ + __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */ + __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */ + __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */ + __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */ + __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */ + __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */ + __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */ + __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */ + __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */ + uint8_t RESERVED_15[12]; + __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */ + __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */ + __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */ + __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */ + __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */ + __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ + __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ + __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ + uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */ + __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ + __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ + __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ + __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */ + __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */ + __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */ + __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */ + __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */ + __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */ + __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */ + __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */ + __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */ + __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ + __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ + __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ + uint8_t RESERVED_16[284]; + __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ + __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ + __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ + __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */ + __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ + __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ + __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ + uint8_t RESERVED_17[488]; + __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ + struct { /* offset: 0x608, array step: 0x8 */ + __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ + __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */ + } CHANNEL[4]; +} ENET_Type; + +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/*! @name EIR - Interrupt Event Register */ +/*! @{ */ +#define ENET_EIR_TS_TIMER_MASK (0x8000U) +#define ENET_EIR_TS_TIMER_SHIFT (15U) +#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) +#define ENET_EIR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIR_TS_AVAIL_SHIFT (16U) +#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) +#define ENET_EIR_WAKEUP_MASK (0x20000U) +#define ENET_EIR_WAKEUP_SHIFT (17U) +#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) +#define ENET_EIR_PLR_MASK (0x40000U) +#define ENET_EIR_PLR_SHIFT (18U) +#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) +#define ENET_EIR_UN_MASK (0x80000U) +#define ENET_EIR_UN_SHIFT (19U) +#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) +#define ENET_EIR_RL_MASK (0x100000U) +#define ENET_EIR_RL_SHIFT (20U) +#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) +#define ENET_EIR_LC_MASK (0x200000U) +#define ENET_EIR_LC_SHIFT (21U) +#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) +#define ENET_EIR_EBERR_MASK (0x400000U) +#define ENET_EIR_EBERR_SHIFT (22U) +#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) +#define ENET_EIR_MII_MASK (0x800000U) +#define ENET_EIR_MII_SHIFT (23U) +#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) +#define ENET_EIR_RXB_MASK (0x1000000U) +#define ENET_EIR_RXB_SHIFT (24U) +#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) +#define ENET_EIR_RXF_MASK (0x2000000U) +#define ENET_EIR_RXF_SHIFT (25U) +#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) +#define ENET_EIR_TXB_MASK (0x4000000U) +#define ENET_EIR_TXB_SHIFT (26U) +#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) +#define ENET_EIR_TXF_MASK (0x8000000U) +#define ENET_EIR_TXF_SHIFT (27U) +#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) +#define ENET_EIR_GRA_MASK (0x10000000U) +#define ENET_EIR_GRA_SHIFT (28U) +#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) +#define ENET_EIR_BABT_MASK (0x20000000U) +#define ENET_EIR_BABT_SHIFT (29U) +#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) +#define ENET_EIR_BABR_MASK (0x40000000U) +#define ENET_EIR_BABR_SHIFT (30U) +#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK) +/*! @} */ + +/*! @name EIMR - Interrupt Mask Register */ +/*! @{ */ +#define ENET_EIMR_TS_TIMER_MASK (0x8000U) +#define ENET_EIMR_TS_TIMER_SHIFT (15U) +#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) +#define ENET_EIMR_TS_AVAIL_MASK (0x10000U) +#define ENET_EIMR_TS_AVAIL_SHIFT (16U) +#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) +#define ENET_EIMR_WAKEUP_MASK (0x20000U) +#define ENET_EIMR_WAKEUP_SHIFT (17U) +#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) +#define ENET_EIMR_PLR_MASK (0x40000U) +#define ENET_EIMR_PLR_SHIFT (18U) +#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) +#define ENET_EIMR_UN_MASK (0x80000U) +#define ENET_EIMR_UN_SHIFT (19U) +#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) +#define ENET_EIMR_RL_MASK (0x100000U) +#define ENET_EIMR_RL_SHIFT (20U) +#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) +#define ENET_EIMR_LC_MASK (0x200000U) +#define ENET_EIMR_LC_SHIFT (21U) +#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) +#define ENET_EIMR_EBERR_MASK (0x400000U) +#define ENET_EIMR_EBERR_SHIFT (22U) +#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) +#define ENET_EIMR_MII_MASK (0x800000U) +#define ENET_EIMR_MII_SHIFT (23U) +#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) +#define ENET_EIMR_RXB_MASK (0x1000000U) +#define ENET_EIMR_RXB_SHIFT (24U) +#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) +#define ENET_EIMR_RXF_MASK (0x2000000U) +#define ENET_EIMR_RXF_SHIFT (25U) +#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) +#define ENET_EIMR_TXB_MASK (0x4000000U) +#define ENET_EIMR_TXB_SHIFT (26U) +/*! TXB - TXB Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) +#define ENET_EIMR_TXF_MASK (0x8000000U) +#define ENET_EIMR_TXF_SHIFT (27U) +/*! TXF - TXF Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) +#define ENET_EIMR_GRA_MASK (0x10000000U) +#define ENET_EIMR_GRA_SHIFT (28U) +/*! GRA - GRA Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) +#define ENET_EIMR_BABT_MASK (0x20000000U) +#define ENET_EIMR_BABT_SHIFT (29U) +/*! BABT - BABT Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) +#define ENET_EIMR_BABR_MASK (0x40000000U) +#define ENET_EIMR_BABR_SHIFT (30U) +/*! BABR - BABR Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ +#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK) +/*! @} */ + +/*! @name RDAR - Receive Descriptor Active Register */ +/*! @{ */ +#define ENET_RDAR_RDAR_MASK (0x1000000U) +#define ENET_RDAR_RDAR_SHIFT (24U) +#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK) +/*! @} */ + +/*! @name TDAR - Transmit Descriptor Active Register */ +/*! @{ */ +#define ENET_TDAR_TDAR_MASK (0x1000000U) +#define ENET_TDAR_TDAR_SHIFT (24U) +#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK) +/*! @} */ + +/*! @name ECR - Ethernet Control Register */ +/*! @{ */ +#define ENET_ECR_RESET_MASK (0x1U) +#define ENET_ECR_RESET_SHIFT (0U) +#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) +#define ENET_ECR_ETHEREN_MASK (0x2U) +#define ENET_ECR_ETHEREN_SHIFT (1U) +/*! ETHEREN - Ethernet Enable + * 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. + * 0b1..MAC is enabled, and reception and transmission are possible. + */ +#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) +#define ENET_ECR_MAGICEN_MASK (0x4U) +#define ENET_ECR_MAGICEN_SHIFT (2U) +/*! MAGICEN - Magic Packet Detection Enable + * 0b0..Magic detection logic disabled. + * 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. + */ +#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) +#define ENET_ECR_SLEEP_MASK (0x8U) +#define ENET_ECR_SLEEP_SHIFT (3U) +/*! SLEEP - Sleep Mode Enable + * 0b0..Normal operating mode. + * 0b1..Sleep mode. + */ +#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) +#define ENET_ECR_EN1588_MASK (0x10U) +#define ENET_ECR_EN1588_SHIFT (4U) +/*! EN1588 - EN1588 Enable + * 0b0..Legacy FEC buffer descriptors and functions enabled. + * 0b1..Enhanced frame time-stamping functions enabled. + */ +#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) +#define ENET_ECR_DBGEN_MASK (0x40U) +#define ENET_ECR_DBGEN_SHIFT (6U) +/*! DBGEN - Debug Enable + * 0b0..MAC continues operation in debug mode. + * 0b1..MAC enters hardware freeze mode when the processor is in debug mode. + */ +#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) +#define ENET_ECR_DBSWP_MASK (0x100U) +#define ENET_ECR_DBSWP_SHIFT (8U) +/*! DBSWP - Descriptor Byte Swapping Enable + * 0b0..The buffer descriptor bytes are not swapped to support big-endian devices. + * 0b1..The buffer descriptor bytes are swapped to support little-endian devices. + */ +#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) +/*! @} */ + +/*! @name MMFR - MII Management Frame Register */ +/*! @{ */ +#define ENET_MMFR_DATA_MASK (0xFFFFU) +#define ENET_MMFR_DATA_SHIFT (0U) +#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) +#define ENET_MMFR_TA_MASK (0x30000U) +#define ENET_MMFR_TA_SHIFT (16U) +#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) +#define ENET_MMFR_RA_MASK (0x7C0000U) +#define ENET_MMFR_RA_SHIFT (18U) +#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) +#define ENET_MMFR_PA_MASK (0xF800000U) +#define ENET_MMFR_PA_SHIFT (23U) +#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) +#define ENET_MMFR_OP_MASK (0x30000000U) +#define ENET_MMFR_OP_SHIFT (28U) +#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) +#define ENET_MMFR_ST_MASK (0xC0000000U) +#define ENET_MMFR_ST_SHIFT (30U) +#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK) +/*! @} */ + +/*! @name MSCR - MII Speed Control Register */ +/*! @{ */ +#define ENET_MSCR_MII_SPEED_MASK (0x7EU) +#define ENET_MSCR_MII_SPEED_SHIFT (1U) +#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) +#define ENET_MSCR_DIS_PRE_MASK (0x80U) +#define ENET_MSCR_DIS_PRE_SHIFT (7U) +/*! DIS_PRE - Disable Preamble + * 0b0..Preamble enabled. + * 0b1..Preamble (32 ones) is not prepended to the MII management frame. + */ +#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) +#define ENET_MSCR_HOLDTIME_MASK (0x700U) +#define ENET_MSCR_HOLDTIME_SHIFT (8U) +/*! HOLDTIME - Hold time On MDIO Output + * 0b000..1 internal module clock cycle + * 0b001..2 internal module clock cycles + * 0b010..3 internal module clock cycles + * 0b111..8 internal module clock cycles + */ +#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK) +/*! @} */ + +/*! @name MIBC - MIB Control Register */ +/*! @{ */ +#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) +#define ENET_MIBC_MIB_CLEAR_SHIFT (29U) +/*! MIB_CLEAR - MIB Clear + * 0b0..See note above. + * 0b1..All statistics counters are reset to 0. + */ +#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) +#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) +#define ENET_MIBC_MIB_IDLE_SHIFT (30U) +/*! MIB_IDLE - MIB Idle + * 0b0..The MIB block is updating MIB counters. + * 0b1..The MIB block is not currently updating any MIB counters. + */ +#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) +#define ENET_MIBC_MIB_DIS_MASK (0x80000000U) +#define ENET_MIBC_MIB_DIS_SHIFT (31U) +/*! MIB_DIS - Disable MIB Logic + * 0b0..MIB logic is enabled. + * 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters. + */ +#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK) +/*! @} */ + +/*! @name RCR - Receive Control Register */ +/*! @{ */ +#define ENET_RCR_LOOP_MASK (0x1U) +#define ENET_RCR_LOOP_SHIFT (0U) +/*! LOOP - Internal Loopback + * 0b0..Loopback disabled. + * 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. + */ +#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) +#define ENET_RCR_DRT_MASK (0x2U) +#define ENET_RCR_DRT_SHIFT (1U) +/*! DRT - Disable Receive On Transmit + * 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. + * 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.) + */ +#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) +#define ENET_RCR_MII_MODE_MASK (0x4U) +#define ENET_RCR_MII_MODE_SHIFT (2U) +/*! MII_MODE - Media Independent Interface Mode + * 0b0..Reserved. + * 0b1..MII or RMII mode, as indicated by the RMII_MODE field. + */ +#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) +#define ENET_RCR_PROM_MASK (0x8U) +#define ENET_RCR_PROM_SHIFT (3U) +/*! PROM - Promiscuous Mode + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) +#define ENET_RCR_BC_REJ_MASK (0x10U) +#define ENET_RCR_BC_REJ_SHIFT (4U) +#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) +#define ENET_RCR_FCE_MASK (0x20U) +#define ENET_RCR_FCE_SHIFT (5U) +#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) +#define ENET_RCR_RMII_MODE_MASK (0x100U) +#define ENET_RCR_RMII_MODE_SHIFT (8U) +/*! RMII_MODE - RMII Mode Enable + * 0b0..MAC configured for MII mode. + * 0b1..MAC configured for RMII operation. + */ +#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) +#define ENET_RCR_RMII_10T_MASK (0x200U) +#define ENET_RCR_RMII_10T_SHIFT (9U) +/*! RMII_10T + * 0b0..100-Mbit/s operation. + * 0b1..10-Mbit/s operation. + */ +#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) +#define ENET_RCR_PADEN_MASK (0x1000U) +#define ENET_RCR_PADEN_SHIFT (12U) +/*! PADEN - Enable Frame Padding Remove On Receive + * 0b0..No padding is removed on receive by the MAC. + * 0b1..Padding is removed from received frames. + */ +#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) +#define ENET_RCR_PAUFWD_MASK (0x2000U) +#define ENET_RCR_PAUFWD_SHIFT (13U) +/*! PAUFWD - Terminate/Forward Pause Frames + * 0b0..Pause frames are terminated and discarded in the MAC. + * 0b1..Pause frames are forwarded to the user application. + */ +#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) +#define ENET_RCR_CRCFWD_MASK (0x4000U) +#define ENET_RCR_CRCFWD_SHIFT (14U) +/*! CRCFWD - Terminate/Forward Received CRC + * 0b0..The CRC field of received frames is transmitted to the user application. + * 0b1..The CRC field is stripped from the frame. + */ +#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) +#define ENET_RCR_CFEN_MASK (0x8000U) +#define ENET_RCR_CFEN_SHIFT (15U) +/*! CFEN - MAC Control Frame Enable + * 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. + * 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. + */ +#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) +#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) +#define ENET_RCR_MAX_FL_SHIFT (16U) +#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) +#define ENET_RCR_NLC_MASK (0x40000000U) +#define ENET_RCR_NLC_SHIFT (30U) +/*! NLC - Payload Length Check Disable + * 0b0..The payload length check is disabled. + * 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field. + */ +#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) +#define ENET_RCR_GRS_MASK (0x80000000U) +#define ENET_RCR_GRS_SHIFT (31U) +#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) +/*! @} */ + +/*! @name TCR - Transmit Control Register */ +/*! @{ */ +#define ENET_TCR_GTS_MASK (0x1U) +#define ENET_TCR_GTS_SHIFT (0U) +#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) +#define ENET_TCR_FDEN_MASK (0x4U) +#define ENET_TCR_FDEN_SHIFT (2U) +#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) +#define ENET_TCR_TFC_PAUSE_MASK (0x8U) +#define ENET_TCR_TFC_PAUSE_SHIFT (3U) +/*! TFC_PAUSE - Transmit Frame Control Pause + * 0b0..No PAUSE frame transmitted. + * 0b1..The MAC stops transmission of data frames after the current transmission is complete. + */ +#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) +#define ENET_TCR_RFC_PAUSE_MASK (0x10U) +#define ENET_TCR_RFC_PAUSE_SHIFT (4U) +#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) +#define ENET_TCR_ADDSEL_MASK (0xE0U) +#define ENET_TCR_ADDSEL_SHIFT (5U) +/*! ADDSEL - Source MAC Address Select On Transmit + * 0b000..Node MAC address programmed on PADDR1/2 registers. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + */ +#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) +#define ENET_TCR_ADDINS_MASK (0x100U) +#define ENET_TCR_ADDINS_SHIFT (8U) +/*! ADDINS - Set MAC Address On Transmit + * 0b0..The source MAC address is not modified by the MAC. + * 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. + */ +#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) +#define ENET_TCR_CRCFWD_MASK (0x200U) +#define ENET_TCR_CRCFWD_SHIFT (9U) +/*! CRCFWD - Forward Frame From Application With CRC + * 0b0..TxBD[TC] controls whether the frame has a CRC from the application. + * 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. + */ +#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK) +/*! @} */ + +/*! @name PALR - Physical Address Lower Register */ +/*! @{ */ +#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) +#define ENET_PALR_PADDR1_SHIFT (0U) +#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK) +/*! @} */ + +/*! @name PAUR - Physical Address Upper Register */ +/*! @{ */ +#define ENET_PAUR_TYPE_MASK (0xFFFFU) +#define ENET_PAUR_TYPE_SHIFT (0U) +#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) +#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) +#define ENET_PAUR_PADDR2_SHIFT (16U) +#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) +/*! @} */ + +/*! @name OPD - Opcode/Pause Duration Register */ +/*! @{ */ +#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) +#define ENET_OPD_PAUSE_DUR_SHIFT (0U) +#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) +#define ENET_OPD_OPCODE_MASK (0xFFFF0000U) +#define ENET_OPD_OPCODE_SHIFT (16U) +#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK) +/*! @} */ + +/*! @name TXIC - Transmit Interrupt Coalescing Register */ +/*! @{ */ +#define ENET_TXIC_ICTT_MASK (0xFFFFU) +#define ENET_TXIC_ICTT_SHIFT (0U) +#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) +#define ENET_TXIC_ICFT_MASK (0xFF00000U) +#define ENET_TXIC_ICFT_SHIFT (20U) +#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK) +#define ENET_TXIC_ICCS_MASK (0x40000000U) +#define ENET_TXIC_ICCS_SHIFT (30U) +/*! ICCS - Interrupt Coalescing Timer Clock Source Select + * 0b0..Use MII/GMII TX clocks. + * 0b1..Use ENET system clock. + */ +#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK) +#define ENET_TXIC_ICEN_MASK (0x80000000U) +#define ENET_TXIC_ICEN_SHIFT (31U) +/*! ICEN - Interrupt Coalescing Enable + * 0b0..Disable Interrupt coalescing. + * 0b1..Enable Interrupt coalescing. + */ +#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK) +/*! @} */ + +/*! @name RXIC - Receive Interrupt Coalescing Register */ +/*! @{ */ +#define ENET_RXIC_ICTT_MASK (0xFFFFU) +#define ENET_RXIC_ICTT_SHIFT (0U) +#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) +#define ENET_RXIC_ICFT_MASK (0xFF00000U) +#define ENET_RXIC_ICFT_SHIFT (20U) +#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK) +#define ENET_RXIC_ICCS_MASK (0x40000000U) +#define ENET_RXIC_ICCS_SHIFT (30U) +/*! ICCS - Interrupt Coalescing Timer Clock Source Select + * 0b0..Use MII/GMII TX clocks. + * 0b1..Use ENET system clock. + */ +#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK) +#define ENET_RXIC_ICEN_MASK (0x80000000U) +#define ENET_RXIC_ICEN_SHIFT (31U) +/*! ICEN - Interrupt Coalescing Enable + * 0b0..Disable Interrupt coalescing. + * 0b1..Enable Interrupt coalescing. + */ +#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK) +/*! @} */ + +/*! @name IAUR - Descriptor Individual Upper Address Register */ +/*! @{ */ +#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) +#define ENET_IAUR_IADDR1_SHIFT (0U) +#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) +/*! @} */ + +/*! @name IALR - Descriptor Individual Lower Address Register */ +/*! @{ */ +#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) +#define ENET_IALR_IADDR2_SHIFT (0U) +#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) +/*! @} */ + +/*! @name GAUR - Descriptor Group Upper Address Register */ +/*! @{ */ +#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) +#define ENET_GAUR_GADDR1_SHIFT (0U) +#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) +/*! @} */ + +/*! @name GALR - Descriptor Group Lower Address Register */ +/*! @{ */ +#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) +#define ENET_GALR_GADDR2_SHIFT (0U) +#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) +/*! @} */ + +/*! @name TFWR - Transmit FIFO Watermark Register */ +/*! @{ */ +#define ENET_TFWR_TFWR_MASK (0x3FU) +#define ENET_TFWR_TFWR_SHIFT (0U) +/*! TFWR - Transmit FIFO Write + * 0b000000..64 bytes written. + * 0b000001..64 bytes written. + * 0b000010..128 bytes written. + * 0b000011..192 bytes written. + * 0b011111..1984 bytes written. + */ +#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) +#define ENET_TFWR_STRFWD_MASK (0x100U) +#define ENET_TFWR_STRFWD_SHIFT (8U) +/*! STRFWD - Store And Forward Enable + * 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR]. + * 0b1..Enabled. + */ +#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK) +/*! @} */ + +/*! @name RDSR - Receive Descriptor Ring Start Register */ +/*! @{ */ +#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) +#define ENET_RDSR_R_DES_START_SHIFT (3U) +#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) +/*! @} */ + +/*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */ +/*! @{ */ +#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) +#define ENET_TDSR_X_DES_START_SHIFT (3U) +#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) +/*! @} */ + +/*! @name MRBR - Maximum Receive Buffer Size Register */ +/*! @{ */ +#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) +#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) +#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) +/*! @} */ + +/*! @name RSFL - Receive FIFO Section Full Threshold */ +/*! @{ */ +#define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU) +#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) +#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) +/*! @} */ + +/*! @name RSEM - Receive FIFO Section Empty Threshold */ +/*! @{ */ +#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU) +#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) +#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) +#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) +#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) +#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK) +/*! @} */ + +/*! @name RAEM - Receive FIFO Almost Empty Threshold */ +/*! @{ */ +#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU) +#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) +#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) +/*! @} */ + +/*! @name RAFL - Receive FIFO Almost Full Threshold */ +/*! @{ */ +#define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU) +#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) +#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) +/*! @} */ + +/*! @name TSEM - Transmit FIFO Section Empty Threshold */ +/*! @{ */ +#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU) +#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) +#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) +/*! @} */ + +/*! @name TAEM - Transmit FIFO Almost Empty Threshold */ +/*! @{ */ +#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU) +#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) +#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) +/*! @} */ + +/*! @name TAFL - Transmit FIFO Almost Full Threshold */ +/*! @{ */ +#define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU) +#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) +#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) +/*! @} */ + +/*! @name TIPG - Transmit Inter-Packet Gap */ +/*! @{ */ +#define ENET_TIPG_IPG_MASK (0x1FU) +#define ENET_TIPG_IPG_SHIFT (0U) +#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK) +/*! @} */ + +/*! @name FTRL - Frame Truncation Length */ +/*! @{ */ +#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) +#define ENET_FTRL_TRUNC_FL_SHIFT (0U) +#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK) +/*! @} */ + +/*! @name TACC - Transmit Accelerator Function Configuration */ +/*! @{ */ +#define ENET_TACC_SHIFT16_MASK (0x1U) +#define ENET_TACC_SHIFT16_SHIFT (0U) +/*! SHIFT16 - TX FIFO Shift-16 + * 0b0..Disabled. + * 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the + * frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This + * function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is + * extended to a 16-byte header. + */ +#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) +#define ENET_TACC_IPCHK_MASK (0x8U) +#define ENET_TACC_IPCHK_SHIFT (3U) +/*! IPCHK + * 0b0..Checksum is not inserted. + * 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must + * be cleared. If a non-IP frame is transmitted the frame is not modified. + */ +#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) +#define ENET_TACC_PROCHK_MASK (0x10U) +#define ENET_TACC_PROCHK_SHIFT (4U) +/*! PROCHK + * 0b0..Checksum not inserted. + * 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the + * frame. The checksum field must be cleared. The other frames are not modified. + */ +#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK) +/*! @} */ + +/*! @name RACC - Receive Accelerator Function Configuration */ +/*! @{ */ +#define ENET_RACC_PADREM_MASK (0x1U) +#define ENET_RACC_PADREM_SHIFT (0U) +/*! PADREM - Enable Padding Removal For Short IP Frames + * 0b0..Padding not removed. + * 0b1..Any bytes following the IP payload section of the frame are removed from the frame. + */ +#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) +#define ENET_RACC_IPDIS_MASK (0x2U) +#define ENET_RACC_IPDIS_SHIFT (1U) +/*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum + * 0b0..Frames with wrong IPv4 header checksum are not discarded. + * 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no + * header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in + * store and forward mode (RSFL cleared). + */ +#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) +#define ENET_RACC_PRODIS_MASK (0x4U) +#define ENET_RACC_PRODIS_SHIFT (2U) +/*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum + * 0b0..Frames with wrong checksum are not discarded. + * 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame + * is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL + * cleared). + */ +#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) +#define ENET_RACC_LINEDIS_MASK (0x40U) +#define ENET_RACC_LINEDIS_SHIFT (6U) +/*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors + * 0b0..Frames with errors are not discarded. + * 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. + */ +#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) +#define ENET_RACC_SHIFT16_MASK (0x80U) +#define ENET_RACC_SHIFT16_SHIFT (7U) +/*! SHIFT16 - RX FIFO Shift-16 + * 0b0..Disabled. + * 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. + */ +#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK) +/*! @} */ + +/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_COL - Tx Collision Count Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) +#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) +#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK) +/*! @} */ + +/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ +/*! @{ */ +#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) +#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) +#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK) +/*! @} */ + +/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) +#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) +#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) +#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_SQE - Reserved Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) +#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) +#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) +#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) +#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) +#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_JAB_COUNT_SHIFT (0U) +#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P64_COUNT_SHIFT (0U) +#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) +#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) +#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) +#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) +#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) +#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) +#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) +#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK) +/*! @} */ + +/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ +/*! @{ */ +#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) +#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) +#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) +#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) +#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) +#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) +#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) +#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK) +/*! @} */ + +/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ +/*! @{ */ +#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) +#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) +#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK) +/*! @} */ + +/*! @name ATCR - Adjustable Timer Control Register */ +/*! @{ */ +#define ENET_ATCR_EN_MASK (0x1U) +#define ENET_ATCR_EN_SHIFT (0U) +/*! EN - Enable Timer + * 0b0..The timer stops at the current value. + * 0b1..The timer starts incrementing. + */ +#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) +#define ENET_ATCR_OFFEN_MASK (0x4U) +#define ENET_ATCR_OFFEN_SHIFT (2U) +/*! OFFEN - Enable One-Shot Offset Event + * 0b0..Disable. + * 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared + * when the offset event is reached, so no further event occurs until the field is set again. The timer + * offset value must be set before setting this field. + */ +#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) +#define ENET_ATCR_OFFRST_MASK (0x8U) +#define ENET_ATCR_OFFRST_SHIFT (3U) +/*! OFFRST - Reset Timer On Offset Event + * 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. + * 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. + */ +#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) +#define ENET_ATCR_PEREN_MASK (0x10U) +#define ENET_ATCR_PEREN_SHIFT (4U) +/*! PEREN - Enable Periodical Event + * 0b0..Disable. + * 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when + * the timer wraps around according to the periodic setting ATPER. The timer period value must be set before + * setting this bit. Not all devices contain the event signal output. See the chip configuration details. + */ +#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) +#define ENET_ATCR_PINPER_MASK (0x80U) +#define ENET_ATCR_PINPER_SHIFT (7U) +/*! PINPER + * 0b0..Disable. + * 0b1..Enable. + */ +#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) +#define ENET_ATCR_RESTART_MASK (0x200U) +#define ENET_ATCR_RESTART_SHIFT (9U) +#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) +#define ENET_ATCR_CAPTURE_MASK (0x800U) +#define ENET_ATCR_CAPTURE_SHIFT (11U) +/*! CAPTURE - Capture Timer Value + * 0b0..No effect. + * 0b1..The current time is captured and can be read from the ATVR register. + */ +#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) +#define ENET_ATCR_SLAVE_MASK (0x2000U) +#define ENET_ATCR_SLAVE_SHIFT (13U) +/*! SLAVE - Enable Timer Slave Mode + * 0b0..The timer is active and all configuration fields in this register are relevant. + * 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except + * CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. + */ +#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK) +/*! @} */ + +/*! @name ATVR - Timer Value Register */ +/*! @{ */ +#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) +#define ENET_ATVR_ATIME_SHIFT (0U) +#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) +/*! @} */ + +/*! @name ATOFF - Timer Offset Register */ +/*! @{ */ +#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) +#define ENET_ATOFF_OFFSET_SHIFT (0U) +#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) +/*! @} */ + +/*! @name ATPER - Timer Period Register */ +/*! @{ */ +#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) +#define ENET_ATPER_PERIOD_SHIFT (0U) +#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK) +/*! @} */ + +/*! @name ATCOR - Timer Correction Register */ +/*! @{ */ +#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) +#define ENET_ATCOR_COR_SHIFT (0U) +#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK) +/*! @} */ + +/*! @name ATINC - Time-Stamping Clock Period Register */ +/*! @{ */ +#define ENET_ATINC_INC_MASK (0x7FU) +#define ENET_ATINC_INC_SHIFT (0U) +#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) +#define ENET_ATINC_INC_CORR_MASK (0x7F00U) +#define ENET_ATINC_INC_CORR_SHIFT (8U) +#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK) +/*! @} */ + +/*! @name ATSTMP - Timestamp of Last Transmitted Frame */ +/*! @{ */ +#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) +#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) +#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK) +/*! @} */ + +/*! @name TGSR - Timer Global Status Register */ +/*! @{ */ +#define ENET_TGSR_TF0_MASK (0x1U) +#define ENET_TGSR_TF0_SHIFT (0U) +/*! TF0 - Copy Of Timer Flag For Channel 0 + * 0b0..Timer Flag for Channel 0 is clear + * 0b1..Timer Flag for Channel 0 is set + */ +#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) +#define ENET_TGSR_TF1_MASK (0x2U) +#define ENET_TGSR_TF1_SHIFT (1U) +/*! TF1 - Copy Of Timer Flag For Channel 1 + * 0b0..Timer Flag for Channel 1 is clear + * 0b1..Timer Flag for Channel 1 is set + */ +#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) +#define ENET_TGSR_TF2_MASK (0x4U) +#define ENET_TGSR_TF2_SHIFT (2U) +/*! TF2 - Copy Of Timer Flag For Channel 2 + * 0b0..Timer Flag for Channel 2 is clear + * 0b1..Timer Flag for Channel 2 is set + */ +#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) +#define ENET_TGSR_TF3_MASK (0x8U) +#define ENET_TGSR_TF3_SHIFT (3U) +/*! TF3 - Copy Of Timer Flag For Channel 3 + * 0b0..Timer Flag for Channel 3 is clear + * 0b1..Timer Flag for Channel 3 is set + */ +#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK) +/*! @} */ + +/*! @name TCSR - Timer Control Status Register */ +/*! @{ */ +#define ENET_TCSR_TDRE_MASK (0x1U) +#define ENET_TCSR_TDRE_SHIFT (0U) +/*! TDRE - Timer DMA Request Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) +#define ENET_TCSR_TMODE_MASK (0x3CU) +#define ENET_TCSR_TMODE_SHIFT (2U) +/*! TMODE - Timer Mode + * 0b0000..Timer Channel is disabled. + * 0b0001..Timer Channel is configured for Input Capture on rising edge. + * 0b0010..Timer Channel is configured for Input Capture on falling edge. + * 0b0011..Timer Channel is configured for Input Capture on both edges. + * 0b0100..Timer Channel is configured for Output Compare - software only. + * 0b0101..Timer Channel is configured for Output Compare - toggle output on compare. + * 0b0110..Timer Channel is configured for Output Compare - clear output on compare. + * 0b0111..Timer Channel is configured for Output Compare - set output on compare. + * 0b1000..Reserved + * 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. + * 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. + * 0b110x..Reserved + * 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. + * 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC. + */ +#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) +#define ENET_TCSR_TIE_MASK (0x40U) +#define ENET_TCSR_TIE_SHIFT (6U) +/*! TIE - Timer Interrupt Enable + * 0b0..Interrupt is disabled + * 0b1..Interrupt is enabled + */ +#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) +#define ENET_TCSR_TF_MASK (0x80U) +#define ENET_TCSR_TF_SHIFT (7U) +/*! TF - Timer Flag + * 0b0..Input Capture or Output Compare has not occurred. + * 0b1..Input Capture or Output Compare has occurred. + */ +#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) +#define ENET_TCSR_TPWC_MASK (0xF800U) +#define ENET_TCSR_TPWC_SHIFT (11U) +/*! TPWC - Timer PulseWidth Control + * 0b00000..Pulse width is one 1588-clock cycle. + * 0b00001..Pulse width is two 1588-clock cycles. + * 0b00010..Pulse width is three 1588-clock cycles. + * 0b00011..Pulse width is four 1588-clock cycles. + * 0b11111..Pulse width is 32 1588-clock cycles. + */ +#define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK) +/*! @} */ + +/* The count of ENET_TCSR */ +#define ENET_TCSR_COUNT (4U) + +/*! @name TCCR - Timer Compare Capture Register */ +/*! @{ */ +#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) +#define ENET_TCCR_TCC_SHIFT (0U) +#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK) +/*! @} */ + +/* The count of ENET_TCCR */ +#define ENET_TCCR_COUNT (4U) + + +/*! + * @} + */ /* end of group ENET_Register_Masks */ + + +/* ENET - Peripheral instance base addresses */ +/** Peripheral ENET base address */ +#define ENET_BASE (0x402D8000u) +/** Peripheral ENET base pointer */ +#define ENET ((ENET_Type *)ENET_BASE) +/** Peripheral ENET2 base address */ +#define ENET2_BASE (0x402D4000u) +/** Peripheral ENET2 base pointer */ +#define ENET2 ((ENET_Type *)ENET2_BASE) +/** Array initializer of ENET peripheral base addresses */ +#define ENET_BASE_ADDRS { ENET_BASE, 0u, ENET2_BASE } +/** Array initializer of ENET peripheral base pointers */ +#define ENET_BASE_PTRS { ENET, (ENET_Type *)0u, ENET2 } +/** Interrupt vectors for the ENET peripheral type */ +#define ENET_Transmit_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn } +#define ENET_Receive_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn } +#define ENET_Error_IRQS { ENET_IRQn, NotAvail_IRQn, ENET2_IRQn } +#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn, NotAvail_IRQn, ENET2_1588_Timer_IRQn } +/* ENET Buffer Descriptor and Buffer Address Alignment. */ +#define ENET_BUFF_ALIGNMENT (64U) + + +/*! + * @} + */ /* end of group ENET_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer + * @{ + */ + +/** EWM - Register Layout Typedef */ +typedef struct { + __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ + __O uint8_t SERV; /**< Service Register, offset: 0x1 */ + __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ + __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ + __IO uint8_t CLKCTRL; /**< Clock Control Register, offset: 0x4 */ + __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */ +} EWM_Type; + +/* ---------------------------------------------------------------------------- + -- EWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EWM_Register_Masks EWM Register Masks + * @{ + */ + +/*! @name CTRL - Control Register */ +/*! @{ */ +#define EWM_CTRL_EWMEN_MASK (0x1U) +#define EWM_CTRL_EWMEN_SHIFT (0U) +#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) +#define EWM_CTRL_ASSIN_MASK (0x2U) +#define EWM_CTRL_ASSIN_SHIFT (1U) +#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) +#define EWM_CTRL_INEN_MASK (0x4U) +#define EWM_CTRL_INEN_SHIFT (2U) +#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) +#define EWM_CTRL_INTEN_MASK (0x8U) +#define EWM_CTRL_INTEN_SHIFT (3U) +#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) +/*! @} */ + +/*! @name SERV - Service Register */ +/*! @{ */ +#define EWM_SERV_SERVICE_MASK (0xFFU) +#define EWM_SERV_SERVICE_SHIFT (0U) +#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) +/*! @} */ + +/*! @name CMPL - Compare Low Register */ +/*! @{ */ +#define EWM_CMPL_COMPAREL_MASK (0xFFU) +#define EWM_CMPL_COMPAREL_SHIFT (0U) +#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) +/*! @} */ + +/*! @name CMPH - Compare High Register */ +/*! @{ */ +#define EWM_CMPH_COMPAREH_MASK (0xFFU) +#define EWM_CMPH_COMPAREH_SHIFT (0U) +#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) +/*! @} */ + +/*! @name CLKCTRL - Clock Control Register */ +/*! @{ */ +#define EWM_CLKCTRL_CLKSEL_MASK (0x3U) +#define EWM_CLKCTRL_CLKSEL_SHIFT (0U) +#define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK) +/*! @} */ + +/*! @name CLKPRESCALER - Clock Prescaler Register */ +/*! @{ */ +#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) +#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) +#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group EWM_Register_Masks */ + + +/* EWM - Peripheral instance base addresses */ +/** Peripheral EWM base address */ +#define EWM_BASE (0x400B4000u) +/** Peripheral EWM base pointer */ +#define EWM ((EWM_Type *)EWM_BASE) +/** Array initializer of EWM peripheral base addresses */ +#define EWM_BASE_ADDRS { EWM_BASE } +/** Array initializer of EWM peripheral base pointers */ +#define EWM_BASE_PTRS { EWM } +/** Interrupt vectors for the EWM peripheral type */ +#define EWM_IRQS { EWM_IRQn } + +/*! + * @} + */ /* end of group EWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer + * @{ + */ + +/** FLEXIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ + __I uint32_t PIN; /**< Pin State Register, offset: 0xC */ + __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ + __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ + __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ + __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ + __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */ + uint8_t RESERVED_3[60]; + __IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_4[112]; + __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_5[240]; + __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_6[112]; + __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_7[112]; + __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_8[112]; + __IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ + uint8_t RESERVED_9[112]; + __IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_10[112]; + __IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ + uint8_t RESERVED_11[112]; + __IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ + uint8_t RESERVED_12[368]; + __IO uint32_t SHIFTBUFNBS[4]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */ + uint8_t RESERVED_13[112]; + __IO uint32_t SHIFTBUFHWS[4]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */ + uint8_t RESERVED_14[112]; + __IO uint32_t SHIFTBUFNIS[4]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */ +} FLEXIO_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) +#define FLEXIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented. + * 0b0000000000000001..Supports state, logic and parallel modes. + */ +#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) +#define FLEXIO_VERID_MINOR_MASK (0xFF0000U) +#define FLEXIO_VERID_MINOR_SHIFT (16U) +#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) +#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) +#define FLEXIO_VERID_MAJOR_SHIFT (24U) +#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) +#define FLEXIO_PARAM_SHIFTER_SHIFT (0U) +#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) +#define FLEXIO_PARAM_TIMER_MASK (0xFF00U) +#define FLEXIO_PARAM_TIMER_SHIFT (8U) +#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) +#define FLEXIO_PARAM_PIN_MASK (0xFF0000U) +#define FLEXIO_PARAM_PIN_SHIFT (16U) +#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) +#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) +#define FLEXIO_PARAM_TRIGGER_SHIFT (24U) +#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) +/*! @} */ + +/*! @name CTRL - FlexIO Control Register */ +/*! @{ */ +#define FLEXIO_CTRL_FLEXEN_MASK (0x1U) +#define FLEXIO_CTRL_FLEXEN_SHIFT (0U) +/*! FLEXEN - FlexIO Enable + * 0b0..FlexIO module is disabled. + * 0b1..FlexIO module is enabled. + */ +#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) +#define FLEXIO_CTRL_SWRST_MASK (0x2U) +#define FLEXIO_CTRL_SWRST_SHIFT (1U) +/*! SWRST - Software Reset + * 0b0..Software reset is disabled + * 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset. + */ +#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) +#define FLEXIO_CTRL_FASTACC_MASK (0x4U) +#define FLEXIO_CTRL_FASTACC_SHIFT (2U) +/*! FASTACC - Fast Access + * 0b0..Configures for normal register accesses to FlexIO + * 0b1..Configures for fast register accesses to FlexIO + */ +#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) +#define FLEXIO_CTRL_DBGE_MASK (0x40000000U) +#define FLEXIO_CTRL_DBGE_SHIFT (30U) +/*! DBGE - Debug Enable + * 0b0..FlexIO is disabled in debug modes. + * 0b1..FlexIO is enabled in debug modes + */ +#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) +#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) +#define FLEXIO_CTRL_DOZEN_SHIFT (31U) +/*! DOZEN - Doze Enable + * 0b0..FlexIO enabled in Doze modes. + * 0b1..FlexIO disabled in Doze modes. + */ +#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) +/*! @} */ + +/*! @name PIN - Pin State Register */ +/*! @{ */ +#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */ +#define FLEXIO_PIN_PDI_SHIFT (0U) +#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */ +/*! @} */ + +/*! @name SHIFTSTAT - Shifter Status Register */ +/*! @{ */ +#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU) +#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) +#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) +/*! @} */ + +/*! @name SHIFTERR - Shifter Error Register */ +/*! @{ */ +#define FLEXIO_SHIFTERR_SEF_MASK (0xFU) +#define FLEXIO_SHIFTERR_SEF_SHIFT (0U) +#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) +/*! @} */ + +/*! @name TIMSTAT - Timer Status Register */ +/*! @{ */ +#define FLEXIO_TIMSTAT_TSF_MASK (0xFU) +#define FLEXIO_TIMSTAT_TSF_SHIFT (0U) +#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) +/*! @} */ + +/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ +/*! @{ */ +#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU) +#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) +#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) +/*! @} */ + +/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ +/*! @{ */ +#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU) +#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) +#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) +/*! @} */ + +/*! @name TIMIEN - Timer Interrupt Enable Register */ +/*! @{ */ +#define FLEXIO_TIMIEN_TEIE_MASK (0xFU) +#define FLEXIO_TIMIEN_TEIE_SHIFT (0U) +#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) +/*! @} */ + +/*! @name SHIFTSDEN - Shifter Status DMA Enable */ +/*! @{ */ +#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU) +#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) +#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) +/*! @} */ + +/*! @name SHIFTSTATE - Shifter State Register */ +/*! @{ */ +#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) +#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) +#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) +/*! @} */ + +/*! @name SHIFTCTL - Shifter Control N Register */ +/*! @{ */ +#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) +#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) +/*! SMOD - Shifter Mode + * 0b000..Disabled. + * 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. + * 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. + * 0b011..Reserved. + * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. + * 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. + * 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes. + * 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. + */ +#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) +#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) +#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Shifter Pin Polarity + * 0b0..Pin is active high + * 0b1..Pin is active low + */ +#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) +#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ +#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) +#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ +#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Shifter Pin Configuration + * 0b00..Shifter pin output disabled + * 0b01..Shifter pin open drain or bidirectional output enable + * 0b10..Shifter pin bidirectional output data + * 0b11..Shifter pin output + */ +#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) +#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) +#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) +/*! TIMPOL - Timer Polarity + * 0b0..Shift on posedge of Shift clock + * 0b1..Shift on negedge of Shift clock + */ +#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) +#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U) +#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) +#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCTL */ +#define FLEXIO_SHIFTCTL_COUNT (4U) + +/*! @name SHIFTCFG - Shifter Configuration N Register */ +/*! @{ */ +#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) +#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) +/*! SSTART - Shifter Start bit + * 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable + * 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift + * 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 + * 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 + */ +#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) +#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) +#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) +/*! SSTOP - Shifter Stop bit + * 0b00..Stop bit disabled for transmitter/receiver/match store + * 0b01..Reserved for transmitter/receiver/match store + * 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 + * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 + */ +#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) +#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) +#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) +/*! INSRC - Input Source + * 0b0..Pin + * 0b1..Shifter N+1 Output + */ +#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) +#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ +#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) +#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ +/*! @} */ + +/* The count of FLEXIO_SHIFTCFG */ +#define FLEXIO_SHIFTCFG_COUNT (4U) + +/*! @name SHIFTBUF - Shifter Buffer N Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) +#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUF */ +#define FLEXIO_SHIFTBUF_COUNT (4U) + +/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBIS */ +#define FLEXIO_SHIFTBUFBIS_COUNT (4U) + +/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBYS */ +#define FLEXIO_SHIFTBUFBYS_COUNT (4U) + +/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBBS */ +#define FLEXIO_SHIFTBUFBBS_COUNT (4U) + +/*! @name TIMCTL - Timer Control N Register */ +/*! @{ */ +#define FLEXIO_TIMCTL_TIMOD_MASK (0x3U) +#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) +/*! TIMOD - Timer Mode + * 0b00..Timer Disabled. + * 0b01..Dual 8-bit counters baud mode. + * 0b10..Dual 8-bit counters PWM high mode. + * 0b11..Single 16-bit counter mode. + */ +#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) +#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) +#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Timer Pin Polarity + * 0b0..Pin is active high + * 0b1..Pin is active low + */ +#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) +#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ +#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) +#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ +#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Timer Pin Configuration + * 0b00..Timer pin output disabled + * 0b01..Timer pin open drain or bidirectional output enable + * 0b10..Timer pin bidirectional output data + * 0b11..Timer pin output + */ +#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) +#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) +#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) +/*! TRGSRC - Trigger Source + * 0b0..External trigger selected + * 0b1..Internal trigger selected + */ +#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) +#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) +#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) +/*! TRGPOL - Trigger Polarity + * 0b0..Trigger active high + * 0b1..Trigger active low + */ +#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) +#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ +#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) +#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ +/*! @} */ + +/* The count of FLEXIO_TIMCTL */ +#define FLEXIO_TIMCTL_COUNT (4U) + +/*! @name TIMCFG - Timer Configuration N Register */ +/*! @{ */ +#define FLEXIO_TIMCFG_TSTART_MASK (0x2U) +#define FLEXIO_TIMCFG_TSTART_SHIFT (1U) +/*! TSTART - Timer Start Bit + * 0b0..Start bit disabled + * 0b1..Start bit enabled + */ +#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) +#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) +#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) +/*! TSTOP - Timer Stop Bit + * 0b00..Stop bit disabled + * 0b01..Stop bit is enabled on timer compare + * 0b10..Stop bit is enabled on timer disable + * 0b11..Stop bit is enabled on timer compare and timer disable + */ +#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) +#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) +#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) +/*! TIMENA - Timer Enable + * 0b000..Timer always enabled + * 0b001..Timer enabled on Timer N-1 enable + * 0b010..Timer enabled on Trigger high + * 0b011..Timer enabled on Trigger high and Pin high + * 0b100..Timer enabled on Pin rising edge + * 0b101..Timer enabled on Pin rising edge and Trigger high + * 0b110..Timer enabled on Trigger rising edge + * 0b111..Timer enabled on Trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) +#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) +#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) +/*! TIMDIS - Timer Disable + * 0b000..Timer never disabled + * 0b001..Timer disabled on Timer N-1 disable + * 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement) + * 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low + * 0b100..Timer disabled on Pin rising or falling edge + * 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high + * 0b110..Timer disabled on Trigger falling edge + * 0b111..Reserved + */ +#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) +#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) +#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) +/*! TIMRST - Timer Reset + * 0b000..Timer never reset + * 0b001..Reserved + * 0b010..Timer reset on Timer Pin equal to Timer Output + * 0b011..Timer reset on Timer Trigger equal to Timer Output + * 0b100..Timer reset on Timer Pin rising edge + * 0b101..Reserved + * 0b110..Timer reset on Trigger rising edge + * 0b111..Timer reset on Trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) +#define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U) +#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) +/*! TIMDEC - Timer Decrement + * 0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output. + * 0b01..Decrement counter on Trigger input (both edges), Shift clock equals Timer output. + * 0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin input. + * 0b11..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. + */ +#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) +#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) +#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) +/*! TIMOUT - Timer Output + * 0b00..Timer output is logic one when enabled and is not affected by timer reset + * 0b01..Timer output is logic zero when enabled and is not affected by timer reset + * 0b10..Timer output is logic one when enabled and on timer reset + * 0b11..Timer output is logic zero when enabled and on timer reset + */ +#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCFG */ +#define FLEXIO_TIMCFG_COUNT (4U) + +/*! @name TIMCMP - Timer Compare N Register */ +/*! @{ */ +#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) +#define FLEXIO_TIMCMP_CMP_SHIFT (0U) +#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCMP */ +#define FLEXIO_TIMCMP_COUNT (4U) + +/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNBS */ +#define FLEXIO_SHIFTBUFNBS_COUNT (4U) + +/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFHWS */ +#define FLEXIO_SHIFTBUFHWS_COUNT (4U) + +/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */ +/*! @{ */ +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNIS */ +#define FLEXIO_SHIFTBUFNIS_COUNT (4U) + + +/*! + * @} + */ /* end of group FLEXIO_Register_Masks */ + + +/* FLEXIO - Peripheral instance base addresses */ +/** Peripheral FLEXIO1 base address */ +#define FLEXIO1_BASE (0x401AC000u) +/** Peripheral FLEXIO1 base pointer */ +#define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE) +/** Peripheral FLEXIO2 base address */ +#define FLEXIO2_BASE (0x401B0000u) +/** Peripheral FLEXIO2 base pointer */ +#define FLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE) +/** Peripheral FLEXIO3 base address */ +#define FLEXIO3_BASE (0x42020000u) +/** Peripheral FLEXIO3 base pointer */ +#define FLEXIO3 ((FLEXIO_Type *)FLEXIO3_BASE) +/** Array initializer of FLEXIO peripheral base addresses */ +#define FLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE, FLEXIO2_BASE, FLEXIO3_BASE } +/** Array initializer of FLEXIO peripheral base pointers */ +#define FLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2, FLEXIO3 } +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn, FLEXIO3_IRQn } + +/*! + * @} + */ /* end of group FLEXIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXRAM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXRAM_Peripheral_Access_Layer FLEXRAM Peripheral Access Layer + * @{ + */ + +/** FLEXRAM - Register Layout Typedef */ +typedef struct { + __IO uint32_t TCM_CTRL; /**< TCM CRTL Register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ + __IO uint32_t INT_STAT_EN; /**< Interrupt Status Enable Register, offset: 0x14 */ + __IO uint32_t INT_SIG_EN; /**< Interrupt Enable Register, offset: 0x18 */ +} FLEXRAM_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXRAM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXRAM_Register_Masks FLEXRAM Register Masks + * @{ + */ + +/*! @name TCM_CTRL - TCM CRTL Register */ +/*! @{ */ +#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U) +#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U) +/*! TCM_WWAIT_EN - TCM Write Wait Mode Enable + * 0b0..TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle. + * 0b1..TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles. + */ +#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK) +#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U) +#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U) +/*! TCM_RWAIT_EN - TCM Read Wait Mode Enable + * 0b0..TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle. + * 0b1..TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles. + */ +#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK) +#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U) +#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U) +#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt Status Register */ +/*! @{ */ +#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U) +#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U) +/*! ITCM_ERR_STATUS - ITCM Access Error Status + * 0b0..ITCM access error does not happen + * 0b1..ITCM access error happens. + */ +#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK) +#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U) +#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U) +/*! DTCM_ERR_STATUS - DTCM Access Error Status + * 0b0..DTCM access error does not happen + * 0b1..DTCM access error happens. + */ +#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK) +#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U) +#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U) +/*! OCRAM_ERR_STATUS - OCRAM Access Error Status + * 0b0..OCRAM access error does not happen + * 0b1..OCRAM access error happens. + */ +#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK) +/*! @} */ + +/*! @name INT_STAT_EN - Interrupt Status Enable Register */ +/*! @{ */ +#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U) +#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U) +/*! ITCM_ERR_STAT_EN - ITCM Access Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK) +#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U) +#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U) +/*! DTCM_ERR_STAT_EN - DTCM Access Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK) +#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U) +#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U) +/*! OCRAM_ERR_STAT_EN - OCRAM Access Error Status Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK) +/*! @} */ + +/*! @name INT_SIG_EN - Interrupt Enable Register */ +/*! @{ */ +#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U) +#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U) +/*! ITCM_ERR_SIG_EN - ITCM Access Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK) +#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U) +#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U) +/*! DTCM_ERR_SIG_EN - DTCM Access Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK) +#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U) +#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U) +/*! OCRAM_ERR_SIG_EN - OCRAM Access Error Interrupt Enable + * 0b0..Masked + * 0b1..Enabled + */ +#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXRAM_Register_Masks */ + + +/* FLEXRAM - Peripheral instance base addresses */ +/** Peripheral FLEXRAM base address */ +#define FLEXRAM_BASE (0x400B0000u) +/** Peripheral FLEXRAM base pointer */ +#define FLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE) +/** Array initializer of FLEXRAM peripheral base addresses */ +#define FLEXRAM_BASE_ADDRS { FLEXRAM_BASE } +/** Array initializer of FLEXRAM peripheral base pointers */ +#define FLEXRAM_BASE_PTRS { FLEXRAM } +/** Interrupt vectors for the FLEXRAM peripheral type */ +#define FLEXRAM_IRQS { FLEXRAM_IRQn } + +/*! + * @} + */ /* end of group FLEXRAM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer + * @{ + */ + +/** FLEXSPI - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ + __IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */ + __IO uint32_t MCR2; /**< Module Control Register 2, offset: 0x8 */ + __IO uint32_t AHBCR; /**< AHB Bus Control Register, offset: 0xC */ + __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x10 */ + __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */ + __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */ + __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */ + __IO uint32_t AHBRXBUFCR0[4]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_0[48]; + __IO uint32_t FLSHCR0[4]; /**< Flash A1 Control Register 0..Flash B2 Control Register 0, array offset: 0x60, array step: 0x4 */ + __IO uint32_t FLSHCR1[4]; /**< Flash A1 Control Register 1..Flash B2 Control Register 1, array offset: 0x70, array step: 0x4 */ + __IO uint32_t FLSHCR2[4]; /**< Flash A1 Control Register 2..Flash B2 Control Register 2, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */ + uint8_t RESERVED_2[8]; + __IO uint32_t IPCR0; /**< IP Control Register 0, offset: 0xA0 */ + __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */ + uint8_t RESERVED_3[8]; + __IO uint32_t IPCMD; /**< IP Command Register, offset: 0xB0 */ + uint8_t RESERVED_4[4]; + __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ + __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ + __IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_5[24]; + __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ + __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ + __I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */ + __I uint32_t AHBSPNDSTS; /**< AHB Suspend Status Register, offset: 0xEC */ + __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ + __I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */ + uint8_t RESERVED_6[8]; + __I uint32_t RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */ + __O uint32_t TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */ + __IO uint32_t LUT[64]; /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */ +} FLEXSPI_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks + * @{ + */ + +/*! @name MCR0 - Module Control Register 0 */ +/*! @{ */ +#define FLEXSPI_MCR0_SWRESET_MASK (0x1U) +#define FLEXSPI_MCR0_SWRESET_SHIFT (0U) +#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) +#define FLEXSPI_MCR0_MDIS_MASK (0x2U) +#define FLEXSPI_MCR0_MDIS_SHIFT (1U) +#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) +#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) +#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) +/*! RXCLKSRC - Sample Clock source selection for Flash Reading + * 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally. + * 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. + * 0b10..Reserved + * 0b11..Flash provided Read strobe and input from DQS pad + */ +#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) +#define FLEXSPI_MCR0_ARDFEN_MASK (0x40U) +#define FLEXSPI_MCR0_ARDFEN_SHIFT (6U) +/*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO. + * 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. + * 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response. + */ +#define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) +#define FLEXSPI_MCR0_ATDFEN_MASK (0x80U) +#define FLEXSPI_MCR0_ATDFEN_SHIFT (7U) +/*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO. + * 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. + * 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response. + */ +#define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) +#define FLEXSPI_MCR0_HSEN_MASK (0x800U) +#define FLEXSPI_MCR0_HSEN_SHIFT (11U) +/*! HSEN - Half Speed Serial Flash access Enable. + * 0b0..Disable divide by 2 of serial flash clock for half speed commands. + * 0b1..Enable divide by 2 of serial flash clock for half speed commands. + */ +#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) +#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) +#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U) +/*! DOZEEN - Doze mode enable bit + * 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. + * 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system. + */ +#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) +#define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U) +#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U) +/*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (SIOA[3:0] and SIOB[3:0]). + * 0b0..Disable. + * 0b1..Enable. + */ +#define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) +#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) +#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) +/*! SCKFREERUNEN - This bit is used to force SCK output free-running. For FPGA applications, + * external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is + * enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2). + * 0b0..Disable. + * 0b1..Enable. + */ +#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) +#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) +#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) +#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) +#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) +#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) +/*! @} */ + +/*! @name MCR1 - Module Control Register 1 */ +/*! @{ */ +#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) +#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) +#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) +#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) +#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) +#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) +/*! @} */ + +/*! @name MCR2 - Module Control Register 2 */ +/*! @{ */ +#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) +#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) +/*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned + * automaticaly when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or + * AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP + * mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. + * 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. + * 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. + */ +#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) +#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) +#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) +#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) +#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) +#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) +/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2. + * 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash + * A1/A2/B1/B2 seperately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, + * FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be + * ignored. + * 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. + */ +#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) +#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) +#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) +/*! SCKBDIFFOPT - SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). + * In this case, port B flash access is not available. After change the value of this feild, + * MCR0[SWRESET] should be set. + * 0b1..SCKB pad is used as port A SCK inverted clock output (Differential clock to SCKA). Port B flash access is not available. + * 0b0..SCKB pad is used as port B SCK clock output. Port B flash access is available. + */ +#define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) +#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) +#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) +#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) +/*! @} */ + +/*! @name AHBCR - AHB Bus Control Register */ +/*! @{ */ +#define FLEXSPI_AHBCR_APAREN_MASK (0x1U) +#define FLEXSPI_AHBCR_APAREN_SHIFT (0U) +/*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) . + * 0b0..Flash will be accessed in Individual mode. + * 0b1..Flash will be accessed in Parallel mode. + */ +#define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) +#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) +#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) +/*! CACHABLEEN - Enable AHB bus cachable read access support. + * 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. + * 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. + */ +#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) +#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) +#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) +/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat + * of AHB write access, refer for more details about AHB bufferable write. + * 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus + * ready after all data is transmitted to External device and AHB command finished. + * 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is + * granted by arbitrator and will not wait for AHB command finished. + */ +#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) +#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) +#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) +#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) +#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) +#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) +/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. + * 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable. + * 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more datas than AHB + * burst required to meet the alignment requirement. + */ +#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) +/*! @} */ + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ +#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) +#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) +#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) +#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) +#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) +#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) +#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) +#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) +#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) +#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) +#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) +#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) +#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) +#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) +#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) +#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) +#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) +#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) +#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) +#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) +#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) +#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) +#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) +#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) +#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U) +#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK) +#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) +#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) +#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) +/*! @} */ + +/*! @name INTR - Interrupt Register */ +/*! @{ */ +#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) +#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) +#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) +#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U) +#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U) +#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) +#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) +#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) +#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) +#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U) +#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U) +#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) +#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) +#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) +#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) +#define FLEXSPI_INTR_IPRXWA_MASK (0x20U) +#define FLEXSPI_INTR_IPRXWA_SHIFT (5U) +#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) +#define FLEXSPI_INTR_IPTXWE_MASK (0x40U) +#define FLEXSPI_INTR_IPTXWE_SHIFT (6U) +#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) +#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) +#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) +#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) +#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) +#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) +#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) +#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U) +#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U) +#define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK) +#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) +#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) +#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) +/*! @} */ + +/*! @name LUTKEY - LUT Key Register */ +/*! @{ */ +#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) +#define FLEXSPI_LUTKEY_KEY_SHIFT (0U) +#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) +/*! @} */ + +/*! @name LUTCR - LUT Control Register */ +/*! @{ */ +#define FLEXSPI_LUTCR_LOCK_MASK (0x1U) +#define FLEXSPI_LUTCR_LOCK_SHIFT (0U) +#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) +#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) +#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) +#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) +/*! @} */ + +/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0 */ +/*! @{ */ +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) +#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) +#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) +#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) +#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) +#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) +#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) +/*! @} */ + +/* The count of FLEXSPI_AHBRXBUFCR0 */ +#define FLEXSPI_AHBRXBUFCR0_COUNT (4U) + +/*! @name FLSHCR0 - Flash A1 Control Register 0..Flash B2 Control Register 0 */ +/*! @{ */ +#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) +#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) +#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR0 */ +#define FLEXSPI_FLSHCR0_COUNT (4U) + +/*! @name FLSHCR1 - Flash A1 Control Register 1..Flash B2 Control Register 1 */ +/*! @{ */ +#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) +#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) +#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) +#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) +#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) +#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) +#define FLEXSPI_FLSHCR1_WA_MASK (0x400U) +#define FLEXSPI_FLSHCR1_WA_SHIFT (10U) +#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) +#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) +#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U) +#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) +/*! CSINTERVALUNIT - CS interval unit + * 0b0..The CS interval unit is 1 serial clock cycle + * 0b1..The CS interval unit is 256 serial clock cycle + */ +#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) +#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) +#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) +#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR1 */ +#define FLEXSPI_FLSHCR1_COUNT (4U) + +/*! @name FLSHCR2 - Flash A1 Control Register 2..Flash B2 Control Register 2 */ +/*! @{ */ +#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU) +#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) +#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) +#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) +#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) +#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) +#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U) +#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) +#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) +#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) +#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) +#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) +#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) +#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) +#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) +#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) +/*! AWRWAITUNIT - AWRWAIT unit + * 0b000..The AWRWAIT unit is 2 ahb clock cycle + * 0b001..The AWRWAIT unit is 8 ahb clock cycle + * 0b010..The AWRWAIT unit is 32 ahb clock cycle + * 0b011..The AWRWAIT unit is 128 ahb clock cycle + * 0b100..The AWRWAIT unit is 512 ahb clock cycle + * 0b101..The AWRWAIT unit is 2048 ahb clock cycle + * 0b110..The AWRWAIT unit is 8192 ahb clock cycle + * 0b111..The AWRWAIT unit is 32768 ahb clock cycle + */ +#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) +#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) +/*! @} */ + +/* The count of FLEXSPI_FLSHCR2 */ +#define FLEXSPI_FLSHCR2_COUNT (4U) + +/*! @name FLSHCR4 - Flash Control Register 4 */ +/*! @{ */ +#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) +#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) +/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. + * 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write + * burst start address alignment when flash is accessed in individual mode. + * 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write + * burst start address alignment when flash is accessed in individual mode. + */ +#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) +#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) +#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) +/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for + * memory device on port A, this bit must be set. + * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + */ +#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) +#define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U) +#define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) +/*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for + * memory device on port B, this bit must be set. + * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + */ +#define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) +/*! @} */ + +/*! @name IPCR0 - IP Control Register 0 */ +/*! @{ */ +#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) +#define FLEXSPI_IPCR0_SFAR_SHIFT (0U) +#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) +/*! @} */ + +/*! @name IPCR1 - IP Control Register 1 */ +/*! @{ */ +#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) +#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) +#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) +#define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U) +#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U) +#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) +#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) +#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) +#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) +#define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U) +#define FLEXSPI_IPCR1_IPAREN_SHIFT (31U) +/*! IPAREN - Parallel mode Enabled for IP command. + * 0b0..Flash will be accessed in Individual mode. + * 0b1..Flash will be accessed in Parallel mode. + */ +#define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) +/*! @} */ + +/*! @name IPCMD - IP Command Register */ +/*! @{ */ +#define FLEXSPI_IPCMD_TRG_MASK (0x1U) +#define FLEXSPI_IPCMD_TRG_SHIFT (0U) +#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) +/*! @} */ + +/*! @name IPRXFCR - IP RX FIFO Control Register */ +/*! @{ */ +#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) +#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) +#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) +#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) +#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) +/*! RXDMAEN - IP RX FIFO reading by DMA enabled. + * 0b0..IP RX FIFO would be read by processor. + * 0b1..IP RX FIFO would be read by DMA. + */ +#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) +#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU) +#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) +#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) +/*! @} */ + +/*! @name IPTXFCR - IP TX FIFO Control Register */ +/*! @{ */ +#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) +#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) +#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) +#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) +#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) +/*! TXDMAEN - IP TX FIFO filling by DMA enabled. + * 0b0..IP TX FIFO would be filled by processor. + * 0b1..IP TX FIFO would be filled by DMA. + */ +#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) +#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU) +#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) +#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) +/*! @} */ + +/*! @name DLLCR - DLL Control Register 0 */ +/*! @{ */ +#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) +#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) +#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) +#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) +#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) +#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) +#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) +#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) +#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) +#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) +#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) +#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) +#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) +#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) +#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) +/*! @} */ + +/* The count of FLEXSPI_DLLCR */ +#define FLEXSPI_DLLCR_COUNT (2U) + +/*! @name STS0 - Status Register 0 */ +/*! @{ */ +#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) +#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) +#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) +#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U) +#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U) +#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) +#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) +#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) +/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted + * by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). + * 0b00..Triggered by AHB read command (triggered by AHB read). + * 0b01..Triggered by AHB write command (triggered by AHB Write). + * 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG). + * 0b11..Triggered by suspended command (resumed). + */ +#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) +/*! @} */ + +/*! @name STS1 - Status Register 1 */ +/*! @{ */ +#define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU) +#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) +#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) +#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) +#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) +/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be + * cleared when INTR[AHBCMDERR] is write-1-clear(w1c). + * 0b0000..No error. + * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence. + * 0b0011..There is unknown instruction opcode in the sequence. + * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + * 0b1110..Sequence execution timeout. + */ +#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) +#define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U) +#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) +#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) +#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) +#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) +/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be + * cleared when INTR[IPCMDERR] is write-1-clear(w1c). + * 0b0000..No error. + * 0b0010..IP command with JMP_ON_CS instruction used in the sequence. + * 0b0011..There is unknown instruction opcode in the sequence. + * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + * 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2). + * 0b1110..Sequence execution timeout. + * 0b1111..Flash boundary crossed. + */ +#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) +/*! @} */ + +/*! @name STS2 - Status Register 2 */ +/*! @{ */ +#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) +#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) +#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) +#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U) +#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U) +#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) +#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) +#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U) +#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) +#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) +#define FLEXSPI_STS2_AREFSEL_SHIFT (8U) +#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) +#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U) +#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U) +#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) +#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U) +#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U) +#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) +#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U) +#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U) +#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) +#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) +#define FLEXSPI_STS2_BREFSEL_SHIFT (24U) +#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) +/*! @} */ + +/*! @name AHBSPNDSTS - AHB Suspend Status Register */ +/*! @{ */ +#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) +#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) +#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) +#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) +#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) +#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) +#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) +#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) +#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) +/*! @} */ + +/*! @name IPRXFSTS - IP RX FIFO Status Register */ +/*! @{ */ +#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) +#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) +#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) +#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) +/*! @} */ + +/*! @name IPTXFSTS - IP TX FIFO Status Register */ +/*! @{ */ +#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) +#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) +#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) +#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) +#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) +#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) +/*! @} */ + +/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */ +/*! @{ */ +#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_RFDR_RXDATA_SHIFT (0U) +#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) +/*! @} */ + +/* The count of FLEXSPI_RFDR */ +#define FLEXSPI_RFDR_COUNT (32U) + +/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */ +/*! @{ */ +#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) +#define FLEXSPI_TFDR_TXDATA_SHIFT (0U) +#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) +/*! @} */ + +/* The count of FLEXSPI_TFDR */ +#define FLEXSPI_TFDR_COUNT (32U) + +/*! @name LUT - LUT 0..LUT 63 */ +/*! @{ */ +#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) +#define FLEXSPI_LUT_OPERAND0_SHIFT (0U) +#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) +#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) +#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) +#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) +#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) +#define FLEXSPI_LUT_OPCODE0_SHIFT (10U) +#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) +#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) +#define FLEXSPI_LUT_OPERAND1_SHIFT (16U) +#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) +#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) +#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) +#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) +#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) +#define FLEXSPI_LUT_OPCODE1_SHIFT (26U) +#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) +/*! @} */ + +/* The count of FLEXSPI_LUT */ +#define FLEXSPI_LUT_COUNT (64U) + + +/*! + * @} + */ /* end of group FLEXSPI_Register_Masks */ + + +/* FLEXSPI - Peripheral instance base addresses */ +/** Peripheral FLEXSPI base address */ +#define FLEXSPI_BASE (0x402A8000u) +/** Peripheral FLEXSPI base pointer */ +#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) +/** Peripheral FLEXSPI2 base address */ +#define FLEXSPI2_BASE (0x402A4000u) +/** Peripheral FLEXSPI2 base pointer */ +#define FLEXSPI2 ((FLEXSPI_Type *)FLEXSPI2_BASE) +/** Array initializer of FLEXSPI peripheral base addresses */ +#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE, 0u, FLEXSPI2_BASE } +/** Array initializer of FLEXSPI peripheral base pointers */ +#define FLEXSPI_BASE_PTRS { FLEXSPI, (FLEXSPI_Type *)0u, FLEXSPI2 } +/** Interrupt vectors for the FLEXSPI peripheral type */ +#define FLEXSPI_IRQS { FLEXSPI_IRQn, NotAvail_IRQn, FLEXSPI2_IRQn } +/* FlexSPI AMBA address. */ +#define FlexSPI_AMBA_BASE (0x60000000U) +/* FlexSPI ASFM address. */ +#define FlexSPI_ASFM_BASE (0x60000000U) +/* Base Address of AHB address space mapped to IP RX FIFO. */ +#define FlexSPI_ARDF_BASE (0x7FC00000U) +/* Base Address of AHB address space mapped to IP TX FIFO. */ +#define FlexSPI_ATDF_BASE (0x7F800000U) +/* FlexSPI2 AMBA address. */ +#define FlexSPI2_AMBA_BASE (0x70000000U) +/* FlexSPI ASFM address. */ +#define FlexSPI2_ASFM_BASE (0x70000000U) +/* Base Address of AHB address space mapped to IP RX FIFO. */ +#define FlexSPI2_ARDF_BASE (0x7F400000U) +/* Base Address of AHB address space mapped to IP TX FIFO. */ +#define FlexSPI2_ATDF_BASE (0x7F000000U) + + +/*! + * @} + */ /* end of group FLEXSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer + * @{ + */ + +/** GPC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CNTR; /**< GPC Interface control register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t IMR[4]; /**< IRQ masking register 1..IRQ masking register 4, array offset: 0x8, array step: 0x4 */ + __I uint32_t ISR[4]; /**< IRQ status resister 1..IRQ status resister 4, array offset: 0x18, array step: 0x4 */ + uint8_t RESERVED_1[12]; + __IO uint32_t IMR5; /**< IRQ masking register 5, offset: 0x34 */ + __I uint32_t ISR5; /**< IRQ status resister 5, offset: 0x38 */ +} GPC_Type; + +/* ---------------------------------------------------------------------------- + -- GPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Register_Masks GPC Register Masks + * @{ + */ + +/*! @name CNTR - GPC Interface control register */ +/*! @{ */ +#define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U) +#define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U) +/*! MEGA_PDN_REQ + * 0b0..No Request + * 0b1..Request power down sequence + */ +#define GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK) +#define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U) +#define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U) +/*! MEGA_PUP_REQ + * 0b0..No Request + * 0b1..Request power up sequence + */ +#define GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK) +#define GPC_CNTR_PDRAM0_PGE_MASK (0x400000U) +#define GPC_CNTR_PDRAM0_PGE_SHIFT (22U) +/*! PDRAM0_PGE + * 0b1..FlexRAM PDRAM0 domain will be power down once when CPU core is power down. + * 0b0..FlexRAM PDRAM0 domain will keep power on even if CPU core is power down. + */ +#define GPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK) +/*! @} */ + +/*! @name IMR - IRQ masking register 1..IRQ masking register 4 */ +/*! @{ */ +#define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR1_SHIFT (0U) +#define GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK) +#define GPC_IMR_IMR2_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR2_SHIFT (0U) +#define GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK) +#define GPC_IMR_IMR3_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR3_SHIFT (0U) +#define GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK) +#define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) +#define GPC_IMR_IMR4_SHIFT (0U) +#define GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK) +/*! @} */ + +/* The count of GPC_IMR */ +#define GPC_IMR_COUNT (4U) + +/*! @name ISR - IRQ status resister 1..IRQ status resister 4 */ +/*! @{ */ +#define GPC_ISR_ISR1_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR1_SHIFT (0U) +#define GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK) +#define GPC_ISR_ISR2_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR2_SHIFT (0U) +#define GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK) +#define GPC_ISR_ISR3_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR3_SHIFT (0U) +#define GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK) +#define GPC_ISR_ISR4_MASK (0xFFFFFFFFU) +#define GPC_ISR_ISR4_SHIFT (0U) +#define GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK) +/*! @} */ + +/* The count of GPC_ISR */ +#define GPC_ISR_COUNT (4U) + +/*! @name IMR5 - IRQ masking register 5 */ +/*! @{ */ +#define GPC_IMR5_IMR5_MASK (0xFFFFFFFFU) +#define GPC_IMR5_IMR5_SHIFT (0U) +#define GPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK) +/*! @} */ + +/*! @name ISR5 - IRQ status resister 5 */ +/*! @{ */ +#define GPC_ISR5_ISR4_MASK (0xFFFFFFFFU) +#define GPC_ISR5_ISR4_SHIFT (0U) +#define GPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPC_Register_Masks */ + + +/* GPC - Peripheral instance base addresses */ +/** Peripheral GPC base address */ +#define GPC_BASE (0x400F4000u) +/** Peripheral GPC base pointer */ +#define GPC ((GPC_Type *)GPC_BASE) +/** Array initializer of GPC peripheral base addresses */ +#define GPC_BASE_ADDRS { GPC_BASE } +/** Array initializer of GPC peripheral base pointers */ +#define GPC_BASE_PTRS { GPC } +/** Interrupt vectors for the GPC peripheral type */ +#define GPC_IRQS { GPC_IRQn } + +/*! + * @} + */ /* end of group GPC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */ + __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */ + __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */ + __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */ + __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */ + __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */ + __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */ + __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */ + uint8_t RESERVED_0[100]; + __O uint32_t DR_SET; /**< GPIO data register SET, offset: 0x84 */ + __O uint32_t DR_CLEAR; /**< GPIO data register CLEAR, offset: 0x88 */ + __O uint32_t DR_TOGGLE; /**< GPIO data register TOGGLE, offset: 0x8C */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name DR - GPIO data register */ +/*! @{ */ +#define GPIO_DR_DR_MASK (0xFFFFFFFFU) +#define GPIO_DR_DR_SHIFT (0U) +#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) +/*! @} */ + +/*! @name GDIR - GPIO direction register */ +/*! @{ */ +#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) +#define GPIO_GDIR_GDIR_SHIFT (0U) +#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) +/*! @} */ + +/*! @name PSR - GPIO pad status register */ +/*! @{ */ +#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU) +#define GPIO_PSR_PSR_SHIFT (0U) +#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) +/*! @} */ + +/*! @name ICR1 - GPIO interrupt configuration register1 */ +/*! @{ */ +#define GPIO_ICR1_ICR0_MASK (0x3U) +#define GPIO_ICR1_ICR0_SHIFT (0U) +/*! ICR0 - ICR0 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) +#define GPIO_ICR1_ICR1_MASK (0xCU) +#define GPIO_ICR1_ICR1_SHIFT (2U) +/*! ICR1 - ICR1 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK) +#define GPIO_ICR1_ICR2_MASK (0x30U) +#define GPIO_ICR1_ICR2_SHIFT (4U) +/*! ICR2 - ICR2 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK) +#define GPIO_ICR1_ICR3_MASK (0xC0U) +#define GPIO_ICR1_ICR3_SHIFT (6U) +/*! ICR3 - ICR3 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK) +#define GPIO_ICR1_ICR4_MASK (0x300U) +#define GPIO_ICR1_ICR4_SHIFT (8U) +/*! ICR4 - ICR4 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK) +#define GPIO_ICR1_ICR5_MASK (0xC00U) +#define GPIO_ICR1_ICR5_SHIFT (10U) +/*! ICR5 - ICR5 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK) +#define GPIO_ICR1_ICR6_MASK (0x3000U) +#define GPIO_ICR1_ICR6_SHIFT (12U) +/*! ICR6 - ICR6 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK) +#define GPIO_ICR1_ICR7_MASK (0xC000U) +#define GPIO_ICR1_ICR7_SHIFT (14U) +/*! ICR7 - ICR7 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK) +#define GPIO_ICR1_ICR8_MASK (0x30000U) +#define GPIO_ICR1_ICR8_SHIFT (16U) +/*! ICR8 - ICR8 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK) +#define GPIO_ICR1_ICR9_MASK (0xC0000U) +#define GPIO_ICR1_ICR9_SHIFT (18U) +/*! ICR9 - ICR9 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK) +#define GPIO_ICR1_ICR10_MASK (0x300000U) +#define GPIO_ICR1_ICR10_SHIFT (20U) +/*! ICR10 - ICR10 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK) +#define GPIO_ICR1_ICR11_MASK (0xC00000U) +#define GPIO_ICR1_ICR11_SHIFT (22U) +/*! ICR11 - ICR11 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK) +#define GPIO_ICR1_ICR12_MASK (0x3000000U) +#define GPIO_ICR1_ICR12_SHIFT (24U) +/*! ICR12 - ICR12 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK) +#define GPIO_ICR1_ICR13_MASK (0xC000000U) +#define GPIO_ICR1_ICR13_SHIFT (26U) +/*! ICR13 - ICR13 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK) +#define GPIO_ICR1_ICR14_MASK (0x30000000U) +#define GPIO_ICR1_ICR14_SHIFT (28U) +/*! ICR14 - ICR14 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK) +#define GPIO_ICR1_ICR15_MASK (0xC0000000U) +#define GPIO_ICR1_ICR15_SHIFT (30U) +/*! ICR15 - ICR15 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) +/*! @} */ + +/*! @name ICR2 - GPIO interrupt configuration register2 */ +/*! @{ */ +#define GPIO_ICR2_ICR16_MASK (0x3U) +#define GPIO_ICR2_ICR16_SHIFT (0U) +/*! ICR16 - ICR16 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) +#define GPIO_ICR2_ICR17_MASK (0xCU) +#define GPIO_ICR2_ICR17_SHIFT (2U) +/*! ICR17 - ICR17 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK) +#define GPIO_ICR2_ICR18_MASK (0x30U) +#define GPIO_ICR2_ICR18_SHIFT (4U) +/*! ICR18 - ICR18 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK) +#define GPIO_ICR2_ICR19_MASK (0xC0U) +#define GPIO_ICR2_ICR19_SHIFT (6U) +/*! ICR19 - ICR19 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK) +#define GPIO_ICR2_ICR20_MASK (0x300U) +#define GPIO_ICR2_ICR20_SHIFT (8U) +/*! ICR20 - ICR20 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK) +#define GPIO_ICR2_ICR21_MASK (0xC00U) +#define GPIO_ICR2_ICR21_SHIFT (10U) +/*! ICR21 - ICR21 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK) +#define GPIO_ICR2_ICR22_MASK (0x3000U) +#define GPIO_ICR2_ICR22_SHIFT (12U) +/*! ICR22 - ICR22 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK) +#define GPIO_ICR2_ICR23_MASK (0xC000U) +#define GPIO_ICR2_ICR23_SHIFT (14U) +/*! ICR23 - ICR23 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK) +#define GPIO_ICR2_ICR24_MASK (0x30000U) +#define GPIO_ICR2_ICR24_SHIFT (16U) +/*! ICR24 - ICR24 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK) +#define GPIO_ICR2_ICR25_MASK (0xC0000U) +#define GPIO_ICR2_ICR25_SHIFT (18U) +/*! ICR25 - ICR25 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK) +#define GPIO_ICR2_ICR26_MASK (0x300000U) +#define GPIO_ICR2_ICR26_SHIFT (20U) +/*! ICR26 - ICR26 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK) +#define GPIO_ICR2_ICR27_MASK (0xC00000U) +#define GPIO_ICR2_ICR27_SHIFT (22U) +/*! ICR27 - ICR27 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK) +#define GPIO_ICR2_ICR28_MASK (0x3000000U) +#define GPIO_ICR2_ICR28_SHIFT (24U) +/*! ICR28 - ICR28 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK) +#define GPIO_ICR2_ICR29_MASK (0xC000000U) +#define GPIO_ICR2_ICR29_SHIFT (26U) +/*! ICR29 - ICR29 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK) +#define GPIO_ICR2_ICR30_MASK (0x30000000U) +#define GPIO_ICR2_ICR30_SHIFT (28U) +/*! ICR30 - ICR30 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK) +#define GPIO_ICR2_ICR31_MASK (0xC0000000U) +#define GPIO_ICR2_ICR31_SHIFT (30U) +/*! ICR31 - ICR31 + * 0b00..Interrupt n is low-level sensitive. + * 0b01..Interrupt n is high-level sensitive. + * 0b10..Interrupt n is rising-edge sensitive. + * 0b11..Interrupt n is falling-edge sensitive. + */ +#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) +/*! @} */ + +/*! @name IMR - GPIO interrupt mask register */ +/*! @{ */ +#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU) +#define GPIO_IMR_IMR_SHIFT (0U) +#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) +/*! @} */ + +/*! @name ISR - GPIO interrupt status register */ +/*! @{ */ +#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU) +#define GPIO_ISR_ISR_SHIFT (0U) +#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) +/*! @} */ + +/*! @name EDGE_SEL - GPIO edge select register */ +/*! @{ */ +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) +#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) +/*! @} */ + +/*! @name DR_SET - GPIO data register SET */ +/*! @{ */ +#define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU) +#define GPIO_DR_SET_DR_SET_SHIFT (0U) +#define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK) +/*! @} */ + +/*! @name DR_CLEAR - GPIO data register CLEAR */ +/*! @{ */ +#define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU) +#define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U) +#define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK) +/*! @} */ + +/*! @name DR_TOGGLE - GPIO data register TOGGLE */ +/*! @{ */ +#define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU) +#define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U) +#define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x401B8000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x401BC000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x401C0000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x401C4000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Peripheral GPIO5 base address */ +#define GPIO5_BASE (0x400C0000u) +/** Peripheral GPIO5 base pointer */ +#define GPIO5 ((GPIO_Type *)GPIO5_BASE) +/** Peripheral GPIO6 base address */ +#define GPIO6_BASE (0x42000000u) +/** Peripheral GPIO6 base pointer */ +#define GPIO6 ((GPIO_Type *)GPIO6_BASE) +/** Peripheral GPIO7 base address */ +#define GPIO7_BASE (0x42004000u) +/** Peripheral GPIO7 base pointer */ +#define GPIO7 ((GPIO_Type *)GPIO7_BASE) +/** Peripheral GPIO8 base address */ +#define GPIO8_BASE (0x42008000u) +/** Peripheral GPIO8 base pointer */ +#define GPIO8 ((GPIO_Type *)GPIO8_BASE) +/** Peripheral GPIO9 base address */ +#define GPIO9_BASE (0x4200C000u) +/** Peripheral GPIO9 base pointer */ +#define GPIO9 ((GPIO_Type *)GPIO9_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE, GPIO8_BASE, GPIO9_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn } +#define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn } +#define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn, GPIO6_7_8_9_IRQn } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer + * @{ + */ + +/** GPT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */ + __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */ + __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */ + __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */ + __IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */ + __I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */ + __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */ +} GPT_Type; + +/* ---------------------------------------------------------------------------- + -- GPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Register_Masks GPT Register Masks + * @{ + */ + +/*! @name CR - GPT Control Register */ +/*! @{ */ +#define GPT_CR_EN_MASK (0x1U) +#define GPT_CR_EN_SHIFT (0U) +/*! EN + * 0b0..GPT is disabled. + * 0b1..GPT is enabled. + */ +#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) +#define GPT_CR_ENMOD_MASK (0x2U) +#define GPT_CR_ENMOD_SHIFT (1U) +/*! ENMOD + * 0b0..GPT counter will retain its value when it is disabled. + * 0b1..GPT counter value is reset to 0 when it is disabled. + */ +#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) +#define GPT_CR_DBGEN_MASK (0x4U) +#define GPT_CR_DBGEN_SHIFT (2U) +/*! DBGEN + * 0b0..GPT is disabled in debug mode. + * 0b1..GPT is enabled in debug mode. + */ +#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) +#define GPT_CR_WAITEN_MASK (0x8U) +#define GPT_CR_WAITEN_SHIFT (3U) +/*! WAITEN + * 0b0..GPT is disabled in wait mode. + * 0b1..GPT is enabled in wait mode. + */ +#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) +#define GPT_CR_DOZEEN_MASK (0x10U) +#define GPT_CR_DOZEEN_SHIFT (4U) +/*! DOZEEN + * 0b0..GPT is disabled in doze mode. + * 0b1..GPT is enabled in doze mode. + */ +#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) +#define GPT_CR_STOPEN_MASK (0x20U) +#define GPT_CR_STOPEN_SHIFT (5U) +/*! STOPEN + * 0b0..GPT is disabled in Stop mode. + * 0b1..GPT is enabled in Stop mode. + */ +#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) +#define GPT_CR_CLKSRC_MASK (0x1C0U) +#define GPT_CR_CLKSRC_SHIFT (6U) +/*! CLKSRC + * 0b000..No clock + * 0b001..Peripheral Clock (ipg_clk) + * 0b010..High Frequency Reference Clock (ipg_clk_highfreq) + * 0b011..External Clock + * 0b100..Low Frequency Reference Clock (ipg_clk_32k) + * 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M) + */ +#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) +#define GPT_CR_FRR_MASK (0x200U) +#define GPT_CR_FRR_SHIFT (9U) +/*! FRR + * 0b0..Restart mode + * 0b1..Free-Run mode + */ +#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) +#define GPT_CR_EN_24M_MASK (0x400U) +#define GPT_CR_EN_24M_SHIFT (10U) +/*! EN_24M + * 0b0..24M clock disabled + * 0b1..24M clock enabled + */ +#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) +#define GPT_CR_SWR_MASK (0x8000U) +#define GPT_CR_SWR_SHIFT (15U) +/*! SWR + * 0b0..GPT is not in reset state + * 0b1..GPT is in reset state + */ +#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) +#define GPT_CR_IM1_MASK (0x30000U) +#define GPT_CR_IM1_SHIFT (16U) +#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) +#define GPT_CR_IM2_MASK (0xC0000U) +#define GPT_CR_IM2_SHIFT (18U) +/*! IM2 + * 0b00..capture disabled + * 0b01..capture on rising edge only + * 0b10..capture on falling edge only + * 0b11..capture on both edges + */ +#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) +#define GPT_CR_OM1_MASK (0x700000U) +#define GPT_CR_OM1_SHIFT (20U) +#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK) +#define GPT_CR_OM2_MASK (0x3800000U) +#define GPT_CR_OM2_SHIFT (23U) +#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) +#define GPT_CR_OM3_MASK (0x1C000000U) +#define GPT_CR_OM3_SHIFT (26U) +/*! OM3 + * 0b000..Output disconnected. No response on pin. + * 0b001..Toggle output pin + * 0b010..Clear output pin + * 0b011..Set output pin + * 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin. + */ +#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) +#define GPT_CR_FO1_MASK (0x20000000U) +#define GPT_CR_FO1_SHIFT (29U) +#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK) +#define GPT_CR_FO2_MASK (0x40000000U) +#define GPT_CR_FO2_SHIFT (30U) +#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) +#define GPT_CR_FO3_MASK (0x80000000U) +#define GPT_CR_FO3_SHIFT (31U) +/*! FO3 + * 0b0..Writing a 0 has no effect. + * 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. + */ +#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) +/*! @} */ + +/*! @name PR - GPT Prescaler Register */ +/*! @{ */ +#define GPT_PR_PRESCALER_MASK (0xFFFU) +#define GPT_PR_PRESCALER_SHIFT (0U) +/*! PRESCALER + * 0b000000000000..Divide by 1 + * 0b000000000001..Divide by 2 + * 0b111111111111..Divide by 4096 + */ +#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) +#define GPT_PR_PRESCALER24M_MASK (0xF000U) +#define GPT_PR_PRESCALER24M_SHIFT (12U) +/*! PRESCALER24M + * 0b0000..Divide by 1 + * 0b0001..Divide by 2 + * 0b1111..Divide by 16 + */ +#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) +/*! @} */ + +/*! @name SR - GPT Status Register */ +/*! @{ */ +#define GPT_SR_OF1_MASK (0x1U) +#define GPT_SR_OF1_SHIFT (0U) +#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) +#define GPT_SR_OF2_MASK (0x2U) +#define GPT_SR_OF2_SHIFT (1U) +#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) +#define GPT_SR_OF3_MASK (0x4U) +#define GPT_SR_OF3_SHIFT (2U) +/*! OF3 + * 0b0..Compare event has not occurred. + * 0b1..Compare event has occurred. + */ +#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) +#define GPT_SR_IF1_MASK (0x8U) +#define GPT_SR_IF1_SHIFT (3U) +#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) +#define GPT_SR_IF2_MASK (0x10U) +#define GPT_SR_IF2_SHIFT (4U) +/*! IF2 + * 0b0..Capture event has not occurred. + * 0b1..Capture event has occurred. + */ +#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) +#define GPT_SR_ROV_MASK (0x20U) +#define GPT_SR_ROV_SHIFT (5U) +/*! ROV + * 0b0..Rollover has not occurred. + * 0b1..Rollover has occurred. + */ +#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) +/*! @} */ + +/*! @name IR - GPT Interrupt Register */ +/*! @{ */ +#define GPT_IR_OF1IE_MASK (0x1U) +#define GPT_IR_OF1IE_SHIFT (0U) +#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) +#define GPT_IR_OF2IE_MASK (0x2U) +#define GPT_IR_OF2IE_SHIFT (1U) +#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) +#define GPT_IR_OF3IE_MASK (0x4U) +#define GPT_IR_OF3IE_SHIFT (2U) +/*! OF3IE + * 0b0..Output Compare Channel n interrupt is disabled. + * 0b1..Output Compare Channel n interrupt is enabled. + */ +#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) +#define GPT_IR_IF1IE_MASK (0x8U) +#define GPT_IR_IF1IE_SHIFT (3U) +#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) +#define GPT_IR_IF2IE_MASK (0x10U) +#define GPT_IR_IF2IE_SHIFT (4U) +/*! IF2IE + * 0b0..IF2IE Input Capture n Interrupt Enable is disabled. + * 0b1..IF2IE Input Capture n Interrupt Enable is enabled. + */ +#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) +#define GPT_IR_ROVIE_MASK (0x20U) +#define GPT_IR_ROVIE_SHIFT (5U) +/*! ROVIE + * 0b0..Rollover interrupt is disabled. + * 0b1..Rollover interrupt enabled. + */ +#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) +/*! @} */ + +/*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */ +/*! @{ */ +#define GPT_OCR_COMP_MASK (0xFFFFFFFFU) +#define GPT_OCR_COMP_SHIFT (0U) +#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) +/*! @} */ + +/* The count of GPT_OCR */ +#define GPT_OCR_COUNT (3U) + +/*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */ +/*! @{ */ +#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) +#define GPT_ICR_CAPT_SHIFT (0U) +#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) +/*! @} */ + +/* The count of GPT_ICR */ +#define GPT_ICR_COUNT (2U) + +/*! @name CNT - GPT Counter Register */ +/*! @{ */ +#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) +#define GPT_CNT_COUNT_SHIFT (0U) +#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GPT_Register_Masks */ + + +/* GPT - Peripheral instance base addresses */ +/** Peripheral GPT1 base address */ +#define GPT1_BASE (0x401EC000u) +/** Peripheral GPT1 base pointer */ +#define GPT1 ((GPT_Type *)GPT1_BASE) +/** Peripheral GPT2 base address */ +#define GPT2_BASE (0x401F0000u) +/** Peripheral GPT2 base pointer */ +#define GPT2 ((GPT_Type *)GPT2_BASE) +/** Array initializer of GPT peripheral base addresses */ +#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE } +/** Array initializer of GPT peripheral base pointers */ +#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2 } +/** Interrupt vectors for the GPT peripheral type */ +#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn } + +/*! + * @} + */ /* end of group GPT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */ + __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */ + __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */ + __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */ + __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */ + __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */ + __O uint32_t TDR[4]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_0[16]; + __I uint32_t TFR[4]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[16]; + __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ + uint8_t RESERVED_2[36]; + __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */ + __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */ + __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */ + __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */ + __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */ + __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */ + __I uint32_t RDR[4]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_3[16]; + __I uint32_t RFR[4]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_4[16]; + __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define I2S_VERID_FEATURE_MASK (0xFFFFU) +#define I2S_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard feature set. + */ +#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) +#define I2S_VERID_MINOR_MASK (0xFF0000U) +#define I2S_VERID_MINOR_SHIFT (16U) +#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) +#define I2S_VERID_MAJOR_MASK (0xFF000000U) +#define I2S_VERID_MAJOR_SHIFT (24U) +#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define I2S_PARAM_DATALINE_MASK (0xFU) +#define I2S_PARAM_DATALINE_SHIFT (0U) +#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) +#define I2S_PARAM_FIFO_MASK (0xF00U) +#define I2S_PARAM_FIFO_SHIFT (8U) +#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) +#define I2S_PARAM_FRAME_MASK (0xF0000U) +#define I2S_PARAM_FRAME_SHIFT (16U) +#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) +/*! @} */ + +/*! @name TCSR - SAI Transmit Control Register */ +/*! @{ */ +#define I2S_TCSR_FRDE_MASK (0x1U) +#define I2S_TCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) +#define I2S_TCSR_FWDE_MASK (0x2U) +#define I2S_TCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) +#define I2S_TCSR_FRIE_MASK (0x100U) +#define I2S_TCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) +#define I2S_TCSR_FWIE_MASK (0x200U) +#define I2S_TCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) +#define I2S_TCSR_FEIE_MASK (0x400U) +#define I2S_TCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) +#define I2S_TCSR_SEIE_MASK (0x800U) +#define I2S_TCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) +#define I2S_TCSR_WSIE_MASK (0x1000U) +#define I2S_TCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) +#define I2S_TCSR_FRF_MASK (0x10000U) +#define I2S_TCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Transmit FIFO watermark has not been reached. + * 0b1..Transmit FIFO watermark has been reached. + */ +#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) +#define I2S_TCSR_FWF_MASK (0x20000U) +#define I2S_TCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..No enabled transmit FIFO is empty. + * 0b1..Enabled transmit FIFO is empty. + */ +#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) +#define I2S_TCSR_FEF_MASK (0x40000U) +#define I2S_TCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Transmit underrun not detected. + * 0b1..Transmit underrun detected. + */ +#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) +#define I2S_TCSR_SEF_MASK (0x80000U) +#define I2S_TCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Sync error not detected. + * 0b1..Frame sync error detected. + */ +#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) +#define I2S_TCSR_WSF_MASK (0x100000U) +#define I2S_TCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Start of word not detected. + * 0b1..Start of word detected. + */ +#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) +#define I2S_TCSR_SR_MASK (0x1000000U) +#define I2S_TCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect. + * 0b1..Software reset. + */ +#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) +#define I2S_TCSR_FR_MASK (0x2000000U) +#define I2S_TCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect. + * 0b1..FIFO reset. + */ +#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) +#define I2S_TCSR_BCE_MASK (0x10000000U) +#define I2S_TCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Transmit bit clock is disabled. + * 0b1..Transmit bit clock is enabled. + */ +#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) +#define I2S_TCSR_DBGE_MASK (0x20000000U) +#define I2S_TCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Transmitter is disabled in Debug mode, after completing the current frame. + * 0b1..Transmitter is enabled in Debug mode. + */ +#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) +#define I2S_TCSR_STOPE_MASK (0x40000000U) +#define I2S_TCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Transmitter disabled in Stop mode. + * 0b1..Transmitter enabled in Stop mode. + */ +#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) +#define I2S_TCSR_TE_MASK (0x80000000U) +#define I2S_TCSR_TE_SHIFT (31U) +/*! TE - Transmitter Enable + * 0b0..Transmitter is disabled. + * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. + */ +#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) +/*! @} */ + +/*! @name TCR1 - SAI Transmit Configuration 1 Register */ +/*! @{ */ +#define I2S_TCR1_TFW_MASK (0x1FU) +#define I2S_TCR1_TFW_SHIFT (0U) +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) +/*! @} */ + +/*! @name TCR2 - SAI Transmit Configuration 2 Register */ +/*! @{ */ +#define I2S_TCR2_DIV_MASK (0xFFU) +#define I2S_TCR2_DIV_SHIFT (0U) +#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) +#define I2S_TCR2_BCD_MASK (0x1000000U) +#define I2S_TCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Bit clock is generated externally in Slave mode. + * 0b1..Bit clock is generated internally in Master mode. + */ +#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) +#define I2S_TCR2_BCP_MASK (0x2000000U) +#define I2S_TCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. + * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + */ +#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) +#define I2S_TCR2_MSEL_MASK (0xC000000U) +#define I2S_TCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus Clock selected. + * 0b01..Master Clock (MCLK) 1 option selected. + * 0b10..Master Clock (MCLK) 2 option selected. + * 0b11..Master Clock (MCLK) 3 option selected. + */ +#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) +#define I2S_TCR2_BCI_MASK (0x10000000U) +#define I2S_TCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..No effect. + * 0b1..Internal logic is clocked as if bit clock was externally generated. + */ +#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) +#define I2S_TCR2_BCS_MASK (0x20000000U) +#define I2S_TCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source. + * 0b1..Swap the bit clock source. + */ +#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) +#define I2S_TCR2_SYNC_MASK (0xC0000000U) +#define I2S_TCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode. + * 0b01..Synchronous with receiver. + * 0b10..Reserved. + * 0b11..Reserved. + */ +#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) +/*! @} */ + +/*! @name TCR3 - SAI Transmit Configuration 3 Register */ +/*! @{ */ +#define I2S_TCR3_WDFL_MASK (0x1FU) +#define I2S_TCR3_WDFL_SHIFT (0U) +#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) +#define I2S_TCR3_TCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ +#define I2S_TCR3_TCE_SHIFT (16U) +#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ +#define I2S_TCR3_CFR_MASK (0xF000000U) +#define I2S_TCR3_CFR_SHIFT (24U) +#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) +/*! @} */ + +/*! @name TCR4 - SAI Transmit Configuration 4 Register */ +/*! @{ */ +#define I2S_TCR4_FSD_MASK (0x1U) +#define I2S_TCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Frame sync is generated externally in Slave mode. + * 0b1..Frame sync is generated internally in Master mode. + */ +#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) +#define I2S_TCR4_FSP_MASK (0x2U) +#define I2S_TCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Frame sync is active high. + * 0b1..Frame sync is active low. + */ +#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) +#define I2S_TCR4_ONDEM_MASK (0x4U) +#define I2S_TCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On Demand Mode + * 0b0..Internal frame sync is generated continuously. + * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. + */ +#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) +#define I2S_TCR4_FSE_MASK (0x8U) +#define I2S_TCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..Frame sync asserts with the first bit of the frame. + * 0b1..Frame sync asserts one bit before the first bit of the frame. + */ +#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) +#define I2S_TCR4_MF_MASK (0x10U) +#define I2S_TCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB is transmitted first. + * 0b1..MSB is transmitted first. + */ +#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) +#define I2S_TCR4_CHMOD_MASK (0x20U) +#define I2S_TCR4_CHMOD_SHIFT (5U) +/*! CHMOD - Channel Mode + * 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. + * 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. + */ +#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) +#define I2S_TCR4_SYWD_MASK (0x1F00U) +#define I2S_TCR4_SYWD_SHIFT (8U) +#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) +#define I2S_TCR4_FRSZ_MASK (0x1F0000U) +#define I2S_TCR4_FRSZ_SHIFT (16U) +#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) +#define I2S_TCR4_FPACK_MASK (0x3000000U) +#define I2S_TCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..FIFO packing is disabled + * 0b01..Reserved + * 0b10..8-bit FIFO packing is enabled + * 0b11..16-bit FIFO packing is enabled + */ +#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) +#define I2S_TCR4_FCOMB_MASK (0xC000000U) +#define I2S_TCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..FIFO combine mode disabled. + * 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers). + * 0b10..FIFO combine mode enabled on FIFO writes (by software). + * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). + */ +#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) +#define I2S_TCR4_FCONT_MASK (0x10000000U) +#define I2S_TCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + */ +#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) +/*! @} */ + +/*! @name TCR5 - SAI Transmit Configuration 5 Register */ +/*! @{ */ +#define I2S_TCR5_FBT_MASK (0x1F00U) +#define I2S_TCR5_FBT_SHIFT (8U) +#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) +#define I2S_TCR5_W0W_MASK (0x1F0000U) +#define I2S_TCR5_W0W_SHIFT (16U) +#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) +#define I2S_TCR5_WNW_MASK (0x1F000000U) +#define I2S_TCR5_WNW_SHIFT (24U) +#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) +/*! @} */ + +/*! @name TDR - SAI Transmit Data Register */ +/*! @{ */ +#define I2S_TDR_TDR_MASK (0xFFFFFFFFU) +#define I2S_TDR_TDR_SHIFT (0U) +#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK) +/*! @} */ + +/* The count of I2S_TDR */ +#define I2S_TDR_COUNT (4U) + +/*! @name TFR - SAI Transmit FIFO Register */ +/*! @{ */ +#define I2S_TFR_RFP_MASK (0x3FU) +#define I2S_TFR_RFP_SHIFT (0U) +#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) +#define I2S_TFR_WFP_MASK (0x3F0000U) +#define I2S_TFR_WFP_SHIFT (16U) +#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) +#define I2S_TFR_WCP_MASK (0x80000000U) +#define I2S_TFR_WCP_SHIFT (31U) +/*! WCP - Write Channel Pointer + * 0b0..No effect. + * 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. + */ +#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK) +/*! @} */ + +/* The count of I2S_TFR */ +#define I2S_TFR_COUNT (4U) + +/*! @name TMR - SAI Transmit Mask Register */ +/*! @{ */ +#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) +#define I2S_TMR_TWM_SHIFT (0U) +/*! TWM - Transmit Word Mask + * 0b00000000000000000000000000000000..Word N is enabled. + * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked. + */ +#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) +/*! @} */ + +/*! @name RCSR - SAI Receive Control Register */ +/*! @{ */ +#define I2S_RCSR_FRDE_MASK (0x1U) +#define I2S_RCSR_FRDE_SHIFT (0U) +/*! FRDE - FIFO Request DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) +#define I2S_RCSR_FWDE_MASK (0x2U) +#define I2S_RCSR_FWDE_SHIFT (1U) +/*! FWDE - FIFO Warning DMA Enable + * 0b0..Disables the DMA request. + * 0b1..Enables the DMA request. + */ +#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) +#define I2S_RCSR_FRIE_MASK (0x100U) +#define I2S_RCSR_FRIE_SHIFT (8U) +/*! FRIE - FIFO Request Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) +#define I2S_RCSR_FWIE_MASK (0x200U) +#define I2S_RCSR_FWIE_SHIFT (9U) +/*! FWIE - FIFO Warning Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) +#define I2S_RCSR_FEIE_MASK (0x400U) +#define I2S_RCSR_FEIE_SHIFT (10U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disables the interrupt. + * 0b1..Enables the interrupt. + */ +#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) +#define I2S_RCSR_SEIE_MASK (0x800U) +#define I2S_RCSR_SEIE_SHIFT (11U) +/*! SEIE - Sync Error Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) +#define I2S_RCSR_WSIE_MASK (0x1000U) +#define I2S_RCSR_WSIE_SHIFT (12U) +/*! WSIE - Word Start Interrupt Enable + * 0b0..Disables interrupt. + * 0b1..Enables interrupt. + */ +#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) +#define I2S_RCSR_FRF_MASK (0x10000U) +#define I2S_RCSR_FRF_SHIFT (16U) +/*! FRF - FIFO Request Flag + * 0b0..Receive FIFO watermark not reached. + * 0b1..Receive FIFO watermark has been reached. + */ +#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) +#define I2S_RCSR_FWF_MASK (0x20000U) +#define I2S_RCSR_FWF_SHIFT (17U) +/*! FWF - FIFO Warning Flag + * 0b0..No enabled receive FIFO is full. + * 0b1..Enabled receive FIFO is full. + */ +#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) +#define I2S_RCSR_FEF_MASK (0x40000U) +#define I2S_RCSR_FEF_SHIFT (18U) +/*! FEF - FIFO Error Flag + * 0b0..Receive overflow not detected. + * 0b1..Receive overflow detected. + */ +#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) +#define I2S_RCSR_SEF_MASK (0x80000U) +#define I2S_RCSR_SEF_SHIFT (19U) +/*! SEF - Sync Error Flag + * 0b0..Sync error not detected. + * 0b1..Frame sync error detected. + */ +#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) +#define I2S_RCSR_WSF_MASK (0x100000U) +#define I2S_RCSR_WSF_SHIFT (20U) +/*! WSF - Word Start Flag + * 0b0..Start of word not detected. + * 0b1..Start of word detected. + */ +#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) +#define I2S_RCSR_SR_MASK (0x1000000U) +#define I2S_RCSR_SR_SHIFT (24U) +/*! SR - Software Reset + * 0b0..No effect. + * 0b1..Software reset. + */ +#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) +#define I2S_RCSR_FR_MASK (0x2000000U) +#define I2S_RCSR_FR_SHIFT (25U) +/*! FR - FIFO Reset + * 0b0..No effect. + * 0b1..FIFO reset. + */ +#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) +#define I2S_RCSR_BCE_MASK (0x10000000U) +#define I2S_RCSR_BCE_SHIFT (28U) +/*! BCE - Bit Clock Enable + * 0b0..Receive bit clock is disabled. + * 0b1..Receive bit clock is enabled. + */ +#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) +#define I2S_RCSR_DBGE_MASK (0x20000000U) +#define I2S_RCSR_DBGE_SHIFT (29U) +/*! DBGE - Debug Enable + * 0b0..Receiver is disabled in Debug mode, after completing the current frame. + * 0b1..Receiver is enabled in Debug mode. + */ +#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) +#define I2S_RCSR_STOPE_MASK (0x40000000U) +#define I2S_RCSR_STOPE_SHIFT (30U) +/*! STOPE - Stop Enable + * 0b0..Receiver disabled in Stop mode. + * 0b1..Receiver enabled in Stop mode. + */ +#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) +#define I2S_RCSR_RE_MASK (0x80000000U) +#define I2S_RCSR_RE_SHIFT (31U) +/*! RE - Receiver Enable + * 0b0..Receiver is disabled. + * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. + */ +#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) +/*! @} */ + +/*! @name RCR1 - SAI Receive Configuration 1 Register */ +/*! @{ */ +#define I2S_RCR1_RFW_MASK (0x1FU) +#define I2S_RCR1_RFW_SHIFT (0U) +#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) +/*! @} */ + +/*! @name RCR2 - SAI Receive Configuration 2 Register */ +/*! @{ */ +#define I2S_RCR2_DIV_MASK (0xFFU) +#define I2S_RCR2_DIV_SHIFT (0U) +#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) +#define I2S_RCR2_BCD_MASK (0x1000000U) +#define I2S_RCR2_BCD_SHIFT (24U) +/*! BCD - Bit Clock Direction + * 0b0..Bit clock is generated externally in Slave mode. + * 0b1..Bit clock is generated internally in Master mode. + */ +#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) +#define I2S_RCR2_BCP_MASK (0x2000000U) +#define I2S_RCR2_BCP_SHIFT (25U) +/*! BCP - Bit Clock Polarity + * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. + * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. + */ +#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) +#define I2S_RCR2_MSEL_MASK (0xC000000U) +#define I2S_RCR2_MSEL_SHIFT (26U) +/*! MSEL - MCLK Select + * 0b00..Bus Clock selected. + * 0b01..Master Clock (MCLK) 1 option selected. + * 0b10..Master Clock (MCLK) 2 option selected. + * 0b11..Master Clock (MCLK) 3 option selected. + */ +#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) +#define I2S_RCR2_BCI_MASK (0x10000000U) +#define I2S_RCR2_BCI_SHIFT (28U) +/*! BCI - Bit Clock Input + * 0b0..No effect. + * 0b1..Internal logic is clocked as if bit clock was externally generated. + */ +#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) +#define I2S_RCR2_BCS_MASK (0x20000000U) +#define I2S_RCR2_BCS_SHIFT (29U) +/*! BCS - Bit Clock Swap + * 0b0..Use the normal bit clock source. + * 0b1..Swap the bit clock source. + */ +#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) +#define I2S_RCR2_SYNC_MASK (0xC0000000U) +#define I2S_RCR2_SYNC_SHIFT (30U) +/*! SYNC - Synchronous Mode + * 0b00..Asynchronous mode. + * 0b01..Synchronous with transmitter. + * 0b10..Reserved. + * 0b11..Reserved. + */ +#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) +/*! @} */ + +/*! @name RCR3 - SAI Receive Configuration 3 Register */ +/*! @{ */ +#define I2S_RCR3_WDFL_MASK (0x1FU) +#define I2S_RCR3_WDFL_SHIFT (0U) +#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) +#define I2S_RCR3_RCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ +#define I2S_RCR3_RCE_SHIFT (16U) +#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ +#define I2S_RCR3_CFR_MASK (0xF000000U) +#define I2S_RCR3_CFR_SHIFT (24U) +#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) +/*! @} */ + +/*! @name RCR4 - SAI Receive Configuration 4 Register */ +/*! @{ */ +#define I2S_RCR4_FSD_MASK (0x1U) +#define I2S_RCR4_FSD_SHIFT (0U) +/*! FSD - Frame Sync Direction + * 0b0..Frame Sync is generated externally in Slave mode. + * 0b1..Frame Sync is generated internally in Master mode. + */ +#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) +#define I2S_RCR4_FSP_MASK (0x2U) +#define I2S_RCR4_FSP_SHIFT (1U) +/*! FSP - Frame Sync Polarity + * 0b0..Frame sync is active high. + * 0b1..Frame sync is active low. + */ +#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) +#define I2S_RCR4_ONDEM_MASK (0x4U) +#define I2S_RCR4_ONDEM_SHIFT (2U) +/*! ONDEM - On Demand Mode + * 0b0..Internal frame sync is generated continuously. + * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. + */ +#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) +#define I2S_RCR4_FSE_MASK (0x8U) +#define I2S_RCR4_FSE_SHIFT (3U) +/*! FSE - Frame Sync Early + * 0b0..Frame sync asserts with the first bit of the frame. + * 0b1..Frame sync asserts one bit before the first bit of the frame. + */ +#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) +#define I2S_RCR4_MF_MASK (0x10U) +#define I2S_RCR4_MF_SHIFT (4U) +/*! MF - MSB First + * 0b0..LSB is received first. + * 0b1..MSB is received first. + */ +#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) +#define I2S_RCR4_SYWD_MASK (0x1F00U) +#define I2S_RCR4_SYWD_SHIFT (8U) +#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) +#define I2S_RCR4_FRSZ_MASK (0x1F0000U) +#define I2S_RCR4_FRSZ_SHIFT (16U) +#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) +#define I2S_RCR4_FPACK_MASK (0x3000000U) +#define I2S_RCR4_FPACK_SHIFT (24U) +/*! FPACK - FIFO Packing Mode + * 0b00..FIFO packing is disabled + * 0b01..Reserved. + * 0b10..8-bit FIFO packing is enabled + * 0b11..16-bit FIFO packing is enabled + */ +#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) +#define I2S_RCR4_FCOMB_MASK (0xC000000U) +#define I2S_RCR4_FCOMB_SHIFT (26U) +/*! FCOMB - FIFO Combine Mode + * 0b00..FIFO combine mode disabled. + * 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers). + * 0b10..FIFO combine mode enabled on FIFO reads (by software). + * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). + */ +#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) +#define I2S_RCR4_FCONT_MASK (0x10000000U) +#define I2S_RCR4_FCONT_SHIFT (28U) +/*! FCONT - FIFO Continue on Error + * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + */ +#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) +/*! @} */ + +/*! @name RCR5 - SAI Receive Configuration 5 Register */ +/*! @{ */ +#define I2S_RCR5_FBT_MASK (0x1F00U) +#define I2S_RCR5_FBT_SHIFT (8U) +#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) +#define I2S_RCR5_W0W_MASK (0x1F0000U) +#define I2S_RCR5_W0W_SHIFT (16U) +#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) +#define I2S_RCR5_WNW_MASK (0x1F000000U) +#define I2S_RCR5_WNW_SHIFT (24U) +#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) +/*! @} */ + +/*! @name RDR - SAI Receive Data Register */ +/*! @{ */ +#define I2S_RDR_RDR_MASK (0xFFFFFFFFU) +#define I2S_RDR_RDR_SHIFT (0U) +#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK) +/*! @} */ + +/* The count of I2S_RDR */ +#define I2S_RDR_COUNT (4U) + +/*! @name RFR - SAI Receive FIFO Register */ +/*! @{ */ +#define I2S_RFR_RFP_MASK (0x3FU) +#define I2S_RFR_RFP_SHIFT (0U) +#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) +#define I2S_RFR_RCP_MASK (0x8000U) +#define I2S_RFR_RCP_SHIFT (15U) +/*! RCP - Receive Channel Pointer + * 0b0..No effect. + * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. + */ +#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) +#define I2S_RFR_WFP_MASK (0x3F0000U) +#define I2S_RFR_WFP_SHIFT (16U) +#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK) +/*! @} */ + +/* The count of I2S_RFR */ +#define I2S_RFR_COUNT (4U) + +/*! @name RMR - SAI Receive Mask Register */ +/*! @{ */ +#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) +#define I2S_RMR_RWM_SHIFT (0U) +/*! RWM - Receive Word Mask + * 0b00000000000000000000000000000000..Word N is enabled. + * 0b00000000000000000000000000000001..Word N is masked. + */ +#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral SAI1 base address */ +#define SAI1_BASE (0x40384000u) +/** Peripheral SAI1 base pointer */ +#define SAI1 ((I2S_Type *)SAI1_BASE) +/** Peripheral SAI2 base address */ +#define SAI2_BASE (0x40388000u) +/** Peripheral SAI2 base pointer */ +#define SAI2 ((I2S_Type *)SAI2_BASE) +/** Peripheral SAI3 base address */ +#define SAI3_BASE (0x4038C000u) +/** Peripheral SAI3 base pointer */ +#define SAI3 ((I2S_Type *)SAI3_BASE) +/** Array initializer of I2S peripheral base addresses */ +#define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3 } +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn } +#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer + * @{ + */ + +/** IOMUXC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[20]; + __IO uint32_t SW_MUX_CTL_PAD[124]; /**< SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register, array offset: 0x14, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_PAD[124]; /**< SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register, array offset: 0x204, array step: 0x4 */ + __IO uint32_t SELECT_INPUT[154]; /**< ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register, array offset: 0x3F4, array step: 0x4 */ + __IO uint32_t SW_MUX_CTL_PAD_1[22]; /**< SW_MUX_CTL_PAD_GPIO_SPI_B0_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SPI_B1_07 SW MUX Control Register, array offset: 0x65C, array step: 0x4 */ + __IO uint32_t SW_PAD_CTL_PAD_1[22]; /**< SW_PAD_CTL_PAD_GPIO_SPI_B0_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SPI_B1_07 SW PAD Control Register, array offset: 0x6B4, array step: 0x4 */ + __IO uint32_t SELECT_INPUT_1[33]; /**< ENET2_IPG_CLK_RMII_SELECT_INPUT DAISY Register..CANFD_IPP_IND_CANRX_SELECT_INPUT DAISY Register, array offset: 0x70C, array step: 0x4 */ +} IOMUXC_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register */ +/*! @{ */ +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: SEMC_DATA00 of instance: semc + * 0b001..Select mux mode: ALT1 mux port: FLEXPWM4_PWMA00 of instance: flexpwm4 + * 0b010..Select mux mode: ALT2 mux port: LPSPI2_SCK of instance: lpspi2 + * 0b011..Select mux mode: ALT3 mux port: XBAR1_XBAR_IN02 of instance: xbar1 + * 0b100..Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO00 of instance: flexio1 + * 0b101..Select mux mode: ALT5 mux port: GPIO4_IO00 of instance: gpio4 + */ +#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) /* Merged from fields with different position or width, of widths (3, 4), largest definition used */ +#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) +#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad GPIO_EMC_00 + * 0b0..Input Path is determined by functionality + */ +#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK) +/*! @} */ + +/* The count of IOMUXC_SW_MUX_CTL_PAD */ +#define IOMUXC_SW_MUX_CTL_PAD_COUNT (124U) + +/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U) +#define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x38U) +#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK (0xC0U) +#define IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b00..low(50MHz) + * 0b01..medium(100MHz) + * 0b10..medium(100MHz) + * 0b11..max(200MHz) + */ +#define IOMUXC_SW_PAD_CTL_PAD_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x800U) +#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PKE_MASK (0x1000U) +#define IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PKE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x2000U) +#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0xC000U) +#define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x10000U) +#define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK) +/*! @} */ + +/* The count of IOMUXC_SW_PAD_CTL_PAD */ +#define IOMUXC_SW_PAD_CTL_PAD_COUNT (124U) + +/*! @name SELECT_INPUT - ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register..XBAR1_IN23_SELECT_INPUT DAISY Register */ +/*! @{ */ +#define IOMUXC_SELECT_INPUT_DAISY_MASK (0x7U) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ +#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) +/*! DAISY - Selecting Pads Involved in Daisy Chain. + * 0b0..Selecting Pad: GPIO_AD_B0_01 for Mode: ALT3 + * 0b1..Selecting Pad: GPIO_AD_B1_02 for Mode: ALT0 + */ +#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3), largest definition used */ +/*! @} */ + +/* The count of IOMUXC_SELECT_INPUT */ +#define IOMUXC_SELECT_INPUT_COUNT (154U) + +/*! @name SW_MUX_CTL_PAD_1 - SW_MUX_CTL_PAD_GPIO_SPI_B0_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_SPI_B1_07 SW MUX Control Register */ +/*! @{ */ +#define IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_MASK (0x7U) +#define IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: FLEXSPI2_B_SCLK of instance: flexspi2 + */ +#define IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_1_MUX_MODE_MASK) +#define IOMUXC_SW_MUX_CTL_PAD_1_SION_MASK (0x10U) +#define IOMUXC_SW_MUX_CTL_PAD_1_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad GPIO_SPI_B0_00 + * 0b0..Input Path is determined by functionality + */ +#define IOMUXC_SW_MUX_CTL_PAD_1_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_1_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_1_SION_MASK) +/*! @} */ + +/* The count of IOMUXC_SW_MUX_CTL_PAD_1 */ +#define IOMUXC_SW_MUX_CTL_PAD_1_COUNT (22U) + +/*! @name SW_PAD_CTL_PAD_1 - SW_PAD_CTL_PAD_GPIO_SPI_B0_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_SPI_B1_07 SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SW_PAD_CTL_PAD_1_SRE_MASK (0x1U) +#define IOMUXC_SW_PAD_CTL_PAD_1_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SW_PAD_CTL_PAD_1_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_SRE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_1_DSE_MASK (0x38U) +#define IOMUXC_SW_PAD_CTL_PAD_1_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SW_PAD_CTL_PAD_1_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_DSE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_1_SPEED_MASK (0xC0U) +#define IOMUXC_SW_PAD_CTL_PAD_1_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b00..low(50MHz) + * 0b01..medium(100MHz) + * 0b10..medium(100MHz) + * 0b11..max(200MHz) + */ +#define IOMUXC_SW_PAD_CTL_PAD_1_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_SPEED_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_SPEED_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_1_ODE_MASK (0x800U) +#define IOMUXC_SW_PAD_CTL_PAD_1_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_1_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_ODE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_1_PKE_MASK (0x1000U) +#define IOMUXC_SW_PAD_CTL_PAD_1_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_1_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_PKE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_PKE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_1_PUE_MASK (0x2000U) +#define IOMUXC_SW_PAD_CTL_PAD_1_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SW_PAD_CTL_PAD_1_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_PUE_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_1_PUS_MASK (0xC000U) +#define IOMUXC_SW_PAD_CTL_PAD_1_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SW_PAD_CTL_PAD_1_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_PUS_MASK) +#define IOMUXC_SW_PAD_CTL_PAD_1_HYS_MASK (0x10000U) +#define IOMUXC_SW_PAD_CTL_PAD_1_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SW_PAD_CTL_PAD_1_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_1_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_1_HYS_MASK) +/*! @} */ + +/* The count of IOMUXC_SW_PAD_CTL_PAD_1 */ +#define IOMUXC_SW_PAD_CTL_PAD_1_COUNT (22U) + +/*! @name SELECT_INPUT_1 - ENET2_IPG_CLK_RMII_SELECT_INPUT DAISY Register..CANFD_IPP_IND_CANRX_SELECT_INPUT DAISY Register */ +/*! @{ */ +#define IOMUXC_SELECT_INPUT_1_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ +#define IOMUXC_SELECT_INPUT_1_DAISY_SHIFT (0U) +/*! DAISY - Selecting Pads Involved in Daisy Chain. + * 0b00..Selecting Pad: GPIO_EMC_33 for Mode: ALT9 + * 0b01..Selecting Pad: GPIO_SD_B0_01 for Mode: ALT9 + * 0b10..Selecting Pad: GPIO_B0_15 for Mode: ALT9 + */ +#define IOMUXC_SELECT_INPUT_1_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_1_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_1_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ +/*! @} */ + +/* The count of IOMUXC_SELECT_INPUT_1 */ +#define IOMUXC_SELECT_INPUT_1_COUNT (33U) + + +/*! + * @} + */ /* end of group IOMUXC_Register_Masks */ + + +/* IOMUXC - Peripheral instance base addresses */ +/** Peripheral IOMUXC base address */ +#define IOMUXC_BASE (0x401F8000u) +/** Peripheral IOMUXC base pointer */ +#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE) +/** Array initializer of IOMUXC peripheral base addresses */ +#define IOMUXC_BASE_ADDRS { IOMUXC_BASE } +/** Array initializer of IOMUXC peripheral base pointers */ +#define IOMUXC_BASE_PTRS { IOMUXC } + +/*! + * @} + */ /* end of group IOMUXC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_GPR - Register Layout Typedef */ +typedef struct { + uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ + __IO uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */ + __IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ + __IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */ + __IO uint32_t GPR4; /**< GPR4 General Purpose Register, offset: 0x10 */ + __IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset: 0x14 */ + __IO uint32_t GPR6; /**< GPR6 General Purpose Register, offset: 0x18 */ + __IO uint32_t GPR7; /**< GPR7 General Purpose Register, offset: 0x1C */ + __IO uint32_t GPR8; /**< GPR8 General Purpose Register, offset: 0x20 */ + uint32_t GPR9; /**< GPR9 General Purpose Register, offset: 0x24 */ + __IO uint32_t GPR10; /**< GPR10 General Purpose Register, offset: 0x28 */ + __IO uint32_t GPR11; /**< GPR11 General Purpose Register, offset: 0x2C */ + __IO uint32_t GPR12; /**< GPR12 General Purpose Register, offset: 0x30 */ + __IO uint32_t GPR13; /**< GPR13 General Purpose Register, offset: 0x34 */ + __IO uint32_t GPR14; /**< GPR14 General Purpose Register, offset: 0x38 */ + uint32_t GPR15; /**< GPR15 General Purpose Register, offset: 0x3C */ + __IO uint32_t GPR16; /**< GPR16 General Purpose Register, offset: 0x40 */ + __IO uint32_t GPR17; /**< GPR17 General Purpose Register, offset: 0x44 */ + __IO uint32_t GPR18; /**< GPR18 General Purpose Register, offset: 0x48 */ + __IO uint32_t GPR19; /**< GPR19 General Purpose Register, offset: 0x4C */ + __IO uint32_t GPR20; /**< GPR20 General Purpose Register, offset: 0x50 */ + __IO uint32_t GPR21; /**< GPR21 General Purpose Register, offset: 0x54 */ + __IO uint32_t GPR22; /**< GPR22 General Purpose Register, offset: 0x58 */ + __IO uint32_t GPR23; /**< GPR23 General Purpose Register, offset: 0x5C */ + __IO uint32_t GPR24; /**< GPR24 General Purpose Register, offset: 0x60 */ + __IO uint32_t GPR25; /**< GPR25 General Purpose Register, offset: 0x64 */ + __IO uint32_t GPR26; /**< GPR26 General Purpose Register, offset: 0x68 */ + __IO uint32_t GPR27; /**< GPR27 General Purpose Register, offset: 0x6C */ + __IO uint32_t GPR28; /**< GPR28 General Purpose Register, offset: 0x70 */ + __IO uint32_t GPR29; /**< GPR29 General Purpose Register, offset: 0x74 */ + __IO uint32_t GPR30; /**< GPR30 General Purpose Register, offset: 0x78 */ + __IO uint32_t GPR31; /**< GPR31 General Purpose Register, offset: 0x7C */ + __IO uint32_t GPR32; /**< GPR32 General Purpose Register, offset: 0x80 */ + __IO uint32_t GPR33; /**< GPR33 General Purpose Register, offset: 0x84 */ + __IO uint32_t GPR34; /**< GPR34 General Purpose Register, offset: 0x88 */ +} IOMUXC_GPR_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks + * @{ + */ + +/*! @name GPR1 - GPR1 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK (0x7U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0U) +/*! SAI1_MCLK1_SEL + * 0b000..ccm.ssi1_clk_root + * 0b001..ccm.ssi2_clk_root + * 0b010..ccm.ssi3_clk_root + * 0b011..iomux.sai1_ipg_clk_sai_mclk + * 0b100..iomux.sai2_ipg_clk_sai_mclk + * 0b101..iomux.sai3_ipg_clk_sai_mclk + * 0b110..Reserved + * 0b111..Reserved + */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK (0x38U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3U) +/*! SAI1_MCLK2_SEL + * 0b000..ccm.ssi1_clk_root + * 0b001..ccm.ssi2_clk_root + * 0b010..ccm.ssi3_clk_root + * 0b011..iomux.sai1_ipg_clk_sai_mclk + * 0b100..iomux.sai2_ipg_clk_sai_mclk + * 0b101..iomux.sai3_ipg_clk_sai_mclk + * 0b110..Reserved + * 0b111..Reserved + */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK (0xC0U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6U) +/*! SAI1_MCLK3_SEL + * 0b00..ccm.spdif0_clk_root + * 0b01..iomux.spdif_tx_clk2 + * 0b10..spdif.spdif_srclk + * 0b11..spdif.spdif_outclock + */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x300U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8U) +/*! SAI2_MCLK3_SEL + * 0b00..ccm.spdif0_clk_root + * 0b01..iomux.spdif_tx_clk2 + * 0b10..spdif.spdif_srclk + * 0b11..spdif.spdif_outclock + */ +#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK) +#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK (0xC00U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10U) +/*! SAI3_MCLK3_SEL + * 0b00..ccm.spdif0_clk_root + * 0b01..iomux.spdif_tx_clk2 + * 0b10..spdif.spdif_srclk + * 0b11..spdif.spdif_outclock + */ +#define IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK) +#define IOMUXC_GPR_GPR1_GINT_MASK (0x1000U) +#define IOMUXC_GPR_GPR1_GINT_SHIFT (12U) +/*! GINT + * 0b0..Global interrupt request is not asserted. + * 0b1..Global interrupt request is asserted. + */ +#define IOMUXC_GPR_GPR1_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GINT_SHIFT)) & IOMUXC_GPR_GPR1_GINT_MASK) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK (0x2000U) +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT (13U) +/*! ENET1_CLK_SEL + * 0b0..ENET1 TX reference clock driven by ref_enetpll. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function. + * 0b1..Gets ENET1 TX reference clock from the ENET1_TX_CLK pin. In this use case, an external OSC provides the + * clock for both the external PHY and the internal controller. + */ +#define IOMUXC_GPR_GPR1_ENET1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK) +#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK (0x4000U) +#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT (14U) +/*! ENET2_CLK_SEL + * 0b0..ENET2 TX reference clock driven by ref_enetpll. This clock is also output to pins via the IOMUX. ENET2_REF_CLK function. + * 0b1..Gets ENET2 TX reference clock from the ENET2_TX_CLK pin. In this use case, an external OSC provides the + * clock for both the external PHY and the internal controller. + */ +#define IOMUXC_GPR_GPR1_ENET2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK (0x8000U) +#define IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT (15U) +/*! USB_EXP_MODE + * 0b0..Exposure mode is disabled. + * 0b1..Exposure mode is enabled. + */ +#define IOMUXC_GPR_GPR1_USB_EXP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_USB_EXP_MODE_SHIFT)) & IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK (0x20000U) +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT (17U) +/*! ENET1_TX_CLK_DIR + * 0b0..ENET1_TX_CLK output driver is disabled + * 0b1..ENET1_TX_CLK output driver is enabled + */ +#define IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK (0x40000U) +#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT (18U) +/*! ENET2_TX_CLK_DIR + * 0b0..ENET2_TX_CLK output driver is disabled + * 0b1..ENET2_TX_CLK output driver is enabled + */ +#define IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK (0x80000U) +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT (19U) +/*! SAI1_MCLK_DIR + * 0b0..sai1.MCLK is input signal + * 0b1..sai1.MCLK is output signal + */ +#define IOMUXC_GPR_GPR1_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100000U) +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (20U) +/*! SAI2_MCLK_DIR + * 0b0..sai2.MCLK is input signal + * 0b1..sai2.MCLK is output signal + */ +#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK (0x200000U) +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT (21U) +/*! SAI3_MCLK_DIR + * 0b0..sai3.MCLK is input signal + * 0b1..sai3.MCLK is output signal + */ +#define IOMUXC_GPR_GPR1_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK) +#define IOMUXC_GPR_GPR1_EXC_MON_MASK (0x400000U) +#define IOMUXC_GPR_GPR1_EXC_MON_SHIFT (22U) +/*! EXC_MON + * 0b0..OKAY response + * 0b1..SLVError response (default) + */ +#define IOMUXC_GPR_GPR1_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR1_EXC_MON_MASK) +#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK (0x800000U) +#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT (23U) +/*! ENET_IPG_CLK_S_EN + * 0b0..ipg_clk_s is gated when there is no IPS access + * 0b1..ipg_clk_s is always on + */ +#define IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_SHIFT)) & IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK) +#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK (0x80000000U) +#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT (31U) +/*! CM7_FORCE_HCLK_EN + * 0b0..AHB clock is not running (gated) + * 0b1..AHB clock is running (enabled) + */ +#define IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK) +/*! @} */ + +/*! @name GPR2 - GPR2 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_MASK (0x1U) +#define IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_SHIFT (0U) +/*! AXBS_L_AHBXL_HIGH_PRIORITY + * 0b0..AXBS_L AHBXL master does not have high priority + * 0b1..AXBS_P AHBXL master has high priority + */ +#define IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY_MASK) +#define IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_MASK (0x2U) +#define IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_SHIFT (1U) +/*! AXBS_L_DMA_HIGH_PRIORITY + * 0b0..AXBS_L DMA master does not have high priority + * 0b1..AXBS_L DMA master has high priority + */ +#define IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY_MASK) +#define IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_MASK (0x4U) +#define IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_SHIFT (2U) +/*! AXBS_L_FORCE_ROUND_ROBIN + * 0b0..AXBS_L masters are not arbitored in round robin, depending on DMA and AHBXL master priority settings. + * 0b1..AXBS_L masters are arbitored in round robin + */ +#define IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN_MASK) +#define IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_MASK (0x8U) +#define IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_SHIFT (3U) +/*! AXBS_P_M0_HIGH_PRIORITY + * 0b0..AXBS_P M0 master doesn't have high priority + * 0b1..AXBS_P M0 master has high priority + */ +#define IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY_MASK) +#define IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_MASK (0x10U) +#define IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_SHIFT (4U) +/*! AXBS_P_M1_HIGH_PRIORITY + * 0b0..AXBS_P M1 master does not have high priority + * 0b1..AXBS_P M1 master has high priority + */ +#define IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY_MASK) +#define IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_MASK (0x20U) +#define IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_SHIFT (5U) +/*! AXBS_P_FORCE_ROUND_ROBIN + * 0b0..AXBS_P masters are not arbitored in round robin, depending on M0/M1 master priority settings. + * 0b1..AXBS_P masters are arbitored in round robin + */ +#define IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_SHIFT)) & IOMUXC_GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN_MASK) +#define IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_MASK (0x40U) +#define IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_SHIFT (6U) +/*! CANFD_FILTER_BYPASS + * 0b0..enable CANFD filter + * 0b1..disable CANFD filter + */ +#define IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_SHIFT)) & IOMUXC_GPR_GPR2_CANFD_FILTER_BYPASS_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK (0x1000U) +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT (12U) +/*! L2_MEM_EN_POWERSAVING + * 0b0..none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect + * 0b1..memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP (priority high to low) to enable power saving levels + */ +#define IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_EN_POWERSAVING_MASK) +#define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK (0x2000U) +#define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT (13U) +/*! RAM_AUTO_CLK_GATING_EN + * 0b0..disable automatically gate off RAM clock + * 0b1..enable automatically gate off RAM clock + */ +#define IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_SHIFT)) & IOMUXC_GPR_GPR2_RAM_AUTO_CLK_GATING_EN_MASK) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK (0x4000U) +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT (14U) +/*! L2_MEM_DEEPSLEEP + * 0b0..no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode + * 0b1..force memory into deep sleep mode + */ +#define IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_SHIFT)) & IOMUXC_GPR_GPR2_L2_MEM_DEEPSLEEP_MASK) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK (0xFF0000U) +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT (16U) +/*! MQS_CLK_DIV - Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency. + * 0b00000000..mclk frequency = 1/1 * hmclk frequency + * 0b00000001..mclk frequency = 1/2 * hmclk frequency + * 0b00000010..mclk frequency = 1/3 * hmclk frequency + * 0b00000011..mclk frequency = 1/4 * hmclk frequency + * 0b00000100..mclk frequency = 1/5 * hmclk frequency + * 0b00000101..mclk frequency = 1/6 * hmclk frequency + * 0b00000110..mclk frequency = 1/7 * hmclk frequency + * 0b00000111..mclk frequency = 1/8 * hmclk frequency + * 0b00001000..mclk frequency = 1/9 * hmclk frequency + * 0b00001001..mclk frequency = 1/10 * hmclk frequency + * 0b00001010..mclk frequency = 1/11 * hmclk frequency + * 0b00001011..mclk frequency = 1/12 * hmclk frequency + * 0b00001100..mclk frequency = 1/13 * hmclk frequency + * 0b00001101..mclk frequency = 1/14 * hmclk frequency + * 0b00001110..mclk frequency = 1/15 * hmclk frequency + * 0b00001111..mclk frequency = 1/16 * hmclk frequency + * 0b00010000..mclk frequency = 1/17 * hmclk frequency + * 0b00010001..mclk frequency = 1/18 * hmclk frequency + * 0b00010010..mclk frequency = 1/19 * hmclk frequency + * 0b00010011..mclk frequency = 1/20 * hmclk frequency + * 0b00010100..mclk frequency = 1/21 * hmclk frequency + * 0b00010101..mclk frequency = 1/22 * hmclk frequency + * 0b00010110..mclk frequency = 1/23 * hmclk frequency + * 0b00010111..mclk frequency = 1/24 * hmclk frequency + * 0b00011000..mclk frequency = 1/25 * hmclk frequency + * 0b00011001..mclk frequency = 1/26 * hmclk frequency + * 0b00011010..mclk frequency = 1/27 * hmclk frequency + * 0b00011011..mclk frequency = 1/28 * hmclk frequency + * 0b00011100..mclk frequency = 1/29 * hmclk frequency + * 0b00011101..mclk frequency = 1/30 * hmclk frequency + * 0b00011110..mclk frequency = 1/31 * hmclk frequency + * 0b00011111..mclk frequency = 1/32 * hmclk frequency + * 0b00100000..mclk frequency = 1/33 * hmclk frequency + * 0b00100001..mclk frequency = 1/34 * hmclk frequency + * 0b00100010..mclk frequency = 1/35 * hmclk frequency + * 0b00100011..mclk frequency = 1/36 * hmclk frequency + * 0b00100100..mclk frequency = 1/37 * hmclk frequency + * 0b00100101..mclk frequency = 1/38 * hmclk frequency + * 0b00100110..mclk frequency = 1/39 * hmclk frequency + * 0b00100111..mclk frequency = 1/40 * hmclk frequency + * 0b00101000..mclk frequency = 1/41 * hmclk frequency + * 0b00101001..mclk frequency = 1/42 * hmclk frequency + * 0b00101010..mclk frequency = 1/43 * hmclk frequency + * 0b00101011..mclk frequency = 1/44 * hmclk frequency + * 0b00101100..mclk frequency = 1/45 * hmclk frequency + * 0b00101101..mclk frequency = 1/46 * hmclk frequency + * 0b00101110..mclk frequency = 1/47 * hmclk frequency + * 0b00101111..mclk frequency = 1/48 * hmclk frequency + * 0b00110000..mclk frequency = 1/49 * hmclk frequency + * 0b00110001..mclk frequency = 1/50 * hmclk frequency + * 0b00110010..mclk frequency = 1/51 * hmclk frequency + * 0b00110011..mclk frequency = 1/52 * hmclk frequency + * 0b00110100..mclk frequency = 1/53 * hmclk frequency + * 0b00110101..mclk frequency = 1/54 * hmclk frequency + * 0b00110110..mclk frequency = 1/55 * hmclk frequency + * 0b00110111..mclk frequency = 1/56 * hmclk frequency + * 0b00111000..mclk frequency = 1/57 * hmclk frequency + * 0b00111001..mclk frequency = 1/58 * hmclk frequency + * 0b00111010..mclk frequency = 1/59 * hmclk frequency + * 0b00111011..mclk frequency = 1/60 * hmclk frequency + * 0b00111100..mclk frequency = 1/61 * hmclk frequency + * 0b00111101..mclk frequency = 1/62 * hmclk frequency + * 0b00111110..mclk frequency = 1/63 * hmclk frequency + * 0b00111111..mclk frequency = 1/64 * hmclk frequency + * 0b01000000..mclk frequency = 1/65 * hmclk frequency + * 0b01000001..mclk frequency = 1/66 * hmclk frequency + * 0b01000010..mclk frequency = 1/67 * hmclk frequency + * 0b01000011..mclk frequency = 1/68 * hmclk frequency + * 0b01000100..mclk frequency = 1/69 * hmclk frequency + * 0b01000101..mclk frequency = 1/70 * hmclk frequency + * 0b01000110..mclk frequency = 1/71 * hmclk frequency + * 0b01000111..mclk frequency = 1/72 * hmclk frequency + * 0b01001000..mclk frequency = 1/73 * hmclk frequency + * 0b01001001..mclk frequency = 1/74 * hmclk frequency + * 0b01001010..mclk frequency = 1/75 * hmclk frequency + * 0b01001011..mclk frequency = 1/76 * hmclk frequency + * 0b01001100..mclk frequency = 1/77 * hmclk frequency + * 0b01001101..mclk frequency = 1/78 * hmclk frequency + * 0b01001110..mclk frequency = 1/79 * hmclk frequency + * 0b01001111..mclk frequency = 1/80 * hmclk frequency + * 0b01010000..mclk frequency = 1/81 * hmclk frequency + * 0b01010001..mclk frequency = 1/82 * hmclk frequency + * 0b01010010..mclk frequency = 1/83 * hmclk frequency + * 0b01010011..mclk frequency = 1/84 * hmclk frequency + * 0b01010100..mclk frequency = 1/85 * hmclk frequency + * 0b01010101..mclk frequency = 1/86 * hmclk frequency + * 0b01010110..mclk frequency = 1/87 * hmclk frequency + * 0b01010111..mclk frequency = 1/88 * hmclk frequency + * 0b01011000..mclk frequency = 1/89 * hmclk frequency + * 0b01011001..mclk frequency = 1/90 * hmclk frequency + * 0b01011010..mclk frequency = 1/91 * hmclk frequency + * 0b01011011..mclk frequency = 1/92 * hmclk frequency + * 0b01011100..mclk frequency = 1/93 * hmclk frequency + * 0b01011101..mclk frequency = 1/94 * hmclk frequency + * 0b01011110..mclk frequency = 1/95 * hmclk frequency + * 0b01011111..mclk frequency = 1/96 * hmclk frequency + * 0b01100000..mclk frequency = 1/97 * hmclk frequency + * 0b01100001..mclk frequency = 1/98 * hmclk frequency + * 0b01100010..mclk frequency = 1/99 * hmclk frequency + * 0b01100011..mclk frequency = 1/100 * hmclk frequency + * 0b01100100..mclk frequency = 1/101 * hmclk frequency + * 0b01100101..mclk frequency = 1/102 * hmclk frequency + * 0b01100110..mclk frequency = 1/103 * hmclk frequency + * 0b01100111..mclk frequency = 1/104 * hmclk frequency + * 0b01101000..mclk frequency = 1/105 * hmclk frequency + * 0b01101001..mclk frequency = 1/106 * hmclk frequency + * 0b01101010..mclk frequency = 1/107 * hmclk frequency + * 0b01101011..mclk frequency = 1/108 * hmclk frequency + * 0b01101100..mclk frequency = 1/109 * hmclk frequency + * 0b01101101..mclk frequency = 1/110 * hmclk frequency + * 0b01101110..mclk frequency = 1/111 * hmclk frequency + * 0b01101111..mclk frequency = 1/112 * hmclk frequency + * 0b01110000..mclk frequency = 1/113 * hmclk frequency + * 0b01110001..mclk frequency = 1/114 * hmclk frequency + * 0b01110010..mclk frequency = 1/115 * hmclk frequency + * 0b01110011..mclk frequency = 1/116 * hmclk frequency + * 0b01110100..mclk frequency = 1/117 * hmclk frequency + * 0b01110101..mclk frequency = 1/118 * hmclk frequency + * 0b01110110..mclk frequency = 1/119 * hmclk frequency + * 0b01110111..mclk frequency = 1/120 * hmclk frequency + * 0b01111000..mclk frequency = 1/121 * hmclk frequency + * 0b01111001..mclk frequency = 1/122 * hmclk frequency + * 0b01111010..mclk frequency = 1/123 * hmclk frequency + * 0b01111011..mclk frequency = 1/124 * hmclk frequency + * 0b01111100..mclk frequency = 1/125 * hmclk frequency + * 0b01111101..mclk frequency = 1/126 * hmclk frequency + * 0b01111110..mclk frequency = 1/127 * hmclk frequency + * 0b01111111..mclk frequency = 1/128 * hmclk frequency + * 0b10000000..mclk frequency = 1/129 * hmclk frequency + * 0b10000001..mclk frequency = 1/130 * hmclk frequency + * 0b10000010..mclk frequency = 1/131 * hmclk frequency + * 0b10000011..mclk frequency = 1/132 * hmclk frequency + * 0b10000100..mclk frequency = 1/133 * hmclk frequency + * 0b10000101..mclk frequency = 1/134 * hmclk frequency + * 0b10000110..mclk frequency = 1/135 * hmclk frequency + * 0b10000111..mclk frequency = 1/136 * hmclk frequency + * 0b10001000..mclk frequency = 1/137 * hmclk frequency + * 0b10001001..mclk frequency = 1/138 * hmclk frequency + * 0b10001010..mclk frequency = 1/139 * hmclk frequency + * 0b10001011..mclk frequency = 1/140 * hmclk frequency + * 0b10001100..mclk frequency = 1/141 * hmclk frequency + * 0b10001101..mclk frequency = 1/142 * hmclk frequency + * 0b10001110..mclk frequency = 1/143 * hmclk frequency + * 0b10001111..mclk frequency = 1/144 * hmclk frequency + * 0b10010000..mclk frequency = 1/145 * hmclk frequency + * 0b10010001..mclk frequency = 1/146 * hmclk frequency + * 0b10010010..mclk frequency = 1/147 * hmclk frequency + * 0b10010011..mclk frequency = 1/148 * hmclk frequency + * 0b10010100..mclk frequency = 1/149 * hmclk frequency + * 0b10010101..mclk frequency = 1/150 * hmclk frequency + * 0b10010110..mclk frequency = 1/151 * hmclk frequency + * 0b10010111..mclk frequency = 1/152 * hmclk frequency + * 0b10011000..mclk frequency = 1/153 * hmclk frequency + * 0b10011001..mclk frequency = 1/154 * hmclk frequency + * 0b10011010..mclk frequency = 1/155 * hmclk frequency + * 0b10011011..mclk frequency = 1/156 * hmclk frequency + * 0b10011100..mclk frequency = 1/157 * hmclk frequency + * 0b10011101..mclk frequency = 1/158 * hmclk frequency + * 0b10011110..mclk frequency = 1/159 * hmclk frequency + * 0b10011111..mclk frequency = 1/160 * hmclk frequency + * 0b10100000..mclk frequency = 1/161 * hmclk frequency + * 0b10100001..mclk frequency = 1/162 * hmclk frequency + * 0b10100010..mclk frequency = 1/163 * hmclk frequency + * 0b10100011..mclk frequency = 1/164 * hmclk frequency + * 0b10100100..mclk frequency = 1/165 * hmclk frequency + * 0b10100101..mclk frequency = 1/166 * hmclk frequency + * 0b10100110..mclk frequency = 1/167 * hmclk frequency + * 0b10100111..mclk frequency = 1/168 * hmclk frequency + * 0b10101000..mclk frequency = 1/169 * hmclk frequency + * 0b10101001..mclk frequency = 1/170 * hmclk frequency + * 0b10101010..mclk frequency = 1/171 * hmclk frequency + * 0b10101011..mclk frequency = 1/172 * hmclk frequency + * 0b10101100..mclk frequency = 1/173 * hmclk frequency + * 0b10101101..mclk frequency = 1/174 * hmclk frequency + * 0b10101110..mclk frequency = 1/175 * hmclk frequency + * 0b10101111..mclk frequency = 1/176 * hmclk frequency + * 0b10110000..mclk frequency = 1/177 * hmclk frequency + * 0b10110001..mclk frequency = 1/178 * hmclk frequency + * 0b10110010..mclk frequency = 1/179 * hmclk frequency + * 0b10110011..mclk frequency = 1/180 * hmclk frequency + * 0b10110100..mclk frequency = 1/181 * hmclk frequency + * 0b10110101..mclk frequency = 1/182 * hmclk frequency + * 0b10110110..mclk frequency = 1/183 * hmclk frequency + * 0b10110111..mclk frequency = 1/184 * hmclk frequency + * 0b10111000..mclk frequency = 1/185 * hmclk frequency + * 0b10111001..mclk frequency = 1/186 * hmclk frequency + * 0b10111010..mclk frequency = 1/187 * hmclk frequency + * 0b10111011..mclk frequency = 1/188 * hmclk frequency + * 0b10111100..mclk frequency = 1/189 * hmclk frequency + * 0b10111101..mclk frequency = 1/190 * hmclk frequency + * 0b10111110..mclk frequency = 1/191 * hmclk frequency + * 0b10111111..mclk frequency = 1/192 * hmclk frequency + * 0b11000000..mclk frequency = 1/193 * hmclk frequency + * 0b11000001..mclk frequency = 1/194 * hmclk frequency + * 0b11000010..mclk frequency = 1/195 * hmclk frequency + * 0b11000011..mclk frequency = 1/196 * hmclk frequency + * 0b11000100..mclk frequency = 1/197 * hmclk frequency + * 0b11000101..mclk frequency = 1/198 * hmclk frequency + * 0b11000110..mclk frequency = 1/199 * hmclk frequency + * 0b11000111..mclk frequency = 1/200 * hmclk frequency + * 0b11001000..mclk frequency = 1/201 * hmclk frequency + * 0b11001001..mclk frequency = 1/202 * hmclk frequency + * 0b11001010..mclk frequency = 1/203 * hmclk frequency + * 0b11001011..mclk frequency = 1/204 * hmclk frequency + * 0b11001100..mclk frequency = 1/205 * hmclk frequency + * 0b11001101..mclk frequency = 1/206 * hmclk frequency + * 0b11001110..mclk frequency = 1/207 * hmclk frequency + * 0b11001111..mclk frequency = 1/208 * hmclk frequency + * 0b11010000..mclk frequency = 1/209 * hmclk frequency + * 0b11010001..mclk frequency = 1/210 * hmclk frequency + * 0b11010010..mclk frequency = 1/211 * hmclk frequency + * 0b11010011..mclk frequency = 1/212 * hmclk frequency + * 0b11010100..mclk frequency = 1/213 * hmclk frequency + * 0b11010101..mclk frequency = 1/214 * hmclk frequency + * 0b11010110..mclk frequency = 1/215 * hmclk frequency + * 0b11010111..mclk frequency = 1/216 * hmclk frequency + * 0b11011000..mclk frequency = 1/217 * hmclk frequency + * 0b11011001..mclk frequency = 1/218 * hmclk frequency + * 0b11011010..mclk frequency = 1/219 * hmclk frequency + * 0b11011011..mclk frequency = 1/220 * hmclk frequency + * 0b11011100..mclk frequency = 1/221 * hmclk frequency + * 0b11011101..mclk frequency = 1/222 * hmclk frequency + * 0b11011110..mclk frequency = 1/223 * hmclk frequency + * 0b11011111..mclk frequency = 1/224 * hmclk frequency + * 0b11100000..mclk frequency = 1/225 * hmclk frequency + * 0b11100001..mclk frequency = 1/226 * hmclk frequency + * 0b11100010..mclk frequency = 1/227 * hmclk frequency + * 0b11100011..mclk frequency = 1/228 * hmclk frequency + * 0b11100100..mclk frequency = 1/229 * hmclk frequency + * 0b11100101..mclk frequency = 1/230 * hmclk frequency + * 0b11100110..mclk frequency = 1/231 * hmclk frequency + * 0b11100111..mclk frequency = 1/232 * hmclk frequency + * 0b11101000..mclk frequency = 1/233 * hmclk frequency + * 0b11101001..mclk frequency = 1/234 * hmclk frequency + * 0b11101010..mclk frequency = 1/235 * hmclk frequency + * 0b11101011..mclk frequency = 1/236 * hmclk frequency + * 0b11101100..mclk frequency = 1/237 * hmclk frequency + * 0b11101101..mclk frequency = 1/238 * hmclk frequency + * 0b11101110..mclk frequency = 1/239 * hmclk frequency + * 0b11101111..mclk frequency = 1/240 * hmclk frequency + * 0b11110000..mclk frequency = 1/241 * hmclk frequency + * 0b11110001..mclk frequency = 1/242 * hmclk frequency + * 0b11110010..mclk frequency = 1/243 * hmclk frequency + * 0b11110011..mclk frequency = 1/244 * hmclk frequency + * 0b11110100..mclk frequency = 1/245 * hmclk frequency + * 0b11110101..mclk frequency = 1/246 * hmclk frequency + * 0b11110110..mclk frequency = 1/247 * hmclk frequency + * 0b11110111..mclk frequency = 1/248 * hmclk frequency + * 0b11111000..mclk frequency = 1/249 * hmclk frequency + * 0b11111001..mclk frequency = 1/250 * hmclk frequency + * 0b11111010..mclk frequency = 1/251 * hmclk frequency + * 0b11111011..mclk frequency = 1/252 * hmclk frequency + * 0b11111100..mclk frequency = 1/253 * hmclk frequency + * 0b11111101..mclk frequency = 1/254 * hmclk frequency + * 0b11111110..mclk frequency = 1/255 * hmclk frequency + * 0b11111111..mclk frequency = 1/256 * hmclk frequency + */ +#define IOMUXC_GPR_GPR2_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK) +#define IOMUXC_GPR_GPR2_MQS_SW_RST_MASK (0x1000000U) +#define IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT (24U) +/*! MQS_SW_RST + * 0b0..Exit software reset for MQS + * 0b1..Enable software reset for MQS + */ +#define IOMUXC_GPR_GPR2_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR2_MQS_SW_RST_MASK) +#define IOMUXC_GPR_GPR2_MQS_EN_MASK (0x2000000U) +#define IOMUXC_GPR_GPR2_MQS_EN_SHIFT (25U) +/*! MQS_EN + * 0b0..Disable MQS + * 0b1..Enable MQS + */ +#define IOMUXC_GPR_GPR2_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR2_MQS_EN_MASK) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK (0x4000000U) +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT (26U) +/*! MQS_OVERSAMPLE + * 0b0..32 + * 0b1..64 + */ +#define IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK) +#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK (0x10000000U) +#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT (28U) +/*! QTIMER1_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ +#define IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER1_TMR_CNTS_FREEZE_MASK) +#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK (0x20000000U) +#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT (29U) +/*! QTIMER2_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ +#define IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER2_TMR_CNTS_FREEZE_MASK) +#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK (0x40000000U) +#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT (30U) +/*! QTIMER3_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ +#define IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER3_TMR_CNTS_FREEZE_MASK) +#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK (0x80000000U) +#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT (31U) +/*! QTIMER4_TMR_CNTS_FREEZE + * 0b0..timer counter work normally + * 0b1..reset counter and ouput flags + */ +#define IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR2_QTIMER4_TMR_CNTS_FREEZE_MASK) +/*! @} */ + +/*! @name GPR3 - GPR3 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR3_OCRAM_CTL_MASK (0xFU) +#define IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT (0U) +#define IOMUXC_GPR_GPR3_OCRAM_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_CTL_MASK) +#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK (0x10U) +#define IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT (4U) +/*! DCP_KEY_SEL + * 0b0..Select [127:0] from snvs/ocotp key as dcp key + * 0b1..Select [255:128] from snvs/ocotp key as dcp key + */ +#define IOMUXC_GPR_GPR3_DCP_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DCP_KEY_SEL_SHIFT)) & IOMUXC_GPR_GPR3_DCP_KEY_SEL_MASK) +#define IOMUXC_GPR_GPR3_OCRAM2_CTL_MASK (0xF00U) +#define IOMUXC_GPR_GPR3_OCRAM2_CTL_SHIFT (8U) +#define IOMUXC_GPR_GPR3_OCRAM2_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM2_CTL_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM2_CTL_MASK) +#define IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_MASK (0x8000U) +#define IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_SHIFT (15U) +/*! AXBS_L_HALT_REQ + * 0b0..axbs_l normal run + * 0b1..request to halt axbs_l + */ +#define IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_SHIFT)) & IOMUXC_GPR_GPR3_AXBS_L_HALT_REQ_MASK) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK (0xF0000U) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT (16U) +#define IOMUXC_GPR_GPR3_OCRAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM_STATUS_MASK) +#define IOMUXC_GPR_GPR3_OCRAM2_STATUS_MASK (0xF000000U) +#define IOMUXC_GPR_GPR3_OCRAM2_STATUS_SHIFT (24U) +#define IOMUXC_GPR_GPR3_OCRAM2_STATUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_OCRAM2_STATUS_SHIFT)) & IOMUXC_GPR_GPR3_OCRAM2_STATUS_MASK) +#define IOMUXC_GPR_GPR3_AXBS_L_HALTED_MASK (0x80000000U) +#define IOMUXC_GPR_GPR3_AXBS_L_HALTED_SHIFT (31U) +/*! AXBS_L_HALTED + * 0b0..axbs_l is not halted + * 0b1..axbs_l is in halted status + */ +#define IOMUXC_GPR_GPR3_AXBS_L_HALTED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_AXBS_L_HALTED_SHIFT)) & IOMUXC_GPR_GPR3_AXBS_L_HALTED_MASK) +/*! @} */ + +/*! @name GPR4 - GPR4 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK (0x1U) +#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT (0U) +/*! EDMA_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK (0x2U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT (1U) +/*! CAN1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK (0x4U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT (2U) +/*! CAN2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK (0x8U) +#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT (3U) +/*! TRNG_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_TRNG_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK (0x10U) +#define IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT (4U) +/*! ENET_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK (0x20U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT (5U) +/*! SAI1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK (0x40U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT (6U) +/*! SAI2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK (0x80U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT (7U) +/*! SAI3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK (0x100U) +#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT (8U) +/*! ENET2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_ENET2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK (0x200U) +#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT (9U) +/*! SEMC_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK (0x400U) +#define IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT (10U) +/*! PIT_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_PIT_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK (0x800U) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT (11U) +/*! FLEXSPI_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK (0x1000U) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT (12U) +/*! FLEXIO1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK (0x2000U) +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT (13U) +/*! FLEXIO2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_MASK (0x4000U) +#define IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_SHIFT (14U) +/*! FLEXIO3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_MASK (0x8000U) +#define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_SHIFT (15U) +/*! FLEXSPI2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK (0x10000U) +#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT (16U) +/*! EDMA_STOP_ACK + * 0b0..EDMA stop acknowledge is not asserted + * 0b1..EDMA stop acknowledge is asserted (EDMA is in STOP mode). + */ +#define IOMUXC_GPR_GPR4_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_EDMA_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK (0x20000U) +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT (17U) +/*! CAN1_STOP_ACK + * 0b0..CAN1 stop acknowledge is not asserted + * 0b1..CAN1 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK (0x40000U) +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT (18U) +/*! CAN2_STOP_ACK + * 0b0..CAN2 stop acknowledge is not asserted + * 0b1..CAN2 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_CAN2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK (0x80000U) +#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT (19U) +/*! TRNG_STOP_ACK + * 0b0..TRNG stop acknowledge is not asserted + * 0b1..TRNG stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_TRNG_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_TRNG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_TRNG_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK (0x100000U) +#define IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT (20U) +/*! ENET_STOP_ACK + * 0b0..ENET1 stop acknowledge is not asserted + * 0b1..ENET1 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK (0x200000U) +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT (21U) +/*! SAI1_STOP_ACK + * 0b0..SAI1 stop acknowledge is not asserted + * 0b1..SAI1 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK (0x400000U) +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT (22U) +/*! SAI2_STOP_ACK + * 0b0..SAI2 stop acknowledge is not asserted + * 0b1..SAI2 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK (0x800000U) +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT (23U) +/*! SAI3_STOP_ACK + * 0b0..SAI3 stop acknowledge is not asserted + * 0b1..SAI3 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK (0x1000000U) +#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT (24U) +/*! ENET2_STOP_ACK + * 0b0..ENET2 stop acknowledge is not asserted + * 0b1..ENET2 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_ENET2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_ENET2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK (0x2000000U) +#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT (25U) +/*! SEMC_STOP_ACK + * 0b0..SEMC stop acknowledge is not asserted + * 0b1..SEMC stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SEMC_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK (0x4000000U) +#define IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT (26U) +/*! PIT_STOP_ACK + * 0b0..PIT stop acknowledge is not asserted + * 0b1..PIT stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_PIT_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PIT_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PIT_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK (0x8000000U) +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT (27U) +/*! FLEXSPI_STOP_ACK + * 0b0..FLEXSPI stop acknowledge is not asserted + * 0b1..FLEXSPI stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK (0x10000000U) +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT (28U) +/*! FLEXIO1_STOP_ACK + * 0b0..FLEXIO1 stop acknowledge is not asserted + * 0b1..FLEXIO1 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK (0x20000000U) +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT (29U) +/*! FLEXIO2_STOP_ACK + * 0b0..FLEXIO2 stop acknowledge is not asserted + * 0b1..FLEXIO2 stop acknowledge is asserted (FLEXIO2 is in STOP mode) + */ +#define IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_MASK (0x40000000U) +#define IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_SHIFT (30U) +/*! FLEXIO3_STOP_ACK + * 0b0..FLEXIO3 stop acknowledge is not asserted + * 0b1..FLEXIO3 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXIO3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_MASK (0x80000000U) +#define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_SHIFT (31U) +/*! FLEXSPI2_STOP_ACK + * 0b0..FLEXSPI2 stop acknowledge is not asserted + * 0b1..FLEXSPI2 stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_FLEXSPI2_STOP_ACK_MASK) +/*! @} */ + +/*! @name GPR5 - GPR5 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR5_WDOG1_MASK_MASK (0x40U) +#define IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT (6U) +/*! WDOG1_MASK + * 0b0..WDOG1 Timeout behaves normally + * 0b1..WDOG1 Timeout is masked + */ +#define IOMUXC_GPR_GPR5_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG1_MASK_MASK) +#define IOMUXC_GPR_GPR5_WDOG2_MASK_MASK (0x80U) +#define IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT (7U) +/*! WDOG2_MASK + * 0b0..WDOG2 Timeout behaves normally + * 0b1..WDOG2 Timeout is masked + */ +#define IOMUXC_GPR_GPR5_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_WDOG2_MASK_MASK) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK (0x800000U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT (23U) +/*! GPT2_CAPIN1_SEL + * 0b0..source from GPT2_CAPTURE1 + * 0b1..source from ENET_1588_EVENT3_OUT (chnnal 3 of IEEE 1588 timer) + */ +#define IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN1_SEL_MASK) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK (0x1000000U) +#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT (24U) +/*! GPT2_CAPIN2_SEL + * 0b0..source from GPT2_CAPTURE2 + * 0b1..source from ENET2_1588_EVENT3_OUT (chnnal 3 of IEEE 1588 timer) + */ +#define IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPT2_CAPIN2_SEL_MASK) +#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK (0x2000000U) +#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT (25U) +/*! ENET_EVENT3IN_SEL + * 0b0..event3 source input from ENET_1588_EVENT3_IN + * 0b1..event3 source input from GPT2.GPT_COMPARE1 + */ +#define IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET_EVENT3IN_SEL_MASK) +#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK (0x4000000U) +#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT (26U) +/*! ENET2_EVENT3IN_SEL + * 0b0..event3 source input from ENET2_1588_EVENT3_IN + * 0b1..event3 source input from GPT2.GPT_COMPARE2 + */ +#define IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET2_EVENT3IN_SEL_MASK) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK (0x10000000U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT (28U) +/*! VREF_1M_CLK_GPT1 + * 0b0..GPT1 ipg_clk_highfreq driven by IPG_PERCLK + * 0b1..GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock + */ +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK (0x20000000U) +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT (29U) +/*! VREF_1M_CLK_GPT2 + * 0b0..GPT2 ipg_clk_highfreq driven by IPG_PERCLK + * 0b1..GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock + */ +#define IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK) +/*! @} */ + +/*! @name GPR6 - GPR6 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (0x1U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0U) +/*! QTIMER1_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (0x2U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1U) +/*! QTIMER1_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (0x4U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2U) +/*! QTIMER1_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (0x8U) +#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3U) +/*! QTIMER1_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (0x10U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4U) +/*! QTIMER2_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (0x20U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5U) +/*! QTIMER2_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (0x40U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6U) +/*! QTIMER2_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (0x80U) +#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7U) +/*! QTIMER2_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U) +/*! QTIMER3_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U) +/*! QTIMER3_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U) +/*! QTIMER3_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U) +#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U) +/*! QTIMER3_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (0x1000U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12U) +/*! QTIMER4_TRM0_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (0x2000U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13U) +/*! QTIMER4_TRM1_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (0x4000U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14U) +/*! QTIMER4_TRM2_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (0x8000U) +#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15U) +/*! QTIMER4_TRM3_INPUT_SEL + * 0b0..input from IOMUX + * 0b1..input from XBAR + */ +#define IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (0x10000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16U) +/*! IOMUXC_XBAR_DIR_SEL_4 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (0x20000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17U) +/*! IOMUXC_XBAR_DIR_SEL_5 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (0x40000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18U) +/*! IOMUXC_XBAR_DIR_SEL_6 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (0x80000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19U) +/*! IOMUXC_XBAR_DIR_SEL_7 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (0x100000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20U) +/*! IOMUXC_XBAR_DIR_SEL_8 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (0x200000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21U) +/*! IOMUXC_XBAR_DIR_SEL_9 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (0x400000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22U) +/*! IOMUXC_XBAR_DIR_SEL_10 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (0x800000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23U) +/*! IOMUXC_XBAR_DIR_SEL_11 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (0x1000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24U) +/*! IOMUXC_XBAR_DIR_SEL_12 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (0x2000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25U) +/*! IOMUXC_XBAR_DIR_SEL_13 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (0x4000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26U) +/*! IOMUXC_XBAR_DIR_SEL_14 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (0x8000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27U) +/*! IOMUXC_XBAR_DIR_SEL_15 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (0x10000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28U) +/*! IOMUXC_XBAR_DIR_SEL_16 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (0x20000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29U) +/*! IOMUXC_XBAR_DIR_SEL_17 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (0x40000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30U) +/*! IOMUXC_XBAR_DIR_SEL_18 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (0x80000000U) +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31U) +/*! IOMUXC_XBAR_DIR_SEL_19 + * 0b0..XBAR_INOUT as input + * 0b1..XBAR_INOUT as output + */ +#define IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK) +/*! @} */ + +/*! @name GPR7 - GPR7 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK (0x1U) +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT (0U) +/*! LPI2C1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK (0x2U) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT (1U) +/*! LPI2C2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK (0x4U) +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT (2U) +/*! LPI2C3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK (0x8U) +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT (3U) +/*! LPI2C4_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK (0x10U) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT (4U) +/*! LPSPI1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK (0x20U) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT (5U) +/*! LPSPI2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK (0x40U) +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT (6U) +/*! LPSPI3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK (0x80U) +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT (7U) +/*! LPSPI4_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK (0x100U) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT (8U) +/*! LPUART1_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK (0x200U) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT (9U) +/*! LPUART2_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK (0x400U) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT (10U) +/*! LPUART3_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK (0x800U) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT (11U) +/*! LPUART4_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK (0x1000U) +#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT (12U) +/*! LPUART5_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK (0x2000U) +#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT (13U) +/*! LPUART6_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK (0x4000U) +#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT (14U) +/*! LPUART7_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK (0x8000U) +#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT (15U) +/*! LPUART8_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR7_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK (0x10000U) +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT (16U) +/*! LPI2C1_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted (the module is in Stop mode) + */ +#define IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK (0x20000U) +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT (17U) +/*! LPI2C2_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK (0x40000U) +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT (18U) +/*! LPI2C3_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK (0x80000U) +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT (19U) +/*! LPI2C4_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPI2C4_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK (0x100000U) +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT (20U) +/*! LPSPI1_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK (0x200000U) +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT (21U) +/*! LPSPI2_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK (0x400000U) +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT (22U) +/*! LPSPI3_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK (0x800000U) +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT (23U) +/*! LPSPI4_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPSPI4_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK (0x1000000U) +#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT (24U) +/*! LPUART1_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART1_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK (0x2000000U) +#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT (25U) +/*! LPUART2_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART2_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK (0x4000000U) +#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT (26U) +/*! LPUART3_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART3_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK (0x8000000U) +#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT (27U) +/*! LPUART4_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART4_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK (0x10000000U) +#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT (28U) +/*! LPUART5_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART5_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK (0x20000000U) +#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT (29U) +/*! LPUART6_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART6_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK (0x40000000U) +#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT (30U) +/*! LPUART7_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR7_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART7_STOP_ACK_MASK) +#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK (0x80000000U) +#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT (31U) +/*! LPUART8_STOP_ACK + * 0b0..stop acknowledge is not asserted + * 0b1..stop acknowledge is asserted (the module is in Stop mode) + */ +#define IOMUXC_GPR_GPR7_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR7_LPUART8_STOP_ACK_MASK) +/*! @} */ + +/*! @name GPR8 - GPR8 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (0x1U) +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0U) +/*! LPI2C1_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK (0x2U) +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1U) +/*! LPI2C1_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C1_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (0x4U) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2U) +/*! LPI2C2_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK (0x8U) +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3U) +/*! LPI2C2_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C2_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (0x10U) +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4U) +/*! LPI2C3_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK (0x20U) +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5U) +/*! LPI2C3_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C3_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (0x40U) +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6U) +/*! LPI2C4_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK (0x80U) +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7U) +/*! LPI2C4_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPI2C4_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (0x100U) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8U) +/*! LPSPI1_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK (0x200U) +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9U) +/*! LPSPI1_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI1_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (0x400U) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10U) +/*! LPSPI2_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK (0x800U) +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11U) +/*! LPSPI2_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI2_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (0x1000U) +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12U) +/*! LPSPI3_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK (0x2000U) +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13U) +/*! LPSPI3_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI3_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (0x4000U) +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14U) +/*! LPSPI4_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK (0x8000U) +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15U) +/*! LPSPI4_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPSPI4_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (0x10000U) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16U) +/*! LPUART1_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK (0x20000U) +#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17U) +/*! LPUART1_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART1_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (0x40000U) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18U) +/*! LPUART2_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK (0x80000U) +#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19U) +/*! LPUART2_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART2_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (0x100000U) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20U) +/*! LPUART3_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK (0x200000U) +#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21U) +/*! LPUART3_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART3_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (0x400000U) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22U) +/*! LPUART4_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK (0x800000U) +#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23U) +/*! LPUART4_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART4_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (0x1000000U) +#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24U) +/*! LPUART5_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK (0x2000000U) +#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25U) +/*! LPUART5_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART5_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (0x4000000U) +#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26U) +/*! LPUART6_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK (0x8000000U) +#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27U) +/*! LPUART6_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART6_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (0x10000000U) +#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28U) +/*! LPUART7_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK (0x20000000U) +#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29U) +/*! LPUART7_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART7_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (0x40000000U) +#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30U) +/*! LPUART8_IPG_STOP_MODE + * 0b0..the module is functional in Stop mode + * 0b1..the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + */ +#define IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK (0x80000000U) +#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31U) +/*! LPUART8_IPG_DOZE + * 0b0..not in doze mode + * 0b1..in doze mode + */ +#define IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR8_LPUART8_IPG_DOZE_MASK) +/*! @} */ + +/*! @name GPR10 - GPR10 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR10_NIDEN_MASK (0x1U) +#define IOMUXC_GPR_GPR10_NIDEN_SHIFT (0U) +/*! NIDEN + * 0b0..Debug turned off. + * 0b1..Debug enabled (default). + */ +#define IOMUXC_GPR_GPR10_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_NIDEN_MASK) +#define IOMUXC_GPR_GPR10_DBG_EN_MASK (0x2U) +#define IOMUXC_GPR_GPR10_DBG_EN_SHIFT (1U) +/*! DBG_EN + * 0b0..Debug turned off. + * 0b1..Debug enabled (default). + */ +#define IOMUXC_GPR_GPR10_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_DBG_EN_MASK) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK (0x4U) +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT (2U) +/*! SEC_ERR_RESP + * 0b0..OKEY response + * 0b1..SLVError (default) + */ +#define IOMUXC_GPR_GPR10_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_SEC_ERR_RESP_MASK) +#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x10U) +#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (4U) +/*! DCPKEY_OCOTP_OR_KEYMUX + * 0b0..Select key from Key MUX (SNVS/OTPMK). + * 0b1..Select key from OCOTP (SW_GP2). + */ +#define IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX_MASK) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK (0x100U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT (8U) +/*! OCRAM_TZ_EN + * 0b0..The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor). + * 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows + * the execution mode access policy described in CSU chapter. + */ +#define IOMUXC_GPR_GPR10_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_EN_MASK) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK (0xFE00U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9U) +#define IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_OCRAM_TZ_ADDR_MASK) +#define IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK (0x10000U) +#define IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT (16U) +/*! LOCK_NIDEN + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_NIDEN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_NIDEN_MASK) +#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK (0x20000U) +#define IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT (17U) +/*! LOCK_DBG_EN + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DBG_EN_MASK) +#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK (0x40000U) +#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT (18U) +/*! LOCK_SEC_ERR_RESP + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_SEC_ERR_RESP_MASK) +#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK (0x100000U) +#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT (20U) +/*! LOCK_DCPKEY_OCOTP_OR_KEYMUX + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX_MASK) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK (0x1000000U) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT (24U) +/*! LOCK_OCRAM_TZ_EN + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_EN_MASK) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0xFE000000U) +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25U) +/*! LOCK_OCRAM_TZ_ADDR + * 0b0000000..Field is not locked + * 0b0000001..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK) +/*! @} */ + +/*! @name GPR11 - GPR11 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (0x3U) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT (0U) +/*! M7_APC_AC_R0_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R0_CTRL_MASK) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (0xCU) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT (2U) +/*! M7_APC_AC_R1_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R1_CTRL_MASK) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (0x30U) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT (4U) +/*! M7_APC_AC_R2_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R2_CTRL_MASK) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (0xC0U) +#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT (6U) +/*! M7_APC_AC_R3_CTRL + * 0b00..No access protection + * 0b01..M7 debug protection enabled + * 0b10..FlexSPI access protection + * 0b11..Both M7 debug and FlexSPI access are protected + */ +#define IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFT)) & IOMUXC_GPR_GPR11_M7_APC_AC_R3_CTRL_MASK) +#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK (0xF00U) +#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT (8U) +#define IOMUXC_GPR_GPR11_BEE_DE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_BEE_DE_RX_EN_SHIFT)) & IOMUXC_GPR_GPR11_BEE_DE_RX_EN_MASK) +/*! @} */ + +/*! @name GPR12 - GPR12 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (0x1U) +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0U) +/*! FLEXIO1_IPG_STOP_MODE + * 0b0..FlexIO1 is functional in Stop mode. + * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode. + */ +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (0x2U) +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1U) +/*! FLEXIO1_IPG_DOZE + * 0b0..FLEXIO1 is not in doze mode + * 0b1..FLEXIO1 is in doze mode + */ +#define IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO1_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (0x4U) +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2U) +/*! FLEXIO2_IPG_STOP_MODE + * 0b0..FlexIO2 is functional in Stop mode. + * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO2 is not functional in Stop mode. + */ +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (0x8U) +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3U) +/*! FLEXIO2_IPG_DOZE + * 0b0..FLEXIO2 is not in doze mode + * 0b1..FLEXIO2 is in doze mode + */ +#define IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO2_IPG_DOZE_MASK) +#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (0x10U) +#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4U) +/*! ACMP_IPG_STOP_MODE + * 0b0..ACMP is functional in Stop mode. + * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, ACMP is not functional in Stop mode. + */ +#define IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_ACMP_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_MASK (0x20U) +#define IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_SHIFT (5U) +/*! FLEXIO3_IPG_STOP_MODE + * 0b0..FlexIO3 is functional in Stop mode. + * 0b1..When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO3 is not functional in Stop mode. + */ +#define IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO3_IPG_STOP_MODE_MASK) +#define IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_MASK (0x40U) +#define IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_SHIFT (6U) +/*! FLEXIO3_IPG_DOZE + * 0b0..FLEXIO3 is not in doze mode + * 0b1..FLEXIO3 is in doze mode + */ +#define IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR12_FLEXIO3_IPG_DOZE_MASK) +/*! @} */ + +/*! @name GPR13 - GPR13 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK (0x1U) +#define IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT (0U) +/*! ARCACHE_USDHC + * 0b0..Cacheable attribute is off for read transactions. + * 0b1..Cacheable attribute is on for read transactions. + */ +#define IOMUXC_GPR_GPR13_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_ARCACHE_USDHC_MASK) +#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK (0x2U) +#define IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT (1U) +/*! AWCACHE_USDHC + * 0b0..Cacheable attribute is off for write transactions. + * 0b1..Cacheable attribute is on for write transactions. + */ +#define IOMUXC_GPR_GPR13_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR13_AWCACHE_USDHC_MASK) +#define IOMUXC_GPR_GPR13_CANFD_STOP_REQ_MASK (0x10U) +#define IOMUXC_GPR_GPR13_CANFD_STOP_REQ_SHIFT (4U) +/*! CANFD_STOP_REQ + * 0b0..stop request off + * 0b1..stop request on + */ +#define IOMUXC_GPR_GPR13_CANFD_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CANFD_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR13_CANFD_STOP_REQ_MASK) +#define IOMUXC_GPR_GPR13_CACHE_ENET_MASK (0x80U) +#define IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT (7U) +/*! CACHE_ENET + * 0b0..Cacheable attribute is off for read/write transactions. + * 0b1..Cacheable attribute is on for read/write transactions. + */ +#define IOMUXC_GPR_GPR13_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_ENET_MASK) +#define IOMUXC_GPR_GPR13_CACHE_USB_MASK (0x2000U) +#define IOMUXC_GPR_GPR13_CACHE_USB_SHIFT (13U) +/*! CACHE_USB + * 0b0..Cacheable attribute is off for read/write transactions. + * 0b1..Cacheable attribute is on for read/write transactions. + */ +#define IOMUXC_GPR_GPR13_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR13_CACHE_USB_MASK) +#define IOMUXC_GPR_GPR13_CANFD_STOP_ACK_MASK (0x100000U) +#define IOMUXC_GPR_GPR13_CANFD_STOP_ACK_SHIFT (20U) +/*! CANFD_STOP_ACK + * 0b0..CANFD stop acknowledge is not asserted + * 0b1..CANFD stop acknowledge is asserted + */ +#define IOMUXC_GPR_GPR13_CANFD_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_CANFD_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR13_CANFD_STOP_ACK_MASK) +/*! @} */ + +/*! @name GPR14 - GPR14 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK (0x1U) +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT (0U) +/*! ACMP1_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN_MASK) +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK (0x2U) +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT (1U) +/*! ACMP2_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN_MASK) +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK (0x4U) +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT (2U) +/*! ACMP3_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN_MASK) +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK (0x8U) +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT (3U) +/*! ACMP4_CMP_IGEN_TRIM_DN + * 0b0..no reduce + * 0b1..reduces + */ +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN_MASK) +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK (0x10U) +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT (4U) +/*! ACMP1_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ +#define IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP_MASK) +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK (0x20U) +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT (5U) +/*! ACMP2_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ +#define IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP_MASK) +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK (0x40U) +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT (6U) +/*! ACMP3_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ +#define IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP_MASK) +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK (0x80U) +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT (7U) +/*! ACMP4_CMP_IGEN_TRIM_UP + * 0b0..no increase + * 0b1..increases + */ +#define IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP_MASK) +#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK (0x100U) +#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT (8U) +/*! ACMP1_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ +#define IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP1_SAMPLE_SYNC_EN_MASK) +#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK (0x200U) +#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT (9U) +/*! ACMP2_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ +#define IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP2_SAMPLE_SYNC_EN_MASK) +#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK (0x400U) +#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT (10U) +/*! ACMP3_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ +#define IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP3_SAMPLE_SYNC_EN_MASK) +#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK (0x800U) +#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT (11U) +/*! ACMP4_SAMPLE_SYNC_EN + * 0b0..select XBAR output + * 0b1..select synced sample_lv + */ +#define IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_SHIFT)) & IOMUXC_GPR_GPR14_ACMP4_SAMPLE_SYNC_EN_MASK) +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK (0xF0000U) +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16U) +/*! CM7_CFGITCMSZ + * 0b0000..0 KB (No ITCM) + * 0b0011..4 KB + * 0b0100..8 KB + * 0b0101..16 KB + * 0b0110..32 KB + * 0b0111..64 KB + * 0b1000..128 KB + * 0b1001..256 KB + * 0b1010..512 KB + */ +#define IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xF00000U) +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20U) +/*! CM7_CFGDTCMSZ + * 0b0000..0 KB (No DTCM) + * 0b0011..4 KB + * 0b0100..8 KB + * 0b0101..16 KB + * 0b0110..32 KB + * 0b0111..64 KB + * 0b1000..128 KB + * 0b1001..256 KB + * 0b1010..512 KB + */ +#define IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK) +/*! @} */ + +/*! @name GPR16 - GPR16 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U) +#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U) +/*! INIT_ITCM_EN + * 0b0..ITCM is disabled + * 0b1..ITCM is enabled + */ +#define IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK) +#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U) +#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U) +/*! INIT_DTCM_EN + * 0b0..DTCM is disabled + * 0b1..DTCM is enabled + */ +#define IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK) +#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U) +#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U) +/*! FLEXRAM_BANK_CFG_SEL + * 0b0..use fuse value to config + * 0b1..use FLEXRAM_BANK_CFG to config + */ +#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK) +/*! @} */ + +/*! @name GPR17 - GPR17 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xFFFFFFFFU) +#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0U) +#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_MASK) +/*! @} */ + +/*! @name GPR18 - GPR18 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R0_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_LOCK_M7_APC_AC_R0_BOT_MASK) +#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT)) & IOMUXC_GPR_GPR18_M7_APC_AC_R0_BOT_MASK) +/*! @} */ + +/*! @name GPR19 - GPR19 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R0_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_LOCK_M7_APC_AC_R0_TOP_MASK) +#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT)) & IOMUXC_GPR_GPR19_M7_APC_AC_R0_TOP_MASK) +/*! @} */ + +/*! @name GPR20 - GPR20 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R1_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_LOCK_M7_APC_AC_R1_BOT_MASK) +#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT)) & IOMUXC_GPR_GPR20_M7_APC_AC_R1_BOT_MASK) +/*! @} */ + +/*! @name GPR21 - GPR21 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R1_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_LOCK_M7_APC_AC_R1_TOP_MASK) +#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT)) & IOMUXC_GPR_GPR21_M7_APC_AC_R1_TOP_MASK) +/*! @} */ + +/*! @name GPR22 - GPR22 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R2_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_LOCK_M7_APC_AC_R2_BOT_MASK) +#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT)) & IOMUXC_GPR_GPR22_M7_APC_AC_R2_BOT_MASK) +/*! @} */ + +/*! @name GPR23 - GPR23 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R2_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_LOCK_M7_APC_AC_R2_TOP_MASK) +#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_GPR_GPR23_M7_APC_AC_R2_TOP_MASK) +/*! @} */ + +/*! @name GPR24 - GPR24 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK (0x1U) +#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT (0U) +/*! LOCK_M7_APC_AC_R3_BOT + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_LOCK_M7_APC_AC_R3_BOT_MASK) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3U) +#define IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT)) & IOMUXC_GPR_GPR24_M7_APC_AC_R3_BOT_MASK) +/*! @} */ + +/*! @name GPR25 - GPR25 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK (0x1U) +#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT (0U) +/*! LOCK_M7_APC_AC_R3_TOP + * 0b0..Register field [31:1] is not locked + * 0b1..Register field [31:1] is locked (read access only) + */ +#define IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_LOCK_M7_APC_AC_R3_TOP_MASK) +#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0xFFFFFFF8U) +#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3U) +#define IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT)) & IOMUXC_GPR_GPR25_M7_APC_AC_R3_TOP_MASK) +/*! @} */ + +/*! @name GPR26 - GPR26 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK (0xFFFFFFFFU) +#define IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_SHIFT (0U) +#define IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR26_GPIO_MUX1_GPIO_SEL_MASK) +/*! @} */ + +/*! @name GPR27 - GPR27 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK (0xFFFFFFFFU) +#define IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_SHIFT (0U) +#define IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR27_GPIO_MUX2_GPIO_SEL_MASK) +/*! @} */ + +/*! @name GPR28 - GPR28 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_MASK (0xFFFFFFFFU) +#define IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_SHIFT (0U) +#define IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR28_GPIO_MUX3_GPIO_SEL_MASK) +/*! @} */ + +/*! @name GPR29 - GPR29 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_MASK (0xFFFFFFFFU) +#define IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_SHIFT (0U) +#define IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_SHIFT)) & IOMUXC_GPR_GPR29_GPIO_MUX4_GPIO_SEL_MASK) +/*! @} */ + +/*! @name GPR30 - GPR30 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_MASK (0xFFFFF000U) +#define IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT (12U) +#define IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT)) & IOMUXC_GPR_GPR30_FLEXSPI_REMAP_ADDR_START_MASK) +/*! @} */ + +/*! @name GPR31 - GPR31 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_MASK (0xFFFFF000U) +#define IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT (12U) +#define IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT)) & IOMUXC_GPR_GPR31_FLEXSPI_REMAP_ADDR_END_MASK) +/*! @} */ + +/*! @name GPR32 - GPR32 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_MASK (0xFFFFF000U) +#define IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT (12U) +#define IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT)) & IOMUXC_GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_MASK) +/*! @} */ + +/*! @name GPR33 - GPR33 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_MASK (0x1U) +#define IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_SHIFT (0U) +/*! OCRAM2_TZ_EN + * 0b0..The TrustZone feature is disabled. Entire OCRAM2 space is available for all access types (secure/non-secure/user/supervisor). + * 0b1..The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows + * the execution mode access policy described in CSU chapter. + */ +#define IOMUXC_GPR_GPR33_OCRAM2_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR33_OCRAM2_TZ_EN_MASK) +#define IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_MASK (0xFEU) +#define IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT (1U) +#define IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR33_OCRAM2_TZ_ADDR_MASK) +#define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_MASK (0x10000U) +#define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_SHIFT (16U) +/*! LOCK_OCRAM2_TZ_EN + * 0b0..Field is not locked + * 0b1..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_SHIFT)) & IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_EN_MASK) +#define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_MASK (0xFE0000U) +#define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT (17U) +/*! LOCK_OCRAM2_TZ_ADDR + * 0b0000000..Field is not locked + * 0b0000001..Field is locked (read access only) + */ +#define IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT)) & IOMUXC_GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_MASK) +/*! @} */ + +/*! @name GPR34 - GPR34 General Purpose Register */ +/*! @{ */ +#define IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_MASK (0xFFU) +#define IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT (0U) +#define IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT)) & IOMUXC_GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_MASK) +#define IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_MASK (0x100U) +#define IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_SHIFT (8U) +/*! SIP_TEST_MUX_QSPI_SIP_EN + * 0b0..SIP_TEST_MUX is disabled + * 0b1..SIP_TEST_MUX is enabled + */ +#define IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_SHIFT)) & IOMUXC_GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group IOMUXC_GPR_Register_Masks */ + + +/* IOMUXC_GPR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_GPR base address */ +#define IOMUXC_GPR_BASE (0x400AC000u) +/** Peripheral IOMUXC_GPR base pointer */ +#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE) +/** Array initializer of IOMUXC_GPR peripheral base addresses */ +#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE } +/** Array initializer of IOMUXC_GPR peripheral base pointers */ +#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR } + +/*! + * @} + */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_Peripheral_Access_Layer IOMUXC_SNVS Peripheral Access Layer + * @{ + */ + +/** IOMUXC_SNVS - Register Layout Typedef */ +typedef struct { + __IO uint32_t SW_MUX_CTL_PAD_WAKEUP; /**< SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register, offset: 0x0 */ + __IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ; /**< SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register, offset: 0x4 */ + __IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ; /**< SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register, offset: 0x8 */ + __IO uint32_t SW_PAD_CTL_PAD_TEST_MODE; /**< SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register, offset: 0xC */ + __IO uint32_t SW_PAD_CTL_PAD_POR_B; /**< SW_PAD_CTL_PAD_POR_B SW PAD Control Register, offset: 0x10 */ + __IO uint32_t SW_PAD_CTL_PAD_ONOFF; /**< SW_PAD_CTL_PAD_ONOFF SW PAD Control Register, offset: 0x14 */ + __IO uint32_t SW_PAD_CTL_PAD_WAKEUP; /**< SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register, offset: 0x18 */ + __IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ; /**< SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register, offset: 0x1C */ + __IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ; /**< SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register, offset: 0x20 */ +} IOMUXC_SNVS_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_Register_Masks IOMUXC_SNVS Register Masks + * @{ + */ + +/*! @name SW_MUX_CTL_PAD_WAKEUP - SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK (0x7U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b101..Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5 + * 0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_MUX_MODE_MASK) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK (0x10U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad WAKEUP + * 0b0..Input Path is determined by functionality + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_SION_MASK) +/*! @} */ + +/*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ - SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK (0x7U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp + * 0b101..Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5 + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_MUX_MODE_MASK) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK (0x10U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad PMIC_ON_REQ + * 0b0..Input Path is determined by functionality + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_SION_MASK) +/*! @} */ + +/*! @name SW_MUX_CTL_PAD_PMIC_STBY_REQ - SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK (0x7U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT (0U) +/*! MUX_MODE - MUX Mode Select Field. + * 0b000..Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: ccm + * 0b101..Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5 + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_MUX_MODE_MASK) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK (0x10U) +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT (4U) +/*! SION - Software Input On Field. + * 0b1..Force input path of pad PMIC_STBY_REQ + * 0b0..Input Path is determined by functionality + */ +#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_SION_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_TEST_MODE - SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_POR_B - SW_PAD_CTL_PAD_POR_B SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_ONOFF - SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_WAKEUP - SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_PMIC_ON_REQ - SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_HYS_MASK) +/*! @} */ + +/*! @name SW_PAD_CTL_PAD_PMIC_STBY_REQ - SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */ +/*! @{ */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK (0x1U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT (0U) +/*! SRE - Slew Rate Field + * 0b0..Slow Slew Rate + * 0b1..Fast Slew Rate + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SRE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK (0x38U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT (3U) +/*! DSE - Drive Strength Field + * 0b000..output driver disabled; + * 0b001..R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + * 0b010..R0/2 + * 0b011..R0/3 + * 0b100..R0/4 + * 0b101..R0/5 + * 0b110..R0/6 + * 0b111..R0/7 + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DSE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK (0xC0U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT (6U) +/*! SPEED - Speed Field + * 0b10..medium(100MHz) + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_SPEED_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK (0x800U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT (11U) +/*! ODE - Open Drain Enable Field + * 0b0..Open Drain Disabled + * 0b1..Open Drain Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_ODE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK (0x1000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT (12U) +/*! PKE - Pull / Keep Enable Field + * 0b0..Pull/Keeper Disabled + * 0b1..Pull/Keeper Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PKE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK (0x2000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT (13U) +/*! PUE - Pull / Keep Select Field + * 0b0..Keeper + * 0b1..Pull + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUE_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK (0xC000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT (14U) +/*! PUS - Pull Up / Down Config. Field + * 0b00..100K Ohm Pull Down + * 0b01..47K Ohm Pull Up + * 0b10..100K Ohm Pull Up + * 0b11..22K Ohm Pull Up + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_PUS_MASK) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK (0x10000U) +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT (16U) +/*! HYS - Hyst. Enable Field + * 0b0..Hysteresis Disabled + * 0b1..Hysteresis Enabled + */ +#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_HYS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group IOMUXC_SNVS_Register_Masks */ + + +/* IOMUXC_SNVS - Peripheral instance base addresses */ +/** Peripheral IOMUXC_SNVS base address */ +#define IOMUXC_SNVS_BASE (0x400A8000u) +/** Peripheral IOMUXC_SNVS base pointer */ +#define IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE) +/** Array initializer of IOMUXC_SNVS peripheral base addresses */ +#define IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE } +/** Array initializer of IOMUXC_SNVS peripheral base pointers */ +#define IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS } + +/*! + * @} + */ /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS_GPR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_GPR_Peripheral_Access_Layer IOMUXC_SNVS_GPR Peripheral Access Layer + * @{ + */ + +/** IOMUXC_SNVS_GPR - Register Layout Typedef */ +typedef struct { + uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ + uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */ + uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ + __IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */ +} IOMUXC_SNVS_GPR_Type; + +/* ---------------------------------------------------------------------------- + -- IOMUXC_SNVS_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_SNVS_GPR_Register_Masks IOMUXC_SNVS_GPR Register Masks + * @{ + */ + +/*! @name GPR3 - GPR3 General Purpose Register */ +/*! @{ */ +#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK (0x1U) +#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT (0U) +#define IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_LPSR_MODE_ENABLE_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK (0x2U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT (1U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STATUS_CAPT_CLR_MASK) +#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK (0xCU) +#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT (2U) +#define IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_POR_PULL_TYPE_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK (0x10000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT (16U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_IN_LOW_VOL_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK (0x20000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT (17U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_CUR_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK (0x40000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT (18U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_OVER_VOL_MASK) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK (0x80000U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT (19U) +#define IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_DCDC_STS_DC_OK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group IOMUXC_SNVS_GPR_Register_Masks */ + + +/* IOMUXC_SNVS_GPR - Peripheral instance base addresses */ +/** Peripheral IOMUXC_SNVS_GPR base address */ +#define IOMUXC_SNVS_GPR_BASE (0x400A4000u) +/** Peripheral IOMUXC_SNVS_GPR base pointer */ +#define IOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE) +/** Array initializer of IOMUXC_SNVS_GPR peripheral base addresses */ +#define IOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE } +/** Array initializer of IOMUXC_SNVS_GPR peripheral base pointers */ +#define IOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR } + +/*! + * @} + */ /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- KPP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer + * @{ + */ + +/** KPP - Register Layout Typedef */ +typedef struct { + __IO uint16_t KPCR; /**< Keypad Control Register, offset: 0x0 */ + __IO uint16_t KPSR; /**< Keypad Status Register, offset: 0x2 */ + __IO uint16_t KDDR; /**< Keypad Data Direction Register, offset: 0x4 */ + __IO uint16_t KPDR; /**< Keypad Data Register, offset: 0x6 */ +} KPP_Type; + +/* ---------------------------------------------------------------------------- + -- KPP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Register_Masks KPP Register Masks + * @{ + */ + +/*! @name KPCR - Keypad Control Register */ +/*! @{ */ +#define KPP_KPCR_KRE_MASK (0xFFU) +#define KPP_KPCR_KRE_SHIFT (0U) +/*! KRE + * 0b00000000..Row is not included in the keypad key press detect. + * 0b00000001..Row is included in the keypad key press detect. + */ +#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK) +#define KPP_KPCR_KCO_MASK (0xFF00U) +#define KPP_KPCR_KCO_SHIFT (8U) +/*! KCO + * 0b00000000..Column strobe output is totem pole drive. + * 0b00000001..Column strobe output is open drain. + */ +#define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK) +/*! @} */ + +/*! @name KPSR - Keypad Status Register */ +/*! @{ */ +#define KPP_KPSR_KPKD_MASK (0x1U) +#define KPP_KPSR_KPKD_SHIFT (0U) +/*! KPKD + * 0b0..No key presses detected + * 0b1..A key has been depressed + */ +#define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK) +#define KPP_KPSR_KPKR_MASK (0x2U) +#define KPP_KPSR_KPKR_SHIFT (1U) +/*! KPKR + * 0b0..No key release detected + * 0b1..All keys have been released + */ +#define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK) +#define KPP_KPSR_KDSC_MASK (0x4U) +#define KPP_KPSR_KDSC_SHIFT (2U) +/*! KDSC + * 0b0..No effect + * 0b1..Set bits that clear the keypad depress synchronizer chain + */ +#define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK) +#define KPP_KPSR_KRSS_MASK (0x8U) +#define KPP_KPSR_KRSS_SHIFT (3U) +/*! KRSS + * 0b0..No effect + * 0b1..Set bits which sets keypad release synchronizer chain + */ +#define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK) +#define KPP_KPSR_KDIE_MASK (0x100U) +#define KPP_KPSR_KDIE_SHIFT (8U) +/*! KDIE + * 0b0..No interrupt request is generated when KPKD is set. + * 0b1..An interrupt request is generated when KPKD is set. + */ +#define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK) +#define KPP_KPSR_KRIE_MASK (0x200U) +#define KPP_KPSR_KRIE_SHIFT (9U) +/*! KRIE + * 0b0..No interrupt request is generated when KPKR is set. + * 0b1..An interrupt request is generated when KPKR is set. + */ +#define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK) +/*! @} */ + +/*! @name KDDR - Keypad Data Direction Register */ +/*! @{ */ +#define KPP_KDDR_KRDD_MASK (0xFFU) +#define KPP_KDDR_KRDD_SHIFT (0U) +/*! KRDD + * 0b00000000..ROWn pin configured as an input. + * 0b00000001..ROWn pin configured as an output. + */ +#define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK) +#define KPP_KDDR_KCDD_MASK (0xFF00U) +#define KPP_KDDR_KCDD_SHIFT (8U) +/*! KCDD + * 0b00000000..COLn pin is configured as an input. + * 0b00000001..COLn pin is configured as an output. + */ +#define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK) +/*! @} */ + +/*! @name KPDR - Keypad Data Register */ +/*! @{ */ +#define KPP_KPDR_KRD_MASK (0xFFU) +#define KPP_KPDR_KRD_SHIFT (0U) +#define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK) +#define KPP_KPDR_KCD_MASK (0xFF00U) +#define KPP_KPDR_KCD_SHIFT (8U) +#define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group KPP_Register_Masks */ + + +/* KPP - Peripheral instance base addresses */ +/** Peripheral KPP base address */ +#define KPP_BASE (0x401FC000u) +/** Peripheral KPP base pointer */ +#define KPP ((KPP_Type *)KPP_BASE) +/** Array initializer of KPP peripheral base addresses */ +#define KPP_BASE_ADDRS { KPP_BASE } +/** Array initializer of KPP peripheral base pointers */ +#define KPP_BASE_PTRS { KPP } +/** Interrupt vectors for the KPP peripheral type */ +#define KPP_IRQS { KPP_IRQn } + +/*! + * @} + */ /* end of group KPP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPI2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer + * @{ + */ + +/** LPI2C - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */ + __IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */ + __IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */ + __IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */ + __IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */ + __IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */ + __IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */ + uint8_t RESERVED_4[4]; + __IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */ + __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ + __O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */ + uint8_t RESERVED_5[12]; + __I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */ + uint8_t RESERVED_6[156]; + __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ + __IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */ + __IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */ + __IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */ + uint8_t RESERVED_7[4]; + __IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */ + __IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */ + uint8_t RESERVED_8[20]; + __IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */ + uint8_t RESERVED_9[12]; + __I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */ + __IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */ + uint8_t RESERVED_10[8]; + __O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */ + uint8_t RESERVED_11[12]; + __I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */ +} LPI2C_Type; + +/* ---------------------------------------------------------------------------- + -- LPI2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Register_Masks LPI2C Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) +#define LPI2C_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000010..Master only, with standard feature set + * 0b0000000000000011..Master and slave, with standard feature set + */ +#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) +#define LPI2C_VERID_MINOR_MASK (0xFF0000U) +#define LPI2C_VERID_MINOR_SHIFT (16U) +#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) +#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) +#define LPI2C_VERID_MAJOR_SHIFT (24U) +#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) +#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) +#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) +#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) +#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) +#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) +/*! @} */ + +/*! @name MCR - Master Control Register */ +/*! @{ */ +#define LPI2C_MCR_MEN_MASK (0x1U) +#define LPI2C_MCR_MEN_SHIFT (0U) +/*! MEN - Master Enable + * 0b0..Master logic is disabled + * 0b1..Master logic is enabled + */ +#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) +#define LPI2C_MCR_RST_MASK (0x2U) +#define LPI2C_MCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Master logic is not reset + * 0b1..Master logic is reset + */ +#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) +#define LPI2C_MCR_DOZEN_MASK (0x4U) +#define LPI2C_MCR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze mode enable + * 0b0..Master is enabled in Doze mode + * 0b1..Master is disabled in Doze mode + */ +#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) +#define LPI2C_MCR_DBGEN_MASK (0x8U) +#define LPI2C_MCR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Master is disabled in debug mode + * 0b1..Master is enabled in debug mode + */ +#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) +#define LPI2C_MCR_RTF_MASK (0x100U) +#define LPI2C_MCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Transmit FIFO is reset + */ +#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) +#define LPI2C_MCR_RRF_MASK (0x200U) +#define LPI2C_MCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Receive FIFO is reset + */ +#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) +/*! @} */ + +/*! @name MSR - Master Status Register */ +/*! @{ */ +#define LPI2C_MSR_TDF_MASK (0x1U) +#define LPI2C_MSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data is not requested + * 0b1..Transmit data is requested + */ +#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) +#define LPI2C_MSR_RDF_MASK (0x2U) +#define LPI2C_MSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive Data is not ready + * 0b1..Receive data is ready + */ +#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) +#define LPI2C_MSR_EPF_MASK (0x100U) +#define LPI2C_MSR_EPF_SHIFT (8U) +/*! EPF - End Packet Flag + * 0b0..Master has not generated a STOP or Repeated START condition + * 0b1..Master has generated a STOP or Repeated START condition + */ +#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) +#define LPI2C_MSR_SDF_MASK (0x200U) +#define LPI2C_MSR_SDF_SHIFT (9U) +/*! SDF - STOP Detect Flag + * 0b0..Master has not generated a STOP condition + * 0b1..Master has generated a STOP condition + */ +#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) +#define LPI2C_MSR_NDF_MASK (0x400U) +#define LPI2C_MSR_NDF_SHIFT (10U) +/*! NDF - NACK Detect Flag + * 0b0..Unexpected NACK was not detected + * 0b1..Unexpected NACK was detected + */ +#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) +#define LPI2C_MSR_ALF_MASK (0x800U) +#define LPI2C_MSR_ALF_SHIFT (11U) +/*! ALF - Arbitration Lost Flag + * 0b0..Master has not lost arbitration + * 0b1..Master has lost arbitration + */ +#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) +#define LPI2C_MSR_FEF_MASK (0x1000U) +#define LPI2C_MSR_FEF_SHIFT (12U) +/*! FEF - FIFO Error Flag + * 0b0..No error + * 0b1..Master sending or receiving data without a START condition + */ +#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) +#define LPI2C_MSR_PLTF_MASK (0x2000U) +#define LPI2C_MSR_PLTF_SHIFT (13U) +/*! PLTF - Pin Low Timeout Flag + * 0b0..Pin low timeout has not occurred or is disabled + * 0b1..Pin low timeout has occurred + */ +#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) +#define LPI2C_MSR_DMF_MASK (0x4000U) +#define LPI2C_MSR_DMF_SHIFT (14U) +/*! DMF - Data Match Flag + * 0b0..Have not received matching data + * 0b1..Have received matching data + */ +#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) +#define LPI2C_MSR_MBF_MASK (0x1000000U) +#define LPI2C_MSR_MBF_SHIFT (24U) +/*! MBF - Master Busy Flag + * 0b0..I2C Master is idle + * 0b1..I2C Master is busy + */ +#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) +#define LPI2C_MSR_BBF_MASK (0x2000000U) +#define LPI2C_MSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..I2C Bus is idle + * 0b1..I2C Bus is busy + */ +#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) +/*! @} */ + +/*! @name MIER - Master Interrupt Enable Register */ +/*! @{ */ +#define LPI2C_MIER_TDIE_MASK (0x1U) +#define LPI2C_MIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) +#define LPI2C_MIER_RDIE_MASK (0x2U) +#define LPI2C_MIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) +#define LPI2C_MIER_EPIE_MASK (0x100U) +#define LPI2C_MIER_EPIE_SHIFT (8U) +/*! EPIE - End Packet Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) +#define LPI2C_MIER_SDIE_MASK (0x200U) +#define LPI2C_MIER_SDIE_SHIFT (9U) +/*! SDIE - STOP Detect Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) +#define LPI2C_MIER_NDIE_MASK (0x400U) +#define LPI2C_MIER_NDIE_SHIFT (10U) +/*! NDIE - NACK Detect Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) +#define LPI2C_MIER_ALIE_MASK (0x800U) +#define LPI2C_MIER_ALIE_SHIFT (11U) +/*! ALIE - Arbitration Lost Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) +#define LPI2C_MIER_FEIE_MASK (0x1000U) +#define LPI2C_MIER_FEIE_SHIFT (12U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Enabled + * 0b1..Disabled + */ +#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) +#define LPI2C_MIER_PLTIE_MASK (0x2000U) +#define LPI2C_MIER_PLTIE_SHIFT (13U) +/*! PLTIE - Pin Low Timeout Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) +#define LPI2C_MIER_DMIE_MASK (0x4000U) +#define LPI2C_MIER_DMIE_SHIFT (14U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) +/*! @} */ + +/*! @name MDER - Master DMA Enable Register */ +/*! @{ */ +#define LPI2C_MDER_TDDE_MASK (0x1U) +#define LPI2C_MDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) +#define LPI2C_MDER_RDDE_MASK (0x2U) +#define LPI2C_MDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) +/*! @} */ + +/*! @name MCFGR0 - Master Configuration Register 0 */ +/*! @{ */ +#define LPI2C_MCFGR0_HREN_MASK (0x1U) +#define LPI2C_MCFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Host request input is disabled + * 0b1..Host request input is enabled + */ +#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) +#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) +#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) +#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) +#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is pin HREQ + * 0b1..Host request input is input trigger + */ +#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) +#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) +#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Circular FIFO is disabled + * 0b1..Circular FIFO is enabled + */ +#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) +#define LPI2C_MCFGR0_RDMO_MASK (0x200U) +#define LPI2C_MCFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO + * 0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set + */ +#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) +/*! @} */ + +/*! @name MCFGR1 - Master Configuration Register 1 */ +/*! @{ */ +#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) +#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) +/*! PRESCALE - Prescaler + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) +#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) +#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) +/*! AUTOSTOP - Automatic STOP Generation + * 0b0..No effect + * 0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy + */ +#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) +#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) +#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) +/*! IGNACK - IGNACK + * 0b0..LPI2C Master will receive ACK and NACK normally + * 0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK + */ +#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) +#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) +#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) +/*! TIMECFG - Timeout Configuration + * 0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout + * 0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout + */ +#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) +#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) +#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1) + * 0b011..Match is enabled (any data word equals MATCH0 OR MATCH1) + * 0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) + * 0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) + * 0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) + * 0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) + */ +#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) +#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) +#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b000..2-pin open drain mode + * 0b001..2-pin output only mode (ultra-fast mode) + * 0b010..2-pin push-pull mode + * 0b011..4-pin push-pull mode + * 0b100..2-pin open drain mode with separate LPI2C slave + * 0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave + * 0b110..2-pin push-pull mode with separate LPI2C slave + * 0b111..4-pin push-pull mode (inverted outputs) + */ +#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) +/*! @} */ + +/*! @name MCFGR2 - Master Configuration Register 2 */ +/*! @{ */ +#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) +#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) +#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) +#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) +#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) +#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) +#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name MCFGR3 - Master Configuration Register 3 */ +/*! @{ */ +#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) +#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) +#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) +/*! @} */ + +/*! @name MDMR - Master Data Match Register */ +/*! @{ */ +#define LPI2C_MDMR_MATCH0_MASK (0xFFU) +#define LPI2C_MDMR_MATCH0_SHIFT (0U) +#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) +#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) +#define LPI2C_MDMR_MATCH1_SHIFT (16U) +#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) +/*! @} */ + +/*! @name MCCR0 - Master Clock Configuration Register 0 */ +/*! @{ */ +#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR0_CLKLO_SHIFT (0U) +#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) +#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR0_CLKHI_SHIFT (8U) +#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) +#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) +#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) +#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR0_DATAVD_SHIFT (24U) +#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) +/*! @} */ + +/*! @name MCCR1 - Master Clock Configuration Register 1 */ +/*! @{ */ +#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR1_CLKLO_SHIFT (0U) +#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) +#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR1_CLKHI_SHIFT (8U) +#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) +#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) +#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) +#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR1_DATAVD_SHIFT (24U) +#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) +/*! @} */ + +/*! @name MFCR - Master FIFO Control Register */ +/*! @{ */ +#define LPI2C_MFCR_TXWATER_MASK (0x3U) +#define LPI2C_MFCR_TXWATER_SHIFT (0U) +#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) +#define LPI2C_MFCR_RXWATER_MASK (0x30000U) +#define LPI2C_MFCR_RXWATER_SHIFT (16U) +#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) +/*! @} */ + +/*! @name MFSR - Master FIFO Status Register */ +/*! @{ */ +#define LPI2C_MFSR_TXCOUNT_MASK (0x7U) +#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) +#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) +#define LPI2C_MFSR_RXCOUNT_MASK (0x70000U) +#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) +#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name MTDR - Master Transmit Data Register */ +/*! @{ */ +#define LPI2C_MTDR_DATA_MASK (0xFFU) +#define LPI2C_MTDR_DATA_SHIFT (0U) +#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) +#define LPI2C_MTDR_CMD_MASK (0x700U) +#define LPI2C_MTDR_CMD_SHIFT (8U) +/*! CMD - Command Data + * 0b000..Transmit DATA[7:0] + * 0b001..Receive (DATA[7:0] + 1) bytes + * 0b010..Generate STOP condition + * 0b011..Receive and discard (DATA[7:0] + 1) bytes + * 0b100..Generate (repeated) START and transmit address in DATA[7:0] + * 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. + * 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode + * 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. + */ +#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) +/*! @} */ + +/*! @name MRDR - Master Receive Data Register */ +/*! @{ */ +#define LPI2C_MRDR_DATA_MASK (0xFFU) +#define LPI2C_MRDR_DATA_SHIFT (0U) +#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) +#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..Receive FIFO is not empty + * 0b1..Receive FIFO is empty + */ +#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) +/*! @} */ + +/*! @name SCR - Slave Control Register */ +/*! @{ */ +#define LPI2C_SCR_SEN_MASK (0x1U) +#define LPI2C_SCR_SEN_SHIFT (0U) +/*! SEN - Slave Enable + * 0b0..I2C Slave mode is disabled + * 0b1..I2C Slave mode is enabled + */ +#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) +#define LPI2C_SCR_RST_MASK (0x2U) +#define LPI2C_SCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Slave mode logic is not reset + * 0b1..Slave mode logic is reset + */ +#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) +#define LPI2C_SCR_FILTEN_MASK (0x10U) +#define LPI2C_SCR_FILTEN_SHIFT (4U) +/*! FILTEN - Filter Enable + * 0b0..Disable digital filter and output delay counter for slave mode + * 0b1..Enable digital filter and output delay counter for slave mode + */ +#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) +#define LPI2C_SCR_FILTDZ_MASK (0x20U) +#define LPI2C_SCR_FILTDZ_SHIFT (5U) +/*! FILTDZ - Filter Doze Enable + * 0b0..Filter remains enabled in Doze mode + * 0b1..Filter is disabled in Doze mode + */ +#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) +#define LPI2C_SCR_RTF_MASK (0x100U) +#define LPI2C_SCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Transmit Data Register is now empty + */ +#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) +#define LPI2C_SCR_RRF_MASK (0x200U) +#define LPI2C_SCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Receive Data Register is now empty + */ +#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) +/*! @} */ + +/*! @name SSR - Slave Status Register */ +/*! @{ */ +#define LPI2C_SSR_TDF_MASK (0x1U) +#define LPI2C_SSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ +#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) +#define LPI2C_SSR_RDF_MASK (0x2U) +#define LPI2C_SSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data is not ready + * 0b1..Receive data is ready + */ +#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) +#define LPI2C_SSR_AVF_MASK (0x4U) +#define LPI2C_SSR_AVF_SHIFT (2U) +/*! AVF - Address Valid Flag + * 0b0..Address Status Register is not valid + * 0b1..Address Status Register is valid + */ +#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) +#define LPI2C_SSR_TAF_MASK (0x8U) +#define LPI2C_SSR_TAF_SHIFT (3U) +/*! TAF - Transmit ACK Flag + * 0b0..Transmit ACK/NACK is not required + * 0b1..Transmit ACK/NACK is required + */ +#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) +#define LPI2C_SSR_RSF_MASK (0x100U) +#define LPI2C_SSR_RSF_SHIFT (8U) +/*! RSF - Repeated Start Flag + * 0b0..Slave has not detected a Repeated START condition + * 0b1..Slave has detected a Repeated START condition + */ +#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) +#define LPI2C_SSR_SDF_MASK (0x200U) +#define LPI2C_SSR_SDF_SHIFT (9U) +/*! SDF - STOP Detect Flag + * 0b0..Slave has not detected a STOP condition + * 0b1..Slave has detected a STOP condition + */ +#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) +#define LPI2C_SSR_BEF_MASK (0x400U) +#define LPI2C_SSR_BEF_SHIFT (10U) +/*! BEF - Bit Error Flag + * 0b0..Slave has not detected a bit error + * 0b1..Slave has detected a bit error + */ +#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) +#define LPI2C_SSR_FEF_MASK (0x800U) +#define LPI2C_SSR_FEF_SHIFT (11U) +/*! FEF - FIFO Error Flag + * 0b0..FIFO underflow or overflow was not detected + * 0b1..FIFO underflow or overflow was detected + */ +#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) +#define LPI2C_SSR_AM0F_MASK (0x1000U) +#define LPI2C_SSR_AM0F_SHIFT (12U) +/*! AM0F - Address Match 0 Flag + * 0b0..Have not received an ADDR0 matching address + * 0b1..Have received an ADDR0 matching address + */ +#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) +#define LPI2C_SSR_AM1F_MASK (0x2000U) +#define LPI2C_SSR_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Flag + * 0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address + * 0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address + */ +#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) +#define LPI2C_SSR_GCF_MASK (0x4000U) +#define LPI2C_SSR_GCF_SHIFT (14U) +/*! GCF - General Call Flag + * 0b0..Slave has not detected the General Call Address or the General Call Address is disabled + * 0b1..Slave has detected the General Call Address + */ +#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) +#define LPI2C_SSR_SARF_MASK (0x8000U) +#define LPI2C_SSR_SARF_SHIFT (15U) +/*! SARF - SMBus Alert Response Flag + * 0b0..SMBus Alert Response is disabled or not detected + * 0b1..SMBus Alert Response is enabled and detected + */ +#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) +#define LPI2C_SSR_SBF_MASK (0x1000000U) +#define LPI2C_SSR_SBF_SHIFT (24U) +/*! SBF - Slave Busy Flag + * 0b0..I2C Slave is idle + * 0b1..I2C Slave is busy + */ +#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) +#define LPI2C_SSR_BBF_MASK (0x2000000U) +#define LPI2C_SSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..I2C Bus is idle + * 0b1..I2C Bus is busy + */ +#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) +/*! @} */ + +/*! @name SIER - Slave Interrupt Enable Register */ +/*! @{ */ +#define LPI2C_SIER_TDIE_MASK (0x1U) +#define LPI2C_SIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) +#define LPI2C_SIER_RDIE_MASK (0x2U) +#define LPI2C_SIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) +#define LPI2C_SIER_AVIE_MASK (0x4U) +#define LPI2C_SIER_AVIE_SHIFT (2U) +/*! AVIE - Address Valid Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) +#define LPI2C_SIER_TAIE_MASK (0x8U) +#define LPI2C_SIER_TAIE_SHIFT (3U) +/*! TAIE - Transmit ACK Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) +#define LPI2C_SIER_RSIE_MASK (0x100U) +#define LPI2C_SIER_RSIE_SHIFT (8U) +/*! RSIE - Repeated Start Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) +#define LPI2C_SIER_SDIE_MASK (0x200U) +#define LPI2C_SIER_SDIE_SHIFT (9U) +/*! SDIE - STOP Detect Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) +#define LPI2C_SIER_BEIE_MASK (0x400U) +#define LPI2C_SIER_BEIE_SHIFT (10U) +/*! BEIE - Bit Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) +#define LPI2C_SIER_FEIE_MASK (0x800U) +#define LPI2C_SIER_FEIE_SHIFT (11U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) +#define LPI2C_SIER_AM0IE_MASK (0x1000U) +#define LPI2C_SIER_AM0IE_SHIFT (12U) +/*! AM0IE - Address Match 0 Interrupt Enable + * 0b0..Enabled + * 0b1..Disabled + */ +#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) +#define LPI2C_SIER_AM1F_MASK (0x2000U) +#define LPI2C_SIER_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) +#define LPI2C_SIER_GCIE_MASK (0x4000U) +#define LPI2C_SIER_GCIE_SHIFT (14U) +/*! GCIE - General Call Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) +#define LPI2C_SIER_SARIE_MASK (0x8000U) +#define LPI2C_SIER_SARIE_SHIFT (15U) +/*! SARIE - SMBus Alert Response Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) +/*! @} */ + +/*! @name SDER - Slave DMA Enable Register */ +/*! @{ */ +#define LPI2C_SDER_TDDE_MASK (0x1U) +#define LPI2C_SDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) +#define LPI2C_SDER_RDDE_MASK (0x2U) +#define LPI2C_SDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) +#define LPI2C_SDER_AVDE_MASK (0x4U) +#define LPI2C_SDER_AVDE_SHIFT (2U) +/*! AVDE - Address Valid DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) +/*! @} */ + +/*! @name SCFGR1 - Slave Configuration Register 1 */ +/*! @{ */ +#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) +#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) +/*! ADRSTALL - Address SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ +#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) +#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) +#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) +/*! RXSTALL - RX SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ +#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) +#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) +#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) +/*! TXDSTALL - TX Data SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ +#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) +#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) +#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) +/*! ACKSTALL - ACK SCL Stall + * 0b0..Clock stretching is disabled + * 0b1..Clock stretching is enabled + */ +#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) +#define LPI2C_SCFGR1_GCEN_MASK (0x100U) +#define LPI2C_SCFGR1_GCEN_SHIFT (8U) +/*! GCEN - General Call Enable + * 0b0..General Call address is disabled + * 0b1..General Call address is enabled + */ +#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) +#define LPI2C_SCFGR1_SAEN_MASK (0x200U) +#define LPI2C_SCFGR1_SAEN_SHIFT (9U) +/*! SAEN - SMBus Alert Enable + * 0b0..Disables match on SMBus Alert + * 0b1..Enables match on SMBus Alert + */ +#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) +#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) +#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) +/*! TXCFG - Transmit Flag Configuration + * 0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty + * 0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty + */ +#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) +#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) +#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) +/*! RXCFG - Receive Data Configuration + * 0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). + * 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address + * Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid + * flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). + */ +#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) +#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) +#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) +/*! IGNACK - Ignore NACK + * 0b0..Slave will end transfer when NACK is detected + * 0b1..Slave will not end transfer when NACK detected + */ +#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) +#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) +#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) +/*! HSMEN - High Speed Mode Enable + * 0b0..Disables detection of HS-mode master code + * 0b1..Enables detection of HS-mode master code + */ +#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) +#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) +#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) +/*! ADDRCFG - Address Configuration + * 0b000..Address match 0 (7-bit) + * 0b001..Address match 0 (10-bit) + * 0b010..Address match 0 (7-bit) or Address match 1 (7-bit) + * 0b011..Address match 0 (10-bit) or Address match 1 (10-bit) + * 0b100..Address match 0 (7-bit) or Address match 1 (10-bit) + * 0b101..Address match 0 (10-bit) or Address match 1 (7-bit) + * 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit) + * 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit) + */ +#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) +/*! @} */ + +/*! @name SCFGR2 - Slave Configuration Register 2 */ +/*! @{ */ +#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) +#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) +#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) +#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) +#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) +#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) +#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) +#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) +#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) +#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name SAMR - Slave Address Match Register */ +/*! @{ */ +#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) +#define LPI2C_SAMR_ADDR0_SHIFT (1U) +#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) +#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) +#define LPI2C_SAMR_ADDR1_SHIFT (17U) +#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) +/*! @} */ + +/*! @name SASR - Slave Address Status Register */ +/*! @{ */ +#define LPI2C_SASR_RADDR_MASK (0x7FFU) +#define LPI2C_SASR_RADDR_SHIFT (0U) +#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) +#define LPI2C_SASR_ANV_MASK (0x4000U) +#define LPI2C_SASR_ANV_SHIFT (14U) +/*! ANV - Address Not Valid + * 0b0..Received Address (RADDR) is valid + * 0b1..Received Address (RADDR) is not valid + */ +#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) +/*! @} */ + +/*! @name STAR - Slave Transmit ACK Register */ +/*! @{ */ +#define LPI2C_STAR_TXNACK_MASK (0x1U) +#define LPI2C_STAR_TXNACK_SHIFT (0U) +/*! TXNACK - Transmit NACK + * 0b0..Write a Transmit ACK for each received word + * 0b1..Write a Transmit NACK for each received word + */ +#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) +/*! @} */ + +/*! @name STDR - Slave Transmit Data Register */ +/*! @{ */ +#define LPI2C_STDR_DATA_MASK (0xFFU) +#define LPI2C_STDR_DATA_SHIFT (0U) +#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) +/*! @} */ + +/*! @name SRDR - Slave Receive Data Register */ +/*! @{ */ +#define LPI2C_SRDR_DATA_MASK (0xFFU) +#define LPI2C_SRDR_DATA_SHIFT (0U) +#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) +#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..The Receive Data Register is not empty + * 0b1..The Receive Data Register is empty + */ +#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) +#define LPI2C_SRDR_SOF_MASK (0x8000U) +#define LPI2C_SRDR_SOF_SHIFT (15U) +/*! SOF - Start Of Frame + * 0b0..Indicates this is not the first data word since a (repeated) START or STOP condition + * 0b1..Indicates this is the first data word since a (repeated) START or STOP condition + */ +#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPI2C_Register_Masks */ + + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE (0x403F0000u) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Peripheral LPI2C2 base address */ +#define LPI2C2_BASE (0x403F4000u) +/** Peripheral LPI2C2 base pointer */ +#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) +/** Peripheral LPI2C3 base address */ +#define LPI2C3_BASE (0x403F8000u) +/** Peripheral LPI2C3 base pointer */ +#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) +/** Peripheral LPI2C4 base address */ +#define LPI2C4_BASE (0x403FC000u) +/** Peripheral LPI2C4 base pointer */ +#define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE) +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE } +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4 } +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn } + +/*! + * @} + */ /* end of group LPI2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer + * @{ + */ + +/** LPSPI - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CR; /**< Control Register, offset: 0x10 */ + __IO uint32_t SR; /**< Status Register, offset: 0x14 */ + __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */ + __IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */ + __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ + uint8_t RESERVED_1[8]; + __IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */ + __IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */ + uint8_t RESERVED_2[8]; + __IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ + uint8_t RESERVED_3[20]; + __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x58 */ + __I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */ + __IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */ + __O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */ + uint8_t RESERVED_4[8]; + __I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */ + __I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */ +} LPSPI_Type; + +/* ---------------------------------------------------------------------------- + -- LPSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Register_Masks LPSPI Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define LPSPI_VERID_FEATURE_MASK (0xFFFFU) +#define LPSPI_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Module Identification Number + * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. + */ +#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) +#define LPSPI_VERID_MINOR_MASK (0xFF0000U) +#define LPSPI_VERID_MINOR_SHIFT (16U) +#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) +#define LPSPI_VERID_MAJOR_MASK (0xFF000000U) +#define LPSPI_VERID_MAJOR_SHIFT (24U) +#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define LPSPI_PARAM_TXFIFO_MASK (0xFFU) +#define LPSPI_PARAM_TXFIFO_SHIFT (0U) +#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) +#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) +#define LPSPI_PARAM_RXFIFO_SHIFT (8U) +#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) +#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) +#define LPSPI_PARAM_PCSNUM_SHIFT (16U) +#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) +/*! @} */ + +/*! @name CR - Control Register */ +/*! @{ */ +#define LPSPI_CR_MEN_MASK (0x1U) +#define LPSPI_CR_MEN_SHIFT (0U) +/*! MEN - Module Enable + * 0b0..Module is disabled + * 0b1..Module is enabled + */ +#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) +#define LPSPI_CR_RST_MASK (0x2U) +#define LPSPI_CR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Module is not reset + * 0b1..Module is reset + */ +#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) +#define LPSPI_CR_DOZEN_MASK (0x4U) +#define LPSPI_CR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze mode enable + * 0b0..Module is enabled in Doze mode + * 0b1..Module is disabled in Doze mode + */ +#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) +#define LPSPI_CR_DBGEN_MASK (0x8U) +#define LPSPI_CR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Module is disabled in debug mode + * 0b1..Module is enabled in debug mode + */ +#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) +#define LPSPI_CR_RTF_MASK (0x100U) +#define LPSPI_CR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Transmit FIFO is reset + */ +#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) +#define LPSPI_CR_RRF_MASK (0x200U) +#define LPSPI_CR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Receive FIFO is reset + */ +#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) +/*! @} */ + +/*! @name SR - Status Register */ +/*! @{ */ +#define LPSPI_SR_TDF_MASK (0x1U) +#define LPSPI_SR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ +#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) +#define LPSPI_SR_RDF_MASK (0x2U) +#define LPSPI_SR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive Data is not ready + * 0b1..Receive data is ready + */ +#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) +#define LPSPI_SR_WCF_MASK (0x100U) +#define LPSPI_SR_WCF_SHIFT (8U) +/*! WCF - Word Complete Flag + * 0b0..Transfer of a received word has not yet completed + * 0b1..Transfer of a received word has completed + */ +#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) +#define LPSPI_SR_FCF_MASK (0x200U) +#define LPSPI_SR_FCF_SHIFT (9U) +/*! FCF - Frame Complete Flag + * 0b0..Frame transfer has not completed + * 0b1..Frame transfer has completed + */ +#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) +#define LPSPI_SR_TCF_MASK (0x400U) +#define LPSPI_SR_TCF_SHIFT (10U) +/*! TCF - Transfer Complete Flag + * 0b0..All transfers have not completed + * 0b1..All transfers have completed + */ +#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) +#define LPSPI_SR_TEF_MASK (0x800U) +#define LPSPI_SR_TEF_SHIFT (11U) +/*! TEF - Transmit Error Flag + * 0b0..Transmit FIFO underrun has not occurred + * 0b1..Transmit FIFO underrun has occurred + */ +#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) +#define LPSPI_SR_REF_MASK (0x1000U) +#define LPSPI_SR_REF_SHIFT (12U) +/*! REF - Receive Error Flag + * 0b0..Receive FIFO has not overflowed + * 0b1..Receive FIFO has overflowed + */ +#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) +#define LPSPI_SR_DMF_MASK (0x2000U) +#define LPSPI_SR_DMF_SHIFT (13U) +/*! DMF - Data Match Flag + * 0b0..Have not received matching data + * 0b1..Have received matching data + */ +#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) +#define LPSPI_SR_MBF_MASK (0x1000000U) +#define LPSPI_SR_MBF_SHIFT (24U) +/*! MBF - Module Busy Flag + * 0b0..LPSPI is idle + * 0b1..LPSPI is busy + */ +#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable Register */ +/*! @{ */ +#define LPSPI_IER_TDIE_MASK (0x1U) +#define LPSPI_IER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) +#define LPSPI_IER_RDIE_MASK (0x2U) +#define LPSPI_IER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) +#define LPSPI_IER_WCIE_MASK (0x100U) +#define LPSPI_IER_WCIE_SHIFT (8U) +/*! WCIE - Word Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) +#define LPSPI_IER_FCIE_MASK (0x200U) +#define LPSPI_IER_FCIE_SHIFT (9U) +/*! FCIE - Frame Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) +#define LPSPI_IER_TCIE_MASK (0x400U) +#define LPSPI_IER_TCIE_SHIFT (10U) +/*! TCIE - Transfer Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) +#define LPSPI_IER_TEIE_MASK (0x800U) +#define LPSPI_IER_TEIE_SHIFT (11U) +/*! TEIE - Transmit Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) +#define LPSPI_IER_REIE_MASK (0x1000U) +#define LPSPI_IER_REIE_SHIFT (12U) +/*! REIE - Receive Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) +#define LPSPI_IER_DMIE_MASK (0x2000U) +#define LPSPI_IER_DMIE_SHIFT (13U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) +/*! @} */ + +/*! @name DER - DMA Enable Register */ +/*! @{ */ +#define LPSPI_DER_TDDE_MASK (0x1U) +#define LPSPI_DER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) +#define LPSPI_DER_RDDE_MASK (0x2U) +#define LPSPI_DER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) +/*! @} */ + +/*! @name CFGR0 - Configuration Register 0 */ +/*! @{ */ +#define LPSPI_CFGR0_HREN_MASK (0x1U) +#define LPSPI_CFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Host request is disabled + * 0b1..Host request is enabled + */ +#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) +#define LPSPI_CFGR0_HRPOL_MASK (0x2U) +#define LPSPI_CFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) +#define LPSPI_CFGR0_HRSEL_MASK (0x4U) +#define LPSPI_CFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is the LPSPI_HREQ pin + * 0b1..Host request input is the input trigger + */ +#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) +#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) +#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Circular FIFO is disabled + * 0b1..Circular FIFO is enabled + */ +#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) +#define LPSPI_CFGR0_RDMO_MASK (0x200U) +#define LPSPI_CFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO as in normal operations + * 0b1..Received data is discarded unless the Data Match Flag (DMF) is set + */ +#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) +/*! @} */ + +/*! @name CFGR1 - Configuration Register 1 */ +/*! @{ */ +#define LPSPI_CFGR1_MASTER_MASK (0x1U) +#define LPSPI_CFGR1_MASTER_SHIFT (0U) +/*! MASTER - Master Mode + * 0b0..Slave mode + * 0b1..Master mode + */ +#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) +#define LPSPI_CFGR1_SAMPLE_MASK (0x2U) +#define LPSPI_CFGR1_SAMPLE_SHIFT (1U) +/*! SAMPLE - Sample Point + * 0b0..Input data is sampled on SCK edge + * 0b1..Input data is sampled on delayed SCK edge + */ +#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) +#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) +#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) +/*! AUTOPCS - Automatic PCS + * 0b0..Automatic PCS generation is disabled + * 0b1..Automatic PCS generation is enabled + */ +#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) +#define LPSPI_CFGR1_NOSTALL_MASK (0x8U) +#define LPSPI_CFGR1_NOSTALL_SHIFT (3U) +/*! NOSTALL - No Stall + * 0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full + * 0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur + */ +#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) +#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) +#define LPSPI_CFGR1_PCSPOL_SHIFT (8U) +/*! PCSPOL - Peripheral Chip Select Polarity + * 0b0000..The Peripheral Chip Select pin PCSx is active low + * 0b0001..The Peripheral Chip Select pin PCSx is active high + */ +#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) +#define LPSPI_CFGR1_MATCFG_MASK (0x70000U) +#define LPSPI_CFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) + * 0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) + * 0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st + * data word = MATCH0) * (2nd data word = MATCH1)] + * 0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., + * [(any data word = MATCH0) * (next data word = MATCH1)] + * 0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] + * 0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] + */ +#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) +#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) +#define LPSPI_CFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b00..SIN is used for input data and SOUT is used for output data + * 0b01..SIN is used for both input and output data + * 0b10..SOUT is used for both input and output data + * 0b11..SOUT is used for input data and SIN is used for output data + */ +#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) +#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) +#define LPSPI_CFGR1_OUTCFG_SHIFT (26U) +/*! OUTCFG - Output Config + * 0b0..Output data retains last value when chip select is negated + * 0b1..Output data is tristated when chip select is negated + */ +#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) +#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) +#define LPSPI_CFGR1_PCSCFG_SHIFT (27U) +/*! PCSCFG - Peripheral Chip Select Configuration + * 0b0..PCS[3:2] are enabled + * 0b1..PCS[3:2] are disabled + */ +#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) +/*! @} */ + +/*! @name DMR0 - Data Match Register 0 */ +/*! @{ */ +#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) +#define LPSPI_DMR0_MATCH0_SHIFT (0U) +#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) +/*! @} */ + +/*! @name DMR1 - Data Match Register 1 */ +/*! @{ */ +#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) +#define LPSPI_DMR1_MATCH1_SHIFT (0U) +#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) +/*! @} */ + +/*! @name CCR - Clock Configuration Register */ +/*! @{ */ +#define LPSPI_CCR_SCKDIV_MASK (0xFFU) +#define LPSPI_CCR_SCKDIV_SHIFT (0U) +#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) +#define LPSPI_CCR_DBT_MASK (0xFF00U) +#define LPSPI_CCR_DBT_SHIFT (8U) +#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) +#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) +#define LPSPI_CCR_PCSSCK_SHIFT (16U) +#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) +#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) +#define LPSPI_CCR_SCKPCS_SHIFT (24U) +#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) +/*! @} */ + +/*! @name FCR - FIFO Control Register */ +/*! @{ */ +#define LPSPI_FCR_TXWATER_MASK (0xFU) +#define LPSPI_FCR_TXWATER_SHIFT (0U) +#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) +#define LPSPI_FCR_RXWATER_MASK (0xF0000U) +#define LPSPI_FCR_RXWATER_SHIFT (16U) +#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) +/*! @} */ + +/*! @name FSR - FIFO Status Register */ +/*! @{ */ +#define LPSPI_FSR_TXCOUNT_MASK (0x1FU) +#define LPSPI_FSR_TXCOUNT_SHIFT (0U) +#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) +#define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U) +#define LPSPI_FSR_RXCOUNT_SHIFT (16U) +#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name TCR - Transmit Command Register */ +/*! @{ */ +#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) +#define LPSPI_TCR_FRAMESZ_SHIFT (0U) +#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) +#define LPSPI_TCR_WIDTH_MASK (0x30000U) +#define LPSPI_TCR_WIDTH_SHIFT (16U) +/*! WIDTH - Transfer Width + * 0b00..1 bit transfer + * 0b01..2 bit transfer + * 0b10..4 bit transfer + * 0b11..Reserved + */ +#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) +#define LPSPI_TCR_TXMSK_MASK (0x40000U) +#define LPSPI_TCR_TXMSK_SHIFT (18U) +/*! TXMSK - Transmit Data Mask + * 0b0..Normal transfer + * 0b1..Mask transmit data + */ +#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) +#define LPSPI_TCR_RXMSK_MASK (0x80000U) +#define LPSPI_TCR_RXMSK_SHIFT (19U) +/*! RXMSK - Receive Data Mask + * 0b0..Normal transfer + * 0b1..Receive data is masked + */ +#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) +#define LPSPI_TCR_CONTC_MASK (0x100000U) +#define LPSPI_TCR_CONTC_SHIFT (20U) +/*! CONTC - Continuing Command + * 0b0..Command word for start of new transfer + * 0b1..Command word for continuing transfer + */ +#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) +#define LPSPI_TCR_CONT_MASK (0x200000U) +#define LPSPI_TCR_CONT_SHIFT (21U) +/*! CONT - Continuous Transfer + * 0b0..Continuous transfer is disabled + * 0b1..Continuous transfer is enabled + */ +#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) +#define LPSPI_TCR_BYSW_MASK (0x400000U) +#define LPSPI_TCR_BYSW_SHIFT (22U) +/*! BYSW - Byte Swap + * 0b0..Byte swap is disabled + * 0b1..Byte swap is enabled + */ +#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) +#define LPSPI_TCR_LSBF_MASK (0x800000U) +#define LPSPI_TCR_LSBF_SHIFT (23U) +/*! LSBF - LSB First + * 0b0..Data is transferred MSB first + * 0b1..Data is transferred LSB first + */ +#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) +#define LPSPI_TCR_PCS_MASK (0x3000000U) +#define LPSPI_TCR_PCS_SHIFT (24U) +/*! PCS - Peripheral Chip Select + * 0b00..Transfer using LPSPI_PCS[0] + * 0b01..Transfer using LPSPI_PCS[1] + * 0b10..Transfer using LPSPI_PCS[2] + * 0b11..Transfer using LPSPI_PCS[3] + */ +#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) +#define LPSPI_TCR_PRESCALE_MASK (0x38000000U) +#define LPSPI_TCR_PRESCALE_SHIFT (27U) +/*! PRESCALE - Prescaler Value + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) +#define LPSPI_TCR_CPHA_MASK (0x40000000U) +#define LPSPI_TCR_CPHA_SHIFT (30U) +/*! CPHA - Clock Phase + * 0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK + * 0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK + */ +#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) +#define LPSPI_TCR_CPOL_MASK (0x80000000U) +#define LPSPI_TCR_CPOL_SHIFT (31U) +/*! CPOL - Clock Polarity + * 0b0..The inactive state value of SCK is low + * 0b1..The inactive state value of SCK is high + */ +#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) +/*! @} */ + +/*! @name TDR - Transmit Data Register */ +/*! @{ */ +#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDR_DATA_SHIFT (0U) +#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) +/*! @} */ + +/*! @name RSR - Receive Status Register */ +/*! @{ */ +#define LPSPI_RSR_SOF_MASK (0x1U) +#define LPSPI_RSR_SOF_SHIFT (0U) +/*! SOF - Start Of Frame + * 0b0..Subsequent data word received after LPSPI_PCS assertion + * 0b1..First data word received after LPSPI_PCS assertion + */ +#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) +#define LPSPI_RSR_RXEMPTY_MASK (0x2U) +#define LPSPI_RSR_RXEMPTY_SHIFT (1U) +/*! RXEMPTY - RX FIFO Empty + * 0b0..RX FIFO is not empty + * 0b1..RX FIFO is empty + */ +#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) +/*! @} */ + +/*! @name RDR - Receive Data Register */ +/*! @{ */ +#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDR_DATA_SHIFT (0U) +#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPSPI_Register_Masks */ + + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE (0x40394000u) +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) +/** Peripheral LPSPI2 base address */ +#define LPSPI2_BASE (0x40398000u) +/** Peripheral LPSPI2 base pointer */ +#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE) +/** Peripheral LPSPI3 base address */ +#define LPSPI3_BASE (0x4039C000u) +/** Peripheral LPSPI3 base pointer */ +#define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE) +/** Peripheral LPSPI4 base address */ +#define LPSPI4_BASE (0x403A0000u) +/** Peripheral LPSPI4 base pointer */ +#define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE) +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE } +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4 } +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn } + +/*! + * @} + */ /* end of group LPSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPUART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer + * @{ + */ + +/** LPUART - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */ + __IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */ + __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */ + __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */ + __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */ + __IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */ + __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */ + __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */ + __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */ + __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */ +} LPUART_Type; + +/* ---------------------------------------------------------------------------- + -- LPUART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Register_Masks LPUART Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ +#define LPUART_VERID_FEATURE_MASK (0xFFFFU) +#define LPUART_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number + * 0b0000000000000001..Standard feature set. + * 0b0000000000000011..Standard feature set with MODEM/IrDA support. + */ +#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) +#define LPUART_VERID_MINOR_MASK (0xFF0000U) +#define LPUART_VERID_MINOR_SHIFT (16U) +#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) +#define LPUART_VERID_MAJOR_MASK (0xFF000000U) +#define LPUART_VERID_MAJOR_SHIFT (24U) +#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ +#define LPUART_PARAM_TXFIFO_MASK (0xFFU) +#define LPUART_PARAM_TXFIFO_SHIFT (0U) +#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) +#define LPUART_PARAM_RXFIFO_MASK (0xFF00U) +#define LPUART_PARAM_RXFIFO_SHIFT (8U) +#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) +/*! @} */ + +/*! @name GLOBAL - LPUART Global Register */ +/*! @{ */ +#define LPUART_GLOBAL_RST_MASK (0x2U) +#define LPUART_GLOBAL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Module is not reset. + * 0b1..Module is reset. + */ +#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) +/*! @} */ + +/*! @name PINCFG - LPUART Pin Configuration Register */ +/*! @{ */ +#define LPUART_PINCFG_TRGSEL_MASK (0x3U) +#define LPUART_PINCFG_TRGSEL_SHIFT (0U) +/*! TRGSEL - Trigger Select + * 0b00..Input trigger is disabled. + * 0b01..Input trigger is used instead of RXD pin input. + * 0b10..Input trigger is used instead of CTS_B pin input. + * 0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. + */ +#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) +/*! @} */ + +/*! @name BAUD - LPUART Baud Rate Register */ +/*! @{ */ +#define LPUART_BAUD_SBR_MASK (0x1FFFU) +#define LPUART_BAUD_SBR_SHIFT (0U) +#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) +#define LPUART_BAUD_SBNS_MASK (0x2000U) +#define LPUART_BAUD_SBNS_SHIFT (13U) +/*! SBNS - Stop Bit Number Select + * 0b0..One stop bit. + * 0b1..Two stop bits. + */ +#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) +#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) +#define LPUART_BAUD_RXEDGIE_SHIFT (14U) +/*! RXEDGIE - RX Input Active Edge Interrupt Enable + * 0b0..Hardware interrupts from STAT[RXEDGIF] are disabled. + * 0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1. + */ +#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) +#define LPUART_BAUD_LBKDIE_MASK (0x8000U) +#define LPUART_BAUD_LBKDIE_SHIFT (15U) +/*! LBKDIE - LIN Break Detect Interrupt Enable + * 0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). + * 0b1..Hardware interrupt requested when STAT[LBKDIF] flag is 1. + */ +#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) +#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) +#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) +/*! RESYNCDIS - Resynchronization Disable + * 0b0..Resynchronization during received data word is supported + * 0b1..Resynchronization during received data word is disabled + */ +#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) +#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) +#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) +/*! BOTHEDGE - Both Edge Sampling + * 0b0..Receiver samples input data using the rising edge of the baud rate clock. + * 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock. + */ +#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) +#define LPUART_BAUD_MATCFG_MASK (0xC0000U) +#define LPUART_BAUD_MATCFG_SHIFT (18U) +/*! MATCFG - Match Configuration + * 0b00..Address Match Wakeup + * 0b01..Idle Match Wakeup + * 0b10..Match On and Match Off + * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input + */ +#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) +#define LPUART_BAUD_RIDMAE_MASK (0x100000U) +#define LPUART_BAUD_RIDMAE_SHIFT (20U) +/*! RIDMAE - Receiver Idle DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) +#define LPUART_BAUD_RDMAE_MASK (0x200000U) +#define LPUART_BAUD_RDMAE_SHIFT (21U) +/*! RDMAE - Receiver Full DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) +#define LPUART_BAUD_TDMAE_MASK (0x800000U) +#define LPUART_BAUD_TDMAE_SHIFT (23U) +/*! TDMAE - Transmitter DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) +#define LPUART_BAUD_OSR_MASK (0x1F000000U) +#define LPUART_BAUD_OSR_SHIFT (24U) +/*! OSR - Oversampling Ratio + * 0b00000..Writing 0 to this field will result in an oversampling ratio of 16 + * 0b00001..Reserved + * 0b00010..Reserved + * 0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set. + * 0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set. + * 0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set. + * 0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set. + * 0b00111..Oversampling ratio of 8. + * 0b01000..Oversampling ratio of 9. + * 0b01001..Oversampling ratio of 10. + * 0b01010..Oversampling ratio of 11. + * 0b01011..Oversampling ratio of 12. + * 0b01100..Oversampling ratio of 13. + * 0b01101..Oversampling ratio of 14. + * 0b01110..Oversampling ratio of 15. + * 0b01111..Oversampling ratio of 16. + * 0b10000..Oversampling ratio of 17. + * 0b10001..Oversampling ratio of 18. + * 0b10010..Oversampling ratio of 19. + * 0b10011..Oversampling ratio of 20. + * 0b10100..Oversampling ratio of 21. + * 0b10101..Oversampling ratio of 22. + * 0b10110..Oversampling ratio of 23. + * 0b10111..Oversampling ratio of 24. + * 0b11000..Oversampling ratio of 25. + * 0b11001..Oversampling ratio of 26. + * 0b11010..Oversampling ratio of 27. + * 0b11011..Oversampling ratio of 28. + * 0b11100..Oversampling ratio of 29. + * 0b11101..Oversampling ratio of 30. + * 0b11110..Oversampling ratio of 31. + * 0b11111..Oversampling ratio of 32. + */ +#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) +#define LPUART_BAUD_M10_MASK (0x20000000U) +#define LPUART_BAUD_M10_SHIFT (29U) +/*! M10 - 10-bit Mode select + * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters. + * 0b1..Receiver and transmitter use 10-bit data characters. + */ +#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) +#define LPUART_BAUD_MAEN2_MASK (0x40000000U) +#define LPUART_BAUD_MAEN2_SHIFT (30U) +/*! MAEN2 - Match Address Mode Enable 2 + * 0b0..Normal operation. + * 0b1..Enables automatic address matching or data matching mode for MATCH[MA2]. + */ +#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) +#define LPUART_BAUD_MAEN1_MASK (0x80000000U) +#define LPUART_BAUD_MAEN1_SHIFT (31U) +/*! MAEN1 - Match Address Mode Enable 1 + * 0b0..Normal operation. + * 0b1..Enables automatic address matching or data matching mode for MATCH[MA1]. + */ +#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) +/*! @} */ + +/*! @name STAT - LPUART Status Register */ +/*! @{ */ +#define LPUART_STAT_MA2F_MASK (0x4000U) +#define LPUART_STAT_MA2F_SHIFT (14U) +/*! MA2F - Match 2 Flag + * 0b0..Received data is not equal to MA2 + * 0b1..Received data is equal to MA2 + */ +#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) +#define LPUART_STAT_MA1F_MASK (0x8000U) +#define LPUART_STAT_MA1F_SHIFT (15U) +/*! MA1F - Match 1 Flag + * 0b0..Received data is not equal to MA1 + * 0b1..Received data is equal to MA1 + */ +#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) +#define LPUART_STAT_PF_MASK (0x10000U) +#define LPUART_STAT_PF_SHIFT (16U) +/*! PF - Parity Error Flag + * 0b0..No parity error. + * 0b1..Parity error. + */ +#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) +#define LPUART_STAT_FE_MASK (0x20000U) +#define LPUART_STAT_FE_SHIFT (17U) +/*! FE - Framing Error Flag + * 0b0..No framing error detected. This does not guarantee the framing is correct. + * 0b1..Framing error. + */ +#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) +#define LPUART_STAT_NF_MASK (0x40000U) +#define LPUART_STAT_NF_SHIFT (18U) +/*! NF - Noise Flag + * 0b0..No noise detected. + * 0b1..Noise detected in the received character in the DATA register. + */ +#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) +#define LPUART_STAT_OR_MASK (0x80000U) +#define LPUART_STAT_OR_SHIFT (19U) +/*! OR - Receiver Overrun Flag + * 0b0..No overrun. + * 0b1..Receive overrun (new LPUART data lost). + */ +#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) +#define LPUART_STAT_IDLE_MASK (0x100000U) +#define LPUART_STAT_IDLE_SHIFT (20U) +/*! IDLE - Idle Line Flag + * 0b0..No idle line detected. + * 0b1..Idle line was detected. + */ +#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) +#define LPUART_STAT_RDRF_MASK (0x200000U) +#define LPUART_STAT_RDRF_SHIFT (21U) +/*! RDRF - Receive Data Register Full Flag + * 0b0..Receive data buffer empty. + * 0b1..Receive data buffer full. + */ +#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) +#define LPUART_STAT_TC_MASK (0x400000U) +#define LPUART_STAT_TC_SHIFT (22U) +/*! TC - Transmission Complete Flag + * 0b0..Transmitter active (sending data, a preamble, or a break). + * 0b1..Transmitter idle (transmission activity complete). + */ +#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) +#define LPUART_STAT_TDRE_MASK (0x800000U) +#define LPUART_STAT_TDRE_SHIFT (23U) +/*! TDRE - Transmit Data Register Empty Flag + * 0b0..Transmit data buffer full. + * 0b1..Transmit data buffer empty. + */ +#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) +#define LPUART_STAT_RAF_MASK (0x1000000U) +#define LPUART_STAT_RAF_SHIFT (24U) +/*! RAF - Receiver Active Flag + * 0b0..LPUART receiver idle waiting for a start bit. + * 0b1..LPUART receiver active (RXD input not idle). + */ +#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) +#define LPUART_STAT_LBKDE_MASK (0x2000000U) +#define LPUART_STAT_LBKDE_SHIFT (25U) +/*! LBKDE - LIN Break Detection Enable + * 0b0..LIN break detect is disabled, normal break character can be detected. + * 0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). + */ +#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) +#define LPUART_STAT_BRK13_MASK (0x4000000U) +#define LPUART_STAT_BRK13_SHIFT (26U) +/*! BRK13 - Break Character Generation Length + * 0b0..Break character is transmitted with length of 9 to 13 bit times. + * 0b1..Break character is transmitted with length of 12 to 15 bit times. + */ +#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) +#define LPUART_STAT_RWUID_MASK (0x8000000U) +#define LPUART_STAT_RWUID_SHIFT (27U) +/*! RWUID - Receive Wake Up Idle Detect + * 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle + * character. During address match wakeup, the IDLE bit does not set when an address does not match. + * 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During + * address match wakeup, the IDLE bit does set when an address does not match. + */ +#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) +#define LPUART_STAT_RXINV_MASK (0x10000000U) +#define LPUART_STAT_RXINV_SHIFT (28U) +/*! RXINV - Receive Data Inversion + * 0b0..Receive data not inverted. + * 0b1..Receive data inverted. + */ +#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) +#define LPUART_STAT_MSBF_MASK (0x20000000U) +#define LPUART_STAT_MSBF_SHIFT (29U) +/*! MSBF - MSB First + * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received + * after the start bit is identified as bit0. + * 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on + * the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is + * identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. + */ +#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) +#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) +#define LPUART_STAT_RXEDGIF_SHIFT (30U) +/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag + * 0b0..No active edge on the receive pin has occurred. + * 0b1..An active edge on the receive pin has occurred. + */ +#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) +#define LPUART_STAT_LBKDIF_MASK (0x80000000U) +#define LPUART_STAT_LBKDIF_SHIFT (31U) +/*! LBKDIF - LIN Break Detect Interrupt Flag + * 0b0..No LIN break character has been detected. + * 0b1..LIN break character has been detected. + */ +#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) +/*! @} */ + +/*! @name CTRL - LPUART Control Register */ +/*! @{ */ +#define LPUART_CTRL_PT_MASK (0x1U) +#define LPUART_CTRL_PT_SHIFT (0U) +/*! PT - Parity Type + * 0b0..Even parity. + * 0b1..Odd parity. + */ +#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) +#define LPUART_CTRL_PE_MASK (0x2U) +#define LPUART_CTRL_PE_SHIFT (1U) +/*! PE - Parity Enable + * 0b0..No hardware parity generation or checking. + * 0b1..Parity enabled. + */ +#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) +#define LPUART_CTRL_ILT_MASK (0x4U) +#define LPUART_CTRL_ILT_SHIFT (2U) +/*! ILT - Idle Line Type Select + * 0b0..Idle character bit count starts after start bit. + * 0b1..Idle character bit count starts after stop bit. + */ +#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) +#define LPUART_CTRL_WAKE_MASK (0x8U) +#define LPUART_CTRL_WAKE_SHIFT (3U) +/*! WAKE - Receiver Wakeup Method Select + * 0b0..Configures RWU for idle-line wakeup. + * 0b1..Configures RWU with address-mark wakeup. + */ +#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) +#define LPUART_CTRL_M_MASK (0x10U) +#define LPUART_CTRL_M_SHIFT (4U) +/*! M - 9-Bit or 8-Bit Mode Select + * 0b0..Receiver and transmitter use 8-bit data characters. + * 0b1..Receiver and transmitter use 9-bit data characters. + */ +#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) +#define LPUART_CTRL_RSRC_MASK (0x20U) +#define LPUART_CTRL_RSRC_SHIFT (5U) +/*! RSRC - Receiver Source Select + * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. + * 0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. + */ +#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) +#define LPUART_CTRL_DOZEEN_MASK (0x40U) +#define LPUART_CTRL_DOZEEN_SHIFT (6U) +/*! DOZEEN - Doze Enable + * 0b0..LPUART is enabled in Doze mode. + * 0b1..LPUART is disabled in Doze mode. + */ +#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) +#define LPUART_CTRL_LOOPS_MASK (0x80U) +#define LPUART_CTRL_LOOPS_SHIFT (7U) +/*! LOOPS - Loop Mode Select + * 0b0..Normal operation - RXD and TXD use separate pins. + * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). + */ +#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) +#define LPUART_CTRL_IDLECFG_MASK (0x700U) +#define LPUART_CTRL_IDLECFG_SHIFT (8U) +/*! IDLECFG - Idle Configuration + * 0b000..1 idle character + * 0b001..2 idle characters + * 0b010..4 idle characters + * 0b011..8 idle characters + * 0b100..16 idle characters + * 0b101..32 idle characters + * 0b110..64 idle characters + * 0b111..128 idle characters + */ +#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) +#define LPUART_CTRL_M7_MASK (0x800U) +#define LPUART_CTRL_M7_SHIFT (11U) +/*! M7 - 7-Bit Mode Select + * 0b0..Receiver and transmitter use 8-bit to 10-bit data characters. + * 0b1..Receiver and transmitter use 7-bit data characters. + */ +#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) +#define LPUART_CTRL_MA2IE_MASK (0x4000U) +#define LPUART_CTRL_MA2IE_SHIFT (14U) +/*! MA2IE - Match 2 Interrupt Enable + * 0b0..MA2F interrupt disabled + * 0b1..MA2F interrupt enabled + */ +#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) +#define LPUART_CTRL_MA1IE_MASK (0x8000U) +#define LPUART_CTRL_MA1IE_SHIFT (15U) +/*! MA1IE - Match 1 Interrupt Enable + * 0b0..MA1F interrupt disabled + * 0b1..MA1F interrupt enabled + */ +#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) +#define LPUART_CTRL_SBK_MASK (0x10000U) +#define LPUART_CTRL_SBK_SHIFT (16U) +/*! SBK - Send Break + * 0b0..Normal transmitter operation. + * 0b1..Queue break character(s) to be sent. + */ +#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) +#define LPUART_CTRL_RWU_MASK (0x20000U) +#define LPUART_CTRL_RWU_SHIFT (17U) +/*! RWU - Receiver Wakeup Control + * 0b0..Normal receiver operation. + * 0b1..LPUART receiver in standby waiting for wakeup condition. + */ +#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) +#define LPUART_CTRL_RE_MASK (0x40000U) +#define LPUART_CTRL_RE_SHIFT (18U) +/*! RE - Receiver Enable + * 0b0..Receiver disabled. + * 0b1..Receiver enabled. + */ +#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) +#define LPUART_CTRL_TE_MASK (0x80000U) +#define LPUART_CTRL_TE_SHIFT (19U) +/*! TE - Transmitter Enable + * 0b0..Transmitter disabled. + * 0b1..Transmitter enabled. + */ +#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) +#define LPUART_CTRL_ILIE_MASK (0x100000U) +#define LPUART_CTRL_ILIE_SHIFT (20U) +/*! ILIE - Idle Line Interrupt Enable + * 0b0..Hardware interrupts from IDLE disabled; use polling. + * 0b1..Hardware interrupt requested when IDLE flag is 1. + */ +#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) +#define LPUART_CTRL_RIE_MASK (0x200000U) +#define LPUART_CTRL_RIE_SHIFT (21U) +/*! RIE - Receiver Interrupt Enable + * 0b0..Hardware interrupts from RDRF disabled; use polling. + * 0b1..Hardware interrupt requested when RDRF flag is 1. + */ +#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) +#define LPUART_CTRL_TCIE_MASK (0x400000U) +#define LPUART_CTRL_TCIE_SHIFT (22U) +/*! TCIE - Transmission Complete Interrupt Enable for + * 0b0..Hardware interrupts from TC disabled; use polling. + * 0b1..Hardware interrupt requested when TC flag is 1. + */ +#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) +#define LPUART_CTRL_TIE_MASK (0x800000U) +#define LPUART_CTRL_TIE_SHIFT (23U) +/*! TIE - Transmit Interrupt Enable + * 0b0..Hardware interrupts from TDRE disabled; use polling. + * 0b1..Hardware interrupt requested when TDRE flag is 1. + */ +#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) +#define LPUART_CTRL_PEIE_MASK (0x1000000U) +#define LPUART_CTRL_PEIE_SHIFT (24U) +/*! PEIE - Parity Error Interrupt Enable + * 0b0..PF interrupts disabled; use polling). + * 0b1..Hardware interrupt requested when PF is set. + */ +#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) +#define LPUART_CTRL_FEIE_MASK (0x2000000U) +#define LPUART_CTRL_FEIE_SHIFT (25U) +/*! FEIE - Framing Error Interrupt Enable + * 0b0..FE interrupts disabled; use polling. + * 0b1..Hardware interrupt requested when FE is set. + */ +#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) +#define LPUART_CTRL_NEIE_MASK (0x4000000U) +#define LPUART_CTRL_NEIE_SHIFT (26U) +/*! NEIE - Noise Error Interrupt Enable + * 0b0..NF interrupts disabled; use polling. + * 0b1..Hardware interrupt requested when NF is set. + */ +#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) +#define LPUART_CTRL_ORIE_MASK (0x8000000U) +#define LPUART_CTRL_ORIE_SHIFT (27U) +/*! ORIE - Overrun Interrupt Enable + * 0b0..OR interrupts disabled; use polling. + * 0b1..Hardware interrupt requested when OR is set. + */ +#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) +#define LPUART_CTRL_TXINV_MASK (0x10000000U) +#define LPUART_CTRL_TXINV_SHIFT (28U) +/*! TXINV - Transmit Data Inversion + * 0b0..Transmit data not inverted. + * 0b1..Transmit data inverted. + */ +#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) +#define LPUART_CTRL_TXDIR_MASK (0x20000000U) +#define LPUART_CTRL_TXDIR_SHIFT (29U) +/*! TXDIR - TXD Pin Direction in Single-Wire Mode + * 0b0..TXD pin is an input in single-wire mode. + * 0b1..TXD pin is an output in single-wire mode. + */ +#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) +#define LPUART_CTRL_R9T8_MASK (0x40000000U) +#define LPUART_CTRL_R9T8_SHIFT (30U) +#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) +#define LPUART_CTRL_R8T9_MASK (0x80000000U) +#define LPUART_CTRL_R8T9_SHIFT (31U) +#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) +/*! @} */ + +/*! @name DATA - LPUART Data Register */ +/*! @{ */ +#define LPUART_DATA_R0T0_MASK (0x1U) +#define LPUART_DATA_R0T0_SHIFT (0U) +#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) +#define LPUART_DATA_R1T1_MASK (0x2U) +#define LPUART_DATA_R1T1_SHIFT (1U) +#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) +#define LPUART_DATA_R2T2_MASK (0x4U) +#define LPUART_DATA_R2T2_SHIFT (2U) +#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) +#define LPUART_DATA_R3T3_MASK (0x8U) +#define LPUART_DATA_R3T3_SHIFT (3U) +#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) +#define LPUART_DATA_R4T4_MASK (0x10U) +#define LPUART_DATA_R4T4_SHIFT (4U) +#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) +#define LPUART_DATA_R5T5_MASK (0x20U) +#define LPUART_DATA_R5T5_SHIFT (5U) +#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) +#define LPUART_DATA_R6T6_MASK (0x40U) +#define LPUART_DATA_R6T6_SHIFT (6U) +#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) +#define LPUART_DATA_R7T7_MASK (0x80U) +#define LPUART_DATA_R7T7_SHIFT (7U) +#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) +#define LPUART_DATA_R8T8_MASK (0x100U) +#define LPUART_DATA_R8T8_SHIFT (8U) +#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) +#define LPUART_DATA_R9T9_MASK (0x200U) +#define LPUART_DATA_R9T9_SHIFT (9U) +#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) +#define LPUART_DATA_IDLINE_MASK (0x800U) +#define LPUART_DATA_IDLINE_SHIFT (11U) +/*! IDLINE - Idle Line + * 0b0..Receiver was not idle before receiving this character. + * 0b1..Receiver was idle before receiving this character. + */ +#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) +#define LPUART_DATA_RXEMPT_MASK (0x1000U) +#define LPUART_DATA_RXEMPT_SHIFT (12U) +/*! RXEMPT - Receive Buffer Empty + * 0b0..Receive buffer contains valid data. + * 0b1..Receive buffer is empty, data returned on read is not valid. + */ +#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) +#define LPUART_DATA_FRETSC_MASK (0x2000U) +#define LPUART_DATA_FRETSC_SHIFT (13U) +/*! FRETSC - Frame Error / Transmit Special Character + * 0b0..The dataword was received without a frame error on read, or transmit a normal character on write. + * 0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit. + */ +#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) +#define LPUART_DATA_PARITYE_MASK (0x4000U) +#define LPUART_DATA_PARITYE_SHIFT (14U) +/*! PARITYE - PARITYE + * 0b0..The dataword was received without a parity error. + * 0b1..The dataword was received with a parity error. + */ +#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) +#define LPUART_DATA_NOISY_MASK (0x8000U) +#define LPUART_DATA_NOISY_SHIFT (15U) +/*! NOISY - NOISY + * 0b0..The dataword was received without noise. + * 0b1..The data was received with noise. + */ +#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) +/*! @} */ + +/*! @name MATCH - LPUART Match Address Register */ +/*! @{ */ +#define LPUART_MATCH_MA1_MASK (0x3FFU) +#define LPUART_MATCH_MA1_SHIFT (0U) +#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) +#define LPUART_MATCH_MA2_MASK (0x3FF0000U) +#define LPUART_MATCH_MA2_SHIFT (16U) +#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) +/*! @} */ + +/*! @name MODIR - LPUART Modem IrDA Register */ +/*! @{ */ +#define LPUART_MODIR_TXCTSE_MASK (0x1U) +#define LPUART_MODIR_TXCTSE_SHIFT (0U) +/*! TXCTSE - Transmitter clear-to-send enable + * 0b0..CTS has no effect on the transmitter. + * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a + * character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the + * mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent + * do not affect its transmission. + */ +#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) +#define LPUART_MODIR_TXRTSE_MASK (0x2U) +#define LPUART_MODIR_TXRTSE_SHIFT (1U) +/*! TXRTSE - Transmitter request-to-send enable + * 0b0..The transmitter has no effect on RTS. + * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the + * start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and + * shift register are completely sent, including the last stop bit. + */ +#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) +#define LPUART_MODIR_TXRTSPOL_MASK (0x4U) +#define LPUART_MODIR_TXRTSPOL_SHIFT (2U) +/*! TXRTSPOL - Transmitter request-to-send polarity + * 0b0..Transmitter RTS is active low. + * 0b1..Transmitter RTS is active high. + */ +#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) +#define LPUART_MODIR_RXRTSE_MASK (0x8U) +#define LPUART_MODIR_RXRTSE_SHIFT (3U) +/*! RXRTSE - Receiver request-to-send enable + * 0b0..The receiver has no effect on RTS. + * 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause + * the receiver data register to become full. RTS is asserted if the receiver data register is not full and + * has not detected a start bit that would cause the receiver data register to become full. + */ +#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) +#define LPUART_MODIR_TXCTSC_MASK (0x10U) +#define LPUART_MODIR_TXCTSC_SHIFT (4U) +/*! TXCTSC - Transmit CTS Configuration + * 0b0..CTS input is sampled at the start of each character. + * 0b1..CTS input is sampled when the transmitter is idle. + */ +#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) +#define LPUART_MODIR_TXCTSSRC_MASK (0x20U) +#define LPUART_MODIR_TXCTSSRC_SHIFT (5U) +/*! TXCTSSRC - Transmit CTS Source + * 0b0..CTS input is the CTS_B pin. + * 0b1..CTS input is the inverted Receiver Match result. + */ +#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) +#define LPUART_MODIR_RTSWATER_MASK (0x300U) +#define LPUART_MODIR_RTSWATER_SHIFT (8U) +#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) +#define LPUART_MODIR_TNP_MASK (0x30000U) +#define LPUART_MODIR_TNP_SHIFT (16U) +/*! TNP - Transmitter narrow pulse + * 0b00..1/OSR. + * 0b01..2/OSR. + * 0b10..3/OSR. + * 0b11..4/OSR. + */ +#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) +#define LPUART_MODIR_IREN_MASK (0x40000U) +#define LPUART_MODIR_IREN_SHIFT (18U) +/*! IREN - Infrared enable + * 0b0..IR disabled. + * 0b1..IR enabled. + */ +#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) +/*! @} */ + +/*! @name FIFO - LPUART FIFO Register */ +/*! @{ */ +#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) +#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) +/*! RXFIFOSIZE - Receive FIFO Buffer Depth + * 0b000..Receive FIFO/Buffer depth = 1 dataword. + * 0b001..Receive FIFO/Buffer depth = 4 datawords. + * 0b010..Receive FIFO/Buffer depth = 8 datawords. + * 0b011..Receive FIFO/Buffer depth = 16 datawords. + * 0b100..Receive FIFO/Buffer depth = 32 datawords. + * 0b101..Receive FIFO/Buffer depth = 64 datawords. + * 0b110..Receive FIFO/Buffer depth = 128 datawords. + * 0b111..Receive FIFO/Buffer depth = 256 datawords. + */ +#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) +#define LPUART_FIFO_RXFE_MASK (0x8U) +#define LPUART_FIFO_RXFE_SHIFT (3U) +/*! RXFE - Receive FIFO Enable + * 0b0..Receive FIFO is not enabled. Buffer is depth 1. + * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. + */ +#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) +#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) +#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) +/*! TXFIFOSIZE - Transmit FIFO Buffer Depth + * 0b000..Transmit FIFO/Buffer depth = 1 dataword. + * 0b001..Transmit FIFO/Buffer depth = 4 datawords. + * 0b010..Transmit FIFO/Buffer depth = 8 datawords. + * 0b011..Transmit FIFO/Buffer depth = 16 datawords. + * 0b100..Transmit FIFO/Buffer depth = 32 datawords. + * 0b101..Transmit FIFO/Buffer depth = 64 datawords. + * 0b110..Transmit FIFO/Buffer depth = 128 datawords. + * 0b111..Transmit FIFO/Buffer depth = 256 datawords + */ +#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) +#define LPUART_FIFO_TXFE_MASK (0x80U) +#define LPUART_FIFO_TXFE_SHIFT (7U) +/*! TXFE - Transmit FIFO Enable + * 0b0..Transmit FIFO is not enabled. Buffer is depth 1. + * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. + */ +#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) +#define LPUART_FIFO_RXUFE_MASK (0x100U) +#define LPUART_FIFO_RXUFE_SHIFT (8U) +/*! RXUFE - Receive FIFO Underflow Interrupt Enable + * 0b0..RXUF flag does not generate an interrupt to the host. + * 0b1..RXUF flag generates an interrupt to the host. + */ +#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) +#define LPUART_FIFO_TXOFE_MASK (0x200U) +#define LPUART_FIFO_TXOFE_SHIFT (9U) +/*! TXOFE - Transmit FIFO Overflow Interrupt Enable + * 0b0..TXOF flag does not generate an interrupt to the host. + * 0b1..TXOF flag generates an interrupt to the host. + */ +#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) +#define LPUART_FIFO_RXIDEN_MASK (0x1C00U) +#define LPUART_FIFO_RXIDEN_SHIFT (10U) +/*! RXIDEN - Receiver Idle Empty Enable + * 0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle. + * 0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. + * 0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. + * 0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. + * 0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. + * 0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. + * 0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. + * 0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. + */ +#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) +#define LPUART_FIFO_RXFLUSH_MASK (0x4000U) +#define LPUART_FIFO_RXFLUSH_SHIFT (14U) +/*! RXFLUSH - Receive FIFO/Buffer Flush + * 0b0..No flush operation occurs. + * 0b1..All data in the receive FIFO/buffer is cleared out. + */ +#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) +#define LPUART_FIFO_TXFLUSH_MASK (0x8000U) +#define LPUART_FIFO_TXFLUSH_SHIFT (15U) +/*! TXFLUSH - Transmit FIFO/Buffer Flush + * 0b0..No flush operation occurs. + * 0b1..All data in the transmit FIFO/Buffer is cleared out. + */ +#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) +#define LPUART_FIFO_RXUF_MASK (0x10000U) +#define LPUART_FIFO_RXUF_SHIFT (16U) +/*! RXUF - Receiver Buffer Underflow Flag + * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared. + * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared. + */ +#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) +#define LPUART_FIFO_TXOF_MASK (0x20000U) +#define LPUART_FIFO_TXOF_SHIFT (17U) +/*! TXOF - Transmitter Buffer Overflow Flag + * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared. + * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared. + */ +#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) +#define LPUART_FIFO_RXEMPT_MASK (0x400000U) +#define LPUART_FIFO_RXEMPT_SHIFT (22U) +/*! RXEMPT - Receive Buffer/FIFO Empty + * 0b0..Receive buffer is not empty. + * 0b1..Receive buffer is empty. + */ +#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) +#define LPUART_FIFO_TXEMPT_MASK (0x800000U) +#define LPUART_FIFO_TXEMPT_SHIFT (23U) +/*! TXEMPT - Transmit Buffer/FIFO Empty + * 0b0..Transmit buffer is not empty. + * 0b1..Transmit buffer is empty. + */ +#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) +/*! @} */ + +/*! @name WATER - LPUART Watermark Register */ +/*! @{ */ +#define LPUART_WATER_TXWATER_MASK (0x3U) +#define LPUART_WATER_TXWATER_SHIFT (0U) +#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) +#define LPUART_WATER_TXCOUNT_MASK (0x700U) +#define LPUART_WATER_TXCOUNT_SHIFT (8U) +#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) +#define LPUART_WATER_RXWATER_MASK (0x30000U) +#define LPUART_WATER_RXWATER_SHIFT (16U) +#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) +#define LPUART_WATER_RXCOUNT_MASK (0x7000000U) +#define LPUART_WATER_RXCOUNT_SHIFT (24U) +#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPUART_Register_Masks */ + + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x40184000u) +/** Peripheral LPUART1 base pointer */ +#define LPUART1 ((LPUART_Type *)LPUART1_BASE) +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE (0x40188000u) +/** Peripheral LPUART2 base pointer */ +#define LPUART2 ((LPUART_Type *)LPUART2_BASE) +/** Peripheral LPUART3 base address */ +#define LPUART3_BASE (0x4018C000u) +/** Peripheral LPUART3 base pointer */ +#define LPUART3 ((LPUART_Type *)LPUART3_BASE) +/** Peripheral LPUART4 base address */ +#define LPUART4_BASE (0x40190000u) +/** Peripheral LPUART4 base pointer */ +#define LPUART4 ((LPUART_Type *)LPUART4_BASE) +/** Peripheral LPUART5 base address */ +#define LPUART5_BASE (0x40194000u) +/** Peripheral LPUART5 base pointer */ +#define LPUART5 ((LPUART_Type *)LPUART5_BASE) +/** Peripheral LPUART6 base address */ +#define LPUART6_BASE (0x40198000u) +/** Peripheral LPUART6 base pointer */ +#define LPUART6 ((LPUART_Type *)LPUART6_BASE) +/** Peripheral LPUART7 base address */ +#define LPUART7_BASE (0x4019C000u) +/** Peripheral LPUART7 base pointer */ +#define LPUART7 ((LPUART_Type *)LPUART7_BASE) +/** Peripheral LPUART8 base address */ +#define LPUART8_BASE (0x401A0000u) +/** Peripheral LPUART8 base pointer */ +#define LPUART8 ((LPUART_Type *)LPUART8_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn } + +/*! + * @} + */ /* end of group LPUART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OCOTP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer + * @{ + */ + +/** OCOTP - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< OTP Controller Control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */ + __IO uint32_t TIMING; /**< OTP Controller Timing Register, offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DATA; /**< OTP Controller Write Data Register, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t READ_CTRL; /**< OTP Controller Write Data Register, offset: 0x30 */ + uint8_t RESERVED_2[12]; + __IO uint32_t READ_FUSE_DATA; /**< OTP Controller Read Data Register, offset: 0x40 */ + uint8_t RESERVED_3[12]; + __IO uint32_t SW_STICKY; /**< Sticky bit Register, offset: 0x50 */ + uint8_t RESERVED_4[12]; + __IO uint32_t SCS; /**< Software Controllable Signals Register, offset: 0x60 */ + __IO uint32_t SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */ + __IO uint32_t SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */ + __IO uint32_t SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */ + __IO uint32_t CRC_ADDR; /**< OTP Controller CRC test address, offset: 0x70 */ + uint8_t RESERVED_5[12]; + __IO uint32_t CRC_VALUE; /**< OTP Controller CRC Value Register, offset: 0x80 */ + uint8_t RESERVED_6[12]; + __I uint32_t VERSION; /**< OTP Controller Version Register, offset: 0x90 */ + uint8_t RESERVED_7[108]; + __IO uint32_t TIMING2; /**< OTP Controller Timing Register, offset: 0x100 */ + uint8_t RESERVED_8[764]; + __IO uint32_t LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */ + uint8_t RESERVED_9[12]; + __IO uint32_t CFG0; /**< Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.), offset: 0x410 */ + uint8_t RESERVED_10[12]; + __IO uint32_t CFG1; /**< Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.), offset: 0x420 */ + uint8_t RESERVED_11[12]; + __IO uint32_t CFG2; /**< Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.), offset: 0x430 */ + uint8_t RESERVED_12[12]; + __IO uint32_t CFG3; /**< Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.), offset: 0x440 */ + uint8_t RESERVED_13[12]; + __IO uint32_t CFG4; /**< Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.), offset: 0x450 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CFG5; /**< Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.), offset: 0x460 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CFG6; /**< Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.), offset: 0x470 */ + uint8_t RESERVED_16[12]; + __IO uint32_t MEM0; /**< Value of OTP Bank1 Word0 (Memory Related Info.), offset: 0x480 */ + uint8_t RESERVED_17[12]; + __IO uint32_t MEM1; /**< Value of OTP Bank1 Word1 (Memory Related Info.), offset: 0x490 */ + uint8_t RESERVED_18[12]; + __IO uint32_t MEM2; /**< Value of OTP Bank1 Word2 (Memory Related Info.), offset: 0x4A0 */ + uint8_t RESERVED_19[12]; + __IO uint32_t MEM3; /**< Value of OTP Bank1 Word3 (Memory Related Info.), offset: 0x4B0 */ + uint8_t RESERVED_20[12]; + __IO uint32_t MEM4; /**< Value of OTP Bank1 Word4 (Memory Related Info.), offset: 0x4C0 */ + uint8_t RESERVED_21[12]; + __IO uint32_t ANA0; /**< Value of OTP Bank1 Word5 (Memory Related Info.), offset: 0x4D0 */ + uint8_t RESERVED_22[12]; + __IO uint32_t ANA1; /**< Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.), offset: 0x4E0 */ + uint8_t RESERVED_23[12]; + __IO uint32_t ANA2; /**< Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.), offset: 0x4F0 */ + uint8_t RESERVED_24[12]; + __IO uint32_t OTPMK0; /**< Value of OTP Bank2 Word0 (OTPMK Key), offset: 0x500 */ + uint8_t RESERVED_25[12]; + __IO uint32_t OTPMK1; /**< Value of OTP Bank2 Word1 (OTPMK Key), offset: 0x510 */ + uint8_t RESERVED_26[12]; + __IO uint32_t OTPMK2; /**< Value of OTP Bank2 Word2 (OTPMK Key), offset: 0x520 */ + uint8_t RESERVED_27[12]; + __IO uint32_t OTPMK3; /**< Value of OTP Bank2 Word3 (OTPMK Key), offset: 0x530 */ + uint8_t RESERVED_28[12]; + __IO uint32_t OTPMK4; /**< Value of OTP Bank2 Word4 (OTPMK Key), offset: 0x540 */ + uint8_t RESERVED_29[12]; + __IO uint32_t OTPMK5; /**< Value of OTP Bank2 Word5 (OTPMK Key), offset: 0x550 */ + uint8_t RESERVED_30[12]; + __IO uint32_t OTPMK6; /**< Value of OTP Bank2 Word6 (OTPMK Key), offset: 0x560 */ + uint8_t RESERVED_31[12]; + __IO uint32_t OTPMK7; /**< Value of OTP Bank2 Word7 (OTPMK Key), offset: 0x570 */ + uint8_t RESERVED_32[12]; + __IO uint32_t SRK0; /**< Shadow Register for OTP Bank3 Word0 (SRK Hash), offset: 0x580 */ + uint8_t RESERVED_33[12]; + __IO uint32_t SRK1; /**< Shadow Register for OTP Bank3 Word1 (SRK Hash), offset: 0x590 */ + uint8_t RESERVED_34[12]; + __IO uint32_t SRK2; /**< Shadow Register for OTP Bank3 Word2 (SRK Hash), offset: 0x5A0 */ + uint8_t RESERVED_35[12]; + __IO uint32_t SRK3; /**< Shadow Register for OTP Bank3 Word3 (SRK Hash), offset: 0x5B0 */ + uint8_t RESERVED_36[12]; + __IO uint32_t SRK4; /**< Shadow Register for OTP Bank3 Word4 (SRK Hash), offset: 0x5C0 */ + uint8_t RESERVED_37[12]; + __IO uint32_t SRK5; /**< Shadow Register for OTP Bank3 Word5 (SRK Hash), offset: 0x5D0 */ + uint8_t RESERVED_38[12]; + __IO uint32_t SRK6; /**< Shadow Register for OTP Bank3 Word6 (SRK Hash), offset: 0x5E0 */ + uint8_t RESERVED_39[12]; + __IO uint32_t SRK7; /**< Shadow Register for OTP Bank3 Word7 (SRK Hash), offset: 0x5F0 */ + uint8_t RESERVED_40[12]; + __IO uint32_t SJC_RESP0; /**< Value of OTP Bank4 Word0 (Secure JTAG Response Field), offset: 0x600 */ + uint8_t RESERVED_41[12]; + __IO uint32_t SJC_RESP1; /**< Value of OTP Bank4 Word1 (Secure JTAG Response Field), offset: 0x610 */ + uint8_t RESERVED_42[12]; + __IO uint32_t MAC0; /**< Value of OTP Bank4 Word2 (MAC Address), offset: 0x620 */ + uint8_t RESERVED_43[12]; + __IO uint32_t MAC1; /**< Value of OTP Bank4 Word3 (MAC Address), offset: 0x630 */ + uint8_t RESERVED_44[12]; + __IO uint32_t MAC2; /**< Value of OTP Bank4 Word4 (MAC2 Address), offset: 0x640 */ + uint8_t RESERVED_45[12]; + __IO uint32_t OTPMK_CRC32; /**< Value of OTP Bank4 Word5 (CRC Key), offset: 0x650 */ + uint8_t RESERVED_46[12]; + __IO uint32_t GP1; /**< Value of OTP Bank4 Word6 (General Purpose Customer Defined Info), offset: 0x660 */ + uint8_t RESERVED_47[12]; + __IO uint32_t GP2; /**< Value of OTP Bank4 Word7 (General Purpose Customer Defined Info), offset: 0x670 */ + uint8_t RESERVED_48[12]; + __IO uint32_t SW_GP1; /**< Value of OTP Bank5 Word0 (SW GP1), offset: 0x680 */ + uint8_t RESERVED_49[12]; + __IO uint32_t SW_GP20; /**< Value of OTP Bank5 Word1 (SW GP2), offset: 0x690 */ + uint8_t RESERVED_50[12]; + __IO uint32_t SW_GP21; /**< Value of OTP Bank5 Word2 (SW GP2), offset: 0x6A0 */ + uint8_t RESERVED_51[12]; + __IO uint32_t SW_GP22; /**< Value of OTP Bank5 Word3 (SW GP2), offset: 0x6B0 */ + uint8_t RESERVED_52[12]; + __IO uint32_t SW_GP23; /**< Value of OTP Bank5 Word4 (SW GP2), offset: 0x6C0 */ + uint8_t RESERVED_53[12]; + __IO uint32_t MISC_CONF0; /**< Value of OTP Bank5 Word5 (Misc Conf), offset: 0x6D0 */ + uint8_t RESERVED_54[12]; + __IO uint32_t MISC_CONF1; /**< Value of OTP Bank5 Word6 (Misc Conf), offset: 0x6E0 */ + uint8_t RESERVED_55[12]; + __IO uint32_t SRK_REVOKE; /**< Value of OTP Bank5 Word7 (SRK Revoke), offset: 0x6F0 */ + uint8_t RESERVED_56[268]; + __IO uint32_t ROM_PATCH0; /**< Value of OTP Bank6 Word0 (ROM Patch), offset: 0x800 */ + uint8_t RESERVED_57[12]; + __IO uint32_t ROM_PATCH1; /**< Value of OTP Bank6 Word1 (ROM Patch), offset: 0x810 */ + uint8_t RESERVED_58[12]; + __IO uint32_t ROM_PATCH2; /**< Value of OTP Bank6 Word2 (ROM Patch), offset: 0x820 */ + uint8_t RESERVED_59[12]; + __IO uint32_t ROM_PATCH3; /**< Value of OTP Bank6 Word3 (ROM Patch), offset: 0x830 */ + uint8_t RESERVED_60[12]; + __IO uint32_t ROM_PATCH4; /**< Value of OTP Bank6 Word4 (ROM Patch), offset: 0x840 */ + uint8_t RESERVED_61[12]; + __IO uint32_t ROM_PATCH5; /**< Value of OTP Bank6 Word5 (ROM Patch), offset: 0x850 */ + uint8_t RESERVED_62[12]; + __IO uint32_t ROM_PATCH6; /**< Value of OTP Bank6 Word6 (ROM Patch), offset: 0x860 */ + uint8_t RESERVED_63[12]; + __IO uint32_t ROM_PATCH7; /**< Value of OTP Bank6 Word7 (ROM Patch), offset: 0x870 */ + uint8_t RESERVED_64[12]; + __IO uint32_t GP30; /**< Value of OTP Bank7 Word0 (GP3), offset: 0x880 */ + uint8_t RESERVED_65[12]; + __IO uint32_t GP31; /**< Value of OTP Bank7 Word1 (GP3), offset: 0x890 */ + uint8_t RESERVED_66[12]; + __IO uint32_t GP32; /**< Value of OTP Bank7 Word2 (GP3), offset: 0x8A0 */ + uint8_t RESERVED_67[12]; + __IO uint32_t GP33; /**< Value of OTP Bank7 Word3 (GP3), offset: 0x8B0 */ + uint8_t RESERVED_68[12]; + __IO uint32_t GP40; /**< Value of OTP Bank7 Word4 (GP4), offset: 0x8C0 */ + uint8_t RESERVED_69[12]; + __IO uint32_t GP41; /**< Value of OTP Bank7 Word5 (GP4), offset: 0x8D0 */ + uint8_t RESERVED_70[12]; + __IO uint32_t GP42; /**< Value of OTP Bank7 Word6 (GP4), offset: 0x8E0 */ + uint8_t RESERVED_71[12]; + __IO uint32_t GP43; /**< Value of OTP Bank7 Word7 (GP4), offset: 0x8F0 */ +} OCOTP_Type; + +/* ---------------------------------------------------------------------------- + -- OCOTP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Register_Masks OCOTP Register Masks + * @{ + */ + +/*! @name CTRL - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_ADDR_SHIFT (0U) +#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK) +#define OCOTP_CTRL_RSVD0_MASK (0xC0U) +#define OCOTP_CTRL_RSVD0_SHIFT (6U) +#define OCOTP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RSVD0_SHIFT)) & OCOTP_CTRL_RSVD0_MASK) +#define OCOTP_CTRL_BUSY_MASK (0x100U) +#define OCOTP_CTRL_BUSY_SHIFT (8U) +#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK) +#define OCOTP_CTRL_ERROR_MASK (0x200U) +#define OCOTP_CTRL_ERROR_SHIFT (9U) +#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK) +#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CRC_TEST_SHIFT)) & OCOTP_CTRL_CRC_TEST_MASK) +#define OCOTP_CTRL_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CRC_FAIL_SHIFT)) & OCOTP_CTRL_CRC_FAIL_MASK) +#define OCOTP_CTRL_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RSVD1_SHIFT)) & OCOTP_CTRL_RSVD1_MASK) +#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) +/*! WR_UNLOCK - WR_UNLOCK + * 0b0011111001110111..Key needed to unlock HW_OCOTP_DATA register. + */ +#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name CTRL_SET - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_SET_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_SET_ADDR_SHIFT (0U) +#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK) +#define OCOTP_CTRL_SET_RSVD0_MASK (0xC0U) +#define OCOTP_CTRL_SET_RSVD0_SHIFT (6U) +#define OCOTP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RSVD0_SHIFT)) & OCOTP_CTRL_SET_RSVD0_MASK) +#define OCOTP_CTRL_SET_BUSY_MASK (0x100U) +#define OCOTP_CTRL_SET_BUSY_SHIFT (8U) +#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK) +#define OCOTP_CTRL_SET_ERROR_MASK (0x200U) +#define OCOTP_CTRL_SET_ERROR_SHIFT (9U) +#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_SET_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_SET_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_SET_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_CRC_TEST_SHIFT)) & OCOTP_CTRL_SET_CRC_TEST_MASK) +#define OCOTP_CTRL_SET_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_SET_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_SET_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_CRC_FAIL_SHIFT)) & OCOTP_CTRL_SET_CRC_FAIL_MASK) +#define OCOTP_CTRL_SET_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_SET_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RSVD1_SHIFT)) & OCOTP_CTRL_SET_RSVD1_MASK) +#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name CTRL_CLR - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_CLR_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U) +#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK) +#define OCOTP_CTRL_CLR_RSVD0_MASK (0xC0U) +#define OCOTP_CTRL_CLR_RSVD0_SHIFT (6U) +#define OCOTP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RSVD0_SHIFT)) & OCOTP_CTRL_CLR_RSVD0_MASK) +#define OCOTP_CTRL_CLR_BUSY_MASK (0x100U) +#define OCOTP_CTRL_CLR_BUSY_SHIFT (8U) +#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK) +#define OCOTP_CTRL_CLR_ERROR_MASK (0x200U) +#define OCOTP_CTRL_CLR_ERROR_SHIFT (9U) +#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_CLR_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_CLR_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_CLR_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_CRC_TEST_SHIFT)) & OCOTP_CTRL_CLR_CRC_TEST_MASK) +#define OCOTP_CTRL_CLR_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_CLR_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_CLR_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_CRC_FAIL_SHIFT)) & OCOTP_CTRL_CLR_CRC_FAIL_MASK) +#define OCOTP_CTRL_CLR_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_CLR_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RSVD1_SHIFT)) & OCOTP_CTRL_CLR_RSVD1_MASK) +#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name CTRL_TOG - OTP Controller Control Register */ +/*! @{ */ +#define OCOTP_CTRL_TOG_ADDR_MASK (0x3FU) +#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U) +#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK) +#define OCOTP_CTRL_TOG_RSVD0_MASK (0xC0U) +#define OCOTP_CTRL_TOG_RSVD0_SHIFT (6U) +#define OCOTP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RSVD0_SHIFT)) & OCOTP_CTRL_TOG_RSVD0_MASK) +#define OCOTP_CTRL_TOG_BUSY_MASK (0x100U) +#define OCOTP_CTRL_TOG_BUSY_SHIFT (8U) +#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK) +#define OCOTP_CTRL_TOG_ERROR_MASK (0x200U) +#define OCOTP_CTRL_TOG_ERROR_SHIFT (9U) +#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK) +#define OCOTP_CTRL_TOG_CRC_TEST_MASK (0x800U) +#define OCOTP_CTRL_TOG_CRC_TEST_SHIFT (11U) +#define OCOTP_CTRL_TOG_CRC_TEST(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_CRC_TEST_SHIFT)) & OCOTP_CTRL_TOG_CRC_TEST_MASK) +#define OCOTP_CTRL_TOG_CRC_FAIL_MASK (0x1000U) +#define OCOTP_CTRL_TOG_CRC_FAIL_SHIFT (12U) +#define OCOTP_CTRL_TOG_CRC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_CRC_FAIL_SHIFT)) & OCOTP_CTRL_TOG_CRC_FAIL_MASK) +#define OCOTP_CTRL_TOG_RSVD1_MASK (0xE000U) +#define OCOTP_CTRL_TOG_RSVD1_SHIFT (13U) +#define OCOTP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RSVD1_SHIFT)) & OCOTP_CTRL_TOG_RSVD1_MASK) +#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U) +#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK) +/*! @} */ + +/*! @name TIMING - OTP Controller Timing Register */ +/*! @{ */ +#define OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU) +#define OCOTP_TIMING_STROBE_PROG_SHIFT (0U) +#define OCOTP_TIMING_STROBE_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_TIMING_STROBE_PROG_MASK) +#define OCOTP_TIMING_RELAX_MASK (0xF000U) +#define OCOTP_TIMING_RELAX_SHIFT (12U) +#define OCOTP_TIMING_RELAX(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_TIMING_RELAX_MASK) +#define OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U) +#define OCOTP_TIMING_STROBE_READ_SHIFT (16U) +#define OCOTP_TIMING_STROBE_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_TIMING_STROBE_READ_MASK) +#define OCOTP_TIMING_WAIT_MASK (0xFC00000U) +#define OCOTP_TIMING_WAIT_SHIFT (22U) +#define OCOTP_TIMING_WAIT(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_TIMING_WAIT_MASK) +#define OCOTP_TIMING_RSRVD0_MASK (0xF0000000U) +#define OCOTP_TIMING_RSRVD0_SHIFT (28U) +#define OCOTP_TIMING_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING_RSRVD0_SHIFT)) & OCOTP_TIMING_RSRVD0_MASK) +/*! @} */ + +/*! @name DATA - OTP Controller Write Data Register */ +/*! @{ */ +#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_DATA_DATA_SHIFT (0U) +#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK) +/*! @} */ + +/*! @name READ_CTRL - OTP Controller Write Data Register */ +/*! @{ */ +#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) +#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) +#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK) +#define OCOTP_READ_CTRL_RSVD0_MASK (0xFFFFFFFEU) +#define OCOTP_READ_CTRL_RSVD0_SHIFT (1U) +#define OCOTP_READ_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_RSVD0_SHIFT)) & OCOTP_READ_CTRL_RSVD0_MASK) +/*! @} */ + +/*! @name READ_FUSE_DATA - OTP Controller Read Data Register */ +/*! @{ */ +#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) +#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK) +/*! @} */ + +/*! @name SW_STICKY - Sticky bit Register */ +/*! @{ */ +#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK (0x1U) +#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT (0U) +#define OCOTP_SW_STICKY_BLOCK_DTCP_KEY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_DTCP_KEY_SHIFT)) & OCOTP_SW_STICKY_BLOCK_DTCP_KEY_MASK) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U) +#define OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U) +#define OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK) +#define OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U) +#define OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U) +#define OCOTP_SW_STICKY_BLOCK_ROM_PART(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK) +#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U) +#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U) +#define OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK) +#define OCOTP_SW_STICKY_RSVD0_MASK (0xFFFFFFE0U) +#define OCOTP_SW_STICKY_RSVD0_SHIFT (5U) +#define OCOTP_SW_STICKY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_STICKY_RSVD0_SHIFT)) & OCOTP_SW_STICKY_RSVD0_MASK) +/*! @} */ + +/*! @name SCS - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK) +#define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SPARE_SHIFT (1U) +#define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK) +#define OCOTP_SCS_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_LOCK_SHIFT (31U) +#define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK) +/*! @} */ + +/*! @name SCS_SET - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK) +#define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_SET_SPARE_SHIFT (1U) +#define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK) +#define OCOTP_SCS_SET_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_SET_LOCK_SHIFT (31U) +#define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK) +/*! @} */ + +/*! @name SCS_CLR - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK) +#define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_CLR_SPARE_SHIFT (1U) +#define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK) +#define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_CLR_LOCK_SHIFT (31U) +#define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK) +/*! @} */ + +/*! @name SCS_TOG - Software Controllable Signals Register */ +/*! @{ */ +#define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U) +#define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U) +#define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK) +#define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU) +#define OCOTP_SCS_TOG_SPARE_SHIFT (1U) +#define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK) +#define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U) +#define OCOTP_SCS_TOG_LOCK_SHIFT (31U) +#define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK) +/*! @} */ + +/*! @name CRC_ADDR - OTP Controller CRC test address */ +/*! @{ */ +#define OCOTP_CRC_ADDR_DATA_START_ADDR_MASK (0xFFU) +#define OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT (0U) +#define OCOTP_CRC_ADDR_DATA_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_DATA_START_ADDR_SHIFT)) & OCOTP_CRC_ADDR_DATA_START_ADDR_MASK) +#define OCOTP_CRC_ADDR_DATA_END_ADDR_MASK (0xFF00U) +#define OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT (8U) +#define OCOTP_CRC_ADDR_DATA_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_DATA_END_ADDR_SHIFT)) & OCOTP_CRC_ADDR_DATA_END_ADDR_MASK) +#define OCOTP_CRC_ADDR_CRC_ADDR_MASK (0xFF0000U) +#define OCOTP_CRC_ADDR_CRC_ADDR_SHIFT (16U) +#define OCOTP_CRC_ADDR_CRC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_CRC_ADDR_SHIFT)) & OCOTP_CRC_ADDR_CRC_ADDR_MASK) +#define OCOTP_CRC_ADDR_OTPMK_CRC_MASK (0x1000000U) +#define OCOTP_CRC_ADDR_OTPMK_CRC_SHIFT (24U) +#define OCOTP_CRC_ADDR_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_OTPMK_CRC_SHIFT)) & OCOTP_CRC_ADDR_OTPMK_CRC_MASK) +#define OCOTP_CRC_ADDR_RSVD0_MASK (0xFE000000U) +#define OCOTP_CRC_ADDR_RSVD0_SHIFT (25U) +#define OCOTP_CRC_ADDR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_ADDR_RSVD0_SHIFT)) & OCOTP_CRC_ADDR_RSVD0_MASK) +/*! @} */ + +/*! @name CRC_VALUE - OTP Controller CRC Value Register */ +/*! @{ */ +#define OCOTP_CRC_VALUE_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_CRC_VALUE_DATA_SHIFT (0U) +#define OCOTP_CRC_VALUE_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CRC_VALUE_DATA_SHIFT)) & OCOTP_CRC_VALUE_DATA_MASK) +/*! @} */ + +/*! @name VERSION - OTP Controller Version Register */ +/*! @{ */ +#define OCOTP_VERSION_STEP_MASK (0xFFFFU) +#define OCOTP_VERSION_STEP_SHIFT (0U) +#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK) +#define OCOTP_VERSION_MINOR_MASK (0xFF0000U) +#define OCOTP_VERSION_MINOR_SHIFT (16U) +#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK) +#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U) +#define OCOTP_VERSION_MAJOR_SHIFT (24U) +#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK) +/*! @} */ + +/*! @name TIMING2 - OTP Controller Timing Register */ +/*! @{ */ +#define OCOTP_TIMING2_RELAX_PROG_MASK (0xFFFU) +#define OCOTP_TIMING2_RELAX_PROG_SHIFT (0U) +#define OCOTP_TIMING2_RELAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_PROG_SHIFT)) & OCOTP_TIMING2_RELAX_PROG_MASK) +#define OCOTP_TIMING2_RSRVD0_MASK (0xF000U) +#define OCOTP_TIMING2_RSRVD0_SHIFT (12U) +#define OCOTP_TIMING2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RSRVD0_SHIFT)) & OCOTP_TIMING2_RSRVD0_MASK) +#define OCOTP_TIMING2_RELAX_READ_MASK (0x3F0000U) +#define OCOTP_TIMING2_RELAX_READ_SHIFT (16U) +#define OCOTP_TIMING2_RELAX_READ(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RELAX_READ_SHIFT)) & OCOTP_TIMING2_RELAX_READ_MASK) +#define OCOTP_TIMING2_RSRVD1_MASK (0xFFC00000U) +#define OCOTP_TIMING2_RSRVD1_SHIFT (22U) +#define OCOTP_TIMING2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_TIMING2_RSRVD1_SHIFT)) & OCOTP_TIMING2_RSRVD1_MASK) +/*! @} */ + +/*! @name LOCK - Value of OTP Bank0 Word0 (Lock controls) */ +/*! @{ */ +#define OCOTP_LOCK_TESTER_MASK (0x3U) +#define OCOTP_LOCK_TESTER_SHIFT (0U) +#define OCOTP_LOCK_TESTER(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_LOCK_TESTER_MASK) +#define OCOTP_LOCK_BOOT_CFG_MASK (0xCU) +#define OCOTP_LOCK_BOOT_CFG_SHIFT (2U) +#define OCOTP_LOCK_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_LOCK_BOOT_CFG_MASK) +#define OCOTP_LOCK_MEM_TRIM_MASK (0x30U) +#define OCOTP_LOCK_MEM_TRIM_SHIFT (4U) +#define OCOTP_LOCK_MEM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MEM_TRIM_SHIFT)) & OCOTP_LOCK_MEM_TRIM_MASK) +#define OCOTP_LOCK_SJC_RESP_MASK (0x40U) +#define OCOTP_LOCK_SJC_RESP_SHIFT (6U) +#define OCOTP_LOCK_SJC_RESP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_LOCK_SJC_RESP_MASK) +#define OCOTP_LOCK_GP4_RLOCK_MASK (0x80U) +#define OCOTP_LOCK_GP4_RLOCK_SHIFT (7U) +#define OCOTP_LOCK_GP4_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP4_RLOCK_SHIFT)) & OCOTP_LOCK_GP4_RLOCK_MASK) +#define OCOTP_LOCK_MAC_ADDR_MASK (0x300U) +#define OCOTP_LOCK_MAC_ADDR_SHIFT (8U) +#define OCOTP_LOCK_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_LOCK_MAC_ADDR_MASK) +#define OCOTP_LOCK_GP1_MASK (0xC00U) +#define OCOTP_LOCK_GP1_SHIFT (10U) +#define OCOTP_LOCK_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP1_SHIFT)) & OCOTP_LOCK_GP1_MASK) +#define OCOTP_LOCK_GP2_MASK (0x3000U) +#define OCOTP_LOCK_GP2_SHIFT (12U) +#define OCOTP_LOCK_GP2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP2_SHIFT)) & OCOTP_LOCK_GP2_MASK) +#define OCOTP_LOCK_ROM_PATCH_MASK (0x8000U) +#define OCOTP_LOCK_ROM_PATCH_SHIFT (15U) +#define OCOTP_LOCK_ROM_PATCH(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ROM_PATCH_SHIFT)) & OCOTP_LOCK_ROM_PATCH_MASK) +#define OCOTP_LOCK_SW_GP1_MASK (0x10000U) +#define OCOTP_LOCK_SW_GP1_SHIFT (16U) +#define OCOTP_LOCK_SW_GP1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP1_SHIFT)) & OCOTP_LOCK_SW_GP1_MASK) +#define OCOTP_LOCK_OTPMK_MASK (0x20000U) +#define OCOTP_LOCK_OTPMK_SHIFT (17U) +#define OCOTP_LOCK_OTPMK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_SHIFT)) & OCOTP_LOCK_OTPMK_MASK) +#define OCOTP_LOCK_ANALOG_MASK (0xC0000U) +#define OCOTP_LOCK_ANALOG_SHIFT (18U) +#define OCOTP_LOCK_ANALOG(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_ANALOG_SHIFT)) & OCOTP_LOCK_ANALOG_MASK) +#define OCOTP_LOCK_OTPMK_CRC_MASK (0x100000U) +#define OCOTP_LOCK_OTPMK_CRC_SHIFT (20U) +#define OCOTP_LOCK_OTPMK_CRC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_OTPMK_CRC_SHIFT)) & OCOTP_LOCK_OTPMK_CRC_MASK) +#define OCOTP_LOCK_SW_GP2_LOCK_MASK (0x200000U) +#define OCOTP_LOCK_SW_GP2_LOCK_SHIFT (21U) +#define OCOTP_LOCK_SW_GP2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_LOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_LOCK_MASK) +#define OCOTP_LOCK_MISC_CONF_MASK (0x400000U) +#define OCOTP_LOCK_MISC_CONF_SHIFT (22U) +#define OCOTP_LOCK_MISC_CONF(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_MISC_CONF_SHIFT)) & OCOTP_LOCK_MISC_CONF_MASK) +#define OCOTP_LOCK_SW_GP2_RLOCK_MASK (0x800000U) +#define OCOTP_LOCK_SW_GP2_RLOCK_SHIFT (23U) +#define OCOTP_LOCK_SW_GP2_RLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_SW_GP2_RLOCK_SHIFT)) & OCOTP_LOCK_SW_GP2_RLOCK_MASK) +#define OCOTP_LOCK_GP4_MASK (0x3000000U) +#define OCOTP_LOCK_GP4_SHIFT (24U) +#define OCOTP_LOCK_GP4(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP4_SHIFT)) & OCOTP_LOCK_GP4_MASK) +#define OCOTP_LOCK_GP3_MASK (0xC000000U) +#define OCOTP_LOCK_GP3_SHIFT (26U) +#define OCOTP_LOCK_GP3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_GP3_SHIFT)) & OCOTP_LOCK_GP3_MASK) +#define OCOTP_LOCK_FIELD_RETURN_MASK (0xF0000000U) +#define OCOTP_LOCK_FIELD_RETURN_SHIFT (28U) +#define OCOTP_LOCK_FIELD_RETURN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCK_FIELD_RETURN_SHIFT)) & OCOTP_LOCK_FIELD_RETURN_MASK) +/*! @} */ + +/*! @name CFG0 - Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG0_BITS_SHIFT (0U) +#define OCOTP_CFG0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG0_BITS_SHIFT)) & OCOTP_CFG0_BITS_MASK) +/*! @} */ + +/*! @name CFG1 - Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG1_BITS_SHIFT (0U) +#define OCOTP_CFG1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG1_BITS_SHIFT)) & OCOTP_CFG1_BITS_MASK) +/*! @} */ + +/*! @name CFG2 - Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG2_BITS_SHIFT (0U) +#define OCOTP_CFG2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG2_BITS_SHIFT)) & OCOTP_CFG2_BITS_MASK) +/*! @} */ + +/*! @name CFG3 - Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG3_BITS_SHIFT (0U) +#define OCOTP_CFG3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG3_BITS_SHIFT)) & OCOTP_CFG3_BITS_MASK) +/*! @} */ + +/*! @name CFG4 - Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG4_BITS_SHIFT (0U) +#define OCOTP_CFG4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG4_BITS_SHIFT)) & OCOTP_CFG4_BITS_MASK) +/*! @} */ + +/*! @name CFG5 - Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG5_BITS_SHIFT (0U) +#define OCOTP_CFG5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG5_BITS_SHIFT)) & OCOTP_CFG5_BITS_MASK) +/*! @} */ + +/*! @name CFG6 - Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) */ +/*! @{ */ +#define OCOTP_CFG6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_CFG6_BITS_SHIFT (0U) +#define OCOTP_CFG6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CFG6_BITS_SHIFT)) & OCOTP_CFG6_BITS_MASK) +/*! @} */ + +/*! @name MEM0 - Value of OTP Bank1 Word0 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM0_BITS_SHIFT (0U) +#define OCOTP_MEM0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM0_BITS_SHIFT)) & OCOTP_MEM0_BITS_MASK) +/*! @} */ + +/*! @name MEM1 - Value of OTP Bank1 Word1 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM1_BITS_SHIFT (0U) +#define OCOTP_MEM1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM1_BITS_SHIFT)) & OCOTP_MEM1_BITS_MASK) +/*! @} */ + +/*! @name MEM2 - Value of OTP Bank1 Word2 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM2_BITS_SHIFT (0U) +#define OCOTP_MEM2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM2_BITS_SHIFT)) & OCOTP_MEM2_BITS_MASK) +/*! @} */ + +/*! @name MEM3 - Value of OTP Bank1 Word3 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM3_BITS_SHIFT (0U) +#define OCOTP_MEM3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM3_BITS_SHIFT)) & OCOTP_MEM3_BITS_MASK) +/*! @} */ + +/*! @name MEM4 - Value of OTP Bank1 Word4 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_MEM4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MEM4_BITS_SHIFT (0U) +#define OCOTP_MEM4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MEM4_BITS_SHIFT)) & OCOTP_MEM4_BITS_MASK) +/*! @} */ + +/*! @name ANA0 - Value of OTP Bank1 Word5 (Memory Related Info.) */ +/*! @{ */ +#define OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA0_BITS_SHIFT (0U) +#define OCOTP_ANA0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA0_BITS_SHIFT)) & OCOTP_ANA0_BITS_MASK) +/*! @} */ + +/*! @name ANA1 - Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.) */ +/*! @{ */ +#define OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA1_BITS_SHIFT (0U) +#define OCOTP_ANA1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA1_BITS_SHIFT)) & OCOTP_ANA1_BITS_MASK) +/*! @} */ + +/*! @name ANA2 - Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.) */ +/*! @{ */ +#define OCOTP_ANA2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ANA2_BITS_SHIFT (0U) +#define OCOTP_ANA2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ANA2_BITS_SHIFT)) & OCOTP_ANA2_BITS_MASK) +/*! @} */ + +/*! @name OTPMK0 - Value of OTP Bank2 Word0 (OTPMK Key) */ +/*! @{ */ +#define OCOTP_OTPMK0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK0_BITS_SHIFT (0U) +#define OCOTP_OTPMK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK0_BITS_SHIFT)) & OCOTP_OTPMK0_BITS_MASK) +/*! @} */ + +/*! @name OTPMK1 - Value of OTP Bank2 Word1 (OTPMK Key) */ +/*! @{ */ +#define OCOTP_OTPMK1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK1_BITS_SHIFT (0U) +#define OCOTP_OTPMK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK1_BITS_SHIFT)) & OCOTP_OTPMK1_BITS_MASK) +/*! @} */ + +/*! @name OTPMK2 - Value of OTP Bank2 Word2 (OTPMK Key) */ +/*! @{ */ +#define OCOTP_OTPMK2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK2_BITS_SHIFT (0U) +#define OCOTP_OTPMK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK2_BITS_SHIFT)) & OCOTP_OTPMK2_BITS_MASK) +/*! @} */ + +/*! @name OTPMK3 - Value of OTP Bank2 Word3 (OTPMK Key) */ +/*! @{ */ +#define OCOTP_OTPMK3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK3_BITS_SHIFT (0U) +#define OCOTP_OTPMK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK3_BITS_SHIFT)) & OCOTP_OTPMK3_BITS_MASK) +/*! @} */ + +/*! @name OTPMK4 - Value of OTP Bank2 Word4 (OTPMK Key) */ +/*! @{ */ +#define OCOTP_OTPMK4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK4_BITS_SHIFT (0U) +#define OCOTP_OTPMK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK4_BITS_SHIFT)) & OCOTP_OTPMK4_BITS_MASK) +/*! @} */ + +/*! @name OTPMK5 - Value of OTP Bank2 Word5 (OTPMK Key) */ +/*! @{ */ +#define OCOTP_OTPMK5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK5_BITS_SHIFT (0U) +#define OCOTP_OTPMK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK5_BITS_SHIFT)) & OCOTP_OTPMK5_BITS_MASK) +/*! @} */ + +/*! @name OTPMK6 - Value of OTP Bank2 Word6 (OTPMK Key) */ +/*! @{ */ +#define OCOTP_OTPMK6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK6_BITS_SHIFT (0U) +#define OCOTP_OTPMK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK6_BITS_SHIFT)) & OCOTP_OTPMK6_BITS_MASK) +/*! @} */ + +/*! @name OTPMK7 - Value of OTP Bank2 Word7 (OTPMK Key) */ +/*! @{ */ +#define OCOTP_OTPMK7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK7_BITS_SHIFT (0U) +#define OCOTP_OTPMK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK7_BITS_SHIFT)) & OCOTP_OTPMK7_BITS_MASK) +/*! @} */ + +/*! @name SRK0 - Shadow Register for OTP Bank3 Word0 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK0_BITS_SHIFT (0U) +#define OCOTP_SRK0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK0_BITS_SHIFT)) & OCOTP_SRK0_BITS_MASK) +/*! @} */ + +/*! @name SRK1 - Shadow Register for OTP Bank3 Word1 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK1_BITS_SHIFT (0U) +#define OCOTP_SRK1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK1_BITS_SHIFT)) & OCOTP_SRK1_BITS_MASK) +/*! @} */ + +/*! @name SRK2 - Shadow Register for OTP Bank3 Word2 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK2_BITS_SHIFT (0U) +#define OCOTP_SRK2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK2_BITS_SHIFT)) & OCOTP_SRK2_BITS_MASK) +/*! @} */ + +/*! @name SRK3 - Shadow Register for OTP Bank3 Word3 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK3_BITS_SHIFT (0U) +#define OCOTP_SRK3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK3_BITS_SHIFT)) & OCOTP_SRK3_BITS_MASK) +/*! @} */ + +/*! @name SRK4 - Shadow Register for OTP Bank3 Word4 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK4_BITS_SHIFT (0U) +#define OCOTP_SRK4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK4_BITS_SHIFT)) & OCOTP_SRK4_BITS_MASK) +/*! @} */ + +/*! @name SRK5 - Shadow Register for OTP Bank3 Word5 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK5_BITS_SHIFT (0U) +#define OCOTP_SRK5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK5_BITS_SHIFT)) & OCOTP_SRK5_BITS_MASK) +/*! @} */ + +/*! @name SRK6 - Shadow Register for OTP Bank3 Word6 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK6_BITS_SHIFT (0U) +#define OCOTP_SRK6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK6_BITS_SHIFT)) & OCOTP_SRK6_BITS_MASK) +/*! @} */ + +/*! @name SRK7 - Shadow Register for OTP Bank3 Word7 (SRK Hash) */ +/*! @{ */ +#define OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK7_BITS_SHIFT (0U) +#define OCOTP_SRK7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK7_BITS_SHIFT)) & OCOTP_SRK7_BITS_MASK) +/*! @} */ + +/*! @name SJC_RESP0 - Value of OTP Bank4 Word0 (Secure JTAG Response Field) */ +/*! @{ */ +#define OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP0_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_SJC_RESP0_BITS_MASK) +/*! @} */ + +/*! @name SJC_RESP1 - Value of OTP Bank4 Word1 (Secure JTAG Response Field) */ +/*! @{ */ +#define OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SJC_RESP1_BITS_SHIFT (0U) +#define OCOTP_SJC_RESP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_SJC_RESP1_BITS_MASK) +/*! @} */ + +/*! @name MAC0 - Value of OTP Bank4 Word2 (MAC Address) */ +/*! @{ */ +#define OCOTP_MAC0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC0_BITS_SHIFT (0U) +#define OCOTP_MAC0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC0_BITS_SHIFT)) & OCOTP_MAC0_BITS_MASK) +/*! @} */ + +/*! @name MAC1 - Value of OTP Bank4 Word3 (MAC Address) */ +/*! @{ */ +#define OCOTP_MAC1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC1_BITS_SHIFT (0U) +#define OCOTP_MAC1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC1_BITS_SHIFT)) & OCOTP_MAC1_BITS_MASK) +/*! @} */ + +/*! @name MAC2 - Value of OTP Bank4 Word4 (MAC2 Address) */ +/*! @{ */ +#define OCOTP_MAC2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MAC2_BITS_SHIFT (0U) +#define OCOTP_MAC2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MAC2_BITS_SHIFT)) & OCOTP_MAC2_BITS_MASK) +/*! @} */ + +/*! @name OTPMK_CRC32 - Value of OTP Bank4 Word5 (CRC Key) */ +/*! @{ */ +#define OCOTP_OTPMK_CRC32_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_OTPMK_CRC32_BITS_SHIFT (0U) +#define OCOTP_OTPMK_CRC32_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OTPMK_CRC32_BITS_SHIFT)) & OCOTP_OTPMK_CRC32_BITS_MASK) +/*! @} */ + +/*! @name GP1 - Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) */ +/*! @{ */ +#define OCOTP_GP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP1_BITS_SHIFT (0U) +#define OCOTP_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP1_BITS_SHIFT)) & OCOTP_GP1_BITS_MASK) +/*! @} */ + +/*! @name GP2 - Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) */ +/*! @{ */ +#define OCOTP_GP2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP2_BITS_SHIFT (0U) +#define OCOTP_GP2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP2_BITS_SHIFT)) & OCOTP_GP2_BITS_MASK) +/*! @} */ + +/*! @name SW_GP1 - Value of OTP Bank5 Word0 (SW GP1) */ +/*! @{ */ +#define OCOTP_SW_GP1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP1_BITS_SHIFT (0U) +#define OCOTP_SW_GP1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP1_BITS_SHIFT)) & OCOTP_SW_GP1_BITS_MASK) +/*! @} */ + +/*! @name SW_GP20 - Value of OTP Bank5 Word1 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP20_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP20_BITS_SHIFT (0U) +#define OCOTP_SW_GP20_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP20_BITS_SHIFT)) & OCOTP_SW_GP20_BITS_MASK) +/*! @} */ + +/*! @name SW_GP21 - Value of OTP Bank5 Word2 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP21_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP21_BITS_SHIFT (0U) +#define OCOTP_SW_GP21_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP21_BITS_SHIFT)) & OCOTP_SW_GP21_BITS_MASK) +/*! @} */ + +/*! @name SW_GP22 - Value of OTP Bank5 Word3 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP22_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP22_BITS_SHIFT (0U) +#define OCOTP_SW_GP22_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP22_BITS_SHIFT)) & OCOTP_SW_GP22_BITS_MASK) +/*! @} */ + +/*! @name SW_GP23 - Value of OTP Bank5 Word4 (SW GP2) */ +/*! @{ */ +#define OCOTP_SW_GP23_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SW_GP23_BITS_SHIFT (0U) +#define OCOTP_SW_GP23_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_GP23_BITS_SHIFT)) & OCOTP_SW_GP23_BITS_MASK) +/*! @} */ + +/*! @name MISC_CONF0 - Value of OTP Bank5 Word5 (Misc Conf) */ +/*! @{ */ +#define OCOTP_MISC_CONF0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MISC_CONF0_BITS_SHIFT (0U) +#define OCOTP_MISC_CONF0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF0_BITS_SHIFT)) & OCOTP_MISC_CONF0_BITS_MASK) +/*! @} */ + +/*! @name MISC_CONF1 - Value of OTP Bank5 Word6 (Misc Conf) */ +/*! @{ */ +#define OCOTP_MISC_CONF1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_MISC_CONF1_BITS_SHIFT (0U) +#define OCOTP_MISC_CONF1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_MISC_CONF1_BITS_SHIFT)) & OCOTP_MISC_CONF1_BITS_MASK) +/*! @} */ + +/*! @name SRK_REVOKE - Value of OTP Bank5 Word7 (SRK Revoke) */ +/*! @{ */ +#define OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_SRK_REVOKE_BITS_SHIFT (0U) +#define OCOTP_SRK_REVOKE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_SRK_REVOKE_BITS_MASK) +/*! @} */ + +/*! @name ROM_PATCH0 - Value of OTP Bank6 Word0 (ROM Patch) */ +/*! @{ */ +#define OCOTP_ROM_PATCH0_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH0_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH0_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH0_BITS_SHIFT)) & OCOTP_ROM_PATCH0_BITS_MASK) +/*! @} */ + +/*! @name ROM_PATCH1 - Value of OTP Bank6 Word1 (ROM Patch) */ +/*! @{ */ +#define OCOTP_ROM_PATCH1_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH1_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH1_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH1_BITS_SHIFT)) & OCOTP_ROM_PATCH1_BITS_MASK) +/*! @} */ + +/*! @name ROM_PATCH2 - Value of OTP Bank6 Word2 (ROM Patch) */ +/*! @{ */ +#define OCOTP_ROM_PATCH2_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH2_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH2_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH2_BITS_SHIFT)) & OCOTP_ROM_PATCH2_BITS_MASK) +/*! @} */ + +/*! @name ROM_PATCH3 - Value of OTP Bank6 Word3 (ROM Patch) */ +/*! @{ */ +#define OCOTP_ROM_PATCH3_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH3_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH3_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH3_BITS_SHIFT)) & OCOTP_ROM_PATCH3_BITS_MASK) +/*! @} */ + +/*! @name ROM_PATCH4 - Value of OTP Bank6 Word4 (ROM Patch) */ +/*! @{ */ +#define OCOTP_ROM_PATCH4_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH4_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH4_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH4_BITS_SHIFT)) & OCOTP_ROM_PATCH4_BITS_MASK) +/*! @} */ + +/*! @name ROM_PATCH5 - Value of OTP Bank6 Word5 (ROM Patch) */ +/*! @{ */ +#define OCOTP_ROM_PATCH5_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH5_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH5_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH5_BITS_SHIFT)) & OCOTP_ROM_PATCH5_BITS_MASK) +/*! @} */ + +/*! @name ROM_PATCH6 - Value of OTP Bank6 Word6 (ROM Patch) */ +/*! @{ */ +#define OCOTP_ROM_PATCH6_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH6_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH6_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH6_BITS_SHIFT)) & OCOTP_ROM_PATCH6_BITS_MASK) +/*! @} */ + +/*! @name ROM_PATCH7 - Value of OTP Bank6 Word7 (ROM Patch) */ +/*! @{ */ +#define OCOTP_ROM_PATCH7_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_ROM_PATCH7_BITS_SHIFT (0U) +#define OCOTP_ROM_PATCH7_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_ROM_PATCH7_BITS_SHIFT)) & OCOTP_ROM_PATCH7_BITS_MASK) +/*! @} */ + +/*! @name GP30 - Value of OTP Bank7 Word0 (GP3) */ +/*! @{ */ +#define OCOTP_GP30_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP30_BITS_SHIFT (0U) +#define OCOTP_GP30_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP30_BITS_SHIFT)) & OCOTP_GP30_BITS_MASK) +/*! @} */ + +/*! @name GP31 - Value of OTP Bank7 Word1 (GP3) */ +/*! @{ */ +#define OCOTP_GP31_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP31_BITS_SHIFT (0U) +#define OCOTP_GP31_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP31_BITS_SHIFT)) & OCOTP_GP31_BITS_MASK) +/*! @} */ + +/*! @name GP32 - Value of OTP Bank7 Word2 (GP3) */ +/*! @{ */ +#define OCOTP_GP32_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP32_BITS_SHIFT (0U) +#define OCOTP_GP32_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP32_BITS_SHIFT)) & OCOTP_GP32_BITS_MASK) +/*! @} */ + +/*! @name GP33 - Value of OTP Bank7 Word3 (GP3) */ +/*! @{ */ +#define OCOTP_GP33_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP33_BITS_SHIFT (0U) +#define OCOTP_GP33_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP33_BITS_SHIFT)) & OCOTP_GP33_BITS_MASK) +/*! @} */ + +/*! @name GP40 - Value of OTP Bank7 Word4 (GP4) */ +/*! @{ */ +#define OCOTP_GP40_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP40_BITS_SHIFT (0U) +#define OCOTP_GP40_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP40_BITS_SHIFT)) & OCOTP_GP40_BITS_MASK) +/*! @} */ + +/*! @name GP41 - Value of OTP Bank7 Word5 (GP4) */ +/*! @{ */ +#define OCOTP_GP41_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP41_BITS_SHIFT (0U) +#define OCOTP_GP41_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP41_BITS_SHIFT)) & OCOTP_GP41_BITS_MASK) +/*! @} */ + +/*! @name GP42 - Value of OTP Bank7 Word6 (GP4) */ +/*! @{ */ +#define OCOTP_GP42_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP42_BITS_SHIFT (0U) +#define OCOTP_GP42_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP42_BITS_SHIFT)) & OCOTP_GP42_BITS_MASK) +/*! @} */ + +/*! @name GP43 - Value of OTP Bank7 Word7 (GP4) */ +/*! @{ */ +#define OCOTP_GP43_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_GP43_BITS_SHIFT (0U) +#define OCOTP_GP43_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_GP43_BITS_SHIFT)) & OCOTP_GP43_BITS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OCOTP_Register_Masks */ + + +/* OCOTP - Peripheral instance base addresses */ +/** Peripheral OCOTP base address */ +#define OCOTP_BASE (0x401F4000u) +/** Peripheral OCOTP base pointer */ +#define OCOTP ((OCOTP_Type *)OCOTP_BASE) +/** Array initializer of OCOTP peripheral base addresses */ +#define OCOTP_BASE_ADDRS { OCOTP_BASE } +/** Array initializer of OCOTP peripheral base pointers */ +#define OCOTP_BASE_PTRS { OCOTP } + +/*! + * @} + */ /* end of group OCOTP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PGC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Peripheral_Access_Layer PGC Peripheral Access Layer + * @{ + */ + +/** PGC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[544]; + __IO uint32_t MEGA_CTRL; /**< PGC Mega Control Register, offset: 0x220 */ + __IO uint32_t MEGA_PUPSCR; /**< PGC Mega Power Up Sequence Control Register, offset: 0x224 */ + __IO uint32_t MEGA_PDNSCR; /**< PGC Mega Pull Down Sequence Control Register, offset: 0x228 */ + __IO uint32_t MEGA_SR; /**< PGC Mega Power Gating Controller Status Register, offset: 0x22C */ + uint8_t RESERVED_1[112]; + __IO uint32_t CPU_CTRL; /**< PGC CPU Control Register, offset: 0x2A0 */ + __IO uint32_t CPU_PUPSCR; /**< PGC CPU Power Up Sequence Control Register, offset: 0x2A4 */ + __IO uint32_t CPU_PDNSCR; /**< PGC CPU Pull Down Sequence Control Register, offset: 0x2A8 */ + __IO uint32_t CPU_SR; /**< PGC CPU Power Gating Controller Status Register, offset: 0x2AC */ +} PGC_Type; + +/* ---------------------------------------------------------------------------- + -- PGC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Register_Masks PGC Register Masks + * @{ + */ + +/*! @name MEGA_CTRL - PGC Mega Control Register */ +/*! @{ */ +#define PGC_MEGA_CTRL_PCR_MASK (0x1U) +#define PGC_MEGA_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define PGC_MEGA_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_CTRL_PCR_SHIFT)) & PGC_MEGA_CTRL_PCR_MASK) +/*! @} */ + +/*! @name MEGA_PUPSCR - PGC Mega Power Up Sequence Control Register */ +/*! @{ */ +#define PGC_MEGA_PUPSCR_SW_MASK (0x3FU) +#define PGC_MEGA_PUPSCR_SW_SHIFT (0U) +#define PGC_MEGA_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW_SHIFT)) & PGC_MEGA_PUPSCR_SW_MASK) +#define PGC_MEGA_PUPSCR_SW2ISO_MASK (0x3F00U) +#define PGC_MEGA_PUPSCR_SW2ISO_SHIFT (8U) +#define PGC_MEGA_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PUPSCR_SW2ISO_SHIFT)) & PGC_MEGA_PUPSCR_SW2ISO_MASK) +/*! @} */ + +/*! @name MEGA_PDNSCR - PGC Mega Pull Down Sequence Control Register */ +/*! @{ */ +#define PGC_MEGA_PDNSCR_ISO_MASK (0x3FU) +#define PGC_MEGA_PDNSCR_ISO_SHIFT (0U) +#define PGC_MEGA_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO_SHIFT)) & PGC_MEGA_PDNSCR_ISO_MASK) +#define PGC_MEGA_PDNSCR_ISO2SW_MASK (0x3F00U) +#define PGC_MEGA_PDNSCR_ISO2SW_SHIFT (8U) +#define PGC_MEGA_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_PDNSCR_ISO2SW_SHIFT)) & PGC_MEGA_PDNSCR_ISO2SW_MASK) +/*! @} */ + +/*! @name MEGA_SR - PGC Mega Power Gating Controller Status Register */ +/*! @{ */ +#define PGC_MEGA_SR_PSR_MASK (0x1U) +#define PGC_MEGA_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define PGC_MEGA_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_MEGA_SR_PSR_SHIFT)) & PGC_MEGA_SR_PSR_MASK) +/*! @} */ + +/*! @name CPU_CTRL - PGC CPU Control Register */ +/*! @{ */ +#define PGC_CPU_CTRL_PCR_MASK (0x1U) +#define PGC_CPU_CTRL_PCR_SHIFT (0U) +/*! PCR + * 0b0..Do not switch off power even if pdn_req is asserted. + * 0b1..Switch off power when pdn_req is asserted. + */ +#define PGC_CPU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_CTRL_PCR_SHIFT)) & PGC_CPU_CTRL_PCR_MASK) +/*! @} */ + +/*! @name CPU_PUPSCR - PGC CPU Power Up Sequence Control Register */ +/*! @{ */ +#define PGC_CPU_PUPSCR_SW_MASK (0x3FU) +#define PGC_CPU_PUPSCR_SW_SHIFT (0U) +#define PGC_CPU_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW_SHIFT)) & PGC_CPU_PUPSCR_SW_MASK) +#define PGC_CPU_PUPSCR_SW2ISO_MASK (0x3F00U) +#define PGC_CPU_PUPSCR_SW2ISO_SHIFT (8U) +#define PGC_CPU_PUPSCR_SW2ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PUPSCR_SW2ISO_SHIFT)) & PGC_CPU_PUPSCR_SW2ISO_MASK) +/*! @} */ + +/*! @name CPU_PDNSCR - PGC CPU Pull Down Sequence Control Register */ +/*! @{ */ +#define PGC_CPU_PDNSCR_ISO_MASK (0x3FU) +#define PGC_CPU_PDNSCR_ISO_SHIFT (0U) +#define PGC_CPU_PDNSCR_ISO(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO_SHIFT)) & PGC_CPU_PDNSCR_ISO_MASK) +#define PGC_CPU_PDNSCR_ISO2SW_MASK (0x3F00U) +#define PGC_CPU_PDNSCR_ISO2SW_SHIFT (8U) +#define PGC_CPU_PDNSCR_ISO2SW(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_PDNSCR_ISO2SW_SHIFT)) & PGC_CPU_PDNSCR_ISO2SW_MASK) +/*! @} */ + +/*! @name CPU_SR - PGC CPU Power Gating Controller Status Register */ +/*! @{ */ +#define PGC_CPU_SR_PSR_MASK (0x1U) +#define PGC_CPU_SR_PSR_SHIFT (0U) +/*! PSR + * 0b0..The target subsystem was not powered down for the previous power-down request. + * 0b1..The target subsystem was powered down for the previous power-down request. + */ +#define PGC_CPU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << PGC_CPU_SR_PSR_SHIFT)) & PGC_CPU_SR_PSR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PGC_Register_Masks */ + + +/* PGC - Peripheral instance base addresses */ +/** Peripheral PGC base address */ +#define PGC_BASE (0x400F4000u) +/** Peripheral PGC base pointer */ +#define PGC ((PGC_Type *)PGC_BASE) +/** Array initializer of PGC peripheral base addresses */ +#define PGC_BASE_ADDRS { PGC_BASE } +/** Array initializer of PGC peripheral base pointers */ +#define PGC_BASE_PTRS { PGC } + +/*! + * @} + */ /* end of group PGC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PIT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer + * @{ + */ + +/** PIT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ + uint8_t RESERVED_0[220]; + __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ + __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ + uint8_t RESERVED_1[24]; + struct { /* offset: 0x100, array step: 0x10 */ + __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ + __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ + __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ + __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ + } CHANNEL[4]; +} PIT_Type; + +/* ---------------------------------------------------------------------------- + -- PIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PIT_Register_Masks PIT Register Masks + * @{ + */ + +/*! @name MCR - PIT Module Control Register */ +/*! @{ */ +#define PIT_MCR_FRZ_MASK (0x1U) +#define PIT_MCR_FRZ_SHIFT (0U) +/*! FRZ - Freeze + * 0b0..Timers continue to run in Debug mode. + * 0b1..Timers are stopped in Debug mode. + */ +#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) +#define PIT_MCR_MDIS_MASK (0x2U) +#define PIT_MCR_MDIS_SHIFT (1U) +/*! MDIS - Module Disable - (PIT section) + * 0b0..Clock for standard PIT timers is enabled. + * 0b1..Clock for standard PIT timers is disabled. + */ +#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) +/*! @} */ + +/*! @name LTMR64H - PIT Upper Lifetime Timer Register */ +/*! @{ */ +#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) +#define PIT_LTMR64H_LTH_SHIFT (0U) +#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK) +/*! @} */ + +/*! @name LTMR64L - PIT Lower Lifetime Timer Register */ +/*! @{ */ +#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) +#define PIT_LTMR64L_LTL_SHIFT (0U) +#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK) +/*! @} */ + +/*! @name LDVAL - Timer Load Value Register */ +/*! @{ */ +#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) +#define PIT_LDVAL_TSV_SHIFT (0U) +#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) +/*! @} */ + +/* The count of PIT_LDVAL */ +#define PIT_LDVAL_COUNT (4U) + +/*! @name CVAL - Current Timer Value Register */ +/*! @{ */ +#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) +#define PIT_CVAL_TVL_SHIFT (0U) +#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) +/*! @} */ + +/* The count of PIT_CVAL */ +#define PIT_CVAL_COUNT (4U) + +/*! @name TCTRL - Timer Control Register */ +/*! @{ */ +#define PIT_TCTRL_TEN_MASK (0x1U) +#define PIT_TCTRL_TEN_SHIFT (0U) +/*! TEN - Timer Enable + * 0b0..Timer n is disabled. + * 0b1..Timer n is enabled. + */ +#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) +#define PIT_TCTRL_TIE_MASK (0x2U) +#define PIT_TCTRL_TIE_SHIFT (1U) +/*! TIE - Timer Interrupt Enable + * 0b0..Interrupt requests from Timer n are disabled. + * 0b1..Interrupt will be requested whenever TIF is set. + */ +#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) +#define PIT_TCTRL_CHN_MASK (0x4U) +#define PIT_TCTRL_CHN_SHIFT (2U) +/*! CHN - Chain Mode + * 0b0..Timer is not chained. + * 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. + */ +#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) +/*! @} */ + +/* The count of PIT_TCTRL */ +#define PIT_TCTRL_COUNT (4U) + +/*! @name TFLG - Timer Flag Register */ +/*! @{ */ +#define PIT_TFLG_TIF_MASK (0x1U) +#define PIT_TFLG_TIF_SHIFT (0U) +/*! TIF - Timer Interrupt Flag + * 0b0..Timeout has not yet occurred. + * 0b1..Timeout has occurred. + */ +#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) +/*! @} */ + +/* The count of PIT_TFLG */ +#define PIT_TFLG_COUNT (4U) + + +/*! + * @} + */ /* end of group PIT_Register_Masks */ + + +/* PIT - Peripheral instance base addresses */ +/** Peripheral PIT base address */ +#define PIT_BASE (0x40084000u) +/** Peripheral PIT base pointer */ +#define PIT ((PIT_Type *)PIT_BASE) +/** Array initializer of PIT peripheral base addresses */ +#define PIT_BASE_ADDRS { PIT_BASE } +/** Array initializer of PIT peripheral base pointers */ +#define PIT_BASE_PTRS { PIT } +/** Interrupt vectors for the PIT peripheral type */ +#define PIT_IRQS { { PIT_IRQn, PIT_IRQn, PIT_IRQn, PIT_IRQn } } + +/*! + * @} + */ /* end of group PIT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PMU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer + * @{ + */ + +/** PMU - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[272]; + __IO uint32_t REG_1P1; /**< Regulator 1P1 Register, offset: 0x110 */ + __IO uint32_t REG_1P1_SET; /**< Regulator 1P1 Register, offset: 0x114 */ + __IO uint32_t REG_1P1_CLR; /**< Regulator 1P1 Register, offset: 0x118 */ + __IO uint32_t REG_1P1_TOG; /**< Regulator 1P1 Register, offset: 0x11C */ + __IO uint32_t REG_3P0; /**< Regulator 3P0 Register, offset: 0x120 */ + __IO uint32_t REG_3P0_SET; /**< Regulator 3P0 Register, offset: 0x124 */ + __IO uint32_t REG_3P0_CLR; /**< Regulator 3P0 Register, offset: 0x128 */ + __IO uint32_t REG_3P0_TOG; /**< Regulator 3P0 Register, offset: 0x12C */ + __IO uint32_t REG_2P5; /**< Regulator 2P5 Register, offset: 0x130 */ + __IO uint32_t REG_2P5_SET; /**< Regulator 2P5 Register, offset: 0x134 */ + __IO uint32_t REG_2P5_CLR; /**< Regulator 2P5 Register, offset: 0x138 */ + __IO uint32_t REG_2P5_TOG; /**< Regulator 2P5 Register, offset: 0x13C */ + __IO uint32_t REG_CORE; /**< Digital Regulator Core Register, offset: 0x140 */ + __IO uint32_t REG_CORE_SET; /**< Digital Regulator Core Register, offset: 0x144 */ + __IO uint32_t REG_CORE_CLR; /**< Digital Regulator Core Register, offset: 0x148 */ + __IO uint32_t REG_CORE_TOG; /**< Digital Regulator Core Register, offset: 0x14C */ + __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ + __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ + __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ + __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ + __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */ + __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */ + __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */ + __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */ + __IO uint32_t MISC2; /**< Miscellaneous Control Register, offset: 0x170 */ + __IO uint32_t MISC2_SET; /**< Miscellaneous Control Register, offset: 0x174 */ + __IO uint32_t MISC2_CLR; /**< Miscellaneous Control Register, offset: 0x178 */ + __IO uint32_t MISC2_TOG; /**< Miscellaneous Control Register, offset: 0x17C */ +} PMU_Type; + +/* ---------------------------------------------------------------------------- + -- PMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Register_Masks PMU Register Masks + * @{ + */ + +/*! @name REG_1P1 - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_BO_SHIFT)) & PMU_REG_1P1_ENABLE_BO_MASK) +#define PMU_REG_1P1_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_OFFSET_SHIFT)) & PMU_REG_1P1_BO_OFFSET_MASK) +#define PMU_REG_1P1_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ +#define PMU_REG_1P1_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_BO_VDD1P1_MASK) +#define PMU_REG_1P1_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_OK_VDD1P1_MASK) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ +#define PMU_REG_1P1_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_1P1_SET - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_SET_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_SET_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_SET_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_BO_SHIFT)) & PMU_REG_1P1_SET_ENABLE_BO_MASK) +#define PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_SET_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_SET_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_SET_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_SET_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_OFFSET_SHIFT)) & PMU_REG_1P1_SET_BO_OFFSET_MASK) +#define PMU_REG_1P1_SET_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ +#define PMU_REG_1P1_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_SET_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_SET_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_SET_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_SET_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_BO_VDD1P1_MASK) +#define PMU_REG_1P1_SET_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_SET_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_SET_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_SET_OK_VDD1P1_MASK) +#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ +#define PMU_REG_1P1_SET_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_SET_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_SET_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_1P1_CLR - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_CLR_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_CLR_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_CLR_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_BO_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_BO_MASK) +#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_CLR_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_CLR_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_OFFSET_SHIFT)) & PMU_REG_1P1_CLR_BO_OFFSET_MASK) +#define PMU_REG_1P1_CLR_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ +#define PMU_REG_1P1_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_CLR_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_CLR_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_BO_VDD1P1_MASK) +#define PMU_REG_1P1_CLR_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_CLR_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_CLR_OK_VDD1P1_MASK) +#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ +#define PMU_REG_1P1_CLR_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_CLR_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_1P1_TOG - Regulator 1P1 Register */ +/*! @{ */ +#define PMU_REG_1P1_TOG_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_1P1_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_LINREG_MASK) +#define PMU_REG_1P1_TOG_ENABLE_BO_MASK (0x2U) +#define PMU_REG_1P1_TOG_ENABLE_BO_SHIFT (1U) +#define PMU_REG_1P1_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_BO_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_BO_MASK) +#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_1P1_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_ILIMIT_MASK) +#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_1P1_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_PULLDOWN_MASK) +#define PMU_REG_1P1_TOG_BO_OFFSET_MASK (0x70U) +#define PMU_REG_1P1_TOG_BO_OFFSET_SHIFT (4U) +#define PMU_REG_1P1_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_OFFSET_SHIFT)) & PMU_REG_1P1_TOG_BO_OFFSET_MASK) +#define PMU_REG_1P1_TOG_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00100..0.8V + * 0b10000..1.1V + * 0b000x1..1.375V + */ +#define PMU_REG_1P1_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_1P1_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_1P1_TOG_BO_VDD1P1_MASK (0x10000U) +#define PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT (16U) +#define PMU_REG_1P1_TOG_BO_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_BO_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_BO_VDD1P1_MASK) +#define PMU_REG_1P1_TOG_OK_VDD1P1_MASK (0x20000U) +#define PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT (17U) +#define PMU_REG_1P1_TOG_OK_VDD1P1(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_OK_VDD1P1_SHIFT)) & PMU_REG_1P1_TOG_OK_VDD1P1_MASK) +#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_ENABLE_WEAK_LINREG_MASK) +#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK (0x80000U) +#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT (19U) +/*! SELREF_WEAK_LINREG + * 0b0..Weak-linreg output tracks low-power-bandgap voltage + * 0b1..Weak-linreg output tracks VDD_SOC_IN voltage + */ +#define PMU_REG_1P1_TOG_SELREF_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_SHIFT)) & PMU_REG_1P1_TOG_SELREF_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_3P0 - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_BO_SHIFT)) & PMU_REG_3P0_ENABLE_BO_MASK) +#define PMU_REG_3P0_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_OFFSET_SHIFT)) & PMU_REG_3P0_BO_OFFSET_MASK) +#define PMU_REG_3P0_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ +#define PMU_REG_3P0_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_VBUS_SEL_SHIFT)) & PMU_REG_3P0_VBUS_SEL_MASK) +#define PMU_REG_3P0_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ +#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_BO_VDD3P0_MASK) +#define PMU_REG_3P0_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_3P0_SET - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_SET_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_SET_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_BO_SHIFT)) & PMU_REG_3P0_SET_ENABLE_BO_MASK) +#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_SET_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_OFFSET_SHIFT)) & PMU_REG_3P0_SET_BO_OFFSET_MASK) +#define PMU_REG_3P0_SET_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ +#define PMU_REG_3P0_SET_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_VBUS_SEL_SHIFT)) & PMU_REG_3P0_SET_VBUS_SEL_MASK) +#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ +#define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_SET_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_SET_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_SET_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_BO_VDD3P0_MASK) +#define PMU_REG_3P0_SET_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_SET_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_SET_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_SET_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_3P0_CLR - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_CLR_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_BO_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_BO_MASK) +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_CLR_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_OFFSET_SHIFT)) & PMU_REG_3P0_CLR_BO_OFFSET_MASK) +#define PMU_REG_3P0_CLR_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ +#define PMU_REG_3P0_CLR_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_VBUS_SEL_SHIFT)) & PMU_REG_3P0_CLR_VBUS_SEL_MASK) +#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ +#define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_CLR_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_BO_VDD3P0_MASK) +#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_CLR_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_CLR_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_3P0_TOG - Regulator 3P0 Register */ +/*! @{ */ +#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_3P0_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_LINREG_MASK) +#define PMU_REG_3P0_TOG_ENABLE_BO_MASK (0x2U) +#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT (1U) +#define PMU_REG_3P0_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_BO_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_BO_MASK) +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_3P0_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK) +#define PMU_REG_3P0_TOG_BO_OFFSET_MASK (0x70U) +#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT (4U) +#define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_OFFSET_SHIFT)) & PMU_REG_3P0_TOG_BO_OFFSET_MASK) +#define PMU_REG_3P0_TOG_VBUS_SEL_MASK (0x80U) +#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT (7U) +/*! VBUS_SEL + * 0b1..Utilize VBUS OTG1 power + * 0b0..Utilize VBUS OTG2 power + */ +#define PMU_REG_3P0_TOG_VBUS_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_VBUS_SEL_SHIFT)) & PMU_REG_3P0_TOG_VBUS_SEL_MASK) +#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.625V + * 0b01111..3.000V + * 0b11111..3.400V + */ +#define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_3P0_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK (0x10000U) +#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT (16U) +#define PMU_REG_3P0_TOG_BO_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_BO_VDD3P0_MASK) +#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK (0x20000U) +#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT (17U) +#define PMU_REG_3P0_TOG_OK_VDD3P0(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT)) & PMU_REG_3P0_TOG_OK_VDD3P0_MASK) +/*! @} */ + +/*! @name REG_2P5 - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_BO_SHIFT)) & PMU_REG_2P5_ENABLE_BO_MASK) +#define PMU_REG_2P5_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_OFFSET_SHIFT)) & PMU_REG_2P5_BO_OFFSET_MASK) +#define PMU_REG_2P5_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ +#define PMU_REG_2P5_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_BO_VDD2P5_MASK) +#define PMU_REG_2P5_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_OK_VDD2P5_MASK) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_2P5_SET - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_SET_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_SET_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_SET_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_SET_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_SET_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_BO_SHIFT)) & PMU_REG_2P5_SET_ENABLE_BO_MASK) +#define PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_SET_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_SET_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_SET_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_SET_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_SET_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_SET_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_OFFSET_SHIFT)) & PMU_REG_2P5_SET_BO_OFFSET_MASK) +#define PMU_REG_2P5_SET_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ +#define PMU_REG_2P5_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_SET_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_SET_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_SET_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_SET_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_BO_VDD2P5_MASK) +#define PMU_REG_2P5_SET_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_SET_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_SET_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_SET_OK_VDD2P5_MASK) +#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_SET_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_SET_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_2P5_CLR - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_CLR_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_CLR_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_CLR_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_CLR_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_CLR_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_BO_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_BO_MASK) +#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_CLR_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_CLR_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_CLR_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_CLR_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_OFFSET_SHIFT)) & PMU_REG_2P5_CLR_BO_OFFSET_MASK) +#define PMU_REG_2P5_CLR_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ +#define PMU_REG_2P5_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_CLR_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_CLR_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_CLR_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_BO_VDD2P5_MASK) +#define PMU_REG_2P5_CLR_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_CLR_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_CLR_OK_VDD2P5_MASK) +#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_CLR_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_2P5_TOG - Regulator 2P5 Register */ +/*! @{ */ +#define PMU_REG_2P5_TOG_ENABLE_LINREG_MASK (0x1U) +#define PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT (0U) +#define PMU_REG_2P5_TOG_ENABLE_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_LINREG_MASK) +#define PMU_REG_2P5_TOG_ENABLE_BO_MASK (0x2U) +#define PMU_REG_2P5_TOG_ENABLE_BO_SHIFT (1U) +#define PMU_REG_2P5_TOG_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_BO_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_BO_MASK) +#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK (0x4U) +#define PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT (2U) +#define PMU_REG_2P5_TOG_ENABLE_ILIMIT(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_ILIMIT_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_ILIMIT_MASK) +#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK (0x8U) +#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT (3U) +#define PMU_REG_2P5_TOG_ENABLE_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_PULLDOWN_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_PULLDOWN_MASK) +#define PMU_REG_2P5_TOG_BO_OFFSET_MASK (0x70U) +#define PMU_REG_2P5_TOG_BO_OFFSET_SHIFT (4U) +#define PMU_REG_2P5_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_OFFSET_SHIFT)) & PMU_REG_2P5_TOG_BO_OFFSET_MASK) +#define PMU_REG_2P5_TOG_OUTPUT_TRG_MASK (0x1F00U) +#define PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT (8U) +/*! OUTPUT_TRG + * 0b00000..2.10V + * 0b10000..2.50V + * 0b11111..2.875V + */ +#define PMU_REG_2P5_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OUTPUT_TRG_SHIFT)) & PMU_REG_2P5_TOG_OUTPUT_TRG_MASK) +#define PMU_REG_2P5_TOG_BO_VDD2P5_MASK (0x10000U) +#define PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT (16U) +#define PMU_REG_2P5_TOG_BO_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_BO_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_BO_VDD2P5_MASK) +#define PMU_REG_2P5_TOG_OK_VDD2P5_MASK (0x20000U) +#define PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT (17U) +#define PMU_REG_2P5_TOG_OK_VDD2P5(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_OK_VDD2P5_SHIFT)) & PMU_REG_2P5_TOG_OK_VDD2P5_MASK) +#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK (0x40000U) +#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT (18U) +#define PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_SHIFT)) & PMU_REG_2P5_TOG_ENABLE_WEAK_LINREG_MASK) +/*! @} */ + +/*! @name REG_CORE - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_TARG_SHIFT)) & PMU_REG_CORE_REG0_TARG_MASK) +#define PMU_REG_CORE_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG0_ADJ_SHIFT)) & PMU_REG_CORE_REG0_ADJ_MASK) +#define PMU_REG_CORE_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit + * increments reflect 25mV core voltage steps. Not all steps will make sense to use either because + * of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_TARG_SHIFT)) & PMU_REG_CORE_REG1_TARG_MASK) +#define PMU_REG_CORE_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG1_ADJ_SHIFT)) & PMU_REG_CORE_REG1_ADJ_MASK) +#define PMU_REG_CORE_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_TARG_SHIFT)) & PMU_REG_CORE_REG2_TARG_MASK) +#define PMU_REG_CORE_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_REG2_ADJ_SHIFT)) & PMU_REG_CORE_REG2_ADJ_MASK) +#define PMU_REG_CORE_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ +#define PMU_REG_CORE_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_RAMP_RATE_SHIFT)) & PMU_REG_CORE_RAMP_RATE_MASK) +#define PMU_REG_CORE_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name REG_CORE_SET - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_SET_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_SET_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_SET_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_TARG_SHIFT)) & PMU_REG_CORE_SET_REG0_TARG_MASK) +#define PMU_REG_CORE_SET_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_SET_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_SET_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG0_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG0_ADJ_MASK) +#define PMU_REG_CORE_SET_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_SET_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit + * increments reflect 25mV core voltage steps. Not all steps will make sense to use either because + * of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_SET_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_TARG_SHIFT)) & PMU_REG_CORE_SET_REG1_TARG_MASK) +#define PMU_REG_CORE_SET_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_SET_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_SET_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG1_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG1_ADJ_MASK) +#define PMU_REG_CORE_SET_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_SET_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_SET_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_TARG_SHIFT)) & PMU_REG_CORE_SET_REG2_TARG_MASK) +#define PMU_REG_CORE_SET_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_SET_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_SET_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_REG2_ADJ_SHIFT)) & PMU_REG_CORE_SET_REG2_ADJ_MASK) +#define PMU_REG_CORE_SET_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_SET_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ +#define PMU_REG_CORE_SET_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_RAMP_RATE_SHIFT)) & PMU_REG_CORE_SET_RAMP_RATE_MASK) +#define PMU_REG_CORE_SET_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_SET_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_SET_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_SET_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_SET_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name REG_CORE_CLR - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_CLR_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_CLR_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_CLR_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG0_TARG_MASK) +#define PMU_REG_CORE_CLR_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_CLR_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_CLR_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG0_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG0_ADJ_MASK) +#define PMU_REG_CORE_CLR_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_CLR_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit + * increments reflect 25mV core voltage steps. Not all steps will make sense to use either because + * of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_CLR_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG1_TARG_MASK) +#define PMU_REG_CORE_CLR_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_CLR_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_CLR_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG1_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG1_ADJ_MASK) +#define PMU_REG_CORE_CLR_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_CLR_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_CLR_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_TARG_SHIFT)) & PMU_REG_CORE_CLR_REG2_TARG_MASK) +#define PMU_REG_CORE_CLR_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_CLR_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_CLR_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_REG2_ADJ_SHIFT)) & PMU_REG_CORE_CLR_REG2_ADJ_MASK) +#define PMU_REG_CORE_CLR_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_CLR_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ +#define PMU_REG_CORE_CLR_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_RAMP_RATE_SHIFT)) & PMU_REG_CORE_CLR_RAMP_RATE_MASK) +#define PMU_REG_CORE_CLR_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_CLR_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_CLR_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_CLR_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name REG_CORE_TOG - Digital Regulator Core Register */ +/*! @{ */ +#define PMU_REG_CORE_TOG_REG0_TARG_MASK (0x1FU) +#define PMU_REG_CORE_TOG_REG0_TARG_SHIFT (0U) +/*! REG0_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_TOG_REG0_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG0_TARG_MASK) +#define PMU_REG_CORE_TOG_REG0_ADJ_MASK (0x1E0U) +#define PMU_REG_CORE_TOG_REG0_ADJ_SHIFT (5U) +/*! REG0_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg0. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_TOG_REG0_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG0_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG0_ADJ_MASK) +#define PMU_REG_CORE_TOG_REG1_TARG_MASK (0x3E00U) +#define PMU_REG_CORE_TOG_REG1_TARG_SHIFT (9U) +/*! REG1_TARG - This bit field defines the target voltage for the vpu/gpu power domain. Single bit + * increments reflect 25mV core voltage steps. Not all steps will make sense to use either because + * of input supply limitations or load operation. + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_TOG_REG1_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG1_TARG_MASK) +#define PMU_REG_CORE_TOG_REG1_ADJ_MASK (0x3C000U) +#define PMU_REG_CORE_TOG_REG1_ADJ_SHIFT (14U) +/*! REG1_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg1. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_TOG_REG1_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG1_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG1_ADJ_MASK) +#define PMU_REG_CORE_TOG_REG2_TARG_MASK (0x7C0000U) +#define PMU_REG_CORE_TOG_REG2_TARG_SHIFT (18U) +/*! REG2_TARG + * 0b00000..Power gated off + * 0b00001..Target core voltage = 0.725V + * 0b00010..Target core voltage = 0.750V + * 0b00011..Target core voltage = 0.775V + * 0b10000..Target core voltage = 1.100V + * 0b11110..Target core voltage = 1.450V + * 0b11111..Power FET switched full on. No regulation. + */ +#define PMU_REG_CORE_TOG_REG2_TARG(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_TARG_SHIFT)) & PMU_REG_CORE_TOG_REG2_TARG_MASK) +#define PMU_REG_CORE_TOG_REG2_ADJ_MASK (0x7800000U) +#define PMU_REG_CORE_TOG_REG2_ADJ_SHIFT (23U) +/*! REG2_ADJ - This bit field defines the adjustment bits to calibrate the target value of Reg2. The + * adjustment is applied on top on any adjustment applied to the global reference in the misc0 + * register. + * 0b0000..No adjustment + * 0b0001..+ 0.25% + * 0b0010..+ 0.50% + * 0b0011..+ 0.75% + * 0b0100..+ 1.00% + * 0b0101..+ 1.25% + * 0b0110..+ 1.50% + * 0b0111..+ 1.75% + * 0b1000..- 0.25% + * 0b1001..- 0.50% + * 0b1010..- 0.75% + * 0b1011..- 1.00% + * 0b1100..- 1.25% + * 0b1101..- 1.50% + * 0b1110..- 1.75% + * 0b1111..- 2.00% + */ +#define PMU_REG_CORE_TOG_REG2_ADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_REG2_ADJ_SHIFT)) & PMU_REG_CORE_TOG_REG2_ADJ_MASK) +#define PMU_REG_CORE_TOG_RAMP_RATE_MASK (0x18000000U) +#define PMU_REG_CORE_TOG_RAMP_RATE_SHIFT (27U) +/*! RAMP_RATE + * 0b00..Fast + * 0b01..Medium Fast + * 0b10..Medium Slow + * 0b11..Slow + */ +#define PMU_REG_CORE_TOG_RAMP_RATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_RAMP_RATE_SHIFT)) & PMU_REG_CORE_TOG_RAMP_RATE_MASK) +#define PMU_REG_CORE_TOG_FET_ODRIVE_MASK (0x20000000U) +#define PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT (29U) +#define PMU_REG_CORE_TOG_FET_ODRIVE(x) (((uint32_t)(((uint32_t)(x)) << PMU_REG_CORE_TOG_FET_ODRIVE_SHIFT)) & PMU_REG_CORE_TOG_FET_ODRIVE_MASK) +/*! @} */ + +/*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_PWD_SHIFT)) & PMU_MISC0_REFTOP_PWD_MASK) +#define PMU_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define PMU_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define PMU_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_REFTOP_VBGUP_MASK) +#define PMU_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ +#define PMU_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define PMU_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_OSC_I_MASK (0x6000U) +#define PMU_MISC0_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define PMU_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_I_SHIFT)) & PMU_MISC0_OSC_I_MASK) +#define PMU_MISC0_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_SHIFT)) & PMU_MISC0_OSC_XTALOK_MASK) +#define PMU_MISC0_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define PMU_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLKGATE_CTRL_MASK) +#define PMU_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define PMU_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLKGATE_DELAY_MASK) +#define PMU_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define PMU_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_XTAL_24M_PWD_MASK) +#define PMU_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) +#define PMU_MISC0_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define PMU_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_SET_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_SET_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_PWD_SHIFT)) & PMU_MISC0_SET_REFTOP_PWD_MASK) +#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define PMU_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_SET_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define PMU_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_SET_REFTOP_VBGUP_MASK) +#define PMU_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ +#define PMU_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_SET_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define PMU_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_SET_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_SET_OSC_I_MASK (0x6000U) +#define PMU_MISC0_SET_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define PMU_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_I_SHIFT)) & PMU_MISC0_SET_OSC_I_MASK) +#define PMU_MISC0_SET_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_SET_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_MASK) +#define PMU_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_SET_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define PMU_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_SET_CLKGATE_CTRL_MASK) +#define PMU_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define PMU_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_SET_CLKGATE_DELAY_MASK) +#define PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define PMU_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_SET_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_SET_XTAL_24M_PWD_MASK) +#define PMU_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) +#define PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define PMU_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_SET_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_CLR_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_CLR_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_PWD_SHIFT)) & PMU_MISC0_CLR_REFTOP_PWD_MASK) +#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define PMU_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define PMU_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_CLR_REFTOP_VBGUP_MASK) +#define PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ +#define PMU_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_CLR_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define PMU_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_CLR_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_CLR_OSC_I_MASK (0x6000U) +#define PMU_MISC0_CLR_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define PMU_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_I_SHIFT)) & PMU_MISC0_CLR_OSC_I_MASK) +#define PMU_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_CLR_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_MASK) +#define PMU_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_CLR_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define PMU_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_CLR_CLKGATE_CTRL_MASK) +#define PMU_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define PMU_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_CLR_CLKGATE_DELAY_MASK) +#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define PMU_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_CLR_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_CLR_XTAL_24M_PWD_MASK) +#define PMU_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) +#define PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define PMU_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_CLR_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ +#define PMU_MISC0_TOG_REFTOP_PWD_MASK (0x1U) +#define PMU_MISC0_TOG_REFTOP_PWD_SHIFT (0U) +#define PMU_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_PWD_SHIFT)) & PMU_MISC0_TOG_REFTOP_PWD_MASK) +#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) +#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define PMU_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & PMU_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) +#define PMU_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) +#define PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define PMU_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGADJ_MASK) +#define PMU_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) +#define PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) +#define PMU_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & PMU_MISC0_TOG_REFTOP_VBGUP_MASK) +#define PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) +#define PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..SUSPEND (DSM) + * 0b01..Analog regulators are ON. + * 0b10..STOP (lower power) + * 0b11..STOP (very lower power) + */ +#define PMU_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & PMU_MISC0_TOG_STOP_MODE_CONFIG_MASK) +#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) +#define PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define PMU_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & PMU_MISC0_TOG_DISCON_HIGH_SNVS_MASK) +#define PMU_MISC0_TOG_OSC_I_MASK (0x6000U) +#define PMU_MISC0_TOG_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define PMU_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_I_SHIFT)) & PMU_MISC0_TOG_OSC_I_MASK) +#define PMU_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) +#define PMU_MISC0_TOG_OSC_XTALOK_SHIFT (15U) +#define PMU_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_MASK) +#define PMU_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) +#define PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) +#define PMU_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & PMU_MISC0_TOG_OSC_XTALOK_EN_MASK) +#define PMU_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) +#define PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define PMU_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & PMU_MISC0_TOG_CLKGATE_CTRL_MASK) +#define PMU_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) +#define PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define PMU_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & PMU_MISC0_TOG_CLKGATE_DELAY_MASK) +#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define PMU_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & PMU_MISC0_TOG_RTC_XTAL_SOURCE_MASK) +#define PMU_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) +#define PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) +#define PMU_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & PMU_MISC0_TOG_XTAL_24M_PWD_MASK) +#define PMU_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) +#define PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define PMU_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & PMU_MISC0_TOG_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC1 - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_LVDS1_CLK_SEL_MASK (0x1FU) +#define PMU_MISC1_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define PMU_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_LVDS2_CLK_SEL_MASK) +#define PMU_MISC1_LVDSCLK1_OBEN_MASK (0x400U) +#define PMU_MISC1_LVDSCLK1_OBEN_SHIFT (10U) +#define PMU_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_OBEN_MASK) +#define PMU_MISC1_LVDSCLK1_IBEN_MASK (0x1000U) +#define PMU_MISC1_LVDSCLK1_IBEN_SHIFT (12U) +#define PMU_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_LVDSCLK2_IBEN_MASK) +#define PMU_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_IRQ_ANA_BO_MASK) +#define PMU_MISC1_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_SET - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU) +#define PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define PMU_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_SET_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_SET_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_SET_LVDS2_CLK_SEL_MASK) +#define PMU_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U) +#define PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U) +#define PMU_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_SET_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_SET_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_OBEN_MASK) +#define PMU_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U) +#define PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U) +#define PMU_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_SET_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_SET_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_SET_LVDSCLK2_IBEN_MASK) +#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_SET_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_SET_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_SET_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_SET_IRQ_ANA_BO_MASK) +#define PMU_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_SET_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_SET_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_SET_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_CLR - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU) +#define PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define PMU_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_CLR_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_CLR_LVDS2_CLK_SEL_MASK) +#define PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U) +#define PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U) +#define PMU_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_CLR_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_OBEN_MASK) +#define PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U) +#define PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U) +#define PMU_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_CLR_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_CLR_LVDSCLK2_IBEN_MASK) +#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_CLR_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_ANA_BO_MASK) +#define PMU_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_CLR_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC1_TOG - Miscellaneous Register 1 */ +/*! @{ */ +#define PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU) +#define PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U) +/*! LVDS1_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + */ +#define PMU_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS1_CLK_SEL_MASK) +#define PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK (0x3E0U) +#define PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT (5U) +/*! LVDS2_CLK_SEL + * 0b00000..Arm PLL + * 0b00001..System PLL + * 0b00010..ref_pfd4_clk == pll2_pfd0_clk + * 0b00011..ref_pfd5_clk == pll2_pfd1_clk + * 0b00100..ref_pfd6_clk == pll2_pfd2_clk + * 0b00101..ref_pfd7_clk == pll2_pfd3_clk + * 0b00110..Audio PLL + * 0b00111..Video PLL + * 0b01000..MLB PLL + * 0b01001..ethernet ref clock (ENET_PLL) + * 0b01010..PCIe ref clock (125M) + * 0b01011..SATA ref clock (100M) + * 0b01100..USB1 PLL clock + * 0b01101..USB2 PLL clock + * 0b01110..ref_pfd0_clk == pll3_pfd0_clk + * 0b01111..ref_pfd1_clk == pll3_pfd1_clk + * 0b10000..ref_pfd2_clk == pll3_pfd2_clk + * 0b10001..ref_pfd3_clk == pll3_pfd3_clk + * 0b10010..xtal (24M) + * 0b10011..LVDS1 (loopback) + * 0b10100..LVDS2 (not useful) + */ +#define PMU_MISC1_TOG_LVDS2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDS2_CLK_SEL_SHIFT)) & PMU_MISC1_TOG_LVDS2_CLK_SEL_MASK) +#define PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U) +#define PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U) +#define PMU_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_OBEN_MASK) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK (0x800U) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT (11U) +#define PMU_MISC1_TOG_LVDSCLK2_OBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_OBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_OBEN_MASK) +#define PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U) +#define PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U) +#define PMU_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK1_IBEN_MASK) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK (0x2000U) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT (13U) +#define PMU_MISC1_TOG_LVDSCLK2_IBEN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_LVDSCLK2_IBEN_SHIFT)) & PMU_MISC1_TOG_LVDSCLK2_IBEN_MASK) +#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U) +#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U) +#define PMU_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK) +#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U) +#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U) +#define PMU_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & PMU_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK) +#define PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U) +#define PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U) +#define PMU_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPPANIC_MASK) +#define PMU_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U) +#define PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U) +#define PMU_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPLOW_MASK) +#define PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U) +#define PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U) +#define PMU_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & PMU_MISC1_TOG_IRQ_TEMPHIGH_MASK) +#define PMU_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U) +#define PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U) +#define PMU_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_ANA_BO_MASK) +#define PMU_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U) +#define PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U) +#define PMU_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & PMU_MISC1_TOG_IRQ_DIG_BO_MASK) +/*! @} */ + +/*! @name MISC2 - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_REG0_BO_STATUS_MASK) +#define PMU_MISC2_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_PLL3_disable_SHIFT)) & PMU_MISC2_PLL3_disable_MASK) +#define PMU_MISC2_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_REG1_BO_STATUS_MASK) +#define PMU_MISC2_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_REG2_BO_STATUS_MASK) +#define PMU_MISC2_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_REG2_OK_SHIFT (22U) +#define PMU_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_OK_SHIFT)) & PMU_MISC2_REG2_OK_MASK) +#define PMU_MISC2_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_REG0_STEP_TIME_MASK) +#define PMU_MISC2_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_REG1_STEP_TIME_MASK) +#define PMU_MISC2_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_REG2_STEP_TIME_MASK) +#define PMU_MISC2_VIDEO_DIV_MASK (0xC0000000U) +#define PMU_MISC2_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define PMU_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_VIDEO_DIV_SHIFT)) & PMU_MISC2_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_SET - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_SET_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_SET_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG0_BO_STATUS_MASK) +#define PMU_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_SET_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_SET_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_PLL3_disable_SHIFT)) & PMU_MISC2_SET_PLL3_disable_MASK) +#define PMU_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_SET_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_SET_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG1_BO_STATUS_MASK) +#define PMU_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_SET_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_SET_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_SET_REG2_BO_STATUS_MASK) +#define PMU_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_SET_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_SET_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_SET_REG2_OK_SHIFT (22U) +#define PMU_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_OK_SHIFT)) & PMU_MISC2_SET_REG2_OK_MASK) +#define PMU_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_SET_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_SET_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG0_STEP_TIME_MASK) +#define PMU_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_SET_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG1_STEP_TIME_MASK) +#define PMU_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_SET_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_SET_REG2_STEP_TIME_MASK) +#define PMU_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U) +#define PMU_MISC2_SET_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define PMU_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_SET_VIDEO_DIV_SHIFT)) & PMU_MISC2_SET_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_CLR - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG0_BO_STATUS_MASK) +#define PMU_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_CLR_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_CLR_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_PLL3_disable_SHIFT)) & PMU_MISC2_CLR_PLL3_disable_MASK) +#define PMU_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG1_BO_STATUS_MASK) +#define PMU_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_CLR_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_CLR_REG2_BO_STATUS_MASK) +#define PMU_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_CLR_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_CLR_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_CLR_REG2_OK_SHIFT (22U) +#define PMU_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_OK_SHIFT)) & PMU_MISC2_CLR_REG2_OK_MASK) +#define PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_CLR_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG0_STEP_TIME_MASK) +#define PMU_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG1_STEP_TIME_MASK) +#define PMU_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_CLR_REG2_STEP_TIME_MASK) +#define PMU_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U) +#define PMU_MISC2_CLR_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define PMU_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_CLR_VIDEO_DIV_SHIFT)) & PMU_MISC2_CLR_VIDEO_DIV_MASK) +/*! @} */ + +/*! @name MISC2_TOG - Miscellaneous Control Register */ +/*! @{ */ +#define PMU_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U) +#define PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U) +/*! REG0_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG0_BO_OFFSET_MASK) +#define PMU_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U) +#define PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U) +/*! REG0_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG0_BO_STATUS_MASK) +#define PMU_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U) +#define PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U) +#define PMU_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG0_ENABLE_BO_MASK) +#define PMU_MISC2_TOG_PLL3_disable_MASK (0x80U) +#define PMU_MISC2_TOG_PLL3_disable_SHIFT (7U) +#define PMU_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_PLL3_disable_SHIFT)) & PMU_MISC2_TOG_PLL3_disable_MASK) +#define PMU_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U) +#define PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U) +/*! REG1_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG1_BO_OFFSET_MASK) +#define PMU_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U) +#define PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U) +/*! REG1_BO_STATUS + * 0b1..Brownout, supply is below target minus brownout offset. + */ +#define PMU_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG1_BO_STATUS_MASK) +#define PMU_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U) +#define PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U) +#define PMU_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG1_ENABLE_BO_MASK) +#define PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U) +#define PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U) +/*! AUDIO_DIV_LSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_LSB_MASK) +#define PMU_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U) +#define PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U) +/*! REG2_BO_OFFSET + * 0b100..Brownout offset = 0.100V + * 0b111..Brownout offset = 0.175V + */ +#define PMU_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & PMU_MISC2_TOG_REG2_BO_OFFSET_MASK) +#define PMU_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U) +#define PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U) +#define PMU_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & PMU_MISC2_TOG_REG2_BO_STATUS_MASK) +#define PMU_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U) +#define PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U) +#define PMU_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & PMU_MISC2_TOG_REG2_ENABLE_BO_MASK) +#define PMU_MISC2_TOG_REG2_OK_MASK (0x400000U) +#define PMU_MISC2_TOG_REG2_OK_SHIFT (22U) +#define PMU_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_OK_SHIFT)) & PMU_MISC2_TOG_REG2_OK_MASK) +#define PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U) +#define PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U) +/*! AUDIO_DIV_MSB + * 0b0..divide by 1 (Default) + * 0b1..divide by 2 + */ +#define PMU_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & PMU_MISC2_TOG_AUDIO_DIV_MSB_MASK) +#define PMU_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U) +#define PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U) +/*! REG0_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG0_STEP_TIME_MASK) +#define PMU_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U) +#define PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U) +/*! REG1_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG1_STEP_TIME_MASK) +#define PMU_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U) +#define PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U) +/*! REG2_STEP_TIME + * 0b00..64 + * 0b01..128 + * 0b10..256 + * 0b11..512 + */ +#define PMU_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & PMU_MISC2_TOG_REG2_STEP_TIME_MASK) +#define PMU_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U) +#define PMU_MISC2_TOG_VIDEO_DIV_SHIFT (30U) +/*! VIDEO_DIV + * 0b00..divide by 1 (Default) + * 0b01..divide by 2 + * 0b10..divide by 1 + * 0b11..divide by 4 + */ +#define PMU_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MISC2_TOG_VIDEO_DIV_SHIFT)) & PMU_MISC2_TOG_VIDEO_DIV_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PMU_Register_Masks */ + + +/* PMU - Peripheral instance base addresses */ +/** Peripheral PMU base address */ +#define PMU_BASE (0x400D8000u) +/** Peripheral PMU base pointer */ +#define PMU ((PMU_Type *)PMU_BASE) +/** Array initializer of PMU peripheral base addresses */ +#define PMU_BASE_ADDRS { PMU_BASE } +/** Array initializer of PMU peripheral base pointers */ +#define PMU_BASE_PTRS { PMU } + +/*! + * @} + */ /* end of group PMU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer + * @{ + */ + +/** PWM - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x60 */ + __I uint16_t CNT; /**< Counter Register, array offset: 0x0, array step: 0x60 */ + __IO uint16_t INIT; /**< Initial Count Register, array offset: 0x2, array step: 0x60 */ + __IO uint16_t CTRL2; /**< Control 2 Register, array offset: 0x4, array step: 0x60 */ + __IO uint16_t CTRL; /**< Control Register, array offset: 0x6, array step: 0x60 */ + uint8_t RESERVED_0[2]; + __IO uint16_t VAL0; /**< Value Register 0, array offset: 0xA, array step: 0x60 */ + __IO uint16_t FRACVAL1; /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */ + __IO uint16_t VAL1; /**< Value Register 1, array offset: 0xE, array step: 0x60 */ + __IO uint16_t FRACVAL2; /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */ + __IO uint16_t VAL2; /**< Value Register 2, array offset: 0x12, array step: 0x60 */ + __IO uint16_t FRACVAL3; /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */ + __IO uint16_t VAL3; /**< Value Register 3, array offset: 0x16, array step: 0x60 */ + __IO uint16_t FRACVAL4; /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */ + __IO uint16_t VAL4; /**< Value Register 4, array offset: 0x1A, array step: 0x60 */ + __IO uint16_t FRACVAL5; /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */ + __IO uint16_t VAL5; /**< Value Register 5, array offset: 0x1E, array step: 0x60 */ + __IO uint16_t FRCTRL; /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */ + __IO uint16_t OCTRL; /**< Output Control Register, array offset: 0x22, array step: 0x60 */ + __IO uint16_t STS; /**< Status Register, array offset: 0x24, array step: 0x60 */ + __IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */ + __IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */ + __IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */ + __IO uint16_t DISMAP[2]; /**< Fault Disable Mapping Register 0..Fault Disable Mapping Register 1, array offset: 0x2C, array step: index*0x60, index2*0x2 */ + __IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */ + __IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */ + __IO uint16_t CAPTCTRLA; /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */ + __IO uint16_t CAPTCOMPA; /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */ + __IO uint16_t CAPTCTRLB; /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */ + __IO uint16_t CAPTCOMPB; /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */ + __IO uint16_t CAPTCTRLX; /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */ + __IO uint16_t CAPTCOMPX; /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */ + __I uint16_t CVAL0; /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */ + __I uint16_t CVAL0CYC; /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */ + __I uint16_t CVAL1; /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */ + __I uint16_t CVAL1CYC; /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */ + __I uint16_t CVAL2; /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */ + __I uint16_t CVAL2CYC; /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */ + __I uint16_t CVAL3; /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */ + __I uint16_t CVAL3CYC; /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */ + __I uint16_t CVAL4; /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */ + __I uint16_t CVAL4CYC; /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */ + __I uint16_t CVAL5; /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */ + __I uint16_t CVAL5CYC; /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */ + uint8_t RESERVED_1[8]; + } SM[4]; + __IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */ + __IO uint16_t MASK; /**< Mask Register, offset: 0x182 */ + __IO uint16_t SWCOUT; /**< Software Controlled Output Register, offset: 0x184 */ + __IO uint16_t DTSRCSEL; /**< PWM Source Select Register, offset: 0x186 */ + __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ + __IO uint16_t MCTRL2; /**< Master Control 2 Register, offset: 0x18A */ + __IO uint16_t FCTRL; /**< Fault Control Register, offset: 0x18C */ + __IO uint16_t FSTS; /**< Fault Status Register, offset: 0x18E */ + __IO uint16_t FFILT; /**< Fault Filter Register, offset: 0x190 */ + __IO uint16_t FTST; /**< Fault Test Register, offset: 0x192 */ + __IO uint16_t FCTRL2; /**< Fault Control 2 Register, offset: 0x194 */ +} PWM_Type; + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/*! @name CNT - Counter Register */ +/*! @{ */ +#define PWM_CNT_CNT_MASK (0xFFFFU) +#define PWM_CNT_CNT_SHIFT (0U) +#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CNT */ +#define PWM_CNT_COUNT (4U) + +/*! @name INIT - Initial Count Register */ +/*! @{ */ +#define PWM_INIT_INIT_MASK (0xFFFFU) +#define PWM_INIT_INIT_SHIFT (0U) +#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK) +/*! @} */ + +/* The count of PWM_INIT */ +#define PWM_INIT_COUNT (4U) + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ +#define PWM_CTRL2_CLK_SEL_MASK (0x3U) +#define PWM_CTRL2_CLK_SEL_SHIFT (0U) +/*! CLK_SEL - Clock Source Select + * 0b00..The IPBus clock is used as the clock for the local prescaler and counter. + * 0b01..EXT_CLK is used as the clock for the local prescaler and counter. + * 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This + * setting should not be used in submodule 0 as it will force the clock to logic 0. + * 0b11..reserved + */ +#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) +#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U) +#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U) +/*! RELOAD_SEL - Reload Source Select + * 0b0..The local RELOAD signal is used to reload registers. + * 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used + * in submodule 0 as it will force the RELOAD signal to logic 0. + */ +#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK) +#define PWM_CTRL2_FORCE_SEL_MASK (0x38U) +#define PWM_CTRL2_FORCE_SEL_SHIFT (3U) +/*! FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + * 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + * 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in + * submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + * 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should + * not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b100..The local sync signal from this submodule is used to force updates. + * 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in + * submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + * 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates. + * 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + */ +#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK) +#define PWM_CTRL2_FORCE_MASK (0x40U) +#define PWM_CTRL2_FORCE_SHIFT (6U) +#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK) +#define PWM_CTRL2_FRCEN_MASK (0x80U) +#define PWM_CTRL2_FRCEN_SHIFT (7U) +/*! FRCEN - FRCEN + * 0b0..Initialization from a FORCE_OUT is disabled. + * 0b1..Initialization from a FORCE_OUT is enabled. + */ +#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK) +#define PWM_CTRL2_INIT_SEL_MASK (0x300U) +#define PWM_CTRL2_INIT_SEL_SHIFT (8U) +/*! INIT_SEL - Initialization Control Select + * 0b00..Local sync (PWM_X) causes initialization. + * 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as + * it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master + * reload occurs. + * 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it + * will force the INIT signal to logic 0. + * 0b11..EXT_SYNC causes initialization. + */ +#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK) +#define PWM_CTRL2_PWMX_INIT_MASK (0x400U) +#define PWM_CTRL2_PWMX_INIT_SHIFT (10U) +#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK) +#define PWM_CTRL2_PWM45_INIT_MASK (0x800U) +#define PWM_CTRL2_PWM45_INIT_SHIFT (11U) +#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK) +#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U) +#define PWM_CTRL2_PWM23_INIT_SHIFT (12U) +#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK) +#define PWM_CTRL2_INDEP_MASK (0x2000U) +#define PWM_CTRL2_INDEP_SHIFT (13U) +/*! INDEP - Independent or Complementary Pair Operation + * 0b0..PWM_A and PWM_B form a complementary PWM pair. + * 0b1..PWM_A and PWM_B outputs are independent PWMs. + */ +#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK) +#define PWM_CTRL2_WAITEN_MASK (0x4000U) +#define PWM_CTRL2_WAITEN_SHIFT (14U) +#define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK) +#define PWM_CTRL2_DBGEN_MASK (0x8000U) +#define PWM_CTRL2_DBGEN_SHIFT (15U) +#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK) +/*! @} */ + +/* The count of PWM_CTRL2 */ +#define PWM_CTRL2_COUNT (4U) + +/*! @name CTRL - Control Register */ +/*! @{ */ +#define PWM_CTRL_DBLEN_MASK (0x1U) +#define PWM_CTRL_DBLEN_SHIFT (0U) +/*! DBLEN - Double Switching Enable + * 0b0..Double switching disabled. + * 0b1..Double switching enabled. + */ +#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) +#define PWM_CTRL_DBLX_MASK (0x2U) +#define PWM_CTRL_DBLX_SHIFT (1U) +/*! DBLX - PWMX Double Switching Enable + * 0b0..PWMX double pulse disabled. + * 0b1..PWMX double pulse enabled. + */ +#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK) +#define PWM_CTRL_LDMOD_MASK (0x4U) +#define PWM_CTRL_LDMOD_SHIFT (2U) +/*! LDMOD - Load Mode Select + * 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + * 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. + * In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + */ +#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK) +#define PWM_CTRL_SPLIT_MASK (0x8U) +#define PWM_CTRL_SPLIT_SHIFT (3U) +/*! SPLIT - Split the DBLPWM signal to PWMA and PWMB + * 0b0..DBLPWM is not split. PWMA and PWMB each have double pulses. + * 0b1..DBLPWM is split to PWMA and PWMB. + */ +#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) +#define PWM_CTRL_PRSC_MASK (0x70U) +#define PWM_CTRL_PRSC_SHIFT (4U) +/*! PRSC - Prescaler + * 0b000..PWM clock frequency = fclk + * 0b001..PWM clock frequency = fclk/2 + * 0b010..PWM clock frequency = fclk/4 + * 0b011..PWM clock frequency = fclk/8 + * 0b100..PWM clock frequency = fclk/16 + * 0b101..PWM clock frequency = fclk/32 + * 0b110..PWM clock frequency = fclk/64 + * 0b111..PWM clock frequency = fclk/128 + */ +#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) +#define PWM_CTRL_COMPMODE_MASK (0x80U) +#define PWM_CTRL_COMPMODE_SHIFT (7U) +/*! COMPMODE - Compare Mode + * 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges + * are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA + * output that is high at the end of a period will maintain this state until a match with VAL3 clears the + * output in the following period. + * 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This + * means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register + * values. This implies that a PWMA output that is high at the end of a period could go low at the start of the + * next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + */ +#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK) +#define PWM_CTRL_DT_MASK (0x300U) +#define PWM_CTRL_DT_SHIFT (8U) +#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK) +#define PWM_CTRL_FULL_MASK (0x400U) +#define PWM_CTRL_FULL_SHIFT (10U) +/*! FULL - Full Cycle Reload + * 0b0..Full-cycle reloads disabled. + * 0b1..Full-cycle reloads enabled. + */ +#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK) +#define PWM_CTRL_HALF_MASK (0x800U) +#define PWM_CTRL_HALF_SHIFT (11U) +/*! HALF - Half Cycle Reload + * 0b0..Half-cycle reloads disabled. + * 0b1..Half-cycle reloads enabled. + */ +#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK) +#define PWM_CTRL_LDFQ_MASK (0xF000U) +#define PWM_CTRL_LDFQ_SHIFT (12U) +/*! LDFQ - Load Frequency + * 0b0000..Every PWM opportunity + * 0b0001..Every 2 PWM opportunities + * 0b0010..Every 3 PWM opportunities + * 0b0011..Every 4 PWM opportunities + * 0b0100..Every 5 PWM opportunities + * 0b0101..Every 6 PWM opportunities + * 0b0110..Every 7 PWM opportunities + * 0b0111..Every 8 PWM opportunities + * 0b1000..Every 9 PWM opportunities + * 0b1001..Every 10 PWM opportunities + * 0b1010..Every 11 PWM opportunities + * 0b1011..Every 12 PWM opportunities + * 0b1100..Every 13 PWM opportunities + * 0b1101..Every 14 PWM opportunities + * 0b1110..Every 15 PWM opportunities + * 0b1111..Every 16 PWM opportunities + */ +#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK) +/*! @} */ + +/* The count of PWM_CTRL */ +#define PWM_CTRL_COUNT (4U) + +/*! @name VAL0 - Value Register 0 */ +/*! @{ */ +#define PWM_VAL0_VAL0_MASK (0xFFFFU) +#define PWM_VAL0_VAL0_SHIFT (0U) +#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK) +/*! @} */ + +/* The count of PWM_VAL0 */ +#define PWM_VAL0_COUNT (4U) + +/*! @name FRACVAL1 - Fractional Value Register 1 */ +/*! @{ */ +#define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U) +#define PWM_FRACVAL1_FRACVAL1_SHIFT (11U) +#define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL1 */ +#define PWM_FRACVAL1_COUNT (4U) + +/*! @name VAL1 - Value Register 1 */ +/*! @{ */ +#define PWM_VAL1_VAL1_MASK (0xFFFFU) +#define PWM_VAL1_VAL1_SHIFT (0U) +#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK) +/*! @} */ + +/* The count of PWM_VAL1 */ +#define PWM_VAL1_COUNT (4U) + +/*! @name FRACVAL2 - Fractional Value Register 2 */ +/*! @{ */ +#define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U) +#define PWM_FRACVAL2_FRACVAL2_SHIFT (11U) +#define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL2 */ +#define PWM_FRACVAL2_COUNT (4U) + +/*! @name VAL2 - Value Register 2 */ +/*! @{ */ +#define PWM_VAL2_VAL2_MASK (0xFFFFU) +#define PWM_VAL2_VAL2_SHIFT (0U) +#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK) +/*! @} */ + +/* The count of PWM_VAL2 */ +#define PWM_VAL2_COUNT (4U) + +/*! @name FRACVAL3 - Fractional Value Register 3 */ +/*! @{ */ +#define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U) +#define PWM_FRACVAL3_FRACVAL3_SHIFT (11U) +#define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL3 */ +#define PWM_FRACVAL3_COUNT (4U) + +/*! @name VAL3 - Value Register 3 */ +/*! @{ */ +#define PWM_VAL3_VAL3_MASK (0xFFFFU) +#define PWM_VAL3_VAL3_SHIFT (0U) +#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK) +/*! @} */ + +/* The count of PWM_VAL3 */ +#define PWM_VAL3_COUNT (4U) + +/*! @name FRACVAL4 - Fractional Value Register 4 */ +/*! @{ */ +#define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U) +#define PWM_FRACVAL4_FRACVAL4_SHIFT (11U) +#define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL4 */ +#define PWM_FRACVAL4_COUNT (4U) + +/*! @name VAL4 - Value Register 4 */ +/*! @{ */ +#define PWM_VAL4_VAL4_MASK (0xFFFFU) +#define PWM_VAL4_VAL4_SHIFT (0U) +#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK) +/*! @} */ + +/* The count of PWM_VAL4 */ +#define PWM_VAL4_COUNT (4U) + +/*! @name FRACVAL5 - Fractional Value Register 5 */ +/*! @{ */ +#define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U) +#define PWM_FRACVAL5_FRACVAL5_SHIFT (11U) +#define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK) +/*! @} */ + +/* The count of PWM_FRACVAL5 */ +#define PWM_FRACVAL5_COUNT (4U) + +/*! @name VAL5 - Value Register 5 */ +/*! @{ */ +#define PWM_VAL5_VAL5_MASK (0xFFFFU) +#define PWM_VAL5_VAL5_SHIFT (0U) +#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK) +/*! @} */ + +/* The count of PWM_VAL5 */ +#define PWM_VAL5_COUNT (4U) + +/*! @name FRCTRL - Fractional Control Register */ +/*! @{ */ +#define PWM_FRCTRL_FRAC1_EN_MASK (0x2U) +#define PWM_FRCTRL_FRAC1_EN_SHIFT (1U) +/*! FRAC1_EN - Fractional Cycle PWM Period Enable + * 0b0..Disable fractional cycle length for the PWM period. + * 0b1..Enable fractional cycle length for the PWM period. + */ +#define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK) +#define PWM_FRCTRL_FRAC23_EN_MASK (0x4U) +#define PWM_FRCTRL_FRAC23_EN_SHIFT (2U) +/*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A + * 0b0..Disable fractional cycle placement for PWM_A. + * 0b1..Enable fractional cycle placement for PWM_A. + */ +#define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK) +#define PWM_FRCTRL_FRAC45_EN_MASK (0x10U) +#define PWM_FRCTRL_FRAC45_EN_SHIFT (4U) +/*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B + * 0b0..Disable fractional cycle placement for PWM_B. + * 0b1..Enable fractional cycle placement for PWM_B. + */ +#define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK) +#define PWM_FRCTRL_FRAC_PU_MASK (0x100U) +#define PWM_FRCTRL_FRAC_PU_SHIFT (8U) +/*! FRAC_PU - Fractional Delay Circuit Power Up + * 0b0..Turn off fractional delay logic. + * 0b1..Power up fractional delay logic. + */ +#define PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK) +#define PWM_FRCTRL_TEST_MASK (0x8000U) +#define PWM_FRCTRL_TEST_SHIFT (15U) +#define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK) +/*! @} */ + +/* The count of PWM_FRCTRL */ +#define PWM_FRCTRL_COUNT (4U) + +/*! @name OCTRL - Output Control Register */ +/*! @{ */ +#define PWM_OCTRL_PWMXFS_MASK (0x3U) +#define PWM_OCTRL_PWMXFS_SHIFT (0U) +/*! PWMXFS - PWM_X Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10..Output is tristated. + * 0b11..Output is tristated. + */ +#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) +#define PWM_OCTRL_PWMBFS_MASK (0xCU) +#define PWM_OCTRL_PWMBFS_SHIFT (2U) +/*! PWMBFS - PWM_B Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10..Output is tristated. + * 0b11..Output is tristated. + */ +#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK) +#define PWM_OCTRL_PWMAFS_MASK (0x30U) +#define PWM_OCTRL_PWMAFS_SHIFT (4U) +/*! PWMAFS - PWM_A Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10..Output is tristated. + * 0b11..Output is tristated. + */ +#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK) +#define PWM_OCTRL_POLX_MASK (0x100U) +#define PWM_OCTRL_POLX_SHIFT (8U) +/*! POLX - PWM_X Output Polarity + * 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + * 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK) +#define PWM_OCTRL_POLB_MASK (0x200U) +#define PWM_OCTRL_POLB_SHIFT (9U) +/*! POLB - PWM_B Output Polarity + * 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + * 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK) +#define PWM_OCTRL_POLA_MASK (0x400U) +#define PWM_OCTRL_POLA_SHIFT (10U) +/*! POLA - PWM_A Output Polarity + * 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + * 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK) +#define PWM_OCTRL_PWMX_IN_MASK (0x2000U) +#define PWM_OCTRL_PWMX_IN_SHIFT (13U) +#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK) +#define PWM_OCTRL_PWMB_IN_MASK (0x4000U) +#define PWM_OCTRL_PWMB_IN_SHIFT (14U) +#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK) +#define PWM_OCTRL_PWMA_IN_MASK (0x8000U) +#define PWM_OCTRL_PWMA_IN_SHIFT (15U) +#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK) +/*! @} */ + +/* The count of PWM_OCTRL */ +#define PWM_OCTRL_COUNT (4U) + +/*! @name STS - Status Register */ +/*! @{ */ +#define PWM_STS_CMPF_MASK (0x3FU) +#define PWM_STS_CMPF_SHIFT (0U) +/*! CMPF - Compare Flags + * 0b000000..No compare event has occurred for a particular VALx value. + * 0b000001..A compare event has occurred for a particular VALx value. + */ +#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) +#define PWM_STS_CFX0_MASK (0x40U) +#define PWM_STS_CFX0_SHIFT (6U) +#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK) +#define PWM_STS_CFX1_MASK (0x80U) +#define PWM_STS_CFX1_SHIFT (7U) +#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK) +#define PWM_STS_CFB0_MASK (0x100U) +#define PWM_STS_CFB0_SHIFT (8U) +#define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK) +#define PWM_STS_CFB1_MASK (0x200U) +#define PWM_STS_CFB1_SHIFT (9U) +#define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK) +#define PWM_STS_CFA0_MASK (0x400U) +#define PWM_STS_CFA0_SHIFT (10U) +#define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK) +#define PWM_STS_CFA1_MASK (0x800U) +#define PWM_STS_CFA1_SHIFT (11U) +#define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK) +#define PWM_STS_RF_MASK (0x1000U) +#define PWM_STS_RF_SHIFT (12U) +/*! RF - Reload Flag + * 0b0..No new reload cycle since last STS[RF] clearing + * 0b1..New reload cycle since last STS[RF] clearing + */ +#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK) +#define PWM_STS_REF_MASK (0x2000U) +#define PWM_STS_REF_SHIFT (13U) +/*! REF - Reload Error Flag + * 0b0..No reload error occurred. + * 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + */ +#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK) +#define PWM_STS_RUF_MASK (0x4000U) +#define PWM_STS_RUF_SHIFT (14U) +/*! RUF - Registers Updated Flag + * 0b0..No register update has occurred since last reload. + * 0b1..At least one of the double buffered registers has been updated since the last reload. + */ +#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK) +/*! @} */ + +/* The count of PWM_STS */ +#define PWM_STS_COUNT (4U) + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ +#define PWM_INTEN_CMPIE_MASK (0x3FU) +#define PWM_INTEN_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enables + * 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. + * 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request. + */ +#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) +#define PWM_INTEN_CX0IE_MASK (0x40U) +#define PWM_INTEN_CX0IE_SHIFT (6U) +/*! CX0IE - Capture X 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX0]. + * 0b1..Interrupt request enabled for STS[CFX0]. + */ +#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) +#define PWM_INTEN_CX1IE_MASK (0x80U) +#define PWM_INTEN_CX1IE_SHIFT (7U) +/*! CX1IE - Capture X 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX1]. + * 0b1..Interrupt request enabled for STS[CFX1]. + */ +#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) +#define PWM_INTEN_CB0IE_MASK (0x100U) +#define PWM_INTEN_CB0IE_SHIFT (8U) +/*! CB0IE - Capture B 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB0]. + * 0b1..Interrupt request enabled for STS[CFB0]. + */ +#define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) +#define PWM_INTEN_CB1IE_MASK (0x200U) +#define PWM_INTEN_CB1IE_SHIFT (9U) +/*! CB1IE - Capture B 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFB1]. + * 0b1..Interrupt request enabled for STS[CFB1]. + */ +#define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) +#define PWM_INTEN_CA0IE_MASK (0x400U) +#define PWM_INTEN_CA0IE_SHIFT (10U) +/*! CA0IE - Capture A 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA0]. + * 0b1..Interrupt request enabled for STS[CFA0]. + */ +#define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) +#define PWM_INTEN_CA1IE_MASK (0x800U) +#define PWM_INTEN_CA1IE_SHIFT (11U) +/*! CA1IE - Capture A 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFA1]. + * 0b1..Interrupt request enabled for STS[CFA1]. + */ +#define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) +#define PWM_INTEN_RIE_MASK (0x1000U) +#define PWM_INTEN_RIE_SHIFT (12U) +/*! RIE - Reload Interrupt Enable + * 0b0..STS[RF] CPU interrupt requests disabled + * 0b1..STS[RF] CPU interrupt requests enabled + */ +#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) +#define PWM_INTEN_REIE_MASK (0x2000U) +#define PWM_INTEN_REIE_SHIFT (13U) +/*! REIE - Reload Error Interrupt Enable + * 0b0..STS[REF] CPU interrupt requests disabled + * 0b1..STS[REF] CPU interrupt requests enabled + */ +#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) +/*! @} */ + +/* The count of PWM_INTEN */ +#define PWM_INTEN_COUNT (4U) + +/*! @name DMAEN - DMA Enable Register */ +/*! @{ */ +#define PWM_DMAEN_CX0DE_MASK (0x1U) +#define PWM_DMAEN_CX0DE_SHIFT (0U) +#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) +#define PWM_DMAEN_CX1DE_MASK (0x2U) +#define PWM_DMAEN_CX1DE_SHIFT (1U) +#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK) +#define PWM_DMAEN_CB0DE_MASK (0x4U) +#define PWM_DMAEN_CB0DE_SHIFT (2U) +#define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK) +#define PWM_DMAEN_CB1DE_MASK (0x8U) +#define PWM_DMAEN_CB1DE_SHIFT (3U) +#define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK) +#define PWM_DMAEN_CA0DE_MASK (0x10U) +#define PWM_DMAEN_CA0DE_SHIFT (4U) +#define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK) +#define PWM_DMAEN_CA1DE_MASK (0x20U) +#define PWM_DMAEN_CA1DE_SHIFT (5U) +#define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK) +#define PWM_DMAEN_CAPTDE_MASK (0xC0U) +#define PWM_DMAEN_CAPTDE_SHIFT (6U) +/*! CAPTDE - Capture DMA Enable Source Select + * 0b00..Read DMA requests disabled. + * 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], + * DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to + * which watermark(s) the DMA request is sensitive. + * 0b10..A local sync (VAL1 matches counter) sets the read DMA request. + * 0b11..A local reload (STS[RF] being set) sets the read DMA request. + */ +#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK) +#define PWM_DMAEN_FAND_MASK (0x100U) +#define PWM_DMAEN_FAND_SHIFT (8U) +/*! FAND - FIFO Watermark AND Control + * 0b0..Selected FIFO watermarks are OR'ed together. + * 0b1..Selected FIFO watermarks are AND'ed together. + */ +#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK) +#define PWM_DMAEN_VALDE_MASK (0x200U) +#define PWM_DMAEN_VALDE_SHIFT (9U) +/*! VALDE - Value Registers DMA Enable + * 0b0..DMA write requests disabled + * 0b1..DMA write requests for the VALx and FRACVALx registers enabled + */ +#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) +/*! @} */ + +/* The count of PWM_DMAEN */ +#define PWM_DMAEN_COUNT (4U) + +/*! @name TCTRL - Output Trigger Control Register */ +/*! @{ */ +#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) +#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) +/*! OUT_TRIG_EN - Output Trigger Enables + * 0b000000..PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + * 0b000001..PWM_OUT_TRIGx will set when the counter value matches the VALx value. + */ +#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) +#define PWM_TCTRL_TRGFRQ_MASK (0x1000U) +#define PWM_TCTRL_TRGFRQ_SHIFT (12U) +/*! TRGFRQ - Trigger frequency + * 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + * 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM + * is not reloaded every period due to CTRL[LDFQ] being non-zero. + */ +#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK) +#define PWM_TCTRL_PWBOT1_MASK (0x4000U) +#define PWM_TCTRL_PWBOT1_SHIFT (14U) +/*! PWBOT1 - Output Trigger 1 Source Select + * 0b0..Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + * 0b1..Route the PWMB output to the PWM_OUT_TRIG1 port. + */ +#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK) +#define PWM_TCTRL_PWAOT0_MASK (0x8000U) +#define PWM_TCTRL_PWAOT0_SHIFT (15U) +/*! PWAOT0 - Output Trigger 0 Source Select + * 0b0..Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + * 0b1..Route the PWMA output to the PWM_OUT_TRIG0 port. + */ +#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) +/*! @} */ + +/* The count of PWM_TCTRL */ +#define PWM_TCTRL_COUNT (4U) + +/*! @name DISMAP - Fault Disable Mapping Register 0..Fault Disable Mapping Register 1 */ +/*! @{ */ +#define PWM_DISMAP_DIS0A_MASK (0xFU) +#define PWM_DISMAP_DIS0A_SHIFT (0U) +#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) +#define PWM_DISMAP_DIS1A_MASK (0xFU) +#define PWM_DISMAP_DIS1A_SHIFT (0U) +#define PWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK) +#define PWM_DISMAP_DIS0B_MASK (0xF0U) +#define PWM_DISMAP_DIS0B_SHIFT (4U) +#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK) +#define PWM_DISMAP_DIS1B_MASK (0xF0U) +#define PWM_DISMAP_DIS1B_SHIFT (4U) +#define PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK) +#define PWM_DISMAP_DIS0X_MASK (0xF00U) +#define PWM_DISMAP_DIS0X_SHIFT (8U) +#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) +#define PWM_DISMAP_DIS1X_MASK (0xF00U) +#define PWM_DISMAP_DIS1X_SHIFT (8U) +#define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK) +/*! @} */ + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT (4U) + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT2 (2U) + +/*! @name DTCNT0 - Deadtime Count Register 0 */ +/*! @{ */ +#define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU) +#define PWM_DTCNT0_DTCNT0_SHIFT (0U) +#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK) +/*! @} */ + +/* The count of PWM_DTCNT0 */ +#define PWM_DTCNT0_COUNT (4U) + +/*! @name DTCNT1 - Deadtime Count Register 1 */ +/*! @{ */ +#define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU) +#define PWM_DTCNT1_DTCNT1_SHIFT (0U) +#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK) +/*! @} */ + +/* The count of PWM_DTCNT1 */ +#define PWM_DTCNT1_COUNT (4U) + +/*! @name CAPTCTRLA - Capture Control A Register */ +/*! @{ */ +#define PWM_CAPTCTRLA_ARMA_MASK (0x1U) +#define PWM_CAPTCTRLA_ARMA_SHIFT (0U) +/*! ARMA - Arm A + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + */ +#define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK) +#define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U) +#define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U) +/*! ONESHOTA - One Shot Mode A + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed + * first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 + * is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. + * The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue + * indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first + * after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is + * armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No + * further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is + * enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + */ +#define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK) +#define PWM_CAPTCTRLA_EDGA0_MASK (0xCU) +#define PWM_CAPTCTRLA_EDGA0_SHIFT (2U) +/*! EDGA0 - Edge A 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK) +#define PWM_CAPTCTRLA_EDGA1_MASK (0x30U) +#define PWM_CAPTCTRLA_EDGA1_SHIFT (4U) +/*! EDGA1 - Edge A 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK) +#define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U) +#define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U) +/*! INP_SELA - Input Select A + * 0b0..Raw PWM_A input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal + * edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and + * CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the + * CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. + */ +#define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK) +#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U) +#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U) +/*! EDGCNTA_EN - Edge Counter A Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK) +#define PWM_CAPTCTRLA_CFAWM_MASK (0x300U) +#define PWM_CAPTCTRLA_CFAWM_SHIFT (8U) +#define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK) +#define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U) +#define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK) +#define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U) +#define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLA */ +#define PWM_CAPTCTRLA_COUNT (4U) + +/*! @name CAPTCOMPA - Capture Compare A Register */ +/*! @{ */ +#define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU) +#define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U) +#define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK) +#define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U) +#define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U) +#define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPA */ +#define PWM_CAPTCOMPA_COUNT (4U) + +/*! @name CAPTCTRLB - Capture Control B Register */ +/*! @{ */ +#define PWM_CAPTCTRLB_ARMB_MASK (0x1U) +#define PWM_CAPTCTRLB_ARMB_SHIFT (0U) +/*! ARMB - Arm B + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + */ +#define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK) +#define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U) +#define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U) +/*! ONESHOTB - One Shot Mode B + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed + * first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 + * is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. + * The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue + * indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first + * after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is + * armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No + * further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is + * enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + */ +#define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK) +#define PWM_CAPTCTRLB_EDGB0_MASK (0xCU) +#define PWM_CAPTCTRLB_EDGB0_SHIFT (2U) +/*! EDGB0 - Edge B 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK) +#define PWM_CAPTCTRLB_EDGB1_MASK (0x30U) +#define PWM_CAPTCTRLB_EDGB1_SHIFT (4U) +/*! EDGB1 - Edge B 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK) +#define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U) +#define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U) +/*! INP_SELB - Input Select B + * 0b0..Raw PWM_B input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal + * edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and + * CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the + * CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. + */ +#define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK) +#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U) +#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U) +/*! EDGCNTB_EN - Edge Counter B Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK) +#define PWM_CAPTCTRLB_CFBWM_MASK (0x300U) +#define PWM_CAPTCTRLB_CFBWM_SHIFT (8U) +#define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK) +#define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U) +#define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK) +#define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U) +#define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLB */ +#define PWM_CAPTCTRLB_COUNT (4U) + +/*! @name CAPTCOMPB - Capture Compare B Register */ +/*! @{ */ +#define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU) +#define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U) +#define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK) +#define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U) +#define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U) +#define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPB */ +#define PWM_CAPTCOMPB_COUNT (4U) + +/*! @name CAPTCTRLX - Capture Control X Register */ +/*! @{ */ +#define PWM_CAPTCTRLX_ARMX_MASK (0x1U) +#define PWM_CAPTCTRLX_ARMX_SHIFT (0U) +/*! ARMX - Arm X + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + */ +#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) +#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) +#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) +/*! ONESHOTX - One Shot Mode Aux + * 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed + * first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is + * armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The + * process continues indefinitely.If only one of the capture circuits is enabled, then captures continue + * indefinitely on the enabled capture circuit. + * 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first + * after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is + * armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further + * captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, + * then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + */ +#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) +#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) +#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) +/*! EDGX0 - Edge X 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK) +#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U) +#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U) +/*! EDGX1 - Edge X 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK) +#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U) +#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) +/*! INP_SELX - Input Select X + * 0b0..Raw PWM_X input signal selected as source. + * 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal + * edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and + * CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the + * CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. + */ +#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) +#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) +#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U) +/*! EDGCNTX_EN - Edge Counter X Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK) +#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U) +#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U) +#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK) +#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U) +#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK) +#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) +#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLX */ +#define PWM_CAPTCTRLX_COUNT (4U) + +/*! @name CAPTCOMPX - Capture Compare X Register */ +/*! @{ */ +#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) +#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) +#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) +#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) +#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) +#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPX */ +#define PWM_CAPTCOMPX_COUNT (4U) + +/*! @name CVAL0 - Capture Value 0 Register */ +/*! @{ */ +#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) +#define PWM_CVAL0_CAPTVAL0_SHIFT (0U) +#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK) +/*! @} */ + +/* The count of PWM_CVAL0 */ +#define PWM_CVAL0_COUNT (4U) + +/*! @name CVAL0CYC - Capture Value 0 Cycle Register */ +/*! @{ */ +#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) +#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) +#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL0CYC */ +#define PWM_CVAL0CYC_COUNT (4U) + +/*! @name CVAL1 - Capture Value 1 Register */ +/*! @{ */ +#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) +#define PWM_CVAL1_CAPTVAL1_SHIFT (0U) +#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK) +/*! @} */ + +/* The count of PWM_CVAL1 */ +#define PWM_CVAL1_COUNT (4U) + +/*! @name CVAL1CYC - Capture Value 1 Cycle Register */ +/*! @{ */ +#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) +#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) +#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL1CYC */ +#define PWM_CVAL1CYC_COUNT (4U) + +/*! @name CVAL2 - Capture Value 2 Register */ +/*! @{ */ +#define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU) +#define PWM_CVAL2_CAPTVAL2_SHIFT (0U) +#define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK) +/*! @} */ + +/* The count of PWM_CVAL2 */ +#define PWM_CVAL2_COUNT (4U) + +/*! @name CVAL2CYC - Capture Value 2 Cycle Register */ +/*! @{ */ +#define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU) +#define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U) +#define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL2CYC */ +#define PWM_CVAL2CYC_COUNT (4U) + +/*! @name CVAL3 - Capture Value 3 Register */ +/*! @{ */ +#define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU) +#define PWM_CVAL3_CAPTVAL3_SHIFT (0U) +#define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK) +/*! @} */ + +/* The count of PWM_CVAL3 */ +#define PWM_CVAL3_COUNT (4U) + +/*! @name CVAL3CYC - Capture Value 3 Cycle Register */ +/*! @{ */ +#define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU) +#define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U) +#define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL3CYC */ +#define PWM_CVAL3CYC_COUNT (4U) + +/*! @name CVAL4 - Capture Value 4 Register */ +/*! @{ */ +#define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU) +#define PWM_CVAL4_CAPTVAL4_SHIFT (0U) +#define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK) +/*! @} */ + +/* The count of PWM_CVAL4 */ +#define PWM_CVAL4_COUNT (4U) + +/*! @name CVAL4CYC - Capture Value 4 Cycle Register */ +/*! @{ */ +#define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU) +#define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U) +#define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL4CYC */ +#define PWM_CVAL4CYC_COUNT (4U) + +/*! @name CVAL5 - Capture Value 5 Register */ +/*! @{ */ +#define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU) +#define PWM_CVAL5_CAPTVAL5_SHIFT (0U) +#define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK) +/*! @} */ + +/* The count of PWM_CVAL5 */ +#define PWM_CVAL5_COUNT (4U) + +/*! @name CVAL5CYC - Capture Value 5 Cycle Register */ +/*! @{ */ +#define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU) +#define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U) +#define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL5CYC */ +#define PWM_CVAL5CYC_COUNT (4U) + +/*! @name OUTEN - Output Enable Register */ +/*! @{ */ +#define PWM_OUTEN_PWMX_EN_MASK (0xFU) +#define PWM_OUTEN_PWMX_EN_SHIFT (0U) +/*! PWMX_EN - PWM_X Output Enables + * 0b0000..PWM_X output disabled. + * 0b0001..PWM_X output enabled. + */ +#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) +#define PWM_OUTEN_PWMB_EN_MASK (0xF0U) +#define PWM_OUTEN_PWMB_EN_SHIFT (4U) +/*! PWMB_EN - PWM_B Output Enables + * 0b0000..PWM_B output disabled. + * 0b0001..PWM_B output enabled. + */ +#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) +#define PWM_OUTEN_PWMA_EN_MASK (0xF00U) +#define PWM_OUTEN_PWMA_EN_SHIFT (8U) +/*! PWMA_EN - PWM_A Output Enables + * 0b0000..PWM_A output disabled. + * 0b0001..PWM_A output enabled. + */ +#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) +/*! @} */ + +/*! @name MASK - Mask Register */ +/*! @{ */ +#define PWM_MASK_MASKX_MASK (0xFU) +#define PWM_MASK_MASKX_SHIFT (0U) +/*! MASKX - PWM_X Masks + * 0b0000..PWM_X output normal. + * 0b0001..PWM_X output masked. + */ +#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) +#define PWM_MASK_MASKB_MASK (0xF0U) +#define PWM_MASK_MASKB_SHIFT (4U) +/*! MASKB - PWM_B Masks + * 0b0000..PWM_B output normal. + * 0b0001..PWM_B output masked. + */ +#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) +#define PWM_MASK_MASKA_MASK (0xF00U) +#define PWM_MASK_MASKA_SHIFT (8U) +/*! MASKA - PWM_A Masks + * 0b0000..PWM_A output normal. + * 0b0001..PWM_A output masked. + */ +#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) +#define PWM_MASK_UPDATE_MASK_MASK (0xF000U) +#define PWM_MASK_UPDATE_MASK_SHIFT (12U) +/*! UPDATE_MASK - Update Mask Bits Immediately + * 0b0000..Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule. + * 0b0001..Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit. + */ +#define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) +/*! @} */ + +/*! @name SWCOUT - Software Controlled Output Register */ +/*! @{ */ +#define PWM_SWCOUT_SM0OUT45_MASK (0x1U) +#define PWM_SWCOUT_SM0OUT45_SHIFT (0U) +/*! SM0OUT45 - Submodule 0 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. + */ +#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) +#define PWM_SWCOUT_SM0OUT23_MASK (0x2U) +#define PWM_SWCOUT_SM0OUT23_SHIFT (1U) +/*! SM0OUT23 - Submodule 0 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. + */ +#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK) +#define PWM_SWCOUT_SM1OUT45_MASK (0x4U) +#define PWM_SWCOUT_SM1OUT45_SHIFT (2U) +/*! SM1OUT45 - Submodule 1 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. + */ +#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK) +#define PWM_SWCOUT_SM1OUT23_MASK (0x8U) +#define PWM_SWCOUT_SM1OUT23_SHIFT (3U) +/*! SM1OUT23 - Submodule 1 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. + */ +#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK) +#define PWM_SWCOUT_SM2OUT45_MASK (0x10U) +#define PWM_SWCOUT_SM2OUT45_SHIFT (4U) +/*! SM2OUT45 - Submodule 2 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. + */ +#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK) +#define PWM_SWCOUT_SM2OUT23_MASK (0x20U) +#define PWM_SWCOUT_SM2OUT23_SHIFT (5U) +/*! SM2OUT23 - Submodule 2 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. + */ +#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK) +#define PWM_SWCOUT_SM3OUT45_MASK (0x40U) +#define PWM_SWCOUT_SM3OUT45_SHIFT (6U) +/*! SM3OUT45 - Submodule 3 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. + */ +#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK) +#define PWM_SWCOUT_SM3OUT23_MASK (0x80U) +#define PWM_SWCOUT_SM3OUT23_SHIFT (7U) +/*! SM3OUT23 - Submodule 3 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. + */ +#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK) +/*! @} */ + +/*! @name DTSRCSEL - PWM Source Select Register */ +/*! @{ */ +#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) +#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) +/*! SM0SEL45 - Submodule 0 PWM45 Control Select + * 0b00..Generated SM0PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM0PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT45] is used by the deadtime logic. + * 0b11..PWM0_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) +#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU) +#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U) +/*! SM0SEL23 - Submodule 0 PWM23 Control Select + * 0b00..Generated SM0PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM0PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT23] is used by the deadtime logic. + * 0b11..PWM0_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK) +#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U) +#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U) +/*! SM1SEL45 - Submodule 1 PWM45 Control Select + * 0b00..Generated SM1PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM1PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT45] is used by the deadtime logic. + * 0b11..PWM1_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) +#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U) +#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U) +/*! SM1SEL23 - Submodule 1 PWM23 Control Select + * 0b00..Generated SM1PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM1PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT23] is used by the deadtime logic. + * 0b11..PWM1_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK) +#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U) +#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U) +/*! SM2SEL45 - Submodule 2 PWM45 Control Select + * 0b00..Generated SM2PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM2PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT45] is used by the deadtime logic. + * 0b11..PWM2_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) +#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U) +#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U) +/*! SM2SEL23 - Submodule 2 PWM23 Control Select + * 0b00..Generated SM2PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM2PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT23] is used by the deadtime logic. + * 0b11..PWM2_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK) +#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U) +#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U) +/*! SM3SEL45 - Submodule 3 PWM45 Control Select + * 0b00..Generated SM3PWM45 signal is used by the deadtime logic. + * 0b01..Inverted generated SM3PWM45 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT45] is used by the deadtime logic. + * 0b11..PWM3_EXTB signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) +#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U) +#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U) +/*! SM3SEL23 - Submodule 3 PWM23 Control Select + * 0b00..Generated SM3PWM23 signal is used by the deadtime logic. + * 0b01..Inverted generated SM3PWM23 signal is used by the deadtime logic. + * 0b10..SWCOUT[SM3OUT23] is used by the deadtime logic. + * 0b11..PWM3_EXTA signal is used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK) +/*! @} */ + +/*! @name MCTRL - Master Control Register */ +/*! @{ */ +#define PWM_MCTRL_LDOK_MASK (0xFU) +#define PWM_MCTRL_LDOK_SHIFT (0U) +/*! LDOK - Load Okay + * 0b0000..Do not load new values. + * 0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule. + */ +#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) +#define PWM_MCTRL_CLDOK_MASK (0xF0U) +#define PWM_MCTRL_CLDOK_SHIFT (4U) +#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK) +#define PWM_MCTRL_RUN_MASK (0xF00U) +#define PWM_MCTRL_RUN_SHIFT (8U) +/*! RUN - Run + * 0b0000..PWM generator is disabled in the corresponding submodule. + * 0b0001..PWM generator is enabled in the corresponding submodule. + */ +#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK) +#define PWM_MCTRL_IPOL_MASK (0xF000U) +#define PWM_MCTRL_IPOL_SHIFT (12U) +/*! IPOL - Current Polarity + * 0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule. + * 0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule. + */ +#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK) +/*! @} */ + +/*! @name MCTRL2 - Master Control 2 Register */ +/*! @{ */ +#define PWM_MCTRL2_MONPLL_MASK (0x3U) +#define PWM_MCTRL2_MONPLL_SHIFT (0U) +/*! MONPLL - Monitor PLL State + * 0b00..Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. + * 0b01..Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. + * 0b10..Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock + * will be controlled by software. These bits are write protected until the next reset. + * 0b11..Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL + * encounters problems. These bits are write protected until the next reset. + */ +#define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK) +/*! @} */ + +/*! @name FCTRL - Fault Control Register */ +/*! @{ */ +#define PWM_FCTRL_FIE_MASK (0xFU) +#define PWM_FCTRL_FIE_SHIFT (0U) +/*! FIE - Fault Interrupt Enables + * 0b0000..FAULTx CPU interrupt requests disabled. + * 0b0001..FAULTx CPU interrupt requests enabled. + */ +#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) +#define PWM_FCTRL_FSAFE_MASK (0xF0U) +#define PWM_FCTRL_FSAFE_SHIFT (4U) +/*! FSAFE - Fault Safety Mode + * 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the + * start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of + * FSTS[FFPINx]. The PWM outputs disabled by this fault input will not be re-enabled until the actual + * FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as + * programmed in DISMAPn). + * 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and + * FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL]. + */ +#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK) +#define PWM_FCTRL_FAUTO_MASK (0xF00U) +#define PWM_FCTRL_FAUTO_SHIFT (8U) +/*! FAUTO - Automatic Fault Clearing + * 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear + * at the start of a half cycle or full cycle depending the state of FSTS[FFULL]. This is further + * controlled by FCTRL[FSAFE]. + * 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at + * the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the + * state of FSTS[FFLAGx]. + */ +#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK) +#define PWM_FCTRL_FLVL_MASK (0xF000U) +#define PWM_FCTRL_FLVL_SHIFT (12U) +/*! FLVL - Fault Level + * 0b0000..A logic 0 on the fault input indicates a fault condition. + * 0b0001..A logic 1 on the fault input indicates a fault condition. + */ +#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK) +/*! @} */ + +/*! @name FSTS - Fault Status Register */ +/*! @{ */ +#define PWM_FSTS_FFLAG_MASK (0xFU) +#define PWM_FSTS_FFLAG_SHIFT (0U) +/*! FFLAG - Fault Flags + * 0b0000..No fault on the FAULTx pin. + * 0b0001..Fault on the FAULTx pin. + */ +#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) +#define PWM_FSTS_FFULL_MASK (0xF0U) +#define PWM_FSTS_FFULL_SHIFT (4U) +/*! FFULL - Full Cycle + * 0b0000..PWM outputs are not re-enabled at the start of a full cycle + * 0b0001..PWM outputs are re-enabled at the start of a full cycle + */ +#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK) +#define PWM_FSTS_FFPIN_MASK (0xF00U) +#define PWM_FSTS_FFPIN_SHIFT (8U) +#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK) +#define PWM_FSTS_FHALF_MASK (0xF000U) +#define PWM_FSTS_FHALF_SHIFT (12U) +/*! FHALF - Half Cycle Fault Recovery + * 0b0000..PWM outputs are not re-enabled at the start of a half cycle. + * 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). + */ +#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK) +/*! @} */ + +/*! @name FFILT - Fault Filter Register */ +/*! @{ */ +#define PWM_FFILT_FILT_PER_MASK (0xFFU) +#define PWM_FFILT_FILT_PER_SHIFT (0U) +#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) +#define PWM_FFILT_FILT_CNT_MASK (0x700U) +#define PWM_FFILT_FILT_CNT_SHIFT (8U) +#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK) +#define PWM_FFILT_GSTR_MASK (0x8000U) +#define PWM_FFILT_GSTR_SHIFT (15U) +/*! GSTR - Fault Glitch Stretch Enable + * 0b0..Fault input glitch stretching is disabled. + * 0b1..Input fault signals will be stretched to at least 2 IPBus clock cycles. + */ +#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK) +/*! @} */ + +/*! @name FTST - Fault Test Register */ +/*! @{ */ +#define PWM_FTST_FTEST_MASK (0x1U) +#define PWM_FTST_FTEST_SHIFT (0U) +/*! FTEST - Fault Test + * 0b0..No fault + * 0b1..Cause a simulated fault + */ +#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK) +/*! @} */ + +/*! @name FCTRL2 - Fault Control 2 Register */ +/*! @{ */ +#define PWM_FCTRL2_NOCOMB_MASK (0xFU) +#define PWM_FCTRL2_NOCOMB_SHIFT (0U) +/*! NOCOMB - No Combinational Path From Fault Input To PWM Output + * 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined + * with the filtered and latched fault signals to disable the PWM outputs. + * 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered + * and latched fault signals are used to disable the PWM outputs. + */ +#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PWM_Register_Masks */ + + +/* PWM - Peripheral instance base addresses */ +/** Peripheral PWM1 base address */ +#define PWM1_BASE (0x403DC000u) +/** Peripheral PWM1 base pointer */ +#define PWM1 ((PWM_Type *)PWM1_BASE) +/** Peripheral PWM2 base address */ +#define PWM2_BASE (0x403E0000u) +/** Peripheral PWM2 base pointer */ +#define PWM2 ((PWM_Type *)PWM2_BASE) +/** Peripheral PWM3 base address */ +#define PWM3_BASE (0x403E4000u) +/** Peripheral PWM3 base pointer */ +#define PWM3 ((PWM_Type *)PWM3_BASE) +/** Peripheral PWM4 base address */ +#define PWM4_BASE (0x403E8000u) +/** Peripheral PWM4 base pointer */ +#define PWM4 ((PWM_Type *)PWM4_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } } +#define PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } } +#define PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } } +#define PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn } + +/*! + * @} + */ /* end of group PWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ROMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Peripheral_Access_Layer ROMC Peripheral Access Layer + * @{ + */ + +/** ROMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[212]; + __IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */ + __IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */ + uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */ + __IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */ + __IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_1[200]; + __IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */ +} ROMC_Type; + +/* ---------------------------------------------------------------------------- + -- ROMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Register_Masks ROMC Register Masks + * @{ + */ + +/*! @name ROMPATCHD - ROMC Data Registers */ +/*! @{ */ +#define ROMC_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) +#define ROMC_ROMPATCHD_DATAX_SHIFT (0U) +#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHD_DATAX_SHIFT)) & ROMC_ROMPATCHD_DATAX_MASK) +/*! @} */ + +/* The count of ROMC_ROMPATCHD */ +#define ROMC_ROMPATCHD_COUNT (8U) + +/*! @name ROMPATCHCNTL - ROMC Control Register */ +/*! @{ */ +#define ROMC_ROMPATCHCNTL_DATAFIX_MASK (0xFFU) +#define ROMC_ROMPATCHCNTL_DATAFIX_SHIFT (0U) +/*! DATAFIX + * 0b00000000..Address comparator triggers a opcode patch + * 0b00000001..Address comparator triggers a data fix + */ +#define ROMC_ROMPATCHCNTL_DATAFIX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DATAFIX_SHIFT)) & ROMC_ROMPATCHCNTL_DATAFIX_MASK) +#define ROMC_ROMPATCHCNTL_DIS_MASK (0x20000000U) +#define ROMC_ROMPATCHCNTL_DIS_SHIFT (29U) +/*! DIS + * 0b0..Does not affect any ROMC functions (default) + * 0b1..Disable all ROMC functions: data fixing, and opcode patching + */ +#define ROMC_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHCNTL_DIS_SHIFT)) & ROMC_ROMPATCHCNTL_DIS_MASK) +/*! @} */ + +/*! @name ROMPATCHENL - ROMC Enable Register Low */ +/*! @{ */ +#define ROMC_ROMPATCHENL_ENABLE_MASK (0xFFFFU) +#define ROMC_ROMPATCHENL_ENABLE_SHIFT (0U) +/*! ENABLE + * 0b0000000000000000..Address comparator disabled + * 0b0000000000000001..Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address + */ +#define ROMC_ROMPATCHENL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHENL_ENABLE_SHIFT)) & ROMC_ROMPATCHENL_ENABLE_MASK) +/*! @} */ + +/*! @name ROMPATCHA - ROMC Address Registers */ +/*! @{ */ +#define ROMC_ROMPATCHA_THUMBX_MASK (0x1U) +#define ROMC_ROMPATCHA_THUMBX_SHIFT (0U) +/*! THUMBX + * 0b0..Arm patch + * 0b1..THUMB patch (ignore if data fix) + */ +#define ROMC_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_THUMBX_SHIFT)) & ROMC_ROMPATCHA_THUMBX_MASK) +#define ROMC_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) +#define ROMC_ROMPATCHA_ADDRX_SHIFT (1U) +#define ROMC_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHA_ADDRX_SHIFT)) & ROMC_ROMPATCHA_ADDRX_MASK) +/*! @} */ + +/* The count of ROMC_ROMPATCHA */ +#define ROMC_ROMPATCHA_COUNT (16U) + +/*! @name ROMPATCHSR - ROMC Status Register */ +/*! @{ */ +#define ROMC_ROMPATCHSR_SOURCE_MASK (0x3FU) +#define ROMC_ROMPATCHSR_SOURCE_SHIFT (0U) +/*! SOURCE + * 0b000000..Address Comparator 0 matched + * 0b000001..Address Comparator 1 matched + * 0b001111..Address Comparator 15 matched + */ +#define ROMC_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SOURCE_SHIFT)) & ROMC_ROMPATCHSR_SOURCE_MASK) +#define ROMC_ROMPATCHSR_SW_MASK (0x20000U) +#define ROMC_ROMPATCHSR_SW_SHIFT (17U) +/*! SW + * 0b0..no event or comparator collisions + * 0b1..a collision has occurred + */ +#define ROMC_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROMC_ROMPATCHSR_SW_SHIFT)) & ROMC_ROMPATCHSR_SW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ROMC_Register_Masks */ + + +/* ROMC - Peripheral instance base addresses */ +/** Peripheral ROMC base address */ +#define ROMC_BASE (0x40180000u) +/** Peripheral ROMC base pointer */ +#define ROMC ((ROMC_Type *)ROMC_BASE) +/** Array initializer of ROMC peripheral base addresses */ +#define ROMC_BASE_ADDRS { ROMC_BASE } +/** Array initializer of ROMC peripheral base pointers */ +#define ROMC_BASE_PTRS { ROMC } + +/*! + * @} + */ /* end of group ROMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTWDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTWDOG_Peripheral_Access_Layer RTWDOG Peripheral Access Layer + * @{ + */ + +/** RTWDOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t CS; /**< Watchdog Control and Status Register, offset: 0x0 */ + __IO uint32_t CNT; /**< Watchdog Counter Register, offset: 0x4 */ + __IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */ + __IO uint32_t WIN; /**< Watchdog Window Register, offset: 0xC */ +} RTWDOG_Type; + +/* ---------------------------------------------------------------------------- + -- RTWDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTWDOG_Register_Masks RTWDOG Register Masks + * @{ + */ + +/*! @name CS - Watchdog Control and Status Register */ +/*! @{ */ +#define RTWDOG_CS_STOP_MASK (0x1U) +#define RTWDOG_CS_STOP_SHIFT (0U) +/*! STOP - Stop Enable + * 0b0..Watchdog disabled in chip stop mode. + * 0b1..Watchdog enabled in chip stop mode. + */ +#define RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK) +#define RTWDOG_CS_WAIT_MASK (0x2U) +#define RTWDOG_CS_WAIT_SHIFT (1U) +/*! WAIT - Wait Enable + * 0b0..Watchdog disabled in chip wait mode. + * 0b1..Watchdog enabled in chip wait mode. + */ +#define RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK) +#define RTWDOG_CS_DBG_MASK (0x4U) +#define RTWDOG_CS_DBG_SHIFT (2U) +/*! DBG - Debug Enable + * 0b0..Watchdog disabled in chip debug mode. + * 0b1..Watchdog enabled in chip debug mode. + */ +#define RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK) +#define RTWDOG_CS_TST_MASK (0x18U) +#define RTWDOG_CS_TST_SHIFT (3U) +/*! TST - Watchdog Test + * 0b00..Watchdog test mode disabled. + * 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should + * use this setting to indicate that the watchdog is functioning normally in user mode. + * 0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. + * 0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. + */ +#define RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK) +#define RTWDOG_CS_UPDATE_MASK (0x20U) +#define RTWDOG_CS_UPDATE_SHIFT (5U) +/*! UPDATE - Allow updates + * 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. + * 0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. + */ +#define RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK) +#define RTWDOG_CS_INT_MASK (0x40U) +#define RTWDOG_CS_INT_SHIFT (6U) +/*! INT - Watchdog Interrupt + * 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed. + * 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. + */ +#define RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK) +#define RTWDOG_CS_EN_MASK (0x80U) +#define RTWDOG_CS_EN_SHIFT (7U) +/*! EN - Watchdog Enable + * 0b0..Watchdog disabled. + * 0b1..Watchdog enabled. + */ +#define RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK) +#define RTWDOG_CS_CLK_MASK (0x300U) +#define RTWDOG_CS_CLK_SHIFT (8U) +/*! CLK - Watchdog Clock + * 0b00..Bus clock + * 0b01..LPO clock + * 0b10..INTCLK (internal clock) + * 0b11..ERCLK (external reference clock) + */ +#define RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK) +#define RTWDOG_CS_RCS_MASK (0x400U) +#define RTWDOG_CS_RCS_SHIFT (10U) +/*! RCS - Reconfiguration Success + * 0b0..Reconfiguring WDOG. + * 0b1..Reconfiguration is successful. + */ +#define RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK) +#define RTWDOG_CS_ULK_MASK (0x800U) +#define RTWDOG_CS_ULK_SHIFT (11U) +/*! ULK - Unlock status + * 0b0..WDOG is locked. + * 0b1..WDOG is unlocked. + */ +#define RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK) +#define RTWDOG_CS_PRES_MASK (0x1000U) +#define RTWDOG_CS_PRES_SHIFT (12U) +/*! PRES - Watchdog prescaler + * 0b0..256 prescaler disabled. + * 0b1..256 prescaler enabled. + */ +#define RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK) +#define RTWDOG_CS_CMD32EN_MASK (0x2000U) +#define RTWDOG_CS_CMD32EN_SHIFT (13U) +/*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words + * 0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. + * 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. + */ +#define RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK) +#define RTWDOG_CS_FLG_MASK (0x4000U) +#define RTWDOG_CS_FLG_SHIFT (14U) +/*! FLG - Watchdog Interrupt Flag + * 0b0..No interrupt occurred. + * 0b1..An interrupt occurred. + */ +#define RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK) +#define RTWDOG_CS_WIN_MASK (0x8000U) +#define RTWDOG_CS_WIN_SHIFT (15U) +/*! WIN - Watchdog Window + * 0b0..Window mode disabled. + * 0b1..Window mode enabled. + */ +#define RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK) +/*! @} */ + +/*! @name CNT - Watchdog Counter Register */ +/*! @{ */ +#define RTWDOG_CNT_CNTLOW_MASK (0xFFU) +#define RTWDOG_CNT_CNTLOW_SHIFT (0U) +#define RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK) +#define RTWDOG_CNT_CNTHIGH_MASK (0xFF00U) +#define RTWDOG_CNT_CNTHIGH_SHIFT (8U) +#define RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK) +/*! @} */ + +/*! @name TOVAL - Watchdog Timeout Value Register */ +/*! @{ */ +#define RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU) +#define RTWDOG_TOVAL_TOVALLOW_SHIFT (0U) +#define RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK) +#define RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) +#define RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U) +#define RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK) +/*! @} */ + +/*! @name WIN - Watchdog Window Register */ +/*! @{ */ +#define RTWDOG_WIN_WINLOW_MASK (0xFFU) +#define RTWDOG_WIN_WINLOW_SHIFT (0U) +#define RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK) +#define RTWDOG_WIN_WINHIGH_MASK (0xFF00U) +#define RTWDOG_WIN_WINHIGH_SHIFT (8U) +#define RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RTWDOG_Register_Masks */ + + +/* RTWDOG - Peripheral instance base addresses */ +/** Peripheral RTWDOG base address */ +#define RTWDOG_BASE (0x400BC000u) +/** Peripheral RTWDOG base pointer */ +#define RTWDOG ((RTWDOG_Type *)RTWDOG_BASE) +/** Array initializer of RTWDOG peripheral base addresses */ +#define RTWDOG_BASE_ADDRS { RTWDOG_BASE } +/** Array initializer of RTWDOG peripheral base pointers */ +#define RTWDOG_BASE_PTRS { RTWDOG } +/** Interrupt vectors for the RTWDOG peripheral type */ +#define RTWDOG_IRQS { RTWDOG_IRQn } +/* Extra definition */ +#define RTWDOG_UPDATE_KEY (0xD928C520U) +#define RTWDOG_REFRESH_KEY (0xB480A602U) + + +/*! + * @} + */ /* end of group RTWDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SEMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMC_Peripheral_Access_Layer SEMC Peripheral Access Layer + * @{ + */ + +/** SEMC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Control Register, offset: 0x0 */ + __IO uint32_t IOCR; /**< IO Mux Control Register, offset: 0x4 */ + __IO uint32_t BMCR0; /**< Master Bus (AXI) Control Register 0, offset: 0x8 */ + __IO uint32_t BMCR1; /**< Master Bus (AXI) Control Register 1, offset: 0xC */ + __IO uint32_t BR[9]; /**< Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device), array offset: 0x10, array step: 0x4 */ + __IO uint32_t DLLCR; /**< DLL Control Register, offset: 0x34 */ + __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x38 */ + __IO uint32_t INTR; /**< Interrupt Enable Register, offset: 0x3C */ + __IO uint32_t SDRAMCR0; /**< SDRAM control register 0, offset: 0x40 */ + __IO uint32_t SDRAMCR1; /**< SDRAM control register 1, offset: 0x44 */ + __IO uint32_t SDRAMCR2; /**< SDRAM control register 2, offset: 0x48 */ + __IO uint32_t SDRAMCR3; /**< SDRAM control register 3, offset: 0x4C */ + __IO uint32_t NANDCR0; /**< NAND control register 0, offset: 0x50 */ + __IO uint32_t NANDCR1; /**< NAND control register 1, offset: 0x54 */ + __IO uint32_t NANDCR2; /**< NAND control register 2, offset: 0x58 */ + __IO uint32_t NANDCR3; /**< NAND control register 3, offset: 0x5C */ + __IO uint32_t NORCR0; /**< NOR control register 0, offset: 0x60 */ + __IO uint32_t NORCR1; /**< NOR control register 1, offset: 0x64 */ + __IO uint32_t NORCR2; /**< NOR control register 2, offset: 0x68 */ + __IO uint32_t NORCR3; /**< NOR control register 3, offset: 0x6C */ + __IO uint32_t SRAMCR0; /**< SRAM control register 0, offset: 0x70 */ + __IO uint32_t SRAMCR1; /**< SRAM control register 1, offset: 0x74 */ + __IO uint32_t SRAMCR2; /**< SRAM control register 2, offset: 0x78 */ + uint32_t SRAMCR3; /**< SRAM control register 3, offset: 0x7C */ + __IO uint32_t DBICR0; /**< DBI-B control register 0, offset: 0x80 */ + __IO uint32_t DBICR1; /**< DBI-B control register 1, offset: 0x84 */ + uint8_t RESERVED_0[8]; + __IO uint32_t IPCR0; /**< IP Command control register 0, offset: 0x90 */ + __IO uint32_t IPCR1; /**< IP Command control register 1, offset: 0x94 */ + __IO uint32_t IPCR2; /**< IP Command control register 2, offset: 0x98 */ + __IO uint32_t IPCMD; /**< IP Command register, offset: 0x9C */ + __IO uint32_t IPTXDAT; /**< TX DATA register (for IP Command), offset: 0xA0 */ + uint8_t RESERVED_1[12]; + __I uint32_t IPRXDAT; /**< RX DATA register (for IP Command), offset: 0xB0 */ + uint8_t RESERVED_2[12]; + __I uint32_t STS0; /**< Status register 0, offset: 0xC0 */ + uint32_t STS1; /**< Status register 1, offset: 0xC4 */ + __I uint32_t STS2; /**< Status register 2, offset: 0xC8 */ + uint32_t STS3; /**< Status register 3, offset: 0xCC */ + uint32_t STS4; /**< Status register 4, offset: 0xD0 */ + uint32_t STS5; /**< Status register 5, offset: 0xD4 */ + uint32_t STS6; /**< Status register 6, offset: 0xD8 */ + uint32_t STS7; /**< Status register 7, offset: 0xDC */ + uint32_t STS8; /**< Status register 8, offset: 0xE0 */ + uint32_t STS9; /**< Status register 9, offset: 0xE4 */ + uint32_t STS10; /**< Status register 10, offset: 0xE8 */ + uint32_t STS11; /**< Status register 11, offset: 0xEC */ + __I uint32_t STS12; /**< Status register 12, offset: 0xF0 */ + __I uint32_t STS13; /**< Status register 13, offset: 0xF4 */ + uint32_t STS14; /**< Status register 14, offset: 0xF8 */ + uint32_t STS15; /**< Status register 15, offset: 0xFC */ +} SEMC_Type; + +/* ---------------------------------------------------------------------------- + -- SEMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMC_Register_Masks SEMC Register Masks + * @{ + */ + +/*! @name MCR - Module Control Register */ +/*! @{ */ +#define SEMC_MCR_SWRST_MASK (0x1U) +#define SEMC_MCR_SWRST_SHIFT (0U) +#define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK) +#define SEMC_MCR_MDIS_MASK (0x2U) +#define SEMC_MCR_MDIS_SHIFT (1U) +/*! MDIS - Module Disable + * 0b0..Module enabled + * 0b1..Module disabled. + */ +#define SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK) +#define SEMC_MCR_DQSMD_MASK (0x4U) +#define SEMC_MCR_DQSMD_SHIFT (2U) +/*! DQSMD - DQS (read strobe) mode + * 0b0..Dummy read strobe loopbacked internally + * 0b1..Dummy read strobe loopbacked from DQS pad or DLL delay chain. Details information at descriptions of DQSSEL bit. + */ +#define SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK) +#define SEMC_MCR_WPOL0_MASK (0x40U) +#define SEMC_MCR_WPOL0_SHIFT (6U) +/*! WPOL0 - WAIT/RDY# polarity for NOR/PSRAM + * 0b0..Low active + * 0b1..High active + */ +#define SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK) +#define SEMC_MCR_WPOL1_MASK (0x80U) +#define SEMC_MCR_WPOL1_SHIFT (7U) +/*! WPOL1 - WAIT/RDY# polarity for NAND + * 0b0..Low active + * 0b1..High active + */ +#define SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK) +#define SEMC_MCR_DQSSEL_MASK (0x400U) +#define SEMC_MCR_DQSSEL_SHIFT (10U) +/*! DQSSEL - Select DQS source when DQSMD and DLLSEL both set. + * 0b0..SDRAM/NOR/SRAM read clock source is from DQS pad in synchronous mode. + * 0b1..SDRAM/NOR/SRAM read clock source is from DLL delay chain in synchronous mode. + */ +#define SEMC_MCR_DQSSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSSEL_SHIFT)) & SEMC_MCR_DQSSEL_MASK) +#define SEMC_MCR_DLLSEL_MASK (0x800U) +#define SEMC_MCR_DLLSEL_SHIFT (11U) +/*! DLLSEL - Select DLL delay chain clock input. + * 0b0..DLL delay chain clock input is from NAND device's DQS pad. For NAND synchronous mode only. + * 0b1..DLL delay chain clock input is from internal clock. For SDRAM, NOR and SRAM synchronous mode only. + */ +#define SEMC_MCR_DLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DLLSEL_SHIFT)) & SEMC_MCR_DLLSEL_MASK) +#define SEMC_MCR_CTO_MASK (0xFF0000U) +#define SEMC_MCR_CTO_SHIFT (16U) +#define SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK) +#define SEMC_MCR_BTO_MASK (0x1F000000U) +#define SEMC_MCR_BTO_SHIFT (24U) +/*! BTO - Bus timeout cycles + * 0b00000..255*1 + * 0b00001-0b11110..255*2 - 255*2^30 + * 0b11111..255*2^31 + */ +#define SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK) +/*! @} */ + +/*! @name IOCR - IO Mux Control Register */ +/*! @{ */ +#define SEMC_IOCR_MUX_A8_MASK (0x7U) +#define SEMC_IOCR_MUX_A8_SHIFT (0U) +/*! MUX_A8 - SEMC_A8 output selection + * 0b000..SDRAM Address bit (A8) + * 0b001..NAND CE# + * 0b010..NOR CE# + * 0b011..PSRAM CE# + * 0b100..DBI CSX + * 0b101..SDRAM Address bit (A8) + * 0b110..SDRAM Address bit (A8) + * 0b111..SDRAM Address bit (A8) + */ +#define SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK) +#define SEMC_IOCR_MUX_CSX0_MASK (0x38U) +#define SEMC_IOCR_MUX_CSX0_SHIFT (3U) +/*! MUX_CSX0 - SEMC_CSX0 output selection + * 0b000..NOR/PSRAM Address bit 24 (A24) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ +#define SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK) +#define SEMC_IOCR_MUX_CSX1_MASK (0x1C0U) +#define SEMC_IOCR_MUX_CSX1_SHIFT (6U) +/*! MUX_CSX1 - SEMC_CSX1 output selection + * 0b000..NOR/PSRAM Address bit 25 (A25) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ +#define SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK) +#define SEMC_IOCR_MUX_CSX2_MASK (0xE00U) +#define SEMC_IOCR_MUX_CSX2_SHIFT (9U) +/*! MUX_CSX2 - SEMC_CSX2 output selection + * 0b000..NOR/PSRAM Address bit 26 (A26) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ +#define SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK) +#define SEMC_IOCR_MUX_CSX3_MASK (0x7000U) +#define SEMC_IOCR_MUX_CSX3_SHIFT (12U) +/*! MUX_CSX3 - SEMC_CSX3 output selection + * 0b000..NOR/PSRAM Address bit 27 (A27) + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NAND CE# + * 0b101..NOR CE# + * 0b110..PSRAM CE# + * 0b111..DBI CSX + */ +#define SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK) +#define SEMC_IOCR_MUX_RDY_MASK (0x38000U) +#define SEMC_IOCR_MUX_RDY_SHIFT (15U) +/*! MUX_RDY - SEMC_RDY function selection + * 0b000..NAND Ready/Wait# input + * 0b001..SDRAM CS1 + * 0b010..SDRAM CS2 + * 0b011..SDRAM CS3 + * 0b100..NOR CE# + * 0b101..PSRAM CE# + * 0b110..DBI CSX + * 0b111..NOR/PSRAM Address bit 27 + */ +#define SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK) +#define SEMC_IOCR_MUX_CLKX0_MASK (0x1000000U) +#define SEMC_IOCR_MUX_CLKX0_SHIFT (24U) +/*! MUX_CLKX0 - SEMC_CLKX0 function selection + * 0b0..NOR clock + * 0b1..SRAM clock + */ +#define SEMC_IOCR_MUX_CLKX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX0_SHIFT)) & SEMC_IOCR_MUX_CLKX0_MASK) +#define SEMC_IOCR_MUX_CLKX1_MASK (0x2000000U) +#define SEMC_IOCR_MUX_CLKX1_SHIFT (25U) +/*! MUX_CLKX1 - SEMC_CLKX1 function selection + * 0b0..NOR clock + * 0b1..SRAM clock + */ +#define SEMC_IOCR_MUX_CLKX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX1_SHIFT)) & SEMC_IOCR_MUX_CLKX1_MASK) +/*! @} */ + +/*! @name BMCR0 - Master Bus (AXI) Control Register 0 */ +/*! @{ */ +#define SEMC_BMCR0_WQOS_MASK (0xFU) +#define SEMC_BMCR0_WQOS_SHIFT (0U) +#define SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK) +#define SEMC_BMCR0_WAGE_MASK (0xF0U) +#define SEMC_BMCR0_WAGE_SHIFT (4U) +#define SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK) +#define SEMC_BMCR0_WSH_MASK (0xFF00U) +#define SEMC_BMCR0_WSH_SHIFT (8U) +#define SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK) +#define SEMC_BMCR0_WRWS_MASK (0xFF0000U) +#define SEMC_BMCR0_WRWS_SHIFT (16U) +#define SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK) +/*! @} */ + +/*! @name BMCR1 - Master Bus (AXI) Control Register 1 */ +/*! @{ */ +#define SEMC_BMCR1_WQOS_MASK (0xFU) +#define SEMC_BMCR1_WQOS_SHIFT (0U) +#define SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK) +#define SEMC_BMCR1_WAGE_MASK (0xF0U) +#define SEMC_BMCR1_WAGE_SHIFT (4U) +#define SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK) +#define SEMC_BMCR1_WPH_MASK (0xFF00U) +#define SEMC_BMCR1_WPH_SHIFT (8U) +#define SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK) +#define SEMC_BMCR1_WRWS_MASK (0xFF0000U) +#define SEMC_BMCR1_WRWS_SHIFT (16U) +#define SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK) +#define SEMC_BMCR1_WBR_MASK (0xFF000000U) +#define SEMC_BMCR1_WBR_SHIFT (24U) +#define SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK) +/*! @} */ + +/*! @name BR - Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device) */ +/*! @{ */ +#define SEMC_BR_VLD_MASK (0x1U) +#define SEMC_BR_VLD_SHIFT (0U) +#define SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK) +#define SEMC_BR_MS_MASK (0x3EU) +#define SEMC_BR_MS_SHIFT (1U) +/*! MS - Memory size + * 0b00000..4KB + * 0b00001..8KB + * 0b00010..16KB + * 0b00011..32KB + * 0b00100..64KB + * 0b00101..128KB + * 0b00110..256KB + * 0b00111..512KB + * 0b01000..1MB + * 0b01001..2MB + * 0b01010..4MB + * 0b01011..8MB + * 0b01100..16MB + * 0b01101..32MB + * 0b01110..64MB + * 0b01111..128MB + * 0b10000..256MB + * 0b10001..512MB + * 0b10010..1GB + * 0b10011..2GB + * 0b10100..4GB + * 0b10101..4GB + * 0b10110..4GB + * 0b10111..4GB + * 0b11000..4GB + * 0b11001..4GB + * 0b11010..4GB + * 0b11011..4GB + * 0b11100..4GB + * 0b11101..4GB + * 0b11110..4GB + * 0b11111..4GB + */ +#define SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK) +#define SEMC_BR_BA_MASK (0xFFFFF000U) +#define SEMC_BR_BA_SHIFT (12U) +#define SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK) +/*! @} */ + +/* The count of SEMC_BR */ +#define SEMC_BR_COUNT (9U) + +/*! @name DLLCR - DLL Control Register */ +/*! @{ */ +#define SEMC_DLLCR_DLLEN_MASK (0x1U) +#define SEMC_DLLCR_DLLEN_SHIFT (0U) +#define SEMC_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLEN_SHIFT)) & SEMC_DLLCR_DLLEN_MASK) +#define SEMC_DLLCR_DLLRESET_MASK (0x2U) +#define SEMC_DLLCR_DLLRESET_SHIFT (1U) +#define SEMC_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLRESET_SHIFT)) & SEMC_DLLCR_DLLRESET_MASK) +#define SEMC_DLLCR_SLVDLYTARGET_MASK (0x78U) +#define SEMC_DLLCR_SLVDLYTARGET_SHIFT (3U) +#define SEMC_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_SLVDLYTARGET_SHIFT)) & SEMC_DLLCR_SLVDLYTARGET_MASK) +#define SEMC_DLLCR_OVRDEN_MASK (0x100U) +#define SEMC_DLLCR_OVRDEN_SHIFT (8U) +#define SEMC_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDEN_SHIFT)) & SEMC_DLLCR_OVRDEN_MASK) +#define SEMC_DLLCR_OVRDVAL_MASK (0x7E00U) +#define SEMC_DLLCR_OVRDVAL_SHIFT (9U) +#define SEMC_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDVAL_SHIFT)) & SEMC_DLLCR_OVRDVAL_MASK) +/*! @} */ + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ +#define SEMC_INTEN_IPCMDDONEEN_MASK (0x1U) +#define SEMC_INTEN_IPCMDDONEEN_SHIFT (0U) +#define SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) +#define SEMC_INTEN_IPCMDERREN_MASK (0x2U) +#define SEMC_INTEN_IPCMDERREN_SHIFT (1U) +#define SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK) +#define SEMC_INTEN_AXICMDERREN_MASK (0x4U) +#define SEMC_INTEN_AXICMDERREN_SHIFT (2U) +#define SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK) +#define SEMC_INTEN_AXIBUSERREN_MASK (0x8U) +#define SEMC_INTEN_AXIBUSERREN_SHIFT (3U) +#define SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) +#define SEMC_INTEN_NDPAGEENDEN_MASK (0x10U) +#define SEMC_INTEN_NDPAGEENDEN_SHIFT (4U) +/*! NDPAGEENDEN - This bit enable/disable the NDPAGEEND interrupt generation. + * 0b0..Disable + * 0b1..Enable + */ +#define SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) +#define SEMC_INTEN_NDNOPENDEN_MASK (0x20U) +#define SEMC_INTEN_NDNOPENDEN_SHIFT (5U) +/*! NDNOPENDEN - This bit enable/disable the NDNOPEND interrupt generation. + * 0b0..Disable + * 0b1..Enable + */ +#define SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) +/*! @} */ + +/*! @name INTR - Interrupt Enable Register */ +/*! @{ */ +#define SEMC_INTR_IPCMDDONE_MASK (0x1U) +#define SEMC_INTR_IPCMDDONE_SHIFT (0U) +#define SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) +#define SEMC_INTR_IPCMDERR_MASK (0x2U) +#define SEMC_INTR_IPCMDERR_SHIFT (1U) +#define SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK) +#define SEMC_INTR_AXICMDERR_MASK (0x4U) +#define SEMC_INTR_AXICMDERR_SHIFT (2U) +#define SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK) +#define SEMC_INTR_AXIBUSERR_MASK (0x8U) +#define SEMC_INTR_AXIBUSERR_SHIFT (3U) +#define SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK) +#define SEMC_INTR_NDPAGEEND_MASK (0x10U) +#define SEMC_INTR_NDPAGEEND_SHIFT (4U) +#define SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK) +#define SEMC_INTR_NDNOPEND_MASK (0x20U) +#define SEMC_INTR_NDNOPEND_SHIFT (5U) +#define SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) +/*! @} */ + +/*! @name SDRAMCR0 - SDRAM control register 0 */ +/*! @{ */ +#define SEMC_SDRAMCR0_PS_MASK (0x1U) +#define SEMC_SDRAMCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ +#define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK) +#define SEMC_SDRAMCR0_BL_MASK (0x70U) +#define SEMC_SDRAMCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..8 + * 0b101..8 + * 0b110..8 + * 0b111..8 + */ +#define SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK) +#define SEMC_SDRAMCR0_COL8_MASK (0x80U) +#define SEMC_SDRAMCR0_COL8_SHIFT (7U) +/*! COL8 - Column 8 selection bit + * 0b0..Column address bit number is decided by COL field. + * 0b1..Column address bit number is 8. COL field is ignored. + */ +#define SEMC_SDRAMCR0_COL8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL8_SHIFT)) & SEMC_SDRAMCR0_COL8_MASK) +#define SEMC_SDRAMCR0_COL_MASK (0x300U) +#define SEMC_SDRAMCR0_COL_SHIFT (8U) +/*! COL - Column address bit number + * 0b00..12 bit + * 0b01..11 bit + * 0b10..10 bit + * 0b11..9 bit + */ +#define SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK) +#define SEMC_SDRAMCR0_CL_MASK (0xC00U) +#define SEMC_SDRAMCR0_CL_SHIFT (10U) +/*! CL - CAS Latency + * 0b00..1 + * 0b01..1 + * 0b10..2 + * 0b11..3 + */ +#define SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK) +#define SEMC_SDRAMCR0_BANK2_MASK (0x4000U) +#define SEMC_SDRAMCR0_BANK2_SHIFT (14U) +/*! BANK2 - 2 Bank selection bit + * 0b0..SDRAM device has 4 banks. + * 0b1..SDRAM device has 2 banks. + */ +#define SEMC_SDRAMCR0_BANK2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BANK2_SHIFT)) & SEMC_SDRAMCR0_BANK2_MASK) +/*! @} */ + +/*! @name SDRAMCR1 - SDRAM control register 1 */ +/*! @{ */ +#define SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU) +#define SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U) +#define SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK) +#define SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U) +#define SEMC_SDRAMCR1_ACT2RW_SHIFT (4U) +#define SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK) +#define SEMC_SDRAMCR1_RFRC_MASK (0x1F00U) +#define SEMC_SDRAMCR1_RFRC_SHIFT (8U) +#define SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK) +#define SEMC_SDRAMCR1_WRC_MASK (0xE000U) +#define SEMC_SDRAMCR1_WRC_SHIFT (13U) +#define SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK) +#define SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U) +#define SEMC_SDRAMCR1_CKEOFF_SHIFT (16U) +#define SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK) +#define SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U) +#define SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U) +#define SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK) +/*! @} */ + +/*! @name SDRAMCR2 - SDRAM control register 2 */ +/*! @{ */ +#define SEMC_SDRAMCR2_SRRC_MASK (0xFFU) +#define SEMC_SDRAMCR2_SRRC_SHIFT (0U) +#define SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK) +#define SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U) +#define SEMC_SDRAMCR2_REF2REF_SHIFT (8U) +#define SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK) +#define SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U) +#define SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U) +#define SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK) +#define SEMC_SDRAMCR2_ITO_MASK (0xFF000000U) +#define SEMC_SDRAMCR2_ITO_SHIFT (24U) +/*! ITO - SDRAM Idle timeout + * 0b00000000..IDLE timeout period is 256*Prescale period. + * 0b00000001-0b11111111..IDLE timeout period is ITO*Prescale period. + */ +#define SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK) +/*! @} */ + +/*! @name SDRAMCR3 - SDRAM control register 3 */ +/*! @{ */ +#define SEMC_SDRAMCR3_REN_MASK (0x1U) +#define SEMC_SDRAMCR3_REN_SHIFT (0U) +#define SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK) +#define SEMC_SDRAMCR3_REBL_MASK (0xEU) +#define SEMC_SDRAMCR3_REBL_SHIFT (1U) +/*! REBL - Refresh burst length + * 0b000..1 + * 0b001..2 + * 0b010..3 + * 0b011..4 + * 0b100..5 + * 0b101..6 + * 0b110..7 + * 0b111..8 + */ +#define SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK) +#define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U) +#define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U) +/*! PRESCALE - Prescaler timer period + * 0b00000000..256*16 cycle + * 0b00000001-0b11111111..PRESCALE*16 cycle + */ +#define SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK) +#define SEMC_SDRAMCR3_RT_MASK (0xFF0000U) +#define SEMC_SDRAMCR3_RT_SHIFT (16U) +/*! RT - Refresh timer period + * 0b00000000..256*Prescaler period + * 0b00000001-0b11111111..RT*Prescaler period + */ +#define SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK) +#define SEMC_SDRAMCR3_UT_MASK (0xFF000000U) +#define SEMC_SDRAMCR3_UT_SHIFT (24U) +/*! UT - Refresh urgent threshold + * 0b00000000..256*Prescaler period + * 0b00000001-0b11111111..UT*Prescaler period + */ +#define SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK) +/*! @} */ + +/*! @name NANDCR0 - NAND control register 0 */ +/*! @{ */ +#define SEMC_NANDCR0_PS_MASK (0x1U) +#define SEMC_NANDCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ +#define SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK) +#define SEMC_NANDCR0_SYNCEN_MASK (0x2U) +#define SEMC_NANDCR0_SYNCEN_SHIFT (1U) +/*! SYNCEN - Select NAND controller mode. + * 0b0..Asynchronous mode is enabled. + * 0b1..Synchronous mode is enabled. + */ +#define SEMC_NANDCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_SYNCEN_SHIFT)) & SEMC_NANDCR0_SYNCEN_MASK) +#define SEMC_NANDCR0_BL_MASK (0x70U) +#define SEMC_NANDCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ +#define SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK) +#define SEMC_NANDCR0_EDO_MASK (0x80U) +#define SEMC_NANDCR0_EDO_SHIFT (7U) +/*! EDO - EDO mode enabled + * 0b0..EDO mode disabled + * 0b1..EDO mode enabled + */ +#define SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK) +#define SEMC_NANDCR0_COL_MASK (0x700U) +#define SEMC_NANDCR0_COL_SHIFT (8U) +/*! COL - Column address bit number + * 0b000..16 + * 0b001..15 + * 0b010..14 + * 0b011..13 + * 0b100..12 + * 0b101..11 + * 0b110..10 + * 0b111..9 + */ +#define SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK) +/*! @} */ + +/*! @name NANDCR1 - NAND control register 1 */ +/*! @{ */ +#define SEMC_NANDCR1_CES_MASK (0xFU) +#define SEMC_NANDCR1_CES_SHIFT (0U) +#define SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK) +#define SEMC_NANDCR1_CEH_MASK (0xF0U) +#define SEMC_NANDCR1_CEH_SHIFT (4U) +#define SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK) +#define SEMC_NANDCR1_WEL_MASK (0xF00U) +#define SEMC_NANDCR1_WEL_SHIFT (8U) +#define SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK) +#define SEMC_NANDCR1_WEH_MASK (0xF000U) +#define SEMC_NANDCR1_WEH_SHIFT (12U) +#define SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK) +#define SEMC_NANDCR1_REL_MASK (0xF0000U) +#define SEMC_NANDCR1_REL_SHIFT (16U) +#define SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK) +#define SEMC_NANDCR1_REH_MASK (0xF00000U) +#define SEMC_NANDCR1_REH_SHIFT (20U) +#define SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK) +#define SEMC_NANDCR1_TA_MASK (0xF000000U) +#define SEMC_NANDCR1_TA_SHIFT (24U) +#define SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK) +#define SEMC_NANDCR1_CEITV_MASK (0xF0000000U) +#define SEMC_NANDCR1_CEITV_SHIFT (28U) +#define SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK) +/*! @} */ + +/*! @name NANDCR2 - NAND control register 2 */ +/*! @{ */ +#define SEMC_NANDCR2_TWHR_MASK (0x3FU) +#define SEMC_NANDCR2_TWHR_SHIFT (0U) +#define SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK) +#define SEMC_NANDCR2_TRHW_MASK (0xFC0U) +#define SEMC_NANDCR2_TRHW_SHIFT (6U) +#define SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK) +#define SEMC_NANDCR2_TADL_MASK (0x3F000U) +#define SEMC_NANDCR2_TADL_SHIFT (12U) +#define SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK) +#define SEMC_NANDCR2_TRR_MASK (0xFC0000U) +#define SEMC_NANDCR2_TRR_SHIFT (18U) +#define SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK) +#define SEMC_NANDCR2_TWB_MASK (0x3F000000U) +#define SEMC_NANDCR2_TWB_SHIFT (24U) +#define SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK) +/*! @} */ + +/*! @name NANDCR3 - NAND control register 3 */ +/*! @{ */ +#define SEMC_NANDCR3_NDOPT1_MASK (0x1U) +#define SEMC_NANDCR3_NDOPT1_SHIFT (0U) +#define SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK) +#define SEMC_NANDCR3_NDOPT2_MASK (0x2U) +#define SEMC_NANDCR3_NDOPT2_SHIFT (1U) +#define SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK) +#define SEMC_NANDCR3_NDOPT3_MASK (0x4U) +#define SEMC_NANDCR3_NDOPT3_SHIFT (2U) +#define SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK) +#define SEMC_NANDCR3_CLE_MASK (0x8U) +#define SEMC_NANDCR3_CLE_SHIFT (3U) +#define SEMC_NANDCR3_CLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_CLE_SHIFT)) & SEMC_NANDCR3_CLE_MASK) +#define SEMC_NANDCR3_RDS_MASK (0xF0000U) +#define SEMC_NANDCR3_RDS_SHIFT (16U) +#define SEMC_NANDCR3_RDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDS_SHIFT)) & SEMC_NANDCR3_RDS_MASK) +#define SEMC_NANDCR3_RDH_MASK (0xF00000U) +#define SEMC_NANDCR3_RDH_SHIFT (20U) +#define SEMC_NANDCR3_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDH_SHIFT)) & SEMC_NANDCR3_RDH_MASK) +#define SEMC_NANDCR3_WDS_MASK (0xF000000U) +#define SEMC_NANDCR3_WDS_SHIFT (24U) +#define SEMC_NANDCR3_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDS_SHIFT)) & SEMC_NANDCR3_WDS_MASK) +#define SEMC_NANDCR3_WDH_MASK (0xF0000000U) +#define SEMC_NANDCR3_WDH_SHIFT (28U) +#define SEMC_NANDCR3_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDH_SHIFT)) & SEMC_NANDCR3_WDH_MASK) +/*! @} */ + +/*! @name NORCR0 - NOR control register 0 */ +/*! @{ */ +#define SEMC_NORCR0_PS_MASK (0x1U) +#define SEMC_NORCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ +#define SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK) +#define SEMC_NORCR0_SYNCEN_MASK (0x2U) +#define SEMC_NORCR0_SYNCEN_SHIFT (1U) +/*! SYNCEN - Select NOR controller mode. + * 0b0..Asynchronous mode is enabled. + * 0b1..Synchronous mode is enabled. + */ +#define SEMC_NORCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_SYNCEN_SHIFT)) & SEMC_NORCR0_SYNCEN_MASK) +#define SEMC_NORCR0_BL_MASK (0x70U) +#define SEMC_NORCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ +#define SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK) +#define SEMC_NORCR0_AM_MASK (0x300U) +#define SEMC_NORCR0_AM_SHIFT (8U) +/*! AM - Address Mode + * 0b00..Address/Data MUX mode + * 0b01..Advanced Address/Data MUX mode + * 0b10..Address/Data non-MUX mode + * 0b11..Address/Data non-MUX mode + */ +#define SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK) +#define SEMC_NORCR0_ADVP_MASK (0x400U) +#define SEMC_NORCR0_ADVP_SHIFT (10U) +/*! ADVP - ADV# polarity + * 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. + * 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH. + */ +#define SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK) +#define SEMC_NORCR0_ADVH_MASK (0x800U) +#define SEMC_NORCR0_ADVH_SHIFT (11U) +/*! ADVH - ADV# level control during address hold state + * 0b0..ADV# is high during address hold state. + * 0b1..ADV# is low during address hold state. + */ +#define SEMC_NORCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVH_SHIFT)) & SEMC_NORCR0_ADVH_MASK) +#define SEMC_NORCR0_COL_MASK (0xF000U) +#define SEMC_NORCR0_COL_SHIFT (12U) +/*! COL - Column Address bit width + * 0b0000..12 Bits + * 0b0001..11 Bits + * 0b0010..10 Bits + * 0b0011..9 Bits + * 0b0100..8 Bits + * 0b0101..7 Bits + * 0b0110..6 Bits + * 0b0111..5 Bits + * 0b1000..4 Bits + * 0b1001..3 Bits + * 0b1010..2 Bits + * 0b1011..12 Bits + * 0b1100..12 Bits + * 0b1101..12 Bits + * 0b1110..12 Bits + * 0b1111..12 Bits + */ +#define SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK) +/*! @} */ + +/*! @name NORCR1 - NOR control register 1 */ +/*! @{ */ +#define SEMC_NORCR1_CES_MASK (0xFU) +#define SEMC_NORCR1_CES_SHIFT (0U) +#define SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK) +#define SEMC_NORCR1_CEH_MASK (0xF0U) +#define SEMC_NORCR1_CEH_SHIFT (4U) +#define SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK) +#define SEMC_NORCR1_AS_MASK (0xF00U) +#define SEMC_NORCR1_AS_SHIFT (8U) +#define SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK) +#define SEMC_NORCR1_AH_MASK (0xF000U) +#define SEMC_NORCR1_AH_SHIFT (12U) +#define SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK) +#define SEMC_NORCR1_WEL_MASK (0xF0000U) +#define SEMC_NORCR1_WEL_SHIFT (16U) +#define SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK) +#define SEMC_NORCR1_WEH_MASK (0xF00000U) +#define SEMC_NORCR1_WEH_SHIFT (20U) +#define SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK) +#define SEMC_NORCR1_REL_MASK (0xF000000U) +#define SEMC_NORCR1_REL_SHIFT (24U) +#define SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK) +#define SEMC_NORCR1_REH_MASK (0xF0000000U) +#define SEMC_NORCR1_REH_SHIFT (28U) +#define SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK) +/*! @} */ + +/*! @name NORCR2 - NOR control register 2 */ +/*! @{ */ +#define SEMC_NORCR2_TA_MASK (0xF00U) +#define SEMC_NORCR2_TA_SHIFT (8U) +#define SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK) +#define SEMC_NORCR2_AWDH_MASK (0xF000U) +#define SEMC_NORCR2_AWDH_SHIFT (12U) +#define SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK) +#define SEMC_NORCR2_LC_MASK (0xF0000U) +#define SEMC_NORCR2_LC_SHIFT (16U) +#define SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK) +#define SEMC_NORCR2_RD_MASK (0xF00000U) +#define SEMC_NORCR2_RD_SHIFT (20U) +#define SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK) +#define SEMC_NORCR2_CEITV_MASK (0xF000000U) +#define SEMC_NORCR2_CEITV_SHIFT (24U) +#define SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK) +#define SEMC_NORCR2_RDH_MASK (0xF0000000U) +#define SEMC_NORCR2_RDH_SHIFT (28U) +#define SEMC_NORCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK) +/*! @} */ + +/*! @name NORCR3 - NOR control register 3 */ +/*! @{ */ +#define SEMC_NORCR3_ASSR_MASK (0xFU) +#define SEMC_NORCR3_ASSR_SHIFT (0U) +#define SEMC_NORCR3_ASSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_ASSR_SHIFT)) & SEMC_NORCR3_ASSR_MASK) +#define SEMC_NORCR3_AHSR_MASK (0xF0U) +#define SEMC_NORCR3_AHSR_SHIFT (4U) +#define SEMC_NORCR3_AHSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_AHSR_SHIFT)) & SEMC_NORCR3_AHSR_MASK) +/*! @} */ + +/*! @name SRAMCR0 - SRAM control register 0 */ +/*! @{ */ +#define SEMC_SRAMCR0_PS_MASK (0x1U) +#define SEMC_SRAMCR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ +#define SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK) +#define SEMC_SRAMCR0_SYNCEN_MASK (0x2U) +#define SEMC_SRAMCR0_SYNCEN_SHIFT (1U) +/*! SYNCEN - Select SRAM controller mode. + * 0b0..Asynchronous mode is enabled. + * 0b1..Synchronous mode is enabled. + */ +#define SEMC_SRAMCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK) +#define SEMC_SRAMCR0_BL_MASK (0x70U) +#define SEMC_SRAMCR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ +#define SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK) +#define SEMC_SRAMCR0_AM_MASK (0x300U) +#define SEMC_SRAMCR0_AM_SHIFT (8U) +/*! AM - Address Mode + * 0b00..Address/Data MUX mode + * 0b01..Advanced Address/Data MUX mode + * 0b10..Address/Data non-MUX mode + * 0b11..Address/Data non-MUX mode + */ +#define SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK) +#define SEMC_SRAMCR0_ADVP_MASK (0x400U) +#define SEMC_SRAMCR0_ADVP_SHIFT (10U) +/*! ADVP - ADV# polarity + * 0b0..ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. + * 0b1..ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH. + */ +#define SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK) +#define SEMC_SRAMCR0_ADVH_MASK (0x800U) +#define SEMC_SRAMCR0_ADVH_SHIFT (11U) +/*! ADVH - ADV# level control during address hold state + * 0b0..ADV# is high during address hold state. + * 0b1..ADV# is low during address hold state. + */ +#define SEMC_SRAMCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVH_SHIFT)) & SEMC_SRAMCR0_ADVH_MASK) +#define SEMC_SRAMCR0_COL_MASK (0xF000U) +#define SEMC_SRAMCR0_COL_SHIFT (12U) +/*! COL - Column Address bit width + * 0b0000..12 Bits + * 0b0001..11 Bits + * 0b0010..10 Bits + * 0b0011..9 Bits + * 0b0100..8 Bits + * 0b0101..7 Bits + * 0b0110..6 Bits + * 0b0111..5 Bits + * 0b1000..4 Bits + * 0b1001..3 Bits + * 0b1010..2 Bits + * 0b1011..12 Bits + * 0b1100..12 Bits + * 0b1101..12 Bits + * 0b1110..12 Bits + * 0b1111..12 Bits + */ +#define SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK) +/*! @} */ + +/*! @name SRAMCR1 - SRAM control register 1 */ +/*! @{ */ +#define SEMC_SRAMCR1_CES_MASK (0xFU) +#define SEMC_SRAMCR1_CES_SHIFT (0U) +#define SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK) +#define SEMC_SRAMCR1_CEH_MASK (0xF0U) +#define SEMC_SRAMCR1_CEH_SHIFT (4U) +#define SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK) +#define SEMC_SRAMCR1_AS_MASK (0xF00U) +#define SEMC_SRAMCR1_AS_SHIFT (8U) +#define SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK) +#define SEMC_SRAMCR1_AH_MASK (0xF000U) +#define SEMC_SRAMCR1_AH_SHIFT (12U) +#define SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK) +#define SEMC_SRAMCR1_WEL_MASK (0xF0000U) +#define SEMC_SRAMCR1_WEL_SHIFT (16U) +#define SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK) +#define SEMC_SRAMCR1_WEH_MASK (0xF00000U) +#define SEMC_SRAMCR1_WEH_SHIFT (20U) +#define SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK) +#define SEMC_SRAMCR1_REL_MASK (0xF000000U) +#define SEMC_SRAMCR1_REL_SHIFT (24U) +#define SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK) +#define SEMC_SRAMCR1_REH_MASK (0xF0000000U) +#define SEMC_SRAMCR1_REH_SHIFT (28U) +#define SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK) +/*! @} */ + +/*! @name SRAMCR2 - SRAM control register 2 */ +/*! @{ */ +#define SEMC_SRAMCR2_WDS_MASK (0xFU) +#define SEMC_SRAMCR2_WDS_SHIFT (0U) +#define SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK) +#define SEMC_SRAMCR2_WDH_MASK (0xF0U) +#define SEMC_SRAMCR2_WDH_SHIFT (4U) +#define SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK) +#define SEMC_SRAMCR2_TA_MASK (0xF00U) +#define SEMC_SRAMCR2_TA_SHIFT (8U) +#define SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK) +#define SEMC_SRAMCR2_AWDH_MASK (0xF000U) +#define SEMC_SRAMCR2_AWDH_SHIFT (12U) +#define SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK) +#define SEMC_SRAMCR2_LC_MASK (0xF0000U) +#define SEMC_SRAMCR2_LC_SHIFT (16U) +#define SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK) +#define SEMC_SRAMCR2_RD_MASK (0xF00000U) +#define SEMC_SRAMCR2_RD_SHIFT (20U) +#define SEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK) +#define SEMC_SRAMCR2_CEITV_MASK (0xF000000U) +#define SEMC_SRAMCR2_CEITV_SHIFT (24U) +#define SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK) +#define SEMC_SRAMCR2_RDH_MASK (0xF0000000U) +#define SEMC_SRAMCR2_RDH_SHIFT (28U) +#define SEMC_SRAMCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RDH_SHIFT)) & SEMC_SRAMCR2_RDH_MASK) +/*! @} */ + +/*! @name DBICR0 - DBI-B control register 0 */ +/*! @{ */ +#define SEMC_DBICR0_PS_MASK (0x1U) +#define SEMC_DBICR0_PS_SHIFT (0U) +/*! PS - Port Size + * 0b0..8bit + * 0b1..16bit + */ +#define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK) +#define SEMC_DBICR0_BL_MASK (0x70U) +#define SEMC_DBICR0_BL_SHIFT (4U) +/*! BL - Burst Length + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..64 + */ +#define SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK) +#define SEMC_DBICR0_COL_MASK (0xF000U) +#define SEMC_DBICR0_COL_SHIFT (12U) +/*! COL - Column Address bit width + * 0b0000..12 Bits + * 0b0001..11 Bits + * 0b0010..10 Bits + * 0b0011..9 Bits + * 0b0100..8 Bits + * 0b0101..7 Bits + * 0b0110..6 Bits + * 0b0111..5 Bits + * 0b1000..4 Bits + * 0b1001..3 Bits + * 0b1010..2 Bits + * 0b1011..12 Bits + * 0b1100..12 Bits + * 0b1101..12 Bits + * 0b1110..12 Bits + * 0b1111..12 Bits + */ +#define SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK) +/*! @} */ + +/*! @name DBICR1 - DBI-B control register 1 */ +/*! @{ */ +#define SEMC_DBICR1_CES_MASK (0xFU) +#define SEMC_DBICR1_CES_SHIFT (0U) +#define SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK) +#define SEMC_DBICR1_CEH_MASK (0xF0U) +#define SEMC_DBICR1_CEH_SHIFT (4U) +#define SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK) +#define SEMC_DBICR1_WEL_MASK (0xF00U) +#define SEMC_DBICR1_WEL_SHIFT (8U) +#define SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK) +#define SEMC_DBICR1_WEH_MASK (0xF000U) +#define SEMC_DBICR1_WEH_SHIFT (12U) +#define SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK) +#define SEMC_DBICR1_REL_MASK (0x3F0000U) +#define SEMC_DBICR1_REL_SHIFT (16U) +#define SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK) +#define SEMC_DBICR1_REH_MASK (0xFC00000U) +#define SEMC_DBICR1_REH_SHIFT (22U) +#define SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK) +#define SEMC_DBICR1_CEITV_MASK (0xF0000000U) +#define SEMC_DBICR1_CEITV_SHIFT (28U) +#define SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK) +/*! @} */ + +/*! @name IPCR0 - IP Command control register 0 */ +/*! @{ */ +#define SEMC_IPCR0_SA_MASK (0xFFFFFFFFU) +#define SEMC_IPCR0_SA_SHIFT (0U) +#define SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK) +/*! @} */ + +/*! @name IPCR1 - IP Command control register 1 */ +/*! @{ */ +#define SEMC_IPCR1_DATSZ_MASK (0x7U) +#define SEMC_IPCR1_DATSZ_SHIFT (0U) +/*! DATSZ - Data Size in Byte + * 0b000..4 + * 0b001..1 + * 0b010..2 + * 0b011..3 + * 0b100..4 + * 0b101..4 + * 0b110..4 + * 0b111..4 + */ +#define SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK) +#define SEMC_IPCR1_NAND_EXT_ADDR_MASK (0xFF00U) +#define SEMC_IPCR1_NAND_EXT_ADDR_SHIFT (8U) +#define SEMC_IPCR1_NAND_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_NAND_EXT_ADDR_SHIFT)) & SEMC_IPCR1_NAND_EXT_ADDR_MASK) +/*! @} */ + +/*! @name IPCR2 - IP Command control register 2 */ +/*! @{ */ +#define SEMC_IPCR2_BM0_MASK (0x1U) +#define SEMC_IPCR2_BM0_SHIFT (0U) +/*! BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ +#define SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK) +#define SEMC_IPCR2_BM1_MASK (0x2U) +#define SEMC_IPCR2_BM1_SHIFT (1U) +/*! BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ +#define SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK) +#define SEMC_IPCR2_BM2_MASK (0x4U) +#define SEMC_IPCR2_BM2_SHIFT (2U) +/*! BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ +#define SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK) +#define SEMC_IPCR2_BM3_MASK (0x8U) +#define SEMC_IPCR2_BM3_SHIFT (3U) +/*! BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24) + * 0b0..Byte Unmasked + * 0b1..Byte Masked + */ +#define SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK) +/*! @} */ + +/*! @name IPCMD - IP Command register */ +/*! @{ */ +#define SEMC_IPCMD_CMD_MASK (0xFFFFU) +#define SEMC_IPCMD_CMD_SHIFT (0U) +#define SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK) +#define SEMC_IPCMD_KEY_MASK (0xFFFF0000U) +#define SEMC_IPCMD_KEY_SHIFT (16U) +#define SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK) +/*! @} */ + +/*! @name IPTXDAT - TX DATA register (for IP Command) */ +/*! @{ */ +#define SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU) +#define SEMC_IPTXDAT_DAT_SHIFT (0U) +#define SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK) +/*! @} */ + +/*! @name IPRXDAT - RX DATA register (for IP Command) */ +/*! @{ */ +#define SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU) +#define SEMC_IPRXDAT_DAT_SHIFT (0U) +#define SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK) +/*! @} */ + +/*! @name STS0 - Status register 0 */ +/*! @{ */ +#define SEMC_STS0_IDLE_MASK (0x1U) +#define SEMC_STS0_IDLE_SHIFT (0U) +#define SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) +#define SEMC_STS0_NARDY_MASK (0x2U) +#define SEMC_STS0_NARDY_SHIFT (1U) +/*! NARDY - Indicating NAND device Ready/WAIT# pin level. + * 0b0..NAND device is not ready + * 0b1..NAND device is ready + */ +#define SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) +/*! @} */ + +/*! @name STS2 - Status register 2 */ +/*! @{ */ +#define SEMC_STS2_NDWRPEND_MASK (0x8U) +#define SEMC_STS2_NDWRPEND_SHIFT (3U) +/*! NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device. + * 0b0..No pending + * 0b1..Pending + */ +#define SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) +/*! @} */ + +/*! @name STS12 - Status register 12 */ +/*! @{ */ +#define SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU) +#define SEMC_STS12_NDADDR_SHIFT (0U) +#define SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK) +/*! @} */ + +/*! @name STS13 - Status register 13 */ +/*! @{ */ +#define SEMC_STS13_SLVLOCK_MASK (0x1U) +#define SEMC_STS13_SLVLOCK_SHIFT (0U) +#define SEMC_STS13_SLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVLOCK_SHIFT)) & SEMC_STS13_SLVLOCK_MASK) +#define SEMC_STS13_REFLOCK_MASK (0x2U) +#define SEMC_STS13_REFLOCK_SHIFT (1U) +#define SEMC_STS13_REFLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFLOCK_SHIFT)) & SEMC_STS13_REFLOCK_MASK) +#define SEMC_STS13_SLVSEL_MASK (0xFCU) +#define SEMC_STS13_SLVSEL_SHIFT (2U) +#define SEMC_STS13_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVSEL_SHIFT)) & SEMC_STS13_SLVSEL_MASK) +#define SEMC_STS13_REFSEL_MASK (0x3F00U) +#define SEMC_STS13_REFSEL_SHIFT (8U) +#define SEMC_STS13_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFSEL_SHIFT)) & SEMC_STS13_REFSEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SEMC_Register_Masks */ + + +/* SEMC - Peripheral instance base addresses */ +/** Peripheral SEMC base address */ +#define SEMC_BASE (0x402F0000u) +/** Peripheral SEMC base pointer */ +#define SEMC ((SEMC_Type *)SEMC_BASE) +/** Array initializer of SEMC peripheral base addresses */ +#define SEMC_BASE_ADDRS { SEMC_BASE } +/** Array initializer of SEMC peripheral base pointers */ +#define SEMC_BASE_PTRS { SEMC } +/** Interrupt vectors for the SEMC peripheral type */ +#define SEMC_IRQS { SEMC_IRQn } + +/*! + * @} + */ /* end of group SEMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SNVS Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer + * @{ + */ + +/** SNVS - Register Layout Typedef */ +typedef struct { + __IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */ + __IO uint32_t HPCOMR; /**< SNVS_HP Command Register, offset: 0x4 */ + __IO uint32_t HPCR; /**< SNVS_HP Control Register, offset: 0x8 */ + __IO uint32_t HPSICR; /**< SNVS_HP Security Interrupt Control Register, offset: 0xC */ + __IO uint32_t HPSVCR; /**< SNVS_HP Security Violation Control Register, offset: 0x10 */ + __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */ + __IO uint32_t HPSVSR; /**< SNVS_HP Security Violation Status Register, offset: 0x18 */ + __IO uint32_t HPHACIVR; /**< SNVS_HP High Assurance Counter IV Register, offset: 0x1C */ + __I uint32_t HPHACR; /**< SNVS_HP High Assurance Counter Register, offset: 0x20 */ + __IO uint32_t HPRTCMR; /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */ + __IO uint32_t HPRTCLR; /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */ + __IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */ + __IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */ + __IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */ + __IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */ + __IO uint32_t LPMKCR; /**< SNVS_LP Master Key Control Register, offset: 0x3C */ + __IO uint32_t LPSVCR; /**< SNVS_LP Security Violation Control Register, offset: 0x40 */ + uint8_t RESERVED_0[4]; + __IO uint32_t LPTDCR; /**< SNVS_LP Tamper Detectors Configuration Register, offset: 0x48 */ + __IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */ + __IO uint32_t LPSRTCMR; /**< SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50 */ + __IO uint32_t LPSRTCLR; /**< SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54 */ + __IO uint32_t LPTAR; /**< SNVS_LP Time Alarm Register, offset: 0x58 */ + __I uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */ + __I uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */ + __IO uint32_t LPPGDR; /**< SNVS_LP Power Glitch Detector Register, offset: 0x64 */ + __IO uint32_t LPGPR0_LEGACY_ALIAS; /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */ + __IO uint32_t LPZMKR[8]; /**< SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4 */ + uint8_t RESERVED_1[4]; + __IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */ + uint8_t RESERVED_2[96]; + __IO uint32_t LPGPR[8]; /**< SNVS_LP General Purpose Registers 0 .. 7, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_3[2776]; + __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */ + __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */ +} SNVS_Type; + +/* ---------------------------------------------------------------------------- + -- SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Register_Masks SNVS Register Masks + * @{ + */ + +/*! @name HPLR - SNVS_HP Lock Register */ +/*! @{ */ +#define SNVS_HPLR_ZMK_WSL_MASK (0x1U) +#define SNVS_HPLR_ZMK_WSL_SHIFT (0U) +/*! ZMK_WSL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK) +#define SNVS_HPLR_ZMK_RSL_MASK (0x2U) +#define SNVS_HPLR_ZMK_RSL_SHIFT (1U) +/*! ZMK_RSL + * 0b0..Read access is allowed (only in software Programming mode) + * 0b1..Read access is not allowed + */ +#define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK) +#define SNVS_HPLR_SRTC_SL_MASK (0x4U) +#define SNVS_HPLR_SRTC_SL_SHIFT (2U) +/*! SRTC_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK) +#define SNVS_HPLR_LPCALB_SL_MASK (0x8U) +#define SNVS_HPLR_LPCALB_SL_SHIFT (3U) +/*! LPCALB_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK) +#define SNVS_HPLR_MC_SL_MASK (0x10U) +#define SNVS_HPLR_MC_SL_SHIFT (4U) +/*! MC_SL + * 0b0..Write access (increment) is allowed + * 0b1..Write access (increment) is not allowed + */ +#define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK) +#define SNVS_HPLR_GPR_SL_MASK (0x20U) +#define SNVS_HPLR_GPR_SL_SHIFT (5U) +/*! GPR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK) +#define SNVS_HPLR_LPSVCR_SL_MASK (0x40U) +#define SNVS_HPLR_LPSVCR_SL_SHIFT (6U) +/*! LPSVCR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK) +#define SNVS_HPLR_LPTDCR_SL_MASK (0x100U) +#define SNVS_HPLR_LPTDCR_SL_SHIFT (8U) +/*! LPTDCR_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_LPTDCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTDCR_SL_SHIFT)) & SNVS_HPLR_LPTDCR_SL_MASK) +#define SNVS_HPLR_MKS_SL_MASK (0x200U) +#define SNVS_HPLR_MKS_SL_SHIFT (9U) +/*! MKS_SL + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK) +#define SNVS_HPLR_HPSVCR_L_MASK (0x10000U) +#define SNVS_HPLR_HPSVCR_L_SHIFT (16U) +/*! HPSVCR_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK) +#define SNVS_HPLR_HPSICR_L_MASK (0x20000U) +#define SNVS_HPLR_HPSICR_L_SHIFT (17U) +/*! HPSICR_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK) +#define SNVS_HPLR_HAC_L_MASK (0x40000U) +#define SNVS_HPLR_HAC_L_SHIFT (18U) +/*! HAC_L + * 0b0..Write access is allowed + * 0b1..Write access is not allowed + */ +#define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK) +/*! @} */ + +/*! @name HPCOMR - SNVS_HP Command Register */ +/*! @{ */ +#define SNVS_HPCOMR_SSM_ST_MASK (0x1U) +#define SNVS_HPCOMR_SSM_ST_SHIFT (0U) +#define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK) +#define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U) +#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U) +/*! SSM_ST_DIS + * 0b0..Secure to Trusted State transition is enabled + * 0b1..Secure to Trusted State transition is disabled + */ +#define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK) +#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U) +#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U) +/*! SSM_SFNS_DIS + * 0b0..Soft Fail to Non-Secure State transition is enabled + * 0b1..Soft Fail to Non-Secure State transition is disabled + */ +#define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK) +#define SNVS_HPCOMR_LP_SWR_MASK (0x10U) +#define SNVS_HPCOMR_LP_SWR_SHIFT (4U) +/*! LP_SWR + * 0b0..No Action + * 0b1..Reset LP section + */ +#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK) +#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U) +#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U) +/*! LP_SWR_DIS + * 0b0..LP software reset is enabled + * 0b1..LP software reset is disabled + */ +#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK) +#define SNVS_HPCOMR_SW_SV_MASK (0x100U) +#define SNVS_HPCOMR_SW_SV_SHIFT (8U) +#define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK) +#define SNVS_HPCOMR_SW_FSV_MASK (0x200U) +#define SNVS_HPCOMR_SW_FSV_SHIFT (9U) +#define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK) +#define SNVS_HPCOMR_SW_LPSV_MASK (0x400U) +#define SNVS_HPCOMR_SW_LPSV_SHIFT (10U) +#define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK) +#define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U) +#define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U) +/*! PROG_ZMK + * 0b0..No Action + * 0b1..Activate hardware key programming mechanism + */ +#define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK) +#define SNVS_HPCOMR_MKS_EN_MASK (0x2000U) +#define SNVS_HPCOMR_MKS_EN_SHIFT (13U) +/*! MKS_EN + * 0b0..OTP master key is selected as an SNVS master key + * 0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR + */ +#define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK) +#define SNVS_HPCOMR_HAC_EN_MASK (0x10000U) +#define SNVS_HPCOMR_HAC_EN_SHIFT (16U) +/*! HAC_EN + * 0b0..High Assurance Counter is disabled + * 0b1..High Assurance Counter is enabled + */ +#define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK) +#define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U) +#define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U) +/*! HAC_LOAD + * 0b0..No Action + * 0b1..Load the HAC + */ +#define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK) +#define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U) +#define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U) +/*! HAC_CLEAR + * 0b0..No Action + * 0b1..Clear the HAC + */ +#define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK) +#define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U) +#define SNVS_HPCOMR_HAC_STOP_SHIFT (19U) +#define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK) +#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) +#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) +#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) +/*! @} */ + +/*! @name HPCR - SNVS_HP Control Register */ +/*! @{ */ +#define SNVS_HPCR_RTC_EN_MASK (0x1U) +#define SNVS_HPCR_RTC_EN_SHIFT (0U) +/*! RTC_EN + * 0b0..RTC is disabled + * 0b1..RTC is enabled + */ +#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) +#define SNVS_HPCR_HPTA_EN_MASK (0x2U) +#define SNVS_HPCR_HPTA_EN_SHIFT (1U) +/*! HPTA_EN + * 0b0..HP Time Alarm Interrupt is disabled + * 0b1..HP Time Alarm Interrupt is enabled + */ +#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) +#define SNVS_HPCR_DIS_PI_MASK (0x4U) +#define SNVS_HPCR_DIS_PI_SHIFT (2U) +/*! DIS_PI + * 0b0..Periodic interrupt will trigger a functional interrupt + * 0b1..Disable periodic interrupt in the function interrupt + */ +#define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK) +#define SNVS_HPCR_PI_EN_MASK (0x8U) +#define SNVS_HPCR_PI_EN_SHIFT (3U) +/*! PI_EN + * 0b0..HP Periodic Interrupt is disabled + * 0b1..HP Periodic Interrupt is enabled + */ +#define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK) +#define SNVS_HPCR_PI_FREQ_MASK (0xF0U) +#define SNVS_HPCR_PI_FREQ_SHIFT (4U) +/*! PI_FREQ + * 0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt + * 0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt + */ +#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK) +#define SNVS_HPCR_HPCALB_EN_MASK (0x100U) +#define SNVS_HPCR_HPCALB_EN_SHIFT (8U) +/*! HPCALB_EN + * 0b0..HP Timer calibration disabled + * 0b1..HP Timer calibration enabled + */ +#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK) +#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U) +#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U) +/*! HPCALB_VAL + * 0b00000..+0 counts per each 32768 ticks of the counter + * 0b00001..+1 counts per each 32768 ticks of the counter + * 0b00010..+2 counts per each 32768 ticks of the counter + * 0b01111..+15 counts per each 32768 ticks of the counter + * 0b10000..-16 counts per each 32768 ticks of the counter + * 0b10001..-15 counts per each 32768 ticks of the counter + * 0b11110..-2 counts per each 32768 ticks of the counter + * 0b11111..-1 counts per each 32768 ticks of the counter + */ +#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK) +#define SNVS_HPCR_HP_TS_MASK (0x10000U) +#define SNVS_HPCR_HP_TS_SHIFT (16U) +/*! HP_TS + * 0b0..No Action + * 0b1..Synchronize the HP Time Counter to the LP Time Counter + */ +#define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK) +#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U) +#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U) +#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK) +#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U) +#define SNVS_HPCR_BTN_MASK_SHIFT (27U) +#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK) +/*! @} */ + +/*! @name HPSICR - SNVS_HP Security Interrupt Control Register */ +/*! @{ */ +#define SNVS_HPSICR_SV0_EN_MASK (0x1U) +#define SNVS_HPSICR_SV0_EN_SHIFT (0U) +/*! SV0_EN + * 0b0..Security Violation 0 Interrupt is Disabled + * 0b1..Security Violation 0 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK) +#define SNVS_HPSICR_SV1_EN_MASK (0x2U) +#define SNVS_HPSICR_SV1_EN_SHIFT (1U) +/*! SV1_EN + * 0b0..Security Violation 1 Interrupt is Disabled + * 0b1..Security Violation 1 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK) +#define SNVS_HPSICR_SV2_EN_MASK (0x4U) +#define SNVS_HPSICR_SV2_EN_SHIFT (2U) +/*! SV2_EN + * 0b0..Security Violation 2 Interrupt is Disabled + * 0b1..Security Violation 2 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK) +#define SNVS_HPSICR_SV3_EN_MASK (0x8U) +#define SNVS_HPSICR_SV3_EN_SHIFT (3U) +/*! SV3_EN + * 0b0..Security Violation 3 Interrupt is Disabled + * 0b1..Security Violation 3 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK) +#define SNVS_HPSICR_SV4_EN_MASK (0x10U) +#define SNVS_HPSICR_SV4_EN_SHIFT (4U) +/*! SV4_EN + * 0b0..Security Violation 4 Interrupt is Disabled + * 0b1..Security Violation 4 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK) +#define SNVS_HPSICR_SV5_EN_MASK (0x20U) +#define SNVS_HPSICR_SV5_EN_SHIFT (5U) +/*! SV5_EN + * 0b0..Security Violation 5 Interrupt is Disabled + * 0b1..Security Violation 5 Interrupt is Enabled + */ +#define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK) +#define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U) +#define SNVS_HPSICR_LPSVI_EN_SHIFT (31U) +/*! LPSVI_EN + * 0b0..LP Security Violation Interrupt is Disabled + * 0b1..LP Security Violation Interrupt is Enabled + */ +#define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK) +/*! @} */ + +/*! @name HPSVCR - SNVS_HP Security Violation Control Register */ +/*! @{ */ +#define SNVS_HPSVCR_SV0_CFG_MASK (0x1U) +#define SNVS_HPSVCR_SV0_CFG_SHIFT (0U) +/*! SV0_CFG + * 0b0..Security Violation 0 is a non-fatal violation + * 0b1..Security Violation 0 is a fatal violation + */ +#define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK) +#define SNVS_HPSVCR_SV1_CFG_MASK (0x2U) +#define SNVS_HPSVCR_SV1_CFG_SHIFT (1U) +/*! SV1_CFG + * 0b0..Security Violation 1 is a non-fatal violation + * 0b1..Security Violation 1 is a fatal violation + */ +#define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK) +#define SNVS_HPSVCR_SV2_CFG_MASK (0x4U) +#define SNVS_HPSVCR_SV2_CFG_SHIFT (2U) +/*! SV2_CFG + * 0b0..Security Violation 2 is a non-fatal violation + * 0b1..Security Violation 2 is a fatal violation + */ +#define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK) +#define SNVS_HPSVCR_SV3_CFG_MASK (0x8U) +#define SNVS_HPSVCR_SV3_CFG_SHIFT (3U) +/*! SV3_CFG + * 0b0..Security Violation 3 is a non-fatal violation + * 0b1..Security Violation 3 is a fatal violation + */ +#define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK) +#define SNVS_HPSVCR_SV4_CFG_MASK (0x10U) +#define SNVS_HPSVCR_SV4_CFG_SHIFT (4U) +/*! SV4_CFG + * 0b0..Security Violation 4 is a non-fatal violation + * 0b1..Security Violation 4 is a fatal violation + */ +#define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK) +#define SNVS_HPSVCR_SV5_CFG_MASK (0x60U) +#define SNVS_HPSVCR_SV5_CFG_SHIFT (5U) +/*! SV5_CFG + * 0b00..Security Violation 5 is disabled + * 0b01..Security Violation 5 is a non-fatal violation + * 0b1x..Security Violation 5 is a fatal violation + */ +#define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK) +#define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U) +#define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U) +/*! LPSV_CFG + * 0b00..LP security violation is disabled + * 0b01..LP security violation is a non-fatal violation + * 0b1x..LP security violation is a fatal violation + */ +#define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK) +/*! @} */ + +/*! @name HPSR - SNVS_HP Status Register */ +/*! @{ */ +#define SNVS_HPSR_HPTA_MASK (0x1U) +#define SNVS_HPSR_HPTA_SHIFT (0U) +/*! HPTA + * 0b0..No time alarm interrupt occurred. + * 0b1..A time alarm interrupt occurred. + */ +#define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK) +#define SNVS_HPSR_PI_MASK (0x2U) +#define SNVS_HPSR_PI_SHIFT (1U) +/*! PI + * 0b0..No periodic interrupt occurred. + * 0b1..A periodic interrupt occurred. + */ +#define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK) +#define SNVS_HPSR_LPDIS_MASK (0x10U) +#define SNVS_HPSR_LPDIS_SHIFT (4U) +#define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK) +#define SNVS_HPSR_BTN_MASK (0x40U) +#define SNVS_HPSR_BTN_SHIFT (6U) +#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK) +#define SNVS_HPSR_BI_MASK (0x80U) +#define SNVS_HPSR_BI_SHIFT (7U) +#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK) +#define SNVS_HPSR_SSM_STATE_MASK (0xF00U) +#define SNVS_HPSR_SSM_STATE_SHIFT (8U) +/*! SSM_STATE + * 0b0000..Init + * 0b0001..Hard Fail + * 0b0011..Soft Fail + * 0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) + * 0b1001..Check + * 0b1011..Non-Secure + * 0b1101..Trusted + * 0b1111..Secure + */ +#define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK) +#define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U) +#define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U) +/*! SECURITY_CONFIG + * 0b0000, 0b1000..FAB configuration + * 0b0001, 0b0010, 0b0011..OPEN configuration + * 0b1010, 0b1001, 0b1011..CLOSED configuration + * 0bx1xx..FIELD RETURN configuration + */ +#define SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK) +#define SNVS_HPSR_OTPMK_SYNDROME_MASK (0x1FF0000U) +#define SNVS_HPSR_OTPMK_SYNDROME_SHIFT (16U) +#define SNVS_HPSR_OTPMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_SYNDROME_SHIFT)) & SNVS_HPSR_OTPMK_SYNDROME_MASK) +#define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U) +#define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U) +/*! OTPMK_ZERO + * 0b0..The OTPMK is not zero. + * 0b1..The OTPMK is zero. + */ +#define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK) +#define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U) +#define SNVS_HPSR_ZMK_ZERO_SHIFT (31U) +/*! ZMK_ZERO + * 0b0..The ZMK is not zero. + * 0b1..The ZMK is zero. + */ +#define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK) +/*! @} */ + +/*! @name HPSVSR - SNVS_HP Security Violation Status Register */ +/*! @{ */ +#define SNVS_HPSVSR_SV0_MASK (0x1U) +#define SNVS_HPSVSR_SV0_SHIFT (0U) +/*! SV0 + * 0b0..No Security Violation 0 security violation was detected. + * 0b1..Security Violation 0 security violation was detected. + */ +#define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK) +#define SNVS_HPSVSR_SV1_MASK (0x2U) +#define SNVS_HPSVSR_SV1_SHIFT (1U) +/*! SV1 + * 0b0..No Security Violation 1 security violation was detected. + * 0b1..Security Violation 1 security violation was detected. + */ +#define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK) +#define SNVS_HPSVSR_SV2_MASK (0x4U) +#define SNVS_HPSVSR_SV2_SHIFT (2U) +/*! SV2 + * 0b0..No Security Violation 2 security violation was detected. + * 0b1..Security Violation 2 security violation was detected. + */ +#define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK) +#define SNVS_HPSVSR_SV3_MASK (0x8U) +#define SNVS_HPSVSR_SV3_SHIFT (3U) +/*! SV3 + * 0b0..No Security Violation 3 security violation was detected. + * 0b1..Security Violation 3 security violation was detected. + */ +#define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK) +#define SNVS_HPSVSR_SV4_MASK (0x10U) +#define SNVS_HPSVSR_SV4_SHIFT (4U) +/*! SV4 + * 0b0..No Security Violation 4 security violation was detected. + * 0b1..Security Violation 4 security violation was detected. + */ +#define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK) +#define SNVS_HPSVSR_SV5_MASK (0x20U) +#define SNVS_HPSVSR_SV5_SHIFT (5U) +/*! SV5 + * 0b0..No Security Violation 5 security violation was detected. + * 0b1..Security Violation 5 security violation was detected. + */ +#define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK) +#define SNVS_HPSVSR_SW_SV_MASK (0x2000U) +#define SNVS_HPSVSR_SW_SV_SHIFT (13U) +#define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK) +#define SNVS_HPSVSR_SW_FSV_MASK (0x4000U) +#define SNVS_HPSVSR_SW_FSV_SHIFT (14U) +#define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK) +#define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U) +#define SNVS_HPSVSR_SW_LPSV_SHIFT (15U) +#define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK) +#define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U) +#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U) +#define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK) +#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U) +#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U) +/*! ZMK_ECC_FAIL + * 0b0..ZMK ECC Failure was not detected. + * 0b1..ZMK ECC Failure was detected. + */ +#define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK) +#define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U) +#define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U) +#define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK) +/*! @} */ + +/*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */ +/*! @{ */ +#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU) +#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U) +#define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK) +/*! @} */ + +/*! @name HPHACR - SNVS_HP High Assurance Counter Register */ +/*! @{ */ +#define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU) +#define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U) +#define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK) +/*! @} */ + +/*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */ +/*! @{ */ +#define SNVS_HPRTCMR_RTC_MASK (0x7FFFU) +#define SNVS_HPRTCMR_RTC_SHIFT (0U) +#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) +/*! @} */ + +/*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */ +/*! @{ */ +#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) +#define SNVS_HPRTCLR_RTC_SHIFT (0U) +#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) +/*! @} */ + +/*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */ +/*! @{ */ +#define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU) +#define SNVS_HPTAMR_HPTA_MS_SHIFT (0U) +#define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK) +/*! @} */ + +/*! @name HPTALR - SNVS_HP Time Alarm LSB Register */ +/*! @{ */ +#define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU) +#define SNVS_HPTALR_HPTA_LS_SHIFT (0U) +#define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK) +/*! @} */ + +/*! @name LPLR - SNVS_LP Lock Register */ +/*! @{ */ +#define SNVS_LPLR_ZMK_WHL_MASK (0x1U) +#define SNVS_LPLR_ZMK_WHL_SHIFT (0U) +/*! ZMK_WHL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK) +#define SNVS_LPLR_ZMK_RHL_MASK (0x2U) +#define SNVS_LPLR_ZMK_RHL_SHIFT (1U) +/*! ZMK_RHL + * 0b0..Read access is allowed (only in software programming mode). + * 0b1..Read access is not allowed. + */ +#define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK) +#define SNVS_LPLR_SRTC_HL_MASK (0x4U) +#define SNVS_LPLR_SRTC_HL_SHIFT (2U) +/*! SRTC_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK) +#define SNVS_LPLR_LPCALB_HL_MASK (0x8U) +#define SNVS_LPLR_LPCALB_HL_SHIFT (3U) +/*! LPCALB_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK) +#define SNVS_LPLR_MC_HL_MASK (0x10U) +#define SNVS_LPLR_MC_HL_SHIFT (4U) +/*! MC_HL + * 0b0..Write access (increment) is allowed. + * 0b1..Write access (increment) is not allowed. + */ +#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK) +#define SNVS_LPLR_GPR_HL_MASK (0x20U) +#define SNVS_LPLR_GPR_HL_SHIFT (5U) +/*! GPR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK) +#define SNVS_LPLR_LPSVCR_HL_MASK (0x40U) +#define SNVS_LPLR_LPSVCR_HL_SHIFT (6U) +/*! LPSVCR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK) +#define SNVS_LPLR_LPTDCR_HL_MASK (0x100U) +#define SNVS_LPLR_LPTDCR_HL_SHIFT (8U) +/*! LPTDCR_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_LPTDCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTDCR_HL_SHIFT)) & SNVS_LPLR_LPTDCR_HL_MASK) +#define SNVS_LPLR_MKS_HL_MASK (0x200U) +#define SNVS_LPLR_MKS_HL_SHIFT (9U) +/*! MKS_HL + * 0b0..Write access is allowed. + * 0b1..Write access is not allowed. + */ +#define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK) +/*! @} */ + +/*! @name LPCR - SNVS_LP Control Register */ +/*! @{ */ +#define SNVS_LPCR_SRTC_ENV_MASK (0x1U) +#define SNVS_LPCR_SRTC_ENV_SHIFT (0U) +/*! SRTC_ENV + * 0b0..SRTC is disabled or invalid. + * 0b1..SRTC is enabled and valid. + */ +#define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK) +#define SNVS_LPCR_LPTA_EN_MASK (0x2U) +#define SNVS_LPCR_LPTA_EN_SHIFT (1U) +/*! LPTA_EN + * 0b0..LP time alarm interrupt is disabled. + * 0b1..LP time alarm interrupt is enabled. + */ +#define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK) +#define SNVS_LPCR_MC_ENV_MASK (0x4U) +#define SNVS_LPCR_MC_ENV_SHIFT (2U) +/*! MC_ENV + * 0b0..MC is disabled or invalid. + * 0b1..MC is enabled and valid. + */ +#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK) +#define SNVS_LPCR_LPWUI_EN_MASK (0x8U) +#define SNVS_LPCR_LPWUI_EN_SHIFT (3U) +#define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK) +#define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U) +#define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U) +/*! SRTC_INV_EN + * 0b0..SRTC stays valid in the case of security violation. + * 0b1..SRTC is invalidated in the case of security violation. + */ +#define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK) +#define SNVS_LPCR_DP_EN_MASK (0x20U) +#define SNVS_LPCR_DP_EN_SHIFT (5U) +/*! DP_EN + * 0b0..Smart PMIC enabled. + * 0b1..Dumb PMIC enabled. + */ +#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK) +#define SNVS_LPCR_TOP_MASK (0x40U) +#define SNVS_LPCR_TOP_SHIFT (6U) +/*! TOP + * 0b0..Leave system power on. + * 0b1..Turn off system power. + */ +#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK) +#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U) +#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U) +#define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK) +#define SNVS_LPCR_LPCALB_EN_MASK (0x100U) +#define SNVS_LPCR_LPCALB_EN_SHIFT (8U) +/*! LPCALB_EN + * 0b0..SRTC Time calibration is disabled. + * 0b1..SRTC Time calibration is enabled. + */ +#define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK) +#define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U) +#define SNVS_LPCR_LPCALB_VAL_SHIFT (10U) +/*! LPCALB_VAL + * 0b00000..+0 counts per each 32768 ticks of the counter clock + * 0b00001..+1 counts per each 32768 ticks of the counter clock + * 0b00010..+2 counts per each 32768 ticks of the counter clock + * 0b01111..+15 counts per each 32768 ticks of the counter clock + * 0b10000..-16 counts per each 32768 ticks of the counter clock + * 0b10001..-15 counts per each 32768 ticks of the counter clock + * 0b11110..-2 counts per each 32768 ticks of the counter clock + * 0b11111..-1 counts per each 32768 ticks of the counter clock + */ +#define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK) +#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U) +#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U) +#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK) +#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U) +#define SNVS_LPCR_DEBOUNCE_SHIFT (18U) +#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK) +#define SNVS_LPCR_ON_TIME_MASK (0x300000U) +#define SNVS_LPCR_ON_TIME_SHIFT (20U) +#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK) +#define SNVS_LPCR_PK_EN_MASK (0x400000U) +#define SNVS_LPCR_PK_EN_SHIFT (22U) +#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK) +#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U) +#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U) +#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK) +#define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U) +#define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U) +#define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK) +/*! @} */ + +/*! @name LPMKCR - SNVS_LP Master Key Control Register */ +/*! @{ */ +#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U) +#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U) +/*! MASTER_KEY_SEL + * 0b0x..Select one time programmable master key. + * 0b10..Select zeroizable master key when MKS_EN bit is set . + * 0b11..Select combined master key when MKS_EN bit is set . + */ +#define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK) +#define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U) +#define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U) +/*! ZMK_HWP + * 0b0..ZMK is in the software programming mode. + * 0b1..ZMK is in the hardware programming mode. + */ +#define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK) +#define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U) +#define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U) +/*! ZMK_VAL + * 0b0..ZMK is not valid. + * 0b1..ZMK is valid. + */ +#define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK) +#define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U) +#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U) +/*! ZMK_ECC_EN + * 0b0..ZMK ECC check is disabled. + * 0b1..ZMK ECC check is enabled. + */ +#define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK) +#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U) +#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U) +#define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK) +/*! @} */ + +/*! @name LPSVCR - SNVS_LP Security Violation Control Register */ +/*! @{ */ +#define SNVS_LPSVCR_SV0_EN_MASK (0x1U) +#define SNVS_LPSVCR_SV0_EN_SHIFT (0U) +/*! SV0_EN + * 0b0..Security Violation 0 is disabled in the LP domain. + * 0b1..Security Violation 0 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK) +#define SNVS_LPSVCR_SV1_EN_MASK (0x2U) +#define SNVS_LPSVCR_SV1_EN_SHIFT (1U) +/*! SV1_EN + * 0b0..Security Violation 1 is disabled in the LP domain. + * 0b1..Security Violation 1 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK) +#define SNVS_LPSVCR_SV2_EN_MASK (0x4U) +#define SNVS_LPSVCR_SV2_EN_SHIFT (2U) +/*! SV2_EN + * 0b0..Security Violation 2 is disabled in the LP domain. + * 0b1..Security Violation 2 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK) +#define SNVS_LPSVCR_SV3_EN_MASK (0x8U) +#define SNVS_LPSVCR_SV3_EN_SHIFT (3U) +/*! SV3_EN + * 0b0..Security Violation 3 is disabled in the LP domain. + * 0b1..Security Violation 3 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK) +#define SNVS_LPSVCR_SV4_EN_MASK (0x10U) +#define SNVS_LPSVCR_SV4_EN_SHIFT (4U) +/*! SV4_EN + * 0b0..Security Violation 4 is disabled in the LP domain. + * 0b1..Security Violation 4 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK) +#define SNVS_LPSVCR_SV5_EN_MASK (0x20U) +#define SNVS_LPSVCR_SV5_EN_SHIFT (5U) +/*! SV5_EN + * 0b0..Security Violation 5 is disabled in the LP domain. + * 0b1..Security Violation 5 is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK) +/*! @} */ + +/*! @name LPTDCR - SNVS_LP Tamper Detectors Configuration Register */ +/*! @{ */ +#define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U) +#define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U) +/*! SRTCR_EN + * 0b0..SRTC rollover is disabled. + * 0b1..SRTC rollover is enabled. + */ +#define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK) +#define SNVS_LPTDCR_MCR_EN_MASK (0x4U) +#define SNVS_LPTDCR_MCR_EN_SHIFT (2U) +/*! MCR_EN + * 0b0..MC rollover is disabled. + * 0b1..MC rollover is enabled. + */ +#define SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK) +#define SNVS_LPTDCR_ET1_EN_MASK (0x200U) +#define SNVS_LPTDCR_ET1_EN_SHIFT (9U) +/*! ET1_EN + * 0b0..External tamper 1 is disabled. + * 0b1..External tamper 1 is enabled. + */ +#define SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK) +#define SNVS_LPTDCR_ET1P_MASK (0x800U) +#define SNVS_LPTDCR_ET1P_SHIFT (11U) +/*! ET1P + * 0b0..External tamper 1 is active low. + * 0b1..External tamper 1 is active high. + */ +#define SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK) +#define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U) +#define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U) +#define SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK) +#define SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U) +#define SNVS_LPTDCR_POR_OBSERV_SHIFT (15U) +#define SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK) +#define SNVS_LPTDCR_OSCB_MASK (0x10000000U) +#define SNVS_LPTDCR_OSCB_SHIFT (28U) +/*! OSCB + * 0b0..Normal SRTC clock oscillator not bypassed. + * 0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source. + */ +#define SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK) +/*! @} */ + +/*! @name LPSR - SNVS_LP Status Register */ +/*! @{ */ +#define SNVS_LPSR_LPTA_MASK (0x1U) +#define SNVS_LPSR_LPTA_SHIFT (0U) +/*! LPTA + * 0b0..No time alarm interrupt occurred. + * 0b1..A time alarm interrupt occurred. + */ +#define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK) +#define SNVS_LPSR_SRTCR_MASK (0x2U) +#define SNVS_LPSR_SRTCR_SHIFT (1U) +/*! SRTCR + * 0b0..SRTC has not reached its maximum value. + * 0b1..SRTC has reached its maximum value. + */ +#define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK) +#define SNVS_LPSR_MCR_MASK (0x4U) +#define SNVS_LPSR_MCR_SHIFT (2U) +/*! MCR + * 0b0..MC has not reached its maximum value. + * 0b1..MC has reached its maximum value. + */ +#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK) +#define SNVS_LPSR_PGD_MASK (0x8U) +#define SNVS_LPSR_PGD_SHIFT (3U) +#define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK) +#define SNVS_LPSR_ET1D_MASK (0x200U) +#define SNVS_LPSR_ET1D_SHIFT (9U) +/*! ET1D + * 0b0..External tampering 1 not detected. + * 0b1..External tampering 1 detected. + */ +#define SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK) +#define SNVS_LPSR_ESVD_MASK (0x10000U) +#define SNVS_LPSR_ESVD_SHIFT (16U) +/*! ESVD + * 0b0..No external security violation. + * 0b1..External security violation is detected. + */ +#define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK) +#define SNVS_LPSR_EO_MASK (0x20000U) +#define SNVS_LPSR_EO_SHIFT (17U) +/*! EO + * 0b0..Emergency off was not detected. + * 0b1..Emergency off was detected. + */ +#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK) +#define SNVS_LPSR_SPO_MASK (0x40000U) +#define SNVS_LPSR_SPO_SHIFT (18U) +/*! SPO + * 0b0..Set Power Off was not detected. + * 0b1..Set Power Off was detected. + */ +#define SNVS_LPSR_SPO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPO_SHIFT)) & SNVS_LPSR_SPO_MASK) +#define SNVS_LPSR_SED_MASK (0x100000U) +#define SNVS_LPSR_SED_SHIFT (20U) +/*! SED + * 0b0..Scan exit was not detected. + * 0b1..Scan exit was detected. + */ +#define SNVS_LPSR_SED(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SED_SHIFT)) & SNVS_LPSR_SED_MASK) +#define SNVS_LPSR_LPNS_MASK (0x40000000U) +#define SNVS_LPSR_LPNS_SHIFT (30U) +/*! LPNS + * 0b0..LP section was not programmed in the non-secure state. + * 0b1..LP section was programmed in the non-secure state. + */ +#define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK) +#define SNVS_LPSR_LPS_MASK (0x80000000U) +#define SNVS_LPSR_LPS_SHIFT (31U) +/*! LPS + * 0b0..LP section was not programmed in secure or trusted state. + * 0b1..LP section was programmed in secure or trusted state. + */ +#define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK) +/*! @} */ + +/*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */ +/*! @{ */ +#define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU) +#define SNVS_LPSRTCMR_SRTC_SHIFT (0U) +#define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK) +/*! @} */ + +/*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */ +/*! @{ */ +#define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU) +#define SNVS_LPSRTCLR_SRTC_SHIFT (0U) +#define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK) +/*! @} */ + +/*! @name LPTAR - SNVS_LP Time Alarm Register */ +/*! @{ */ +#define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU) +#define SNVS_LPTAR_LPTA_SHIFT (0U) +#define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK) +/*! @} */ + +/*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */ +/*! @{ */ +#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) +#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) +#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) +#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) +#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) +/*! @} */ + +/*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */ +/*! @{ */ +#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) +#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) +#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) +/*! @} */ + +/*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */ +/*! @{ */ +#define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU) +#define SNVS_LPPGDR_PGD_SHIFT (0U) +#define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK) +/*! @} */ + +/*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */ +/*! @{ */ +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U) +#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK) +/*! @} */ + +/*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */ +/*! @{ */ +#define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU) +#define SNVS_LPZMKR_ZMK_SHIFT (0U) +#define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK) +/*! @} */ + +/* The count of SNVS_LPZMKR */ +#define SNVS_LPZMKR_COUNT (8U) + +/*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */ +/*! @{ */ +#define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U) +#define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK) +/*! @} */ + +/* The count of SNVS_LPGPR_ALIAS */ +#define SNVS_LPGPR_ALIAS_COUNT (4U) + +/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 7 */ +/*! @{ */ +#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) +#define SNVS_LPGPR_GPR_SHIFT (0U) +#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) +/*! @} */ + +/* The count of SNVS_LPGPR */ +#define SNVS_LPGPR_COUNT (8U) + +/*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */ +/*! @{ */ +#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) +#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) +#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) +#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U) +#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U) +#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK) +#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) +#define SNVS_HPVIDR1_IP_ID_SHIFT (16U) +#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) +/*! @} */ + +/*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */ +/*! @{ */ +#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU) +#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U) +#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK) +#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U) +#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U) +#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK) +#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U) +#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U) +#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK) +#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) +#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U) +#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SNVS_Register_Masks */ + + +/* SNVS - Peripheral instance base addresses */ +/** Peripheral SNVS base address */ +#define SNVS_BASE (0x400D4000u) +/** Peripheral SNVS base pointer */ +#define SNVS ((SNVS_Type *)SNVS_BASE) +/** Array initializer of SNVS peripheral base addresses */ +#define SNVS_BASE_ADDRS { SNVS_BASE } +/** Array initializer of SNVS peripheral base pointers */ +#define SNVS_BASE_PTRS { SNVS } +/** Interrupt vectors for the SNVS peripheral type */ +#define SNVS_IRQS { SNVS_LP_WRAPPER_IRQn } +#define SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn } +#define SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn } + +/*! + * @} + */ /* end of group SNVS_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPDIF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer + * @{ + */ + +/** SPDIF - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ + __IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */ + __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */ + __IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */ + union { /* offset: 0x10 */ + __O uint32_t SIC; /**< InterruptClear Register, offset: 0x10 */ + __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ + }; + __I uint32_t SRL; /**< SPDIFRxLeft Register, offset: 0x14 */ + __I uint32_t SRR; /**< SPDIFRxRight Register, offset: 0x18 */ + __I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register, offset: 0x1C */ + __I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register, offset: 0x20 */ + __I uint32_t SRU; /**< UchannelRx Register, offset: 0x24 */ + __I uint32_t SRQ; /**< QchannelRx Register, offset: 0x28 */ + __O uint32_t STL; /**< SPDIFTxLeft Register, offset: 0x2C */ + __O uint32_t STR; /**< SPDIFTxRight Register, offset: 0x30 */ + __IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */ + __IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */ + uint8_t RESERVED_0[8]; + __I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */ + uint8_t RESERVED_1[8]; + __IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */ +} SPDIF_Type; + +/* ---------------------------------------------------------------------------- + -- SPDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Register_Masks SPDIF Register Masks + * @{ + */ + +/*! @name SCR - SPDIF Configuration Register */ +/*! @{ */ +#define SPDIF_SCR_USRC_SEL_MASK (0x3U) +#define SPDIF_SCR_USRC_SEL_SHIFT (0U) +/*! USrc_Sel + * 0b00..No embedded U channel + * 0b01..U channel from SPDIF receive block (CD mode) + * 0b10..Reserved + * 0b11..U channel from on chip transmitter + */ +#define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK) +#define SPDIF_SCR_TXSEL_MASK (0x1CU) +#define SPDIF_SCR_TXSEL_SHIFT (2U) +/*! TxSel + * 0b000..Off and output 0 + * 0b001..Feed-through SPDIFIN + * 0b101..Tx Normal operation + */ +#define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK) +#define SPDIF_SCR_VALCTRL_MASK (0x20U) +#define SPDIF_SCR_VALCTRL_SHIFT (5U) +/*! ValCtrl + * 0b0..Outgoing Validity always set + * 0b1..Outgoing Validity always clear + */ +#define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK) +#define SPDIF_SCR_DMA_TX_EN_MASK (0x100U) +#define SPDIF_SCR_DMA_TX_EN_SHIFT (8U) +#define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK) +#define SPDIF_SCR_DMA_RX_EN_MASK (0x200U) +#define SPDIF_SCR_DMA_RX_EN_SHIFT (9U) +#define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK) +#define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U) +#define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U) +/*! TxFIFO_Ctrl + * 0b00..Send out digital zero on SPDIF Tx + * 0b01..Tx Normal operation + * 0b10..Reset to 1 sample remaining + * 0b11..Reserved + */ +#define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK) +#define SPDIF_SCR_SOFT_RESET_MASK (0x1000U) +#define SPDIF_SCR_SOFT_RESET_SHIFT (12U) +#define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK) +#define SPDIF_SCR_LOW_POWER_MASK (0x2000U) +#define SPDIF_SCR_LOW_POWER_SHIFT (13U) +#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) +#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U) +#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U) +/*! TxFIFOEmpty_Sel + * 0b00..Empty interrupt if 0 sample in Tx left and right FIFOs + * 0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs + * 0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs + * 0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs + */ +#define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) +#define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U) +#define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U) +/*! TxAutoSync + * 0b0..Tx FIFO auto sync off + * 0b1..Tx FIFO auto sync on + */ +#define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK) +#define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U) +#define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U) +/*! RxAutoSync + * 0b0..Rx FIFO auto sync off + * 0b1..RxFIFO auto sync on + */ +#define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK) +#define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U) +#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U) +/*! RxFIFOFull_Sel + * 0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs + * 0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs + * 0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs + * 0b11..Full interrupt if at least 16 sample in Rx left and right FIFO + */ +#define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK) +#define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U) +#define SPDIF_SCR_RXFIFO_RST_SHIFT (21U) +/*! RxFIFO_Rst + * 0b0..Normal operation + * 0b1..Reset register to 1 sample remaining + */ +#define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK) +#define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U) +#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U) +/*! RxFIFO_Off_On + * 0b0..SPDIF Rx FIFO is on + * 0b1..SPDIF Rx FIFO is off. Does not accept data from interface + */ +#define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK) +#define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U) +#define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U) +/*! RxFIFO_Ctrl + * 0b0..Normal operation + * 0b1..Always read zero from Rx data register + */ +#define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK) +/*! @} */ + +/*! @name SRCD - CDText Control Register */ +/*! @{ */ +#define SPDIF_SRCD_USYNCMODE_MASK (0x2U) +#define SPDIF_SRCD_USYNCMODE_SHIFT (1U) +/*! USyncMode + * 0b0..Non-CD data + * 0b1..CD user channel subcode + */ +#define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK) +/*! @} */ + +/*! @name SRPC - PhaseConfig Register */ +/*! @{ */ +#define SPDIF_SRPC_GAINSEL_MASK (0x38U) +#define SPDIF_SRPC_GAINSEL_SHIFT (3U) +/*! GainSel + * 0b000..24*(2**10) + * 0b001..16*(2**10) + * 0b010..12*(2**10) + * 0b011..8*(2**10) + * 0b100..6*(2**10) + * 0b101..4*(2**10) + * 0b110..3*(2**10) + */ +#define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK) +#define SPDIF_SRPC_LOCK_MASK (0x40U) +#define SPDIF_SRPC_LOCK_SHIFT (6U) +#define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK) +#define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U) +#define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U) +/*! ClkSrc_Sel + * 0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) + * 0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) + * 0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK + * 0b0101..REF_CLK_32K (XTALOSC) + * 0b0110..tx_clk (SPDIF0_CLK_ROOT) + * 0b1000..SPDIF_EXT_CLK + */ +#define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK) +/*! @} */ + +/*! @name SIE - InterruptEn Register */ +/*! @{ */ +#define SPDIF_SIE_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIE_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK) +#define SPDIF_SIE_TXEM_MASK (0x2U) +#define SPDIF_SIE_TXEM_SHIFT (1U) +#define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK) +#define SPDIF_SIE_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIE_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK) +#define SPDIF_SIE_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIE_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK) +#define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK) +#define SPDIF_SIE_UQERR_MASK (0x20U) +#define SPDIF_SIE_UQERR_SHIFT (5U) +#define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK) +#define SPDIF_SIE_UQSYNC_MASK (0x40U) +#define SPDIF_SIE_UQSYNC_SHIFT (6U) +#define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK) +#define SPDIF_SIE_QRXOV_MASK (0x80U) +#define SPDIF_SIE_QRXOV_SHIFT (7U) +#define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK) +#define SPDIF_SIE_QRXFUL_MASK (0x100U) +#define SPDIF_SIE_QRXFUL_SHIFT (8U) +#define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK) +#define SPDIF_SIE_URXOV_MASK (0x200U) +#define SPDIF_SIE_URXOV_SHIFT (9U) +#define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK) +#define SPDIF_SIE_URXFUL_MASK (0x400U) +#define SPDIF_SIE_URXFUL_SHIFT (10U) +#define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK) +#define SPDIF_SIE_BITERR_MASK (0x4000U) +#define SPDIF_SIE_BITERR_SHIFT (14U) +#define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK) +#define SPDIF_SIE_SYMERR_MASK (0x8000U) +#define SPDIF_SIE_SYMERR_SHIFT (15U) +#define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK) +#define SPDIF_SIE_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIE_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK) +#define SPDIF_SIE_CNEW_MASK (0x20000U) +#define SPDIF_SIE_CNEW_SHIFT (17U) +#define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK) +#define SPDIF_SIE_TXRESYN_MASK (0x40000U) +#define SPDIF_SIE_TXRESYN_SHIFT (18U) +#define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK) +#define SPDIF_SIE_TXUNOV_MASK (0x80000U) +#define SPDIF_SIE_TXUNOV_SHIFT (19U) +#define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK) +#define SPDIF_SIE_LOCK_MASK (0x100000U) +#define SPDIF_SIE_LOCK_SHIFT (20U) +#define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK) +/*! @} */ + +/*! @name SIC - InterruptClear Register */ +/*! @{ */ +#define SPDIF_SIC_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIC_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK) +#define SPDIF_SIC_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIC_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK) +#define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK) +#define SPDIF_SIC_UQERR_MASK (0x20U) +#define SPDIF_SIC_UQERR_SHIFT (5U) +#define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK) +#define SPDIF_SIC_UQSYNC_MASK (0x40U) +#define SPDIF_SIC_UQSYNC_SHIFT (6U) +#define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK) +#define SPDIF_SIC_QRXOV_MASK (0x80U) +#define SPDIF_SIC_QRXOV_SHIFT (7U) +#define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK) +#define SPDIF_SIC_URXOV_MASK (0x200U) +#define SPDIF_SIC_URXOV_SHIFT (9U) +#define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK) +#define SPDIF_SIC_BITERR_MASK (0x4000U) +#define SPDIF_SIC_BITERR_SHIFT (14U) +#define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK) +#define SPDIF_SIC_SYMERR_MASK (0x8000U) +#define SPDIF_SIC_SYMERR_SHIFT (15U) +#define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK) +#define SPDIF_SIC_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIC_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK) +#define SPDIF_SIC_CNEW_MASK (0x20000U) +#define SPDIF_SIC_CNEW_SHIFT (17U) +#define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK) +#define SPDIF_SIC_TXRESYN_MASK (0x40000U) +#define SPDIF_SIC_TXRESYN_SHIFT (18U) +#define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK) +#define SPDIF_SIC_TXUNOV_MASK (0x80000U) +#define SPDIF_SIC_TXUNOV_SHIFT (19U) +#define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK) +#define SPDIF_SIC_LOCK_MASK (0x100000U) +#define SPDIF_SIC_LOCK_SHIFT (20U) +#define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK) +/*! @} */ + +/*! @name SIS - InterruptStat Register */ +/*! @{ */ +#define SPDIF_SIS_RXFIFOFUL_MASK (0x1U) +#define SPDIF_SIS_RXFIFOFUL_SHIFT (0U) +#define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK) +#define SPDIF_SIS_TXEM_MASK (0x2U) +#define SPDIF_SIS_TXEM_SHIFT (1U) +#define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK) +#define SPDIF_SIS_LOCKLOSS_MASK (0x4U) +#define SPDIF_SIS_LOCKLOSS_SHIFT (2U) +#define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK) +#define SPDIF_SIS_RXFIFORESYN_MASK (0x8U) +#define SPDIF_SIS_RXFIFORESYN_SHIFT (3U) +#define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK) +#define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U) +#define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U) +#define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK) +#define SPDIF_SIS_UQERR_MASK (0x20U) +#define SPDIF_SIS_UQERR_SHIFT (5U) +#define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK) +#define SPDIF_SIS_UQSYNC_MASK (0x40U) +#define SPDIF_SIS_UQSYNC_SHIFT (6U) +#define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK) +#define SPDIF_SIS_QRXOV_MASK (0x80U) +#define SPDIF_SIS_QRXOV_SHIFT (7U) +#define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK) +#define SPDIF_SIS_QRXFUL_MASK (0x100U) +#define SPDIF_SIS_QRXFUL_SHIFT (8U) +#define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK) +#define SPDIF_SIS_URXOV_MASK (0x200U) +#define SPDIF_SIS_URXOV_SHIFT (9U) +#define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK) +#define SPDIF_SIS_URXFUL_MASK (0x400U) +#define SPDIF_SIS_URXFUL_SHIFT (10U) +#define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK) +#define SPDIF_SIS_BITERR_MASK (0x4000U) +#define SPDIF_SIS_BITERR_SHIFT (14U) +#define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK) +#define SPDIF_SIS_SYMERR_MASK (0x8000U) +#define SPDIF_SIS_SYMERR_SHIFT (15U) +#define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK) +#define SPDIF_SIS_VALNOGOOD_MASK (0x10000U) +#define SPDIF_SIS_VALNOGOOD_SHIFT (16U) +#define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK) +#define SPDIF_SIS_CNEW_MASK (0x20000U) +#define SPDIF_SIS_CNEW_SHIFT (17U) +#define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK) +#define SPDIF_SIS_TXRESYN_MASK (0x40000U) +#define SPDIF_SIS_TXRESYN_SHIFT (18U) +#define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK) +#define SPDIF_SIS_TXUNOV_MASK (0x80000U) +#define SPDIF_SIS_TXUNOV_SHIFT (19U) +#define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK) +#define SPDIF_SIS_LOCK_MASK (0x100000U) +#define SPDIF_SIS_LOCK_SHIFT (20U) +#define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK) +/*! @} */ + +/*! @name SRL - SPDIFRxLeft Register */ +/*! @{ */ +#define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_SRL_RXDATALEFT_SHIFT (0U) +#define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK) +/*! @} */ + +/*! @name SRR - SPDIFRxRight Register */ +/*! @{ */ +#define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_SRR_RXDATARIGHT_SHIFT (0U) +#define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK) +/*! @} */ + +/*! @name SRCSH - SPDIFRxCChannel_h Register */ +/*! @{ */ +#define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU) +#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U) +#define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK) +/*! @} */ + +/*! @name SRCSL - SPDIFRxCChannel_l Register */ +/*! @{ */ +#define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU) +#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U) +#define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK) +/*! @} */ + +/*! @name SRU - UchannelRx Register */ +/*! @{ */ +#define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRU_RXUCHANNEL_SHIFT (0U) +#define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK) +/*! @} */ + +/*! @name SRQ - QchannelRx Register */ +/*! @{ */ +#define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU) +#define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U) +#define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK) +/*! @} */ + +/*! @name STL - SPDIFTxLeft Register */ +/*! @{ */ +#define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU) +#define SPDIF_STL_TXDATALEFT_SHIFT (0U) +#define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK) +/*! @} */ + +/*! @name STR - SPDIFTxRight Register */ +/*! @{ */ +#define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU) +#define SPDIF_STR_TXDATARIGHT_SHIFT (0U) +#define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK) +/*! @} */ + +/*! @name STCSCH - SPDIFTxCChannelCons_h Register */ +/*! @{ */ +#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU) +#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U) +#define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK) +/*! @} */ + +/*! @name STCSCL - SPDIFTxCChannelCons_l Register */ +/*! @{ */ +#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU) +#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U) +#define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK) +/*! @} */ + +/*! @name SRFM - FreqMeas Register */ +/*! @{ */ +#define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU) +#define SPDIF_SRFM_FREQMEAS_SHIFT (0U) +#define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK) +/*! @} */ + +/*! @name STC - SPDIFTxClk Register */ +/*! @{ */ +#define SPDIF_STC_TXCLK_DF_MASK (0x7FU) +#define SPDIF_STC_TXCLK_DF_SHIFT (0U) +/*! TxClk_DF + * 0b0000000..divider factor is 1 + * 0b0000001..divider factor is 2 + * 0b1111111..divider factor is 128 + */ +#define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK) +#define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U) +#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U) +/*! tx_all_clk_en + * 0b0..disable transfer clock. + * 0b1..enable transfer clock. + */ +#define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK) +#define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U) +#define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U) +/*! TxClk_Source + * 0b000..XTALOSC input (XTALOSC clock) + * 0b001..tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) + * 0b010..tx_clk1 (from SAI1) + * 0b011..tx_clk2 SPDIF_EXT_CLK, from pads + * 0b100..tx_clk3 (from SAI2) + * 0b101..ipg_clk input (frequency divided) + * 0b110..tx_clk4 (from SAI3) + */ +#define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK) +#define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) +#define SPDIF_STC_SYSCLK_DF_SHIFT (11U) +/*! SYSCLK_DF + * 0b000000000..no clock signal + * 0b000000001..divider factor is 2 + * 0b111111111..divider factor is 512 + */ +#define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPDIF_Register_Masks */ + + +/* SPDIF - Peripheral instance base addresses */ +/** Peripheral SPDIF base address */ +#define SPDIF_BASE (0x40380000u) +/** Peripheral SPDIF base pointer */ +#define SPDIF ((SPDIF_Type *)SPDIF_BASE) +/** Array initializer of SPDIF peripheral base addresses */ +#define SPDIF_BASE_ADDRS { SPDIF_BASE } +/** Array initializer of SPDIF peripheral base pointers */ +#define SPDIF_BASE_PTRS { SPDIF } +/** Interrupt vectors for the SPDIF peripheral type */ +#define SPDIF_IRQS { SPDIF_IRQn } + +/*! + * @} + */ /* end of group SPDIF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer + * @{ + */ + +/** SRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ + __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x4 */ + __IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x8 */ + uint8_t RESERVED_0[16]; + __I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x1C */ + __IO uint32_t GPR[10]; /**< SRC General Purpose Register 1..SRC General Purpose Register 10, array offset: 0x20, array step: 0x4 */ +} SRC_Type; + +/* ---------------------------------------------------------------------------- + -- SRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Register_Masks SRC Register Masks + * @{ + */ + +/*! @name SCR - SRC Control Register */ +/*! @{ */ +#define SRC_SCR_MASK_WDOG_RST_MASK (0x780U) +#define SRC_SCR_MASK_WDOG_RST_SHIFT (7U) +/*! mask_wdog_rst + * 0b0101..wdog_rst_b is masked + * 0b1010..wdog_rst_b is not masked (default) + */ +#define SRC_SCR_MASK_WDOG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG_RST_SHIFT)) & SRC_SCR_MASK_WDOG_RST_MASK) +#define SRC_SCR_CORE0_RST_MASK (0x2000U) +#define SRC_SCR_CORE0_RST_SHIFT (13U) +/*! core0_rst + * 0b0..do not assert core0 reset + * 0b1..assert core0 reset + */ +#define SRC_SCR_CORE0_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_RST_SHIFT)) & SRC_SCR_CORE0_RST_MASK) +#define SRC_SCR_CORE0_DBG_RST_MASK (0x20000U) +#define SRC_SCR_CORE0_DBG_RST_SHIFT (17U) +/*! core0_dbg_rst + * 0b0..do not assert core0 debug reset + * 0b1..assert core0 debug reset + */ +#define SRC_SCR_CORE0_DBG_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_CORE0_DBG_RST_SHIFT)) & SRC_SCR_CORE0_DBG_RST_MASK) +#define SRC_SCR_DBG_RST_MSK_PG_MASK (0x2000000U) +#define SRC_SCR_DBG_RST_MSK_PG_SHIFT (25U) +/*! dbg_rst_msk_pg + * 0b0..do not mask core debug resets (debug resets will be asserted after power gating event) + * 0b1..mask core debug resets (debug resets won't be asserted after power gating event) + */ +#define SRC_SCR_DBG_RST_MSK_PG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DBG_RST_MSK_PG_SHIFT)) & SRC_SCR_DBG_RST_MSK_PG_MASK) +#define SRC_SCR_MASK_WDOG3_RST_MASK (0xF0000000U) +#define SRC_SCR_MASK_WDOG3_RST_SHIFT (28U) +/*! mask_wdog3_rst + * 0b0101..wdog3_rst_b is masked + * 0b1010..wdog3_rst_b is not masked + */ +#define SRC_SCR_MASK_WDOG3_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_WDOG3_RST_SHIFT)) & SRC_SCR_MASK_WDOG3_RST_MASK) +/*! @} */ + +/*! @name SBMR1 - SRC Boot Mode Register 1 */ +/*! @{ */ +#define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU) +#define SRC_SBMR1_BOOT_CFG1_SHIFT (0U) +#define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK) +#define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U) +#define SRC_SBMR1_BOOT_CFG2_SHIFT (8U) +#define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK) +#define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U) +#define SRC_SBMR1_BOOT_CFG3_SHIFT (16U) +#define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK) +#define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U) +#define SRC_SBMR1_BOOT_CFG4_SHIFT (24U) +#define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK) +/*! @} */ + +/*! @name SRSR - SRC Reset Status Register */ +/*! @{ */ +#define SRC_SRSR_IPP_RESET_B_MASK (0x1U) +#define SRC_SRSR_IPP_RESET_B_SHIFT (0U) +/*! ipp_reset_b + * 0b0..Reset is not a result of ipp_reset_b pin. + * 0b1..Reset is a result of ipp_reset_b pin. + */ +#define SRC_SRSR_IPP_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_SHIFT)) & SRC_SRSR_IPP_RESET_B_MASK) +#define SRC_SRSR_LOCKUP_SYSRESETREQ_MASK (0x2U) +#define SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT (1U) +/*! lockup_sysresetreq + * 0b0..Reset is not a result of the mentioned case. + * 0b1..Reset is a result of the mentioned case. + */ +#define SRC_SRSR_LOCKUP_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_LOCKUP_SYSRESETREQ_SHIFT)) & SRC_SRSR_LOCKUP_SYSRESETREQ_MASK) +#define SRC_SRSR_CSU_RESET_B_MASK (0x4U) +#define SRC_SRSR_CSU_RESET_B_SHIFT (2U) +/*! csu_reset_b + * 0b0..Reset is not a result of the csu_reset_b event. + * 0b1..Reset is a result of the csu_reset_b event. + */ +#define SRC_SRSR_CSU_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_SHIFT)) & SRC_SRSR_CSU_RESET_B_MASK) +#define SRC_SRSR_IPP_USER_RESET_B_MASK (0x8U) +#define SRC_SRSR_IPP_USER_RESET_B_SHIFT (3U) +/*! ipp_user_reset_b + * 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. + * 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event. + */ +#define SRC_SRSR_IPP_USER_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_MASK) +#define SRC_SRSR_WDOG_RST_B_MASK (0x10U) +#define SRC_SRSR_WDOG_RST_B_SHIFT (4U) +/*! wdog_rst_b + * 0b0..Reset is not a result of the watchdog time-out event. + * 0b1..Reset is a result of the watchdog time-out event. + */ +#define SRC_SRSR_WDOG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_SHIFT)) & SRC_SRSR_WDOG_RST_B_MASK) +#define SRC_SRSR_JTAG_RST_B_MASK (0x20U) +#define SRC_SRSR_JTAG_RST_B_SHIFT (5U) +/*! jtag_rst_b + * 0b0..Reset is not a result of HIGH-Z reset from JTAG. + * 0b1..Reset is a result of HIGH-Z reset from JTAG. + */ +#define SRC_SRSR_JTAG_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_SHIFT)) & SRC_SRSR_JTAG_RST_B_MASK) +#define SRC_SRSR_JTAG_SW_RST_MASK (0x40U) +#define SRC_SRSR_JTAG_SW_RST_SHIFT (6U) +/*! jtag_sw_rst + * 0b0..Reset is not a result of software reset from JTAG. + * 0b1..Reset is a result of software reset from JTAG. + */ +#define SRC_SRSR_JTAG_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_SHIFT)) & SRC_SRSR_JTAG_SW_RST_MASK) +#define SRC_SRSR_WDOG3_RST_B_MASK (0x80U) +#define SRC_SRSR_WDOG3_RST_B_SHIFT (7U) +/*! wdog3_rst_b + * 0b0..Reset is not a result of the watchdog3 time-out event. + * 0b1..Reset is a result of the watchdog3 time-out event. + */ +#define SRC_SRSR_WDOG3_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_SHIFT)) & SRC_SRSR_WDOG3_RST_B_MASK) +#define SRC_SRSR_TEMPSENSE_RST_B_MASK (0x100U) +#define SRC_SRSR_TEMPSENSE_RST_B_SHIFT (8U) +/*! tempsense_rst_b + * 0b0..Reset is not a result of software reset from Temperature Sensor. + * 0b1..Reset is a result of software reset from Temperature Sensor. + */ +#define SRC_SRSR_TEMPSENSE_RST_B(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_MASK) +/*! @} */ + +/*! @name SBMR2 - SRC Boot Mode Register 2 */ +/*! @{ */ +#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U) +#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U) +#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) +#define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U) +#define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U) +#define SRC_SBMR2_DIR_BT_DIS(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK) +#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U) +#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U) +#define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK) +#define SRC_SBMR2_BMOD_MASK (0x3000000U) +#define SRC_SBMR2_BMOD_SHIFT (24U) +#define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK) +/*! @} */ + +/*! @name GPR - SRC General Purpose Register 1..SRC General Purpose Register 10 */ +/*! @{ */ +#define SRC_GPR_PERSISTENT_ARG0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ARG0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ARG0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ARG0_SHIFT)) & SRC_GPR_PERSISTENT_ARG0_MASK) +#define SRC_GPR_PERSISTENT_ENTRY0_MASK (0xFFFFFFFFU) +#define SRC_GPR_PERSISTENT_ENTRY0_SHIFT (0U) +#define SRC_GPR_PERSISTENT_ENTRY0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_PERSISTENT_ENTRY0_SHIFT)) & SRC_GPR_PERSISTENT_ENTRY0_MASK) +/*! @} */ + +/* The count of SRC_GPR */ +#define SRC_GPR_COUNT (10U) + + +/*! + * @} + */ /* end of group SRC_Register_Masks */ + + +/* SRC - Peripheral instance base addresses */ +/** Peripheral SRC base address */ +#define SRC_BASE (0x400F8000u) +/** Peripheral SRC base pointer */ +#define SRC ((SRC_Type *)SRC_BASE) +/** Array initializer of SRC peripheral base addresses */ +#define SRC_BASE_ADDRS { SRC_BASE } +/** Array initializer of SRC peripheral base pointers */ +#define SRC_BASE_PTRS { SRC } +/** Interrupt vectors for the SRC peripheral type */ +#define SRC_IRQS { SRC_IRQn } +/* Backward compatibility */ +#define SRC_SCR_MWDR_MASK SRC_SCR_MASK_WDOG_RST_MASK +#define SRC_SCR_MWDR_SHIFT SRC_SCR_MASK_WDOG_RST_SHIFT +#define SRC_SCR_MWDR(x) SRC_SCR_MASK_WDOG_RST(x) +#define SRC_SRSR_WDOG_MASK SRC_SRSR_WDOG_RST_B_MASK +#define SRC_SRSR_WDOG_SHIFT SRC_SRSR_WDOG_RST_B_SHIFT +#define SRC_SRSR_WDOG(x) SRC_SRSR_WDOG_RST_B(x) +#define SRC_SRSR_JTAG_MASK SRC_SRSR_JTAG_RST_B_MASK +#define SRC_SRSR_JTAG_SHIFT SRC_SRSR_JTAG_RST_B_SHIFT +#define SRC_SRSR_JTAG(x) SRC_SRSR_JTAG_RST_B(x) +#define SRC_SRSR_SJC_MASK SRC_SRSR_JTAG_SW_RST_MASK +#define SRC_SRSR_SJC_SHIFT SRC_SRSR_JTAG_SW_RST_SHIFT +#define SRC_SRSR_SJC(x) SRC_SRSR_JTAG_SW_RST(x) +#define SRC_SRSR_TSR_MASK SRC_SRSR_TEMPSENSE_RST_B_MASK +#define SRC_SRSR_TSR_SHIFT SRC_SRSR_TEMPSENSE_RST_B_SHIFT +#define SRC_SRSR_TSR(x) SRC_SRSR_TEMPSENSE_RST_B(x) +/* Extra definition */ +#define SRC_SRSR_W1C_BITS_MASK ( SRC_SRSR_WDOG3_RST_B_MASK \ + | SRC_SRSR_JTAG_SW_RST_MASK \ + | SRC_SRSR_JTAG_RST_B_MASK \ + | SRC_SRSR_WDOG_RST_B_MASK \ + | SRC_SRSR_IPP_USER_RESET_B_MASK \ + | SRC_SRSR_CSU_RESET_B_MASK \ + | SRC_SRSR_LOCKUP_SYSRESETREQ_MASK \ + | SRC_SRSR_IPP_RESET_B_MASK) + + +/*! + * @} + */ /* end of group SRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TEMPMON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Peripheral_Access_Layer TEMPMON Peripheral Access Layer + * @{ + */ + +/** TEMPMON - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[384]; + __IO uint32_t TEMPSENSE0; /**< Tempsensor Control Register 0, offset: 0x180 */ + __IO uint32_t TEMPSENSE0_SET; /**< Tempsensor Control Register 0, offset: 0x184 */ + __IO uint32_t TEMPSENSE0_CLR; /**< Tempsensor Control Register 0, offset: 0x188 */ + __IO uint32_t TEMPSENSE0_TOG; /**< Tempsensor Control Register 0, offset: 0x18C */ + __IO uint32_t TEMPSENSE1; /**< Tempsensor Control Register 1, offset: 0x190 */ + __IO uint32_t TEMPSENSE1_SET; /**< Tempsensor Control Register 1, offset: 0x194 */ + __IO uint32_t TEMPSENSE1_CLR; /**< Tempsensor Control Register 1, offset: 0x198 */ + __IO uint32_t TEMPSENSE1_TOG; /**< Tempsensor Control Register 1, offset: 0x19C */ + uint8_t RESERVED_1[240]; + __IO uint32_t TEMPSENSE2; /**< Tempsensor Control Register 2, offset: 0x290 */ + __IO uint32_t TEMPSENSE2_SET; /**< Tempsensor Control Register 2, offset: 0x294 */ + __IO uint32_t TEMPSENSE2_CLR; /**< Tempsensor Control Register 2, offset: 0x298 */ + __IO uint32_t TEMPSENSE2_TOG; /**< Tempsensor Control Register 2, offset: 0x29C */ +} TEMPMON_Type; + +/* ---------------------------------------------------------------------------- + -- TEMPMON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks + * @{ + */ + +/*! @name TEMPSENSE0 - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ +#define TEMPMON_TEMPSENSE0_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ +#define TEMPMON_TEMPSENSE0_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE0_SET - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ +#define TEMPMON_TEMPSENSE0_SET_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_SET_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ +#define TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_SET_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_SET_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ +#define TEMPMON_TEMPSENSE0_SET_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_SET_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_SET_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_SET_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_SET_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_SET_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE0_CLR - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ +#define TEMPMON_TEMPSENSE0_CLR_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ +#define TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ +#define TEMPMON_TEMPSENSE0_CLR_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_CLR_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_CLR_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE0_TOG - Tempsensor Control Register 0 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK (0x1U) +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT (0U) +/*! POWER_DOWN + * 0b0..Enable power to the temperature sensor. + * 0b1..Power down the temperature sensor. + */ +#define TEMPMON_TEMPSENSE0_TOG_POWER_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_POWER_DOWN_MASK) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK (0x2U) +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT (1U) +/*! MEASURE_TEMP + * 0b0..Do not start the measurement process. + * 0b1..Start the measurement process. + */ +#define TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_MEASURE_TEMP_MASK) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK (0x4U) +#define TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT (2U) +/*! FINISHED + * 0b0..Last measurement is not ready yet. + * 0b1..Last measurement is valid. + */ +#define TEMPMON_TEMPSENSE0_TOG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_FINISHED_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_FINISHED_MASK) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK (0xFFF00U) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT (8U) +#define TEMPMON_TEMPSENSE0_TOG_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_TEMP_CNT_MASK) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK (0xFFF00000U) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT (20U) +#define TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE0_TOG_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE1 - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE1_SET - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_SET_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE1_CLR - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE1_TOG - Tempsensor Control Register 1 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK (0xFFFFU) +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT (0U) +#define TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT)) & TEMPMON_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) +/*! @} */ + +/*! @name TEMPSENSE2 - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE2_SET - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_SET_PANIC_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE2_CLR - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_CLR_PANIC_ALARM_VALUE_MASK) +/*! @} */ + +/*! @name TEMPSENSE2_TOG - Tempsensor Control Register 2 */ +/*! @{ */ +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK (0xFFFU) +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT (0U) +#define TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_LOW_ALARM_VALUE_MASK) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK (0xFFF0000U) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT (16U) +#define TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_SHIFT)) & TEMPMON_TEMPSENSE2_TOG_PANIC_ALARM_VALUE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TEMPMON_Register_Masks */ + + +/* TEMPMON - Peripheral instance base addresses */ +/** Peripheral TEMPMON base address */ +#define TEMPMON_BASE (0x400D8000u) +/** Peripheral TEMPMON base pointer */ +#define TEMPMON ((TEMPMON_Type *)TEMPMON_BASE) +/** Array initializer of TEMPMON peripheral base addresses */ +#define TEMPMON_BASE_ADDRS { TEMPMON_BASE } +/** Array initializer of TEMPMON peripheral base pointers */ +#define TEMPMON_BASE_PTRS { TEMPMON } + +/*! + * @} + */ /* end of group TEMPMON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TMR_Peripheral_Access_Layer TMR Peripheral Access Layer + * @{ + */ + +/** TMR - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x20 */ + __IO uint16_t COMP1; /**< Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20 */ + __IO uint16_t COMP2; /**< Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20 */ + __IO uint16_t CAPT; /**< Timer Channel Capture Register, array offset: 0x4, array step: 0x20 */ + __IO uint16_t LOAD; /**< Timer Channel Load Register, array offset: 0x6, array step: 0x20 */ + __IO uint16_t HOLD; /**< Timer Channel Hold Register, array offset: 0x8, array step: 0x20 */ + __IO uint16_t CNTR; /**< Timer Channel Counter Register, array offset: 0xA, array step: 0x20 */ + __IO uint16_t CTRL; /**< Timer Channel Control Register, array offset: 0xC, array step: 0x20 */ + __IO uint16_t SCTRL; /**< Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20 */ + __IO uint16_t CMPLD1; /**< Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20 */ + __IO uint16_t CMPLD2; /**< Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20 */ + __IO uint16_t CSCTRL; /**< Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20 */ + __IO uint16_t FILT; /**< Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20 */ + __IO uint16_t DMA; /**< Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20 */ + uint8_t RESERVED_0[4]; + __IO uint16_t ENBL; /**< Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances */ + } CHANNEL[4]; +} TMR_Type; + +/* ---------------------------------------------------------------------------- + -- TMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TMR_Register_Masks TMR Register Masks + * @{ + */ + +/*! @name COMP1 - Timer Channel Compare Register 1 */ +/*! @{ */ +#define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU) +#define TMR_COMP1_COMPARISON_1_SHIFT (0U) +#define TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK) +/*! @} */ + +/* The count of TMR_COMP1 */ +#define TMR_COMP1_COUNT (4U) + +/*! @name COMP2 - Timer Channel Compare Register 2 */ +/*! @{ */ +#define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU) +#define TMR_COMP2_COMPARISON_2_SHIFT (0U) +#define TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK) +/*! @} */ + +/* The count of TMR_COMP2 */ +#define TMR_COMP2_COUNT (4U) + +/*! @name CAPT - Timer Channel Capture Register */ +/*! @{ */ +#define TMR_CAPT_CAPTURE_MASK (0xFFFFU) +#define TMR_CAPT_CAPTURE_SHIFT (0U) +#define TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK) +/*! @} */ + +/* The count of TMR_CAPT */ +#define TMR_CAPT_COUNT (4U) + +/*! @name LOAD - Timer Channel Load Register */ +/*! @{ */ +#define TMR_LOAD_LOAD_MASK (0xFFFFU) +#define TMR_LOAD_LOAD_SHIFT (0U) +#define TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK) +/*! @} */ + +/* The count of TMR_LOAD */ +#define TMR_LOAD_COUNT (4U) + +/*! @name HOLD - Timer Channel Hold Register */ +/*! @{ */ +#define TMR_HOLD_HOLD_MASK (0xFFFFU) +#define TMR_HOLD_HOLD_SHIFT (0U) +#define TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK) +/*! @} */ + +/* The count of TMR_HOLD */ +#define TMR_HOLD_COUNT (4U) + +/*! @name CNTR - Timer Channel Counter Register */ +/*! @{ */ +#define TMR_CNTR_COUNTER_MASK (0xFFFFU) +#define TMR_CNTR_COUNTER_SHIFT (0U) +#define TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK) +/*! @} */ + +/* The count of TMR_CNTR */ +#define TMR_CNTR_COUNT (4U) + +/*! @name CTRL - Timer Channel Control Register */ +/*! @{ */ +#define TMR_CTRL_OUTMODE_MASK (0x7U) +#define TMR_CTRL_OUTMODE_SHIFT (0U) +/*! OUTMODE - Output Mode + * 0b000..Asserted while counter is active + * 0b001..Clear OFLAG output on successful compare + * 0b010..Set OFLAG output on successful compare + * 0b011..Toggle OFLAG output on successful compare + * 0b100..Toggle OFLAG output using alternating compare registers + * 0b101..Set on compare, cleared on secondary source input edge + * 0b110..Set on compare, cleared on counter rollover + * 0b111..Enable gated clock output while counter is active + */ +#define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK) +#define TMR_CTRL_COINIT_MASK (0x8U) +#define TMR_CTRL_COINIT_SHIFT (3U) +/*! COINIT - Co-Channel Initialization + * 0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer + * 0b1..Co-channel counter/timers may force a re-initialization of this counter/timer + */ +#define TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK) +#define TMR_CTRL_DIR_MASK (0x10U) +#define TMR_CTRL_DIR_SHIFT (4U) +/*! DIR - Count Direction + * 0b0..Count up. + * 0b1..Count down. + */ +#define TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK) +#define TMR_CTRL_LENGTH_MASK (0x20U) +#define TMR_CTRL_LENGTH_SHIFT (5U) +/*! LENGTH - Count Length + * 0b0..Count until roll over at $FFFF and continue from $0000. + * 0b1..Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter + * reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. + * When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful + * comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 + * value is reached, re-initializes, counts until COMP1 value is reached, and so on. + */ +#define TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK) +#define TMR_CTRL_ONCE_MASK (0x40U) +#define TMR_CTRL_ONCE_SHIFT (6U) +/*! ONCE - Count Once + * 0b0..Count repeatedly. + * 0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a + * COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When + * output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to + * the COMP2 value, and then stops. + */ +#define TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK) +#define TMR_CTRL_SCS_MASK (0x180U) +#define TMR_CTRL_SCS_SHIFT (7U) +/*! SCS - Secondary Count Source + * 0b00..Counter 0 input pin + * 0b01..Counter 1 input pin + * 0b10..Counter 2 input pin + * 0b11..Counter 3 input pin + */ +#define TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK) +#define TMR_CTRL_PCS_MASK (0x1E00U) +#define TMR_CTRL_PCS_SHIFT (9U) +/*! PCS - Primary Count Source + * 0b0000..Counter 0 input pin + * 0b0001..Counter 1 input pin + * 0b0010..Counter 2 input pin + * 0b0011..Counter 3 input pin + * 0b0100..Counter 0 output + * 0b0101..Counter 1 output + * 0b0110..Counter 2 output + * 0b0111..Counter 3 output + * 0b1000..IP bus clock divide by 1 prescaler + * 0b1001..IP bus clock divide by 2 prescaler + * 0b1010..IP bus clock divide by 4 prescaler + * 0b1011..IP bus clock divide by 8 prescaler + * 0b1100..IP bus clock divide by 16 prescaler + * 0b1101..IP bus clock divide by 32 prescaler + * 0b1110..IP bus clock divide by 64 prescaler + * 0b1111..IP bus clock divide by 128 prescaler + */ +#define TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK) +#define TMR_CTRL_CM_MASK (0xE000U) +#define TMR_CTRL_CM_SHIFT (13U) +/*! CM - Count Mode + * 0b000..No operation + * 0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges + * are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising + * edges are counted regardless of the value of SCTRL[IPS]. + * 0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. + * 0b011..Count rising edges of primary source while secondary input high active + * 0b100..Quadrature count mode, uses primary and secondary sources + * 0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only + * when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. + * 0b110..Edge of secondary source triggers primary count until compare + * 0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs. + */ +#define TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK) +/*! @} */ + +/* The count of TMR_CTRL */ +#define TMR_CTRL_COUNT (4U) + +/*! @name SCTRL - Timer Channel Status and Control Register */ +/*! @{ */ +#define TMR_SCTRL_OEN_MASK (0x1U) +#define TMR_SCTRL_OEN_SHIFT (0U) +/*! OEN - Output Enable + * 0b0..The external pin is configured as an input. + * 0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as + * their input see the driven value. The polarity of the signal is determined by OPS. + */ +#define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK) +#define TMR_SCTRL_OPS_MASK (0x2U) +#define TMR_SCTRL_OPS_SHIFT (1U) +/*! OPS - Output Polarity Select + * 0b0..True polarity. + * 0b1..Inverted polarity. + */ +#define TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK) +#define TMR_SCTRL_FORCE_MASK (0x4U) +#define TMR_SCTRL_FORCE_SHIFT (2U) +#define TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK) +#define TMR_SCTRL_VAL_MASK (0x8U) +#define TMR_SCTRL_VAL_SHIFT (3U) +#define TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK) +#define TMR_SCTRL_EEOF_MASK (0x10U) +#define TMR_SCTRL_EEOF_SHIFT (4U) +#define TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK) +#define TMR_SCTRL_MSTR_MASK (0x20U) +#define TMR_SCTRL_MSTR_SHIFT (5U) +#define TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK) +#define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U) +#define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U) +/*! CAPTURE_MODE - Input Capture Mode + * 0b00..Capture function is disabled + * 0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input + * 0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input + * 0b11..Load capture register on both edges of input + */ +#define TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK) +#define TMR_SCTRL_INPUT_MASK (0x100U) +#define TMR_SCTRL_INPUT_SHIFT (8U) +#define TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK) +#define TMR_SCTRL_IPS_MASK (0x200U) +#define TMR_SCTRL_IPS_SHIFT (9U) +#define TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK) +#define TMR_SCTRL_IEFIE_MASK (0x400U) +#define TMR_SCTRL_IEFIE_SHIFT (10U) +#define TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK) +#define TMR_SCTRL_IEF_MASK (0x800U) +#define TMR_SCTRL_IEF_SHIFT (11U) +#define TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK) +#define TMR_SCTRL_TOFIE_MASK (0x1000U) +#define TMR_SCTRL_TOFIE_SHIFT (12U) +#define TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK) +#define TMR_SCTRL_TOF_MASK (0x2000U) +#define TMR_SCTRL_TOF_SHIFT (13U) +#define TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK) +#define TMR_SCTRL_TCFIE_MASK (0x4000U) +#define TMR_SCTRL_TCFIE_SHIFT (14U) +#define TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK) +#define TMR_SCTRL_TCF_MASK (0x8000U) +#define TMR_SCTRL_TCF_SHIFT (15U) +#define TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK) +/*! @} */ + +/* The count of TMR_SCTRL */ +#define TMR_SCTRL_COUNT (4U) + +/*! @name CMPLD1 - Timer Channel Comparator Load Register 1 */ +/*! @{ */ +#define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU) +#define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U) +#define TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK) +/*! @} */ + +/* The count of TMR_CMPLD1 */ +#define TMR_CMPLD1_COUNT (4U) + +/*! @name CMPLD2 - Timer Channel Comparator Load Register 2 */ +/*! @{ */ +#define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU) +#define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U) +#define TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK) +/*! @} */ + +/* The count of TMR_CMPLD2 */ +#define TMR_CMPLD2_COUNT (4U) + +/*! @name CSCTRL - Timer Channel Comparator Status and Control Register */ +/*! @{ */ +#define TMR_CSCTRL_CL1_MASK (0x3U) +#define TMR_CSCTRL_CL1_SHIFT (0U) +/*! CL1 - Compare Load Control 1 + * 0b00..Never preload + * 0b01..Load upon successful compare with the value in COMP1 + * 0b10..Load upon successful compare with the value in COMP2 + * 0b11..Reserved + */ +#define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK) +#define TMR_CSCTRL_CL2_MASK (0xCU) +#define TMR_CSCTRL_CL2_SHIFT (2U) +/*! CL2 - Compare Load Control 2 + * 0b00..Never preload + * 0b01..Load upon successful compare with the value in COMP1 + * 0b10..Load upon successful compare with the value in COMP2 + * 0b11..Reserved + */ +#define TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK) +#define TMR_CSCTRL_TCF1_MASK (0x10U) +#define TMR_CSCTRL_TCF1_SHIFT (4U) +#define TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK) +#define TMR_CSCTRL_TCF2_MASK (0x20U) +#define TMR_CSCTRL_TCF2_SHIFT (5U) +#define TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK) +#define TMR_CSCTRL_TCF1EN_MASK (0x40U) +#define TMR_CSCTRL_TCF1EN_SHIFT (6U) +#define TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK) +#define TMR_CSCTRL_TCF2EN_MASK (0x80U) +#define TMR_CSCTRL_TCF2EN_SHIFT (7U) +#define TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK) +#define TMR_CSCTRL_UP_MASK (0x200U) +#define TMR_CSCTRL_UP_SHIFT (9U) +/*! UP - Counting Direction Indicator + * 0b0..The last count was in the DOWN direction. + * 0b1..The last count was in the UP direction. + */ +#define TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK) +#define TMR_CSCTRL_TCI_MASK (0x400U) +#define TMR_CSCTRL_TCI_SHIFT (10U) +/*! TCI - Triggered Count Initialization Control + * 0b0..Stop counter upon receiving a second trigger event while still counting from the first trigger event. + * 0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event. + */ +#define TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK) +#define TMR_CSCTRL_ROC_MASK (0x800U) +#define TMR_CSCTRL_ROC_SHIFT (11U) +/*! ROC - Reload on Capture + * 0b0..Do not reload the counter on a capture event. + * 0b1..Reload the counter on a capture event. + */ +#define TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK) +#define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U) +#define TMR_CSCTRL_ALT_LOAD_SHIFT (12U) +/*! ALT_LOAD - Alternative Load Enable + * 0b0..Counter can be re-initialized only with the LOAD register. + * 0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction. + */ +#define TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK) +#define TMR_CSCTRL_FAULT_MASK (0x2000U) +#define TMR_CSCTRL_FAULT_SHIFT (13U) +/*! FAULT - Fault Enable + * 0b0..Fault function disabled. + * 0b1..Fault function enabled. + */ +#define TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK) +#define TMR_CSCTRL_DBG_EN_MASK (0xC000U) +#define TMR_CSCTRL_DBG_EN_SHIFT (14U) +/*! DBG_EN - Debug Actions Enable + * 0b00..Continue with normal operation during debug mode. (default) + * 0b01..Halt TMR counter during debug mode. + * 0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). + * 0b11..Both halt counter and force output to 0 during debug mode. + */ +#define TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK) +/*! @} */ + +/* The count of TMR_CSCTRL */ +#define TMR_CSCTRL_COUNT (4U) + +/*! @name FILT - Timer Channel Input Filter Register */ +/*! @{ */ +#define TMR_FILT_FILT_PER_MASK (0xFFU) +#define TMR_FILT_FILT_PER_SHIFT (0U) +#define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK) +#define TMR_FILT_FILT_CNT_MASK (0x700U) +#define TMR_FILT_FILT_CNT_SHIFT (8U) +#define TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK) +/*! @} */ + +/* The count of TMR_FILT */ +#define TMR_FILT_COUNT (4U) + +/*! @name DMA - Timer Channel DMA Enable Register */ +/*! @{ */ +#define TMR_DMA_IEFDE_MASK (0x1U) +#define TMR_DMA_IEFDE_SHIFT (0U) +#define TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK) +#define TMR_DMA_CMPLD1DE_MASK (0x2U) +#define TMR_DMA_CMPLD1DE_SHIFT (1U) +#define TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK) +#define TMR_DMA_CMPLD2DE_MASK (0x4U) +#define TMR_DMA_CMPLD2DE_SHIFT (2U) +#define TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK) +/*! @} */ + +/* The count of TMR_DMA */ +#define TMR_DMA_COUNT (4U) + +/*! @name ENBL - Timer Channel Enable Register */ +/*! @{ */ +#define TMR_ENBL_ENBL_MASK (0xFU) +#define TMR_ENBL_ENBL_SHIFT (0U) +/*! ENBL - Timer Channel Enable + * 0b0000..Timer channel is disabled. + * 0b0001..Timer channel is enabled. (default) + */ +#define TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK) +/*! @} */ + +/* The count of TMR_ENBL */ +#define TMR_ENBL_COUNT (4U) + + +/*! + * @} + */ /* end of group TMR_Register_Masks */ + + +/* TMR - Peripheral instance base addresses */ +/** Peripheral TMR1 base address */ +#define TMR1_BASE (0x401DC000u) +/** Peripheral TMR1 base pointer */ +#define TMR1 ((TMR_Type *)TMR1_BASE) +/** Peripheral TMR2 base address */ +#define TMR2_BASE (0x401E0000u) +/** Peripheral TMR2 base pointer */ +#define TMR2 ((TMR_Type *)TMR2_BASE) +/** Peripheral TMR3 base address */ +#define TMR3_BASE (0x401E4000u) +/** Peripheral TMR3 base pointer */ +#define TMR3 ((TMR_Type *)TMR3_BASE) +/** Peripheral TMR4 base address */ +#define TMR4_BASE (0x401E8000u) +/** Peripheral TMR4 base pointer */ +#define TMR4 ((TMR_Type *)TMR4_BASE) +/** Array initializer of TMR peripheral base addresses */ +#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE } +/** Array initializer of TMR peripheral base pointers */ +#define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 } +/** Interrupt vectors for the TMR peripheral type */ +#define TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn } + +/*! + * @} + */ /* end of group TMR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TRNG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer + * @{ + */ + +/** TRNG - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCTL; /**< Miscellaneous Control Register, offset: 0x0 */ + __IO uint32_t SCMISC; /**< Statistical Check Miscellaneous Register, offset: 0x4 */ + __IO uint32_t PKRRNG; /**< Poker Range Register, offset: 0x8 */ + union { /* offset: 0xC */ + __IO uint32_t PKRMAX; /**< Poker Maximum Limit Register, offset: 0xC */ + __I uint32_t PKRSQ; /**< Poker Square Calculation Result Register, offset: 0xC */ + }; + __IO uint32_t SDCTL; /**< Seed Control Register, offset: 0x10 */ + union { /* offset: 0x14 */ + __IO uint32_t SBLIM; /**< Sparse Bit Limit Register, offset: 0x14 */ + __I uint32_t TOTSAM; /**< Total Samples Register, offset: 0x14 */ + }; + __IO uint32_t FRQMIN; /**< Frequency Count Minimum Limit Register, offset: 0x18 */ + union { /* offset: 0x1C */ + __I uint32_t FRQCNT; /**< Frequency Count Register, offset: 0x1C */ + __IO uint32_t FRQMAX; /**< Frequency Count Maximum Limit Register, offset: 0x1C */ + }; + union { /* offset: 0x20 */ + __I uint32_t SCMC; /**< Statistical Check Monobit Count Register, offset: 0x20 */ + __IO uint32_t SCML; /**< Statistical Check Monobit Limit Register, offset: 0x20 */ + }; + union { /* offset: 0x24 */ + __I uint32_t SCR1C; /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */ + __IO uint32_t SCR1L; /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */ + }; + union { /* offset: 0x28 */ + __I uint32_t SCR2C; /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */ + __IO uint32_t SCR2L; /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */ + }; + union { /* offset: 0x2C */ + __I uint32_t SCR3C; /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */ + __IO uint32_t SCR3L; /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */ + }; + union { /* offset: 0x30 */ + __I uint32_t SCR4C; /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */ + __IO uint32_t SCR4L; /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */ + }; + union { /* offset: 0x34 */ + __I uint32_t SCR5C; /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */ + __IO uint32_t SCR5L; /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */ + }; + union { /* offset: 0x38 */ + __I uint32_t SCR6PC; /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */ + __IO uint32_t SCR6PL; /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */ + }; + __I uint32_t STATUS; /**< Status Register, offset: 0x3C */ + __I uint32_t ENT[16]; /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */ + __I uint32_t PKRCNT10; /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */ + __I uint32_t PKRCNT32; /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */ + __I uint32_t PKRCNT54; /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */ + __I uint32_t PKRCNT76; /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */ + __I uint32_t PKRCNT98; /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */ + __I uint32_t PKRCNTBA; /**< Statistical Check Poker Count B and A Register, offset: 0x94 */ + __I uint32_t PKRCNTDC; /**< Statistical Check Poker Count D and C Register, offset: 0x98 */ + __I uint32_t PKRCNTFE; /**< Statistical Check Poker Count F and E Register, offset: 0x9C */ + __IO uint32_t SEC_CFG; /**< Security Configuration Register, offset: 0xA0 */ + __IO uint32_t INT_CTRL; /**< Interrupt Control Register, offset: 0xA4 */ + __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xA8 */ + __I uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xAC */ + uint8_t RESERVED_0[64]; + __I uint32_t VID1; /**< Version ID Register (MS), offset: 0xF0 */ + __I uint32_t VID2; /**< Version ID Register (LS), offset: 0xF4 */ +} TRNG_Type; + +/* ---------------------------------------------------------------------------- + -- TRNG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRNG_Register_Masks TRNG Register Masks + * @{ + */ + +/*! @name MCTL - Miscellaneous Control Register */ +/*! @{ */ +#define TRNG_MCTL_SAMP_MODE_MASK (0x3U) +#define TRNG_MCTL_SAMP_MODE_SHIFT (0U) +/*! SAMP_MODE + * 0b00..use Von Neumann data into both Entropy shifter and Statistical Checker + * 0b01..use raw data into both Entropy shifter and Statistical Checker + * 0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker + * 0b11..undefined/reserved. + */ +#define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK) +#define TRNG_MCTL_OSC_DIV_MASK (0xCU) +#define TRNG_MCTL_OSC_DIV_SHIFT (2U) +/*! OSC_DIV + * 0b00..use ring oscillator with no divide + * 0b01..use ring oscillator divided-by-2 + * 0b10..use ring oscillator divided-by-4 + * 0b11..use ring oscillator divided-by-8 + */ +#define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK) +#define TRNG_MCTL_UNUSED4_MASK (0x10U) +#define TRNG_MCTL_UNUSED4_SHIFT (4U) +#define TRNG_MCTL_UNUSED4(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED4_SHIFT)) & TRNG_MCTL_UNUSED4_MASK) +#define TRNG_MCTL_UNUSED5_MASK (0x20U) +#define TRNG_MCTL_UNUSED5_SHIFT (5U) +#define TRNG_MCTL_UNUSED5(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED5_SHIFT)) & TRNG_MCTL_UNUSED5_MASK) +#define TRNG_MCTL_RST_DEF_MASK (0x40U) +#define TRNG_MCTL_RST_DEF_SHIFT (6U) +#define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK) +#define TRNG_MCTL_FOR_SCLK_MASK (0x80U) +#define TRNG_MCTL_FOR_SCLK_SHIFT (7U) +#define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK) +#define TRNG_MCTL_FCT_FAIL_MASK (0x100U) +#define TRNG_MCTL_FCT_FAIL_SHIFT (8U) +#define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK) +#define TRNG_MCTL_FCT_VAL_MASK (0x200U) +#define TRNG_MCTL_FCT_VAL_SHIFT (9U) +#define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK) +#define TRNG_MCTL_ENT_VAL_MASK (0x400U) +#define TRNG_MCTL_ENT_VAL_SHIFT (10U) +#define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK) +#define TRNG_MCTL_TST_OUT_MASK (0x800U) +#define TRNG_MCTL_TST_OUT_SHIFT (11U) +#define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK) +#define TRNG_MCTL_ERR_MASK (0x1000U) +#define TRNG_MCTL_ERR_SHIFT (12U) +#define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK) +#define TRNG_MCTL_TSTOP_OK_MASK (0x2000U) +#define TRNG_MCTL_TSTOP_OK_SHIFT (13U) +#define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK) +#define TRNG_MCTL_LRUN_CONT_MASK (0x4000U) +#define TRNG_MCTL_LRUN_CONT_SHIFT (14U) +#define TRNG_MCTL_LRUN_CONT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_LRUN_CONT_SHIFT)) & TRNG_MCTL_LRUN_CONT_MASK) +#define TRNG_MCTL_PRGM_MASK (0x10000U) +#define TRNG_MCTL_PRGM_SHIFT (16U) +#define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK) +/*! @} */ + +/*! @name SCMISC - Statistical Check Miscellaneous Register */ +/*! @{ */ +#define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU) +#define TRNG_SCMISC_LRUN_MAX_SHIFT (0U) +#define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK) +#define TRNG_SCMISC_RTY_CT_MASK (0xF0000U) +#define TRNG_SCMISC_RTY_CT_SHIFT (16U) +#define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK) +/*! @} */ + +/*! @name PKRRNG - Poker Range Register */ +/*! @{ */ +#define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU) +#define TRNG_PKRRNG_PKR_RNG_SHIFT (0U) +#define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK) +/*! @} */ + +/*! @name PKRMAX - Poker Maximum Limit Register */ +/*! @{ */ +#define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU) +#define TRNG_PKRMAX_PKR_MAX_SHIFT (0U) +#define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK) +/*! @} */ + +/*! @name PKRSQ - Poker Square Calculation Result Register */ +/*! @{ */ +#define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU) +#define TRNG_PKRSQ_PKR_SQ_SHIFT (0U) +#define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK) +/*! @} */ + +/*! @name SDCTL - Seed Control Register */ +/*! @{ */ +#define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU) +#define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U) +#define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK) +#define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U) +#define TRNG_SDCTL_ENT_DLY_SHIFT (16U) +#define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK) +/*! @} */ + +/*! @name SBLIM - Sparse Bit Limit Register */ +/*! @{ */ +#define TRNG_SBLIM_SB_LIM_MASK (0x3FFU) +#define TRNG_SBLIM_SB_LIM_SHIFT (0U) +#define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK) +/*! @} */ + +/*! @name TOTSAM - Total Samples Register */ +/*! @{ */ +#define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU) +#define TRNG_TOTSAM_TOT_SAM_SHIFT (0U) +#define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK) +/*! @} */ + +/*! @name FRQMIN - Frequency Count Minimum Limit Register */ +/*! @{ */ +#define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU) +#define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U) +#define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK) +/*! @} */ + +/*! @name FRQCNT - Frequency Count Register */ +/*! @{ */ +#define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU) +#define TRNG_FRQCNT_FRQ_CT_SHIFT (0U) +#define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK) +/*! @} */ + +/*! @name FRQMAX - Frequency Count Maximum Limit Register */ +/*! @{ */ +#define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU) +#define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U) +#define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK) +/*! @} */ + +/*! @name SCMC - Statistical Check Monobit Count Register */ +/*! @{ */ +#define TRNG_SCMC_MONO_CT_MASK (0xFFFFU) +#define TRNG_SCMC_MONO_CT_SHIFT (0U) +#define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK) +/*! @} */ + +/*! @name SCML - Statistical Check Monobit Limit Register */ +/*! @{ */ +#define TRNG_SCML_MONO_MAX_MASK (0xFFFFU) +#define TRNG_SCML_MONO_MAX_SHIFT (0U) +#define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK) +#define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U) +#define TRNG_SCML_MONO_RNG_SHIFT (16U) +#define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK) +/*! @} */ + +/*! @name SCR1C - Statistical Check Run Length 1 Count Register */ +/*! @{ */ +#define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU) +#define TRNG_SCR1C_R1_0_CT_SHIFT (0U) +#define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK) +#define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U) +#define TRNG_SCR1C_R1_1_CT_SHIFT (16U) +#define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK) +/*! @} */ + +/*! @name SCR1L - Statistical Check Run Length 1 Limit Register */ +/*! @{ */ +#define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU) +#define TRNG_SCR1L_RUN1_MAX_SHIFT (0U) +#define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK) +#define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U) +#define TRNG_SCR1L_RUN1_RNG_SHIFT (16U) +#define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK) +/*! @} */ + +/*! @name SCR2C - Statistical Check Run Length 2 Count Register */ +/*! @{ */ +#define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU) +#define TRNG_SCR2C_R2_0_CT_SHIFT (0U) +#define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK) +#define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U) +#define TRNG_SCR2C_R2_1_CT_SHIFT (16U) +#define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK) +/*! @} */ + +/*! @name SCR2L - Statistical Check Run Length 2 Limit Register */ +/*! @{ */ +#define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU) +#define TRNG_SCR2L_RUN2_MAX_SHIFT (0U) +#define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK) +#define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U) +#define TRNG_SCR2L_RUN2_RNG_SHIFT (16U) +#define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK) +/*! @} */ + +/*! @name SCR3C - Statistical Check Run Length 3 Count Register */ +/*! @{ */ +#define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU) +#define TRNG_SCR3C_R3_0_CT_SHIFT (0U) +#define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK) +#define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U) +#define TRNG_SCR3C_R3_1_CT_SHIFT (16U) +#define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK) +/*! @} */ + +/*! @name SCR3L - Statistical Check Run Length 3 Limit Register */ +/*! @{ */ +#define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU) +#define TRNG_SCR3L_RUN3_MAX_SHIFT (0U) +#define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK) +#define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U) +#define TRNG_SCR3L_RUN3_RNG_SHIFT (16U) +#define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK) +/*! @} */ + +/*! @name SCR4C - Statistical Check Run Length 4 Count Register */ +/*! @{ */ +#define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU) +#define TRNG_SCR4C_R4_0_CT_SHIFT (0U) +#define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK) +#define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U) +#define TRNG_SCR4C_R4_1_CT_SHIFT (16U) +#define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK) +/*! @} */ + +/*! @name SCR4L - Statistical Check Run Length 4 Limit Register */ +/*! @{ */ +#define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU) +#define TRNG_SCR4L_RUN4_MAX_SHIFT (0U) +#define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK) +#define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U) +#define TRNG_SCR4L_RUN4_RNG_SHIFT (16U) +#define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK) +/*! @} */ + +/*! @name SCR5C - Statistical Check Run Length 5 Count Register */ +/*! @{ */ +#define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU) +#define TRNG_SCR5C_R5_0_CT_SHIFT (0U) +#define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK) +#define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U) +#define TRNG_SCR5C_R5_1_CT_SHIFT (16U) +#define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK) +/*! @} */ + +/*! @name SCR5L - Statistical Check Run Length 5 Limit Register */ +/*! @{ */ +#define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU) +#define TRNG_SCR5L_RUN5_MAX_SHIFT (0U) +#define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK) +#define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U) +#define TRNG_SCR5L_RUN5_RNG_SHIFT (16U) +#define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK) +/*! @} */ + +/*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */ +/*! @{ */ +#define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU) +#define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U) +#define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK) +#define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U) +#define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U) +#define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK) +/*! @} */ + +/*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */ +/*! @{ */ +#define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU) +#define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U) +#define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK) +#define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U) +#define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U) +#define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK) +/*! @} */ + +/*! @name STATUS - Status Register */ +/*! @{ */ +#define TRNG_STATUS_TF1BR0_MASK (0x1U) +#define TRNG_STATUS_TF1BR0_SHIFT (0U) +#define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK) +#define TRNG_STATUS_TF1BR1_MASK (0x2U) +#define TRNG_STATUS_TF1BR1_SHIFT (1U) +#define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK) +#define TRNG_STATUS_TF2BR0_MASK (0x4U) +#define TRNG_STATUS_TF2BR0_SHIFT (2U) +#define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK) +#define TRNG_STATUS_TF2BR1_MASK (0x8U) +#define TRNG_STATUS_TF2BR1_SHIFT (3U) +#define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK) +#define TRNG_STATUS_TF3BR0_MASK (0x10U) +#define TRNG_STATUS_TF3BR0_SHIFT (4U) +#define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK) +#define TRNG_STATUS_TF3BR1_MASK (0x20U) +#define TRNG_STATUS_TF3BR1_SHIFT (5U) +#define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK) +#define TRNG_STATUS_TF4BR0_MASK (0x40U) +#define TRNG_STATUS_TF4BR0_SHIFT (6U) +#define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK) +#define TRNG_STATUS_TF4BR1_MASK (0x80U) +#define TRNG_STATUS_TF4BR1_SHIFT (7U) +#define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK) +#define TRNG_STATUS_TF5BR0_MASK (0x100U) +#define TRNG_STATUS_TF5BR0_SHIFT (8U) +#define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK) +#define TRNG_STATUS_TF5BR1_MASK (0x200U) +#define TRNG_STATUS_TF5BR1_SHIFT (9U) +#define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK) +#define TRNG_STATUS_TF6PBR0_MASK (0x400U) +#define TRNG_STATUS_TF6PBR0_SHIFT (10U) +#define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK) +#define TRNG_STATUS_TF6PBR1_MASK (0x800U) +#define TRNG_STATUS_TF6PBR1_SHIFT (11U) +#define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK) +#define TRNG_STATUS_TFSB_MASK (0x1000U) +#define TRNG_STATUS_TFSB_SHIFT (12U) +#define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK) +#define TRNG_STATUS_TFLR_MASK (0x2000U) +#define TRNG_STATUS_TFLR_SHIFT (13U) +#define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK) +#define TRNG_STATUS_TFP_MASK (0x4000U) +#define TRNG_STATUS_TFP_SHIFT (14U) +#define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK) +#define TRNG_STATUS_TFMB_MASK (0x8000U) +#define TRNG_STATUS_TFMB_SHIFT (15U) +#define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK) +#define TRNG_STATUS_RETRY_CT_MASK (0xF0000U) +#define TRNG_STATUS_RETRY_CT_SHIFT (16U) +#define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK) +/*! @} */ + +/*! @name ENT - Entropy Read Register */ +/*! @{ */ +#define TRNG_ENT_ENT_MASK (0xFFFFFFFFU) +#define TRNG_ENT_ENT_SHIFT (0U) +#define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK) +/*! @} */ + +/* The count of TRNG_ENT */ +#define TRNG_ENT_COUNT (16U) + +/*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */ +/*! @{ */ +#define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U) +#define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK) +#define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U) +#define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK) +/*! @} */ + +/*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */ +/*! @{ */ +#define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U) +#define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK) +#define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U) +#define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK) +/*! @} */ + +/*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */ +/*! @{ */ +#define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U) +#define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK) +#define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U) +#define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK) +/*! @} */ + +/*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */ +/*! @{ */ +#define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U) +#define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK) +#define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U) +#define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK) +/*! @} */ + +/*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */ +/*! @{ */ +#define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU) +#define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U) +#define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK) +#define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U) +#define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK) +/*! @} */ + +/*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */ +/*! @{ */ +#define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU) +#define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U) +#define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK) +#define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U) +#define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK) +/*! @} */ + +/*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */ +/*! @{ */ +#define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU) +#define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U) +#define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK) +#define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U) +#define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK) +/*! @} */ + +/*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */ +/*! @{ */ +#define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU) +#define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U) +#define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK) +#define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U) +#define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U) +#define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK) +/*! @} */ + +/*! @name SEC_CFG - Security Configuration Register */ +/*! @{ */ +#define TRNG_SEC_CFG_UNUSED0_MASK (0x1U) +#define TRNG_SEC_CFG_UNUSED0_SHIFT (0U) +#define TRNG_SEC_CFG_UNUSED0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED0_SHIFT)) & TRNG_SEC_CFG_UNUSED0_MASK) +#define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U) +#define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U) +/*! NO_PRGM + * 0b0..Programability of registers controlled only by the Miscellaneous Control Register's access mode bit. + * 0b1..Overides Miscellaneous Control Register access mode and prevents TRNG register programming. + */ +#define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK) +#define TRNG_SEC_CFG_UNUSED2_MASK (0x4U) +#define TRNG_SEC_CFG_UNUSED2_SHIFT (2U) +#define TRNG_SEC_CFG_UNUSED2(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_UNUSED2_SHIFT)) & TRNG_SEC_CFG_UNUSED2_MASK) +/*! @} */ + +/*! @name INT_CTRL - Interrupt Control Register */ +/*! @{ */ +#define TRNG_INT_CTRL_HW_ERR_MASK (0x1U) +#define TRNG_INT_CTRL_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..Corresponding bit of INT_STATUS register cleared. + * 0b1..Corresponding bit of INT_STATUS register active. + */ +#define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK) +#define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U) +#define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ +#define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK) +#define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U) +#define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ +#define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK) +#define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U) +#define TRNG_INT_CTRL_UNUSED_SHIFT (3U) +#define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK) +/*! @} */ + +/*! @name INT_MASK - Mask Register */ +/*! @{ */ +#define TRNG_INT_MASK_HW_ERR_MASK (0x1U) +#define TRNG_INT_MASK_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..Corresponding interrupt of INT_STATUS is masked. + * 0b1..Corresponding bit of INT_STATUS is active. + */ +#define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK) +#define TRNG_INT_MASK_ENT_VAL_MASK (0x2U) +#define TRNG_INT_MASK_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ +#define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK) +#define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U) +#define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..Same behavior as bit 0 of this register. + * 0b1..Same behavior as bit 0 of this register. + */ +#define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt Status Register */ +/*! @{ */ +#define TRNG_INT_STATUS_HW_ERR_MASK (0x1U) +#define TRNG_INT_STATUS_HW_ERR_SHIFT (0U) +/*! HW_ERR + * 0b0..no error + * 0b1..error detected. + */ +#define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK) +#define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U) +#define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U) +/*! ENT_VAL + * 0b0..Busy generation entropy. Any value read is invalid. + * 0b1..TRNG can be stopped and entropy is valid if read. + */ +#define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK) +#define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U) +#define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U) +/*! FRQ_CT_FAIL + * 0b0..No hardware nor self test frequency errors. + * 0b1..The frequency counter has detected a failure. + */ +#define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) +/*! @} */ + +/*! @name VID1 - Version ID Register (MS) */ +/*! @{ */ +#define TRNG_VID1_MIN_REV_MASK (0xFFU) +#define TRNG_VID1_MIN_REV_SHIFT (0U) +/*! MIN_REV + * 0b00000000..Minor revision number for TRNG. + */ +#define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK) +#define TRNG_VID1_MAJ_REV_MASK (0xFF00U) +#define TRNG_VID1_MAJ_REV_SHIFT (8U) +/*! MAJ_REV + * 0b00000001..Major revision number for TRNG. + */ +#define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK) +#define TRNG_VID1_IP_ID_MASK (0xFFFF0000U) +#define TRNG_VID1_IP_ID_SHIFT (16U) +/*! IP_ID + * 0b0000000000110000..ID for TRNG. + */ +#define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK) +/*! @} */ + +/*! @name VID2 - Version ID Register (LS) */ +/*! @{ */ +#define TRNG_VID2_CONFIG_OPT_MASK (0xFFU) +#define TRNG_VID2_CONFIG_OPT_SHIFT (0U) +/*! CONFIG_OPT + * 0b00000000..TRNG_CONFIG_OPT for TRNG. + */ +#define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK) +#define TRNG_VID2_ECO_REV_MASK (0xFF00U) +#define TRNG_VID2_ECO_REV_SHIFT (8U) +/*! ECO_REV + * 0b00000000..TRNG_ECO_REV for TRNG. + */ +#define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK) +#define TRNG_VID2_INTG_OPT_MASK (0xFF0000U) +#define TRNG_VID2_INTG_OPT_SHIFT (16U) +/*! INTG_OPT + * 0b00000000..INTG_OPT for TRNG. + */ +#define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK) +#define TRNG_VID2_ERA_MASK (0xFF000000U) +#define TRNG_VID2_ERA_SHIFT (24U) +/*! ERA + * 0b00000000..COMPILE_OPT for TRNG. + */ +#define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TRNG_Register_Masks */ + + +/* TRNG - Peripheral instance base addresses */ +/** Peripheral TRNG base address */ +#define TRNG_BASE (0x400CC000u) +/** Peripheral TRNG base pointer */ +#define TRNG ((TRNG_Type *)TRNG_BASE) +/** Array initializer of TRNG peripheral base addresses */ +#define TRNG_BASE_ADDRS { TRNG_BASE } +/** Array initializer of TRNG peripheral base pointers */ +#define TRNG_BASE_PTRS { TRNG } +/** Interrupt vectors for the TRNG peripheral type */ +#define TRNG_IRQS { TRNG_IRQn } + +/*! + * @} + */ /* end of group TRNG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TSC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSC_Peripheral_Access_Layer TSC Peripheral Access Layer + * @{ + */ + +/** TSC - Register Layout Typedef */ +typedef struct { + __IO uint32_t BASIC_SETTING; /**< , offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t PRE_CHARGE_TIME; /**< , offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t FLOW_CONTROL; /**< Flow Control, offset: 0x20 */ + uint8_t RESERVED_2[12]; + __I uint32_t MEASEURE_VALUE; /**< Measure Value, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __IO uint32_t INT_EN; /**< Interrupt Enable, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t INT_SIG_EN; /**< Interrupt Signal Enable, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t INT_STATUS; /**< Intterrupt Status, offset: 0x60 */ + uint8_t RESERVED_6[12]; + __IO uint32_t DEBUG_MODE; /**< , offset: 0x70 */ + uint8_t RESERVED_7[12]; + __IO uint32_t DEBUG_MODE2; /**< , offset: 0x80 */ +} TSC_Type; + +/* ---------------------------------------------------------------------------- + -- TSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TSC_Register_Masks TSC Register Masks + * @{ + */ + +/*! @name BASIC_SETTING - */ +/*! @{ */ +#define TSC_BASIC_SETTING_AUTO_MEASURE_MASK (0x1U) +#define TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT (0U) +/*! AUTO_MEASURE - Auto Measure + * 0b0..Disable Auto Measure + * 0b1..Auto Measure + */ +#define TSC_BASIC_SETTING_AUTO_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_AUTO_MEASURE_SHIFT)) & TSC_BASIC_SETTING_AUTO_MEASURE_MASK) +#define TSC_BASIC_SETTING_4_5_WIRE_MASK (0x10U) +#define TSC_BASIC_SETTING_4_5_WIRE_SHIFT (4U) +/*! 4_5_WIRE - 4/5 Wire detection + * 0b0..4-Wire Detection Mode + * 0b1..5-Wire Detection Mode + */ +#define TSC_BASIC_SETTING_4_5_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_4_5_WIRE_SHIFT)) & TSC_BASIC_SETTING_4_5_WIRE_MASK) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK (0xFFFFFF00U) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT (8U) +#define TSC_BASIC_SETTING_MEASURE_DELAY_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_BASIC_SETTING_MEASURE_DELAY_TIME_SHIFT)) & TSC_BASIC_SETTING_MEASURE_DELAY_TIME_MASK) +/*! @} */ + +/*! @name PRE_CHARGE_TIME - */ +/*! @{ */ +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK (0xFFFFFFFFU) +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT (0U) +#define TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(x) (((uint32_t)(((uint32_t)(x)) << TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_SHIFT)) & TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME_MASK) +/*! @} */ + +/*! @name FLOW_CONTROL - Flow Control */ +/*! @{ */ +#define TSC_FLOW_CONTROL_SW_RST_MASK (0x1U) +#define TSC_FLOW_CONTROL_SW_RST_SHIFT (0U) +#define TSC_FLOW_CONTROL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_SW_RST_SHIFT)) & TSC_FLOW_CONTROL_SW_RST_MASK) +#define TSC_FLOW_CONTROL_START_MEASURE_MASK (0x10U) +#define TSC_FLOW_CONTROL_START_MEASURE_SHIFT (4U) +/*! START_MEASURE - Start Measure + * 0b0..Do not start measure for now + * 0b1..Start measure the X/Y coordinate value + */ +#define TSC_FLOW_CONTROL_START_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_START_MEASURE_MASK) +#define TSC_FLOW_CONTROL_DROP_MEASURE_MASK (0x100U) +#define TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT (8U) +/*! DROP_MEASURE - Drop Measure + * 0b0..Do not drop measure for now + * 0b1..Drop the measure and controller return to idle status + */ +#define TSC_FLOW_CONTROL_DROP_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DROP_MEASURE_SHIFT)) & TSC_FLOW_CONTROL_DROP_MEASURE_MASK) +#define TSC_FLOW_CONTROL_START_SENSE_MASK (0x1000U) +#define TSC_FLOW_CONTROL_START_SENSE_SHIFT (12U) +/*! START_SENSE - Start Sense + * 0b0..Stay at idle status + * 0b1..Start sense detection and (if auto_measure set to 1) measure after detect a touch + */ +#define TSC_FLOW_CONTROL_START_SENSE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_START_SENSE_SHIFT)) & TSC_FLOW_CONTROL_START_SENSE_MASK) +#define TSC_FLOW_CONTROL_DISABLE_MASK (0x10000U) +#define TSC_FLOW_CONTROL_DISABLE_SHIFT (16U) +/*! DISABLE + * 0b0..Leave HW state machine control + * 0b1..SW set to idle status + */ +#define TSC_FLOW_CONTROL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_FLOW_CONTROL_DISABLE_SHIFT)) & TSC_FLOW_CONTROL_DISABLE_MASK) +/*! @} */ + +/*! @name MEASEURE_VALUE - Measure Value */ +/*! @{ */ +#define TSC_MEASEURE_VALUE_Y_VALUE_MASK (0xFFFU) +#define TSC_MEASEURE_VALUE_Y_VALUE_SHIFT (0U) +#define TSC_MEASEURE_VALUE_Y_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_Y_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_Y_VALUE_MASK) +#define TSC_MEASEURE_VALUE_X_VALUE_MASK (0xFFF0000U) +#define TSC_MEASEURE_VALUE_X_VALUE_SHIFT (16U) +#define TSC_MEASEURE_VALUE_X_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_MEASEURE_VALUE_X_VALUE_SHIFT)) & TSC_MEASEURE_VALUE_X_VALUE_MASK) +/*! @} */ + +/*! @name INT_EN - Interrupt Enable */ +/*! @{ */ +#define TSC_INT_EN_MEASURE_INT_EN_MASK (0x1U) +#define TSC_INT_EN_MEASURE_INT_EN_SHIFT (0U) +/*! MEASURE_INT_EN - Measure Interrupt Enable + * 0b0..Disable measure interrupt + * 0b1..Enable measure interrupt + */ +#define TSC_INT_EN_MEASURE_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_MEASURE_INT_EN_SHIFT)) & TSC_INT_EN_MEASURE_INT_EN_MASK) +#define TSC_INT_EN_DETECT_INT_EN_MASK (0x10U) +#define TSC_INT_EN_DETECT_INT_EN_SHIFT (4U) +/*! DETECT_INT_EN - Detect Interrupt Enable + * 0b0..Disable detect interrupt + * 0b1..Enable detect interrupt + */ +#define TSC_INT_EN_DETECT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_DETECT_INT_EN_SHIFT)) & TSC_INT_EN_DETECT_INT_EN_MASK) +#define TSC_INT_EN_IDLE_SW_INT_EN_MASK (0x1000U) +#define TSC_INT_EN_IDLE_SW_INT_EN_SHIFT (12U) +/*! IDLE_SW_INT_EN - Idle Software Interrupt Enable + * 0b0..Disable idle software interrupt + * 0b1..Enable idle software interrupt + */ +#define TSC_INT_EN_IDLE_SW_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_EN_IDLE_SW_INT_EN_SHIFT)) & TSC_INT_EN_IDLE_SW_INT_EN_MASK) +/*! @} */ + +/*! @name INT_SIG_EN - Interrupt Signal Enable */ +/*! @{ */ +#define TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK (0x1U) +#define TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT (0U) +#define TSC_INT_SIG_EN_MEASURE_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_MEASURE_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK) +#define TSC_INT_SIG_EN_DETECT_SIG_EN_MASK (0x10U) +#define TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT (4U) +/*! DETECT_SIG_EN - Detect Signal Enable + * 0b0..Disable detect signal + * 0b1..Enable detect signal + */ +#define TSC_INT_SIG_EN_DETECT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_DETECT_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_DETECT_SIG_EN_MASK) +#define TSC_INT_SIG_EN_VALID_SIG_EN_MASK (0x100U) +#define TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT (8U) +/*! VALID_SIG_EN - Valid Signal Enable + * 0b0..Disable valid signal + * 0b1..Enable valid signal + */ +#define TSC_INT_SIG_EN_VALID_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_VALID_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_VALID_SIG_EN_MASK) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK (0x1000U) +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT (12U) +/*! IDLE_SW_SIG_EN - Idle Software Signal Enable + * 0b0..Disable idle software signal + * 0b1..Enable idle software signal + */ +#define TSC_INT_SIG_EN_IDLE_SW_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_SIG_EN_IDLE_SW_SIG_EN_SHIFT)) & TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK) +/*! @} */ + +/*! @name INT_STATUS - Intterrupt Status */ +/*! @{ */ +#define TSC_INT_STATUS_MEASURE_MASK (0x1U) +#define TSC_INT_STATUS_MEASURE_SHIFT (0U) +/*! MEASURE - Measure Signal + * 0b0..Does not exist a measure signal + * 0b1..Exist a measure signal + */ +#define TSC_INT_STATUS_MEASURE(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_MEASURE_SHIFT)) & TSC_INT_STATUS_MEASURE_MASK) +#define TSC_INT_STATUS_DETECT_MASK (0x10U) +#define TSC_INT_STATUS_DETECT_SHIFT (4U) +/*! DETECT - Detect Signal + * 0b0..Does not exist a detect signal + * 0b1..Exist detect signal + */ +#define TSC_INT_STATUS_DETECT(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_DETECT_SHIFT)) & TSC_INT_STATUS_DETECT_MASK) +#define TSC_INT_STATUS_VALID_MASK (0x100U) +#define TSC_INT_STATUS_VALID_SHIFT (8U) +/*! VALID - Valid Signal + * 0b0..There is no touch detected after measurement, indicates that the measured value is not valid + * 0b1..There is touch detection after measurement, indicates that the measure is valid + */ +#define TSC_INT_STATUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_VALID_SHIFT)) & TSC_INT_STATUS_VALID_MASK) +#define TSC_INT_STATUS_IDLE_SW_MASK (0x1000U) +#define TSC_INT_STATUS_IDLE_SW_SHIFT (12U) +/*! IDLE_SW - Idle Software + * 0b0..Haven't return to idle status + * 0b1..Already return to idle status + */ +#define TSC_INT_STATUS_IDLE_SW(x) (((uint32_t)(((uint32_t)(x)) << TSC_INT_STATUS_IDLE_SW_SHIFT)) & TSC_INT_STATUS_IDLE_SW_MASK) +/*! @} */ + +/*! @name DEBUG_MODE - */ +/*! @{ */ +#define TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK (0xFFFU) +#define TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT (0U) +#define TSC_DEBUG_MODE_ADC_CONV_VALUE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_CONV_VALUE_SHIFT)) & TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_MASK (0x1000U) +#define TSC_DEBUG_MODE_ADC_COCO_SHIFT (12U) +#define TSC_DEBUG_MODE_ADC_COCO(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_MASK) +#define TSC_DEBUG_MODE_EXT_HWTS_MASK (0x1F0000U) +#define TSC_DEBUG_MODE_EXT_HWTS_SHIFT (16U) +#define TSC_DEBUG_MODE_EXT_HWTS(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_EXT_HWTS_SHIFT)) & TSC_DEBUG_MODE_EXT_HWTS_MASK) +#define TSC_DEBUG_MODE_TRIGGER_MASK (0x1000000U) +#define TSC_DEBUG_MODE_TRIGGER_SHIFT (24U) +/*! TRIGGER - Trigger + * 0b0..No hardware trigger signal + * 0b1..Hardware trigger signal, the signal must last at least 1 ips clock period + */ +#define TSC_DEBUG_MODE_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_TRIGGER_SHIFT)) & TSC_DEBUG_MODE_TRIGGER_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK (0x2000000U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT (25U) +/*! ADC_COCO_CLEAR - ADC Coco Clear + * 0b0..No ADC COCO clear + * 0b1..Set ADC COCO clear + */ +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK (0x4000000U) +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT (26U) +/*! ADC_COCO_CLEAR_DISABLE - ADC COCO Clear Disable + * 0b0..Allow TSC hardware generates ADC COCO clear + * 0b1..Prevent TSC from generate ADC COCO clear signal + */ +#define TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_SHIFT)) & TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK) +#define TSC_DEBUG_MODE_DEBUG_EN_MASK (0x10000000U) +#define TSC_DEBUG_MODE_DEBUG_EN_SHIFT (28U) +/*! DEBUG_EN - Debug Enable + * 0b0..Enable debug mode + * 0b1..Disable debug mode + */ +#define TSC_DEBUG_MODE_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE_DEBUG_EN_SHIFT)) & TSC_DEBUG_MODE_DEBUG_EN_MASK) +/*! @} */ + +/*! @name DEBUG_MODE2 - */ +/*! @{ */ +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK (0x1U) +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT (0U) +/*! XPUL_PULL_DOWN - XPUL Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_XPUL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK (0x2U) +#define TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT (1U) +/*! XPUL_PULL_UP - XPUL Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_XPUL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK (0x4U) +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT (2U) +/*! XPUL_200K_PULL_UP - XPUL Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_XPUL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK (0x8U) +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT (3U) +/*! XNUR_PULL_DOWN - XNUR Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_XNUR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK (0x10U) +#define TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT (4U) +/*! XNUR_PULL_UP - XNUR Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_XNUR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK (0x20U) +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT (5U) +/*! XNUR_200K_PULL_UP - XNUR Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_XNUR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK (0x40U) +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT (6U) +/*! YPLL_PULL_DOWN - YPLL Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_YPLL_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK (0x80U) +#define TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT (7U) +/*! YPLL_PULL_UP - YPLL Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open the switch + */ +#define TSC_DEBUG_MODE2_YPLL_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK (0x100U) +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT (8U) +/*! YPLL_200K_PULL_UP - YPLL Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_YPLL_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK (0x200U) +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT (9U) +/*! YNLR_PULL_DOWN - YNLR Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_YNLR_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK (0x400U) +#define TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT (10U) +/*! YNLR_PULL_UP - YNLR Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_YNLR_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK (0x800U) +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT (11U) +/*! YNLR_200K_PULL_UP - YNLR Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_YNLR_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK (0x1000U) +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT (12U) +/*! WIPER_PULL_DOWN - Wiper Wire Pull Down Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_WIPER_PULL_DOWN(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK (0x2000U) +#define TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT (13U) +/*! WIPER_PULL_UP - Wiper Wire Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_WIPER_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK (0x4000U) +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT (14U) +/*! WIPER_200K_PULL_UP - Wiper Wire 200K Pull Up Switch + * 0b0..Close the switch + * 0b1..Open up the switch + */ +#define TSC_DEBUG_MODE2_WIPER_200K_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_SHIFT)) & TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK (0x10000U) +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT (16U) +/*! DETECT_FOUR_WIRE - Detect Four Wire + * 0b0..No detect signal + * 0b1..Yes, there is a detect on the touch screen. + */ +#define TSC_DEBUG_MODE2_DETECT_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK (0x20000U) +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT (17U) +/*! DETECT_FIVE_WIRE - Detect Five Wire + * 0b0..No detect signal + * 0b1..Yes, there is a detect on the touch screen. + */ +#define TSC_DEBUG_MODE2_DETECT_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK) +#define TSC_DEBUG_MODE2_STATE_MACHINE_MASK (0x700000U) +#define TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT (20U) +/*! STATE_MACHINE - State Machine + * 0b000..Idle + * 0b001..Pre-charge + * 0b010..Detect + * 0b011..X-measure + * 0b100..Y-measure + * 0b101..Pre-charge + * 0b110..Detect + */ +#define TSC_DEBUG_MODE2_STATE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT)) & TSC_DEBUG_MODE2_STATE_MACHINE_MASK) +#define TSC_DEBUG_MODE2_INTERMEDIATE_MASK (0x800000U) +#define TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT (23U) +/*! INTERMEDIATE - Intermediate State + * 0b0..Not in intermedia + * 0b1..Intermedia + */ +#define TSC_DEBUG_MODE2_INTERMEDIATE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_INTERMEDIATE_SHIFT)) & TSC_DEBUG_MODE2_INTERMEDIATE_MASK) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK (0x1000000U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT (24U) +/*! DETECT_ENABLE_FOUR_WIRE - Detect Enable Four Wire + * 0b0..Do not read four wire detect value, read default value from analogue + * 0b1..Read four wire detect status from analogue + */ +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK (0x10000000U) +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT (28U) +/*! DETECT_ENABLE_FIVE_WIRE - Detect Enable Five Wire + * 0b0..Do not read five wire detect value, read default value from analogue + * 0b1..Read five wire detect status from analogue + */ +#define TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_SHIFT)) & TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK) +#define TSC_DEBUG_MODE2_DE_GLITCH_MASK (0x60000000U) +#define TSC_DEBUG_MODE2_DE_GLITCH_SHIFT (29U) +/*! DE_GLITCH + * 0b00..Normal function: 0x1fff ipg clock cycles; Low power mode: 0x9 low power clock cycles + * 0b01..Normal function: 0xfff ipg clock cycles; Low power mode: :0x7 low power clock cycles + * 0b10..Normal function: 0x7ff ipg clock cycles; Low power mode:0x5 low power clock cycles + * 0b11..Normal function: 0x3 ipg clock cycles; Low power mode:0x3 low power clock cycles + */ +#define TSC_DEBUG_MODE2_DE_GLITCH(x) (((uint32_t)(((uint32_t)(x)) << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT)) & TSC_DEBUG_MODE2_DE_GLITCH_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group TSC_Register_Masks */ + + +/* TSC - Peripheral instance base addresses */ +/** Peripheral TSC base address */ +#define TSC_BASE (0x400E0000u) +/** Peripheral TSC base pointer */ +#define TSC ((TSC_Type *)TSC_BASE) +/** Array initializer of TSC peripheral base addresses */ +#define TSC_BASE_ADDRS { TSC_BASE } +/** Array initializer of TSC peripheral base pointers */ +#define TSC_BASE_PTRS { TSC } +/** Interrupt vectors for the TSC peripheral type */ +#define TSC_IRQS { TSC_DIG_IRQn } +/* Backward compatibility */ +#define TSC_BASIC_SETTING__4_5_WIRE_MASK TSC_BASIC_SETTING_4_5_WIRE_MASK +#define TSC_BASIC_SETTING__4_5_WIRE_SHIFT TSC_BASIC_SETTING_4_5_WIRE_SHIFT +#define TSC_BASIC_SETTING__4_5_WIRE(x) TSC_BASIC_SETTING_4_5_WIRE(x) + + +/*! + * @} + */ /* end of group TSC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint32_t ID; /**< Identification register, offset: 0x0 */ + __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */ + __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */ + __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */ + __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */ + __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */ + uint8_t RESERVED_0[104]; + __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */ + __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */ + __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */ + __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */ + __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */ + uint8_t RESERVED_1[108]; + __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */ + uint8_t RESERVED_2[1]; + __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */ + __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */ + __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */ + uint8_t RESERVED_3[20]; + __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */ + uint8_t RESERVED_4[2]; + __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */ + uint8_t RESERVED_5[24]; + __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */ + __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */ + __IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */ + __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */ + uint8_t RESERVED_6[4]; + union { /* offset: 0x154 */ + __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */ + __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */ + }; + union { /* offset: 0x158 */ + __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */ + __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */ + }; + uint8_t RESERVED_7[4]; + __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */ + __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */ + uint8_t RESERVED_8[16]; + __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */ + __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */ + __I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */ + __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */ + uint8_t RESERVED_9[28]; + __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */ + __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */ + __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */ + __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */ + __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */ + __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */ + __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */ + __IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */ + __IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name ID - Identification register */ +/*! @{ */ +#define USB_ID_ID_MASK (0x3FU) +#define USB_ID_ID_SHIFT (0U) +#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) +#define USB_ID_NID_MASK (0x3F00U) +#define USB_ID_NID_SHIFT (8U) +#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK) +#define USB_ID_REVISION_MASK (0xFF0000U) +#define USB_ID_REVISION_SHIFT (16U) +#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) +/*! @} */ + +/*! @name HWGENERAL - Hardware General */ +/*! @{ */ +#define USB_HWGENERAL_PHYW_MASK (0x30U) +#define USB_HWGENERAL_PHYW_SHIFT (4U) +/*! PHYW + * 0b00..8 bit wide data bus Software non-programmable + * 0b01..16 bit wide data bus Software non-programmable + * 0b10..Reset to 8 bit wide data bus Software programmable + * 0b11..Reset to 16 bit wide data bus Software programmable + */ +#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) +#define USB_HWGENERAL_PHYM_MASK (0x1C0U) +#define USB_HWGENERAL_PHYM_SHIFT (6U) +/*! PHYM + * 0b000..UTMI/UMTI+ + * 0b001..ULPI DDR + * 0b010..ULPI + * 0b011..Serial Only + * 0b100..Software programmable - reset to UTMI/UTMI+ + * 0b101..Software programmable - reset to ULPI DDR + * 0b110..Software programmable - reset to ULPI + * 0b111..Software programmable - reset to Serial + */ +#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) +#define USB_HWGENERAL_SM_MASK (0x600U) +#define USB_HWGENERAL_SM_SHIFT (9U) +/*! SM + * 0b00..No Serial Engine, always use parallel signalling. + * 0b01..Serial Engine present, always use serial signalling for FS/LS. + * 0b10..Software programmable - Reset to use parallel signalling for FS/LS + * 0b11..Software programmable - Reset to use serial signalling for FS/LS + */ +#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK) +/*! @} */ + +/*! @name HWHOST - Host Hardware Parameters */ +/*! @{ */ +#define USB_HWHOST_HC_MASK (0x1U) +#define USB_HWHOST_HC_SHIFT (0U) +/*! HC + * 0b1..Supported + * 0b0..Not supported + */ +#define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) +#define USB_HWHOST_NPORT_MASK (0xEU) +#define USB_HWHOST_NPORT_SHIFT (1U) +#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) +/*! @} */ + +/*! @name HWDEVICE - Device Hardware Parameters */ +/*! @{ */ +#define USB_HWDEVICE_DC_MASK (0x1U) +#define USB_HWDEVICE_DC_SHIFT (0U) +/*! DC + * 0b1..Supported + * 0b0..Not supported + */ +#define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) +#define USB_HWDEVICE_DEVEP_MASK (0x3EU) +#define USB_HWDEVICE_DEVEP_SHIFT (1U) +#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) +/*! @} */ + +/*! @name HWTXBUF - TX Buffer Hardware Parameters */ +/*! @{ */ +#define USB_HWTXBUF_TXBURST_MASK (0xFFU) +#define USB_HWTXBUF_TXBURST_SHIFT (0U) +#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) +#define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) +#define USB_HWTXBUF_TXCHANADD_SHIFT (16U) +#define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) +/*! @} */ + +/*! @name HWRXBUF - RX Buffer Hardware Parameters */ +/*! @{ */ +#define USB_HWRXBUF_RXBURST_MASK (0xFFU) +#define USB_HWRXBUF_RXBURST_SHIFT (0U) +#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) +#define USB_HWRXBUF_RXADD_MASK (0xFF00U) +#define USB_HWRXBUF_RXADD_SHIFT (8U) +#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) +/*! @} */ + +/*! @name GPTIMER0LD - General Purpose Timer #0 Load */ +/*! @{ */ +#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ +/*! @{ */ +#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) +#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ +#define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) +#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) +/*! GPTRST + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD + */ +#define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) +#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN + * 0b0..Stop counting + * 0b1..Run + */ +#define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name GPTIMER1LD - General Purpose Timer #1 Load */ +/*! @{ */ +#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) +#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) +#define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) +/*! @} */ + +/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ +/*! @{ */ +#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) +#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) +#define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) +#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) +#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) +/*! GPTMODE + * 0b0..One Shot Mode + * 0b1..Repeat Mode + */ +#define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) +#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) +#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) +/*! GPTRST + * 0b0..No action + * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD + */ +#define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) +#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) +#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) +/*! GPTRUN + * 0b0..Stop counting + * 0b1..Run + */ +#define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK) +/*! @} */ + +/*! @name SBUSCFG - System Bus Config */ +/*! @{ */ +#define USB_SBUSCFG_AHBBRST_MASK (0x7U) +#define USB_SBUSCFG_AHBBRST_SHIFT (0U) +/*! AHBBRST + * 0b000..Incremental burst of unspecified length only + * 0b001..INCR4 burst, then single transfer + * 0b010..INCR8 burst, INCR4 burst, then single transfer + * 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + * 0b100..Reserved, don't use + * 0b101..INCR4 burst, then incremental burst of unspecified length + * 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length + * 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + */ +#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK) +/*! @} */ + +/*! @name CAPLENGTH - Capability Registers Length */ +/*! @{ */ +#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) +#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) +#define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) +/*! @} */ + +/*! @name HCIVERSION - Host Controller Interface Version */ +/*! @{ */ +#define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) +#define USB_HCIVERSION_HCIVERSION_SHIFT (0U) +#define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) +/*! @} */ + +/*! @name HCSPARAMS - Host Controller Structural Parameters */ +/*! @{ */ +#define USB_HCSPARAMS_N_PORTS_MASK (0xFU) +#define USB_HCSPARAMS_N_PORTS_SHIFT (0U) +#define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) +#define USB_HCSPARAMS_PPC_MASK (0x10U) +#define USB_HCSPARAMS_PPC_SHIFT (4U) +#define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK) +#define USB_HCSPARAMS_N_PCC_MASK (0xF00U) +#define USB_HCSPARAMS_N_PCC_SHIFT (8U) +#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) +#define USB_HCSPARAMS_N_CC_MASK (0xF000U) +#define USB_HCSPARAMS_N_CC_SHIFT (12U) +/*! N_CC + * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported. + * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported. + */ +#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) +#define USB_HCSPARAMS_PI_MASK (0x10000U) +#define USB_HCSPARAMS_PI_SHIFT (16U) +#define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK) +#define USB_HCSPARAMS_N_PTT_MASK (0xF00000U) +#define USB_HCSPARAMS_N_PTT_SHIFT (20U) +#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK) +#define USB_HCSPARAMS_N_TT_MASK (0xF000000U) +#define USB_HCSPARAMS_N_TT_SHIFT (24U) +#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) +/*! @} */ + +/*! @name HCCPARAMS - Host Controller Capability Parameters */ +/*! @{ */ +#define USB_HCCPARAMS_ADC_MASK (0x1U) +#define USB_HCCPARAMS_ADC_SHIFT (0U) +#define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) +#define USB_HCCPARAMS_PFL_MASK (0x2U) +#define USB_HCCPARAMS_PFL_SHIFT (1U) +#define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK) +#define USB_HCCPARAMS_ASP_MASK (0x4U) +#define USB_HCCPARAMS_ASP_SHIFT (2U) +#define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK) +#define USB_HCCPARAMS_IST_MASK (0xF0U) +#define USB_HCCPARAMS_IST_SHIFT (4U) +#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK) +#define USB_HCCPARAMS_EECP_MASK (0xFF00U) +#define USB_HCCPARAMS_EECP_SHIFT (8U) +#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) +/*! @} */ + +/*! @name DCIVERSION - Device Controller Interface Version */ +/*! @{ */ +#define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) +#define USB_DCIVERSION_DCIVERSION_SHIFT (0U) +#define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) +/*! @} */ + +/*! @name DCCPARAMS - Device Controller Capability Parameters */ +/*! @{ */ +#define USB_DCCPARAMS_DEN_MASK (0x1FU) +#define USB_DCCPARAMS_DEN_SHIFT (0U) +#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) +#define USB_DCCPARAMS_DC_MASK (0x80U) +#define USB_DCCPARAMS_DC_SHIFT (7U) +#define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK) +#define USB_DCCPARAMS_HC_MASK (0x100U) +#define USB_DCCPARAMS_HC_SHIFT (8U) +#define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) +/*! @} */ + +/*! @name USBCMD - USB Command Register */ +/*! @{ */ +#define USB_USBCMD_RS_MASK (0x1U) +#define USB_USBCMD_RS_SHIFT (0U) +#define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) +#define USB_USBCMD_RST_MASK (0x2U) +#define USB_USBCMD_RST_SHIFT (1U) +#define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK) +#define USB_USBCMD_FS_1_MASK (0xCU) +#define USB_USBCMD_FS_1_SHIFT (2U) +#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) +#define USB_USBCMD_PSE_MASK (0x10U) +#define USB_USBCMD_PSE_SHIFT (4U) +/*! PSE + * 0b0..Do not process the Periodic Schedule + * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule. + */ +#define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) +#define USB_USBCMD_ASE_MASK (0x20U) +#define USB_USBCMD_ASE_SHIFT (5U) +/*! ASE + * 0b0..Do not process the Asynchronous Schedule. + * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + */ +#define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) +#define USB_USBCMD_IAA_MASK (0x40U) +#define USB_USBCMD_IAA_SHIFT (6U) +#define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK) +#define USB_USBCMD_ASP_MASK (0x300U) +#define USB_USBCMD_ASP_SHIFT (8U) +#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK) +#define USB_USBCMD_ASPE_MASK (0x800U) +#define USB_USBCMD_ASPE_SHIFT (11U) +#define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK) +#define USB_USBCMD_ATDTW_MASK (0x1000U) +#define USB_USBCMD_ATDTW_SHIFT (12U) +#define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK) +#define USB_USBCMD_SUTW_MASK (0x2000U) +#define USB_USBCMD_SUTW_SHIFT (13U) +#define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) +#define USB_USBCMD_FS_2_MASK (0x8000U) +#define USB_USBCMD_FS_2_SHIFT (15U) +/*! FS_2 + * 0b0..1024 elements (4096 bytes) Default value + * 0b1..512 elements (2048 bytes) + */ +#define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) +#define USB_USBCMD_ITC_MASK (0xFF0000U) +#define USB_USBCMD_ITC_SHIFT (16U) +/*! ITC + * 0b00000000..Immediate (no threshold) + * 0b00000001..1 micro-frame + * 0b00000010..2 micro-frames + * 0b00000100..4 micro-frames + * 0b00001000..8 micro-frames + * 0b00010000..16 micro-frames + * 0b00100000..32 micro-frames + * 0b01000000..64 micro-frames + */ +#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK) +/*! @} */ + +/*! @name USBSTS - USB Status Register */ +/*! @{ */ +#define USB_USBSTS_UI_MASK (0x1U) +#define USB_USBSTS_UI_SHIFT (0U) +#define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) +#define USB_USBSTS_UEI_MASK (0x2U) +#define USB_USBSTS_UEI_SHIFT (1U) +#define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK) +#define USB_USBSTS_PCI_MASK (0x4U) +#define USB_USBSTS_PCI_SHIFT (2U) +#define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK) +#define USB_USBSTS_FRI_MASK (0x8U) +#define USB_USBSTS_FRI_SHIFT (3U) +#define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK) +#define USB_USBSTS_SEI_MASK (0x10U) +#define USB_USBSTS_SEI_SHIFT (4U) +#define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK) +#define USB_USBSTS_AAI_MASK (0x20U) +#define USB_USBSTS_AAI_SHIFT (5U) +#define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK) +#define USB_USBSTS_URI_MASK (0x40U) +#define USB_USBSTS_URI_SHIFT (6U) +#define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK) +#define USB_USBSTS_SRI_MASK (0x80U) +#define USB_USBSTS_SRI_SHIFT (7U) +#define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK) +#define USB_USBSTS_SLI_MASK (0x100U) +#define USB_USBSTS_SLI_SHIFT (8U) +#define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK) +#define USB_USBSTS_ULPII_MASK (0x400U) +#define USB_USBSTS_ULPII_SHIFT (10U) +#define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK) +#define USB_USBSTS_HCH_MASK (0x1000U) +#define USB_USBSTS_HCH_SHIFT (12U) +#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK) +#define USB_USBSTS_RCL_MASK (0x2000U) +#define USB_USBSTS_RCL_SHIFT (13U) +#define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK) +#define USB_USBSTS_PS_MASK (0x4000U) +#define USB_USBSTS_PS_SHIFT (14U) +#define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK) +#define USB_USBSTS_AS_MASK (0x8000U) +#define USB_USBSTS_AS_SHIFT (15U) +#define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK) +#define USB_USBSTS_NAKI_MASK (0x10000U) +#define USB_USBSTS_NAKI_SHIFT (16U) +#define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK) +#define USB_USBSTS_TI0_MASK (0x1000000U) +#define USB_USBSTS_TI0_SHIFT (24U) +#define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK) +#define USB_USBSTS_TI1_MASK (0x2000000U) +#define USB_USBSTS_TI1_SHIFT (25U) +#define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) +/*! @} */ + +/*! @name USBINTR - Interrupt Enable Register */ +/*! @{ */ +#define USB_USBINTR_UE_MASK (0x1U) +#define USB_USBINTR_UE_SHIFT (0U) +#define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) +#define USB_USBINTR_UEE_MASK (0x2U) +#define USB_USBINTR_UEE_SHIFT (1U) +#define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK) +#define USB_USBINTR_PCE_MASK (0x4U) +#define USB_USBINTR_PCE_SHIFT (2U) +#define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK) +#define USB_USBINTR_FRE_MASK (0x8U) +#define USB_USBINTR_FRE_SHIFT (3U) +#define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK) +#define USB_USBINTR_SEE_MASK (0x10U) +#define USB_USBINTR_SEE_SHIFT (4U) +#define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK) +#define USB_USBINTR_AAE_MASK (0x20U) +#define USB_USBINTR_AAE_SHIFT (5U) +#define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK) +#define USB_USBINTR_URE_MASK (0x40U) +#define USB_USBINTR_URE_SHIFT (6U) +#define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK) +#define USB_USBINTR_SRE_MASK (0x80U) +#define USB_USBINTR_SRE_SHIFT (7U) +#define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK) +#define USB_USBINTR_SLE_MASK (0x100U) +#define USB_USBINTR_SLE_SHIFT (8U) +#define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK) +#define USB_USBINTR_ULPIE_MASK (0x400U) +#define USB_USBINTR_ULPIE_SHIFT (10U) +#define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK) +#define USB_USBINTR_NAKE_MASK (0x10000U) +#define USB_USBINTR_NAKE_SHIFT (16U) +#define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK) +#define USB_USBINTR_UAIE_MASK (0x40000U) +#define USB_USBINTR_UAIE_SHIFT (18U) +#define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK) +#define USB_USBINTR_UPIE_MASK (0x80000U) +#define USB_USBINTR_UPIE_SHIFT (19U) +#define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK) +#define USB_USBINTR_TIE0_MASK (0x1000000U) +#define USB_USBINTR_TIE0_SHIFT (24U) +#define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK) +#define USB_USBINTR_TIE1_MASK (0x2000000U) +#define USB_USBINTR_TIE1_SHIFT (25U) +#define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) +/*! @} */ + +/*! @name FRINDEX - USB Frame Index */ +/*! @{ */ +#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) +#define USB_FRINDEX_FRINDEX_SHIFT (0U) +/*! FRINDEX + * 0b00000000000000..(1024) 12 + * 0b00000000000001..(512) 11 + * 0b00000000000010..(256) 10 + * 0b00000000000011..(128) 9 + * 0b00000000000100..(64) 8 + * 0b00000000000101..(32) 7 + * 0b00000000000110..(16) 6 + * 0b00000000000111..(8) 5 + */ +#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK) +/*! @} */ + +/*! @name DEVICEADDR - Device Address */ +/*! @{ */ +#define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) +#define USB_DEVICEADDR_USBADRA_SHIFT (24U) +#define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) +#define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) +#define USB_DEVICEADDR_USBADR_SHIFT (25U) +#define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) +/*! @} */ + +/*! @name PERIODICLISTBASE - Frame List Base Address */ +/*! @{ */ +#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) +#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) +#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) +/*! @} */ + +/*! @name ASYNCLISTADDR - Next Asynch. Address */ +/*! @{ */ +#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) +#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) +#define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) +/*! @} */ + +/*! @name ENDPTLISTADDR - Endpoint List Address */ +/*! @{ */ +#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) +#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) +#define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) +/*! @} */ + +/*! @name BURSTSIZE - Programmable Burst Size */ +/*! @{ */ +#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) +#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) +#define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) +#define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U) +#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) +#define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) +/*! @} */ + +/*! @name TXFILLTUNING - TX FIFO Fill Tuning */ +/*! @{ */ +#define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU) +#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) +#define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) +#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) +#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) +#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) +#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) +#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) +#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) +/*! @} */ + +/*! @name ENDPTNAK - Endpoint NAK */ +/*! @{ */ +#define USB_ENDPTNAK_EPRN_MASK (0xFFU) +#define USB_ENDPTNAK_EPRN_SHIFT (0U) +#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) +#define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) +#define USB_ENDPTNAK_EPTN_SHIFT (16U) +#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) +/*! @} */ + +/*! @name ENDPTNAKEN - Endpoint NAK Enable */ +/*! @{ */ +#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) +#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) +#define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) +#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) +#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) +#define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) +/*! @} */ + +/*! @name CONFIGFLAG - Configure Flag Register */ +/*! @{ */ +#define USB_CONFIGFLAG_CF_MASK (0x1U) +#define USB_CONFIGFLAG_CF_SHIFT (0U) +/*! CF + * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller. + * 0b1..Port routing control logic default-routes all ports to this host controller. + */ +#define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK) +/*! @} */ + +/*! @name PORTSC1 - Port Status & Control */ +/*! @{ */ +#define USB_PORTSC1_CCS_MASK (0x1U) +#define USB_PORTSC1_CCS_SHIFT (0U) +#define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) +#define USB_PORTSC1_CSC_MASK (0x2U) +#define USB_PORTSC1_CSC_SHIFT (1U) +#define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK) +#define USB_PORTSC1_PE_MASK (0x4U) +#define USB_PORTSC1_PE_SHIFT (2U) +#define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK) +#define USB_PORTSC1_PEC_MASK (0x8U) +#define USB_PORTSC1_PEC_SHIFT (3U) +#define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) +#define USB_PORTSC1_OCA_MASK (0x10U) +#define USB_PORTSC1_OCA_SHIFT (4U) +/*! OCA + * 0b1..This port currently has an over-current condition + * 0b0..This port does not have an over-current condition. + */ +#define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) +#define USB_PORTSC1_OCC_MASK (0x20U) +#define USB_PORTSC1_OCC_SHIFT (5U) +#define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK) +#define USB_PORTSC1_FPR_MASK (0x40U) +#define USB_PORTSC1_FPR_SHIFT (6U) +#define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK) +#define USB_PORTSC1_SUSP_MASK (0x80U) +#define USB_PORTSC1_SUSP_SHIFT (7U) +#define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK) +#define USB_PORTSC1_PR_MASK (0x100U) +#define USB_PORTSC1_PR_SHIFT (8U) +#define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK) +#define USB_PORTSC1_HSP_MASK (0x200U) +#define USB_PORTSC1_HSP_SHIFT (9U) +#define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) +#define USB_PORTSC1_LS_MASK (0xC00U) +#define USB_PORTSC1_LS_SHIFT (10U) +/*! LS + * 0b00..SE0 + * 0b10..J-state + * 0b01..K-state + * 0b11..Undefined + */ +#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) +#define USB_PORTSC1_PP_MASK (0x1000U) +#define USB_PORTSC1_PP_SHIFT (12U) +#define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK) +#define USB_PORTSC1_PO_MASK (0x2000U) +#define USB_PORTSC1_PO_SHIFT (13U) +#define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) +#define USB_PORTSC1_PIC_MASK (0xC000U) +#define USB_PORTSC1_PIC_SHIFT (14U) +/*! PIC + * 0b00..Port indicators are off + * 0b01..Amber + * 0b10..Green + * 0b11..Undefined + */ +#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) +#define USB_PORTSC1_PTC_MASK (0xF0000U) +#define USB_PORTSC1_PTC_SHIFT (16U) +/*! PTC + * 0b0000..TEST_MODE_DISABLE + * 0b0001..J_STATE + * 0b0010..K_STATE + * 0b0011..SE0 (host) / NAK (device) + * 0b0100..Packet + * 0b0101..FORCE_ENABLE_HS + * 0b0110..FORCE_ENABLE_FS + * 0b0111..FORCE_ENABLE_LS + */ +#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) +#define USB_PORTSC1_WKCN_MASK (0x100000U) +#define USB_PORTSC1_WKCN_SHIFT (20U) +#define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK) +#define USB_PORTSC1_WKDC_MASK (0x200000U) +#define USB_PORTSC1_WKDC_SHIFT (21U) +#define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK) +#define USB_PORTSC1_WKOC_MASK (0x400000U) +#define USB_PORTSC1_WKOC_SHIFT (22U) +#define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) +#define USB_PORTSC1_PHCD_MASK (0x800000U) +#define USB_PORTSC1_PHCD_SHIFT (23U) +/*! PHCD + * 0b1..Disable PHY clock + * 0b0..Enable PHY clock + */ +#define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) +#define USB_PORTSC1_PFSC_MASK (0x1000000U) +#define USB_PORTSC1_PFSC_SHIFT (24U) +/*! PFSC + * 0b1..Forced to full speed + * 0b0..Normal operation + */ +#define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) +#define USB_PORTSC1_PTS_2_MASK (0x2000000U) +#define USB_PORTSC1_PTS_2_SHIFT (25U) +#define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) +#define USB_PORTSC1_PSPD_MASK (0xC000000U) +#define USB_PORTSC1_PSPD_SHIFT (26U) +/*! PSPD + * 0b00..Full Speed + * 0b01..Low Speed + * 0b10..High Speed + * 0b11..Undefined + */ +#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) +#define USB_PORTSC1_PTW_MASK (0x10000000U) +#define USB_PORTSC1_PTW_SHIFT (28U) +/*! PTW + * 0b0..Select the 8-bit UTMI interface [60MHz] + * 0b1..Select the 16-bit UTMI interface [30MHz] + */ +#define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) +#define USB_PORTSC1_STS_MASK (0x20000000U) +#define USB_PORTSC1_STS_SHIFT (29U) +#define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK) +#define USB_PORTSC1_PTS_1_MASK (0xC0000000U) +#define USB_PORTSC1_PTS_1_SHIFT (30U) +#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) +/*! @} */ + +/*! @name OTGSC - On-The-Go Status & control */ +/*! @{ */ +#define USB_OTGSC_VD_MASK (0x1U) +#define USB_OTGSC_VD_SHIFT (0U) +#define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) +#define USB_OTGSC_VC_MASK (0x2U) +#define USB_OTGSC_VC_SHIFT (1U) +#define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK) +#define USB_OTGSC_OT_MASK (0x8U) +#define USB_OTGSC_OT_SHIFT (3U) +#define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK) +#define USB_OTGSC_DP_MASK (0x10U) +#define USB_OTGSC_DP_SHIFT (4U) +#define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK) +#define USB_OTGSC_IDPU_MASK (0x20U) +#define USB_OTGSC_IDPU_SHIFT (5U) +#define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK) +#define USB_OTGSC_ID_MASK (0x100U) +#define USB_OTGSC_ID_SHIFT (8U) +#define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK) +#define USB_OTGSC_AVV_MASK (0x200U) +#define USB_OTGSC_AVV_SHIFT (9U) +#define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK) +#define USB_OTGSC_ASV_MASK (0x400U) +#define USB_OTGSC_ASV_SHIFT (10U) +#define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK) +#define USB_OTGSC_BSV_MASK (0x800U) +#define USB_OTGSC_BSV_SHIFT (11U) +#define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK) +#define USB_OTGSC_BSE_MASK (0x1000U) +#define USB_OTGSC_BSE_SHIFT (12U) +#define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK) +#define USB_OTGSC_TOG_1MS_MASK (0x2000U) +#define USB_OTGSC_TOG_1MS_SHIFT (13U) +#define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK) +#define USB_OTGSC_DPS_MASK (0x4000U) +#define USB_OTGSC_DPS_SHIFT (14U) +#define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK) +#define USB_OTGSC_IDIS_MASK (0x10000U) +#define USB_OTGSC_IDIS_SHIFT (16U) +#define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK) +#define USB_OTGSC_AVVIS_MASK (0x20000U) +#define USB_OTGSC_AVVIS_SHIFT (17U) +#define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK) +#define USB_OTGSC_ASVIS_MASK (0x40000U) +#define USB_OTGSC_ASVIS_SHIFT (18U) +#define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK) +#define USB_OTGSC_BSVIS_MASK (0x80000U) +#define USB_OTGSC_BSVIS_SHIFT (19U) +#define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK) +#define USB_OTGSC_BSEIS_MASK (0x100000U) +#define USB_OTGSC_BSEIS_SHIFT (20U) +#define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK) +#define USB_OTGSC_STATUS_1MS_MASK (0x200000U) +#define USB_OTGSC_STATUS_1MS_SHIFT (21U) +#define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK) +#define USB_OTGSC_DPIS_MASK (0x400000U) +#define USB_OTGSC_DPIS_SHIFT (22U) +#define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK) +#define USB_OTGSC_IDIE_MASK (0x1000000U) +#define USB_OTGSC_IDIE_SHIFT (24U) +#define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK) +#define USB_OTGSC_AVVIE_MASK (0x2000000U) +#define USB_OTGSC_AVVIE_SHIFT (25U) +#define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK) +#define USB_OTGSC_ASVIE_MASK (0x4000000U) +#define USB_OTGSC_ASVIE_SHIFT (26U) +#define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK) +#define USB_OTGSC_BSVIE_MASK (0x8000000U) +#define USB_OTGSC_BSVIE_SHIFT (27U) +#define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK) +#define USB_OTGSC_BSEIE_MASK (0x10000000U) +#define USB_OTGSC_BSEIE_SHIFT (28U) +#define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK) +#define USB_OTGSC_EN_1MS_MASK (0x20000000U) +#define USB_OTGSC_EN_1MS_SHIFT (29U) +#define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK) +#define USB_OTGSC_DPIE_MASK (0x40000000U) +#define USB_OTGSC_DPIE_SHIFT (30U) +#define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) +/*! @} */ + +/*! @name USBMODE - USB Device Mode */ +/*! @{ */ +#define USB_USBMODE_CM_MASK (0x3U) +#define USB_USBMODE_CM_SHIFT (0U) +/*! CM + * 0b00..Idle [Default for combination host/device] + * 0b01..Reserved + * 0b10..Device Controller [Default for device only controller] + * 0b11..Host Controller [Default for host only controller] + */ +#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) +#define USB_USBMODE_ES_MASK (0x4U) +#define USB_USBMODE_ES_SHIFT (2U) +/*! ES + * 0b0..Little Endian [Default] + * 0b1..Big Endian + */ +#define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) +#define USB_USBMODE_SLOM_MASK (0x8U) +#define USB_USBMODE_SLOM_SHIFT (3U) +/*! SLOM + * 0b0..Setup Lockouts On (default); + * 0b1..Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register . + */ +#define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) +#define USB_USBMODE_SDIS_MASK (0x10U) +#define USB_USBMODE_SDIS_SHIFT (4U) +#define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) +/*! @} */ + +/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ +/*! @{ */ +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) +#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) +/*! @} */ + +/*! @name ENDPTPRIME - Endpoint Prime */ +/*! @{ */ +#define USB_ENDPTPRIME_PERB_MASK (0xFFU) +#define USB_ENDPTPRIME_PERB_SHIFT (0U) +#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) +#define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) +#define USB_ENDPTPRIME_PETB_SHIFT (16U) +#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) +/*! @} */ + +/*! @name ENDPTFLUSH - Endpoint Flush */ +/*! @{ */ +#define USB_ENDPTFLUSH_FERB_MASK (0xFFU) +#define USB_ENDPTFLUSH_FERB_SHIFT (0U) +#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) +#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) +#define USB_ENDPTFLUSH_FETB_SHIFT (16U) +#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) +/*! @} */ + +/*! @name ENDPTSTAT - Endpoint Status */ +/*! @{ */ +#define USB_ENDPTSTAT_ERBR_MASK (0xFFU) +#define USB_ENDPTSTAT_ERBR_SHIFT (0U) +#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) +#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) +#define USB_ENDPTSTAT_ETBR_SHIFT (16U) +#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) +/*! @} */ + +/*! @name ENDPTCOMPLETE - Endpoint Complete */ +/*! @{ */ +#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) +#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) +#define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) +#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) +#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) +#define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL0 - Endpoint Control0 */ +/*! @{ */ +#define USB_ENDPTCTRL0_RXS_MASK (0x1U) +#define USB_ENDPTCTRL0_RXS_SHIFT (0U) +#define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) +#define USB_ENDPTCTRL0_RXT_MASK (0xCU) +#define USB_ENDPTCTRL0_RXT_SHIFT (2U) +#define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK) +#define USB_ENDPTCTRL0_RXE_MASK (0x80U) +#define USB_ENDPTCTRL0_RXE_SHIFT (7U) +#define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK) +#define USB_ENDPTCTRL0_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL0_TXS_SHIFT (16U) +#define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK) +#define USB_ENDPTCTRL0_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL0_TXT_SHIFT (18U) +#define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK) +#define USB_ENDPTCTRL0_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL0_TXE_SHIFT (23U) +#define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) +/*! @} */ + +/*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ +/*! @{ */ +#define USB_ENDPTCTRL_RXS_MASK (0x1U) +#define USB_ENDPTCTRL_RXS_SHIFT (0U) +#define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK) +#define USB_ENDPTCTRL_RXD_MASK (0x2U) +#define USB_ENDPTCTRL_RXD_SHIFT (1U) +#define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK) +#define USB_ENDPTCTRL_RXT_MASK (0xCU) +#define USB_ENDPTCTRL_RXT_SHIFT (2U) +#define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK) +#define USB_ENDPTCTRL_RXI_MASK (0x20U) +#define USB_ENDPTCTRL_RXI_SHIFT (5U) +#define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK) +#define USB_ENDPTCTRL_RXR_MASK (0x40U) +#define USB_ENDPTCTRL_RXR_SHIFT (6U) +#define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK) +#define USB_ENDPTCTRL_RXE_MASK (0x80U) +#define USB_ENDPTCTRL_RXE_SHIFT (7U) +#define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK) +#define USB_ENDPTCTRL_TXS_MASK (0x10000U) +#define USB_ENDPTCTRL_TXS_SHIFT (16U) +#define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK) +#define USB_ENDPTCTRL_TXD_MASK (0x20000U) +#define USB_ENDPTCTRL_TXD_SHIFT (17U) +#define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK) +#define USB_ENDPTCTRL_TXT_MASK (0xC0000U) +#define USB_ENDPTCTRL_TXT_SHIFT (18U) +#define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK) +#define USB_ENDPTCTRL_TXI_MASK (0x200000U) +#define USB_ENDPTCTRL_TXI_SHIFT (21U) +#define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK) +#define USB_ENDPTCTRL_TXR_MASK (0x400000U) +#define USB_ENDPTCTRL_TXR_SHIFT (22U) +#define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK) +#define USB_ENDPTCTRL_TXE_MASK (0x800000U) +#define USB_ENDPTCTRL_TXE_SHIFT (23U) +#define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK) +/*! @} */ + +/* The count of USB_ENDPTCTRL */ +#define USB_ENDPTCTRL_COUNT (7U) + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB1 base address */ +#define USB1_BASE (0x402E0000u) +/** Peripheral USB1 base pointer */ +#define USB1 ((USB_Type *)USB1_BASE) +/** Peripheral USB2 base address */ +#define USB2_BASE (0x402E0200u) +/** Peripheral USB2 base pointer */ +#define USB2 ((USB_Type *)USB2_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { 0u, USB1_BASE, USB2_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { (USB_Type *)0u, USB1, USB2 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn } +/* Backward compatibility */ +#define GPTIMER0CTL GPTIMER0CTRL +#define GPTIMER1CTL GPTIMER1CTRL +#define USB_SBUSCFG SBUSCFG +#define EPLISTADDR ENDPTLISTADDR +#define EPSETUPSR ENDPTSETUPSTAT +#define EPPRIME ENDPTPRIME +#define EPFLUSH ENDPTFLUSH +#define EPSR ENDPTSTAT +#define EPCOMPLETE ENDPTCOMPLETE +#define EPCR ENDPTCTRL +#define EPCR0 ENDPTCTRL0 +#define USBHS_ID_ID_MASK USB_ID_ID_MASK +#define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT +#define USBHS_ID_ID(x) USB_ID_ID(x) +#define USBHS_ID_NID_MASK USB_ID_NID_MASK +#define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT +#define USBHS_ID_NID(x) USB_ID_NID(x) +#define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK +#define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT +#define USBHS_ID_REVISION(x) USB_ID_REVISION(x) +#define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK +#define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT +#define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x) +#define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK +#define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT +#define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x) +#define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK +#define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT +#define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x) +#define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK +#define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT +#define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x) +#define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK +#define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT +#define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x) +#define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK +#define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT +#define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x) +#define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK +#define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT +#define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x) +#define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK +#define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT +#define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x) +#define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK +#define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT +#define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x) +#define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK +#define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT +#define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x) +#define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK +#define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT +#define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x) +#define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK +#define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT +#define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x) +#define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK +#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x) +#define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK +#define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x) +#define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK +#define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x) +#define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK +#define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x) +#define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK +#define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT +#define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x) +#define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK +#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT +#define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x) +#define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK +#define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT +#define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x) +#define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK +#define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT +#define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x) +#define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK +#define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT +#define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x) +#define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK +#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT +#define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x) +#define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x) +#define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK +#define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT +#define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x) +#define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK +#define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT +#define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x) +#define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK +#define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT +#define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x) +#define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK +#define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT +#define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x) +#define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK +#define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT +#define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x) +#define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK +#define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT +#define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x) +#define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK +#define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT +#define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x) +#define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK +#define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT +#define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x) +#define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK +#define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT +#define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x) +#define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK +#define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT +#define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x) +#define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK +#define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT +#define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x) +#define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK +#define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT +#define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x) +#define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK +#define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT +#define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x) +#define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK +#define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT +#define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x) +#define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK +#define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT +#define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x) +#define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK +#define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT +#define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x) +#define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK +#define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT +#define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x) +#define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK +#define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT +#define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x) +#define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK +#define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT +#define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x) +#define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK +#define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT +#define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x) +#define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK +#define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT +#define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x) +#define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK +#define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT +#define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x) +#define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK +#define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT +#define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x) +#define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK +#define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT +#define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x) +#define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK +#define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT +#define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x) +#define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK +#define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT +#define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x) +#define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK +#define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT +#define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x) +#define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK +#define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT +#define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x) +#define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK +#define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT +#define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x) +#define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK +#define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT +#define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x) +#define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK +#define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT +#define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x) +#define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK +#define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT +#define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x) +#define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK +#define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT +#define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x) +#define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK +#define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT +#define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x) +#define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK +#define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT +#define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x) +#define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK +#define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT +#define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x) +#define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK +#define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT +#define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x) +#define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK +#define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT +#define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x) +#define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK +#define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT +#define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x) +#define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK +#define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT +#define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x) +#define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK +#define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT +#define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x) +#define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK +#define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT +#define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x) +#define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK +#define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT +#define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x) +#define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK +#define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT +#define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x) +#define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK +#define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT +#define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x) +#define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK +#define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT +#define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x) +#define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK +#define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT +#define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x) +#define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK +#define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT +#define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x) +#define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK +#define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT +#define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x) +#define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK +#define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT +#define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x) +#define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK +#define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT +#define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x) +#define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK +#define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT +#define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x) +#define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK +#define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT +#define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x) +#define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK +#define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT +#define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x) +#define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK +#define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT +#define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x) +#define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK +#define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT +#define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x) +#define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK +#define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT +#define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x) +#define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK +#define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT +#define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x) +#define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK +#define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT +#define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x) +#define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK +#define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT +#define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x) +#define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK +#define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT +#define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x) +#define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK +#define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT +#define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x) +#define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK +#define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT +#define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x) +#define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK +#define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT +#define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x) +#define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK +#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT +#define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x) +#define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK +#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT +#define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x) +#define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK +#define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT +#define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x) +#define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK +#define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT +#define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x) +#define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK +#define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT +#define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x) +#define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK +#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT +#define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x) +#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK +#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT +#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x) +#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK +#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT +#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x) +#define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK +#define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT +#define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x) +#define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK +#define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT +#define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x) +#define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK +#define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT +#define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x) +#define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK +#define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT +#define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x) +#define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK +#define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT +#define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x) +#define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK +#define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT +#define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x) +#define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK +#define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT +#define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x) +#define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK +#define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT +#define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x) +#define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK +#define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT +#define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x) +#define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK +#define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT +#define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x) +#define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK +#define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT +#define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x) +#define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK +#define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT +#define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x) +#define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK +#define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT +#define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x) +#define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK +#define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT +#define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x) +#define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK +#define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT +#define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x) +#define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK +#define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT +#define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x) +#define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK +#define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT +#define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x) +#define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK +#define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT +#define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x) +#define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK +#define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT +#define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x) +#define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK +#define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT +#define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x) +#define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK +#define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT +#define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x) +#define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK +#define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT +#define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x) +#define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK +#define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT +#define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x) +#define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK +#define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT +#define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x) +#define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK +#define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT +#define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x) +#define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK +#define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT +#define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x) +#define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK +#define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT +#define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x) +#define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK +#define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT +#define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x) +#define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK +#define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT +#define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x) +#define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK +#define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT +#define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x) +#define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK +#define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT +#define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x) +#define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK +#define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT +#define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x) +#define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK +#define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT +#define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x) +#define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK +#define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT +#define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x) +#define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK +#define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT +#define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x) +#define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK +#define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT +#define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x) +#define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK +#define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT +#define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x) +#define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK +#define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT +#define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x) +#define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK +#define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT +#define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x) +#define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK +#define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT +#define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x) +#define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK +#define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT +#define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x) +#define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK +#define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT +#define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x) +#define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK +#define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT +#define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x) +#define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK +#define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT +#define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x) +#define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK +#define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT +#define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x) +#define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK +#define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT +#define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x) +#define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK +#define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT +#define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x) +#define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK +#define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT +#define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x) +#define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK +#define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT +#define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x) +#define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK +#define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT +#define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x) +#define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK +#define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT +#define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x) +#define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK +#define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT +#define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x) +#define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK +#define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT +#define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x) +#define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK +#define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT +#define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x) +#define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK +#define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT +#define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x) +#define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK +#define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT +#define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x) +#define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK +#define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT +#define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x) +#define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK +#define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT +#define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x) +#define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK +#define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT +#define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x) +#define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK +#define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT +#define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x) +#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK +#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT +#define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) +#define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK +#define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT +#define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x) +#define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK +#define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT +#define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x) +#define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK +#define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT +#define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x) +#define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK +#define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT +#define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x) +#define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK +#define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT +#define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x) +#define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK +#define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT +#define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x) +#define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK +#define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT +#define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x) +#define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK +#define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT +#define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x) +#define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK +#define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT +#define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x) +#define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK +#define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT +#define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x) +#define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK +#define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT +#define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x) +#define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK +#define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT +#define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x) +#define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK +#define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT +#define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x) +#define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK +#define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT +#define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x) +#define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK +#define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT +#define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x) +#define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK +#define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT +#define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x) +#define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK +#define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT +#define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x) +#define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK +#define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT +#define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x) +#define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK +#define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT +#define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x) +#define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK +#define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT +#define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x) +#define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK +#define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT +#define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x) +#define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK +#define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT +#define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x) +#define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK +#define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT +#define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x) +#define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK +#define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT +#define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x) +#define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK +#define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT +#define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x) +#define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK +#define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT +#define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x) +#define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT +#define USBHS_Type USB_Type +#define USBHS_BASE_ADDRS { USB1_BASE, USB2_BASE } +#define USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn } +#define USBHS_IRQHandler USB_OTG1_IRQHandler + + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBNC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer + * @{ + */ + +/** USBNC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __IO uint32_t USB_OTGn_CTRL; /**< USB OTG1 Control Register..USB OTG2 Control Register, offset: 0x800 */ + uint8_t RESERVED_1[20]; + __IO uint32_t USB_OTGn_PHY_CTRL_0; /**< OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register, offset: 0x818 */ +} USBNC_Type; + +/* ---------------------------------------------------------------------------- + -- USBNC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Masks USBNC Register Masks + * @{ + */ + +/*! @name USB_OTGn_CTRL - USB OTG1 Control Register..USB OTG2 Control Register */ +/*! @{ */ +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U) +/*! OVER_CUR_DIS + * 0b1..Disables overcurrent detection + * 0b0..Enables overcurrent detection + */ +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U) +/*! OVER_CUR_POL + * 0b1..Low active (low on this signal represents an overcurrent condition) + * 0b0..High active (high on this signal represents an overcurrent condition) + */ +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK) +#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U) +#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U) +/*! PWR_POL + * 0b1..PMIC Power Pin is High active. + * 0b0..PMIC Power Pin is Low active. + */ +#define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK) +#define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U) +#define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U) +/*! WIE + * 0b1..Interrupt Enabled + * 0b0..Interrupt Disabled + */ +#define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U) +/*! WKUP_SW_EN + * 0b1..Enable + * 0b0..Disable + */ +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U) +/*! WKUP_SW + * 0b1..Force wake-up + * 0b0..Inactive + */ +#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U) +/*! WKUP_ID_EN + * 0b1..Enable + * 0b0..Disable + */ +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U) +/*! WKUP_VBUS_EN + * 0b1..Enable + * 0b0..Disable + */ +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U) +/*! WKUP_DPDM_EN + * 0b1..(Default) DPDM changes wake-up to be enabled, it is for device only. + * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0. + */ +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK) +#define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U) +#define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U) +/*! WIR + * 0b1..Wake-up Interrupt Request received + * 0b0..No wake-up interrupt request received + */ +#define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK) +/*! @} */ + +/*! @name USB_OTGn_PHY_CTRL_0 - OTG1 UTMI PHY Control 0 Register..OTG2 UTMI PHY Control 0 Register */ +/*! @{ */ +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK (0x80000000U) +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT (31U) +/*! UTMI_CLK_VLD + * 0b1..Valid + * 0b0..Invalid + */ +#define USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_SHIFT)) & USBNC_USB_OTGn_PHY_CTRL_0_UTMI_CLK_VLD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBNC_Register_Masks */ + + +/* USBNC - Peripheral instance base addresses */ +/** Peripheral USBNC1 base address */ +#define USBNC1_BASE (0x402E0000u) +/** Peripheral USBNC1 base pointer */ +#define USBNC1 ((USBNC_Type *)USBNC1_BASE) +/** Peripheral USBNC2 base address */ +#define USBNC2_BASE (0x402E0004u) +/** Peripheral USBNC2 base pointer */ +#define USBNC2 ((USBNC_Type *)USBNC2_BASE) +/** Array initializer of USBNC peripheral base addresses */ +#define USBNC_BASE_ADDRS { 0u, USBNC1_BASE, USBNC2_BASE } +/** Array initializer of USBNC peripheral base pointers */ +#define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC1, USBNC2 } + +/*! + * @} + */ /* end of group USBNC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USBPHY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer + * @{ + */ + +/** USBPHY - Register Layout Typedef */ +typedef struct { + __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */ + __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */ + __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */ + __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */ + __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */ + __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */ + __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */ + __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */ + __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */ + __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */ + __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */ + __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */ + __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */ + __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ + __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ + __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ + __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ + uint8_t RESERVED_0[12]; + __IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50 */ + __IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */ + __IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */ + __IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */ + __I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */ + uint8_t RESERVED_1[12]; + __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ + __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ + __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ + __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ + __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ +} USBPHY_Type; + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/*! @name PWD - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_RSVD0_SHIFT (0U) +#define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD0_SHIFT)) & USBPHY_PWD_RSVD0_MASK) +#define USBPHY_PWD_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) +#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) +#define USBPHY_PWD_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_RSVD1_SHIFT (13U) +#define USBPHY_PWD_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD1_SHIFT)) & USBPHY_PWD_RSVD1_MASK) +#define USBPHY_PWD_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) +#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) +#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) +#define USBPHY_PWD_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK) +#define USBPHY_PWD_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_RSVD2_SHIFT (21U) +#define USBPHY_PWD_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RSVD2_SHIFT)) & USBPHY_PWD_RSVD2_MASK) +/*! @} */ + +/*! @name PWD_SET - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_SET_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_SET_RSVD0_SHIFT (0U) +#define USBPHY_PWD_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD0_SHIFT)) & USBPHY_PWD_SET_RSVD0_MASK) +#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) +#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) +#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) +#define USBPHY_PWD_SET_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_SET_RSVD1_SHIFT (13U) +#define USBPHY_PWD_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD1_SHIFT)) & USBPHY_PWD_SET_RSVD1_MASK) +#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) +#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) +#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) +#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) +#define USBPHY_PWD_SET_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_SET_RSVD2_SHIFT (21U) +#define USBPHY_PWD_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RSVD2_SHIFT)) & USBPHY_PWD_SET_RSVD2_MASK) +/*! @} */ + +/*! @name PWD_CLR - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_CLR_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_CLR_RSVD0_SHIFT (0U) +#define USBPHY_PWD_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD0_SHIFT)) & USBPHY_PWD_CLR_RSVD0_MASK) +#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) +#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) +#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) +#define USBPHY_PWD_CLR_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_CLR_RSVD1_SHIFT (13U) +#define USBPHY_PWD_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD1_SHIFT)) & USBPHY_PWD_CLR_RSVD1_MASK) +#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) +#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) +#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) +#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) +#define USBPHY_PWD_CLR_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_CLR_RSVD2_SHIFT (21U) +#define USBPHY_PWD_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RSVD2_SHIFT)) & USBPHY_PWD_CLR_RSVD2_MASK) +/*! @} */ + +/*! @name PWD_TOG - USB PHY Power-Down Register */ +/*! @{ */ +#define USBPHY_PWD_TOG_RSVD0_MASK (0x3FFU) +#define USBPHY_PWD_TOG_RSVD0_SHIFT (0U) +#define USBPHY_PWD_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD0_SHIFT)) & USBPHY_PWD_TOG_RSVD0_MASK) +#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) +#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) +#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) +#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) +#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) +#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) +#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) +#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) +#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) +#define USBPHY_PWD_TOG_RSVD1_MASK (0x1E000U) +#define USBPHY_PWD_TOG_RSVD1_SHIFT (13U) +#define USBPHY_PWD_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD1_SHIFT)) & USBPHY_PWD_TOG_RSVD1_MASK) +#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) +#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) +#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) +#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) +#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) +#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) +#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) +#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) +#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) +#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) +#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) +#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) +#define USBPHY_PWD_TOG_RSVD2_MASK (0xFFE00000U) +#define USBPHY_PWD_TOG_RSVD2_SHIFT (21U) +#define USBPHY_PWD_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RSVD2_SHIFT)) & USBPHY_PWD_TOG_RSVD2_MASK) +/*! @} */ + +/*! @name TX - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_D_CAL_MASK (0xFU) +#define USBPHY_TX_D_CAL_SHIFT (0U) +#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) +#define USBPHY_TX_RSVD0_MASK (0xF0U) +#define USBPHY_TX_RSVD0_SHIFT (4U) +#define USBPHY_TX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD0_SHIFT)) & USBPHY_TX_RSVD0_MASK) +#define USBPHY_TX_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK) +#define USBPHY_TX_RSVD1_MASK (0xF000U) +#define USBPHY_TX_RSVD1_SHIFT (12U) +#define USBPHY_TX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD1_SHIFT)) & USBPHY_TX_RSVD1_MASK) +#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) +#define USBPHY_TX_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_RSVD2_SHIFT (20U) +#define USBPHY_TX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD2_SHIFT)) & USBPHY_TX_RSVD2_MASK) +#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_RSVD5_SHIFT (29U) +#define USBPHY_TX_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_RSVD5_SHIFT)) & USBPHY_TX_RSVD5_MASK) +/*! @} */ + +/*! @name TX_SET - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_SET_D_CAL_MASK (0xFU) +#define USBPHY_TX_SET_D_CAL_SHIFT (0U) +#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) +#define USBPHY_TX_SET_RSVD0_MASK (0xF0U) +#define USBPHY_TX_SET_RSVD0_SHIFT (4U) +#define USBPHY_TX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD0_SHIFT)) & USBPHY_TX_SET_RSVD0_MASK) +#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK) +#define USBPHY_TX_SET_RSVD1_MASK (0xF000U) +#define USBPHY_TX_SET_RSVD1_SHIFT (12U) +#define USBPHY_TX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD1_SHIFT)) & USBPHY_TX_SET_RSVD1_MASK) +#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) +#define USBPHY_TX_SET_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_SET_RSVD2_SHIFT (20U) +#define USBPHY_TX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD2_SHIFT)) & USBPHY_TX_SET_RSVD2_MASK) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_SET_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_SET_RSVD5_SHIFT (29U) +#define USBPHY_TX_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_RSVD5_SHIFT)) & USBPHY_TX_SET_RSVD5_MASK) +/*! @} */ + +/*! @name TX_CLR - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_CLR_D_CAL_MASK (0xFU) +#define USBPHY_TX_CLR_D_CAL_SHIFT (0U) +#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) +#define USBPHY_TX_CLR_RSVD0_MASK (0xF0U) +#define USBPHY_TX_CLR_RSVD0_SHIFT (4U) +#define USBPHY_TX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD0_SHIFT)) & USBPHY_TX_CLR_RSVD0_MASK) +#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK) +#define USBPHY_TX_CLR_RSVD1_MASK (0xF000U) +#define USBPHY_TX_CLR_RSVD1_SHIFT (12U) +#define USBPHY_TX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD1_SHIFT)) & USBPHY_TX_CLR_RSVD1_MASK) +#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) +#define USBPHY_TX_CLR_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_CLR_RSVD2_SHIFT (20U) +#define USBPHY_TX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD2_SHIFT)) & USBPHY_TX_CLR_RSVD2_MASK) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_CLR_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_CLR_RSVD5_SHIFT (29U) +#define USBPHY_TX_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_RSVD5_SHIFT)) & USBPHY_TX_CLR_RSVD5_MASK) +/*! @} */ + +/*! @name TX_TOG - USB PHY Transmitter Control Register */ +/*! @{ */ +#define USBPHY_TX_TOG_D_CAL_MASK (0xFU) +#define USBPHY_TX_TOG_D_CAL_SHIFT (0U) +#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) +#define USBPHY_TX_TOG_RSVD0_MASK (0xF0U) +#define USBPHY_TX_TOG_RSVD0_SHIFT (4U) +#define USBPHY_TX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD0_SHIFT)) & USBPHY_TX_TOG_RSVD0_MASK) +#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U) +#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK) +#define USBPHY_TX_TOG_RSVD1_MASK (0xF000U) +#define USBPHY_TX_TOG_RSVD1_SHIFT (12U) +#define USBPHY_TX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD1_SHIFT)) & USBPHY_TX_TOG_RSVD1_MASK) +#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) +#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) +#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) +#define USBPHY_TX_TOG_RSVD2_MASK (0x3F00000U) +#define USBPHY_TX_TOG_RSVD2_SHIFT (20U) +#define USBPHY_TX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD2_SHIFT)) & USBPHY_TX_TOG_RSVD2_MASK) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U) +#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK) +#define USBPHY_TX_TOG_RSVD5_MASK (0xE0000000U) +#define USBPHY_TX_TOG_RSVD5_SHIFT (29U) +#define USBPHY_TX_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_RSVD5_SHIFT)) & USBPHY_TX_TOG_RSVD5_MASK) +/*! @} */ + +/*! @name RX - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_ENVADJ_MASK (0x7U) +#define USBPHY_RX_ENVADJ_SHIFT (0U) +#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) +#define USBPHY_RX_RSVD0_MASK (0x8U) +#define USBPHY_RX_RSVD0_SHIFT (3U) +#define USBPHY_RX_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD0_SHIFT)) & USBPHY_RX_RSVD0_MASK) +#define USBPHY_RX_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) +#define USBPHY_RX_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_RSVD1_SHIFT (7U) +#define USBPHY_RX_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD1_SHIFT)) & USBPHY_RX_RSVD1_MASK) +#define USBPHY_RX_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK) +#define USBPHY_RX_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_RSVD2_SHIFT (23U) +#define USBPHY_RX_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RSVD2_SHIFT)) & USBPHY_RX_RSVD2_MASK) +/*! @} */ + +/*! @name RX_SET - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_SET_ENVADJ_MASK (0x7U) +#define USBPHY_RX_SET_ENVADJ_SHIFT (0U) +#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) +#define USBPHY_RX_SET_RSVD0_MASK (0x8U) +#define USBPHY_RX_SET_RSVD0_SHIFT (3U) +#define USBPHY_RX_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD0_SHIFT)) & USBPHY_RX_SET_RSVD0_MASK) +#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) +#define USBPHY_RX_SET_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_SET_RSVD1_SHIFT (7U) +#define USBPHY_RX_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD1_SHIFT)) & USBPHY_RX_SET_RSVD1_MASK) +#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) +#define USBPHY_RX_SET_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_SET_RSVD2_SHIFT (23U) +#define USBPHY_RX_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RSVD2_SHIFT)) & USBPHY_RX_SET_RSVD2_MASK) +/*! @} */ + +/*! @name RX_CLR - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) +#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) +#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) +#define USBPHY_RX_CLR_RSVD0_MASK (0x8U) +#define USBPHY_RX_CLR_RSVD0_SHIFT (3U) +#define USBPHY_RX_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD0_SHIFT)) & USBPHY_RX_CLR_RSVD0_MASK) +#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) +#define USBPHY_RX_CLR_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_CLR_RSVD1_SHIFT (7U) +#define USBPHY_RX_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD1_SHIFT)) & USBPHY_RX_CLR_RSVD1_MASK) +#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) +#define USBPHY_RX_CLR_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_CLR_RSVD2_SHIFT (23U) +#define USBPHY_RX_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RSVD2_SHIFT)) & USBPHY_RX_CLR_RSVD2_MASK) +/*! @} */ + +/*! @name RX_TOG - USB PHY Receiver Control Register */ +/*! @{ */ +#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) +#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) +#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) +#define USBPHY_RX_TOG_RSVD0_MASK (0x8U) +#define USBPHY_RX_TOG_RSVD0_SHIFT (3U) +#define USBPHY_RX_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD0_SHIFT)) & USBPHY_RX_TOG_RSVD0_MASK) +#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) +#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) +#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) +#define USBPHY_RX_TOG_RSVD1_MASK (0x3FFF80U) +#define USBPHY_RX_TOG_RSVD1_SHIFT (7U) +#define USBPHY_RX_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD1_SHIFT)) & USBPHY_RX_TOG_RSVD1_MASK) +#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) +#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) +#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) +#define USBPHY_RX_TOG_RSVD2_MASK (0xFF800000U) +#define USBPHY_RX_TOG_RSVD2_SHIFT (23U) +#define USBPHY_RX_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RSVD2_SHIFT)) & USBPHY_RX_TOG_RSVD2_MASK) +/*! @} */ + +/*! @name CTRL - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RSVD1_SHIFT)) & USBPHY_CTRL_RSVD1_MASK) +#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) +#define USBPHY_CTRL_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_SET - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_SET_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_SET_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_SET_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_SET_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_SET_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_SET_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RSVD1_SHIFT)) & USBPHY_CTRL_SET_RSVD1_MASK) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) +#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_CLR - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_CLR_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_CLR_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_CLR_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_CLR_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_CLR_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RSVD1_SHIFT)) & USBPHY_CTRL_CLR_RSVD1_MASK) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) +#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) +/*! @} */ + +/*! @name CTRL_TOG - USB PHY General Control Register */ +/*! @{ */ +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK (0x2000U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT (13U) +#define USBPHY_CTRL_TOG_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_TOG_DATA_ON_LRADC_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK (0x40000U) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT (18U) +#define USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_SHIFT)) & USBPHY_CTRL_TOG_ENAUTO_PWRON_PLL_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) +#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) +#define USBPHY_CTRL_TOG_RSVD1_MASK (0x6000000U) +#define USBPHY_CTRL_TOG_RSVD1_SHIFT (25U) +#define USBPHY_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RSVD1_SHIFT)) & USBPHY_CTRL_TOG_RSVD1_MASK) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) +#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) +#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) +#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) +#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) +#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) +/*! @} */ + +/*! @name STATUS - USB PHY Status Register */ +/*! @{ */ +#define USBPHY_STATUS_RSVD0_MASK (0x7U) +#define USBPHY_STATUS_RSVD0_SHIFT (0U) +#define USBPHY_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD0_SHIFT)) & USBPHY_STATUS_RSVD0_MASK) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) +#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) +#define USBPHY_STATUS_RSVD1_MASK (0x30U) +#define USBPHY_STATUS_RSVD1_SHIFT (4U) +#define USBPHY_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD1_SHIFT)) & USBPHY_STATUS_RSVD1_MASK) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) +#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) +#define USBPHY_STATUS_RSVD2_MASK (0x80U) +#define USBPHY_STATUS_RSVD2_SHIFT (7U) +#define USBPHY_STATUS_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD2_SHIFT)) & USBPHY_STATUS_RSVD2_MASK) +#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) +#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) +#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) +#define USBPHY_STATUS_RSVD3_MASK (0x200U) +#define USBPHY_STATUS_RSVD3_SHIFT (9U) +#define USBPHY_STATUS_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD3_SHIFT)) & USBPHY_STATUS_RSVD3_MASK) +#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) +#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) +#define USBPHY_STATUS_RSVD4_MASK (0xFFFFF800U) +#define USBPHY_STATUS_RSVD4_SHIFT (11U) +#define USBPHY_STATUS_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RSVD4_SHIFT)) & USBPHY_STATUS_RSVD4_MASK) +/*! @} */ + +/*! @name DEBUG - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK) +#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD1_SHIFT)) & USBPHY_DEBUG_RSVD1_MASK) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD2_SHIFT)) & USBPHY_DEBUG_RSVD2_MASK) +#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK) +#define USBPHY_DEBUG_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD3_SHIFT)) & USBPHY_DEBUG_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG_SET - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_SET_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_SET_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD0_SHIFT)) & USBPHY_DEBUG_SET_RSVD0_MASK) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_SET_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_SET_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD1_SHIFT)) & USBPHY_DEBUG_SET_RSVD1_MASK) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_SET_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_SET_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD2_SHIFT)) & USBPHY_DEBUG_SET_RSVD2_MASK) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK) +#define USBPHY_DEBUG_SET_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_SET_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_RSVD3_SHIFT)) & USBPHY_DEBUG_SET_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG_CLR - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_CLR_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_CLR_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG_CLR_RSVD0_MASK) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_CLR_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_CLR_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG_CLR_RSVD1_MASK) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_CLR_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_CLR_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD2_SHIFT)) & USBPHY_DEBUG_CLR_RSVD2_MASK) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK) +#define USBPHY_DEBUG_CLR_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_CLR_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_RSVD3_SHIFT)) & USBPHY_DEBUG_CLR_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG_TOG - USB PHY Debug Register */ +/*! @{ */ +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U) +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK) +#define USBPHY_DEBUG_TOG_RSVD0_MASK (0xC0U) +#define USBPHY_DEBUG_TOG_RSVD0_SHIFT (6U) +#define USBPHY_DEBUG_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG_TOG_RSVD0_MASK) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK) +#define USBPHY_DEBUG_TOG_RSVD1_MASK (0xE000U) +#define USBPHY_DEBUG_TOG_RSVD1_SHIFT (13U) +#define USBPHY_DEBUG_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG_TOG_RSVD1_MASK) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK) +#define USBPHY_DEBUG_TOG_RSVD2_MASK (0xE00000U) +#define USBPHY_DEBUG_TOG_RSVD2_SHIFT (21U) +#define USBPHY_DEBUG_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD2_SHIFT)) & USBPHY_DEBUG_TOG_RSVD2_MASK) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK) +#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U) +#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK) +#define USBPHY_DEBUG_TOG_RSVD3_MASK (0x80000000U) +#define USBPHY_DEBUG_TOG_RSVD3_SHIFT (31U) +#define USBPHY_DEBUG_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_RSVD3_SHIFT)) & USBPHY_DEBUG_TOG_RSVD3_MASK) +/*! @} */ + +/*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */ +/*! @{ */ +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK) +/*! @} */ + +/*! @name DEBUG1 - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD0_SHIFT)) & USBPHY_DEBUG1_RSVD0_MASK) +#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_RSVD1_SHIFT)) & USBPHY_DEBUG1_RSVD1_MASK) +/*! @} */ + +/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_SET_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_SET_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD0_SHIFT)) & USBPHY_DEBUG1_SET_RSVD0_MASK) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_SET_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_SET_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_RSVD1_SHIFT)) & USBPHY_DEBUG1_SET_RSVD1_MASK) +/*! @} */ + +/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_CLR_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_CLR_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD0_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD0_MASK) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_CLR_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_CLR_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_RSVD1_SHIFT)) & USBPHY_DEBUG1_CLR_RSVD1_MASK) +/*! @} */ + +/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ +/*! @{ */ +#define USBPHY_DEBUG1_TOG_RSVD0_MASK (0x1FFFU) +#define USBPHY_DEBUG1_TOG_RSVD0_SHIFT (0U) +#define USBPHY_DEBUG1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD0_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD0_MASK) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) +#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) +#define USBPHY_DEBUG1_TOG_RSVD1_MASK (0xFFFF8000U) +#define USBPHY_DEBUG1_TOG_RSVD1_SHIFT (15U) +#define USBPHY_DEBUG1_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_RSVD1_SHIFT)) & USBPHY_DEBUG1_TOG_RSVD1_MASK) +/*! @} */ + +/*! @name VERSION - UTMI RTL Version */ +/*! @{ */ +#define USBPHY_VERSION_STEP_MASK (0xFFFFU) +#define USBPHY_VERSION_STEP_SHIFT (0U) +#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) +#define USBPHY_VERSION_MINOR_MASK (0xFF0000U) +#define USBPHY_VERSION_MINOR_SHIFT (16U) +#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) +#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) +#define USBPHY_VERSION_MAJOR_SHIFT (24U) +#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USBPHY_Register_Masks */ + + +/* USBPHY - Peripheral instance base addresses */ +/** Peripheral USBPHY1 base address */ +#define USBPHY1_BASE (0x400D9000u) +/** Peripheral USBPHY1 base pointer */ +#define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) +/** Peripheral USBPHY2 base address */ +#define USBPHY2_BASE (0x400DA000u) +/** Peripheral USBPHY2 base pointer */ +#define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE) +/** Array initializer of USBPHY peripheral base addresses */ +#define USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE } +/** Array initializer of USBPHY peripheral base pointers */ +#define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 } +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { NotAvail_IRQn, USB_PHY1_IRQn, USB_PHY2_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) + + +/*! + * @} + */ /* end of group USBPHY_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer + * @{ + */ + +/** USB_ANALOG - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[416]; + struct { /* offset: 0x1A0, array step: 0x60 */ + __IO uint32_t VBUS_DETECT; /**< USB VBUS Detect Register, array offset: 0x1A0, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_SET; /**< USB VBUS Detect Register, array offset: 0x1A4, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_CLR; /**< USB VBUS Detect Register, array offset: 0x1A8, array step: 0x60 */ + __IO uint32_t VBUS_DETECT_TOG; /**< USB VBUS Detect Register, array offset: 0x1AC, array step: 0x60 */ + __IO uint32_t CHRG_DETECT; /**< USB Charger Detect Register, array offset: 0x1B0, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_SET; /**< USB Charger Detect Register, array offset: 0x1B4, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_CLR; /**< USB Charger Detect Register, array offset: 0x1B8, array step: 0x60 */ + __IO uint32_t CHRG_DETECT_TOG; /**< USB Charger Detect Register, array offset: 0x1BC, array step: 0x60 */ + __I uint32_t VBUS_DETECT_STAT; /**< USB VBUS Detect Status Register, array offset: 0x1C0, array step: 0x60 */ + uint8_t RESERVED_0[12]; + __I uint32_t CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, array offset: 0x1D0, array step: 0x60 */ + uint8_t RESERVED_1[28]; + __IO uint32_t MISC; /**< USB Misc Register, array offset: 0x1F0, array step: 0x60 */ + __IO uint32_t MISC_SET; /**< USB Misc Register, array offset: 0x1F4, array step: 0x60 */ + __IO uint32_t MISC_CLR; /**< USB Misc Register, array offset: 0x1F8, array step: 0x60 */ + __IO uint32_t MISC_TOG; /**< USB Misc Register, array offset: 0x1FC, array step: 0x60 */ + } INSTANCE[2]; + __I uint32_t DIGPROG; /**< Chip Silicon Version, offset: 0x260 */ +} USB_ANALOG_Type; + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks + * @{ + */ + +/*! @name VBUS_DETECT - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT */ +#define USB_ANALOG_VBUS_DETECT_COUNT (2U) + +/*! @name VBUS_DETECT_SET - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_SET */ +#define USB_ANALOG_VBUS_DETECT_SET_COUNT (2U) + +/*! @name VBUS_DETECT_CLR - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_CLR */ +#define USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U) + +/*! @name VBUS_DETECT_TOG - USB VBUS Detect Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) +/*! VBUSVALID_THRESH + * 0b000..4.0V + * 0b001..4.1V + * 0b010..4.2V + * 0b011..4.3V + * 0b100..4.4V (default) + * 0b101..4.5V + * 0b110..4.6V + * 0b111..4.7V + */ +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U) +#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) +#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U) +#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_TOG */ +#define USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U) + +/*! @name CHRG_DETECT - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ +#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ +#define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT */ +#define USB_ANALOG_CHRG_DETECT_COUNT (2U) + +/*! @name CHRG_DETECT_SET - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ +#define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_SET */ +#define USB_ANALOG_CHRG_DETECT_SET_COUNT (2U) + +/*! @name CHRG_DETECT_CLR - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ +#define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_CLR */ +#define USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U) + +/*! @name CHRG_DETECT_TOG - USB Charger Detect Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) +/*! CHK_CONTACT - Check the contact of USB plug + * 0b0..Do not check the contact of USB plug. + * 0b1..Check whether the USB plug has been in contact with each other + */ +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U) +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U) +/*! CHK_CHRG_B - Check the charger connection + * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + * 0b1..Do not check whether a charger is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U) +/*! EN_B + * 0b0..Enable the charger detector. + * 0b1..Disable the charger detector. + */ +#define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_TOG */ +#define USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U) + +/*! @name VBUS_DETECT_STAT - USB VBUS Detect Status Register */ +/*! @{ */ +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U) +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U) +#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U) +#define USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U) +#define USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U) +#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK) +/*! @} */ + +/* The count of USB_ANALOG_VBUS_DETECT_STAT */ +#define USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U) + +/*! @name CHRG_DETECT_STAT - USB Charger Detect Status Register */ +/*! @{ */ +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U) +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U) +/*! PLUG_CONTACT + * 0b0..The USB plug has not made contact. + * 0b1..The USB plug has made good contact. + */ +#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U) +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U) +/*! CHRG_DETECTED + * 0b0..The USB port is not connected to a charger. + * 0b1..A charger (either a dedicated charger or a host charger) is connected to the USB port. + */ +#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U) +#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U) +#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK) +/*! @} */ + +/* The count of USB_ANALOG_CHRG_DETECT_STAT */ +#define USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U) + +/*! @name MISC - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC */ +#define USB_ANALOG_MISC_COUNT (2U) + +/*! @name MISC_SET - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC_SET */ +#define USB_ANALOG_MISC_SET_COUNT (2U) + +/*! @name MISC_CLR - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC_CLR */ +#define USB_ANALOG_MISC_CLR_COUNT (2U) + +/*! @name MISC_TOG - USB Misc Register */ +/*! @{ */ +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U) +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U) +#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U) +#define USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U) +#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK) +/*! @} */ + +/* The count of USB_ANALOG_MISC_TOG */ +#define USB_ANALOG_MISC_TOG_COUNT (2U) + +/*! @name DIGPROG - Chip Silicon Version */ +/*! @{ */ +#define USB_ANALOG_DIGPROG_SILICON_REVISION_MASK (0xFFFFFFFFU) +#define USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT (0U) +/*! SILICON_REVISION + * 0b00000000011011000000000000000000..Silicon revision 1.0 + */ +#define USB_ANALOG_DIGPROG_SILICON_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_SILICON_REVISION_SHIFT)) & USB_ANALOG_DIGPROG_SILICON_REVISION_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_ANALOG_Register_Masks */ + + +/* USB_ANALOG - Peripheral instance base addresses */ +/** Peripheral USB_ANALOG base address */ +#define USB_ANALOG_BASE (0x400D8000u) +/** Peripheral USB_ANALOG base pointer */ +#define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE) +/** Array initializer of USB_ANALOG peripheral base addresses */ +#define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE } +/** Array initializer of USB_ANALOG peripheral base pointers */ +#define USB_ANALOG_BASE_PTRS { USB_ANALOG } + +/*! + * @} + */ /* end of group USB_ANALOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USDHC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer + * @{ + */ + +/** USDHC - Register Layout Typedef */ +typedef struct { + __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */ + __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */ + __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */ + __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */ + __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */ + __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */ + __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */ + __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */ + __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */ + __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */ + __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */ + __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */ + __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */ + __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */ + __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */ + __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */ + __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */ + __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */ + __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */ + uint8_t RESERVED_0[4]; + __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */ + __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */ + __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */ + __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */ + __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */ + uint8_t RESERVED_2[84]; + __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */ + __IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */ + __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ + __IO uint32_t TUNING_CTRL; /**< Tuning Control Register, offset: 0xCC */ +} USDHC_Type; + +/* ---------------------------------------------------------------------------- + -- USDHC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USDHC_Register_Masks USDHC Register Masks + * @{ + */ + +/*! @name DS_ADDR - DMA System Address */ +/*! @{ */ +#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) +#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) +#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK) +/*! @} */ + +/*! @name BLK_ATT - Block Attributes */ +/*! @{ */ +#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) +#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) +/*! BLKSIZE - Block Size + * 0b1000000000000..4096 Bytes + * 0b0100000000000..2048 Bytes + * 0b0001000000000..512 Bytes + * 0b0000111111111..511 Bytes + * 0b0000000000100..4 Bytes + * 0b0000000000011..3 Bytes + * 0b0000000000010..2 Bytes + * 0b0000000000001..1 Byte + * 0b0000000000000..No data transfer + */ +#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) +#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) +#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) +/*! BLKCNT - Block Count + * 0b1111111111111111..65535 blocks + * 0b0000000000000010..2 blocks + * 0b0000000000000001..1 block + * 0b0000000000000000..Stop Count + */ +#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK) +/*! @} */ + +/*! @name CMD_ARG - Command Argument */ +/*! @{ */ +#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) +#define USDHC_CMD_ARG_CMDARG_SHIFT (0U) +#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK) +/*! @} */ + +/*! @name CMD_XFR_TYP - Command Transfer Type */ +/*! @{ */ +#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) +#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) +/*! RSPTYP - Response Type Select + * 0b00..No Response + * 0b01..Response Length 136 + * 0b10..Response Length 48 + * 0b11..Response Length 48, check Busy after response + */ +#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) +#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) +#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) +/*! CCCEN - Command CRC Check Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) +#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) +#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) +/*! CICEN - Command Index Check Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) +#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) +#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) +/*! DPSEL - Data Present Select + * 0b1..Data Present + * 0b0..No Data Present + */ +#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) +#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) +#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) +/*! CMDTYP - Command Type + * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR + * 0b10..Resume CMD52 for writing Function Select in CCCR + * 0b01..Suspend CMD52 for writing Bus Suspend in CCCR + * 0b00..Normal Other commands + */ +#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) +#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) +#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) +#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK) +/*! @} */ + +/*! @name CMD_RSP0 - Command Response0 */ +/*! @{ */ +#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) +#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK) +/*! @} */ + +/*! @name CMD_RSP1 - Command Response1 */ +/*! @{ */ +#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) +#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK) +/*! @} */ + +/*! @name CMD_RSP2 - Command Response2 */ +/*! @{ */ +#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) +#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK) +/*! @} */ + +/*! @name CMD_RSP3 - Command Response3 */ +/*! @{ */ +#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) +#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) +#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK) +/*! @} */ + +/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ +/*! @{ */ +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) +#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK) +/*! @} */ + +/*! @name PRES_STATE - Present State */ +/*! @{ */ +#define USDHC_PRES_STATE_CIHB_MASK (0x1U) +#define USDHC_PRES_STATE_CIHB_SHIFT (0U) +/*! CIHB - Command Inhibit (CMD) + * 0b1..Cannot issue command + * 0b0..Can issue command using only CMD line + */ +#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) +#define USDHC_PRES_STATE_CDIHB_MASK (0x2U) +#define USDHC_PRES_STATE_CDIHB_SHIFT (1U) +/*! CDIHB - Command Inhibit (DATA) + * 0b1..Cannot issue command which uses the DATA line + * 0b0..Can issue command which uses the DATA line + */ +#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) +#define USDHC_PRES_STATE_DLA_MASK (0x4U) +#define USDHC_PRES_STATE_DLA_SHIFT (2U) +/*! DLA - Data Line Active + * 0b1..DATA Line Active + * 0b0..DATA Line Inactive + */ +#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) +#define USDHC_PRES_STATE_SDSTB_MASK (0x8U) +#define USDHC_PRES_STATE_SDSTB_SHIFT (3U) +/*! SDSTB - SD Clock Stable + * 0b1..Clock is stable. + * 0b0..Clock is changing frequency and not stable. + */ +#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) +#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U) +#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U) +/*! IPGOFF - IPG_CLK Gated Off Internally + * 0b1..IPG_CLK is gated off. + * 0b0..IPG_CLK is active. + */ +#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) +#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U) +#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U) +/*! HCKOFF - HCLK Gated Off Internally + * 0b1..HCLK is gated off. + * 0b0..HCLK is active. + */ +#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) +#define USDHC_PRES_STATE_PEROFF_MASK (0x40U) +#define USDHC_PRES_STATE_PEROFF_SHIFT (6U) +/*! PEROFF - IPG_PERCLK Gated Off Internally + * 0b1..IPG_PERCLK is gated off. + * 0b0..IPG_PERCLK is active. + */ +#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) +#define USDHC_PRES_STATE_SDOFF_MASK (0x80U) +#define USDHC_PRES_STATE_SDOFF_SHIFT (7U) +/*! SDOFF - SD Clock Gated Off Internally + * 0b1..SD Clock is gated off. + * 0b0..SD Clock is active. + */ +#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) +#define USDHC_PRES_STATE_WTA_MASK (0x100U) +#define USDHC_PRES_STATE_WTA_SHIFT (8U) +/*! WTA - Write Transfer Active + * 0b1..Transferring data + * 0b0..No valid data + */ +#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) +#define USDHC_PRES_STATE_RTA_MASK (0x200U) +#define USDHC_PRES_STATE_RTA_SHIFT (9U) +/*! RTA - Read Transfer Active + * 0b1..Transferring data + * 0b0..No valid data + */ +#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) +#define USDHC_PRES_STATE_BWEN_MASK (0x400U) +#define USDHC_PRES_STATE_BWEN_SHIFT (10U) +/*! BWEN - Buffer Write Enable + * 0b1..Write enable + * 0b0..Write disable + */ +#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) +#define USDHC_PRES_STATE_BREN_MASK (0x800U) +#define USDHC_PRES_STATE_BREN_SHIFT (11U) +/*! BREN - Buffer Read Enable + * 0b1..Read enable + * 0b0..Read disable + */ +#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) +#define USDHC_PRES_STATE_RTR_MASK (0x1000U) +#define USDHC_PRES_STATE_RTR_SHIFT (12U) +/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode) + * 0b1..Sampling clock needs re-tuning + * 0b0..Fixed or well tuned sampling clock + */ +#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) +#define USDHC_PRES_STATE_TSCD_MASK (0x8000U) +#define USDHC_PRES_STATE_TSCD_SHIFT (15U) +/*! TSCD - Tape Select Change Done + * 0b1..Delay cell select change is finished. + * 0b0..Delay cell select change is not finished. + */ +#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) +#define USDHC_PRES_STATE_CINST_MASK (0x10000U) +#define USDHC_PRES_STATE_CINST_SHIFT (16U) +/*! CINST - Card Inserted + * 0b1..Card Inserted + * 0b0..Power on Reset or No Card + */ +#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) +#define USDHC_PRES_STATE_CDPL_MASK (0x40000U) +#define USDHC_PRES_STATE_CDPL_SHIFT (18U) +/*! CDPL - Card Detect Pin Level + * 0b1..Card present (CD_B = 0) + * 0b0..No card present (CD_B = 1) + */ +#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) +#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) +#define USDHC_PRES_STATE_WPSPL_SHIFT (19U) +/*! WPSPL - Write Protect Switch Pin Level + * 0b1..Write enabled (WP = 0) + * 0b0..Write protected (WP = 1) + */ +#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) +#define USDHC_PRES_STATE_CLSL_MASK (0x800000U) +#define USDHC_PRES_STATE_CLSL_SHIFT (23U) +#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) +#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) +#define USDHC_PRES_STATE_DLSL_SHIFT (24U) +/*! DLSL - DATA[7:0] Line Signal Level + * 0b00000111..Data 7 line signal level + * 0b00000110..Data 6 line signal level + * 0b00000101..Data 5 line signal level + * 0b00000100..Data 4 line signal level + * 0b00000011..Data 3 line signal level + * 0b00000010..Data 2 line signal level + * 0b00000001..Data 1 line signal level + * 0b00000000..Data 0 line signal level + */ +#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK) +/*! @} */ + +/*! @name PROT_CTRL - Protocol Control */ +/*! @{ */ +#define USDHC_PROT_CTRL_LCTL_MASK (0x1U) +#define USDHC_PROT_CTRL_LCTL_SHIFT (0U) +/*! LCTL - LED Control + * 0b1..LED on + * 0b0..LED off + */ +#define USDHC_PROT_CTRL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK) +#define USDHC_PROT_CTRL_DTW_MASK (0x6U) +#define USDHC_PROT_CTRL_DTW_SHIFT (1U) +/*! DTW - Data Transfer Width + * 0b10..8-bit mode + * 0b01..4-bit mode + * 0b00..1-bit mode + * 0b11..Reserved + */ +#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) +#define USDHC_PROT_CTRL_D3CD_MASK (0x8U) +#define USDHC_PROT_CTRL_D3CD_SHIFT (3U) +/*! D3CD - DATA3 as Card Detection Pin + * 0b1..DATA3 as Card Detection Pin + * 0b0..DATA3 does not monitor Card Insertion + */ +#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) +#define USDHC_PROT_CTRL_EMODE_MASK (0x30U) +#define USDHC_PROT_CTRL_EMODE_SHIFT (4U) +/*! EMODE - Endian Mode + * 0b00..Big Endian Mode + * 0b01..Half Word Big Endian Mode + * 0b10..Little Endian Mode + * 0b11..Reserved + */ +#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) +#define USDHC_PROT_CTRL_CDTL_MASK (0x40U) +#define USDHC_PROT_CTRL_CDTL_SHIFT (6U) +/*! CDTL - Card Detect Test Level + * 0b1..Card Detect Test Level is 1, card inserted + * 0b0..Card Detect Test Level is 0, no card inserted + */ +#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) +#define USDHC_PROT_CTRL_CDSS_MASK (0x80U) +#define USDHC_PROT_CTRL_CDSS_SHIFT (7U) +/*! CDSS - Card Detect Signal Selection + * 0b1..Card Detection Test Level is selected (for test purpose). + * 0b0..Card Detection Level is selected (for normal purpose). + */ +#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) +#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) +#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) +/*! DMASEL - DMA Select + * 0b00..No DMA or Simple DMA is selected + * 0b01..ADMA1 is selected + * 0b10..ADMA2 is selected + * 0b11..reserved + */ +#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) +#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) +#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) +/*! SABGREQ - Stop At Block Gap Request + * 0b1..Stop + * 0b0..Transfer + */ +#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) +#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) +#define USDHC_PROT_CTRL_CREQ_SHIFT (17U) +/*! CREQ - Continue Request + * 0b1..Restart + * 0b0..No effect + */ +#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) +#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) +#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) +/*! RWCTL - Read Wait Control + * 0b1..Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set + * 0b0..Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set + */ +#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) +#define USDHC_PROT_CTRL_IABG_MASK (0x80000U) +#define USDHC_PROT_CTRL_IABG_SHIFT (19U) +/*! IABG - Interrupt At Block Gap + * 0b1..Enabled + * 0b0..Disabled + */ +#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) +#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) +#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) +#define USDHC_PROT_CTRL_WECINT_SHIFT (24U) +/*! WECINT - Wakeup Event Enable On Card Interrupt + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) +#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) +#define USDHC_PROT_CTRL_WECINS_SHIFT (25U) +/*! WECINS - Wakeup Event Enable On SD Card Insertion + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) +#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) +#define USDHC_PROT_CTRL_WECRM_SHIFT (26U) +/*! WECRM - Wakeup Event Enable On SD Card Removal + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) +#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U) +#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U) +/*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP + * 0bxx1..Burst length is enabled for INCR + * 0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16 + * 0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP + */ +#define USDHC_PROT_CTRL_BURST_LEN_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) +/*! NON_EXACT_BLK_RD - NON_EXACT_BLK_RD + * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. + * 0b0..The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read. + */ +#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK) +/*! @} */ + +/*! @name SYS_CTRL - System Control */ +/*! @{ */ +#define USDHC_SYS_CTRL_DVS_MASK (0xF0U) +#define USDHC_SYS_CTRL_DVS_SHIFT (4U) +/*! DVS - Divisor + * 0b0000..Divide-by-1 + * 0b0001..Divide-by-2 + * 0b1110..Divide-by-15 + * 0b1111..Divide-by-16 + */ +#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) +#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) +#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) +#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) +#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) +#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) +/*! DTOCV - Data Timeout Counter Value + * 0b1111..SDCLK x 2 29 + * 0b1110..SDCLK x 2 28 + * 0b1101..SDCLK x 2 27 + * 0b0001..SDCLK x 2 15 + * 0b0000..SDCLK x 2 14 + */ +#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) +#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) +#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) +#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) +#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) +#define USDHC_SYS_CTRL_RSTA_SHIFT (24U) +/*! RSTA - Software Reset For ALL + * 0b1..Reset + * 0b0..No Reset + */ +#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) +#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) +#define USDHC_SYS_CTRL_RSTC_SHIFT (25U) +/*! RSTC - Software Reset For CMD Line + * 0b1..Reset + * 0b0..No Reset + */ +#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) +#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) +#define USDHC_SYS_CTRL_RSTD_SHIFT (26U) +/*! RSTD - Software Reset For DATA Line + * 0b1..Reset + * 0b0..No Reset + */ +#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) +#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) +#define USDHC_SYS_CTRL_INITA_SHIFT (27U) +#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) +#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) +#define USDHC_SYS_CTRL_RSTT_SHIFT (28U) +#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK) +/*! @} */ + +/*! @name INT_STATUS - Interrupt Status */ +/*! @{ */ +#define USDHC_INT_STATUS_CC_MASK (0x1U) +#define USDHC_INT_STATUS_CC_SHIFT (0U) +/*! CC - Command Complete + * 0b1..Command complete + * 0b0..Command not complete + */ +#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) +#define USDHC_INT_STATUS_TC_MASK (0x2U) +#define USDHC_INT_STATUS_TC_SHIFT (1U) +/*! TC - Transfer Complete + * 0b1..Transfer complete + * 0b0..Transfer not complete + */ +#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) +#define USDHC_INT_STATUS_BGE_MASK (0x4U) +#define USDHC_INT_STATUS_BGE_SHIFT (2U) +/*! BGE - Block Gap Event + * 0b1..Transaction stopped at block gap + * 0b0..No block gap event + */ +#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) +#define USDHC_INT_STATUS_DINT_MASK (0x8U) +#define USDHC_INT_STATUS_DINT_SHIFT (3U) +/*! DINT - DMA Interrupt + * 0b1..DMA Interrupt is generated + * 0b0..No DMA Interrupt + */ +#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) +#define USDHC_INT_STATUS_BWR_MASK (0x10U) +#define USDHC_INT_STATUS_BWR_SHIFT (4U) +/*! BWR - Buffer Write Ready + * 0b1..Ready to write buffer: + * 0b0..Not ready to write buffer + */ +#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) +#define USDHC_INT_STATUS_BRR_MASK (0x20U) +#define USDHC_INT_STATUS_BRR_SHIFT (5U) +/*! BRR - Buffer Read Ready + * 0b1..Ready to read buffer + * 0b0..Not ready to read buffer + */ +#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) +#define USDHC_INT_STATUS_CINS_MASK (0x40U) +#define USDHC_INT_STATUS_CINS_SHIFT (6U) +/*! CINS - Card Insertion + * 0b1..Card inserted + * 0b0..Card state unstable or removed + */ +#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) +#define USDHC_INT_STATUS_CRM_MASK (0x80U) +#define USDHC_INT_STATUS_CRM_SHIFT (7U) +/*! CRM - Card Removal + * 0b1..Card removed + * 0b0..Card state unstable or inserted + */ +#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) +#define USDHC_INT_STATUS_CINT_MASK (0x100U) +#define USDHC_INT_STATUS_CINT_SHIFT (8U) +/*! CINT - Card Interrupt + * 0b1..Generate Card Interrupt + * 0b0..No Card Interrupt + */ +#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) +#define USDHC_INT_STATUS_RTE_MASK (0x1000U) +#define USDHC_INT_STATUS_RTE_SHIFT (12U) +/*! RTE - Re-Tuning Event: (only for SD3.0 SDR104 mode and EMMC HS200 mode) + * 0b1..Re-Tuning should be performed + * 0b0..Re-Tuning is not required + */ +#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) +#define USDHC_INT_STATUS_TP_MASK (0x4000U) +#define USDHC_INT_STATUS_TP_SHIFT (14U) +#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) +#define USDHC_INT_STATUS_CTOE_MASK (0x10000U) +#define USDHC_INT_STATUS_CTOE_SHIFT (16U) +/*! CTOE - Command Timeout Error + * 0b1..Time out + * 0b0..No Error + */ +#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) +#define USDHC_INT_STATUS_CCE_MASK (0x20000U) +#define USDHC_INT_STATUS_CCE_SHIFT (17U) +/*! CCE - Command CRC Error + * 0b1..CRC Error Generated. + * 0b0..No Error + */ +#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) +#define USDHC_INT_STATUS_CEBE_MASK (0x40000U) +#define USDHC_INT_STATUS_CEBE_SHIFT (18U) +/*! CEBE - Command End Bit Error + * 0b1..End Bit Error Generated + * 0b0..No Error + */ +#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) +#define USDHC_INT_STATUS_CIE_MASK (0x80000U) +#define USDHC_INT_STATUS_CIE_SHIFT (19U) +/*! CIE - Command Index Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) +#define USDHC_INT_STATUS_DTOE_MASK (0x100000U) +#define USDHC_INT_STATUS_DTOE_SHIFT (20U) +/*! DTOE - Data Timeout Error + * 0b1..Time out + * 0b0..No Error + */ +#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) +#define USDHC_INT_STATUS_DCE_MASK (0x200000U) +#define USDHC_INT_STATUS_DCE_SHIFT (21U) +/*! DCE - Data CRC Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) +#define USDHC_INT_STATUS_DEBE_MASK (0x400000U) +#define USDHC_INT_STATUS_DEBE_SHIFT (22U) +/*! DEBE - Data End Bit Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) +#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) +#define USDHC_INT_STATUS_AC12E_SHIFT (24U) +/*! AC12E - Auto CMD12 Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) +#define USDHC_INT_STATUS_TNE_MASK (0x4000000U) +#define USDHC_INT_STATUS_TNE_SHIFT (26U) +#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) +#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) +#define USDHC_INT_STATUS_DMAE_SHIFT (28U) +/*! DMAE - DMA Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK) +/*! @} */ + +/*! @name INT_STATUS_EN - Interrupt Status Enable */ +/*! @{ */ +#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) +#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) +/*! CCSEN - Command Complete Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) +#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) +#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) +/*! TCSEN - Transfer Complete Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) +#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) +#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) +/*! BGESEN - Block Gap Event Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) +#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) +#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) +/*! DINTSEN - DMA Interrupt Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) +#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) +#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) +/*! BWRSEN - Buffer Write Ready Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) +#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) +#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) +/*! BRRSEN - Buffer Read Ready Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) +#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) +#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) +/*! CINSSEN - Card Insertion Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) +#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) +#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) +/*! CRMSEN - Card Removal Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) +#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) +#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) +/*! CINTSEN - Card Interrupt Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) +#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) +#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) +/*! RTESEN - Re-Tuning Event Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) +#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U) +#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U) +/*! TPSEN - Tuning Pass Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) +#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) +#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) +/*! CTOESEN - Command Timeout Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) +#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) +#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) +/*! CCESEN - Command CRC Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) +#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) +#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) +/*! CEBESEN - Command End Bit Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) +#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) +#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) +/*! CIESEN - Command Index Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) +#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) +#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) +/*! DTOESEN - Data Timeout Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) +#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) +#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) +/*! DCESEN - Data CRC Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) +#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) +#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) +/*! DEBESEN - Data End Bit Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) +#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) +#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) +/*! AC12ESEN - Auto CMD12 Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) +#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) +#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) +/*! TNESEN - Tuning Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) +#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) +#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) +/*! DMAESEN - DMA Error Status Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK) +/*! @} */ + +/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ +/*! @{ */ +#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) +#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) +/*! CCIEN - Command Complete Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) +#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) +/*! TCIEN - Transfer Complete Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) +#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) +/*! BGEIEN - Block Gap Event Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) +#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) +/*! DINTIEN - DMA Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) +#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) +/*! BWRIEN - Buffer Write Ready Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) +#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) +#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) +/*! BRRIEN - Buffer Read Ready Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) +#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) +/*! CINSIEN - Card Insertion Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) +#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) +/*! CRMIEN - Card Removal Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) +#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) +/*! CINTIEN - Card Interrupt Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) +#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) +#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) +/*! RTEIEN - Re-Tuning Event Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U) +#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U) +/*! TPIEN - Tuning Pass Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) +#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) +/*! CTOEIEN - Command Timeout Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) +#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) +/*! CCEIEN - Command CRC Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) +#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) +/*! CEBEIEN - Command End Bit Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) +#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) +/*! CIEIEN - Command Index Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) +#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) +/*! DTOEIEN - Data Timeout Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) +#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) +/*! DCEIEN - Data CRC Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) +#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) +/*! DEBEIEN - Data End Bit Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) +#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) +/*! AC12EIEN - Auto CMD12 Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) +#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) +#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) +/*! TNEIEN - Tuning Error Interrupt Enable + * 0b1..Enabled + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) +#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) +#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) +/*! DMAEIEN - DMA Error Interrupt Enable + * 0b1..Enable + * 0b0..Masked + */ +#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK) +/*! @} */ + +/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ +/*! @{ */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) +/*! AC12NE - Auto CMD12 Not Executed + * 0b1..Not executed + * 0b0..Executed + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) +/*! AC12TOE - Auto CMD12 / 23 Timeout Error + * 0b1..Time out + * 0b0..No error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) +/*! AC12EBE - Auto CMD12 / 23 End Bit Error + * 0b1..End Bit Error Generated + * 0b0..No error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) +/*! AC12CE - Auto CMD12 / 23 CRC Error + * 0b1..CRC Error Met in Auto CMD12/23 Response + * 0b0..No CRC error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) +/*! AC12IE - Auto CMD12 / 23 Index Error + * 0b1..Error, the CMD index in response is not CMD12/23 + * 0b0..No error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) +/*! CNIBAC12E - Command Not Issued By Auto CMD12 Error + * 0b1..Not Issued + * 0b0..No error + */ +#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) +#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) +/*! SMP_CLK_SEL - Sample Clock Select + * 0b1..Tuned clock is used to sample data + * 0b0..Fixed clock is used to sample data + */ +#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK) +/*! @} */ + +/*! @name HOST_CTRL_CAP - Host Controller Capabilities */ +/*! @{ */ +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) +#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) +#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) +#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U) +#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) +/*! USE_TUNING_SDR50 - Use Tuning for SDR50 + * 0b1..SDR50 requires tuning + * 0b0..SDR does not require tuning + */ +#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U) +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U) +/*! RETUNING_MODE - Retuning Mode + * 0b00..Mode 1 + * 0b01..Mode 2 + * 0b10..Mode 3 + * 0b11..Reserved + */ +#define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK) +#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) +#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) +/*! MBL - Max Block Length + * 0b000..512 bytes + * 0b001..1024 bytes + * 0b010..2048 bytes + * 0b011..4096 bytes + */ +#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) +#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) +#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) +/*! ADMAS - ADMA Support + * 0b1..Advanced DMA Supported + * 0b0..Advanced DMA Not supported + */ +#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) +#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) +#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) +/*! HSS - High Speed Support + * 0b1..High Speed Supported + * 0b0..High Speed Not Supported + */ +#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) +#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) +#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) +/*! DMAS - DMA Support + * 0b1..DMA Supported + * 0b0..DMA not supported + */ +#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) +#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) +#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) +/*! SRS - Suspend / Resume Support + * 0b1..Supported + * 0b0..Not supported + */ +#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) +#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) +#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) +/*! VS33 - Voltage Support 3.3V + * 0b1..3.3V supported + * 0b0..3.3V not supported + */ +#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) +#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) +#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) +/*! VS30 - Voltage Support 3.0 V + * 0b1..3.0V supported + * 0b0..3.0V not supported + */ +#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) +#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) +#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) +/*! VS18 - Voltage Support 1.8 V + * 0b1..1.8V supported + * 0b0..1.8V not supported + */ +#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK) +/*! @} */ + +/*! @name WTMK_LVL - Watermark Level */ +/*! @{ */ +#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) +#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) +#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) +#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U) +#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U) +#define USDHC_WTMK_LVL_RD_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK) +#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) +#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) +#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK) +#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U) +#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U) +#define USDHC_WTMK_LVL_WR_BRST_LEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK) +/*! @} */ + +/*! @name MIX_CTRL - Mixer Control */ +/*! @{ */ +#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) +#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) +/*! DMAEN - DMA Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) +#define USDHC_MIX_CTRL_BCEN_MASK (0x2U) +#define USDHC_MIX_CTRL_BCEN_SHIFT (1U) +/*! BCEN - Block Count Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) +#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) +#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) +/*! AC12EN - Auto CMD12 Enable + * 0b1..Enable + * 0b0..Disable + */ +#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) +#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) +#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) +#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) +#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) +#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) +/*! DTDSEL - Data Transfer Direction Select + * 0b1..Read (Card to Host) + * 0b0..Write (Host to Card) + */ +#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) +#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) +#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) +/*! MSBSEL - Multi / Single Block Select + * 0b1..Multiple Blocks + * 0b0..Single Block + */ +#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) +#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) +#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) +#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) +#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) +#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) +#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) +#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) +#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) +/*! EXE_TUNE - Execute Tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) + * 0b1..Execute Tuning + * 0b0..Not Tuned or Tuning Completed + */ +#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) +#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) +#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) +/*! SMP_CLK_SEL - SMP_CLK_SEL + * 0b1..Tuned clock is used to sample data / cmd + * 0b0..Fixed clock is used to sample data / cmd + */ +#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) +#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) +/*! AUTO_TUNE_EN - Auto Tuning Enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode) + * 0b1..Enable auto tuning + * 0b0..Disable auto tuning + */ +#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) +#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) +#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) +/*! FBCLK_SEL - Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) + * 0b1..Feedback clock comes from the ipp_card_clk_out + * 0b0..Feedback clock comes from the loopback CLK + */ +#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) +/*! @} */ + +/*! @name FORCE_EVENT - Force Event */ +/*! @{ */ +#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) +#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) +#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) +#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) +#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) +#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) +#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) +#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) +#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) +#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) +#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) +#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) +#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) +#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) +#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) +#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) +#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) +#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) +#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) +#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) +#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) +#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) +#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) +#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) +#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) +#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) +#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) +#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) +#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) +#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) +#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) +#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) +#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) +#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) +#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) +#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) +#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) +#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) +#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) +#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) +#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) +#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) +#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) +#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) +#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK) +/*! @} */ + +/*! @name ADMA_ERR_STATUS - ADMA Error Status Register */ +/*! @{ */ +#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) +#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) +#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) +#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) +#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) +/*! ADMALME - ADMA Length Mismatch Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) +#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) +#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) +/*! ADMADCE - ADMA Descriptor Error + * 0b1..Error + * 0b0..No Error + */ +#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK) +/*! @} */ + +/*! @name ADMA_SYS_ADDR - ADMA System Address */ +/*! @{ */ +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) +#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK) +/*! @} */ + +/*! @name DLL_CTRL - DLL (Delay Line) Control */ +/*! @{ */ +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) +#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) +#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) +#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) +#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) +#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK) +/*! @} */ + +/*! @name DLL_STATUS - DLL Status */ +/*! @{ */ +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) +#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) +#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) +#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK) +/*! @} */ + +/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ +/*! @{ */ +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) +#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) +#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) +#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) +#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK) +/*! @} */ + +/*! @name VEND_SPEC - Vendor Specific Register */ +/*! @{ */ +#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) +#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) +/*! VSELECT - Voltage Selection + * 0b1..Change the voltage to low voltage range, around 1.8 V + * 0b0..Change the voltage to high voltage range, around 3.0 V + */ +#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) +/*! CONFLICT_CHK_EN - Conflict check enable. + * 0b0..Conflict check disable + * 0b1..Conflict check enable + */ +#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) +/*! AC12_WR_CHKBUSY_EN - AC12_WR_CHKBUSY_EN + * 0b0..Do not check busy after auto CMD12 for write data packet + * 0b1..Check busy after auto CMD12 for write data packet + */ +#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) +#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) +/*! FRC_SDCLK_ON - FRC_SDCLK_ON + * 0b0..CLK active or inactive is fully controlled by the hardware. + * 0b1..Force CLK active. + */ +#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) +#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) +#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) +/*! CRC_CHK_DIS - CRC Check Disable + * 0b0..Check CRC16 for every read data packet and check CRC bits for every write data packet + * 0b1..Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet + */ +#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) +#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) +#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) +/*! CMD_BYTE_EN - CMD_BYTE_EN + * 0b0..Disable + * 0b1..Enable + */ +#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK) +/*! @} */ + +/*! @name MMC_BOOT - MMC Boot Register */ +/*! @{ */ +#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) +#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) +/*! DTOCV_ACK - DTOCV_ACK + * 0b0000..SDCLK x 2^14 + * 0b0001..SDCLK x 2^15 + * 0b0010..SDCLK x 2^16 + * 0b0011..SDCLK x 2^17 + * 0b0100..SDCLK x 2^18 + * 0b0101..SDCLK x 2^19 + * 0b0110..SDCLK x 2^20 + * 0b0111..SDCLK x 2^21 + * 0b1110..SDCLK x 2^28 + * 0b1111..SDCLK x 2^29 + */ +#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) +#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) +#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) +/*! BOOT_ACK - BOOT_ACK + * 0b0..No ack + * 0b1..Ack + */ +#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) +#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) +#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) +/*! BOOT_MODE - BOOT_MODE + * 0b0..Normal boot + * 0b1..Alternative boot + */ +#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) +#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) +#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) +/*! BOOT_EN - BOOT_EN + * 0b0..Fast boot disable + * 0b1..Fast boot enable + */ +#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) +#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) +#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) +#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) +/*! DISABLE_TIME_OUT - Disable Time Out + * 0b0..Enable time out + * 0b1..Disable time out + */ +#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) +#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK) +/*! @} */ + +/*! @name VEND_SPEC2 - Vendor Specific 2 Register */ +/*! @{ */ +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) +/*! CARD_INT_D3_TEST - Card Interrupt Detection Test + * 0b0..Check the card interrupt only when DATA3 is high. + * 0b1..Check the card interrupt by ignoring the status of DATA3. + */ +#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) +#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U) +#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) +#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) +/*! TUNING_CMD_EN - TUNING_CMD_EN + * 0b0..Auto tuning circuit does not check the CMD line. + * 0b1..Auto tuning circuit checks the CMD line. + */ +#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) +/*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23 + * 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable. + * 0b0..Disable + */ +#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK (0x2000U) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT (13U) +#define USDHC_VEND_SPEC2_PART_DLL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_PART_DLL_DEBUG_SHIFT)) & USDHC_VEND_SPEC2_PART_DLL_DEBUG_MASK) +#define USDHC_VEND_SPEC2_BUS_RST_MASK (0x4000U) +#define USDHC_VEND_SPEC2_BUS_RST_SHIFT (14U) +#define USDHC_VEND_SPEC2_BUS_RST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_BUS_RST_SHIFT)) & USDHC_VEND_SPEC2_BUS_RST_MASK) +/*! @} */ + +/*! @name TUNING_CTRL - Tuning Control Register */ +/*! @{ */ +#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU) +#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) +#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) +#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) +#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) +#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) +#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) +#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) +#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) +#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) +#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) +#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) +#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) +#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) +#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USDHC_Register_Masks */ + + +/* USDHC - Peripheral instance base addresses */ +/** Peripheral USDHC1 base address */ +#define USDHC1_BASE (0x402C0000u) +/** Peripheral USDHC1 base pointer */ +#define USDHC1 ((USDHC_Type *)USDHC1_BASE) +/** Peripheral USDHC2 base address */ +#define USDHC2_BASE (0x402C4000u) +/** Peripheral USDHC2 base pointer */ +#define USDHC2 ((USDHC_Type *)USDHC2_BASE) +/** Array initializer of USDHC peripheral base addresses */ +#define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE } +/** Array initializer of USDHC peripheral base pointers */ +#define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 } +/** Interrupt vectors for the USDHC peripheral type */ +#define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn } + +/*! + * @} + */ /* end of group USDHC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer + * @{ + */ + +/** WDOG - Register Layout Typedef */ +typedef struct { + __IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */ + __IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */ + __I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */ + __IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */ + __IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */ +} WDOG_Type; + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/*! @name WCR - Watchdog Control Register */ +/*! @{ */ +#define WDOG_WCR_WDZST_MASK (0x1U) +#define WDOG_WCR_WDZST_SHIFT (0U) +/*! WDZST - WDZST + * 0b0..Continue timer operation (Default). + * 0b1..Suspend the watchdog timer. + */ +#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) +#define WDOG_WCR_WDBG_MASK (0x2U) +#define WDOG_WCR_WDBG_SHIFT (1U) +/*! WDBG - WDBG + * 0b0..Continue WDOG timer operation (Default). + * 0b1..Suspend the watchdog timer. + */ +#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) +#define WDOG_WCR_WDE_MASK (0x4U) +#define WDOG_WCR_WDE_SHIFT (2U) +/*! WDE - WDE + * 0b0..Disable the Watchdog (Default). + * 0b1..Enable the Watchdog. + */ +#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) +#define WDOG_WCR_WDT_MASK (0x8U) +#define WDOG_WCR_WDT_SHIFT (3U) +/*! WDT - WDT + * 0b0..No effect on WDOG_B (Default). + * 0b1..Assert WDOG_B upon a Watchdog Time-out event. + */ +#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) +#define WDOG_WCR_SRS_MASK (0x10U) +#define WDOG_WCR_SRS_SHIFT (4U) +/*! SRS - SRS + * 0b0..Assert system reset signal. + * 0b1..No effect on the system (Default). + */ +#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) +#define WDOG_WCR_WDA_MASK (0x20U) +#define WDOG_WCR_WDA_SHIFT (5U) +/*! WDA - WDA + * 0b0..Assert WDOG_B output. + * 0b1..No effect on system (Default). + */ +#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) +#define WDOG_WCR_SRE_MASK (0x40U) +#define WDOG_WCR_SRE_SHIFT (6U) +/*! SRE - software reset extension, an option way to generate software reset + * 0b0..using original way to generate software reset (default) + * 0b1..using new way to generate software reset. + */ +#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) +#define WDOG_WCR_WDW_MASK (0x80U) +#define WDOG_WCR_WDW_SHIFT (7U) +/*! WDW - WDW + * 0b0..Continue WDOG timer operation (Default). + * 0b1..Suspend WDOG timer operation. + */ +#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) +#define WDOG_WCR_WT_MASK (0xFF00U) +#define WDOG_WCR_WT_SHIFT (8U) +/*! WT - WT + * 0b00000000..- 0.5 Seconds (Default). + * 0b00000001..- 1.0 Seconds. + * 0b00000010..- 1.5 Seconds. + * 0b00000011..- 2.0 Seconds. + * 0b11111111..- 128 Seconds. + */ +#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK) +/*! @} */ + +/*! @name WSR - Watchdog Service Register */ +/*! @{ */ +#define WDOG_WSR_WSR_MASK (0xFFFFU) +#define WDOG_WSR_WSR_SHIFT (0U) +/*! WSR - WSR + * 0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR). + * 0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR). + */ +#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK) +/*! @} */ + +/*! @name WRSR - Watchdog Reset Status Register */ +/*! @{ */ +#define WDOG_WRSR_SFTW_MASK (0x1U) +#define WDOG_WRSR_SFTW_SHIFT (0U) +/*! SFTW - SFTW + * 0b0..Reset is not the result of a software reset. + * 0b1..Reset is the result of a software reset. + */ +#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) +#define WDOG_WRSR_TOUT_MASK (0x2U) +#define WDOG_WRSR_TOUT_SHIFT (1U) +/*! TOUT - TOUT + * 0b0..Reset is not the result of a WDOG timeout. + * 0b1..Reset is the result of a WDOG timeout. + */ +#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) +#define WDOG_WRSR_POR_MASK (0x10U) +#define WDOG_WRSR_POR_SHIFT (4U) +/*! POR - POR + * 0b0..Reset is not the result of a power on reset. + * 0b1..Reset is the result of a power on reset. + */ +#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK) +/*! @} */ + +/*! @name WICR - Watchdog Interrupt Control Register */ +/*! @{ */ +#define WDOG_WICR_WICT_MASK (0xFFU) +#define WDOG_WICR_WICT_SHIFT (0U) +/*! WICT - WICT + * 0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. + * 0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. + * 0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). + * 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. + */ +#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) +#define WDOG_WICR_WTIS_MASK (0x4000U) +#define WDOG_WICR_WTIS_SHIFT (14U) +/*! WTIS - WTIS + * 0b0..No interrupt has occurred (Default). + * 0b1..Interrupt has occurred + */ +#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) +#define WDOG_WICR_WIE_MASK (0x8000U) +#define WDOG_WICR_WIE_SHIFT (15U) +/*! WIE - WIE + * 0b0..Disable Interrupt (Default). + * 0b1..Enable Interrupt. + */ +#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK) +/*! @} */ + +/*! @name WMCR - Watchdog Miscellaneous Control Register */ +/*! @{ */ +#define WDOG_WMCR_PDE_MASK (0x1U) +#define WDOG_WMCR_PDE_SHIFT (0U) +/*! PDE - PDE + * 0b0..Power Down Counter of WDOG is disabled. + * 0b1..Power Down Counter of WDOG is enabled (Default). + */ +#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WDOG_Register_Masks */ + + +/* WDOG - Peripheral instance base addresses */ +/** Peripheral WDOG1 base address */ +#define WDOG1_BASE (0x400B8000u) +/** Peripheral WDOG1 base pointer */ +#define WDOG1 ((WDOG_Type *)WDOG1_BASE) +/** Peripheral WDOG2 base address */ +#define WDOG2_BASE (0x400D0000u) +/** Peripheral WDOG2 base pointer */ +#define WDOG2 ((WDOG_Type *)WDOG2_BASE) +/** Array initializer of WDOG peripheral base addresses */ +#define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE } +/** Array initializer of WDOG peripheral base pointers */ +#define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 } +/** Interrupt vectors for the WDOG peripheral type */ +#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn } + +/*! + * @} + */ /* end of group WDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XBARA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARA_Peripheral_Access_Layer XBARA Peripheral Access Layer + * @{ + */ + +/** XBARA - Register Layout Typedef */ +typedef struct { + __IO uint16_t SEL0; /**< Crossbar A Select Register 0, offset: 0x0 */ + __IO uint16_t SEL1; /**< Crossbar A Select Register 1, offset: 0x2 */ + __IO uint16_t SEL2; /**< Crossbar A Select Register 2, offset: 0x4 */ + __IO uint16_t SEL3; /**< Crossbar A Select Register 3, offset: 0x6 */ + __IO uint16_t SEL4; /**< Crossbar A Select Register 4, offset: 0x8 */ + __IO uint16_t SEL5; /**< Crossbar A Select Register 5, offset: 0xA */ + __IO uint16_t SEL6; /**< Crossbar A Select Register 6, offset: 0xC */ + __IO uint16_t SEL7; /**< Crossbar A Select Register 7, offset: 0xE */ + __IO uint16_t SEL8; /**< Crossbar A Select Register 8, offset: 0x10 */ + __IO uint16_t SEL9; /**< Crossbar A Select Register 9, offset: 0x12 */ + __IO uint16_t SEL10; /**< Crossbar A Select Register 10, offset: 0x14 */ + __IO uint16_t SEL11; /**< Crossbar A Select Register 11, offset: 0x16 */ + __IO uint16_t SEL12; /**< Crossbar A Select Register 12, offset: 0x18 */ + __IO uint16_t SEL13; /**< Crossbar A Select Register 13, offset: 0x1A */ + __IO uint16_t SEL14; /**< Crossbar A Select Register 14, offset: 0x1C */ + __IO uint16_t SEL15; /**< Crossbar A Select Register 15, offset: 0x1E */ + __IO uint16_t SEL16; /**< Crossbar A Select Register 16, offset: 0x20 */ + __IO uint16_t SEL17; /**< Crossbar A Select Register 17, offset: 0x22 */ + __IO uint16_t SEL18; /**< Crossbar A Select Register 18, offset: 0x24 */ + __IO uint16_t SEL19; /**< Crossbar A Select Register 19, offset: 0x26 */ + __IO uint16_t SEL20; /**< Crossbar A Select Register 20, offset: 0x28 */ + __IO uint16_t SEL21; /**< Crossbar A Select Register 21, offset: 0x2A */ + __IO uint16_t SEL22; /**< Crossbar A Select Register 22, offset: 0x2C */ + __IO uint16_t SEL23; /**< Crossbar A Select Register 23, offset: 0x2E */ + __IO uint16_t SEL24; /**< Crossbar A Select Register 24, offset: 0x30 */ + __IO uint16_t SEL25; /**< Crossbar A Select Register 25, offset: 0x32 */ + __IO uint16_t SEL26; /**< Crossbar A Select Register 26, offset: 0x34 */ + __IO uint16_t SEL27; /**< Crossbar A Select Register 27, offset: 0x36 */ + __IO uint16_t SEL28; /**< Crossbar A Select Register 28, offset: 0x38 */ + __IO uint16_t SEL29; /**< Crossbar A Select Register 29, offset: 0x3A */ + __IO uint16_t SEL30; /**< Crossbar A Select Register 30, offset: 0x3C */ + __IO uint16_t SEL31; /**< Crossbar A Select Register 31, offset: 0x3E */ + __IO uint16_t SEL32; /**< Crossbar A Select Register 32, offset: 0x40 */ + __IO uint16_t SEL33; /**< Crossbar A Select Register 33, offset: 0x42 */ + __IO uint16_t SEL34; /**< Crossbar A Select Register 34, offset: 0x44 */ + __IO uint16_t SEL35; /**< Crossbar A Select Register 35, offset: 0x46 */ + __IO uint16_t SEL36; /**< Crossbar A Select Register 36, offset: 0x48 */ + __IO uint16_t SEL37; /**< Crossbar A Select Register 37, offset: 0x4A */ + __IO uint16_t SEL38; /**< Crossbar A Select Register 38, offset: 0x4C */ + __IO uint16_t SEL39; /**< Crossbar A Select Register 39, offset: 0x4E */ + __IO uint16_t SEL40; /**< Crossbar A Select Register 40, offset: 0x50 */ + __IO uint16_t SEL41; /**< Crossbar A Select Register 41, offset: 0x52 */ + __IO uint16_t SEL42; /**< Crossbar A Select Register 42, offset: 0x54 */ + __IO uint16_t SEL43; /**< Crossbar A Select Register 43, offset: 0x56 */ + __IO uint16_t SEL44; /**< Crossbar A Select Register 44, offset: 0x58 */ + __IO uint16_t SEL45; /**< Crossbar A Select Register 45, offset: 0x5A */ + __IO uint16_t SEL46; /**< Crossbar A Select Register 46, offset: 0x5C */ + __IO uint16_t SEL47; /**< Crossbar A Select Register 47, offset: 0x5E */ + __IO uint16_t SEL48; /**< Crossbar A Select Register 48, offset: 0x60 */ + __IO uint16_t SEL49; /**< Crossbar A Select Register 49, offset: 0x62 */ + __IO uint16_t SEL50; /**< Crossbar A Select Register 50, offset: 0x64 */ + __IO uint16_t SEL51; /**< Crossbar A Select Register 51, offset: 0x66 */ + __IO uint16_t SEL52; /**< Crossbar A Select Register 52, offset: 0x68 */ + __IO uint16_t SEL53; /**< Crossbar A Select Register 53, offset: 0x6A */ + __IO uint16_t SEL54; /**< Crossbar A Select Register 54, offset: 0x6C */ + __IO uint16_t SEL55; /**< Crossbar A Select Register 55, offset: 0x6E */ + __IO uint16_t SEL56; /**< Crossbar A Select Register 56, offset: 0x70 */ + __IO uint16_t SEL57; /**< Crossbar A Select Register 57, offset: 0x72 */ + __IO uint16_t SEL58; /**< Crossbar A Select Register 58, offset: 0x74 */ + __IO uint16_t SEL59; /**< Crossbar A Select Register 59, offset: 0x76 */ + __IO uint16_t SEL60; /**< Crossbar A Select Register 60, offset: 0x78 */ + __IO uint16_t SEL61; /**< Crossbar A Select Register 61, offset: 0x7A */ + __IO uint16_t SEL62; /**< Crossbar A Select Register 62, offset: 0x7C */ + __IO uint16_t SEL63; /**< Crossbar A Select Register 63, offset: 0x7E */ + __IO uint16_t SEL64; /**< Crossbar A Select Register 64, offset: 0x80 */ + __IO uint16_t SEL65; /**< Crossbar A Select Register 65, offset: 0x82 */ + __IO uint16_t CTRL0; /**< Crossbar A Control Register 0, offset: 0x84 */ + __IO uint16_t CTRL1; /**< Crossbar A Control Register 1, offset: 0x86 */ +} XBARA_Type; + +/* ---------------------------------------------------------------------------- + -- XBARA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARA_Register_Masks XBARA Register Masks + * @{ + */ + +/*! @name SEL0 - Crossbar A Select Register 0 */ +/*! @{ */ +#define XBARA_SEL0_SEL0_MASK (0x7FU) +#define XBARA_SEL0_SEL0_SHIFT (0U) +#define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK) +#define XBARA_SEL0_SEL1_MASK (0x7F00U) +#define XBARA_SEL0_SEL1_SHIFT (8U) +#define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK) +/*! @} */ + +/*! @name SEL1 - Crossbar A Select Register 1 */ +/*! @{ */ +#define XBARA_SEL1_SEL2_MASK (0x7FU) +#define XBARA_SEL1_SEL2_SHIFT (0U) +#define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK) +#define XBARA_SEL1_SEL3_MASK (0x7F00U) +#define XBARA_SEL1_SEL3_SHIFT (8U) +#define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK) +/*! @} */ + +/*! @name SEL2 - Crossbar A Select Register 2 */ +/*! @{ */ +#define XBARA_SEL2_SEL4_MASK (0x7FU) +#define XBARA_SEL2_SEL4_SHIFT (0U) +#define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK) +#define XBARA_SEL2_SEL5_MASK (0x7F00U) +#define XBARA_SEL2_SEL5_SHIFT (8U) +#define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK) +/*! @} */ + +/*! @name SEL3 - Crossbar A Select Register 3 */ +/*! @{ */ +#define XBARA_SEL3_SEL6_MASK (0x7FU) +#define XBARA_SEL3_SEL6_SHIFT (0U) +#define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK) +#define XBARA_SEL3_SEL7_MASK (0x7F00U) +#define XBARA_SEL3_SEL7_SHIFT (8U) +#define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK) +/*! @} */ + +/*! @name SEL4 - Crossbar A Select Register 4 */ +/*! @{ */ +#define XBARA_SEL4_SEL8_MASK (0x7FU) +#define XBARA_SEL4_SEL8_SHIFT (0U) +#define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK) +#define XBARA_SEL4_SEL9_MASK (0x7F00U) +#define XBARA_SEL4_SEL9_SHIFT (8U) +#define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK) +/*! @} */ + +/*! @name SEL5 - Crossbar A Select Register 5 */ +/*! @{ */ +#define XBARA_SEL5_SEL10_MASK (0x7FU) +#define XBARA_SEL5_SEL10_SHIFT (0U) +#define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK) +#define XBARA_SEL5_SEL11_MASK (0x7F00U) +#define XBARA_SEL5_SEL11_SHIFT (8U) +#define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK) +/*! @} */ + +/*! @name SEL6 - Crossbar A Select Register 6 */ +/*! @{ */ +#define XBARA_SEL6_SEL12_MASK (0x7FU) +#define XBARA_SEL6_SEL12_SHIFT (0U) +#define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK) +#define XBARA_SEL6_SEL13_MASK (0x7F00U) +#define XBARA_SEL6_SEL13_SHIFT (8U) +#define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK) +/*! @} */ + +/*! @name SEL7 - Crossbar A Select Register 7 */ +/*! @{ */ +#define XBARA_SEL7_SEL14_MASK (0x7FU) +#define XBARA_SEL7_SEL14_SHIFT (0U) +#define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK) +#define XBARA_SEL7_SEL15_MASK (0x7F00U) +#define XBARA_SEL7_SEL15_SHIFT (8U) +#define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK) +/*! @} */ + +/*! @name SEL8 - Crossbar A Select Register 8 */ +/*! @{ */ +#define XBARA_SEL8_SEL16_MASK (0x7FU) +#define XBARA_SEL8_SEL16_SHIFT (0U) +#define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK) +#define XBARA_SEL8_SEL17_MASK (0x7F00U) +#define XBARA_SEL8_SEL17_SHIFT (8U) +#define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK) +/*! @} */ + +/*! @name SEL9 - Crossbar A Select Register 9 */ +/*! @{ */ +#define XBARA_SEL9_SEL18_MASK (0x7FU) +#define XBARA_SEL9_SEL18_SHIFT (0U) +#define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK) +#define XBARA_SEL9_SEL19_MASK (0x7F00U) +#define XBARA_SEL9_SEL19_SHIFT (8U) +#define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK) +/*! @} */ + +/*! @name SEL10 - Crossbar A Select Register 10 */ +/*! @{ */ +#define XBARA_SEL10_SEL20_MASK (0x7FU) +#define XBARA_SEL10_SEL20_SHIFT (0U) +#define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK) +#define XBARA_SEL10_SEL21_MASK (0x7F00U) +#define XBARA_SEL10_SEL21_SHIFT (8U) +#define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK) +/*! @} */ + +/*! @name SEL11 - Crossbar A Select Register 11 */ +/*! @{ */ +#define XBARA_SEL11_SEL22_MASK (0x7FU) +#define XBARA_SEL11_SEL22_SHIFT (0U) +#define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK) +#define XBARA_SEL11_SEL23_MASK (0x7F00U) +#define XBARA_SEL11_SEL23_SHIFT (8U) +#define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK) +/*! @} */ + +/*! @name SEL12 - Crossbar A Select Register 12 */ +/*! @{ */ +#define XBARA_SEL12_SEL24_MASK (0x7FU) +#define XBARA_SEL12_SEL24_SHIFT (0U) +#define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK) +#define XBARA_SEL12_SEL25_MASK (0x7F00U) +#define XBARA_SEL12_SEL25_SHIFT (8U) +#define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK) +/*! @} */ + +/*! @name SEL13 - Crossbar A Select Register 13 */ +/*! @{ */ +#define XBARA_SEL13_SEL26_MASK (0x7FU) +#define XBARA_SEL13_SEL26_SHIFT (0U) +#define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK) +#define XBARA_SEL13_SEL27_MASK (0x7F00U) +#define XBARA_SEL13_SEL27_SHIFT (8U) +#define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK) +/*! @} */ + +/*! @name SEL14 - Crossbar A Select Register 14 */ +/*! @{ */ +#define XBARA_SEL14_SEL28_MASK (0x7FU) +#define XBARA_SEL14_SEL28_SHIFT (0U) +#define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK) +#define XBARA_SEL14_SEL29_MASK (0x7F00U) +#define XBARA_SEL14_SEL29_SHIFT (8U) +#define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK) +/*! @} */ + +/*! @name SEL15 - Crossbar A Select Register 15 */ +/*! @{ */ +#define XBARA_SEL15_SEL30_MASK (0x7FU) +#define XBARA_SEL15_SEL30_SHIFT (0U) +#define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK) +#define XBARA_SEL15_SEL31_MASK (0x7F00U) +#define XBARA_SEL15_SEL31_SHIFT (8U) +#define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK) +/*! @} */ + +/*! @name SEL16 - Crossbar A Select Register 16 */ +/*! @{ */ +#define XBARA_SEL16_SEL32_MASK (0x7FU) +#define XBARA_SEL16_SEL32_SHIFT (0U) +#define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK) +#define XBARA_SEL16_SEL33_MASK (0x7F00U) +#define XBARA_SEL16_SEL33_SHIFT (8U) +#define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK) +/*! @} */ + +/*! @name SEL17 - Crossbar A Select Register 17 */ +/*! @{ */ +#define XBARA_SEL17_SEL34_MASK (0x7FU) +#define XBARA_SEL17_SEL34_SHIFT (0U) +#define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK) +#define XBARA_SEL17_SEL35_MASK (0x7F00U) +#define XBARA_SEL17_SEL35_SHIFT (8U) +#define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK) +/*! @} */ + +/*! @name SEL18 - Crossbar A Select Register 18 */ +/*! @{ */ +#define XBARA_SEL18_SEL36_MASK (0x7FU) +#define XBARA_SEL18_SEL36_SHIFT (0U) +#define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK) +#define XBARA_SEL18_SEL37_MASK (0x7F00U) +#define XBARA_SEL18_SEL37_SHIFT (8U) +#define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK) +/*! @} */ + +/*! @name SEL19 - Crossbar A Select Register 19 */ +/*! @{ */ +#define XBARA_SEL19_SEL38_MASK (0x7FU) +#define XBARA_SEL19_SEL38_SHIFT (0U) +#define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK) +#define XBARA_SEL19_SEL39_MASK (0x7F00U) +#define XBARA_SEL19_SEL39_SHIFT (8U) +#define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK) +/*! @} */ + +/*! @name SEL20 - Crossbar A Select Register 20 */ +/*! @{ */ +#define XBARA_SEL20_SEL40_MASK (0x7FU) +#define XBARA_SEL20_SEL40_SHIFT (0U) +#define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK) +#define XBARA_SEL20_SEL41_MASK (0x7F00U) +#define XBARA_SEL20_SEL41_SHIFT (8U) +#define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK) +/*! @} */ + +/*! @name SEL21 - Crossbar A Select Register 21 */ +/*! @{ */ +#define XBARA_SEL21_SEL42_MASK (0x7FU) +#define XBARA_SEL21_SEL42_SHIFT (0U) +#define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK) +#define XBARA_SEL21_SEL43_MASK (0x7F00U) +#define XBARA_SEL21_SEL43_SHIFT (8U) +#define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK) +/*! @} */ + +/*! @name SEL22 - Crossbar A Select Register 22 */ +/*! @{ */ +#define XBARA_SEL22_SEL44_MASK (0x7FU) +#define XBARA_SEL22_SEL44_SHIFT (0U) +#define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK) +#define XBARA_SEL22_SEL45_MASK (0x7F00U) +#define XBARA_SEL22_SEL45_SHIFT (8U) +#define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK) +/*! @} */ + +/*! @name SEL23 - Crossbar A Select Register 23 */ +/*! @{ */ +#define XBARA_SEL23_SEL46_MASK (0x7FU) +#define XBARA_SEL23_SEL46_SHIFT (0U) +#define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK) +#define XBARA_SEL23_SEL47_MASK (0x7F00U) +#define XBARA_SEL23_SEL47_SHIFT (8U) +#define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK) +/*! @} */ + +/*! @name SEL24 - Crossbar A Select Register 24 */ +/*! @{ */ +#define XBARA_SEL24_SEL48_MASK (0x7FU) +#define XBARA_SEL24_SEL48_SHIFT (0U) +#define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK) +#define XBARA_SEL24_SEL49_MASK (0x7F00U) +#define XBARA_SEL24_SEL49_SHIFT (8U) +#define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK) +/*! @} */ + +/*! @name SEL25 - Crossbar A Select Register 25 */ +/*! @{ */ +#define XBARA_SEL25_SEL50_MASK (0x7FU) +#define XBARA_SEL25_SEL50_SHIFT (0U) +#define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK) +#define XBARA_SEL25_SEL51_MASK (0x7F00U) +#define XBARA_SEL25_SEL51_SHIFT (8U) +#define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK) +/*! @} */ + +/*! @name SEL26 - Crossbar A Select Register 26 */ +/*! @{ */ +#define XBARA_SEL26_SEL52_MASK (0x7FU) +#define XBARA_SEL26_SEL52_SHIFT (0U) +#define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK) +#define XBARA_SEL26_SEL53_MASK (0x7F00U) +#define XBARA_SEL26_SEL53_SHIFT (8U) +#define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK) +/*! @} */ + +/*! @name SEL27 - Crossbar A Select Register 27 */ +/*! @{ */ +#define XBARA_SEL27_SEL54_MASK (0x7FU) +#define XBARA_SEL27_SEL54_SHIFT (0U) +#define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK) +#define XBARA_SEL27_SEL55_MASK (0x7F00U) +#define XBARA_SEL27_SEL55_SHIFT (8U) +#define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK) +/*! @} */ + +/*! @name SEL28 - Crossbar A Select Register 28 */ +/*! @{ */ +#define XBARA_SEL28_SEL56_MASK (0x7FU) +#define XBARA_SEL28_SEL56_SHIFT (0U) +#define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK) +#define XBARA_SEL28_SEL57_MASK (0x7F00U) +#define XBARA_SEL28_SEL57_SHIFT (8U) +#define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK) +/*! @} */ + +/*! @name SEL29 - Crossbar A Select Register 29 */ +/*! @{ */ +#define XBARA_SEL29_SEL58_MASK (0x7FU) +#define XBARA_SEL29_SEL58_SHIFT (0U) +#define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK) +#define XBARA_SEL29_SEL59_MASK (0x7F00U) +#define XBARA_SEL29_SEL59_SHIFT (8U) +#define XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK) +/*! @} */ + +/*! @name SEL30 - Crossbar A Select Register 30 */ +/*! @{ */ +#define XBARA_SEL30_SEL60_MASK (0x7FU) +#define XBARA_SEL30_SEL60_SHIFT (0U) +#define XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK) +#define XBARA_SEL30_SEL61_MASK (0x7F00U) +#define XBARA_SEL30_SEL61_SHIFT (8U) +#define XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK) +/*! @} */ + +/*! @name SEL31 - Crossbar A Select Register 31 */ +/*! @{ */ +#define XBARA_SEL31_SEL62_MASK (0x7FU) +#define XBARA_SEL31_SEL62_SHIFT (0U) +#define XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK) +#define XBARA_SEL31_SEL63_MASK (0x7F00U) +#define XBARA_SEL31_SEL63_SHIFT (8U) +#define XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK) +/*! @} */ + +/*! @name SEL32 - Crossbar A Select Register 32 */ +/*! @{ */ +#define XBARA_SEL32_SEL64_MASK (0x7FU) +#define XBARA_SEL32_SEL64_SHIFT (0U) +#define XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK) +#define XBARA_SEL32_SEL65_MASK (0x7F00U) +#define XBARA_SEL32_SEL65_SHIFT (8U) +#define XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK) +/*! @} */ + +/*! @name SEL33 - Crossbar A Select Register 33 */ +/*! @{ */ +#define XBARA_SEL33_SEL66_MASK (0x7FU) +#define XBARA_SEL33_SEL66_SHIFT (0U) +#define XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK) +#define XBARA_SEL33_SEL67_MASK (0x7F00U) +#define XBARA_SEL33_SEL67_SHIFT (8U) +#define XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK) +/*! @} */ + +/*! @name SEL34 - Crossbar A Select Register 34 */ +/*! @{ */ +#define XBARA_SEL34_SEL68_MASK (0x7FU) +#define XBARA_SEL34_SEL68_SHIFT (0U) +#define XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK) +#define XBARA_SEL34_SEL69_MASK (0x7F00U) +#define XBARA_SEL34_SEL69_SHIFT (8U) +#define XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK) +/*! @} */ + +/*! @name SEL35 - Crossbar A Select Register 35 */ +/*! @{ */ +#define XBARA_SEL35_SEL70_MASK (0x7FU) +#define XBARA_SEL35_SEL70_SHIFT (0U) +#define XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK) +#define XBARA_SEL35_SEL71_MASK (0x7F00U) +#define XBARA_SEL35_SEL71_SHIFT (8U) +#define XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK) +/*! @} */ + +/*! @name SEL36 - Crossbar A Select Register 36 */ +/*! @{ */ +#define XBARA_SEL36_SEL72_MASK (0x7FU) +#define XBARA_SEL36_SEL72_SHIFT (0U) +#define XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK) +#define XBARA_SEL36_SEL73_MASK (0x7F00U) +#define XBARA_SEL36_SEL73_SHIFT (8U) +#define XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK) +/*! @} */ + +/*! @name SEL37 - Crossbar A Select Register 37 */ +/*! @{ */ +#define XBARA_SEL37_SEL74_MASK (0x7FU) +#define XBARA_SEL37_SEL74_SHIFT (0U) +#define XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK) +#define XBARA_SEL37_SEL75_MASK (0x7F00U) +#define XBARA_SEL37_SEL75_SHIFT (8U) +#define XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK) +/*! @} */ + +/*! @name SEL38 - Crossbar A Select Register 38 */ +/*! @{ */ +#define XBARA_SEL38_SEL76_MASK (0x7FU) +#define XBARA_SEL38_SEL76_SHIFT (0U) +#define XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK) +#define XBARA_SEL38_SEL77_MASK (0x7F00U) +#define XBARA_SEL38_SEL77_SHIFT (8U) +#define XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK) +/*! @} */ + +/*! @name SEL39 - Crossbar A Select Register 39 */ +/*! @{ */ +#define XBARA_SEL39_SEL78_MASK (0x7FU) +#define XBARA_SEL39_SEL78_SHIFT (0U) +#define XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK) +#define XBARA_SEL39_SEL79_MASK (0x7F00U) +#define XBARA_SEL39_SEL79_SHIFT (8U) +#define XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK) +/*! @} */ + +/*! @name SEL40 - Crossbar A Select Register 40 */ +/*! @{ */ +#define XBARA_SEL40_SEL80_MASK (0x7FU) +#define XBARA_SEL40_SEL80_SHIFT (0U) +#define XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK) +#define XBARA_SEL40_SEL81_MASK (0x7F00U) +#define XBARA_SEL40_SEL81_SHIFT (8U) +#define XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK) +/*! @} */ + +/*! @name SEL41 - Crossbar A Select Register 41 */ +/*! @{ */ +#define XBARA_SEL41_SEL82_MASK (0x7FU) +#define XBARA_SEL41_SEL82_SHIFT (0U) +#define XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK) +#define XBARA_SEL41_SEL83_MASK (0x7F00U) +#define XBARA_SEL41_SEL83_SHIFT (8U) +#define XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK) +/*! @} */ + +/*! @name SEL42 - Crossbar A Select Register 42 */ +/*! @{ */ +#define XBARA_SEL42_SEL84_MASK (0x7FU) +#define XBARA_SEL42_SEL84_SHIFT (0U) +#define XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK) +#define XBARA_SEL42_SEL85_MASK (0x7F00U) +#define XBARA_SEL42_SEL85_SHIFT (8U) +#define XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK) +/*! @} */ + +/*! @name SEL43 - Crossbar A Select Register 43 */ +/*! @{ */ +#define XBARA_SEL43_SEL86_MASK (0x7FU) +#define XBARA_SEL43_SEL86_SHIFT (0U) +#define XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK) +#define XBARA_SEL43_SEL87_MASK (0x7F00U) +#define XBARA_SEL43_SEL87_SHIFT (8U) +#define XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK) +/*! @} */ + +/*! @name SEL44 - Crossbar A Select Register 44 */ +/*! @{ */ +#define XBARA_SEL44_SEL88_MASK (0x7FU) +#define XBARA_SEL44_SEL88_SHIFT (0U) +#define XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK) +#define XBARA_SEL44_SEL89_MASK (0x7F00U) +#define XBARA_SEL44_SEL89_SHIFT (8U) +#define XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK) +/*! @} */ + +/*! @name SEL45 - Crossbar A Select Register 45 */ +/*! @{ */ +#define XBARA_SEL45_SEL90_MASK (0x7FU) +#define XBARA_SEL45_SEL90_SHIFT (0U) +#define XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK) +#define XBARA_SEL45_SEL91_MASK (0x7F00U) +#define XBARA_SEL45_SEL91_SHIFT (8U) +#define XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK) +/*! @} */ + +/*! @name SEL46 - Crossbar A Select Register 46 */ +/*! @{ */ +#define XBARA_SEL46_SEL92_MASK (0x7FU) +#define XBARA_SEL46_SEL92_SHIFT (0U) +#define XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK) +#define XBARA_SEL46_SEL93_MASK (0x7F00U) +#define XBARA_SEL46_SEL93_SHIFT (8U) +#define XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK) +/*! @} */ + +/*! @name SEL47 - Crossbar A Select Register 47 */ +/*! @{ */ +#define XBARA_SEL47_SEL94_MASK (0x7FU) +#define XBARA_SEL47_SEL94_SHIFT (0U) +#define XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK) +#define XBARA_SEL47_SEL95_MASK (0x7F00U) +#define XBARA_SEL47_SEL95_SHIFT (8U) +#define XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK) +/*! @} */ + +/*! @name SEL48 - Crossbar A Select Register 48 */ +/*! @{ */ +#define XBARA_SEL48_SEL96_MASK (0x7FU) +#define XBARA_SEL48_SEL96_SHIFT (0U) +#define XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK) +#define XBARA_SEL48_SEL97_MASK (0x7F00U) +#define XBARA_SEL48_SEL97_SHIFT (8U) +#define XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK) +/*! @} */ + +/*! @name SEL49 - Crossbar A Select Register 49 */ +/*! @{ */ +#define XBARA_SEL49_SEL98_MASK (0x7FU) +#define XBARA_SEL49_SEL98_SHIFT (0U) +#define XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK) +#define XBARA_SEL49_SEL99_MASK (0x7F00U) +#define XBARA_SEL49_SEL99_SHIFT (8U) +#define XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK) +/*! @} */ + +/*! @name SEL50 - Crossbar A Select Register 50 */ +/*! @{ */ +#define XBARA_SEL50_SEL100_MASK (0x7FU) +#define XBARA_SEL50_SEL100_SHIFT (0U) +#define XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK) +#define XBARA_SEL50_SEL101_MASK (0x7F00U) +#define XBARA_SEL50_SEL101_SHIFT (8U) +#define XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK) +/*! @} */ + +/*! @name SEL51 - Crossbar A Select Register 51 */ +/*! @{ */ +#define XBARA_SEL51_SEL102_MASK (0x7FU) +#define XBARA_SEL51_SEL102_SHIFT (0U) +#define XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK) +#define XBARA_SEL51_SEL103_MASK (0x7F00U) +#define XBARA_SEL51_SEL103_SHIFT (8U) +#define XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK) +/*! @} */ + +/*! @name SEL52 - Crossbar A Select Register 52 */ +/*! @{ */ +#define XBARA_SEL52_SEL104_MASK (0x7FU) +#define XBARA_SEL52_SEL104_SHIFT (0U) +#define XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK) +#define XBARA_SEL52_SEL105_MASK (0x7F00U) +#define XBARA_SEL52_SEL105_SHIFT (8U) +#define XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK) +/*! @} */ + +/*! @name SEL53 - Crossbar A Select Register 53 */ +/*! @{ */ +#define XBARA_SEL53_SEL106_MASK (0x7FU) +#define XBARA_SEL53_SEL106_SHIFT (0U) +#define XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK) +#define XBARA_SEL53_SEL107_MASK (0x7F00U) +#define XBARA_SEL53_SEL107_SHIFT (8U) +#define XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK) +/*! @} */ + +/*! @name SEL54 - Crossbar A Select Register 54 */ +/*! @{ */ +#define XBARA_SEL54_SEL108_MASK (0x7FU) +#define XBARA_SEL54_SEL108_SHIFT (0U) +#define XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK) +#define XBARA_SEL54_SEL109_MASK (0x7F00U) +#define XBARA_SEL54_SEL109_SHIFT (8U) +#define XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK) +/*! @} */ + +/*! @name SEL55 - Crossbar A Select Register 55 */ +/*! @{ */ +#define XBARA_SEL55_SEL110_MASK (0x7FU) +#define XBARA_SEL55_SEL110_SHIFT (0U) +#define XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK) +#define XBARA_SEL55_SEL111_MASK (0x7F00U) +#define XBARA_SEL55_SEL111_SHIFT (8U) +#define XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK) +/*! @} */ + +/*! @name SEL56 - Crossbar A Select Register 56 */ +/*! @{ */ +#define XBARA_SEL56_SEL112_MASK (0x7FU) +#define XBARA_SEL56_SEL112_SHIFT (0U) +#define XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK) +#define XBARA_SEL56_SEL113_MASK (0x7F00U) +#define XBARA_SEL56_SEL113_SHIFT (8U) +#define XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK) +/*! @} */ + +/*! @name SEL57 - Crossbar A Select Register 57 */ +/*! @{ */ +#define XBARA_SEL57_SEL114_MASK (0x7FU) +#define XBARA_SEL57_SEL114_SHIFT (0U) +#define XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK) +#define XBARA_SEL57_SEL115_MASK (0x7F00U) +#define XBARA_SEL57_SEL115_SHIFT (8U) +#define XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK) +/*! @} */ + +/*! @name SEL58 - Crossbar A Select Register 58 */ +/*! @{ */ +#define XBARA_SEL58_SEL116_MASK (0x7FU) +#define XBARA_SEL58_SEL116_SHIFT (0U) +#define XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK) +#define XBARA_SEL58_SEL117_MASK (0x7F00U) +#define XBARA_SEL58_SEL117_SHIFT (8U) +#define XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK) +/*! @} */ + +/*! @name SEL59 - Crossbar A Select Register 59 */ +/*! @{ */ +#define XBARA_SEL59_SEL118_MASK (0x7FU) +#define XBARA_SEL59_SEL118_SHIFT (0U) +#define XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK) +#define XBARA_SEL59_SEL119_MASK (0x7F00U) +#define XBARA_SEL59_SEL119_SHIFT (8U) +#define XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK) +/*! @} */ + +/*! @name SEL60 - Crossbar A Select Register 60 */ +/*! @{ */ +#define XBARA_SEL60_SEL120_MASK (0x7FU) +#define XBARA_SEL60_SEL120_SHIFT (0U) +#define XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK) +#define XBARA_SEL60_SEL121_MASK (0x7F00U) +#define XBARA_SEL60_SEL121_SHIFT (8U) +#define XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK) +/*! @} */ + +/*! @name SEL61 - Crossbar A Select Register 61 */ +/*! @{ */ +#define XBARA_SEL61_SEL122_MASK (0x7FU) +#define XBARA_SEL61_SEL122_SHIFT (0U) +#define XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK) +#define XBARA_SEL61_SEL123_MASK (0x7F00U) +#define XBARA_SEL61_SEL123_SHIFT (8U) +#define XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK) +/*! @} */ + +/*! @name SEL62 - Crossbar A Select Register 62 */ +/*! @{ */ +#define XBARA_SEL62_SEL124_MASK (0x7FU) +#define XBARA_SEL62_SEL124_SHIFT (0U) +#define XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK) +#define XBARA_SEL62_SEL125_MASK (0x7F00U) +#define XBARA_SEL62_SEL125_SHIFT (8U) +#define XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK) +/*! @} */ + +/*! @name SEL63 - Crossbar A Select Register 63 */ +/*! @{ */ +#define XBARA_SEL63_SEL126_MASK (0x7FU) +#define XBARA_SEL63_SEL126_SHIFT (0U) +#define XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK) +#define XBARA_SEL63_SEL127_MASK (0x7F00U) +#define XBARA_SEL63_SEL127_SHIFT (8U) +#define XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK) +/*! @} */ + +/*! @name SEL64 - Crossbar A Select Register 64 */ +/*! @{ */ +#define XBARA_SEL64_SEL128_MASK (0x7FU) +#define XBARA_SEL64_SEL128_SHIFT (0U) +#define XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK) +#define XBARA_SEL64_SEL129_MASK (0x7F00U) +#define XBARA_SEL64_SEL129_SHIFT (8U) +#define XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK) +/*! @} */ + +/*! @name SEL65 - Crossbar A Select Register 65 */ +/*! @{ */ +#define XBARA_SEL65_SEL130_MASK (0x7FU) +#define XBARA_SEL65_SEL130_SHIFT (0U) +#define XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK) +#define XBARA_SEL65_SEL131_MASK (0x7F00U) +#define XBARA_SEL65_SEL131_SHIFT (8U) +#define XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK) +/*! @} */ + +/*! @name CTRL0 - Crossbar A Control Register 0 */ +/*! @{ */ +#define XBARA_CTRL0_DEN0_MASK (0x1U) +#define XBARA_CTRL0_DEN0_SHIFT (0U) +/*! DEN0 - DMA Enable for XBAR_OUT0 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ +#define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK) +#define XBARA_CTRL0_IEN0_MASK (0x2U) +#define XBARA_CTRL0_IEN0_SHIFT (1U) +/*! IEN0 - Interrupt Enable for XBAR_OUT0 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK) +#define XBARA_CTRL0_EDGE0_MASK (0xCU) +#define XBARA_CTRL0_EDGE0_SHIFT (2U) +/*! EDGE0 - Active edge for edge detection on XBAR_OUT0 + * 0b00..STS0 never asserts + * 0b01..STS0 asserts on rising edges of XBAR_OUT0 + * 0b10..STS0 asserts on falling edges of XBAR_OUT0 + * 0b11..STS0 asserts on rising and falling edges of XBAR_OUT0 + */ +#define XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK) +#define XBARA_CTRL0_STS0_MASK (0x10U) +#define XBARA_CTRL0_STS0_SHIFT (4U) +/*! STS0 - Edge detection status for XBAR_OUT0 + * 0b0..Active edge not yet detected on XBAR_OUT0 + * 0b1..Active edge detected on XBAR_OUT0 + */ +#define XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK) +#define XBARA_CTRL0_DEN1_MASK (0x100U) +#define XBARA_CTRL0_DEN1_SHIFT (8U) +/*! DEN1 - DMA Enable for XBAR_OUT1 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ +#define XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK) +#define XBARA_CTRL0_IEN1_MASK (0x200U) +#define XBARA_CTRL0_IEN1_SHIFT (9U) +/*! IEN1 - Interrupt Enable for XBAR_OUT1 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK) +#define XBARA_CTRL0_EDGE1_MASK (0xC00U) +#define XBARA_CTRL0_EDGE1_SHIFT (10U) +/*! EDGE1 - Active edge for edge detection on XBAR_OUT1 + * 0b00..STS1 never asserts + * 0b01..STS1 asserts on rising edges of XBAR_OUT1 + * 0b10..STS1 asserts on falling edges of XBAR_OUT1 + * 0b11..STS1 asserts on rising and falling edges of XBAR_OUT1 + */ +#define XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK) +#define XBARA_CTRL0_STS1_MASK (0x1000U) +#define XBARA_CTRL0_STS1_SHIFT (12U) +/*! STS1 - Edge detection status for XBAR_OUT1 + * 0b0..Active edge not yet detected on XBAR_OUT1 + * 0b1..Active edge detected on XBAR_OUT1 + */ +#define XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK) +/*! @} */ + +/*! @name CTRL1 - Crossbar A Control Register 1 */ +/*! @{ */ +#define XBARA_CTRL1_DEN2_MASK (0x1U) +#define XBARA_CTRL1_DEN2_SHIFT (0U) +/*! DEN2 - DMA Enable for XBAR_OUT2 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ +#define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK) +#define XBARA_CTRL1_IEN2_MASK (0x2U) +#define XBARA_CTRL1_IEN2_SHIFT (1U) +/*! IEN2 - Interrupt Enable for XBAR_OUT2 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK) +#define XBARA_CTRL1_EDGE2_MASK (0xCU) +#define XBARA_CTRL1_EDGE2_SHIFT (2U) +/*! EDGE2 - Active edge for edge detection on XBAR_OUT2 + * 0b00..STS2 never asserts + * 0b01..STS2 asserts on rising edges of XBAR_OUT2 + * 0b10..STS2 asserts on falling edges of XBAR_OUT2 + * 0b11..STS2 asserts on rising and falling edges of XBAR_OUT2 + */ +#define XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK) +#define XBARA_CTRL1_STS2_MASK (0x10U) +#define XBARA_CTRL1_STS2_SHIFT (4U) +/*! STS2 - Edge detection status for XBAR_OUT2 + * 0b0..Active edge not yet detected on XBAR_OUT2 + * 0b1..Active edge detected on XBAR_OUT2 + */ +#define XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK) +#define XBARA_CTRL1_DEN3_MASK (0x100U) +#define XBARA_CTRL1_DEN3_SHIFT (8U) +/*! DEN3 - DMA Enable for XBAR_OUT3 + * 0b0..DMA disabled + * 0b1..DMA enabled + */ +#define XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK) +#define XBARA_CTRL1_IEN3_MASK (0x200U) +#define XBARA_CTRL1_IEN3_SHIFT (9U) +/*! IEN3 - Interrupt Enable for XBAR_OUT3 + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK) +#define XBARA_CTRL1_EDGE3_MASK (0xC00U) +#define XBARA_CTRL1_EDGE3_SHIFT (10U) +/*! EDGE3 - Active edge for edge detection on XBAR_OUT3 + * 0b00..STS3 never asserts + * 0b01..STS3 asserts on rising edges of XBAR_OUT3 + * 0b10..STS3 asserts on falling edges of XBAR_OUT3 + * 0b11..STS3 asserts on rising and falling edges of XBAR_OUT3 + */ +#define XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK) +#define XBARA_CTRL1_STS3_MASK (0x1000U) +#define XBARA_CTRL1_STS3_SHIFT (12U) +/*! STS3 - Edge detection status for XBAR_OUT3 + * 0b0..Active edge not yet detected on XBAR_OUT3 + * 0b1..Active edge detected on XBAR_OUT3 + */ +#define XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group XBARA_Register_Masks */ + + +/* XBARA - Peripheral instance base addresses */ +/** Peripheral XBARA1 base address */ +#define XBARA1_BASE (0x403BC000u) +/** Peripheral XBARA1 base pointer */ +#define XBARA1 ((XBARA_Type *)XBARA1_BASE) +/** Array initializer of XBARA peripheral base addresses */ +#define XBARA_BASE_ADDRS { XBARA1_BASE } +/** Array initializer of XBARA peripheral base pointers */ +#define XBARA_BASE_PTRS { XBARA1 } + +/*! + * @} + */ /* end of group XBARA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XBARB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARB_Peripheral_Access_Layer XBARB Peripheral Access Layer + * @{ + */ + +/** XBARB - Register Layout Typedef */ +typedef struct { + __IO uint16_t SEL0; /**< Crossbar B Select Register 0, offset: 0x0 */ + __IO uint16_t SEL1; /**< Crossbar B Select Register 1, offset: 0x2 */ + __IO uint16_t SEL2; /**< Crossbar B Select Register 2, offset: 0x4 */ + __IO uint16_t SEL3; /**< Crossbar B Select Register 3, offset: 0x6 */ + __IO uint16_t SEL4; /**< Crossbar B Select Register 4, offset: 0x8 */ + __IO uint16_t SEL5; /**< Crossbar B Select Register 5, offset: 0xA */ + __IO uint16_t SEL6; /**< Crossbar B Select Register 6, offset: 0xC */ + __IO uint16_t SEL7; /**< Crossbar B Select Register 7, offset: 0xE */ +} XBARB_Type; + +/* ---------------------------------------------------------------------------- + -- XBARB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XBARB_Register_Masks XBARB Register Masks + * @{ + */ + +/*! @name SEL0 - Crossbar B Select Register 0 */ +/*! @{ */ +#define XBARB_SEL0_SEL0_MASK (0x3FU) +#define XBARB_SEL0_SEL0_SHIFT (0U) +#define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK) +#define XBARB_SEL0_SEL1_MASK (0x3F00U) +#define XBARB_SEL0_SEL1_SHIFT (8U) +#define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK) +/*! @} */ + +/*! @name SEL1 - Crossbar B Select Register 1 */ +/*! @{ */ +#define XBARB_SEL1_SEL2_MASK (0x3FU) +#define XBARB_SEL1_SEL2_SHIFT (0U) +#define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK) +#define XBARB_SEL1_SEL3_MASK (0x3F00U) +#define XBARB_SEL1_SEL3_SHIFT (8U) +#define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK) +/*! @} */ + +/*! @name SEL2 - Crossbar B Select Register 2 */ +/*! @{ */ +#define XBARB_SEL2_SEL4_MASK (0x3FU) +#define XBARB_SEL2_SEL4_SHIFT (0U) +#define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK) +#define XBARB_SEL2_SEL5_MASK (0x3F00U) +#define XBARB_SEL2_SEL5_SHIFT (8U) +#define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK) +/*! @} */ + +/*! @name SEL3 - Crossbar B Select Register 3 */ +/*! @{ */ +#define XBARB_SEL3_SEL6_MASK (0x3FU) +#define XBARB_SEL3_SEL6_SHIFT (0U) +#define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK) +#define XBARB_SEL3_SEL7_MASK (0x3F00U) +#define XBARB_SEL3_SEL7_SHIFT (8U) +#define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK) +/*! @} */ + +/*! @name SEL4 - Crossbar B Select Register 4 */ +/*! @{ */ +#define XBARB_SEL4_SEL8_MASK (0x3FU) +#define XBARB_SEL4_SEL8_SHIFT (0U) +#define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK) +#define XBARB_SEL4_SEL9_MASK (0x3F00U) +#define XBARB_SEL4_SEL9_SHIFT (8U) +#define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK) +/*! @} */ + +/*! @name SEL5 - Crossbar B Select Register 5 */ +/*! @{ */ +#define XBARB_SEL5_SEL10_MASK (0x3FU) +#define XBARB_SEL5_SEL10_SHIFT (0U) +#define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK) +#define XBARB_SEL5_SEL11_MASK (0x3F00U) +#define XBARB_SEL5_SEL11_SHIFT (8U) +#define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK) +/*! @} */ + +/*! @name SEL6 - Crossbar B Select Register 6 */ +/*! @{ */ +#define XBARB_SEL6_SEL12_MASK (0x3FU) +#define XBARB_SEL6_SEL12_SHIFT (0U) +#define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK) +#define XBARB_SEL6_SEL13_MASK (0x3F00U) +#define XBARB_SEL6_SEL13_SHIFT (8U) +#define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK) +/*! @} */ + +/*! @name SEL7 - Crossbar B Select Register 7 */ +/*! @{ */ +#define XBARB_SEL7_SEL14_MASK (0x3FU) +#define XBARB_SEL7_SEL14_SHIFT (0U) +#define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK) +#define XBARB_SEL7_SEL15_MASK (0x3F00U) +#define XBARB_SEL7_SEL15_SHIFT (8U) +#define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group XBARB_Register_Masks */ + + +/* XBARB - Peripheral instance base addresses */ +/** Peripheral XBARB2 base address */ +#define XBARB2_BASE (0x403C0000u) +/** Peripheral XBARB2 base pointer */ +#define XBARB2 ((XBARB_Type *)XBARB2_BASE) +/** Peripheral XBARB3 base address */ +#define XBARB3_BASE (0x403C4000u) +/** Peripheral XBARB3 base pointer */ +#define XBARB3 ((XBARB_Type *)XBARB3_BASE) +/** Array initializer of XBARB peripheral base addresses */ +#define XBARB_BASE_ADDRS { 0u, 0u, XBARB2_BASE, XBARB3_BASE } +/** Array initializer of XBARB peripheral base pointers */ +#define XBARB_BASE_PTRS { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 } + +/*! + * @} + */ /* end of group XBARB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Peripheral_Access_Layer XTALOSC24M Peripheral Access Layer + * @{ + */ + +/** XTALOSC24M - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[336]; + __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */ + __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */ + __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */ + __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */ + uint8_t RESERVED_1[272]; + __IO uint32_t LOWPWR_CTRL; /**< XTAL OSC (LP) Control Register, offset: 0x270 */ + __IO uint32_t LOWPWR_CTRL_SET; /**< XTAL OSC (LP) Control Register, offset: 0x274 */ + __IO uint32_t LOWPWR_CTRL_CLR; /**< XTAL OSC (LP) Control Register, offset: 0x278 */ + __IO uint32_t LOWPWR_CTRL_TOG; /**< XTAL OSC (LP) Control Register, offset: 0x27C */ + uint8_t RESERVED_2[32]; + __IO uint32_t OSC_CONFIG0; /**< XTAL OSC Configuration 0 Register, offset: 0x2A0 */ + __IO uint32_t OSC_CONFIG0_SET; /**< XTAL OSC Configuration 0 Register, offset: 0x2A4 */ + __IO uint32_t OSC_CONFIG0_CLR; /**< XTAL OSC Configuration 0 Register, offset: 0x2A8 */ + __IO uint32_t OSC_CONFIG0_TOG; /**< XTAL OSC Configuration 0 Register, offset: 0x2AC */ + __IO uint32_t OSC_CONFIG1; /**< XTAL OSC Configuration 1 Register, offset: 0x2B0 */ + __IO uint32_t OSC_CONFIG1_SET; /**< XTAL OSC Configuration 1 Register, offset: 0x2B4 */ + __IO uint32_t OSC_CONFIG1_CLR; /**< XTAL OSC Configuration 1 Register, offset: 0x2B8 */ + __IO uint32_t OSC_CONFIG1_TOG; /**< XTAL OSC Configuration 1 Register, offset: 0x2BC */ + __IO uint32_t OSC_CONFIG2; /**< XTAL OSC Configuration 2 Register, offset: 0x2C0 */ + __IO uint32_t OSC_CONFIG2_SET; /**< XTAL OSC Configuration 2 Register, offset: 0x2C4 */ + __IO uint32_t OSC_CONFIG2_CLR; /**< XTAL OSC Configuration 2 Register, offset: 0x2C8 */ + __IO uint32_t OSC_CONFIG2_TOG; /**< XTAL OSC Configuration 2 Register, offset: 0x2CC */ +} XTALOSC24M_Type; + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Register_Masks XTALOSC24M Register Masks + * @{ + */ + +/*! @name MISC0 - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define XTALOSC24M_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define XTALOSC24M_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define XTALOSC24M_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_I_SHIFT)) & XTALOSC24M_MISC0_OSC_I_MASK) +#define XTALOSC24M_MISC0_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define XTALOSC24M_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define XTALOSC24M_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define XTALOSC24M_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define XTALOSC24M_MISC0_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_SET - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define XTALOSC24M_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_SET_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_SET_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_SET_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_SET_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_SET_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define XTALOSC24M_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_I_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_I_MASK) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_SET_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define XTALOSC24M_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define XTALOSC24M_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_SET_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_SET_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_SET_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define XTALOSC24M_MISC0_SET_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_SET_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_CLR - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_CLR_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_CLR_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_CLR_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_CLR_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_CLR_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define XTALOSC24M_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_I_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_I_MASK) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_CLR_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define XTALOSC24M_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define XTALOSC24M_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_CLR_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_CLR_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_CLR_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_CLR_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name MISC0_TOG - Miscellaneous Register 0 */ +/*! @{ */ +#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK (0x1U) +#define XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT (0U) +#define XTALOSC24M_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_PWD_MASK) +#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U) +#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U) +/*! REFTOP_SELFBIASOFF + * 0b0..Uses coarse bias currents for startup + * 0b1..Uses bandgap-based bias currents for best performance. + */ +#define XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_SELFBIASOFF_MASK) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U) +/*! REFTOP_VBGADJ + * 0b000..Nominal VBG + * 0b001..VBG+0.78% + * 0b010..VBG+1.56% + * 0b011..VBG+2.34% + * 0b100..VBG-0.78% + * 0b101..VBG-1.56% + * 0b110..VBG-2.34% + * 0b111..VBG-3.12% + */ +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGADJ_MASK) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U) +#define XTALOSC24M_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & XTALOSC24M_MISC0_TOG_REFTOP_VBGUP_MASK) +#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U) +#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U) +/*! STOP_MODE_CONFIG + * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + */ +#define XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & XTALOSC24M_MISC0_TOG_STOP_MODE_CONFIG_MASK) +#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U) +#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U) +/*! DISCON_HIGH_SNVS + * 0b0..Turn on the switch + * 0b1..Turn off the switch + */ +#define XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & XTALOSC24M_MISC0_TOG_DISCON_HIGH_SNVS_MASK) +#define XTALOSC24M_MISC0_TOG_OSC_I_MASK (0x6000U) +#define XTALOSC24M_MISC0_TOG_OSC_I_SHIFT (13U) +/*! OSC_I + * 0b00..Nominal + * 0b01..Decrease current by 12.5% + * 0b10..Decrease current by 25.0% + * 0b11..Decrease current by 37.5% + */ +#define XTALOSC24M_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_I_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_I_MASK) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK (0x8000U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT (15U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_MASK) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U) +#define XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & XTALOSC24M_MISC0_TOG_OSC_XTALOK_EN_MASK) +#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U) +#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U) +/*! CLKGATE_CTRL + * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down. + * 0b1..Prevent the logic from ever gating off the clock. + */ +#define XTALOSC24M_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_CTRL_MASK) +#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U) +#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U) +/*! CLKGATE_DELAY + * 0b000..0.5ms + * 0b001..1.0ms + * 0b010..2.0ms + * 0b011..3.0ms + * 0b100..4.0ms + * 0b101..5.0ms + * 0b110..6.0ms + * 0b111..7.0ms + */ +#define XTALOSC24M_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & XTALOSC24M_MISC0_TOG_CLKGATE_DELAY_MASK) +#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U) +#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U) +/*! RTC_XTAL_SOURCE + * 0b0..Internal ring oscillator + * 0b1..RTC_XTAL + */ +#define XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & XTALOSC24M_MISC0_TOG_RTC_XTAL_SOURCE_MASK) +#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U) +#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U) +#define XTALOSC24M_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & XTALOSC24M_MISC0_TOG_XTAL_24M_PWD_MASK) +#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK (0x80000000U) +#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT (31U) +/*! VID_PLL_PREDIV + * 0b0..Divide by 1 + * 0b1..Divide by 2 + */ +#define XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_SHIFT)) & XTALOSC24M_MISC0_TOG_VID_PLL_PREDIV_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ +#define XTALOSC24M_LOWPWR_CTRL_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ +#define XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL_SET - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ +#define XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL_CLR - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ +#define XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name LOWPWR_CTRL_TOG - XTAL OSC (LP) Control Register */ +/*! @{ */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK (0x1U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT (0U) +/*! RC_OSC_EN + * 0b0..Use XTAL OSC to source the 24MHz clock + * 0b1..Use RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RC_OSC_EN_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK (0x10U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT (4U) +/*! OSC_SEL + * 0b0..XTAL OSC + * 0b1..RC OSC + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_OSC_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK (0x20U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT (5U) +/*! LPBG_SEL + * 0b0..Normal power bandgap + * 0b1..Low power bandgap + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_SEL_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK (0x40U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT (6U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_LPBG_TEST_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK (0x80U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT (7U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_REFTOP_IBIAS_OFF_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK (0x100U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT (8U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK (0x200U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT (9U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK (0x400U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT (10U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK (0x800U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT (11U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK (0x2000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT (13U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_RCOSC_CG_OVERRIDE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK (0xC000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT (14U) +/*! XTALOSC_PWRUP_DELAY + * 0b00..0.25ms + * 0b01..0.5ms + * 0b10..1ms + * 0b11..2ms + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_DELAY_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK (0x10000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT (16U) +/*! XTALOSC_PWRUP_STAT + * 0b0..Not stable + * 0b1..Stable and ready to use + */ +#define XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_XTALOSC_PWRUP_STAT_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK (0x20000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT (17U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK (0x40000U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT (18U) +#define XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0 - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0_SET - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_SET_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_SET_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_SET_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_SET_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0_CLR - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_CLR_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_CLR_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_CLR_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG0_TOG - XTAL OSC Configuration 0 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG0_TOG_START_MASK (0x1U) +#define XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG0_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_START_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_START_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK (0x2U) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT (1U) +#define XTALOSC24M_OSC_CONFIG0_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_ENABLE_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK (0x4U) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT (2U) +#define XTALOSC24M_OSC_CONFIG0_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_BYPASS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK (0x8U) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT (3U) +#define XTALOSC24M_OSC_CONFIG0_TOG_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_INVERT_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_INVERT_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK (0xFF0U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT (4U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK (0xF000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT (12U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_PLUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK (0xF0000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_HYST_MINUS_MASK) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK (0xFF000000U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT (24U) +#define XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG0_TOG_RC_OSC_PROG_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1 - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1_SET - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_SET_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1_CLR - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_CLR_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG1_TOG - XTAL OSC Configuration 1 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK (0xFFF00000U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT (20U) +#define XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_SHIFT)) & XTALOSC24M_OSC_CONFIG1_TOG_COUNT_RC_CUR_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2 - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLK_1M_ERR_FL_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2_SET - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_SET_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_SET_CLK_1M_ERR_FL_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2_CLR - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_CLR_CLK_1M_ERR_FL_MASK) +/*! @} */ + +/*! @name OSC_CONFIG2_TOG - XTAL OSC Configuration 2 Register */ +/*! @{ */ +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK (0xFFFU) +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT (0U) +#define XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_COUNT_1M_TRG_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK (0x10000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT (16U) +#define XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_ENABLE_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK (0x20000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT (17U) +#define XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_MUX_1M_MASK) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK (0x80000000U) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT (31U) +#define XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL(x) (((uint32_t)(((uint32_t)(x)) << XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_SHIFT)) & XTALOSC24M_OSC_CONFIG2_TOG_CLK_1M_ERR_FL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group XTALOSC24M_Register_Masks */ + + +/* XTALOSC24M - Peripheral instance base addresses */ +/** Peripheral XTALOSC24M base address */ +#define XTALOSC24M_BASE (0x400D8000u) +/** Peripheral XTALOSC24M base pointer */ +#define XTALOSC24M ((XTALOSC24M_Type *)XTALOSC24M_BASE) +/** Array initializer of XTALOSC24M peripheral base addresses */ +#define XTALOSC24M_BASE_ADDRS { XTALOSC24M_BASE } +/** Array initializer of XTALOSC24M peripheral base pointers */ +#define XTALOSC24M_BASE_PTRS { XTALOSC24M } + +/*! + * @} + */ /* end of group XTALOSC24M_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__CWCC__) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _MIMXRT1061_H_ */ + diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/MIMXRT1061.xml b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/MIMXRT1061.xml new file mode 100644 index 0000000000..6ab4e8f15d --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/MIMXRT1061.xml @@ -0,0 +1,248250 @@ + + + nxp.com + MIMXRT1061 + 1.0 + MIMXRT1061DVL6A + +Copyright 2016-2019 NXP +All rights reserved. + +SPDX-License-Identifier: BSD-3-Clause + + + CM7 + r0p1 + little + true + true + true + 4 + false + + 8 + 32 + + + AIPSTZ1 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ1_ + AIPSTZ + 0x4007C000 + + 0 + 0x54 + registers + + + + MPR + Master Priviledge Registers + 0 + 32 + read-write + 0x77000000 + 0xFFFFFFFF + + + MPROT5 + Master 5 Priviledge, Buffer, Read, Write Control. + 8 + 4 + read-write + + + MPL0 + Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + #xxx0 + + + MPL1 + Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + #xxx1 + + + + + MPROT3 + Master 3 Priviledge, Buffer, Read, Write Control. + 16 + 4 + read-write + + + MPL0 + Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + #xxx0 + + + MPL1 + Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + #xxx1 + + + + + MPROT2 + Master 2 Priviledge, Buffer, Read, Write Control + 20 + 4 + read-write + + + MPL0 + Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + #xxx0 + + + MPL1 + Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + #xxx1 + + + + + MPROT1 + Master 1 Priviledge, Buffer, Read, Write Control + 24 + 4 + read-write + + + MPL0 + Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + #xxx0 + + + MPL1 + Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + #xxx1 + + + + + MPROT0 + Master 0 Priviledge, Buffer, Read, Write Control + 28 + 4 + read-write + + + MPL0 + Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. + #xxx0 + + + MPL1 + Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. + #xxx1 + + + + + + + OPACR + Off-Platform Peripheral Access Control Registers + 0x40 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC7 + Off-platform Peripheral Access Control 7 + 0 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC6 + Off-platform Peripheral Access Control 6 + 4 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC5 + Off-platform Peripheral Access Control 5 + 8 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC4 + Off-platform Peripheral Access Control 4 + 12 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC3 + Off-platform Peripheral Access Control 3 + 16 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC2 + Off-platform Peripheral Access Control 2 + 20 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC1 + Off-platform Peripheral Access Control 1 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC0 + Off-platform Peripheral Access Control 0 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + OPACR1 + Off-Platform Peripheral Access Control Registers + 0x44 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC15 + Off-platform Peripheral Access Control 15 + 0 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC14 + Off-platform Peripheral Access Control 14 + 4 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC13 + Off-platform Peripheral Access Control 13 + 8 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC12 + Off-platform Peripheral Access Control 12 + 12 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC11 + Off-platform Peripheral Access Control 11 + 16 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC10 + Off-platform Peripheral Access Control 10 + 20 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC9 + Off-platform Peripheral Access Control 9 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC8 + Off-platform Peripheral Access Control 8 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + OPACR2 + Off-Platform Peripheral Access Control Registers + 0x48 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC23 + Off-platform Peripheral Access Control 23 + 0 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC22 + Off-platform Peripheral Access Control 22 + 4 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC21 + Off-platform Peripheral Access Control 21 + 8 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC20 + Off-platform Peripheral Access Control 20 + 12 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC19 + Off-platform Peripheral Access Control 19 + 16 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC18 + Off-platform Peripheral Access Control 18 + 20 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC17 + Off-platform Peripheral Access Control 17 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC16 + Off-platform Peripheral Access Control 16 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + OPACR3 + Off-Platform Peripheral Access Control Registers + 0x4C + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC31 + Off-platform Peripheral Access Control 31 + 0 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC30 + Off-platform Peripheral Access Control 30 + 4 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC29 + Off-platform Peripheral Access Control 29 + 8 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC28 + Off-platform Peripheral Access Control 28 + 12 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC27 + Off-platform Peripheral Access Control 27 + 16 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC26 + Off-platform Peripheral Access Control 26 + 20 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC25 + Off-platform Peripheral Access Control 25 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC24 + Off-platform Peripheral Access Control 24 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + OPACR4 + Off-Platform Peripheral Access Control Registers + 0x50 + 32 + read-write + 0x44444444 + 0xFFFFFFFF + + + OPAC33 + Off-platform Peripheral Access Control 33 + 24 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + OPAC32 + Off-platform Peripheral Access Control 32 + 28 + 4 + read-write + + + TP0 + Accesses from an untrusted master are allowed. + #xxx0 + + + TP1 + Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access is terminated with an error response and no peripheral access is initiated on the IPS bus. + #xxx1 + + + + + + + + + AIPSTZ2 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ2_ + 0x4017C000 + + 0 + 0x54 + registers + + + + AIPSTZ3 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ3_ + 0x4027C000 + + 0 + 0x54 + registers + + + + AIPSTZ4 + AIPSTZ Control Registers + AIPSTZ + AIPSTZ4_ + 0x4037C000 + + 0 + 0x54 + registers + + + + DCDC + DCDC + DCDC + 0x40080000 + + 0 + 0x10 + registers + + + DCDC + 69 + + + + REG0 + DCDC Register 0 + 0 + 32 + read-write + 0x14030111 + 0xFFFFFFFF + + + PWD_ZCD + power down the zero cross detection function for discontinuous conductor mode + 0 + 1 + read-write + + + DISABLE_AUTO_CLK_SWITCH + Disable automatic clock switch from internal osc to xtal clock. + 1 + 1 + read-write + + + SEL_CLK + select 24 MHz Crystal clock for DCDC, when dcdc_disable_auto_clk_switch is set. + 2 + 1 + read-write + + + PWD_OSC_INT + Power down internal osc. Only set this bit, when 24 MHz crystal osc is available + 3 + 1 + read-write + + + PWD_CUR_SNS_CMP + The power down signal of the current detector. + 4 + 1 + read-write + + + CUR_SNS_THRSH + Set the threshold of current detector, if the peak current of the inductor exceeds the threshold, the current detector will assert + 5 + 3 + read-write + + + PWD_OVERCUR_DET + power down overcurrent detection comparator + 8 + 1 + read-write + + + OVERCUR_TRIG_ADJ + The threshold of over current detection in run mode and power save mode: run mode power save mode 0x0 1 A 0 + 9 + 2 + read-write + + + PWD_CMP_BATT_DET + set to "1" to power down the low voltage detection comparator + 11 + 1 + read-write + + + ADJ_POSLIMIT_BUCK + adjust value to poslimit_buck register + 12 + 4 + read-write + + + EN_LP_OVERLOAD_SNS + enable the overload detection in power save mode, if current is larger than the overloading threshold (typical value is 50 mA), DCDC will switch to the run mode automatically + 16 + 1 + read-write + + + PWD_HIGH_VOLT_DET + power down overvoltage detection comparator + 17 + 1 + read-write + + + LP_OVERLOAD_THRSH + the threshold of the counting number of charging times during the period that lp_overload_freq_sel sets in power save mode + 18 + 2 + read-write + + + LP_OVERLOAD_FREQ_SEL + the period of counting the charging times in power save mode 0: eight 32k cycle 1: sixteen 32k cycle + 20 + 1 + read-write + + + LP_HIGH_HYS + Adjust hysteretic value in low power from 12.5mV to 25mV + 21 + 1 + read-write + + + PWD_CMP_OFFSET + power down output range comparator + 26 + 1 + read-write + + + XTALOK_DISABLE + 1'b1: Disable xtalok detection circuit 1'b0: Enable xtalok detection circuit + 27 + 1 + read-write + + + CURRENT_ALERT_RESET + reset current alert signal + 28 + 1 + read-write + + + XTAL_24M_OK + set to 1 to switch internal ring osc to xtal 24M + 29 + 1 + read-write + + + STS_DC_OK + Status register to indicate DCDC status. 1'b1: DCDC already settled 1'b0: DCDC is settling + 31 + 1 + read-only + + + + + REG1 + DCDC Register 1 + 0x4 + 32 + read-write + 0x111BA29C + 0xFFFFFFFF + + + REG_FBK_SEL + select the feedback point of the internal regulator + 7 + 2 + read-write + + + REG_RLOAD_SW + control the load resistor of the internal regulator of DCDC, the load resistor is connected as default "1", and need set to "0" to disconnect the load resistor + 9 + 1 + read-write + + + LP_CMP_ISRC_SEL + set the current bias of low power comparator 0x0: 50 nA 0x1: 100 nA 0x2: 200 nA 0x3: 400 nA + 12 + 2 + read-write + + + LOOPCTRL_HST_THRESH + increase the threshold detection for common mode analog comparator + 21 + 1 + read-write + + + LOOPCTRL_EN_HYST + Enable hysteresis in switching converter common mode analog comparators + 23 + 1 + read-write + + + VBG_TRIM + trim bandgap voltage + 24 + 5 + read-write + + + + + REG2 + DCDC Register 2 + 0x8 + 32 + read-write + 0x4009 + 0xFFFFFFFF + + + LOOPCTRL_DC_C + Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter, and can be used to optimize efficiency and loop response + 0 + 2 + read-write + + + LOOPCTRL_DC_R + Magnitude of proportional control parameter in the switching DC-DC converter control loop. + 2 + 4 + read-write + + + LOOPCTRL_DC_FF + Two's complement feed forward step in duty cycle in the switching DC-DC converter + 6 + 3 + read-write + + + LOOPCTRL_EN_RCSCALE + Enable analog circuit of DC-DC converter to respond faster under transient load conditions. + 9 + 3 + read-write + + + LOOPCTRL_RCSCALE_THRSH + Increase the threshold detection for RC scale circuit. + 12 + 1 + read-write + + + LOOPCTRL_HYST_SIGN + Invert the sign of the hysteresis in DC-DC analog comparators. + 13 + 1 + read-write + + + DISABLE_PULSE_SKIP + Set to "0" : stop charging if the duty cycle is lower than what set by dcdc_neglimit_in + 27 + 1 + read-write + + + DCM_SET_CTRL + Set high to improve the transition from heavy load to light load + 28 + 1 + read-write + + + + + REG3 + DCDC Register 3 + 0xC + 32 + read-write + 0x10E + 0xFFFFFFFF + + + TRG + Target value of VDD_SOC, 25 mV each step 0x0: 0.8V 0xE: 1.15V 0x1F:1.575V + 0 + 5 + read-write + + + TARGET_LP + Target value of standby (low power) mode 0x0: 0 + 8 + 3 + read-write + + + MINPWR_DC_HALFCLK + Set DCDC clock to half freqeuncy for continuous mode + 24 + 1 + read-write + + + MISC_DELAY_TIMING + Ajust delay to reduce ground noise + 27 + 1 + read-write + + + MISC_DISABLEFET_LOGIC + Reserved + 28 + 1 + read-write + + + DISABLE_STEP + Disable stepping for the output VDD_SOC of DCDC + 30 + 1 + read-write + + + + + + + PIT + PIT + PIT + 0x40084000 + + 0 + 0x140 + registers + + + PIT + 122 + + + + MCR + PIT Module Control Register + 0 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + FRZ + Freeze + 0 + 1 + read-write + + + FRZ_0 + Timers continue to run in Debug mode. + 0 + + + FRZ_1 + Timers are stopped in Debug mode. + 0x1 + + + + + MDIS + Module Disable - (PIT section) + 1 + 1 + read-write + + + MDIS_0 + Clock for standard PIT timers is enabled. + 0 + + + MDIS_1 + Clock for standard PIT timers is disabled. + 0x1 + + + + + + + LTMR64H + PIT Upper Lifetime Timer Register + 0xE0 + 32 + read-only + 0 + 0xFFFFFFFF + + + LTH + Life Timer value + 0 + 32 + read-only + + + + + LTMR64L + PIT Lower Lifetime Timer Register + 0xE4 + 32 + read-only + 0 + 0xFFFFFFFF + + + LTL + Life Timer value + 0 + 32 + read-only + + + + + 4 + 0x10 + TIMER[%s] + no description available + 0x100 + + LDVAL + Timer Load Value Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSV + Timer Start Value + 0 + 32 + read-write + + + + + CVAL + Current Timer Value Register + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + TVL + Current Timer Value + 0 + 32 + read-only + + + + + TCTRL + Timer Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEN + Timer Enable + 0 + 1 + read-write + + + TEN_0 + Timer n is disabled. + 0 + + + TEN_1 + Timer n is enabled. + 0x1 + + + + + TIE + Timer Interrupt Enable + 1 + 1 + read-write + + + TIE_0 + Interrupt requests from Timer n are disabled. + 0 + + + TIE_1 + Interrupt will be requested whenever TIF is set. + 0x1 + + + + + CHN + Chain Mode + 2 + 1 + read-write + + + CHN_0 + Timer is not chained. + 0 + + + CHN_1 + Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. + 0x1 + + + + + + + TFLG + Timer Flag Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TIF + Timer Interrupt Flag + 0 + 1 + read-write + oneToClear + + + TIF_0 + Timeout has not yet occurred. + 0 + + + TIF_1 + Timeout has occurred. + 0x1 + + + + + + + + + + CMP1 + High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) + ACMP + CMP1_ + ACMP + 0x40094000 + + 0 + 0x6 + registers + + + ACMP1 + 123 + + + + CR0 + CMP Control Register 0 + 0 + 8 + read-write + 0 + 0xFF + + + HYSTCTR + Comparator hard block hysteresis control + 0 + 2 + read-write + + + HYSTCTR_0 + Level 0 + 0 + + + HYSTCTR_1 + Level 1 + 0x1 + + + HYSTCTR_2 + Level 2 + 0x2 + + + HYSTCTR_3 + Level 3 + 0x3 + + + + + FILTER_CNT + Filter Sample Count + 4 + 3 + read-write + + + FILTER_CNT_0 + Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. + 0 + + + FILTER_CNT_1 + One sample must agree. The comparator output is simply sampled. + 0x1 + + + FILTER_CNT_2 + 2 consecutive samples must agree. + 0x2 + + + FILTER_CNT_3 + 3 consecutive samples must agree. + 0x3 + + + FILTER_CNT_4 + 4 consecutive samples must agree. + 0x4 + + + FILTER_CNT_5 + 5 consecutive samples must agree. + 0x5 + + + FILTER_CNT_6 + 6 consecutive samples must agree. + 0x6 + + + FILTER_CNT_7 + 7 consecutive samples must agree. + 0x7 + + + + + + + CR1 + CMP Control Register 1 + 0x1 + 8 + read-write + 0 + 0xFF + + + EN + Comparator Module Enable + 0 + 1 + read-write + + + EN_0 + Analog Comparator is disabled. + 0 + + + EN_1 + Analog Comparator is enabled. + 0x1 + + + + + OPE + Comparator Output Pin Enable + 1 + 1 + read-write + + + OPE_0 + CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect. + 0 + + + OPE_1 + CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. + 0x1 + + + + + COS + Comparator Output Select + 2 + 1 + read-write + + + COS_0 + Set the filtered comparator output (CMPO) to equal COUT. + 0 + + + COS_1 + Set the unfiltered comparator output (CMPO) to equal COUTA. + 0x1 + + + + + INV + Comparator INVERT + 3 + 1 + read-write + + + INV_0 + Does not invert the comparator output. + 0 + + + INV_1 + Inverts the comparator output. + 0x1 + + + + + PMODE + Power Mode Select + 4 + 1 + read-write + + + PMODE_0 + Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. + 0 + + + PMODE_1 + High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. + 0x1 + + + + + WE + Windowing Enable + 6 + 1 + read-write + + + WE_0 + Windowing mode is not selected. + 0 + + + WE_1 + Windowing mode is selected. + 0x1 + + + + + SE + Sample Enable + 7 + 1 + read-write + + + SE_0 + Sampling mode is not selected. + 0 + + + SE_1 + Sampling mode is selected. + 0x1 + + + + + + + FPR + CMP Filter Period Register + 0x2 + 8 + read-write + 0 + 0xFF + + + FILT_PER + Filter Sample Period + 0 + 8 + read-write + + + + + SCR + CMP Status and Control Register + 0x3 + 8 + read-write + 0 + 0xFF + + + COUT + Analog Comparator Output + 0 + 1 + read-only + + + CFF + Analog Comparator Flag Falling + 1 + 1 + read-write + oneToClear + + + CFF_0 + Falling-edge on COUT has not been detected. + 0 + + + CFF_1 + Falling-edge on COUT has occurred. + 0x1 + + + + + CFR + Analog Comparator Flag Rising + 2 + 1 + read-write + oneToClear + + + CFR_0 + Rising-edge on COUT has not been detected. + 0 + + + CFR_1 + Rising-edge on COUT has occurred. + 0x1 + + + + + IEF + Comparator Interrupt Enable Falling + 3 + 1 + read-write + + + IEF_0 + Interrupt is disabled. + 0 + + + IEF_1 + Interrupt is enabled. + 0x1 + + + + + IER + Comparator Interrupt Enable Rising + 4 + 1 + read-write + + + IER_0 + Interrupt is disabled. + 0 + + + IER_1 + Interrupt is enabled. + 0x1 + + + + + DMAEN + DMA Enable Control + 6 + 1 + read-write + + + DMAEN_0 + DMA is disabled. + 0 + + + DMAEN_1 + DMA is enabled. + 0x1 + + + + + + + DACCR + DAC Control Register + 0x4 + 8 + read-write + 0 + 0xFF + + + VOSEL + DAC Output Voltage Select + 0 + 6 + read-write + + + VRSEL + Supply Voltage Reference Source Select + 6 + 1 + read-write + + + VRSEL_0 + Vin1 is selected as resistor ladder network supply reference. + 0 + + + VRSEL_1 + Vin2 is selected as resistor ladder network supply reference. + 0x1 + + + + + DACEN + DAC Enable + 7 + 1 + read-write + + + DACEN_0 + DAC is disabled. + 0 + + + DACEN_1 + DAC is enabled. + 0x1 + + + + + + + MUXCR + MUX Control Register + 0x5 + 8 + read-write + 0 + 0xFF + + + MSEL + Minus Input Mux Control + 0 + 3 + read-write + + + MSEL_0 + IN0 + 0 + + + MSEL_1 + IN1 + 0x1 + + + MSEL_2 + IN2 + 0x2 + + + MSEL_3 + IN3 + 0x3 + + + MSEL_4 + IN4 + 0x4 + + + MSEL_5 + IN5 + 0x5 + + + MSEL_6 + IN6 + 0x6 + + + MSEL_7 + IN7 + 0x7 + + + + + PSEL + Plus Input Mux Control + 3 + 3 + read-write + + + PSEL_0 + IN0 + 0 + + + PSEL_1 + IN1 + 0x1 + + + PSEL_2 + IN2 + 0x2 + + + PSEL_3 + IN3 + 0x3 + + + PSEL_4 + IN4 + 0x4 + + + PSEL_5 + IN5 + 0x5 + + + PSEL_6 + IN6 + 0x6 + + + PSEL_7 + IN7 + 0x7 + + + + + + + + + CMP2 + High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) + ACMP + CMP2_ + 0x40094008 + + 0 + 0x6 + registers + + + ACMP2 + 124 + + + + CMP3 + High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) + ACMP + CMP3_ + 0x40094010 + + 0 + 0x6 + registers + + + ACMP3 + 125 + + + + CMP4 + High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) + ACMP + CMP4_ + 0x40094018 + + 0 + 0x6 + registers + + + ACMP4 + 126 + + + + IOMUXC_SNVS_GPR + IOMUXC + IOMUXC_SNVS_GPR + IOMUXC_SNVS_GPR_ + 0x400A4000 + + 0 + 0x10 + registers + + + + GPR0 + GPR0 General Purpose Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR1 + GPR1 General Purpose Register + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR2 + GPR2 General Purpose Register + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR3 + GPR3 General Purpose Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + LPSR_MODE_ENABLE + Set to enable LPSR mode. + 0 + 1 + read-write + + + DCDC_STATUS_CAPT_CLR + DCDC captured status clear + 1 + 1 + read-write + + + POR_PULL_TYPE + POR_B pad control + 2 + 2 + read-write + + + DCDC_IN_LOW_VOL + DCDC_IN low voltage detect. + 16 + 1 + read-only + + + DCDC_OVER_CUR + DCDC output over current alert + 17 + 1 + read-only + + + DCDC_OVER_VOL + DCDC output over voltage alert + 18 + 1 + read-only + + + DCDC_STS_DC_OK + DCDC status OK + 19 + 1 + read-only + + + + + + + IOMUXC_SNVS + IOMUXC_SNVS + IOMUXC_SNVS + IOMUXC_SNVS_ + 0x400A8000 + + 0 + 0x24 + registers + + + + SW_MUX_CTL_PAD_WAKEUP + SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register + 0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5 + 0x5 + + + ALT7 + Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad WAKEUP + 0x1 + + + + + + + SW_MUX_CTL_PAD_PMIC_ON_REQ + SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp + 0 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad PMIC_ON_REQ + 0x1 + + + + + + + SW_MUX_CTL_PAD_PMIC_STBY_REQ + SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: ccm + 0 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO5_IO02 of instance: gpio5 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad PMIC_STBY_REQ + 0x1 + + + + + + + SW_PAD_CTL_PAD_TEST_MODE + SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register + 0xC + 32 + read-write + 0x30A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_POR_B + SW_PAD_CTL_PAD_POR_B SW PAD Control Register + 0x10 + 32 + read-write + 0x1B0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_ONOFF + SW_PAD_CTL_PAD_ONOFF SW PAD Control Register + 0x14 + 32 + read-write + 0x1B0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_WAKEUP + SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register + 0x18 + 32 + read-write + 0x1B0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_PMIC_ON_REQ + SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register + 0x1C + 32 + read-write + 0xB8A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_PMIC_STBY_REQ + SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register + 0x20 + 32 + read-write + 0xA0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_260_Ohm___3_3V__150_Ohm_1_8V__240_Ohm_for_DDR_ + R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-only + + + SPEED + medium(100MHz) + 0x2 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + + + IOMUXC_GPR + IOMUXC_GPR + IOMUXC_GPR + IOMUXC_GPR_ + 0x400AC000 + + 0 + 0x8C + registers + + + + GPR0 + GPR0 General Purpose Register + 0 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR1 + GPR1 General Purpose Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SAI1_MCLK1_SEL + SAI1 MCLK1 source select + 0 + 3 + read-write + + + SAI1_MCLK1_SEL_0 + ccm.ssi1_clk_root + 0 + + + SAI1_MCLK1_SEL_1 + ccm.ssi2_clk_root + 0x1 + + + SAI1_MCLK1_SEL_2 + ccm.ssi3_clk_root + 0x2 + + + SAI1_MCLK1_SEL_3 + iomux.sai1_ipg_clk_sai_mclk + 0x3 + + + SAI1_MCLK1_SEL_4 + iomux.sai2_ipg_clk_sai_mclk + 0x4 + + + SAI1_MCLK1_SEL_5 + iomux.sai3_ipg_clk_sai_mclk + 0x5 + + + + + SAI1_MCLK2_SEL + SAI1 MCLK2 source select + 3 + 3 + read-write + + + SAI1_MCLK2_SEL_0 + ccm.ssi1_clk_root + 0 + + + SAI1_MCLK2_SEL_1 + ccm.ssi2_clk_root + 0x1 + + + SAI1_MCLK2_SEL_2 + ccm.ssi3_clk_root + 0x2 + + + SAI1_MCLK2_SEL_3 + iomux.sai1_ipg_clk_sai_mclk + 0x3 + + + SAI1_MCLK2_SEL_4 + iomux.sai2_ipg_clk_sai_mclk + 0x4 + + + SAI1_MCLK2_SEL_5 + iomux.sai3_ipg_clk_sai_mclk + 0x5 + + + + + SAI1_MCLK3_SEL + SAI1 MCLK3 source select + 6 + 2 + read-write + + + SAI1_MCLK3_SEL_0 + ccm.spdif0_clk_root + 0 + + + SAI1_MCLK3_SEL_1 + iomux.spdif_tx_clk2 + 0x1 + + + SAI1_MCLK3_SEL_2 + spdif.spdif_srclk + 0x2 + + + SAI1_MCLK3_SEL_3 + spdif.spdif_outclock + 0x3 + + + + + SAI2_MCLK3_SEL + SAI2 MCLK3 source select + 8 + 2 + read-write + + + SAI2_MCLK3_SEL_0 + ccm.spdif0_clk_root + 0 + + + SAI2_MCLK3_SEL_1 + iomux.spdif_tx_clk2 + 0x1 + + + SAI2_MCLK3_SEL_2 + spdif.spdif_srclk + 0x2 + + + SAI2_MCLK3_SEL_3 + spdif.spdif_outclock + 0x3 + + + + + SAI3_MCLK3_SEL + SAI3 MCLK3 source select + 10 + 2 + read-write + + + SAI3_MCLK3_SEL_0 + ccm.spdif0_clk_root + 0 + + + SAI3_MCLK3_SEL_1 + iomux.spdif_tx_clk2 + 0x1 + + + SAI3_MCLK3_SEL_2 + spdif.spdif_srclk + 0x2 + + + SAI3_MCLK3_SEL_3 + spdif.spdif_outclock + 0x3 + + + + + GINT + Global interrupt "0" bit (connected to ARM M7 IRQ#0 and GPC) + 12 + 1 + read-write + + + GINT_0 + Global interrupt request is not asserted. + 0 + + + GINT_1 + Global interrupt request is asserted. + 0x1 + + + + + ENET1_CLK_SEL + ENET1 reference clock mode select. + 13 + 1 + read-write + + + ENET1_CLK_SEL_0 + ENET1 TX reference clock driven by ref_enetpll. This clock is also output to pins via the IOMUX. ENET_REF_CLK1 function. + 0 + + + ENET1_CLK_SEL_1 + Gets ENET1 TX reference clock from the ENET1_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller. + 0x1 + + + + + ENET2_CLK_SEL + ENET2 reference clock mode select. + 14 + 1 + read-write + + + ENET2_CLK_SEL_0 + ENET2 TX reference clock driven by ref_enetpll. This clock is also output to pins via the IOMUX. ENET2_REF_CLK function. + 0 + + + ENET2_CLK_SEL_1 + Gets ENET2 TX reference clock from the ENET2_TX_CLK pin. In this use case, an external OSC provides the clock for both the external PHY and the internal controller. + 0x1 + + + + + USB_EXP_MODE + USB Exposure mode + 15 + 1 + read-write + + + USB_EXP_MODE_0 + Exposure mode is disabled. + 0 + + + USB_EXP_MODE_1 + Exposure mode is enabled. + 0x1 + + + + + ENET1_TX_CLK_DIR + ENET1_TX_CLK data direction control + 17 + 1 + read-write + + + ENET1_TX_CLK_DIR_0 + ENET1_TX_CLK output driver is disabled + 0 + + + ENET1_TX_CLK_DIR_1 + ENET1_TX_CLK output driver is enabled + 0x1 + + + + + ENET2_TX_CLK_DIR + ENET2_TX_CLK data direction control + 18 + 1 + read-write + + + ENET2_TX_CLK_DIR_0 + ENET2_TX_CLK output driver is disabled + 0 + + + ENET2_TX_CLK_DIR_1 + ENET2_TX_CLK output driver is enabled + 0x1 + + + + + SAI1_MCLK_DIR + sai1.MCLK signal direction control + 19 + 1 + read-write + + + SAI1_MCLK_DIR_0 + sai1.MCLK is input signal + 0 + + + SAI1_MCLK_DIR_1 + sai1.MCLK is output signal + 0x1 + + + + + SAI2_MCLK_DIR + sai2.MCLK signal direction control + 20 + 1 + read-write + + + SAI2_MCLK_DIR_0 + sai2.MCLK is input signal + 0 + + + SAI2_MCLK_DIR_1 + sai2.MCLK is output signal + 0x1 + + + + + SAI3_MCLK_DIR + sai3.MCLK signal direction control + 21 + 1 + read-write + + + SAI3_MCLK_DIR_0 + sai3.MCLK is input signal + 0 + + + SAI3_MCLK_DIR_1 + sai3.MCLK is output signal + 0x1 + + + + + EXC_MON + Exclusive monitor response select of illegal command + 22 + 1 + read-write + + + EXC_MON_0 + OKAY response + 0 + + + EXC_MON_1 + SLVError response (default) + 0x1 + + + + + ENET_IPG_CLK_S_EN + ENET and ENET2 ipg_clk_s clock gating enable + 23 + 1 + read-write + + + ENET_IPG_CLK_S_EN_0 + ipg_clk_s is gated when there is no IPS access + 0 + + + ENET_IPG_CLK_S_EN_1 + ipg_clk_s is always on + 0x1 + + + + + CM7_FORCE_HCLK_EN + ARM CM7 platform AHB clock enable + 31 + 1 + read-write + + + CM7_FORCE_HCLK_EN_0 + AHB clock is not running (gated) + 0 + + + CM7_FORCE_HCLK_EN_1 + AHB clock is running (enabled) + 0x1 + + + + + + + GPR2 + GPR2 General Purpose Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + AXBS_L_AHBXL_HIGH_PRIORITY + AXBS_L AHBXL master has higher priority.Do not set both DMA and AHBXL to high priority. + 0 + 1 + read-write + + + AXBS_L_AHBXL_HIGH_PRIORITY_0 + AXBS_L AHBXL master does not have high priority + 0 + + + AXBS_L_AHBXL_HIGH_PRIORITY_1 + AXBS_P AHBXL master has high priority + 0x1 + + + + + AXBS_L_DMA_HIGH_PRIORITY + AXBS_L DMA master has higher priority.Do not set both DMA and AHBXL to high priority. + 1 + 1 + read-write + + + AXBS_L_DMA_HIGH_PRIORITY_0 + AXBS_L DMA master does not have high priority + 0 + + + AXBS_L_DMA_HIGH_PRIORITY_1 + AXBS_L DMA master has high priority + 0x1 + + + + + AXBS_L_FORCE_ROUND_ROBIN + Force Round Robin in AXBS_L + 2 + 1 + read-write + + + AXBS_L_FORCE_ROUND_ROBIN_0 + AXBS_L masters are not arbitored in round robin, depending on DMA and AHBXL master priority settings. + 0 + + + AXBS_L_FORCE_ROUND_ROBIN_1 + AXBS_L masters are arbitored in round robin + 0x1 + + + + + AXBS_P_M0_HIGH_PRIORITY + AXBS_P M0 master has higher priority.Do not set both M1 and M0 to high priority. + 3 + 1 + read-write + + + AXBS_P_M0_HIGH_PRIORITY_0 + AXBS_P M0 master doesn't have high priority + 0 + + + AXBS_P_M0_HIGH_PRIORITY_1 + AXBS_P M0 master has high priority + 0x1 + + + + + AXBS_P_M1_HIGH_PRIORITY + AXBS_P M1 master has higher priority.Do not set both M1 and M0 to high priority. + 4 + 1 + read-write + + + AXBS_P_M1_HIGH_PRIORITY_0 + AXBS_P M1 master does not have high priority + 0 + + + AXBS_P_M1_HIGH_PRIORITY_1 + AXBS_P M1 master has high priority + 0x1 + + + + + AXBS_P_FORCE_ROUND_ROBIN + Force Round Robin in AXBS_P. This bit can override master M0 M1 high priority configuration. + 5 + 1 + read-write + + + AXBS_P_FORCE_ROUND_ROBIN_0 + AXBS_P masters are not arbitored in round robin, depending on M0/M1 master priority settings. + 0 + + + AXBS_P_FORCE_ROUND_ROBIN_1 + AXBS_P masters are arbitored in round robin + 0x1 + + + + + CANFD_FILTER_BYPASS + Disable CANFD filter + 6 + 1 + read-write + + + CANFD_FILTER_BYPASS_0 + enable CANFD filter + 0 + + + CANFD_FILTER_BYPASS_1 + disable CANFD filter + 0x1 + + + + + L2_MEM_EN_POWERSAVING + enable power saving features on L2 memory + 12 + 1 + read-write + + + L2_MEM_EN_POWERSAVING_0 + none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect + 0 + + + L2_MEM_EN_POWERSAVING_1 + memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP (priority high to low) to enable power saving levels + 0x1 + + + + + RAM_AUTO_CLK_GATING_EN + Automatically gate off RAM clock when RAM is not accessed. + 13 + 1 + read-write + + + RAM_AUTO_CLK_GATING_EN_0 + disable automatically gate off RAM clock + 0 + + + RAM_AUTO_CLK_GATING_EN_1 + enable automatically gate off RAM clock + 0x1 + + + + + L2_MEM_DEEPSLEEP + control how memory enter Deep Sleep mode (shutdown periphery power, but maintain memory contents, outputs of memory are pulled low) + 14 + 1 + read-write + + + L2_MEM_DEEPSLEEP_0 + no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode + 0 + + + L2_MEM_DEEPSLEEP_1 + force memory into deep sleep mode + 0x1 + + + + + MQS_CLK_DIV + Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency. + 16 + 8 + read-write + + + DIVIDE_1 + mclk frequency = 1/1 * hmclk frequency + 0 + + + DIVIDE_2 + mclk frequency = 1/2 * hmclk frequency + 0x1 + + + DIVIDE_3 + mclk frequency = 1/3 * hmclk frequency + 0x2 + + + DIVIDE_4 + mclk frequency = 1/4 * hmclk frequency + 0x3 + + + DIVIDE_5 + mclk frequency = 1/5 * hmclk frequency + 0x4 + + + DIVIDE_6 + mclk frequency = 1/6 * hmclk frequency + 0x5 + + + DIVIDE_7 + mclk frequency = 1/7 * hmclk frequency + 0x6 + + + DIVIDE_8 + mclk frequency = 1/8 * hmclk frequency + 0x7 + + + DIVIDE_9 + mclk frequency = 1/9 * hmclk frequency + 0x8 + + + DIVIDE_10 + mclk frequency = 1/10 * hmclk frequency + 0x9 + + + DIVIDE_11 + mclk frequency = 1/11 * hmclk frequency + 0xA + + + DIVIDE_12 + mclk frequency = 1/12 * hmclk frequency + 0xB + + + DIVIDE_13 + mclk frequency = 1/13 * hmclk frequency + 0xC + + + DIVIDE_14 + mclk frequency = 1/14 * hmclk frequency + 0xD + + + DIVIDE_15 + mclk frequency = 1/15 * hmclk frequency + 0xE + + + DIVIDE_16 + mclk frequency = 1/16 * hmclk frequency + 0xF + + + DIVIDE_17 + mclk frequency = 1/17 * hmclk frequency + 0x10 + + + DIVIDE_18 + mclk frequency = 1/18 * hmclk frequency + 0x11 + + + DIVIDE_19 + mclk frequency = 1/19 * hmclk frequency + 0x12 + + + DIVIDE_20 + mclk frequency = 1/20 * hmclk frequency + 0x13 + + + DIVIDE_21 + mclk frequency = 1/21 * hmclk frequency + 0x14 + + + DIVIDE_22 + mclk frequency = 1/22 * hmclk frequency + 0x15 + + + DIVIDE_23 + mclk frequency = 1/23 * hmclk frequency + 0x16 + + + DIVIDE_24 + mclk frequency = 1/24 * hmclk frequency + 0x17 + + + DIVIDE_25 + mclk frequency = 1/25 * hmclk frequency + 0x18 + + + DIVIDE_26 + mclk frequency = 1/26 * hmclk frequency + 0x19 + + + DIVIDE_27 + mclk frequency = 1/27 * hmclk frequency + 0x1A + + + DIVIDE_28 + mclk frequency = 1/28 * hmclk frequency + 0x1B + + + DIVIDE_29 + mclk frequency = 1/29 * hmclk frequency + 0x1C + + + DIVIDE_30 + mclk frequency = 1/30 * hmclk frequency + 0x1D + + + DIVIDE_31 + mclk frequency = 1/31 * hmclk frequency + 0x1E + + + DIVIDE_32 + mclk frequency = 1/32 * hmclk frequency + 0x1F + + + DIVIDE_33 + mclk frequency = 1/33 * hmclk frequency + 0x20 + + + DIVIDE_34 + mclk frequency = 1/34 * hmclk frequency + 0x21 + + + DIVIDE_35 + mclk frequency = 1/35 * hmclk frequency + 0x22 + + + DIVIDE_36 + mclk frequency = 1/36 * hmclk frequency + 0x23 + + + DIVIDE_37 + mclk frequency = 1/37 * hmclk frequency + 0x24 + + + DIVIDE_38 + mclk frequency = 1/38 * hmclk frequency + 0x25 + + + DIVIDE_39 + mclk frequency = 1/39 * hmclk frequency + 0x26 + + + DIVIDE_40 + mclk frequency = 1/40 * hmclk frequency + 0x27 + + + DIVIDE_41 + mclk frequency = 1/41 * hmclk frequency + 0x28 + + + DIVIDE_42 + mclk frequency = 1/42 * hmclk frequency + 0x29 + + + DIVIDE_43 + mclk frequency = 1/43 * hmclk frequency + 0x2A + + + DIVIDE_44 + mclk frequency = 1/44 * hmclk frequency + 0x2B + + + DIVIDE_45 + mclk frequency = 1/45 * hmclk frequency + 0x2C + + + DIVIDE_46 + mclk frequency = 1/46 * hmclk frequency + 0x2D + + + DIVIDE_47 + mclk frequency = 1/47 * hmclk frequency + 0x2E + + + DIVIDE_48 + mclk frequency = 1/48 * hmclk frequency + 0x2F + + + DIVIDE_49 + mclk frequency = 1/49 * hmclk frequency + 0x30 + + + DIVIDE_50 + mclk frequency = 1/50 * hmclk frequency + 0x31 + + + DIVIDE_51 + mclk frequency = 1/51 * hmclk frequency + 0x32 + + + DIVIDE_52 + mclk frequency = 1/52 * hmclk frequency + 0x33 + + + DIVIDE_53 + mclk frequency = 1/53 * hmclk frequency + 0x34 + + + DIVIDE_54 + mclk frequency = 1/54 * hmclk frequency + 0x35 + + + DIVIDE_55 + mclk frequency = 1/55 * hmclk frequency + 0x36 + + + DIVIDE_56 + mclk frequency = 1/56 * hmclk frequency + 0x37 + + + DIVIDE_57 + mclk frequency = 1/57 * hmclk frequency + 0x38 + + + DIVIDE_58 + mclk frequency = 1/58 * hmclk frequency + 0x39 + + + DIVIDE_59 + mclk frequency = 1/59 * hmclk frequency + 0x3A + + + DIVIDE_60 + mclk frequency = 1/60 * hmclk frequency + 0x3B + + + DIVIDE_61 + mclk frequency = 1/61 * hmclk frequency + 0x3C + + + DIVIDE_62 + mclk frequency = 1/62 * hmclk frequency + 0x3D + + + DIVIDE_63 + mclk frequency = 1/63 * hmclk frequency + 0x3E + + + DIVIDE_64 + mclk frequency = 1/64 * hmclk frequency + 0x3F + + + DIVIDE_65 + mclk frequency = 1/65 * hmclk frequency + 0x40 + + + DIVIDE_66 + mclk frequency = 1/66 * hmclk frequency + 0x41 + + + DIVIDE_67 + mclk frequency = 1/67 * hmclk frequency + 0x42 + + + DIVIDE_68 + mclk frequency = 1/68 * hmclk frequency + 0x43 + + + DIVIDE_69 + mclk frequency = 1/69 * hmclk frequency + 0x44 + + + DIVIDE_70 + mclk frequency = 1/70 * hmclk frequency + 0x45 + + + DIVIDE_71 + mclk frequency = 1/71 * hmclk frequency + 0x46 + + + DIVIDE_72 + mclk frequency = 1/72 * hmclk frequency + 0x47 + + + DIVIDE_73 + mclk frequency = 1/73 * hmclk frequency + 0x48 + + + DIVIDE_74 + mclk frequency = 1/74 * hmclk frequency + 0x49 + + + DIVIDE_75 + mclk frequency = 1/75 * hmclk frequency + 0x4A + + + DIVIDE_76 + mclk frequency = 1/76 * hmclk frequency + 0x4B + + + DIVIDE_77 + mclk frequency = 1/77 * hmclk frequency + 0x4C + + + DIVIDE_78 + mclk frequency = 1/78 * hmclk frequency + 0x4D + + + DIVIDE_79 + mclk frequency = 1/79 * hmclk frequency + 0x4E + + + DIVIDE_80 + mclk frequency = 1/80 * hmclk frequency + 0x4F + + + DIVIDE_81 + mclk frequency = 1/81 * hmclk frequency + 0x50 + + + DIVIDE_82 + mclk frequency = 1/82 * hmclk frequency + 0x51 + + + DIVIDE_83 + mclk frequency = 1/83 * hmclk frequency + 0x52 + + + DIVIDE_84 + mclk frequency = 1/84 * hmclk frequency + 0x53 + + + DIVIDE_85 + mclk frequency = 1/85 * hmclk frequency + 0x54 + + + DIVIDE_86 + mclk frequency = 1/86 * hmclk frequency + 0x55 + + + DIVIDE_87 + mclk frequency = 1/87 * hmclk frequency + 0x56 + + + DIVIDE_88 + mclk frequency = 1/88 * hmclk frequency + 0x57 + + + DIVIDE_89 + mclk frequency = 1/89 * hmclk frequency + 0x58 + + + DIVIDE_90 + mclk frequency = 1/90 * hmclk frequency + 0x59 + + + DIVIDE_91 + mclk frequency = 1/91 * hmclk frequency + 0x5A + + + DIVIDE_92 + mclk frequency = 1/92 * hmclk frequency + 0x5B + + + DIVIDE_93 + mclk frequency = 1/93 * hmclk frequency + 0x5C + + + DIVIDE_94 + mclk frequency = 1/94 * hmclk frequency + 0x5D + + + DIVIDE_95 + mclk frequency = 1/95 * hmclk frequency + 0x5E + + + DIVIDE_96 + mclk frequency = 1/96 * hmclk frequency + 0x5F + + + DIVIDE_97 + mclk frequency = 1/97 * hmclk frequency + 0x60 + + + DIVIDE_98 + mclk frequency = 1/98 * hmclk frequency + 0x61 + + + DIVIDE_99 + mclk frequency = 1/99 * hmclk frequency + 0x62 + + + DIVIDE_100 + mclk frequency = 1/100 * hmclk frequency + 0x63 + + + DIVIDE_101 + mclk frequency = 1/101 * hmclk frequency + 0x64 + + + DIVIDE_102 + mclk frequency = 1/102 * hmclk frequency + 0x65 + + + DIVIDE_103 + mclk frequency = 1/103 * hmclk frequency + 0x66 + + + DIVIDE_104 + mclk frequency = 1/104 * hmclk frequency + 0x67 + + + DIVIDE_105 + mclk frequency = 1/105 * hmclk frequency + 0x68 + + + DIVIDE_106 + mclk frequency = 1/106 * hmclk frequency + 0x69 + + + DIVIDE_107 + mclk frequency = 1/107 * hmclk frequency + 0x6A + + + DIVIDE_108 + mclk frequency = 1/108 * hmclk frequency + 0x6B + + + DIVIDE_109 + mclk frequency = 1/109 * hmclk frequency + 0x6C + + + DIVIDE_110 + mclk frequency = 1/110 * hmclk frequency + 0x6D + + + DIVIDE_111 + mclk frequency = 1/111 * hmclk frequency + 0x6E + + + DIVIDE_112 + mclk frequency = 1/112 * hmclk frequency + 0x6F + + + DIVIDE_113 + mclk frequency = 1/113 * hmclk frequency + 0x70 + + + DIVIDE_114 + mclk frequency = 1/114 * hmclk frequency + 0x71 + + + DIVIDE_115 + mclk frequency = 1/115 * hmclk frequency + 0x72 + + + DIVIDE_116 + mclk frequency = 1/116 * hmclk frequency + 0x73 + + + DIVIDE_117 + mclk frequency = 1/117 * hmclk frequency + 0x74 + + + DIVIDE_118 + mclk frequency = 1/118 * hmclk frequency + 0x75 + + + DIVIDE_119 + mclk frequency = 1/119 * hmclk frequency + 0x76 + + + DIVIDE_120 + mclk frequency = 1/120 * hmclk frequency + 0x77 + + + DIVIDE_121 + mclk frequency = 1/121 * hmclk frequency + 0x78 + + + DIVIDE_122 + mclk frequency = 1/122 * hmclk frequency + 0x79 + + + DIVIDE_123 + mclk frequency = 1/123 * hmclk frequency + 0x7A + + + DIVIDE_124 + mclk frequency = 1/124 * hmclk frequency + 0x7B + + + DIVIDE_125 + mclk frequency = 1/125 * hmclk frequency + 0x7C + + + DIVIDE_126 + mclk frequency = 1/126 * hmclk frequency + 0x7D + + + DIVIDE_127 + mclk frequency = 1/127 * hmclk frequency + 0x7E + + + DIVIDE_128 + mclk frequency = 1/128 * hmclk frequency + 0x7F + + + DIVIDE_129 + mclk frequency = 1/129 * hmclk frequency + 0x80 + + + DIVIDE_130 + mclk frequency = 1/130 * hmclk frequency + 0x81 + + + DIVIDE_131 + mclk frequency = 1/131 * hmclk frequency + 0x82 + + + DIVIDE_132 + mclk frequency = 1/132 * hmclk frequency + 0x83 + + + DIVIDE_133 + mclk frequency = 1/133 * hmclk frequency + 0x84 + + + DIVIDE_134 + mclk frequency = 1/134 * hmclk frequency + 0x85 + + + DIVIDE_135 + mclk frequency = 1/135 * hmclk frequency + 0x86 + + + DIVIDE_136 + mclk frequency = 1/136 * hmclk frequency + 0x87 + + + DIVIDE_137 + mclk frequency = 1/137 * hmclk frequency + 0x88 + + + DIVIDE_138 + mclk frequency = 1/138 * hmclk frequency + 0x89 + + + DIVIDE_139 + mclk frequency = 1/139 * hmclk frequency + 0x8A + + + DIVIDE_140 + mclk frequency = 1/140 * hmclk frequency + 0x8B + + + DIVIDE_141 + mclk frequency = 1/141 * hmclk frequency + 0x8C + + + DIVIDE_142 + mclk frequency = 1/142 * hmclk frequency + 0x8D + + + DIVIDE_143 + mclk frequency = 1/143 * hmclk frequency + 0x8E + + + DIVIDE_144 + mclk frequency = 1/144 * hmclk frequency + 0x8F + + + DIVIDE_145 + mclk frequency = 1/145 * hmclk frequency + 0x90 + + + DIVIDE_146 + mclk frequency = 1/146 * hmclk frequency + 0x91 + + + DIVIDE_147 + mclk frequency = 1/147 * hmclk frequency + 0x92 + + + DIVIDE_148 + mclk frequency = 1/148 * hmclk frequency + 0x93 + + + DIVIDE_149 + mclk frequency = 1/149 * hmclk frequency + 0x94 + + + DIVIDE_150 + mclk frequency = 1/150 * hmclk frequency + 0x95 + + + DIVIDE_151 + mclk frequency = 1/151 * hmclk frequency + 0x96 + + + DIVIDE_152 + mclk frequency = 1/152 * hmclk frequency + 0x97 + + + DIVIDE_153 + mclk frequency = 1/153 * hmclk frequency + 0x98 + + + DIVIDE_154 + mclk frequency = 1/154 * hmclk frequency + 0x99 + + + DIVIDE_155 + mclk frequency = 1/155 * hmclk frequency + 0x9A + + + DIVIDE_156 + mclk frequency = 1/156 * hmclk frequency + 0x9B + + + DIVIDE_157 + mclk frequency = 1/157 * hmclk frequency + 0x9C + + + DIVIDE_158 + mclk frequency = 1/158 * hmclk frequency + 0x9D + + + DIVIDE_159 + mclk frequency = 1/159 * hmclk frequency + 0x9E + + + DIVIDE_160 + mclk frequency = 1/160 * hmclk frequency + 0x9F + + + DIVIDE_161 + mclk frequency = 1/161 * hmclk frequency + 0xA0 + + + DIVIDE_162 + mclk frequency = 1/162 * hmclk frequency + 0xA1 + + + DIVIDE_163 + mclk frequency = 1/163 * hmclk frequency + 0xA2 + + + DIVIDE_164 + mclk frequency = 1/164 * hmclk frequency + 0xA3 + + + DIVIDE_165 + mclk frequency = 1/165 * hmclk frequency + 0xA4 + + + DIVIDE_166 + mclk frequency = 1/166 * hmclk frequency + 0xA5 + + + DIVIDE_167 + mclk frequency = 1/167 * hmclk frequency + 0xA6 + + + DIVIDE_168 + mclk frequency = 1/168 * hmclk frequency + 0xA7 + + + DIVIDE_169 + mclk frequency = 1/169 * hmclk frequency + 0xA8 + + + DIVIDE_170 + mclk frequency = 1/170 * hmclk frequency + 0xA9 + + + DIVIDE_171 + mclk frequency = 1/171 * hmclk frequency + 0xAA + + + DIVIDE_172 + mclk frequency = 1/172 * hmclk frequency + 0xAB + + + DIVIDE_173 + mclk frequency = 1/173 * hmclk frequency + 0xAC + + + DIVIDE_174 + mclk frequency = 1/174 * hmclk frequency + 0xAD + + + DIVIDE_175 + mclk frequency = 1/175 * hmclk frequency + 0xAE + + + DIVIDE_176 + mclk frequency = 1/176 * hmclk frequency + 0xAF + + + DIVIDE_177 + mclk frequency = 1/177 * hmclk frequency + 0xB0 + + + DIVIDE_178 + mclk frequency = 1/178 * hmclk frequency + 0xB1 + + + DIVIDE_179 + mclk frequency = 1/179 * hmclk frequency + 0xB2 + + + DIVIDE_180 + mclk frequency = 1/180 * hmclk frequency + 0xB3 + + + DIVIDE_181 + mclk frequency = 1/181 * hmclk frequency + 0xB4 + + + DIVIDE_182 + mclk frequency = 1/182 * hmclk frequency + 0xB5 + + + DIVIDE_183 + mclk frequency = 1/183 * hmclk frequency + 0xB6 + + + DIVIDE_184 + mclk frequency = 1/184 * hmclk frequency + 0xB7 + + + DIVIDE_185 + mclk frequency = 1/185 * hmclk frequency + 0xB8 + + + DIVIDE_186 + mclk frequency = 1/186 * hmclk frequency + 0xB9 + + + DIVIDE_187 + mclk frequency = 1/187 * hmclk frequency + 0xBA + + + DIVIDE_188 + mclk frequency = 1/188 * hmclk frequency + 0xBB + + + DIVIDE_189 + mclk frequency = 1/189 * hmclk frequency + 0xBC + + + DIVIDE_190 + mclk frequency = 1/190 * hmclk frequency + 0xBD + + + DIVIDE_191 + mclk frequency = 1/191 * hmclk frequency + 0xBE + + + DIVIDE_192 + mclk frequency = 1/192 * hmclk frequency + 0xBF + + + DIVIDE_193 + mclk frequency = 1/193 * hmclk frequency + 0xC0 + + + DIVIDE_194 + mclk frequency = 1/194 * hmclk frequency + 0xC1 + + + DIVIDE_195 + mclk frequency = 1/195 * hmclk frequency + 0xC2 + + + DIVIDE_196 + mclk frequency = 1/196 * hmclk frequency + 0xC3 + + + DIVIDE_197 + mclk frequency = 1/197 * hmclk frequency + 0xC4 + + + DIVIDE_198 + mclk frequency = 1/198 * hmclk frequency + 0xC5 + + + DIVIDE_199 + mclk frequency = 1/199 * hmclk frequency + 0xC6 + + + DIVIDE_200 + mclk frequency = 1/200 * hmclk frequency + 0xC7 + + + DIVIDE_201 + mclk frequency = 1/201 * hmclk frequency + 0xC8 + + + DIVIDE_202 + mclk frequency = 1/202 * hmclk frequency + 0xC9 + + + DIVIDE_203 + mclk frequency = 1/203 * hmclk frequency + 0xCA + + + DIVIDE_204 + mclk frequency = 1/204 * hmclk frequency + 0xCB + + + DIVIDE_205 + mclk frequency = 1/205 * hmclk frequency + 0xCC + + + DIVIDE_206 + mclk frequency = 1/206 * hmclk frequency + 0xCD + + + DIVIDE_207 + mclk frequency = 1/207 * hmclk frequency + 0xCE + + + DIVIDE_208 + mclk frequency = 1/208 * hmclk frequency + 0xCF + + + DIVIDE_209 + mclk frequency = 1/209 * hmclk frequency + 0xD0 + + + DIVIDE_210 + mclk frequency = 1/210 * hmclk frequency + 0xD1 + + + DIVIDE_211 + mclk frequency = 1/211 * hmclk frequency + 0xD2 + + + DIVIDE_212 + mclk frequency = 1/212 * hmclk frequency + 0xD3 + + + DIVIDE_213 + mclk frequency = 1/213 * hmclk frequency + 0xD4 + + + DIVIDE_214 + mclk frequency = 1/214 * hmclk frequency + 0xD5 + + + DIVIDE_215 + mclk frequency = 1/215 * hmclk frequency + 0xD6 + + + DIVIDE_216 + mclk frequency = 1/216 * hmclk frequency + 0xD7 + + + DIVIDE_217 + mclk frequency = 1/217 * hmclk frequency + 0xD8 + + + DIVIDE_218 + mclk frequency = 1/218 * hmclk frequency + 0xD9 + + + DIVIDE_219 + mclk frequency = 1/219 * hmclk frequency + 0xDA + + + DIVIDE_220 + mclk frequency = 1/220 * hmclk frequency + 0xDB + + + DIVIDE_221 + mclk frequency = 1/221 * hmclk frequency + 0xDC + + + DIVIDE_222 + mclk frequency = 1/222 * hmclk frequency + 0xDD + + + DIVIDE_223 + mclk frequency = 1/223 * hmclk frequency + 0xDE + + + DIVIDE_224 + mclk frequency = 1/224 * hmclk frequency + 0xDF + + + DIVIDE_225 + mclk frequency = 1/225 * hmclk frequency + 0xE0 + + + DIVIDE_226 + mclk frequency = 1/226 * hmclk frequency + 0xE1 + + + DIVIDE_227 + mclk frequency = 1/227 * hmclk frequency + 0xE2 + + + DIVIDE_228 + mclk frequency = 1/228 * hmclk frequency + 0xE3 + + + DIVIDE_229 + mclk frequency = 1/229 * hmclk frequency + 0xE4 + + + DIVIDE_230 + mclk frequency = 1/230 * hmclk frequency + 0xE5 + + + DIVIDE_231 + mclk frequency = 1/231 * hmclk frequency + 0xE6 + + + DIVIDE_232 + mclk frequency = 1/232 * hmclk frequency + 0xE7 + + + DIVIDE_233 + mclk frequency = 1/233 * hmclk frequency + 0xE8 + + + DIVIDE_234 + mclk frequency = 1/234 * hmclk frequency + 0xE9 + + + DIVIDE_235 + mclk frequency = 1/235 * hmclk frequency + 0xEA + + + DIVIDE_236 + mclk frequency = 1/236 * hmclk frequency + 0xEB + + + DIVIDE_237 + mclk frequency = 1/237 * hmclk frequency + 0xEC + + + DIVIDE_238 + mclk frequency = 1/238 * hmclk frequency + 0xED + + + DIVIDE_239 + mclk frequency = 1/239 * hmclk frequency + 0xEE + + + DIVIDE_240 + mclk frequency = 1/240 * hmclk frequency + 0xEF + + + DIVIDE_241 + mclk frequency = 1/241 * hmclk frequency + 0xF0 + + + DIVIDE_242 + mclk frequency = 1/242 * hmclk frequency + 0xF1 + + + DIVIDE_243 + mclk frequency = 1/243 * hmclk frequency + 0xF2 + + + DIVIDE_244 + mclk frequency = 1/244 * hmclk frequency + 0xF3 + + + DIVIDE_245 + mclk frequency = 1/245 * hmclk frequency + 0xF4 + + + DIVIDE_246 + mclk frequency = 1/246 * hmclk frequency + 0xF5 + + + DIVIDE_247 + mclk frequency = 1/247 * hmclk frequency + 0xF6 + + + DIVIDE_248 + mclk frequency = 1/248 * hmclk frequency + 0xF7 + + + DIVIDE_249 + mclk frequency = 1/249 * hmclk frequency + 0xF8 + + + DIVIDE_250 + mclk frequency = 1/250 * hmclk frequency + 0xF9 + + + DIVIDE_251 + mclk frequency = 1/251 * hmclk frequency + 0xFA + + + DIVIDE_252 + mclk frequency = 1/252 * hmclk frequency + 0xFB + + + DIVIDE_253 + mclk frequency = 1/253 * hmclk frequency + 0xFC + + + DIVIDE_254 + mclk frequency = 1/254 * hmclk frequency + 0xFD + + + DIVIDE_255 + mclk frequency = 1/255 * hmclk frequency + 0xFE + + + DIVIDE_256 + mclk frequency = 1/256 * hmclk frequency + 0xFF + + + + + MQS_SW_RST + MQS software reset + 24 + 1 + read-write + + + MQS_SW_RST_0 + Exit software reset for MQS + 0 + + + MQS_SW_RST_1 + Enable software reset for MQS + 0x1 + + + + + MQS_EN + MQS enable. + 25 + 1 + read-write + + + MQS_EN_0 + Disable MQS + 0 + + + MQS_EN_1 + Enable MQS + 0x1 + + + + + MQS_OVERSAMPLE + Used to control the PWM oversampling rate compared with mclk. + 26 + 1 + read-write + + + MQS_OVERSAMPLE_0 + 32 + 0 + + + MQS_OVERSAMPLE_1 + 64 + 0x1 + + + + + QTIMER1_TMR_CNTS_FREEZE + QTIMER1 timer counter freeze + 28 + 1 + read-write + + + QTIMER1_TMR_CNTS_FREEZE_0 + timer counter work normally + 0 + + + QTIMER1_TMR_CNTS_FREEZE_1 + reset counter and ouput flags + 0x1 + + + + + QTIMER2_TMR_CNTS_FREEZE + QTIMER2 timer counter freeze + 29 + 1 + read-write + + + QTIMER2_TMR_CNTS_FREEZE_0 + timer counter work normally + 0 + + + QTIMER2_TMR_CNTS_FREEZE_1 + reset counter and ouput flags + 0x1 + + + + + QTIMER3_TMR_CNTS_FREEZE + QTIMER3 timer counter freeze + 30 + 1 + read-write + + + QTIMER3_TMR_CNTS_FREEZE_0 + timer counter work normally + 0 + + + QTIMER3_TMR_CNTS_FREEZE_1 + reset counter and ouput flags + 0x1 + + + + + QTIMER4_TMR_CNTS_FREEZE + QTIMER4 timer counter freeze + 31 + 1 + read-write + + + QTIMER4_TMR_CNTS_FREEZE_0 + timer counter work normally + 0 + + + QTIMER4_TMR_CNTS_FREEZE_1 + reset counter and ouput flags + 0x1 + + + + + + + GPR3 + GPR3 General Purpose Register + 0xC + 32 + read-write + 0xF0F0 + 0xFFFFFFFF + + + OCRAM_CTL + OCRAM_CTL[3] - write address pipeline control bit + 0 + 4 + read-write + + + DCP_KEY_SEL + Select 128-bit dcp key from 256-bit key from snvs/ocotp + 4 + 1 + read-write + + + DCP_KEY_SEL_0 + Select [127:0] from snvs/ocotp key as dcp key + 0 + + + DCP_KEY_SEL_1 + Select [255:128] from snvs/ocotp key as dcp key + 0x1 + + + + + OCRAM2_CTL + OCRAM2_CTL[3] - write address pipeline control bit + 8 + 4 + read-write + + + AXBS_L_HALT_REQ + Request to halt axbs_l + 15 + 1 + read-write + + + AXBS_L_HALT_REQ_0 + axbs_l normal run + 0 + + + AXBS_L_HALT_REQ_1 + request to halt axbs_l + 0x1 + + + + + OCRAM_STATUS + This field shows the OCRAM pipeline settings status, controlled by OCRAM_CTL bits respectively + 16 + 4 + read-only + + + OCRAM2_STATUS + This field shows the OCRAM2 pipeline settings status, controlled by OCRAM2_CTL bits respectively + 24 + 4 + read-only + + + AXBS_L_HALTED + This bit shows the status of axbs_l + 31 + 1 + read-write + + + AXBS_L_HALTED_0 + axbs_l is not halted + 0 + + + AXBS_L_HALTED_1 + axbs_l is in halted status + 0x1 + + + + + + + GPR4 + GPR4 General Purpose Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + EDMA_STOP_REQ + EDMA stop request. + 0 + 1 + read-write + + + EDMA_STOP_REQ_0 + stop request off + 0 + + + EDMA_STOP_REQ_1 + stop request on + 0x1 + + + + + CAN1_STOP_REQ + CAN1 stop request. + 1 + 1 + read-write + + + CAN1_STOP_REQ_0 + stop request off + 0 + + + CAN1_STOP_REQ_1 + stop request on + 0x1 + + + + + CAN2_STOP_REQ + CAN2 stop request. + 2 + 1 + read-write + + + CAN2_STOP_REQ_0 + stop request off + 0 + + + CAN2_STOP_REQ_1 + stop request on + 0x1 + + + + + TRNG_STOP_REQ + TRNG stop request. + 3 + 1 + read-write + + + TRNG_STOP_REQ_0 + stop request off + 0 + + + TRNG_STOP_REQ_1 + stop request on + 0x1 + + + + + ENET_STOP_REQ + ENET stop request. + 4 + 1 + read-write + + + ENET_STOP_REQ_0 + stop request off + 0 + + + ENET_STOP_REQ_1 + stop request on + 0x1 + + + + + SAI1_STOP_REQ + SAI1 stop request. + 5 + 1 + read-write + + + SAI1_STOP_REQ_0 + stop request off + 0 + + + SAI1_STOP_REQ_1 + stop request on + 0x1 + + + + + SAI2_STOP_REQ + SAI2 stop request. + 6 + 1 + read-write + + + SAI2_STOP_REQ_0 + stop request off + 0 + + + SAI2_STOP_REQ_1 + stop request on + 0x1 + + + + + SAI3_STOP_REQ + SAI3 stop request. + 7 + 1 + read-write + + + SAI3_STOP_REQ_0 + stop request off + 0 + + + SAI3_STOP_REQ_1 + stop request on + 0x1 + + + + + ENET2_STOP_REQ + ENET2 stop request. + 8 + 1 + read-write + + + ENET2_STOP_REQ_0 + stop request off + 0 + + + ENET2_STOP_REQ_1 + stop request on + 0x1 + + + + + SEMC_STOP_REQ + SEMC stop request. + 9 + 1 + read-write + + + SEMC_STOP_REQ_0 + stop request off + 0 + + + SEMC_STOP_REQ_1 + stop request on + 0x1 + + + + + PIT_STOP_REQ + PIT stop request. + 10 + 1 + read-write + + + PIT_STOP_REQ_0 + stop request off + 0 + + + PIT_STOP_REQ_1 + stop request on + 0x1 + + + + + FLEXSPI_STOP_REQ + FlexSPI stop request. + 11 + 1 + read-write + + + FLEXSPI_STOP_REQ_0 + stop request off + 0 + + + FLEXSPI_STOP_REQ_1 + stop request on + 0x1 + + + + + FLEXIO1_STOP_REQ + FlexIO1 stop request. + 12 + 1 + read-write + + + FLEXIO1_STOP_REQ_0 + stop request off + 0 + + + FLEXIO1_STOP_REQ_1 + stop request on + 0x1 + + + + + FLEXIO2_STOP_REQ + FlexIO2 stop request. + 13 + 1 + read-write + + + FLEXIO2_STOP_REQ_0 + stop request off + 0 + + + FLEXIO2_STOP_REQ_1 + stop request on + 0x1 + + + + + FLEXIO3_STOP_REQ + On-platform flexio3 stop request. + 14 + 1 + read-write + + + FLEXIO3_STOP_REQ_0 + stop request off + 0 + + + FLEXIO3_STOP_REQ_1 + stop request on + 0x1 + + + + + FLEXSPI2_STOP_REQ + FlexSPI2 stop request. + 15 + 1 + read-write + + + FLEXSPI2_STOP_REQ_0 + stop request off + 0 + + + FLEXSPI2_STOP_REQ_1 + stop request on + 0x1 + + + + + EDMA_STOP_ACK + EDMA stop acknowledge. This is a status (read-only) bit + 16 + 1 + read-only + + + EDMA_STOP_ACK_0 + EDMA stop acknowledge is not asserted + 0 + + + EDMA_STOP_ACK_1 + EDMA stop acknowledge is asserted (EDMA is in STOP mode). + 0x1 + + + + + CAN1_STOP_ACK + CAN1 stop acknowledge. + 17 + 1 + read-only + + + CAN1_STOP_ACK_0 + CAN1 stop acknowledge is not asserted + 0 + + + CAN1_STOP_ACK_1 + CAN1 stop acknowledge is asserted + 0x1 + + + + + CAN2_STOP_ACK + CAN2 stop acknowledge. + 18 + 1 + read-only + + + CAN2_STOP_ACK_0 + CAN2 stop acknowledge is not asserted + 0 + + + CAN2_STOP_ACK_1 + CAN2 stop acknowledge is asserted + 0x1 + + + + + TRNG_STOP_ACK + TRNG stop acknowledge + 19 + 1 + read-only + + + TRNG_STOP_ACK_0 + TRNG stop acknowledge is not asserted + 0 + + + TRNG_STOP_ACK_1 + TRNG stop acknowledge is asserted + 0x1 + + + + + ENET_STOP_ACK + ENET stop acknowledge. + 20 + 1 + read-only + + + ENET_STOP_ACK_0 + ENET1 stop acknowledge is not asserted + 0 + + + ENET_STOP_ACK_1 + ENET1 stop acknowledge is asserted + 0x1 + + + + + SAI1_STOP_ACK + SAI1 stop acknowledge + 21 + 1 + read-only + + + SAI1_STOP_ACK_0 + SAI1 stop acknowledge is not asserted + 0 + + + SAI1_STOP_ACK_1 + SAI1 stop acknowledge is asserted + 0x1 + + + + + SAI2_STOP_ACK + SAI2 stop acknowledge + 22 + 1 + read-only + + + SAI2_STOP_ACK_0 + SAI2 stop acknowledge is not asserted + 0 + + + SAI2_STOP_ACK_1 + SAI2 stop acknowledge is asserted + 0x1 + + + + + SAI3_STOP_ACK + SAI3 stop acknowledge + 23 + 1 + read-only + + + SAI3_STOP_ACK_0 + SAI3 stop acknowledge is not asserted + 0 + + + SAI3_STOP_ACK_1 + SAI3 stop acknowledge is asserted + 0x1 + + + + + ENET2_STOP_ACK + ENET2 stop acknowledge. + 24 + 1 + read-only + + + ENET2_STOP_ACK_0 + ENET2 stop acknowledge is not asserted + 0 + + + ENET2_STOP_ACK_1 + ENET2 stop acknowledge is asserted + 0x1 + + + + + SEMC_STOP_ACK + SEMC stop acknowledge + 25 + 1 + read-only + + + SEMC_STOP_ACK_0 + SEMC stop acknowledge is not asserted + 0 + + + SEMC_STOP_ACK_1 + SEMC stop acknowledge is asserted + 0x1 + + + + + PIT_STOP_ACK + PIT stop acknowledge + 26 + 1 + read-only + + + PIT_STOP_ACK_0 + PIT stop acknowledge is not asserted + 0 + + + PIT_STOP_ACK_1 + PIT stop acknowledge is asserted + 0x1 + + + + + FLEXSPI_STOP_ACK + FLEXSPI stop acknowledge + 27 + 1 + read-only + + + FLEXSPI_STOP_ACK_0 + FLEXSPI stop acknowledge is not asserted + 0 + + + FLEXSPI_STOP_ACK_1 + FLEXSPI stop acknowledge is asserted + 0x1 + + + + + FLEXIO1_STOP_ACK + FLEXIO1 stop acknowledge + 28 + 1 + read-only + + + FLEXIO1_STOP_ACK_0 + FLEXIO1 stop acknowledge is not asserted + 0 + + + FLEXIO1_STOP_ACK_1 + FLEXIO1 stop acknowledge is asserted + 0x1 + + + + + FLEXIO2_STOP_ACK + FLEXIO2 stop acknowledge + 29 + 1 + read-only + + + FLEXIO2_STOP_ACK_0 + FLEXIO2 stop acknowledge is not asserted + 0 + + + FLEXIO2_STOP_ACK_1 + FLEXIO2 stop acknowledge is asserted (FLEXIO2 is in STOP mode) + 0x1 + + + + + FLEXIO3_STOP_ACK + On-platform FLEXIO3 stop acknowledge + 30 + 1 + read-only + + + FLEXIO3_STOP_ACK_0 + FLEXIO3 stop acknowledge is not asserted + 0 + + + FLEXIO3_STOP_ACK_1 + FLEXIO3 stop acknowledge is asserted + 0x1 + + + + + FLEXSPI2_STOP_ACK + FLEXSPI2 stop acknowledge + 31 + 1 + read-only + + + FLEXSPI2_STOP_ACK_0 + FLEXSPI2 stop acknowledge is not asserted + 0 + + + FLEXSPI2_STOP_ACK_1 + FLEXSPI2 stop acknowledge is asserted + 0x1 + + + + + + + GPR5 + GPR5 General Purpose Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDOG1_MASK + WDOG1 Timeout Mask + 6 + 1 + read-write + + + WDOG1_MASK_0 + WDOG1 Timeout behaves normally + 0 + + + WDOG1_MASK_1 + WDOG1 Timeout is masked + 0x1 + + + + + WDOG2_MASK + WDOG2 Timeout Mask + 7 + 1 + read-write + + + WDOG2_MASK_0 + WDOG2 Timeout behaves normally + 0 + + + WDOG2_MASK_1 + WDOG2 Timeout is masked + 0x1 + + + + + GPT2_CAPIN1_SEL + GPT2 input capture channel 1 source select + 23 + 1 + read-write + + + GPT2_CAPIN1_SEL_0 + source from GPT2_CAPTURE1 + 0 + + + GPT2_CAPIN1_SEL_1 + source from ENET_1588_EVENT3_OUT (chnnal 3 of IEEE 1588 timer) + 0x1 + + + + + GPT2_CAPIN2_SEL + GPT2 input capture channel 2 source select + 24 + 1 + read-write + + + GPT2_CAPIN2_SEL_0 + source from GPT2_CAPTURE2 + 0 + + + GPT2_CAPIN2_SEL_1 + source from ENET2_1588_EVENT3_OUT (chnnal 3 of IEEE 1588 timer) + 0x1 + + + + + ENET_EVENT3IN_SEL + ENET input timer event3 source select + 25 + 1 + read-write + + + ENET_EVENT3IN_SEL_0 + event3 source input from ENET_1588_EVENT3_IN + 0 + + + ENET_EVENT3IN_SEL_1 + event3 source input from GPT2.GPT_COMPARE1 + 0x1 + + + + + ENET2_EVENT3IN_SEL + ENET2 input timer event3 source select + 26 + 1 + read-write + + + ENET2_EVENT3IN_SEL_0 + event3 source input from ENET2_1588_EVENT3_IN + 0 + + + ENET2_EVENT3IN_SEL_1 + event3 source input from GPT2.GPT_COMPARE2 + 0x1 + + + + + VREF_1M_CLK_GPT1 + GPT1 1 MHz clock source select + 28 + 1 + read-write + + + VREF_1M_CLK_GPT1_0 + GPT1 ipg_clk_highfreq driven by IPG_PERCLK + 0 + + + VREF_1M_CLK_GPT1_1 + GPT1 ipg_clk_highfreq driven by anatop 1 MHz clock + 0x1 + + + + + VREF_1M_CLK_GPT2 + GPT2 1 MHz clock source select + 29 + 1 + read-write + + + VREF_1M_CLK_GPT2_0 + GPT2 ipg_clk_highfreq driven by IPG_PERCLK + 0 + + + VREF_1M_CLK_GPT2_1 + GPT2 ipg_clk_highfreq driven by anatop 1 MHz clock + 0x1 + + + + + + + GPR6 + GPR6 General Purpose Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + QTIMER1_TRM0_INPUT_SEL + QTIMER1 TMR0 input select + 0 + 1 + read-write + + + QTIMER1_TRM0_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER1_TRM0_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER1_TRM1_INPUT_SEL + QTIMER1 TMR1 input select + 1 + 1 + read-write + + + QTIMER1_TRM1_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER1_TRM1_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER1_TRM2_INPUT_SEL + QTIMER1 TMR2 input select + 2 + 1 + read-write + + + QTIMER1_TRM2_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER1_TRM2_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER1_TRM3_INPUT_SEL + QTIMER1 TMR3 input select + 3 + 1 + read-write + + + QTIMER1_TRM3_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER1_TRM3_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER2_TRM0_INPUT_SEL + QTIMER2 TMR0 input select + 4 + 1 + read-write + + + QTIMER2_TRM0_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER2_TRM0_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER2_TRM1_INPUT_SEL + QTIMER2 TMR1 input select + 5 + 1 + read-write + + + QTIMER2_TRM1_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER2_TRM1_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER2_TRM2_INPUT_SEL + QTIMER2 TMR2 input select + 6 + 1 + read-write + + + QTIMER2_TRM2_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER2_TRM2_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER2_TRM3_INPUT_SEL + QTIMER2 TMR3 input select + 7 + 1 + read-write + + + QTIMER2_TRM3_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER2_TRM3_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER3_TRM0_INPUT_SEL + QTIMER3 TMR0 input select + 8 + 1 + read-write + + + QTIMER3_TRM0_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER3_TRM0_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER3_TRM1_INPUT_SEL + QTIMER3 TMR1 input select + 9 + 1 + read-write + + + QTIMER3_TRM1_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER3_TRM1_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER3_TRM2_INPUT_SEL + QTIMER3 TMR2 input select + 10 + 1 + read-write + + + QTIMER3_TRM2_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER3_TRM2_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER3_TRM3_INPUT_SEL + QTIMER3 TMR3 input select + 11 + 1 + read-write + + + QTIMER3_TRM3_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER3_TRM3_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER4_TRM0_INPUT_SEL + QTIMER4 TMR0 input select + 12 + 1 + read-write + + + QTIMER4_TRM0_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER4_TRM0_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER4_TRM1_INPUT_SEL + QTIMER4 TMR1 input select + 13 + 1 + read-write + + + QTIMER4_TRM1_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER4_TRM1_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER4_TRM2_INPUT_SEL + QTIMER4 TMR2 input select + 14 + 1 + read-write + + + QTIMER4_TRM2_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER4_TRM2_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + QTIMER4_TRM3_INPUT_SEL + QTIMER4 TMR3 input select + 15 + 1 + read-write + + + QTIMER4_TRM3_INPUT_SEL_0 + input from IOMUX + 0 + + + QTIMER4_TRM3_INPUT_SEL_1 + input from XBAR + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_4 + IOMUXC XBAR_INOUT4 function direction select + 16 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_4_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_4_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_5 + IOMUXC XBAR_INOUT5 function direction select + 17 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_5_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_5_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_6 + IOMUXC XBAR_INOUT6 function direction select + 18 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_6_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_6_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_7 + IOMUXC XBAR_INOUT7 function direction select + 19 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_7_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_7_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_8 + IOMUXC XBAR_INOUT8 function direction select + 20 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_8_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_8_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_9 + IOMUXC XBAR_INOUT9 function direction select + 21 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_9_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_9_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_10 + IOMUXC XBAR_INOUT10 function direction select + 22 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_10_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_10_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_11 + IOMUXC XBAR_INOUT11 function direction select + 23 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_11_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_11_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_12 + IOMUXC XBAR_INOUT12 function direction select + 24 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_12_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_12_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_13 + IOMUXC XBAR_INOUT13 function direction select + 25 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_13_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_13_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_14 + IOMUXC XBAR_INOUT14 function direction select + 26 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_14_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_14_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_15 + IOMUXC XBAR_INOUT15 function direction select + 27 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_15_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_15_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_16 + IOMUXC XBAR_INOUT16 function direction select + 28 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_16_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_16_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_17 + IOMUXC XBAR_INOUT17 function direction select + 29 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_17_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_17_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_18 + IOMUXC XBAR_INOUT18 function direction select + 30 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_18_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_18_1 + XBAR_INOUT as output + 0x1 + + + + + IOMUXC_XBAR_DIR_SEL_19 + IOMUXC XBAR_INOUT19 function direction select + 31 + 1 + read-write + + + IOMUXC_XBAR_DIR_SEL_19_0 + XBAR_INOUT as input + 0 + + + IOMUXC_XBAR_DIR_SEL_19_1 + XBAR_INOUT as output + 0x1 + + + + + + + GPR7 + GPR7 General Purpose Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + LPI2C1_STOP_REQ + LPI2C1 stop request + 0 + 1 + read-write + + + LPI2C1_STOP_REQ_0 + stop request off + 0 + + + LPI2C1_STOP_REQ_1 + stop request on + 0x1 + + + + + LPI2C2_STOP_REQ + LPI2C2 stop request + 1 + 1 + read-write + + + LPI2C2_STOP_REQ_0 + stop request off + 0 + + + LPI2C2_STOP_REQ_1 + stop request on + 0x1 + + + + + LPI2C3_STOP_REQ + LPI2C3 stop request + 2 + 1 + read-write + + + LPI2C3_STOP_REQ_0 + stop request off + 0 + + + LPI2C3_STOP_REQ_1 + stop request on + 0x1 + + + + + LPI2C4_STOP_REQ + LPI2C4 stop request + 3 + 1 + read-write + + + LPI2C4_STOP_REQ_0 + stop request off + 0 + + + LPI2C4_STOP_REQ_1 + stop request on + 0x1 + + + + + LPSPI1_STOP_REQ + LPSPI1 stop request + 4 + 1 + read-write + + + LPSPI1_STOP_REQ_0 + stop request off + 0 + + + LPSPI1_STOP_REQ_1 + stop request on + 0x1 + + + + + LPSPI2_STOP_REQ + LPSPI2 stop request + 5 + 1 + read-write + + + LPSPI2_STOP_REQ_0 + stop request off + 0 + + + LPSPI2_STOP_REQ_1 + stop request on + 0x1 + + + + + LPSPI3_STOP_REQ + LPSPI3 stop request + 6 + 1 + read-write + + + LPSPI3_STOP_REQ_0 + stop request off + 0 + + + LPSPI3_STOP_REQ_1 + stop request on + 0x1 + + + + + LPSPI4_STOP_REQ + LPSPI4 stop request + 7 + 1 + read-write + + + LPSPI4_STOP_REQ_0 + stop request off + 0 + + + LPSPI4_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART1_STOP_REQ + LPUART1 stop request + 8 + 1 + read-write + + + LPUART1_STOP_REQ_0 + stop request off + 0 + + + LPUART1_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART2_STOP_REQ + LPUART1 stop request + 9 + 1 + read-write + + + LPUART2_STOP_REQ_0 + stop request off + 0 + + + LPUART2_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART3_STOP_REQ + LPUART3 stop request + 10 + 1 + read-write + + + LPUART3_STOP_REQ_0 + stop request off + 0 + + + LPUART3_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART4_STOP_REQ + LPUART4 stop request + 11 + 1 + read-write + + + LPUART4_STOP_REQ_0 + stop request off + 0 + + + LPUART4_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART5_STOP_REQ + LPUART5 stop request + 12 + 1 + read-write + + + LPUART5_STOP_REQ_0 + stop request off + 0 + + + LPUART5_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART6_STOP_REQ + LPUART6 stop request + 13 + 1 + read-write + + + LPUART6_STOP_REQ_0 + stop request off + 0 + + + LPUART6_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART7_STOP_REQ + LPUART7 stop request + 14 + 1 + read-write + + + LPUART7_STOP_REQ_0 + stop request off + 0 + + + LPUART7_STOP_REQ_1 + stop request on + 0x1 + + + + + LPUART8_STOP_REQ + LPUART8 stop request + 15 + 1 + read-write + + + LPUART8_STOP_REQ_0 + stop request off + 0 + + + LPUART8_STOP_REQ_1 + stop request on + 0x1 + + + + + LPI2C1_STOP_ACK + LPI2C1 stop acknowledge + 16 + 1 + read-only + + + LPI2C1_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPI2C1_STOP_ACK_1 + stop acknowledge is asserted (the module is in Stop mode) + 0x1 + + + + + LPI2C2_STOP_ACK + LPI2C2 stop acknowledge + 17 + 1 + read-only + + + LPI2C2_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPI2C2_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPI2C3_STOP_ACK + LPI2C3 stop acknowledge + 18 + 1 + read-only + + + LPI2C3_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPI2C3_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPI2C4_STOP_ACK + LPI2C4 stop acknowledge + 19 + 1 + read-only + + + LPI2C4_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPI2C4_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPSPI1_STOP_ACK + LPSPI1 stop acknowledge + 20 + 1 + read-only + + + LPSPI1_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPSPI1_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPSPI2_STOP_ACK + LPSPI2 stop acknowledge + 21 + 1 + read-only + + + LPSPI2_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPSPI2_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPSPI3_STOP_ACK + LPSPI3 stop acknowledge + 22 + 1 + read-only + + + LPSPI3_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPSPI3_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPSPI4_STOP_ACK + LPSPI4 stop acknowledge + 23 + 1 + read-only + + + LPSPI4_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPSPI4_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART1_STOP_ACK + LPUART1 stop acknowledge + 24 + 1 + read-only + + + LPUART1_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART1_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART2_STOP_ACK + LPUART1 stop acknowledge + 25 + 1 + read-only + + + LPUART2_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART2_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART3_STOP_ACK + LPUART3 stop acknowledge + 26 + 1 + read-only + + + LPUART3_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART3_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART4_STOP_ACK + LPUART4 stop acknowledge + 27 + 1 + read-only + + + LPUART4_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART4_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART5_STOP_ACK + LPUART5 stop acknowledge + 28 + 1 + read-only + + + LPUART5_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART5_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART6_STOP_ACK + LPUART6 stop acknowledge + 29 + 1 + read-only + + + LPUART6_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART6_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART7_STOP_ACK + LPUART7 stop acknowledge + 30 + 1 + read-only + + + LPUART7_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART7_STOP_ACK_1 + stop acknowledge is asserted + 0x1 + + + + + LPUART8_STOP_ACK + LPUART8 stop acknowledge + 31 + 1 + read-only + + + LPUART8_STOP_ACK_0 + stop acknowledge is not asserted + 0 + + + LPUART8_STOP_ACK_1 + stop acknowledge is asserted (the module is in Stop mode) + 0x1 + + + + + + + GPR8 + GPR8 General Purpose Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + LPI2C1_IPG_STOP_MODE + LPI2C1 stop mode selection, cannot change when ipg_stop is asserted. + 0 + 1 + read-write + + + LPI2C1_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPI2C1_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPI2C1_IPG_DOZE + LPI2C1 ipg_doze mode + 1 + 1 + read-write + + + LPI2C1_IPG_DOZE_0 + not in doze mode + 0 + + + LPI2C1_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPI2C2_IPG_STOP_MODE + LPI2C2 stop mode selection, cannot change when ipg_stop is asserted. + 2 + 1 + read-write + + + LPI2C2_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPI2C2_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPI2C2_IPG_DOZE + LPI2C2 ipg_doze mode + 3 + 1 + read-write + + + LPI2C2_IPG_DOZE_0 + not in doze mode + 0 + + + LPI2C2_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPI2C3_IPG_STOP_MODE + LPI2C3 stop mode selection, cannot change when ipg_stop is asserted. + 4 + 1 + read-write + + + LPI2C3_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPI2C3_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPI2C3_IPG_DOZE + LPI2C3 ipg_doze mode + 5 + 1 + read-write + + + LPI2C3_IPG_DOZE_0 + not in doze mode + 0 + + + LPI2C3_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPI2C4_IPG_STOP_MODE + LPI2C4 stop mode selection, cannot change when ipg_stop is asserted. + 6 + 1 + read-write + + + LPI2C4_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPI2C4_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPI2C4_IPG_DOZE + LPI2C4 ipg_doze mode + 7 + 1 + read-write + + + LPI2C4_IPG_DOZE_0 + not in doze mode + 0 + + + LPI2C4_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPSPI1_IPG_STOP_MODE + LPSPI1 stop mode selection, cannot change when ipg_stop is asserted. + 8 + 1 + read-write + + + LPSPI1_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPSPI1_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPSPI1_IPG_DOZE + LPSPI1 ipg_doze mode + 9 + 1 + read-write + + + LPSPI1_IPG_DOZE_0 + not in doze mode + 0 + + + LPSPI1_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPSPI2_IPG_STOP_MODE + LPSPI2 stop mode selection, cannot change when ipg_stop is asserted. + 10 + 1 + read-write + + + LPSPI2_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPSPI2_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPSPI2_IPG_DOZE + LPSPI2 ipg_doze mode + 11 + 1 + read-write + + + LPSPI2_IPG_DOZE_0 + not in doze mode + 0 + + + LPSPI2_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPSPI3_IPG_STOP_MODE + LPSPI3 stop mode selection, cannot change when ipg_stop is asserted. + 12 + 1 + read-write + + + LPSPI3_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPSPI3_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPSPI3_IPG_DOZE + LPSPI3 ipg_doze mode + 13 + 1 + read-write + + + LPSPI3_IPG_DOZE_0 + not in doze mode + 0 + + + LPSPI3_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPSPI4_IPG_STOP_MODE + LPSPI4 stop mode selection, cannot change when ipg_stop is asserted. + 14 + 1 + read-write + + + LPSPI4_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPSPI4_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPSPI4_IPG_DOZE + LPSPI4 ipg_doze mode + 15 + 1 + read-write + + + LPSPI4_IPG_DOZE_0 + not in doze mode + 0 + + + LPSPI4_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART1_IPG_STOP_MODE + LPUART1 stop mode selection, cannot change when ipg_stop is asserted. + 16 + 1 + read-write + + + LPUART1_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART1_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART1_IPG_DOZE + LPUART1 ipg_doze mode + 17 + 1 + read-write + + + LPUART1_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART1_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART2_IPG_STOP_MODE + LPUART2 stop mode selection, cannot change when ipg_stop is asserted. + 18 + 1 + read-write + + + LPUART2_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART2_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART2_IPG_DOZE + LPUART2 ipg_doze mode + 19 + 1 + read-write + + + LPUART2_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART2_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART3_IPG_STOP_MODE + LPUART3 stop mode selection, cannot change when ipg_stop is asserted. + 20 + 1 + read-write + + + LPUART3_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART3_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART3_IPG_DOZE + LPUART3 ipg_doze mode + 21 + 1 + read-write + + + LPUART3_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART3_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART4_IPG_STOP_MODE + LPUART4 stop mode selection, cannot change when ipg_stop is asserted. + 22 + 1 + read-write + + + LPUART4_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART4_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART4_IPG_DOZE + LPUART4 ipg_doze mode + 23 + 1 + read-write + + + LPUART4_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART4_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART5_IPG_STOP_MODE + LPUART5 stop mode selection, cannot change when ipg_stop is asserted. + 24 + 1 + read-write + + + LPUART5_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART5_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART5_IPG_DOZE + LPUART5 ipg_doze mode + 25 + 1 + read-write + + + LPUART5_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART5_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART6_IPG_STOP_MODE + LPUART6 stop mode selection, cannot change when ipg_stop is asserted. + 26 + 1 + read-write + + + LPUART6_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART6_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART6_IPG_DOZE + LPUART6 ipg_doze mode + 27 + 1 + read-write + + + LPUART6_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART6_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART7_IPG_STOP_MODE + LPUART7 stop mode selection, cannot change when ipg_stop is asserted. + 28 + 1 + read-write + + + LPUART7_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART7_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART7_IPG_DOZE + LPUART7 ipg_doze mode + 29 + 1 + read-write + + + LPUART7_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART7_IPG_DOZE_1 + in doze mode + 0x1 + + + + + LPUART8_IPG_STOP_MODE + LPUART8 stop mode selection, cannot change when ipg_stop is asserted. + 30 + 1 + read-write + + + LPUART8_IPG_STOP_MODE_0 + the module is functional in Stop mode + 0 + + + LPUART8_IPG_STOP_MODE_1 + the module is NOT functional in Stop mode, when this bit is equal to 1 and ipg_stop is asserted + 0x1 + + + + + LPUART8_IPG_DOZE + LPUART8 ipg_doze mode + 31 + 1 + read-write + + + LPUART8_IPG_DOZE_0 + not in doze mode + 0 + + + LPUART8_IPG_DOZE_1 + in doze mode + 0x1 + + + + + + + GPR9 + GPR9 General Purpose Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR10 + GPR10 General Purpose Register + 0x28 + 32 + read-write + 0x7 + 0xFFFFFFFF + + + NIDEN + ARM non-secure (non-invasive) debug enable + 0 + 1 + read-write + + + NIDEN_0 + Debug turned off. + 0 + + + NIDEN_1 + Debug enabled (default). + 0x1 + + + + + DBG_EN + ARM invasive debug enable + 1 + 1 + read-write + + + DBG_EN_0 + Debug turned off. + 0 + + + DBG_EN_1 + Debug enabled (default). + 0x1 + + + + + SEC_ERR_RESP + Security error response enable for all security gaskets (on both AHB and AXI buses) + 2 + 1 + read-write + + + SEC_ERR_RESP_0 + OKEY response + 0 + + + SEC_ERR_RESP_1 + SLVError (default) + 0x1 + + + + + DCPKEY_OCOTP_OR_KEYMUX + DCP Key selection bit. + 4 + 1 + read-write + + + DCPKEY_OCOTP_OR_KEYMUX_0 + Select key from Key MUX (SNVS/OTPMK). + 0 + + + DCPKEY_OCOTP_OR_KEYMUX_1 + Select key from OCOTP (SW_GP2). + 0x1 + + + + + OCRAM_TZ_EN + OCRAM TrustZone (TZ) enable. + 8 + 1 + read-write + + + OCRAM_TZ_EN_0 + The TrustZone feature is disabled. Entire OCRAM space is available for all access types (secure/non-secure/user/supervisor). + 0 + + + OCRAM_TZ_EN_1 + The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter. + 0x1 + + + + + OCRAM_TZ_ADDR + OCRAM TrustZone (TZ) start address + 9 + 7 + read-write + + + LOCK_NIDEN + Lock NIDEN field for changes + 16 + 1 + read-write + + + LOCK_NIDEN_0 + Field is not locked + 0 + + + LOCK_NIDEN_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_DBG_EN + Lock DBG_EN field for changes + 17 + 1 + read-write + + + LOCK_DBG_EN_0 + Field is not locked + 0 + + + LOCK_DBG_EN_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_SEC_ERR_RESP + Lock SEC_ERR_RESP field for changes + 18 + 1 + read-write + + + LOCK_SEC_ERR_RESP_0 + Field is not locked + 0 + + + LOCK_SEC_ERR_RESP_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_DCPKEY_OCOTP_OR_KEYMUX + Lock DCP Key OCOTP/Key MUX selection bit + 20 + 1 + read-write + + + LOCK_DCPKEY_OCOTP_OR_KEYMUX_0 + Field is not locked + 0 + + + LOCK_DCPKEY_OCOTP_OR_KEYMUX_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_OCRAM_TZ_EN + Lock OCRAM_TZ_EN field for changes + 24 + 1 + read-write + + + LOCK_OCRAM_TZ_EN_0 + Field is not locked + 0 + + + LOCK_OCRAM_TZ_EN_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_OCRAM_TZ_ADDR + Lock OCRAM_TZ_ADDR field for changes + 25 + 7 + read-write + + + LOCK_OCRAM_TZ_ADDR_0 + Field is not locked + 0 + + + LOCK_OCRAM_TZ_ADDR_1 + Field is locked (read access only) + 0x1 + + + + + + + GPR11 + GPR11 General Purpose Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + M7_APC_AC_R0_CTRL + Access control of memory region-0 + 0 + 2 + read-write + + + M7_APC_AC_R0_CTRL_0 + No access protection + 0 + + + M7_APC_AC_R0_CTRL_1 + M7 debug protection enabled + 0x1 + + + M7_APC_AC_R0_CTRL_2 + FlexSPI access protection + 0x2 + + + M7_APC_AC_R0_CTRL_3 + Both M7 debug and FlexSPI access are protected + 0x3 + + + + + M7_APC_AC_R1_CTRL + Access control of memory region-1 + 2 + 2 + read-write + + + M7_APC_AC_R1_CTRL_0 + No access protection + 0 + + + M7_APC_AC_R1_CTRL_1 + M7 debug protection enabled + 0x1 + + + M7_APC_AC_R1_CTRL_2 + FlexSPI access protection + 0x2 + + + M7_APC_AC_R1_CTRL_3 + Both M7 debug and FlexSPI access are protected + 0x3 + + + + + M7_APC_AC_R2_CTRL + Access control of memory region-2 + 4 + 2 + read-write + + + M7_APC_AC_R2_CTRL_0 + No access protection + 0 + + + M7_APC_AC_R2_CTRL_1 + M7 debug protection enabled + 0x1 + + + M7_APC_AC_R2_CTRL_2 + FlexSPI access protection + 0x2 + + + M7_APC_AC_R2_CTRL_3 + Both M7 debug and FlexSPI access are protected + 0x3 + + + + + M7_APC_AC_R3_CTRL + Access control of memory region-3 + 6 + 2 + read-write + + + M7_APC_AC_R3_CTRL_0 + No access protection + 0 + + + M7_APC_AC_R3_CTRL_1 + M7 debug protection enabled + 0x1 + + + M7_APC_AC_R3_CTRL_2 + FlexSPI access protection + 0x2 + + + M7_APC_AC_R3_CTRL_3 + Both M7 debug and FlexSPI access are protected + 0x3 + + + + + BEE_DE_RX_EN + BEE data decryption of memory region-n (n = 3 to 0) + 8 + 4 + read-write + + + + + GPR12 + GPR12 General Purpose Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXIO1_IPG_STOP_MODE + FlexIO1 stop mode selection. Cannot change when ipg_stop is asserted. + 0 + 1 + read-write + + + FLEXIO1_IPG_STOP_MODE_0 + FlexIO1 is functional in Stop mode. + 0 + + + FLEXIO1_IPG_STOP_MODE_1 + When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO1 is not functional in Stop mode. + 0x1 + + + + + FLEXIO1_IPG_DOZE + FLEXIO1 ipg_doze mode + 1 + 1 + read-write + + + FLEXIO1_IPG_DOZE_0 + FLEXIO1 is not in doze mode + 0 + + + FLEXIO1_IPG_DOZE_1 + FLEXIO1 is in doze mode + 0x1 + + + + + FLEXIO2_IPG_STOP_MODE + FlexIO2 stop mode selection. Cannot change when ipg_stop is asserted. + 2 + 1 + read-write + + + FLEXIO2_IPG_STOP_MODE_0 + FlexIO2 is functional in Stop mode. + 0 + + + FLEXIO2_IPG_STOP_MODE_1 + When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO2 is not functional in Stop mode. + 0x1 + + + + + FLEXIO2_IPG_DOZE + FLEXIO2 ipg_doze mode + 3 + 1 + read-write + + + FLEXIO2_IPG_DOZE_0 + FLEXIO2 is not in doze mode + 0 + + + FLEXIO2_IPG_DOZE_1 + FLEXIO2 is in doze mode + 0x1 + + + + + ACMP_IPG_STOP_MODE + ACMP stop mode selection. Cannot change when ipg_stop is asserted. + 4 + 1 + read-write + + + ACMP_IPG_STOP_MODE_0 + ACMP is functional in Stop mode. + 0 + + + ACMP_IPG_STOP_MODE_1 + When this bit is equal to 1'b1 and ipg_stop is asserted, ACMP is not functional in Stop mode. + 0x1 + + + + + FLEXIO3_IPG_STOP_MODE + FlexIO3 stop mode selection. Cannot change when ipg_stop is asserted. + 5 + 1 + read-write + + + FLEXIO3_IPG_STOP_MODE_0 + FlexIO3 is functional in Stop mode. + 0 + + + FLEXIO3_IPG_STOP_MODE_1 + When this bit is equal to 1'b1 and ipg_stop is asserted, FlexIO3 is not functional in Stop mode. + 0x1 + + + + + FLEXIO3_IPG_DOZE + FLEXIO3 ipg_doze mode + 6 + 1 + read-write + + + FLEXIO3_IPG_DOZE_0 + FLEXIO3 is not in doze mode + 0 + + + FLEXIO3_IPG_DOZE_1 + FLEXIO3 is in doze mode + 0x1 + + + + + + + GPR13 + GPR13 General Purpose Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ARCACHE_USDHC + uSDHC block cacheable attribute value of AXI read transactions + 0 + 1 + read-write + + + ARCACHE_USDHC_0 + Cacheable attribute is off for read transactions. + 0 + + + ARCACHE_USDHC_1 + Cacheable attribute is on for read transactions. + 0x1 + + + + + AWCACHE_USDHC + uSDHC block cacheable attribute value of AXI write transactions + 1 + 1 + read-write + + + AWCACHE_USDHC_0 + Cacheable attribute is off for write transactions. + 0 + + + AWCACHE_USDHC_1 + Cacheable attribute is on for write transactions. + 0x1 + + + + + CANFD_STOP_REQ + CANFD stop request. + 4 + 1 + read-write + + + CANFD_STOP_REQ_0 + stop request off + 0 + + + CANFD_STOP_REQ_1 + stop request on + 0x1 + + + + + CACHE_ENET + ENET block cacheable attribute value of AXI transactions + 7 + 1 + read-write + + + CACHE_ENET_0 + Cacheable attribute is off for read/write transactions. + 0 + + + CACHE_ENET_1 + Cacheable attribute is on for read/write transactions. + 0x1 + + + + + CACHE_USB + USB block cacheable attribute value of AXI transactions + 13 + 1 + read-write + + + CACHE_USB_0 + Cacheable attribute is off for read/write transactions. + 0 + + + CACHE_USB_1 + Cacheable attribute is on for read/write transactions. + 0x1 + + + + + CANFD_STOP_ACK + CANFD stop acknowledge. + 20 + 1 + read-only + + + CANFD_STOP_ACK_0 + CANFD stop acknowledge is not asserted + 0 + + + CANFD_STOP_ACK_1 + CANFD stop acknowledge is asserted + 0x1 + + + + + + + GPR14 + GPR14 General Purpose Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACMP1_CMP_IGEN_TRIM_DN + reduces ACMP1 internal bias current by 30% + 0 + 1 + read-write + + + ACMP1_CMP_IGEN_TRIM_DN_0 + no reduce + 0 + + + ACMP1_CMP_IGEN_TRIM_DN_1 + reduces + 0x1 + + + + + ACMP2_CMP_IGEN_TRIM_DN + reduces ACMP2 internal bias current by 30% + 1 + 1 + read-write + + + ACMP2_CMP_IGEN_TRIM_DN_0 + no reduce + 0 + + + ACMP2_CMP_IGEN_TRIM_DN_1 + reduces + 0x1 + + + + + ACMP3_CMP_IGEN_TRIM_DN + reduces ACMP3 internal bias current by 30% + 2 + 1 + read-write + + + ACMP3_CMP_IGEN_TRIM_DN_0 + no reduce + 0 + + + ACMP3_CMP_IGEN_TRIM_DN_1 + reduces + 0x1 + + + + + ACMP4_CMP_IGEN_TRIM_DN + reduces ACMP4 internal bias current by 30% + 3 + 1 + read-write + + + ACMP4_CMP_IGEN_TRIM_DN_0 + no reduce + 0 + + + ACMP4_CMP_IGEN_TRIM_DN_1 + reduces + 0x1 + + + + + ACMP1_CMP_IGEN_TRIM_UP + increases ACMP1 internal bias current by 30% + 4 + 1 + read-write + + + ACMP1_CMP_IGEN_TRIM_UP_0 + no increase + 0 + + + ACMP1_CMP_IGEN_TRIM_UP_1 + increases + 0x1 + + + + + ACMP2_CMP_IGEN_TRIM_UP + increases ACMP2 internal bias current by 30% + 5 + 1 + read-write + + + ACMP2_CMP_IGEN_TRIM_UP_0 + no increase + 0 + + + ACMP2_CMP_IGEN_TRIM_UP_1 + increases + 0x1 + + + + + ACMP3_CMP_IGEN_TRIM_UP + increases ACMP3 internal bias current by 30% + 6 + 1 + read-write + + + ACMP3_CMP_IGEN_TRIM_UP_0 + no increase + 0 + + + ACMP3_CMP_IGEN_TRIM_UP_1 + increases + 0x1 + + + + + ACMP4_CMP_IGEN_TRIM_UP + increases ACMP4 internal bias current by 30% + 7 + 1 + read-write + + + ACMP4_CMP_IGEN_TRIM_UP_0 + no increase + 0 + + + ACMP4_CMP_IGEN_TRIM_UP_1 + increases + 0x1 + + + + + ACMP1_SAMPLE_SYNC_EN + ACMP1 sample_lv source select + 8 + 1 + read-write + + + ACMP1_SAMPLE_SYNC_EN_0 + select XBAR output + 0 + + + ACMP1_SAMPLE_SYNC_EN_1 + select synced sample_lv + 0x1 + + + + + ACMP2_SAMPLE_SYNC_EN + ACMP2 sample_lv source select + 9 + 1 + read-write + + + ACMP2_SAMPLE_SYNC_EN_0 + select XBAR output + 0 + + + ACMP2_SAMPLE_SYNC_EN_1 + select synced sample_lv + 0x1 + + + + + ACMP3_SAMPLE_SYNC_EN + ACMP3 sample_lv source select + 10 + 1 + read-write + + + ACMP3_SAMPLE_SYNC_EN_0 + select XBAR output + 0 + + + ACMP3_SAMPLE_SYNC_EN_1 + select synced sample_lv + 0x1 + + + + + ACMP4_SAMPLE_SYNC_EN + ACMP4 sample_lv source select + 11 + 1 + read-write + + + ACMP4_SAMPLE_SYNC_EN_0 + select XBAR output + 0 + + + ACMP4_SAMPLE_SYNC_EN_1 + select synced sample_lv + 0x1 + + + + + CM7_CFGITCMSZ + ITCM total size configuration + 16 + 4 + read-write + + + CM7_CFGITCMSZ_0 + 0 KB (No ITCM) + 0 + + + CM7_CFGITCMSZ_3 + 4 KB + 0x3 + + + CM7_CFGITCMSZ_4 + 8 KB + 0x4 + + + CM7_CFGITCMSZ_5 + 16 KB + 0x5 + + + CM7_CFGITCMSZ_6 + 32 KB + 0x6 + + + CM7_CFGITCMSZ_7 + 64 KB + 0x7 + + + CM7_CFGITCMSZ_8 + 128 KB + 0x8 + + + CM7_CFGITCMSZ_9 + 256 KB + 0x9 + + + CM7_CFGITCMSZ_10 + 512 KB + 0xA + + + + + CM7_CFGDTCMSZ + DTCM total size configuration + 20 + 4 + read-write + + + CM7_CFGDTCMSZ_0 + 0 KB (No DTCM) + 0 + + + CM7_CFGDTCMSZ_3 + 4 KB + 0x3 + + + CM7_CFGDTCMSZ_4 + 8 KB + 0x4 + + + CM7_CFGDTCMSZ_5 + 16 KB + 0x5 + + + CM7_CFGDTCMSZ_6 + 32 KB + 0x6 + + + CM7_CFGDTCMSZ_7 + 64 KB + 0x7 + + + CM7_CFGDTCMSZ_8 + 128 KB + 0x8 + + + CM7_CFGDTCMSZ_9 + 256 KB + 0x9 + + + CM7_CFGDTCMSZ_10 + 512 KB + 0xA + + + + + + + GPR15 + GPR15 General Purpose Register + 0x3C + 32 + read-only + 0xFFFFFFFF + 0xFFFFFFFF + + + GPR16 + GPR16 General Purpose Register + 0x40 + 32 + read-write + 0x200003 + 0xFFFFFFFF + + + INIT_ITCM_EN + ITCM enable initialization out of reset + 0 + 1 + read-write + + + INIT_ITCM_EN_0 + ITCM is disabled + 0 + + + INIT_ITCM_EN_1 + ITCM is enabled + 0x1 + + + + + INIT_DTCM_EN + DTCM enable initialization out of reset + 1 + 1 + read-write + + + INIT_DTCM_EN_0 + DTCM is disabled + 0 + + + INIT_DTCM_EN_1 + DTCM is enabled + 0x1 + + + + + FLEXRAM_BANK_CFG_SEL + FlexRAM bank config source select + 2 + 1 + read-write + + + FLEXRAM_BANK_CFG_SEL_0 + use fuse value to config + 0 + + + FLEXRAM_BANK_CFG_SEL_1 + use FLEXRAM_BANK_CFG to config + 0x1 + + + + + + + GPR17 + GPR17 General Purpose Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXRAM_BANK_CFG + FlexRAM bank config value + 0 + 32 + read-write + + + + + GPR18 + GPR18 General Purpose Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R0_BOT + lock M7_APC_AC_R0_BOT field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R0_BOT_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R0_BOT_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R0_BOT + APC end address of memory region-0 + 3 + 29 + read-write + + + + + GPR19 + GPR19 General Purpose Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R0_TOP + lock M7_APC_AC_R0_TOP field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R0_TOP_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R0_TOP_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R0_TOP + APC start address of memory region-0 + 3 + 29 + read-write + + + + + GPR20 + GPR20 General Purpose Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R1_BOT + lock M7_APC_AC_R1_BOT field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R1_BOT_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R1_BOT_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R1_BOT + APC end address of memory region-1 + 3 + 29 + read-write + + + + + GPR21 + GPR21 General Purpose Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R1_TOP + lock M7_APC_AC_R1_TOP field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R1_TOP_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R1_TOP_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R1_TOP + APC start address of memory region-1 + 3 + 29 + read-write + + + + + GPR22 + GPR22 General Purpose Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R2_BOT + lock M7_APC_AC_R2_BOT field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R2_BOT_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R2_BOT_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R2_BOT + APC end address of memory region-2 + 3 + 29 + read-write + + + + + GPR23 + GPR23 General Purpose Register + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R2_TOP + lock M7_APC_AC_R2_TOP field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R2_TOP_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R2_TOP_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R2_TOP + APC start address of memory region-2 + 3 + 29 + read-write + + + + + GPR24 + GPR24 General Purpose Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R3_BOT + lock M7_APC_AC_R3_BOT field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R3_BOT_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R3_BOT_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R3_BOT + APC end address of memory region-3 + 3 + 29 + read-write + + + + + GPR25 + GPR25 General Purpose Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOCK_M7_APC_AC_R3_TOP + lock M7_APC_AC_R3_TOP field for changes + 0 + 1 + read-write + + + LOCK_M7_APC_AC_R3_TOP_0 + Register field [31:1] is not locked + 0 + + + LOCK_M7_APC_AC_R3_TOP_1 + Register field [31:1] is locked (read access only) + 0x1 + + + + + M7_APC_AC_R3_TOP + APC start address of memory region-3 + 3 + 29 + read-write + + + + + GPR26 + GPR26 General Purpose Register + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPIO_MUX1_GPIO_SEL + GPIO1 and GPIO6 share same IO MUX function, GPIO_MUX1 selects one GPIO function. + 0 + 32 + read-write + + + + + GPR27 + GPR27 General Purpose Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPIO_MUX2_GPIO_SEL + GPIO2 and GPIO7 share same IO MUX function, GPIO_MUX2 selects one GPIO function. + 0 + 32 + read-write + + + + + GPR28 + GPR28 General Purpose Register + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPIO_MUX3_GPIO_SEL + GPIO3 and GPIO8 share same IO MUX function, GPIO_MUX3 selects one GPIO function. + 0 + 32 + read-write + + + + + GPR29 + GPR29 General Purpose Register + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPIO_MUX4_GPIO_SEL + GPIO4 and GPIO9 share same IO MUX function, GPIO_MUX4 selects one GPIO function. + 0 + 32 + read-write + + + + + GPR30 + GPR30 General Purpose Register + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXSPI_REMAP_ADDR_START + Start address of flexspi1 and flexspi2 + 12 + 20 + read-write + + + + + GPR31 + GPR31 General Purpose Register + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXSPI_REMAP_ADDR_END + End address of flexspi1 and flexspi2 + 12 + 20 + read-write + + + + + GPR32 + GPR32 General Purpose Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXSPI_REMAP_ADDR_OFFSET + Offset address of flexspi1 and flexspi2 + 12 + 20 + read-write + + + + + GPR33 + GPR33 General Purpose Register + 0x84 + 32 + read-write + 0x7 + 0xFFFFFFFF + + + OCRAM2_TZ_EN + OCRAM2 TrustZone (TZ) enable. + 0 + 1 + read-write + + + OCRAM2_TZ_EN_0 + The TrustZone feature is disabled. Entire OCRAM2 space is available for all access types (secure/non-secure/user/supervisor). + 0 + + + OCRAM2_TZ_EN_1 + The TrustZone feature is enabled. Access to address in the range specified by [ENDADDR:STARTADDR] follows the execution mode access policy described in CSU chapter. + 0x1 + + + + + OCRAM2_TZ_ADDR + OCRAM2 TrustZone (TZ) start address + 1 + 7 + read-write + + + LOCK_OCRAM2_TZ_EN + Lock OCRAM2_TZ_EN field for changes + 16 + 1 + read-write + + + LOCK_OCRAM2_TZ_EN_0 + Field is not locked + 0 + + + LOCK_OCRAM2_TZ_EN_1 + Field is locked (read access only) + 0x1 + + + + + LOCK_OCRAM2_TZ_ADDR + Lock OCRAM2_TZ_ADDR field for changes + 17 + 7 + read-write + + + LOCK_OCRAM2_TZ_ADDR_0 + Field is not locked + 0 + + + LOCK_OCRAM2_TZ_ADDR_1 + Field is locked (read access only) + 0x1 + + + + + + + GPR34 + GPR34 General Purpose Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + SIP_TEST_MUX_BOOT_PIN_SEL + Boot Pin select in SIP_TEST_MUX + 0 + 8 + read-write + + + SIP_TEST_MUX_QSPI_SIP_EN + Enable SIP_TEST_MUX + 8 + 1 + read-write + + + SIP_TEST_MUX_QSPI_SIP_EN_0 + SIP_TEST_MUX is disabled + 0 + + + SIP_TEST_MUX_QSPI_SIP_EN_1 + SIP_TEST_MUX is enabled + 0x1 + + + + + + + + + FLEXRAM + FLEXRAM + FLEXRAM + 0x400B0000 + + 0 + 0x1000 + registers + + + FLEXRAM + 38 + + + + TCM_CTRL + TCM CRTL Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TCM_WWAIT_EN + TCM Write Wait Mode Enable + 0 + 1 + read-write + + + TCM_WWAIT_EN_0 + TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle. + 0 + + + TCM_WWAIT_EN_1 + TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles. + 0x1 + + + + + TCM_RWAIT_EN + TCM Read Wait Mode Enable + 1 + 1 + read-write + + + TCM_RWAIT_EN_0 + TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle. + 0 + + + TCM_RWAIT_EN_1 + TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles. + 0x1 + + + + + FORCE_CLK_ON + Force RAM Clock Always On + 2 + 1 + read-write + + + + + INT_STATUS + Interrupt Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITCM_ERR_STATUS + ITCM Access Error Status + 3 + 1 + read-write + oneToClear + + + ITCM_ERR_STATUS_0 + ITCM access error does not happen + 0 + + + ITCM_ERR_STATUS_1 + ITCM access error happens. + 0x1 + + + + + DTCM_ERR_STATUS + DTCM Access Error Status + 4 + 1 + read-write + oneToClear + + + DTCM_ERR_STATUS_0 + DTCM access error does not happen + 0 + + + DTCM_ERR_STATUS_1 + DTCM access error happens. + 0x1 + + + + + OCRAM_ERR_STATUS + OCRAM Access Error Status + 5 + 1 + read-write + oneToClear + + + OCRAM_ERR_STATUS_0 + OCRAM access error does not happen + 0 + + + OCRAM_ERR_STATUS_1 + OCRAM access error happens. + 0x1 + + + + + + + INT_STAT_EN + Interrupt Status Enable Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITCM_ERR_STAT_EN + ITCM Access Error Status Enable + 3 + 1 + read-write + + + ITCM_ERR_STAT_EN_0 + Masked + 0 + + + ITCM_ERR_STAT_EN_1 + Enabled + 0x1 + + + + + DTCM_ERR_STAT_EN + DTCM Access Error Status Enable + 4 + 1 + read-write + + + DTCM_ERR_STAT_EN_0 + Masked + 0 + + + DTCM_ERR_STAT_EN_1 + Enabled + 0x1 + + + + + OCRAM_ERR_STAT_EN + OCRAM Access Error Status Enable + 5 + 1 + read-write + + + OCRAM_ERR_STAT_EN_0 + Masked + 0 + + + OCRAM_ERR_STAT_EN_1 + Enabled + 0x1 + + + + + + + INT_SIG_EN + Interrupt Enable Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITCM_ERR_SIG_EN + ITCM Access Error Interrupt Enable + 3 + 1 + read-write + + + ITCM_ERR_SIG_EN_0 + Masked + 0 + + + ITCM_ERR_SIG_EN_1 + Enabled + 0x1 + + + + + DTCM_ERR_SIG_EN + DTCM Access Error Interrupt Enable + 4 + 1 + read-write + + + DTCM_ERR_SIG_EN_0 + Masked + 0 + + + DTCM_ERR_SIG_EN_1 + Enabled + 0x1 + + + + + OCRAM_ERR_SIG_EN + OCRAM Access Error Interrupt Enable + 5 + 1 + read-write + + + OCRAM_ERR_SIG_EN_0 + Masked + 0 + + + OCRAM_ERR_SIG_EN_1 + Enabled + 0x1 + + + + + + + + + EWM + EWM + EWM + 0x400B4000 + + 0 + 0x6 + registers + + + EWM + 94 + + + + CTRL + Control Register + 0 + 8 + read-write + 0 + 0xFF + + + EWMEN + EWM enable. + 0 + 1 + read-writeOnce + + + ASSIN + EWM_in's Assertion State Select. + 1 + 1 + read-writeOnce + + + INEN + Input Enable. + 2 + 1 + read-writeOnce + + + INTEN + Interrupt Enable. + 3 + 1 + read-write + + + + + SERV + Service Register + 0x1 + 8 + read-write + 0 + 0xFF + + + SERVICE + SERVICE + 0 + 8 + read-write + + + + + CMPL + Compare Low Register + 0x2 + 8 + read-writeOnce + 0 + 0xFF + + + COMPAREL + COMPAREL + 0 + 8 + read-writeOnce + + + + + CMPH + Compare High Register + 0x3 + 8 + read-writeOnce + 0xFF + 0xFF + + + COMPAREH + COMPAREH + 0 + 8 + read-writeOnce + + + + + CLKCTRL + Clock Control Register + 0x4 + 8 + read-write + 0 + 0xFF + + + CLKSEL + CLKSEL + 0 + 2 + read-writeOnce + + + + + CLKPRESCALER + Clock Prescaler Register + 0x5 + 8 + read-writeOnce + 0 + 0xFF + + + CLK_DIV + CLK_DIV + 0 + 8 + read-writeOnce + + + + + + + WDOG1 + WDOG + WDOG + WDOG + 0x400B8000 + + 0 + 0xA + registers + + + WDOG1 + 92 + + + + WCR + Watchdog Control Register + 0 + 16 + read-write + 0x30 + 0xFFFF + + + WDZST + WDZST + 0 + 1 + read-write + + + WDZST_0 + Continue timer operation (Default). + 0 + + + WDZST_1 + Suspend the watchdog timer. + 0x1 + + + + + WDBG + WDBG + 1 + 1 + read-write + + + WDBG_0 + Continue WDOG timer operation (Default). + 0 + + + WDBG_1 + Suspend the watchdog timer. + 0x1 + + + + + WDE + WDE + 2 + 1 + read-write + + + WDE_0 + Disable the Watchdog (Default). + 0 + + + WDE_1 + Enable the Watchdog. + 0x1 + + + + + WDT + WDT + 3 + 1 + read-write + + + WDT_0 + No effect on WDOG_B (Default). + 0 + + + WDT_1 + Assert WDOG_B upon a Watchdog Time-out event. + 0x1 + + + + + SRS + SRS + 4 + 1 + read-write + + + SRS_0 + Assert system reset signal. + 0 + + + SRS_1 + No effect on the system (Default). + 0x1 + + + + + WDA + WDA + 5 + 1 + read-write + + + WDA_0 + Assert WDOG_B output. + 0 + + + WDA_1 + No effect on system (Default). + 0x1 + + + + + SRE + software reset extension, an option way to generate software reset + 6 + 1 + read-write + + + SRE_0 + using original way to generate software reset (default) + 0 + + + SRE_1 + using new way to generate software reset. + 0x1 + + + + + WDW + WDW + 7 + 1 + read-write + + + WDW_0 + Continue WDOG timer operation (Default). + 0 + + + WDW_1 + Suspend WDOG timer operation. + 0x1 + + + + + WT + WT + 8 + 8 + read-write + + + WT_0 + - 0.5 Seconds (Default). + 0 + + + WT_1 + - 1.0 Seconds. + 0x1 + + + WT_2 + - 1.5 Seconds. + 0x2 + + + WT_3 + - 2.0 Seconds. + 0x3 + + + WT_255 + - 128 Seconds. + 0xFF + + + + + + + WSR + Watchdog Service Register + 0x2 + 16 + read-write + 0 + 0xFFFF + + + WSR + WSR + 0 + 16 + read-write + + + WSR_21845 + Write to the Watchdog Service Register (WDOG_WSR). + 0x5555 + + + WSR_43690 + Write to the Watchdog Service Register (WDOG_WSR). + 0xAAAA + + + + + + + WRSR + Watchdog Reset Status Register + 0x4 + 16 + read-only + 0 + 0xFFFF + + + SFTW + SFTW + 0 + 1 + read-only + + + SFTW_0 + Reset is not the result of a software reset. + 0 + + + SFTW_1 + Reset is the result of a software reset. + 0x1 + + + + + TOUT + TOUT + 1 + 1 + read-only + + + TOUT_0 + Reset is not the result of a WDOG timeout. + 0 + + + TOUT_1 + Reset is the result of a WDOG timeout. + 0x1 + + + + + POR + POR + 4 + 1 + read-only + + + POR_0 + Reset is not the result of a power on reset. + 0 + + + POR_1 + Reset is the result of a power on reset. + 0x1 + + + + + + + WICR + Watchdog Interrupt Control Register + 0x6 + 16 + read-write + 0x4 + 0xFFFF + + + WICT + WICT + 0 + 8 + read-write + + + WICT_0 + WICT[7:0] = Time duration between interrupt and time-out is 0 seconds. + 0 + + + WICT_1 + WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds. + 0x1 + + + WICT_4 + WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default). + 0x4 + + + WICT_255 + WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. + 0xFF + + + + + WTIS + WTIS + 14 + 1 + read-write + oneToClear + + + WTIS_0 + No interrupt has occurred (Default). + 0 + + + WTIS_1 + Interrupt has occurred + 0x1 + + + + + WIE + WIE + 15 + 1 + read-write + + + WIE_0 + Disable Interrupt (Default). + 0 + + + WIE_1 + Enable Interrupt. + 0x1 + + + + + + + WMCR + Watchdog Miscellaneous Control Register + 0x8 + 16 + read-write + 0x1 + 0xFFFF + + + PDE + PDE + 0 + 1 + read-write + + + PDE_0 + Power Down Counter of WDOG is disabled. + 0 + + + PDE_1 + Power Down Counter of WDOG is enabled (Default). + 0x1 + + + + + + + + + WDOG2 + WDOG + WDOG + 0x400D0000 + + 0 + 0xA + registers + + + WDOG2 + 45 + + + + RTWDOG + WDOG + RTWDOG + 0x400BC000 + + 0 + 0x10 + registers + + + RTWDOG + 93 + + + + CS + Watchdog Control and Status Register + 0 + 32 + read-write + 0x2980 + 0xFFFFFFFF + + + STOP + Stop Enable + 0 + 1 + read-write + + + STOP_0 + Watchdog disabled in chip stop mode. + 0 + + + STOP_1 + Watchdog enabled in chip stop mode. + 0x1 + + + + + WAIT + Wait Enable + 1 + 1 + read-write + + + WAIT_0 + Watchdog disabled in chip wait mode. + 0 + + + WAIT_1 + Watchdog enabled in chip wait mode. + 0x1 + + + + + DBG + Debug Enable + 2 + 1 + read-write + + + DBG_0 + Watchdog disabled in chip debug mode. + 0 + + + DBG_1 + Watchdog enabled in chip debug mode. + 0x1 + + + + + TST + Watchdog Test + 3 + 2 + read-write + + + TST_0 + Watchdog test mode disabled. + 0 + + + TST_1 + Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. + 0x1 + + + TST_2 + Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. + 0x2 + + + TST_3 + Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. + 0x3 + + + + + UPDATE + Allow updates + 5 + 1 + read-write + + + UPDATE_0 + Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. + 0 + + + UPDATE_1 + Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. + 0x1 + + + + + INT + Watchdog Interrupt + 6 + 1 + read-write + + + INT_0 + Watchdog interrupts are disabled. Watchdog resets are not delayed. + 0 + + + INT_1 + Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. + 0x1 + + + + + EN + Watchdog Enable + 7 + 1 + read-write + + + EN_0 + Watchdog disabled. + 0 + + + EN_1 + Watchdog enabled. + 0x1 + + + + + CLK + Watchdog Clock + 8 + 2 + read-write + + + CLK_0 + Bus clock + 0 + + + CLK_1 + LPO clock + 0x1 + + + CLK_2 + INTCLK (internal clock) + 0x2 + + + CLK_3 + ERCLK (external reference clock) + 0x3 + + + + + RCS + Reconfiguration Success + 10 + 1 + read-only + + + RCS_0 + Reconfiguring WDOG. + 0 + + + RCS_1 + Reconfiguration is successful. + 0x1 + + + + + ULK + Unlock status + 11 + 1 + read-only + + + ULK_0 + WDOG is locked. + 0 + + + ULK_1 + WDOG is unlocked. + 0x1 + + + + + PRES + Watchdog prescaler + 12 + 1 + read-write + + + PRES_0 + 256 prescaler disabled. + 0 + + + PRES_1 + 256 prescaler enabled. + 0x1 + + + + + CMD32EN + Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words + 13 + 1 + read-write + + + CMD32EN_0 + Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. + 0 + + + CMD32EN_1 + Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. + 0x1 + + + + + FLG + Watchdog Interrupt Flag + 14 + 1 + read-write + oneToClear + + + FLG_0 + No interrupt occurred. + 0 + + + FLG_1 + An interrupt occurred. + 0x1 + + + + + WIN + Watchdog Window + 15 + 1 + read-write + + + WIN_0 + Window mode disabled. + 0 + + + WIN_1 + Window mode enabled. + 0x1 + + + + + + + CNT + Watchdog Counter Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CNTLOW + Low byte of the Watchdog Counter + 0 + 8 + read-write + + + CNTHIGH + High byte of the Watchdog Counter + 8 + 8 + read-write + + + + + TOVAL + Watchdog Timeout Value Register + 0x8 + 32 + read-write + 0x400 + 0xFFFFFFFF + + + TOVALLOW + Low byte of the timeout value + 0 + 8 + read-write + + + TOVALHIGH + High byte of the timeout value + 8 + 8 + read-write + + + + + WIN + Watchdog Window Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + WINLOW + Low byte of Watchdog Window + 0 + 8 + read-write + + + WINHIGH + High byte of Watchdog Window + 8 + 8 + read-write + + + + + + + ADC1 + Analog-to-Digital Converter + ADC + ADC1_ + ADC + 0x400C4000 + + 0 + 0x5C + registers + + + ADC1 + 67 + + + + HC0 + Control register for hardware triggers + 0 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + ADCH_16 + External channel selection from ADC_ETC + 0x10 + + + ADCH_25 + VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + 0x19 + + + ADCH_31 + Conversion Disabled. Hardware Triggers will not initiate any conversion. + 0x1F + + + + + AIEN + Conversion Complete Interrupt Enable/Disable Control + 7 + 1 + read-write + + + AIEN_0 + Conversion complete interrupt disabled + 0 + + + AIEN_1 + Conversion complete interrupt enabled + 0x1 + + + + + + + 7 + 0x4 + 1,2,3,4,5,6,7 + HC%s + Control register for hardware triggers + 0x4 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + ADCH + Input Channel Select + 0 + 5 + read-write + + + ADCH_16 + External channel selection from ADC_ETC + 0x10 + + + ADCH_25 + VREFSH = internal channel, for ADC self-test, hard connected to VRH internally + 0x19 + + + ADCH_31 + Conversion Disabled. Hardware Triggers will not initiate any conversion. + 0x1F + + + + + AIEN + Conversion Complete Interrupt Enable/Disable Control + 7 + 1 + read-write + + + AIEN_0 + Conversion complete interrupt disabled + 0 + + + AIEN_1 + Conversion complete interrupt enabled + 0x1 + + + + + + + HS + Status register for HW triggers + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + COCO0 + Conversion Complete Flag + 0 + 1 + read-only + + + + + R0 + Data result register for HW triggers + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + CDATA + Data (result of an ADC conversion) + 0 + 12 + read-only + + + + + 7 + 0x4 + 1,2,3,4,5,6,7 + R%s + Data result register for HW triggers + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + CDATA + Data (result of an ADC conversion) + 0 + 12 + read-only + + + + + CFG + Configuration register + 0x44 + 32 + read-write + 0x200 + 0xFFFFFFFF + + + ADICLK + Input Clock Select + 0 + 2 + read-write + + + ADICLK_0 + IPG clock + 0 + + + ADICLK_1 + IPG clock divided by 2 + 0x1 + + + ADICLK_3 + Asynchronous clock (ADACK) + 0x3 + + + + + MODE + Conversion Mode Selection + 2 + 2 + read-write + + + MODE_0 + 8-bit conversion + 0 + + + MODE_1 + 10-bit conversion + 0x1 + + + MODE_2 + 12-bit conversion + 0x2 + + + + + ADLSMP + Long Sample Time Configuration + 4 + 1 + read-write + + + ADLSMP_0 + Short sample mode. + 0 + + + ADLSMP_1 + Long sample mode. + 0x1 + + + + + ADIV + Clock Divide Select + 5 + 2 + read-write + + + ADIV_0 + Input clock + 0 + + + ADIV_1 + Input clock / 2 + 0x1 + + + ADIV_2 + Input clock / 4 + 0x2 + + + ADIV_3 + Input clock / 8 + 0x3 + + + + + ADLPC + Low-Power Configuration + 7 + 1 + read-write + + + ADLPC_0 + ADC hard block not in low power mode. + 0 + + + ADLPC_1 + ADC hard block in low power mode. + 0x1 + + + + + ADSTS + Defines the sample time duration + 8 + 2 + read-write + + + ADSTS_0 + Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b + 0 + + + ADSTS_1 + Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b + 0x1 + + + ADSTS_2 + Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b + 0x2 + + + ADSTS_3 + Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b + 0x3 + + + + + ADHSC + High Speed Configuration + 10 + 1 + read-write + + + ADHSC_0 + Normal conversion selected. + 0 + + + ADHSC_1 + High speed conversion selected. + 0x1 + + + + + REFSEL + Voltage Reference Selection + 11 + 2 + read-write + + + REFSEL_0 + Selects VREFH/VREFL as reference voltage. + 0 + + + + + ADTRG + Conversion Trigger Select + 13 + 1 + read-write + + + ADTRG_0 + Software trigger selected + 0 + + + ADTRG_1 + Hardware trigger selected + 0x1 + + + + + AVGS + Hardware Average select + 14 + 2 + read-write + + + AVGS_0 + 4 samples averaged + 0 + + + AVGS_1 + 8 samples averaged + 0x1 + + + AVGS_2 + 16 samples averaged + 0x2 + + + AVGS_3 + 32 samples averaged + 0x3 + + + + + OVWREN + Data Overwrite Enable + 16 + 1 + read-write + + + OVWREN_0 + Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data. + 0 + + + OVWREN_1 + Enable the overwriting. + 0x1 + + + + + + + GC + General control register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADACKEN + Asynchronous clock output enable + 0 + 1 + read-write + + + ADACKEN_0 + Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. + 0 + + + ADACKEN_1 + Asynchronous clock and clock output enabled regardless of the state of the ADC + 0x1 + + + + + DMAEN + DMA Enable + 1 + 1 + read-write + + + DMAEN_0 + DMA disabled (default) + 0 + + + DMAEN_1 + DMA enabled + 0x1 + + + + + ACREN + Compare Function Range Enable + 2 + 1 + read-write + + + ACREN_0 + Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared. + 0 + + + ACREN_1 + Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared. + 0x1 + + + + + ACFGT + Compare Function Greater Than Enable + 3 + 1 + read-write + + + ACFGT_0 + Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive" functionality based on the values placed in the ADC_CV register. + 0 + + + ACFGT_1 + Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive" functionality based on the values placed in the ADC_CV registers. + 0x1 + + + + + ACFE + Compare Function Enable + 4 + 1 + read-write + + + ACFE_0 + Compare function disabled + 0 + + + ACFE_1 + Compare function enabled + 0x1 + + + + + AVGE + Hardware average enable + 5 + 1 + read-write + + + AVGE_0 + Hardware average function disabled + 0 + + + AVGE_1 + Hardware average function enabled + 0x1 + + + + + ADCO + Continuous Conversion Enable + 6 + 1 + read-write + + + ADCO_0 + One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + 0 + + + ADCO_1 + Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. + 0x1 + + + + + CAL + Calibration + 7 + 1 + read-write + + + + + GS + General status register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + ADACT + Conversion Active + 0 + 1 + read-only + + + ADACT_0 + Conversion not in progress. + 0 + + + ADACT_1 + Conversion in progress. + 0x1 + + + + + CALF + Calibration Failed Flag + 1 + 1 + read-write + oneToClear + + + CALF_0 + Calibration completed normally. + 0 + + + CALF_1 + Calibration failed. ADC accuracy specifications are not guaranteed. + 0x1 + + + + + AWKST + Asynchronous wakeup interrupt status + 2 + 1 + read-write + oneToClear + + + AWKST_0 + No asynchronous interrupt. + 0 + + + AWKST_1 + Asynchronous wake up interrupt occurred in stop mode. + 0x1 + + + + + + + CV + Compare value register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + CV1 + Compare Value 1 + 0 + 12 + read-write + + + CV2 + Compare Value 2 + 16 + 12 + read-write + + + + + OFS + Offset correction value register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFS + Offset value + 0 + 12 + read-write + + + SIGN + Sign bit + 12 + 1 + read-write + + + SIGN_0 + The offset value is added with the raw result + 0 + + + SIGN_1 + The offset value is subtracted from the raw converted value + 0x1 + + + + + + + CAL + Calibration value register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + CAL_CODE + Calibration Result Value + 0 + 4 + read-write + + + + + + + ADC2 + Analog-to-Digital Converter + ADC + ADC2_ + 0x400C8000 + + 0 + 0x5C + registers + + + ADC2 + 68 + + + + TRNG + TRNG + TRNG + 0x400CC000 + + 0 + 0xF8 + registers + + + TRNG + 53 + + + + MCTL + Miscellaneous Control Register + 0 + 32 + read-write + 0x12001 + 0xFFFFFFFF + + + SAMP_MODE + Sample Mode + 0 + 2 + read-write + + + SAMP_MODE_0 + use Von Neumann data into both Entropy shifter and Statistical Checker + 0 + + + SAMP_MODE_1 + use raw data into both Entropy shifter and Statistical Checker + 0x1 + + + SAMP_MODE_2 + use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker + 0x2 + + + SAMP_MODE_3 + undefined/reserved. + 0x3 + + + + + OSC_DIV + Oscillator Divide + 2 + 2 + read-write + + + OSC_DIV_0 + use ring oscillator with no divide + 0 + + + OSC_DIV_1 + use ring oscillator divided-by-2 + 0x1 + + + OSC_DIV_2 + use ring oscillator divided-by-4 + 0x2 + + + OSC_DIV_3 + use ring oscillator divided-by-8 + 0x3 + + + + + UNUSED4 + This bit is unused. Always reads zero. + 4 + 1 + read-only + + + UNUSED5 + This bit is unused. Always reads zero. + 5 + 1 + read-only + + + RST_DEF + Reset Defaults + 6 + 1 + write-only + + + FOR_SCLK + Force System Clock + 7 + 1 + read-write + + + FCT_FAIL + Read only: Frequency Count Fail + 8 + 1 + read-only + + + FCT_VAL + Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT. + 9 + 1 + read-only + + + ENT_VAL + Read only: Entropy Valid + 10 + 1 + read-only + + + TST_OUT + Read only: Test point inside ring oscillator. + 11 + 1 + read-only + + + ERR + Read: Error status + 12 + 1 + read-write + oneToClear + + + TSTOP_OK + TRNG_OK_TO_STOP + 13 + 1 + read-only + + + LRUN_CONT + Long run count continues between entropy generations + 14 + 1 + read-write + + + PRGM + Programming Mode Select + 16 + 1 + read-write + + + + + SCMISC + Statistical Check Miscellaneous Register + 0x4 + 32 + read-write + 0x10022 + 0xFFFFFFFF + + + LRUN_MAX + LONG RUN MAX LIMIT + 0 + 8 + read-write + + + RTY_CT + RETRY COUNT + 16 + 4 + read-write + + + + + PKRRNG + Poker Range Register + 0x8 + 32 + read-write + 0x9A3 + 0xFFFFFFFF + + + PKR_RNG + Poker Range + 0 + 16 + read-write + + + + + PKRMAX + Poker Maximum Limit Register + MAX_SQ + 0xC + 32 + read-write + 0x6920 + 0xFFFFFFFF + + + PKR_MAX + Poker Maximum Limit. + 0 + 24 + read-write + + + + + PKRSQ + Poker Square Calculation Result Register + MAX_SQ + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_SQ + Poker Square Calculation Result. + 0 + 24 + read-only + + + + + SDCTL + Seed Control Register + 0x10 + 32 + read-write + 0xC8009C4 + 0xFFFFFFFF + + + SAMP_SIZE + Sample Size + 0 + 16 + read-write + + + ENT_DLY + Entropy Delay + 16 + 16 + read-write + + + + + SBLIM + Sparse Bit Limit Register + SBLIM_TOTSAM + 0x14 + 32 + read-write + 0x3F + 0xFFFFFFFF + + + SB_LIM + Sparse Bit Limit + 0 + 10 + read-write + + + + + TOTSAM + Total Samples Register + SBLIM_TOTSAM + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + TOT_SAM + Total Samples + 0 + 20 + read-only + + + + + FRQMIN + Frequency Count Minimum Limit Register + 0x18 + 32 + read-write + 0x640 + 0xFFFFFFFF + + + FRQ_MIN + Frequency Count Minimum Limit + 0 + 22 + read-write + + + + + FRQCNT + Frequency Count Register + MAX_CNT + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + FRQ_CT + Frequency Count + 0 + 22 + read-only + + + + + FRQMAX + Frequency Count Maximum Limit Register + MAX_CNT + 0x1C + 32 + read-write + 0x6400 + 0xFFFFFFFF + + + FRQ_MAX + Frequency Counter Maximum Limit + 0 + 22 + read-write + + + + + SCMC + Statistical Check Monobit Count Register + SCML_MC + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + MONO_CT + Monobit Count + 0 + 16 + read-only + + + + + SCML + Statistical Check Monobit Limit Register + SCML_MC + 0x20 + 32 + read-write + 0x10C0568 + 0xFFFFFFFF + + + MONO_MAX + Monobit Maximum Limit + 0 + 16 + read-write + + + MONO_RNG + Monobit Range + 16 + 16 + read-write + + + + + SCR1C + Statistical Check Run Length 1 Count Register + SCR1L_1C + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + R1_0_CT + Runs of Zero, Length 1 Count + 0 + 15 + read-only + + + R1_1_CT + Runs of One, Length 1 Count + 16 + 15 + read-only + + + + + SCR1L + Statistical Check Run Length 1 Limit Register + SCR1L_1C + 0x24 + 32 + read-write + 0xB20195 + 0xFFFFFFFF + + + RUN1_MAX + Run Length 1 Maximum Limit + 0 + 15 + read-write + + + RUN1_RNG + Run Length 1 Range + 16 + 15 + read-write + + + + + SCR2C + Statistical Check Run Length 2 Count Register + SCR2L_2C + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + R2_0_CT + Runs of Zero, Length 2 Count + 0 + 14 + read-only + + + R2_1_CT + Runs of One, Length 2 Count + 16 + 14 + read-only + + + + + SCR2L + Statistical Check Run Length 2 Limit Register + SCR2L_2C + 0x28 + 32 + read-write + 0x7A00DC + 0xFFFFFFFF + + + RUN2_MAX + Run Length 2 Maximum Limit + 0 + 14 + read-write + + + RUN2_RNG + Run Length 2 Range + 16 + 14 + read-write + + + + + SCR3C + Statistical Check Run Length 3 Count Register + SCR3L_3C + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + R3_0_CT + Runs of Zeroes, Length 3 Count + 0 + 13 + read-only + + + R3_1_CT + Runs of Ones, Length 3 Count + 16 + 13 + read-only + + + + + SCR3L + Statistical Check Run Length 3 Limit Register + SCR3L_3C + 0x2C + 32 + read-write + 0x58007D + 0xFFFFFFFF + + + RUN3_MAX + Run Length 3 Maximum Limit + 0 + 13 + read-write + + + RUN3_RNG + Run Length 3 Range + 16 + 13 + read-write + + + + + SCR4C + Statistical Check Run Length 4 Count Register + SCR4L_4C + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + R4_0_CT + Runs of Zero, Length 4 Count + 0 + 12 + read-only + + + R4_1_CT + Runs of One, Length 4 Count + 16 + 12 + read-only + + + + + SCR4L + Statistical Check Run Length 4 Limit Register + SCR4L_4C + 0x30 + 32 + read-write + 0x40004B + 0xFFFFFFFF + + + RUN4_MAX + Run Length 4 Maximum Limit + 0 + 12 + read-write + + + RUN4_RNG + Run Length 4 Range + 16 + 12 + read-write + + + + + SCR5C + Statistical Check Run Length 5 Count Register + SCR5L_5C + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + R5_0_CT + Runs of Zero, Length 5 Count + 0 + 11 + read-only + + + R5_1_CT + Runs of One, Length 5 Count + 16 + 11 + read-only + + + + + SCR5L + Statistical Check Run Length 5 Limit Register + SCR5L_5C + 0x34 + 32 + read-write + 0x2E002F + 0xFFFFFFFF + + + RUN5_MAX + Run Length 5 Maximum Limit + 0 + 11 + read-write + + + RUN5_RNG + Run Length 5 Range + 16 + 11 + read-write + + + + + SCR6PC + Statistical Check Run Length 6+ Count Register + SCR6PL_PC + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + R6P_0_CT + Runs of Zero, Length 6+ Count + 0 + 11 + read-only + + + R6P_1_CT + Runs of One, Length 6+ Count + 16 + 11 + read-only + + + + + SCR6PL + Statistical Check Run Length 6+ Limit Register + SCR6PL_PC + 0x38 + 32 + read-write + 0x2E002F + 0xFFFFFFFF + + + RUN6P_MAX + Run Length 6+ Maximum Limit + 0 + 11 + read-write + + + RUN6P_RNG + Run Length 6+ Range + 16 + 11 + read-write + + + + + STATUS + Status Register + 0x3C + 32 + read-only + 0 + 0xFFFFFFFF + + + TF1BR0 + Test Fail, 1-Bit Run, Sampling 0s. If TF1BR0=1, the 1-Bit Run, Sampling 0s Test has failed. + 0 + 1 + read-only + + + TF1BR1 + Test Fail, 1-Bit Run, Sampling 1s. If TF1BR1=1, the 1-Bit Run, Sampling 1s Test has failed. + 1 + 1 + read-only + + + TF2BR0 + Test Fail, 2-Bit Run, Sampling 0s. If TF2BR0=1, the 2-Bit Run, Sampling 0s Test has failed. + 2 + 1 + read-only + + + TF2BR1 + Test Fail, 2-Bit Run, Sampling 1s. If TF2BR1=1, the 2-Bit Run, Sampling 1s Test has failed. + 3 + 1 + read-only + + + TF3BR0 + Test Fail, 3-Bit Run, Sampling 0s. If TF3BR0=1, the 3-Bit Run, Sampling 0s Test has failed. + 4 + 1 + read-only + + + TF3BR1 + Test Fail, 3-Bit Run, Sampling 1s. If TF3BR1=1, the 3-Bit Run, Sampling 1s Test has failed. + 5 + 1 + read-only + + + TF4BR0 + Test Fail, 4-Bit Run, Sampling 0s. If TF4BR0=1, the 4-Bit Run, Sampling 0s Test has failed. + 6 + 1 + read-only + + + TF4BR1 + Test Fail, 4-Bit Run, Sampling 1s. If TF4BR1=1, the 4-Bit Run, Sampling 1s Test has failed. + 7 + 1 + read-only + + + TF5BR0 + Test Fail, 5-Bit Run, Sampling 0s. If TF5BR0=1, the 5-Bit Run, Sampling 0s Test has failed. + 8 + 1 + read-only + + + TF5BR1 + Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed. + 9 + 1 + read-only + + + TF6PBR0 + Test Fail, 6 Plus Bit Run, Sampling 0s + 10 + 1 + read-only + + + TF6PBR1 + Test Fail, 6 Plus Bit Run, Sampling 1s + 11 + 1 + read-only + + + TFSB + Test Fail, Sparse Bit. If TFSB=1, the Sparse Bit Test has failed. + 12 + 1 + read-only + + + TFLR + Test Fail, Long Run. If TFLR=1, the Long Run Test has failed. + 13 + 1 + read-only + + + TFP + Test Fail, Poker. If TFP=1, the Poker Test has failed. + 14 + 1 + read-only + + + TFMB + Test Fail, Mono Bit. If TFMB=1, the Mono Bit Test has failed. + 15 + 1 + read-only + + + RETRY_CT + RETRY COUNT + 16 + 4 + read-only + + + + + 16 + 0x4 + ENT[%s] + Entropy Read Register + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + ENT + Entropy Value + 0 + 32 + read-only + + + + + PKRCNT10 + Statistical Check Poker Count 1 and 0 Register + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_0_CT + Poker 0h Count + 0 + 16 + read-only + + + PKR_1_CT + Poker 1h Count + 16 + 16 + read-only + + + + + PKRCNT32 + Statistical Check Poker Count 3 and 2 Register + 0x84 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_2_CT + Poker 2h Count + 0 + 16 + read-only + + + PKR_3_CT + Poker 3h Count + 16 + 16 + read-only + + + + + PKRCNT54 + Statistical Check Poker Count 5 and 4 Register + 0x88 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_4_CT + Poker 4h Count + 0 + 16 + read-only + + + PKR_5_CT + Poker 5h Count + 16 + 16 + read-only + + + + + PKRCNT76 + Statistical Check Poker Count 7 and 6 Register + 0x8C + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_6_CT + Poker 6h Count + 0 + 16 + read-only + + + PKR_7_CT + Poker 7h Count + 16 + 16 + read-only + + + + + PKRCNT98 + Statistical Check Poker Count 9 and 8 Register + 0x90 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_8_CT + Poker 8h Count + 0 + 16 + read-only + + + PKR_9_CT + Poker 9h Count + 16 + 16 + read-only + + + + + PKRCNTBA + Statistical Check Poker Count B and A Register + 0x94 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_A_CT + Poker Ah Count + 0 + 16 + read-only + + + PKR_B_CT + Poker Bh Count + 16 + 16 + read-only + + + + + PKRCNTDC + Statistical Check Poker Count D and C Register + 0x98 + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_C_CT + Poker Ch Count + 0 + 16 + read-only + + + PKR_D_CT + Poker Dh Count + 16 + 16 + read-only + + + + + PKRCNTFE + Statistical Check Poker Count F and E Register + 0x9C + 32 + read-only + 0 + 0xFFFFFFFF + + + PKR_E_CT + Poker Eh Count + 0 + 16 + read-only + + + PKR_F_CT + Poker Fh Count + 16 + 16 + read-only + + + + + SEC_CFG + Security Configuration Register + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + UNUSED0 + This bit is unused. Ignore. + 0 + 1 + read-write + + + NO_PRGM + If set, the TRNG registers cannot be programmed + 1 + 1 + read-write + + + NO_PRGM_0 + Programability of registers controlled only by the Miscellaneous Control Register's access mode bit. + 0 + + + NO_PRGM_1 + Overides Miscellaneous Control Register access mode and prevents TRNG register programming. + 0x1 + + + + + UNUSED2 + This bit is unused. Ignore. + 2 + 1 + read-write + + + + + INT_CTRL + Interrupt Control Register + 0xA4 + 32 + read-write + 0x7 + 0xFFFFFFFF + + + HW_ERR + Bit position that can be cleared if corresponding bit of INT_STATUS register has been asserted. + 0 + 1 + read-write + + + HW_ERR_0 + Corresponding bit of INT_STATUS register cleared. + 0 + + + HW_ERR_1 + Corresponding bit of INT_STATUS register active. + 0x1 + + + + + ENT_VAL + Same behavior as bit 0 of this register. + 1 + 1 + read-write + + + ENT_VAL_0 + Same behavior as bit 0 of this register. + 0 + + + ENT_VAL_1 + Same behavior as bit 0 of this register. + 0x1 + + + + + FRQ_CT_FAIL + Same behavior as bit 0 of this register. + 2 + 1 + read-write + + + FRQ_CT_FAIL_0 + Same behavior as bit 0 of this register. + 0 + + + FRQ_CT_FAIL_1 + Same behavior as bit 0 of this register. + 0x1 + + + + + + + INT_MASK + Mask Register + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + HW_ERR + Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. + 0 + 1 + read-write + + + HW_ERR_0 + Corresponding interrupt of INT_STATUS is masked. + 0 + + + HW_ERR_1 + Corresponding bit of INT_STATUS is active. + 0x1 + + + + + ENT_VAL + Same behavior as bit 0 of this register. + 1 + 1 + read-write + + + ENT_VAL_0 + Same behavior as bit 0 of this register. + 0 + + + ENT_VAL_1 + Same behavior as bit 0 of this register. + 0x1 + + + + + FRQ_CT_FAIL + Same behavior as bit 0 of this register. + 2 + 1 + read-write + + + FRQ_CT_FAIL_0 + Same behavior as bit 0 of this register. + 0 + + + FRQ_CT_FAIL_1 + Same behavior as bit 0 of this register. + 0x1 + + + + + + + INT_STATUS + Interrupt Status Register + 0xAC + 32 + read-only + 0 + 0xFFFFFFFF + + + HW_ERR + Read: Error status + 0 + 1 + read-only + + + HW_ERR_0 + no error + 0 + + + HW_ERR_1 + error detected. + 0x1 + + + + + ENT_VAL + Read only: Entropy Valid + 1 + 1 + read-only + + + ENT_VAL_0 + Busy generation entropy. Any value read is invalid. + 0 + + + ENT_VAL_1 + TRNG can be stopped and entropy is valid if read. + 0x1 + + + + + FRQ_CT_FAIL + Read only: Frequency Count Fail + 2 + 1 + read-only + + + FRQ_CT_FAIL_0 + No hardware nor self test frequency errors. + 0 + + + FRQ_CT_FAIL_1 + The frequency counter has detected a failure. + 0x1 + + + + + + + VID1 + Version ID Register (MS) + 0xF0 + 32 + read-only + 0x300301 + 0xFFFFFFFF + + + MIN_REV + Shows the IP's Minor revision of the TRNG. + 0 + 8 + read-only + + + MIN_REV_0 + Minor revision number for TRNG. + 0 + + + + + MAJ_REV + Shows the IP's Major revision of the TRNG. + 8 + 8 + read-only + + + MAJ_REV_1 + Major revision number for TRNG. + 0x1 + + + + + IP_ID + Shows the IP ID. + 16 + 16 + read-only + + + IP_ID_48 + ID for TRNG. + 0x30 + + + + + + + VID2 + Version ID Register (LS) + 0xF4 + 32 + read-only + 0 + 0xFFFFFFFF + + + CONFIG_OPT + Shows the IP's Configuaration options for the TRNG. + 0 + 8 + read-only + + + CONFIG_OPT_0 + TRNG_CONFIG_OPT for TRNG. + 0 + + + + + ECO_REV + Shows the IP's ECO revision of the TRNG. + 8 + 8 + read-only + + + ECO_REV_0 + TRNG_ECO_REV for TRNG. + 0 + + + + + INTG_OPT + Shows the integration options for the TRNG. + 16 + 8 + read-only + + + INTG_OPT_0 + INTG_OPT for TRNG. + 0 + + + + + ERA + Shows the compile options for the TRNG. + 24 + 8 + read-only + + + ERA_0 + COMPILE_OPT for TRNG. + 0 + + + + + + + + + SNVS + SNVS + SNVS + 0x400D4000 + + 0 + 0x10000 + registers + + + SNVS_HP_WRAPPER + 46 + + + SNVS_HP_WRAPPER_TZ + 47 + + + SNVS_LP_WRAPPER + 48 + + + + HPLR + SNVS_HP Lock Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ZMK_WSL + Zeroizable Master Key Write Soft Lock When set, prevents any writes (software and hardware) to the ZMK registers and the ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR + 0 + 1 + read-write + + + ZMK_WSL_0 + Write access is allowed + 0 + + + ZMK_WSL_1 + Write access is not allowed + 0x1 + + + + + ZMK_RSL + Zeroizable Master Key Read Soft Lock When set, prevents any software reads to the ZMK Registers and ZMK_ECC_VALUE field of the LPMKCR + 1 + 1 + read-write + + + ZMK_RSL_0 + Read access is allowed (only in software Programming mode) + 0 + + + ZMK_RSL_1 + Read access is not allowed + 0x1 + + + + + SRTC_SL + Secure Real Time Counter Soft Lock When set, prevents any writes to the SRTC Registers, SRTC_ENV, and SRTC_INV_EN bits + 2 + 1 + read-write + + + SRTC_SL_0 + Write access is allowed + 0 + + + SRTC_SL_1 + Write access is not allowed + 0x1 + + + + + LPCALB_SL + LP Calibration Soft Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN) + 3 + 1 + read-write + + + LPCALB_SL_0 + Write access is allowed + 0 + + + LPCALB_SL_1 + Write access is not allowed + 0x1 + + + + + MC_SL + Monotonic Counter Soft Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit + 4 + 1 + read-write + + + MC_SL_0 + Write access (increment) is allowed + 0 + + + MC_SL_1 + Write access (increment) is not allowed + 0x1 + + + + + GPR_SL + General Purpose Register Soft Lock When set, prevents any writes to the GPR + 5 + 1 + read-write + + + GPR_SL_0 + Write access is allowed + 0 + + + GPR_SL_1 + Write access is not allowed + 0x1 + + + + + LPSVCR_SL + LP Security Violation Control Register Soft Lock When set, prevents any writes to the LPSVCR + 6 + 1 + read-write + + + LPSVCR_SL_0 + Write access is allowed + 0 + + + LPSVCR_SL_1 + Write access is not allowed + 0x1 + + + + + LPTDCR_SL + LP Tamper Detectors Configuration Register Soft Lock When set, prevents any writes to the LPTDCR + 8 + 1 + read-write + + + LPTDCR_SL_0 + Write access is allowed + 0 + + + LPTDCR_SL_1 + Write access is not allowed + 0x1 + + + + + MKS_SL + Master Key Select Soft Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LPMKCR + 9 + 1 + read-write + + + MKS_SL_0 + Write access is allowed + 0 + + + MKS_SL_1 + Write access is not allowed + 0x1 + + + + + HPSVCR_L + HP Security Violation Control Register Lock When set, prevents any writes to the HPSVCR + 16 + 1 + read-write + + + HPSVCR_L_0 + Write access is allowed + 0 + + + HPSVCR_L_1 + Write access is not allowed + 0x1 + + + + + HPSICR_L + HP Security Interrupt Control Register Lock When set, prevents any writes to the HPSICR + 17 + 1 + read-write + + + HPSICR_L_0 + Write access is allowed + 0 + + + HPSICR_L_1 + Write access is not allowed + 0x1 + + + + + HAC_L + High Assurance Counter Lock When set, prevents any writes to HPHACIVR, HPHACR, and HAC_EN bit of HPCOMR + 18 + 1 + read-write + + + HAC_L_0 + Write access is allowed + 0 + + + HAC_L_1 + Write access is not allowed + 0x1 + + + + + + + HPCOMR + SNVS_HP Command Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSM_ST + SSM State Transition Transition state of the system security monitor + 0 + 1 + write-only + + + SSM_ST_DIS + SSM Secure to Trusted State Transition Disable When set, disables the SSM transition from secure to trusted state + 1 + 1 + read-write + + + SSM_ST_DIS_0 + Secure to Trusted State transition is enabled + 0 + + + SSM_ST_DIS_1 + Secure to Trusted State transition is disabled + 0x1 + + + + + SSM_SFNS_DIS + SSM Soft Fail to Non-Secure State Transition Disable When set, it disables the SSM transition from soft fail to non-secure state + 2 + 1 + read-write + + + SSM_SFNS_DIS_0 + Soft Fail to Non-Secure State transition is enabled + 0 + + + SSM_SFNS_DIS_1 + Soft Fail to Non-Secure State transition is disabled + 0x1 + + + + + LP_SWR + LP Software Reset When set to 1, most registers in the SNVS_LP section are reset, but the following registers are not reset by an LP software reset: Secure Real Time Counter Time Alarm Register This bit cannot be set when the LP_SWR_DIS bit is set + 4 + 1 + write-only + + + LP_SWR_0 + No Action + 0 + + + LP_SWR_1 + Reset LP section + 0x1 + + + + + LP_SWR_DIS + LP Software Reset Disable When set, disables the LP software reset + 5 + 1 + read-write + + + LP_SWR_DIS_0 + LP software reset is enabled + 0 + + + LP_SWR_DIS_1 + LP software reset is disabled + 0x1 + + + + + SW_SV + Software Security Violation When set, the system security monitor treats this bit as a non-fatal security violation + 8 + 1 + read-write + + + SW_FSV + Software Fatal Security Violation When set, the system security monitor treats this bit as a fatal security violation + 9 + 1 + read-write + + + SW_LPSV + LP Software Security Violation When set, SNVS_LP treats this bit as a security violation + 10 + 1 + read-write + + + PROG_ZMK + Program Zeroizable Master Key This bit activates ZMK hardware programming mechanism + 12 + 1 + write-only + + + PROG_ZMK_0 + No Action + 0 + + + PROG_ZMK_1 + Activate hardware key programming mechanism + 0x1 + + + + + MKS_EN + Master Key Select Enable When not set, the one time programmable (OTP) master key is selected by default + 13 + 1 + read-write + + + MKS_EN_0 + OTP master key is selected as an SNVS master key + 0 + + + MKS_EN_1 + SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR + 0x1 + + + + + HAC_EN + High Assurance Counter Enable This bit controls the SSM transition from the soft fail to the hard fail state + 16 + 1 + read-write + + + HAC_EN_0 + High Assurance Counter is disabled + 0 + + + HAC_EN_1 + High Assurance Counter is enabled + 0x1 + + + + + HAC_LOAD + High Assurance Counter Load When set, it loads the High Assurance Counter Register with the value of the High Assurance Counter Load Register + 17 + 1 + write-only + + + HAC_LOAD_0 + No Action + 0 + + + HAC_LOAD_1 + Load the HAC + 0x1 + + + + + HAC_CLEAR + High Assurance Counter Clear When set, it clears the High Assurance Counter Register + 18 + 1 + write-only + + + HAC_CLEAR_0 + No Action + 0 + + + HAC_CLEAR_1 + Clear the HAC + 0x1 + + + + + HAC_STOP + High Assurance Counter Stop This bit can be set only when SSM is in soft fail state + 19 + 1 + read-write + + + NPSWA_EN + Non-Privileged Software Access Enable When set, allows non-privileged software to access all SNVS registers, including those that are privileged software read/write access only + 31 + 1 + read-write + + + + + HPCR + SNVS_HP Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC_EN + HP Real Time Counter Enable + 0 + 1 + read-write + + + RTC_EN_0 + RTC is disabled + 0 + + + RTC_EN_1 + RTC is enabled + 0x1 + + + + + HPTA_EN + HP Time Alarm Enable When set, the time alarm interrupt is generated if the value in the HP Time Alarm Registers is equal to the value of the HP Real Time Counter + 1 + 1 + read-write + + + HPTA_EN_0 + HP Time Alarm Interrupt is disabled + 0 + + + HPTA_EN_1 + HP Time Alarm Interrupt is enabled + 0x1 + + + + + DIS_PI + Disable periodic interrupt in the functional interrupt + 2 + 1 + read-write + + + DIS_PI_0 + Periodic interrupt will trigger a functional interrupt + 0 + + + DIS_PI_1 + Disable periodic interrupt in the function interrupt + 0x1 + + + + + PI_EN + HP Periodic Interrupt Enable The periodic interrupt can be generated only if the HP Real Time Counter is enabled + 3 + 1 + read-write + + + PI_EN_0 + HP Periodic Interrupt is disabled + 0 + + + PI_EN_1 + HP Periodic Interrupt is enabled + 0x1 + + + + + PI_FREQ + Periodic Interrupt Frequency Defines frequency of the periodic interrupt + 4 + 4 + read-write + + + PI_FREQ_0 + - bit 0 of the HPRTCLR is selected as a source of the periodic interrupt + 0 + + + PI_FREQ_1 + - bit 1 of the HPRTCLR is selected as a source of the periodic interrupt + 0x1 + + + PI_FREQ_2 + - bit 2 of the HPRTCLR is selected as a source of the periodic interrupt + 0x2 + + + PI_FREQ_3 + - bit 3 of the HPRTCLR is selected as a source of the periodic interrupt + 0x3 + + + PI_FREQ_4 + - bit 4 of the HPRTCLR is selected as a source of the periodic interrupt + 0x4 + + + PI_FREQ_5 + - bit 5 of the HPRTCLR is selected as a source of the periodic interrupt + 0x5 + + + PI_FREQ_6 + - bit 6 of the HPRTCLR is selected as a source of the periodic interrupt + 0x6 + + + PI_FREQ_7 + - bit 7 of the HPRTCLR is selected as a source of the periodic interrupt + 0x7 + + + PI_FREQ_8 + - bit 8 of the HPRTCLR is selected as a source of the periodic interrupt + 0x8 + + + PI_FREQ_9 + - bit 9 of the HPRTCLR is selected as a source of the periodic interrupt + 0x9 + + + PI_FREQ_10 + - bit 10 of the HPRTCLR is selected as a source of the periodic interrupt + 0xA + + + PI_FREQ_11 + - bit 11 of the HPRTCLR is selected as a source of the periodic interrupt + 0xB + + + PI_FREQ_12 + - bit 12 of the HPRTCLR is selected as a source of the periodic interrupt + 0xC + + + PI_FREQ_13 + - bit 13 of the HPRTCLR is selected as a source of the periodic interrupt + 0xD + + + PI_FREQ_14 + - bit 14 of the HPRTCLR is selected as a source of the periodic interrupt + 0xE + + + PI_FREQ_15 + - bit 15 of the HPRTCLR is selected as a source of the periodic interrupt + 0xF + + + + + HPCALB_EN + HP Real Time Counter Calibration Enabled Indicates that the time calibration mechanism is enabled. + 8 + 1 + read-write + + + HPCALB_EN_0 + HP Timer calibration disabled + 0 + + + HPCALB_EN_1 + HP Timer calibration enabled + 0x1 + + + + + HPCALB_VAL + HP Calibration Value Defines signed calibration value for the HP Real Time Counter + 10 + 5 + read-write + + + HPCALB_VAL_0 + +0 counts per each 32768 ticks of the counter + 0 + + + HPCALB_VAL_1 + +1 counts per each 32768 ticks of the counter + 0x1 + + + HPCALB_VAL_2 + +2 counts per each 32768 ticks of the counter + 0x2 + + + HPCALB_VAL_15 + +15 counts per each 32768 ticks of the counter + 0xF + + + HPCALB_VAL_16 + -16 counts per each 32768 ticks of the counter + 0x10 + + + HPCALB_VAL_17 + -15 counts per each 32768 ticks of the counter + 0x11 + + + HPCALB_VAL_30 + -2 counts per each 32768 ticks of the counter + 0x1E + + + HPCALB_VAL_31 + -1 counts per each 32768 ticks of the counter + 0x1F + + + + + HP_TS + HP Time Synchronize + 16 + 1 + read-write + + + HP_TS_0 + No Action + 0 + + + HP_TS_1 + Synchronize the HP Time Counter to the LP Time Counter + 0x1 + + + + + BTN_CONFIG + Button Configuration + 24 + 3 + read-write + + + BTN_MASK + Button interrupt mask + 27 + 1 + read-write + + + + + HPSICR + SNVS_HP Security Interrupt Control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SV0_EN + Security Violation 0 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 0 security violation + 0 + 1 + read-write + + + SV0_EN_0 + Security Violation 0 Interrupt is Disabled + 0 + + + SV0_EN_1 + Security Violation 0 Interrupt is Enabled + 0x1 + + + + + SV1_EN + Security Violation 1 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 1 security violation + 1 + 1 + read-write + + + SV1_EN_0 + Security Violation 1 Interrupt is Disabled + 0 + + + SV1_EN_1 + Security Violation 1 Interrupt is Enabled + 0x1 + + + + + SV2_EN + Security Violation 2 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 2 security violation + 2 + 1 + read-write + + + SV2_EN_0 + Security Violation 2 Interrupt is Disabled + 0 + + + SV2_EN_1 + Security Violation 2 Interrupt is Enabled + 0x1 + + + + + SV3_EN + Security Violation 3 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 3 security violation + 3 + 1 + read-write + + + SV3_EN_0 + Security Violation 3 Interrupt is Disabled + 0 + + + SV3_EN_1 + Security Violation 3 Interrupt is Enabled + 0x1 + + + + + SV4_EN + Security Violation 4 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 4 security violation + 4 + 1 + read-write + + + SV4_EN_0 + Security Violation 4 Interrupt is Disabled + 0 + + + SV4_EN_1 + Security Violation 4 Interrupt is Enabled + 0x1 + + + + + SV5_EN + Security Violation 5 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 5 security violation + 5 + 1 + read-write + + + SV5_EN_0 + Security Violation 5 Interrupt is Disabled + 0 + + + SV5_EN_1 + Security Violation 5 Interrupt is Enabled + 0x1 + + + + + LPSVI_EN + LP Security Violation Interrupt Enable This bit enables generating of the security interrupt to the host processor upon security violation signal from the LP section + 31 + 1 + read-write + + + LPSVI_EN_0 + LP Security Violation Interrupt is Disabled + 0 + + + LPSVI_EN_1 + LP Security Violation Interrupt is Enabled + 0x1 + + + + + + + HPSVCR + SNVS_HP Security Violation Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SV0_CFG + Security Violation 0 Security Violation Configuration This field configures the Security Violation 0 Security Violation Input + 0 + 1 + read-write + + + SV0_CFG_0 + Security Violation 0 is a non-fatal violation + 0 + + + SV0_CFG_1 + Security Violation 0 is a fatal violation + 0x1 + + + + + SV1_CFG + Security Violation 1 Security Violation Configuration This field configures the Security Violation 1 Security Violation Input + 1 + 1 + read-write + + + SV1_CFG_0 + Security Violation 1 is a non-fatal violation + 0 + + + SV1_CFG_1 + Security Violation 1 is a fatal violation + 0x1 + + + + + SV2_CFG + Security Violation 2 Security Violation Configuration This field configures the Security Violation 2 Security Violation Input + 2 + 1 + read-write + + + SV2_CFG_0 + Security Violation 2 is a non-fatal violation + 0 + + + SV2_CFG_1 + Security Violation 2 is a fatal violation + 0x1 + + + + + SV3_CFG + Security Violation 3 Security Violation Configuration This field configures the Security Violation 3 Security Violation Input + 3 + 1 + read-write + + + SV3_CFG_0 + Security Violation 3 is a non-fatal violation + 0 + + + SV3_CFG_1 + Security Violation 3 is a fatal violation + 0x1 + + + + + SV4_CFG + Security Violation 4 Security Violation Configuration This field configures the Security Violation 4 Security Violation Input + 4 + 1 + read-write + + + SV4_CFG_0 + Security Violation 4 is a non-fatal violation + 0 + + + SV4_CFG_1 + Security Violation 4 is a fatal violation + 0x1 + + + + + SV5_CFG + Security Violation 5 Security Violation Configuration This field configures the Security Violation 5 Security Violation Input + 5 + 2 + read-write + + + SV5_CFG_0 + Security Violation 5 is disabled + 0 + + + SV5_CFG_1 + Security Violation 5 is a non-fatal violation + 0x1 + + + SV5_CFG_2 + Security Violation 5 is a fatal violation + #1x + + + + + LPSV_CFG + LP Security Violation Configuration This field configures the LP security violation source. + 30 + 2 + read-write + + + LPSV_CFG_0 + LP security violation is disabled + 0 + + + LPSV_CFG_1 + LP security violation is a non-fatal violation + 0x1 + + + LPSV_CFG_2 + LP security violation is a fatal violation + #1x + + + + + + + HPSR + SNVS_HP Status Register + 0x14 + 32 + read-write + 0x80003000 + 0xFFFFFFFF + + + HPTA + HP Time Alarm Indicates that the HP Time Alarm has occurred since this bit was last cleared. + 0 + 1 + read-write + oneToClear + + + HPTA_0 + No time alarm interrupt occurred. + 0 + + + HPTA_1 + A time alarm interrupt occurred. + 0x1 + + + + + PI + Periodic Interrupt Indicates that periodic interrupt has occurred since this bit was last cleared. + 1 + 1 + read-write + oneToClear + + + PI_0 + No periodic interrupt occurred. + 0 + + + PI_1 + A periodic interrupt occurred. + 0x1 + + + + + LPDIS + Low Power Disable If 1, the low power section has been disabled by means of an input signal to SNVS + 4 + 1 + read-only + + + BTN + Button Value of the BTN input + 6 + 1 + read-only + + + BI + Button Interrupt Signal ipi_snvs_btn_int_b was asserted. + 7 + 1 + read-write + oneToClear + + + SSM_STATE + System Security Monitor State This field contains the encoded state of the SSM's state machine + 8 + 4 + read-only + + + SSM_STATE_0 + Init + 0 + + + SSM_STATE_1 + Hard Fail + 0x1 + + + SSM_STATE_3 + Soft Fail + 0x3 + + + SSM_STATE_8 + Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle) + 0x8 + + + SSM_STATE_9 + Check + 0x9 + + + SSM_STATE_11 + Non-Secure + 0xB + + + SSM_STATE_13 + Trusted + 0xD + + + SSM_STATE_15 + Secure + 0xF + + + + + SECURITY_CONFIG + Security Configuration This field reflects the settings of the sys_secure_boot input and the three security configuration inputs to SNVS + 12 + 4 + read-only + + + FAB_CONFIG + FAB configuration + 0 + + + OPEN_CONFIG + OPEN configuration + 0x1 + + + OPEN_CONFIG + OPEN configuration + 0x2 + + + OPEN_CONFIG + OPEN configuration + 0x3 + + + FIELD_RETURN_CONFIG + FIELD RETURN configuration + #x1xx + + + FAB_CONFIG + FAB configuration + 0x8 + + + CLOSED_CONFIG + CLOSED configuration + 0x9 + + + CLOSED_CONFIG + CLOSED configuration + 0xA + + + CLOSED_CONFIG + CLOSED configuration + 0xB + + + + + OTPMK_SYNDROME + One Time Programmable Master Key Syndrome In the case of a single-bit error, the eight lower bits of this value indicate the bit number of error location + 16 + 9 + read-only + + + OTPMK_ZERO + One Time Programmable Master Key is Equal to Zero + 27 + 1 + read-only + + + OTPMK_ZERO_0 + The OTPMK is not zero. + 0 + + + OTPMK_ZERO_1 + The OTPMK is zero. + 0x1 + + + + + ZMK_ZERO + Zeroizable Master Key is Equal to Zero + 31 + 1 + read-only + + + ZMK_ZERO_0 + The ZMK is not zero. + 0 + + + ZMK_ZERO_1 + The ZMK is zero. + 0x1 + + + + + + + HPSVSR + SNVS_HP Security Violation Status Register + 0x18 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + SV0 + Security Violation 0 security violation was detected. + 0 + 1 + read-write + oneToClear + + + SV0_0 + No Security Violation 0 security violation was detected. + 0 + + + SV0_1 + Security Violation 0 security violation was detected. + 0x1 + + + + + SV1 + Security Violation 1 security violation was detected. + 1 + 1 + read-write + oneToClear + + + SV1_0 + No Security Violation 1 security violation was detected. + 0 + + + SV1_1 + Security Violation 1 security violation was detected. + 0x1 + + + + + SV2 + Security Violation 2 security violation was detected. + 2 + 1 + read-write + oneToClear + + + SV2_0 + No Security Violation 2 security violation was detected. + 0 + + + SV2_1 + Security Violation 2 security violation was detected. + 0x1 + + + + + SV3 + Security Violation 3 security violation was detected. + 3 + 1 + read-write + oneToClear + + + SV3_0 + No Security Violation 3 security violation was detected. + 0 + + + SV3_1 + Security Violation 3 security violation was detected. + 0x1 + + + + + SV4 + Security Violation 4 security violation was detected. + 4 + 1 + read-write + oneToClear + + + SV4_0 + No Security Violation 4 security violation was detected. + 0 + + + SV4_1 + Security Violation 4 security violation was detected. + 0x1 + + + + + SV5 + Security Violation 5 security violation was detected. + 5 + 1 + read-write + oneToClear + + + SV5_0 + No Security Violation 5 security violation was detected. + 0 + + + SV5_1 + Security Violation 5 security violation was detected. + 0x1 + + + + + SW_SV + Software Security Violation This bit is a read-only copy of the SW_SV bit in the HP Command Register + 13 + 1 + read-only + + + SW_FSV + Software Fatal Security Violation This bit is a read-only copy of the SW_FSV bit in the HP Command Register + 14 + 1 + read-only + + + SW_LPSV + LP Software Security Violation This bit is a read-only copy of the SW_LPSV bit in the HP Command Register + 15 + 1 + read-only + + + ZMK_SYNDROME + Zeroizable Master Key Syndrome The ZMK syndrome indicates the single-bit error location and parity for the ZMK register + 16 + 9 + read-only + + + ZMK_ECC_FAIL + Zeroizable Master Key Error Correcting Code Check Failure When set, this bit triggers a bad key violation to the SSM and a security violation to the SNVS_LP section, which clears security sensitive data + 27 + 1 + read-write + oneToClear + + + ZMK_ECC_FAIL_0 + ZMK ECC Failure was not detected. + 0 + + + ZMK_ECC_FAIL_1 + ZMK ECC Failure was detected. + 0x1 + + + + + LP_SEC_VIO + LP Security Violation A security volation was detected in the SNVS low power section. + 31 + 1 + read-only + + + + + HPHACIVR + SNVS_HP High Assurance Counter IV Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + HAC_COUNTER_IV + High Assurance Counter Initial Value This register is used to set the starting count value to the high assurance counter + 0 + 32 + read-write + + + + + HPHACR + SNVS_HP High Assurance Counter Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + HAC_COUNTER + High Assurance Counter When the HAC_EN bit is set and the SSM is in the soft fail state, this counter starts to count down with the system clock + 0 + 32 + read-only + + + + + HPRTCMR + SNVS_HP Real Time Counter MSB Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC + HP Real Time Counter The most-significant 15 bits of the RTC + 0 + 15 + read-write + + + + + HPRTCLR + SNVS_HP Real Time Counter LSB Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + RTC + HP Real Time Counter least-significant 32 bits + 0 + 32 + read-write + + + + + HPTAMR + SNVS_HP Time Alarm MSB Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + HPTA_MS + HP Time Alarm, most-significant 15 bits + 0 + 15 + read-write + + + + + HPTALR + SNVS_HP Time Alarm LSB Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + HPTA_LS + HP Time Alarm, 32 least-significant bits + 0 + 32 + read-write + + + + + LPLR + SNVS_LP Lock Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ZMK_WHL + Zeroizable Master Key Write Hard Lock When set, prevents any writes (software and hardware) to the ZMK registers and ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR + 0 + 1 + read-write + + + ZMK_WHL_0 + Write access is allowed. + 0 + + + ZMK_WHL_1 + Write access is not allowed. + 0x1 + + + + + ZMK_RHL + Zeroizable Master Key Read Hard Lock When set, prevents any software reads to the ZMK registers and ZMK_ECC_VALUE field of the LPMKCR + 1 + 1 + read-write + + + ZMK_RHL_0 + Read access is allowed (only in software programming mode). + 0 + + + ZMK_RHL_1 + Read access is not allowed. + 0x1 + + + + + SRTC_HL + Secure Real Time Counter Hard Lock When set, prevents any writes to the SRTC registers, SRTC_ENV, and SRTC_INV_EN bits + 2 + 1 + read-write + + + SRTC_HL_0 + Write access is allowed. + 0 + + + SRTC_HL_1 + Write access is not allowed. + 0x1 + + + + + LPCALB_HL + LP Calibration Hard Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN) + 3 + 1 + read-write + + + LPCALB_HL_0 + Write access is allowed. + 0 + + + LPCALB_HL_1 + Write access is not allowed. + 0x1 + + + + + MC_HL + Monotonic Counter Hard Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit + 4 + 1 + read-write + + + MC_HL_0 + Write access (increment) is allowed. + 0 + + + MC_HL_1 + Write access (increment) is not allowed. + 0x1 + + + + + GPR_HL + General Purpose Register Hard Lock When set, prevents any writes to the GPR + 5 + 1 + read-write + + + GPR_HL_0 + Write access is allowed. + 0 + + + GPR_HL_1 + Write access is not allowed. + 0x1 + + + + + LPSVCR_HL + LP Security Violation Control Register Hard Lock When set, prevents any writes to the LPSVCR + 6 + 1 + read-write + + + LPSVCR_HL_0 + Write access is allowed. + 0 + + + LPSVCR_HL_1 + Write access is not allowed. + 0x1 + + + + + LPTDCR_HL + LP Tamper Detectors Configuration Register Hard Lock When set, prevents any writes to the LPTDCR + 8 + 1 + read-write + + + LPTDCR_HL_0 + Write access is allowed. + 0 + + + LPTDCR_HL_1 + Write access is not allowed. + 0x1 + + + + + MKS_HL + Master Key Select Hard Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LP Master Key Control Register + 9 + 1 + read-write + + + MKS_HL_0 + Write access is allowed. + 0 + + + MKS_HL_1 + Write access is not allowed. + 0x1 + + + + + + + LPCR + SNVS_LP Control Register + 0x38 + 32 + read-write + 0x20 + 0xFFFFFFFF + + + SRTC_ENV + Secure Real Time Counter Enabled and Valid When set, the SRTC becomes operational + 0 + 1 + read-write + + + SRTC_ENV_0 + SRTC is disabled or invalid. + 0 + + + SRTC_ENV_1 + SRTC is enabled and valid. + 0x1 + + + + + LPTA_EN + LP Time Alarm Enable When set, the SNVS functional interrupt is asserted if the LP Time Alarm Register is equal to the 32 MSBs of the secure real time counter + 1 + 1 + read-write + + + LPTA_EN_0 + LP time alarm interrupt is disabled. + 0 + + + LPTA_EN_1 + LP time alarm interrupt is enabled. + 0x1 + + + + + MC_ENV + Monotonic Counter Enabled and Valid When set, the MC can be incremented (by write transaction to the LPSMCMR or LPSMCLR) + 2 + 1 + read-write + + + MC_ENV_0 + MC is disabled or invalid. + 0 + + + MC_ENV_1 + MC is enabled and valid. + 0x1 + + + + + LPWUI_EN + LP Wake-Up Interrupt Enable This interrupt line should be connected to the external pin and is intended to inform the external chip about an SNVS_LP event (tamper event, MC rollover, SRTC rollover, or time alarm ) + 3 + 1 + read-write + + + SRTC_INV_EN + If this bit is 1, in the case of a security violation the SRTC stops counting and the SRTC is invalidated (SRTC_ENV bit is cleared) + 4 + 1 + read-write + + + SRTC_INV_EN_0 + SRTC stays valid in the case of security violation. + 0 + + + SRTC_INV_EN_1 + SRTC is invalidated in the case of security violation. + 0x1 + + + + + DP_EN + Dumb PMIC Enabled When set, software can control the system power + 5 + 1 + read-write + + + DP_EN_0 + Smart PMIC enabled. + 0 + + + DP_EN_1 + Dumb PMIC enabled. + 0x1 + + + + + TOP + Turn off System Power Asserting this bit causes a signal to be sent to the Power Management IC to turn off the system power + 6 + 1 + read-write + + + TOP_0 + Leave system power on. + 0 + + + TOP_1 + Turn off system power. + 0x1 + + + + + PWR_GLITCH_EN + Power Glitch Enable By default the detection of a power glitch does not cause the pmic_en_b signal to be asserted + 7 + 1 + read-write + + + LPCALB_EN + LP Calibration Enable When set, enables the SRTC calibration mechanism + 8 + 1 + read-write + + + LPCALB_EN_0 + SRTC Time calibration is disabled. + 0 + + + LPCALB_EN_1 + SRTC Time calibration is enabled. + 0x1 + + + + + LPCALB_VAL + LP Calibration Value Defines signed calibration value for SRTC + 10 + 5 + read-write + + + LPCALB_VAL_0 + +0 counts per each 32768 ticks of the counter clock + 0 + + + LPCALB_VAL_1 + +1 counts per each 32768 ticks of the counter clock + 0x1 + + + LPCALB_VAL_2 + +2 counts per each 32768 ticks of the counter clock + 0x2 + + + LPCALB_VAL_15 + +15 counts per each 32768 ticks of the counter clock + 0xF + + + LPCALB_VAL_16 + -16 counts per each 32768 ticks of the counter clock + 0x10 + + + LPCALB_VAL_17 + -15 counts per each 32768 ticks of the counter clock + 0x11 + + + LPCALB_VAL_30 + -2 counts per each 32768 ticks of the counter clock + 0x1E + + + LPCALB_VAL_31 + -1 counts per each 32768 ticks of the counter clock + 0x1F + + + + + BTN_PRESS_TIME + This field configures the button press time out values for the PMIC Logic + 16 + 2 + read-write + + + DEBOUNCE + This field configures the amount of debounce time for the BTN input signal + 18 + 2 + read-write + + + ON_TIME + The ON_TIME field is used to configure the period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoC power + 20 + 2 + read-write + + + PK_EN + PMIC On Request Enable The value written to PK_EN will be asserted on output signal snvs_lp_pk_en + 22 + 1 + read-write + + + PK_OVERRIDE + PMIC On Request Override The value written to PK_OVERRIDE will be asserted on output signal snvs_lp_pk_override + 23 + 1 + read-write + + + GPR_Z_DIS + General Purpose Registers Zeroization Disable + 24 + 1 + read-write + + + + + LPMKCR + SNVS_LP Master Key Control Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + MASTER_KEY_SEL + Master Key Select These bits select the SNVS Master Key output when Master Key Select bits are enabled by MKS_EN bit in the HPCOMR + 0 + 2 + read-write + + + MASTER_KEY_SEL_0 + Select one time programmable master key. + #0x + + + MASTER_KEY_SEL_2 + Select zeroizable master key when MKS_EN bit is set . + 0x2 + + + MASTER_KEY_SEL_3 + Select combined master key when MKS_EN bit is set . + 0x3 + + + + + ZMK_HWP + Zeroizable Master Key hardware Programming mode When set, only the hardware key programming mechanism can set the ZMK and software cannot read it + 2 + 1 + read-write + + + ZMK_HWP_0 + ZMK is in the software programming mode. + 0 + + + ZMK_HWP_1 + ZMK is in the hardware programming mode. + 0x1 + + + + + ZMK_VAL + Zeroizable Master Key Valid When set, the ZMK value can be selected by the master key control block for use by cryptographic modules + 3 + 1 + read-write + + + ZMK_VAL_0 + ZMK is not valid. + 0 + + + ZMK_VAL_1 + ZMK is valid. + 0x1 + + + + + ZMK_ECC_EN + Zeroizable Master Key Error Correcting Code Check Enable Writing one to this field automatically calculates and sets the ZMK ECC value in the ZMK_ECC_VALUE field of this register + 4 + 1 + read-write + + + ZMK_ECC_EN_0 + ZMK ECC check is disabled. + 0 + + + ZMK_ECC_EN_1 + ZMK ECC check is enabled. + 0x1 + + + + + ZMK_ECC_VALUE + Zeroizable Master Key Error Correcting Code Value This field is automatically calculated and set when one is written into ZMK_ECC_EN bit of this register + 7 + 9 + read-only + + + + + LPSVCR + SNVS_LP Security Violation Control Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + SV0_EN + Security Violation 0 Enable This bit enables Security Violation 0 Input + 0 + 1 + read-write + + + SV0_EN_0 + Security Violation 0 is disabled in the LP domain. + 0 + + + SV0_EN_1 + Security Violation 0 is enabled in the LP domain. + 0x1 + + + + + SV1_EN + Security Violation 1 Enable This bit enables Security Violation 1 Input + 1 + 1 + read-write + + + SV1_EN_0 + Security Violation 1 is disabled in the LP domain. + 0 + + + SV1_EN_1 + Security Violation 1 is enabled in the LP domain. + 0x1 + + + + + SV2_EN + Security Violation 2 Enable This bit enables Security Violation 2 Input + 2 + 1 + read-write + + + SV2_EN_0 + Security Violation 2 is disabled in the LP domain. + 0 + + + SV2_EN_1 + Security Violation 2 is enabled in the LP domain. + 0x1 + + + + + SV3_EN + Security Violation 3 Enable This bit enables Security Violation 3 Input + 3 + 1 + read-write + + + SV3_EN_0 + Security Violation 3 is disabled in the LP domain. + 0 + + + SV3_EN_1 + Security Violation 3 is enabled in the LP domain. + 0x1 + + + + + SV4_EN + Security Violation 4 Enable This bit enables Security Violation 4 Input + 4 + 1 + read-write + + + SV4_EN_0 + Security Violation 4 is disabled in the LP domain. + 0 + + + SV4_EN_1 + Security Violation 4 is enabled in the LP domain. + 0x1 + + + + + SV5_EN + Security Violation 5 Enable This bit enables Security Violation 5 Input + 5 + 1 + read-write + + + SV5_EN_0 + Security Violation 5 is disabled in the LP domain. + 0 + + + SV5_EN_1 + Security Violation 5 is enabled in the LP domain. + 0x1 + + + + + + + LPTDCR + SNVS_LP Tamper Detectors Configuration Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRTCR_EN + SRTC Rollover Enable When set, an SRTC rollover event generates an LP security violation. + 1 + 1 + read-write + + + SRTCR_EN_0 + SRTC rollover is disabled. + 0 + + + SRTCR_EN_1 + SRTC rollover is enabled. + 0x1 + + + + + MCR_EN + MC Rollover Enable When set, an MC Rollover event generates an LP security violation. + 2 + 1 + read-write + + + MCR_EN_0 + MC rollover is disabled. + 0 + + + MCR_EN_1 + MC rollover is enabled. + 0x1 + + + + + ET1_EN + External Tampering 1 Enable When set, external tampering 1 detection generates an LP security violation + 9 + 1 + read-write + + + ET1_EN_0 + External tamper 1 is disabled. + 0 + + + ET1_EN_1 + External tamper 1 is enabled. + 0x1 + + + + + ET1P + External Tampering 1 Polarity This bit is used to determine the polarity of external tamper 1. + 11 + 1 + read-write + + + ET1P_0 + External tamper 1 is active low. + 0 + + + ET1P_1 + External tamper 1 is active high. + 0x1 + + + + + PFD_OBSERV + System Power Fail Detector (PFD) Observability Flop The asynchronous reset input of this flop is connected directly to the inverted output of the PFD analog circuitry (external to the SNVS block) + 14 + 1 + read-write + + + POR_OBSERV + Power On Reset (POR) Observability Flop The asynchronous reset input of this flop is connected directly to the output of the POR analog circuitry (external to the SNVS + 15 + 1 + read-write + + + OSCB + Oscillator Bypass When OSCB=1 the osc_bypass signal is asserted + 28 + 1 + read-write + + + OSCB_0 + Normal SRTC clock oscillator not bypassed. + 0 + + + OSCB_1 + Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source. + 0x1 + + + + + + + LPSR + SNVS_LP Status Register + 0x4C + 32 + read-write + 0x8 + 0xFFFFFFFF + + + LPTA + LP Time Alarm + 0 + 1 + read-write + oneToClear + + + LPTA_0 + No time alarm interrupt occurred. + 0 + + + LPTA_1 + A time alarm interrupt occurred. + 0x1 + + + + + SRTCR + Secure Real Time Counter Rollover + 1 + 1 + read-write + oneToClear + + + SRTCR_0 + SRTC has not reached its maximum value. + 0 + + + SRTCR_1 + SRTC has reached its maximum value. + 0x1 + + + + + MCR + Monotonic Counter Rollover + 2 + 1 + read-write + oneToClear + + + MCR_0 + MC has not reached its maximum value. + 0 + + + MCR_1 + MC has reached its maximum value. + 0x1 + + + + + PGD + Power Supply Glitch Detected 0 No power supply glitch. 1 Power supply glitch is detected. + 3 + 1 + read-write + oneToClear + + + ET1D + External Tampering 1 Detected + 9 + 1 + read-write + oneToClear + + + ET1D_0 + External tampering 1 not detected. + 0 + + + ET1D_1 + External tampering 1 detected. + 0x1 + + + + + ESVD + External Security Violation Detected Indicates that a security violation is detected on one of the HP security violation ports + 16 + 1 + read-write + oneToClear + + + ESVD_0 + No external security violation. + 0 + + + ESVD_1 + External security violation is detected. + 0x1 + + + + + EO + Emergency Off This bit is set when a power off is requested. + 17 + 1 + read-write + oneToClear + + + EO_0 + Emergency off was not detected. + 0 + + + EO_1 + Emergency off was detected. + 0x1 + + + + + SPO + Set Power Off The SPO bit is set when the power button is pressed longer than the configured debounce time + 18 + 1 + read-write + oneToClear + + + SPO_0 + Set Power Off was not detected. + 0 + + + SPO_1 + Set Power Off was detected. + 0x1 + + + + + SED + Scan Exit Detected + 20 + 1 + read-write + oneToClear + + + SED_0 + Scan exit was not detected. + 0 + + + SED_1 + Scan exit was detected. + 0x1 + + + + + LPNS + LP Section is Non-Secured Indicates that LP section was provisioned/programmed in the non-secure state + 30 + 1 + read-only + + + LPNS_0 + LP section was not programmed in the non-secure state. + 0 + + + LPNS_1 + LP section was programmed in the non-secure state. + 0x1 + + + + + LPS + LP Section is Secured Indicates that the LP section is provisioned/programmed in the secure or trusted state + 31 + 1 + read-only + + + LPS_0 + LP section was not programmed in secure or trusted state. + 0 + + + LPS_1 + LP section was programmed in secure or trusted state. + 0x1 + + + + + + + LPSRTCMR + SNVS_LP Secure Real Time Counter MSB Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRTC + LP Secure Real Time Counter The most-significant 15 bits of the SRTC + 0 + 15 + read-write + + + + + LPSRTCLR + SNVS_LP Secure Real Time Counter LSB Register + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + SRTC + LP Secure Real Time Counter least-significant 32 bits This register can be programmed only when SRTC is not active and not locked, meaning the SRTC_ENV, SRTC_SL, and SRTC_HL bits are not set + 0 + 32 + read-write + + + + + LPTAR + SNVS_LP Time Alarm Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + LPTA + LP Time Alarm This register can be programmed only when the LP time alarm is disabled (LPTA_EN bit is not set) + 0 + 32 + read-write + + + + + LPSMCMR + SNVS_LP Secure Monotonic Counter MSB Register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + MON_COUNTER + Monotonic Counter most-significant 16 Bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR register is detected + 0 + 16 + read-only + + + MC_ERA_BITS + Monotonic Counter Era Bits These bits are inputs to the module and typically connect to fuses + 16 + 16 + read-only + + + + + LPSMCLR + SNVS_LP Secure Monotonic Counter LSB Register + 0x60 + 32 + read-only + 0 + 0xFFFFFFFF + + + MON_COUNTER + Monotonic Counter bits The MC is incremented by one when: A write transaction to the LPSMCMR or LPSMCLR Register is detected + 0 + 32 + read-only + + + + + LPPGDR + SNVS_LP Power Glitch Detector Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + PGD + Power Glitch Detector Value + 0 + 32 + read-write + + + + + LPGPR0_legacy_alias + SNVS_LP General Purpose Register 0 (legacy alias) + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. + 0 + 32 + read-write + + + + + 8 + 0x4 + LPZMKR[%s] + SNVS_LP Zeroizable Master Key Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + ZMK + Zeroizable Master Key Each of these registers contains 32 bits of the 256-bit ZMK value + 0 + 32 + read-write + + + + + 4 + 0x4 + LPGPR_alias[%s] + SNVS_LP General Purpose Registers 0 .. 3 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. + 0 + 32 + read-write + + + + + 8 + 0x4 + LPGPR[%s] + SNVS_LP General Purpose Registers 0 .. 7 + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR + General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed. + 0 + 32 + read-write + + + + + HPVIDR1 + SNVS_HP Version ID Register 1 + 0xBF8 + 32 + read-only + 0x3E0104 + 0xFFFFFFFF + + + MINOR_REV + SNVS block minor version number + 0 + 8 + read-only + + + MAJOR_REV + SNVS block major version number + 8 + 8 + read-only + + + IP_ID + SNVS block ID + 16 + 16 + read-only + + + + + HPVIDR2 + SNVS_HP Version ID Register 2 + 0xBFC + 32 + read-only + 0x6000000 + 0xFFFFFFFF + + + CONFIG_OPT + SNVS Configuration Options + 0 + 8 + read-only + + + ECO_REV + SNVS ECO Revision + 8 + 8 + read-only + + + INTG_OPT + SNVS Integration Options + 16 + 8 + read-only + + + IP_ERA + IP Era 00h - Era 1 or 2 03h - Era 3 04h - Era 4 05h - Era 5 + 24 + 8 + read-only + + + + + + + CCM_ANALOG + CCM_ANALOG + CCM_ANALOG + CCM_ANALOG_ + 0x400D8000 + + 0 + 0x180 + registers + + + + PLL_ARM + Analog ARM PLL control Register + 0 + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PLL_SEL + Reserved + 19 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ARM_SET + Analog ARM PLL control Register + 0x4 + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PLL_SEL + Reserved + 19 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ARM_CLR + Analog ARM PLL control Register + 0x8 + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PLL_SEL + Reserved + 19 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ARM_TOG + Analog ARM PLL control Register + 0xC + 32 + read-write + 0x13063 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + PLL_SEL + Reserved + 19 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB1 + Analog USB1 480MHz PLL Control Register + 0x10 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB1_SET + Analog USB1 480MHz PLL Control Register + 0x14 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB1_CLR + Analog USB1 480MHz PLL Control Register + 0x18 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB1_TOG + Analog USB1 480MHz PLL Control Register + 0x1C + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + Powers the 9-phase PLL outputs for USBPHYn + 6 + 1 + read-write + + + EN_USB_CLKS_0 + PLL outputs for USBPHYn off. + 0 + + + EN_USB_CLKS_1 + PLL outputs for USBPHYn on. + 0x1 + + + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB2 + Analog USB2 480MHz PLL Control Register + 0x20 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB2_SET + Analog USB2 480MHz PLL Control Register + 0x24 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB2_CLR + Analog USB2 480MHz PLL Control Register + 0x28 + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_USB2_TOG + Analog USB2 480MHz PLL Control Register + 0x2C + 32 + read-write + 0x12000 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 1 + 1 + read-write + + + EN_USB_CLKS + 0: 8-phase PLL outputs for USBPHY1 are powered down + 6 + 1 + read-write + + + POWER + Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens. + 12 + 1 + read-write + + + ENABLE + Enable the PLL clock output. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS + Analog System PLL Control Register + 0x30 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS_SET + Analog System PLL Control Register + 0x34 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS_CLR + Analog System PLL Control Register + 0x38 + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS_TOG + Analog System PLL Control Register + 0x3C + 32 + read-write + 0x13001 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. 0 - Fout=Fref*20; 1 - Fout=Fref*22. + 0 + 1 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_SYS_SS + 528MHz System PLL Spread Spectrum Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + STEP + Frequency change step = step/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz. + 0 + 15 + read-write + + + ENABLE + Enable bit + 15 + 1 + read-write + + + ENABLE_0 + Spread spectrum modulation disabled + 0 + + + ENABLE_1 + Soread spectrum modulation enabled + 0x1 + + + + + STOP + Frequency change = stop/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz. + 16 + 16 + read-write + + + + + PLL_SYS_NUM + Numerator of 528MHz System PLL Fractional Loop Divider Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + A + 30 bit numerator (A) of fractional loop divider (signed integer). + 0 + 30 + read-write + + + + + PLL_SYS_DENOM + Denominator of 528MHz System PLL Fractional Loop Divider Register + 0x60 + 32 + read-write + 0x12 + 0xFFFFFFFF + + + B + 30 bit Denominator (B) of fractional loop divider (unsigned integer). + 0 + 30 + read-write + + + + + PLL_AUDIO + Analog Audio PLL control Register + 0x70 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_AUDIO_SET + Analog Audio PLL control Register + 0x74 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_AUDIO_CLR + Analog Audio PLL control Register + 0x78 + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_AUDIO_TOG + Analog Audio PLL control Register + 0x7C + 32 + read-write + 0x11006 + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked. 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_AUDIO_NUM + Numerator of Audio PLL Fractional Loop Divider Register + 0x80 + 32 + read-write + 0x5F5E100 + 0xFFFFFFFF + + + A + 30 bit numerator of fractional loop divider. + 0 + 30 + read-write + + + + + PLL_AUDIO_DENOM + Denominator of Audio PLL Fractional Loop Divider Register + 0x90 + 32 + read-write + 0x2964619C + 0xFFFFFFFF + + + B + 30 bit Denominator of fractional loop divider. + 0 + 30 + read-write + + + + + PLL_VIDEO + Analog Video PLL control Register + 0xA0 + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enalbe PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_VIDEO_SET + Analog Video PLL control Register + 0xA4 + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enalbe PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_VIDEO_CLR + Analog Video PLL control Register + 0xA8 + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enalbe PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_VIDEO_TOG + Analog Video PLL control Register + 0xAC + 32 + read-write + 0x1100C + 0xFFFFFFFF + + + DIV_SELECT + This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. + 0 + 7 + read-write + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enalbe PLL output + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + POST_DIV_SELECT + These bits implement a divider after the PLL, but before the enable and bypass mux. + 19 + 2 + read-write + + + POST_DIV_SELECT_0 + Divide by 4. + 0 + + + POST_DIV_SELECT_1 + Divide by 2. + 0x1 + + + POST_DIV_SELECT_2 + Divide by 1. + 0x2 + + + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_VIDEO_NUM + Numerator of Video PLL Fractional Loop Divider Register + 0xB0 + 32 + read-write + 0x5F5E100 + 0xFFFFFFFF + + + A + 30 bit numerator of fractional loop divider(Signed number), absolute value should be less than denominator + 0 + 30 + read-write + + + + + PLL_VIDEO_DENOM + Denominator of Video PLL Fractional Loop Divider Register + 0xC0 + 32 + read-write + 0x10A24447 + 0xFFFFFFFF + + + B + 30 bit Denominator of fractional loop divider. + 0 + 30 + read-write + + + + + PLL_ENET + Analog ENET PLL Control Register + 0xE0 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + DIV_SELECT + Controls the frequency of the ethernet reference clock + 0 + 2 + read-write + + + ENET2_DIV_SELECT + Controls the frequency of the ENET2 reference clock. + 2 + 2 + read-write + + + ENET2_DIV_SELECT_0 + 25MHz + 0 + + + ENET2_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET2_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET2_DIV_SELECT_3 + 125MHz + 0x3 + + + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the PLL providing the ENET reference clock. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + ENET2_REF_EN + Enable the PLL providing the ENET2 reference clock + 20 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 21 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ENET_SET + Analog ENET PLL Control Register + 0xE4 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + DIV_SELECT + Controls the frequency of the ethernet reference clock + 0 + 2 + read-write + + + ENET2_DIV_SELECT + Controls the frequency of the ENET2 reference clock. + 2 + 2 + read-write + + + ENET2_DIV_SELECT_0 + 25MHz + 0 + + + ENET2_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET2_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET2_DIV_SELECT_3 + 125MHz + 0x3 + + + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the PLL providing the ENET reference clock. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + ENET2_REF_EN + Enable the PLL providing the ENET2 reference clock + 20 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 21 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ENET_CLR + Analog ENET PLL Control Register + 0xE8 + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + DIV_SELECT + Controls the frequency of the ethernet reference clock + 0 + 2 + read-write + + + ENET2_DIV_SELECT + Controls the frequency of the ENET2 reference clock. + 2 + 2 + read-write + + + ENET2_DIV_SELECT_0 + 25MHz + 0 + + + ENET2_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET2_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET2_DIV_SELECT_3 + 125MHz + 0x3 + + + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the PLL providing the ENET reference clock. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + ENET2_REF_EN + Enable the PLL providing the ENET2 reference clock + 20 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 21 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PLL_ENET_TOG + Analog ENET PLL Control Register + 0xEC + 32 + read-write + 0x11001 + 0xFFFFFFFF + + + DIV_SELECT + Controls the frequency of the ethernet reference clock + 0 + 2 + read-write + + + ENET2_DIV_SELECT + Controls the frequency of the ENET2 reference clock. + 2 + 2 + read-write + + + ENET2_DIV_SELECT_0 + 25MHz + 0 + + + ENET2_DIV_SELECT_1 + 50MHz + 0x1 + + + ENET2_DIV_SELECT_2 + 100MHz (not 50% duty cycle) + 0x2 + + + ENET2_DIV_SELECT_3 + 125MHz + 0x3 + + + + + POWERDOWN + Powers down the PLL. + 12 + 1 + read-write + + + ENABLE + Enable the PLL providing the ENET reference clock. + 13 + 1 + read-write + + + BYPASS_CLK_SRC + Determines the bypass source. + 14 + 2 + read-write + + + REF_CLK_24M + Select the 24MHz oscillator as source. + 0 + + + CLK1 + Select the CLK1_N / CLK1_P as source. + 0x1 + + + + + BYPASS + Bypass the PLL. + 16 + 1 + read-write + + + ENET2_REF_EN + Enable the PLL providing the ENET2 reference clock + 20 + 1 + read-write + + + ENET_25M_REF_EN + Enable the PLL providing ENET 25 MHz reference clock + 21 + 1 + read-write + + + LOCK + 1 - PLL is currently locked; 0 - PLL is not currently locked. + 31 + 1 + read-only + + + + + PFD_480 + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xF0 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_480_SET + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xF4 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_480_CLR + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xF8 + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_480_TOG + 480MHz Clock (PLL3) Phase Fractional Divider Control Register + 0xFC + 32 + read-write + 0x1311100C + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_528 + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x100 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_528_SET + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x104 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_528_CLR + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x108 + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + PFD_528_TOG + 528MHz Clock (PLL2) Phase Fractional Divider Control Register + 0x10C + 32 + read-write + 0x1018101B + 0xFFFFFFFF + + + PFD0_FRAC + This field controls the fractional divide value + 0 + 6 + read-write + + + PFD0_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 6 + 1 + read-only + + + PFD0_CLKGATE + If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings) + 7 + 1 + read-write + + + PFD1_FRAC + This field controls the fractional divide value + 8 + 6 + read-write + + + PFD1_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 14 + 1 + read-only + + + PFD1_CLKGATE + IO Clock Gate + 15 + 1 + read-write + + + PFD2_FRAC + This field controls the fractional divide value + 16 + 6 + read-write + + + PFD2_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 22 + 1 + read-only + + + PFD2_CLKGATE + IO Clock Gate + 23 + 1 + read-write + + + PFD3_FRAC + This field controls the fractional divide value + 24 + 6 + read-write + + + PFD3_STABLE + This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code + 30 + 1 + read-only + + + PFD3_CLKGATE + IO Clock Gate + 31 + 1 + read-write + + + + + MISC0 + Miscellaneous Register 0 + 0x150 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except RTC powered down on stop mode assertion. + 0 + + + STOP_MODE_CONFIG_1 + Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + 0x1 + + + STOP_MODE_CONFIG_2 + Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. + 0x2 + + + STOP_MODE_CONFIG_3 + Beside RTC, low-power bandgap is selected and the rest analog is powered down. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 29 + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 30 + 1 + read-write + + + + + MISC0_SET + Miscellaneous Register 0 + 0x154 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except RTC powered down on stop mode assertion. + 0 + + + STOP_MODE_CONFIG_1 + Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + 0x1 + + + STOP_MODE_CONFIG_2 + Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. + 0x2 + + + STOP_MODE_CONFIG_3 + Beside RTC, low-power bandgap is selected and the rest analog is powered down. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 29 + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 30 + 1 + read-write + + + + + MISC0_CLR + Miscellaneous Register 0 + 0x158 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except RTC powered down on stop mode assertion. + 0 + + + STOP_MODE_CONFIG_1 + Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + 0x1 + + + STOP_MODE_CONFIG_2 + Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. + 0x2 + + + STOP_MODE_CONFIG_3 + Beside RTC, low-power bandgap is selected and the rest analog is powered down. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 29 + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 30 + 1 + read-write + + + + + MISC0_TOG + Miscellaneous Register 0 + 0x15C + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to CCM. See Power Management Unit (PMU) + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except RTC powered down on stop mode assertion. + 0 + + + STOP_MODE_CONFIG_1 + Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on. + 0x1 + + + STOP_MODE_CONFIG_2 + Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog bandgap together with the rest analog is powered down. + 0x2 + + + STOP_MODE_CONFIG_3 + Beside RTC, low-power bandgap is selected and the rest analog is powered down. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock + 29 + 1 + read-write + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true + 30 + 1 + read-write + + + + + MISC1 + Miscellaneous Register 1 + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_SET + Miscellaneous Register 1 + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_CLR + Miscellaneous Register 1 + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_TOG + Miscellaneous Register 1 + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC2 + Miscellaneous Register 2 + 0x170 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 5 + 1 + read-write + + + REG0_OK + ARM supply Not related to CCM. See Power Management Unit (PMU) + 6 + 1 + read-only + + + PLL3_DISABLE + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 7 + 1 + read-write + + + PLL3_DISABLE_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_DISABLE_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 13 + 1 + read-write + + + REG1_OK + GPU/VPU supply Not related to CCM. See Power Management Unit (PMU) + 14 + 1 + read-only + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_SET + Miscellaneous Register 2 + 0x174 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 5 + 1 + read-write + + + REG0_OK + ARM supply Not related to CCM. See Power Management Unit (PMU) + 6 + 1 + read-only + + + PLL3_DISABLE + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 7 + 1 + read-write + + + PLL3_DISABLE_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_DISABLE_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 13 + 1 + read-write + + + REG1_OK + GPU/VPU supply Not related to CCM. See Power Management Unit (PMU) + 14 + 1 + read-only + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_CLR + Miscellaneous Register 2 + 0x178 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 5 + 1 + read-write + + + REG0_OK + ARM supply Not related to CCM. See Power Management Unit (PMU) + 6 + 1 + read-only + + + PLL3_DISABLE + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 7 + 1 + read-write + + + PLL3_DISABLE_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_DISABLE_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 13 + 1 + read-write + + + REG1_OK + GPU/VPU supply Not related to CCM. See Power Management Unit (PMU) + 14 + 1 + read-only + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_TOG + Miscellaneous Register 2 + 0x17C + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 5 + 1 + read-write + + + REG0_OK + ARM supply Not related to CCM. See Power Management Unit (PMU) + 6 + 1 + read-only + + + PLL3_DISABLE + When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode + 7 + 1 + read-write + + + PLL3_DISABLE_0 + PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode + 0 + + + PLL3_DISABLE_1 + PLL3 can be disabled when the SoC is not in any low power mode + 0x1 + + + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU) + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 13 + 1 + read-write + + + REG1_OK + GPU/VPU supply Not related to CCM. See Power Management Unit (PMU) + 14 + 1 + read-only + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit.Not related to CCM. See Power Management Unit (PMU) + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU) + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU) + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + + + PMU + PMU + CCM_ANALOG + PMU + PMU_ + 0x400D8000 + + 0 + 0x180 + registers + + + PMU_EVENT + 61 + + + + REG_1P1 + Regulator 1P1 Register + 0x110 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_4 + 0.8V + 0x4 + + + OUTPUT_TRG_16 + 1.1V + 0x10 + + + + + BO_VDD1P1 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD1P1 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 1p1 regulator + 18 + 1 + read-write + + + SELREF_WEAK_LINREG + Selects the source for the reference voltage of the weak 1p1 regulator. + 19 + 1 + read-write + + + SELREF_WEAK_LINREG_0 + Weak-linreg output tracks low-power-bandgap voltage + 0 + + + SELREF_WEAK_LINREG_1 + Weak-linreg output tracks VDD_SOC_IN voltage + 0x1 + + + + + + + REG_1P1_SET + Regulator 1P1 Register + 0x114 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_4 + 0.8V + 0x4 + + + OUTPUT_TRG_16 + 1.1V + 0x10 + + + + + BO_VDD1P1 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD1P1 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 1p1 regulator + 18 + 1 + read-write + + + SELREF_WEAK_LINREG + Selects the source for the reference voltage of the weak 1p1 regulator. + 19 + 1 + read-write + + + SELREF_WEAK_LINREG_0 + Weak-linreg output tracks low-power-bandgap voltage + 0 + + + SELREF_WEAK_LINREG_1 + Weak-linreg output tracks VDD_SOC_IN voltage + 0x1 + + + + + + + REG_1P1_CLR + Regulator 1P1 Register + 0x118 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_4 + 0.8V + 0x4 + + + OUTPUT_TRG_16 + 1.1V + 0x10 + + + + + BO_VDD1P1 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD1P1 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 1p1 regulator + 18 + 1 + read-write + + + SELREF_WEAK_LINREG + Selects the source for the reference voltage of the weak 1p1 regulator. + 19 + 1 + read-write + + + SELREF_WEAK_LINREG_0 + Weak-linreg output tracks low-power-bandgap voltage + 0 + + + SELREF_WEAK_LINREG_1 + Weak-linreg output tracks VDD_SOC_IN voltage + 0x1 + + + + + + + REG_1P1_TOG + Regulator 1P1 Register + 0x11C + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_4 + 0.8V + 0x4 + + + OUTPUT_TRG_16 + 1.1V + 0x10 + + + + + BO_VDD1P1 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD1P1 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 1p1 regulator + 18 + 1 + read-write + + + SELREF_WEAK_LINREG + Selects the source for the reference voltage of the weak 1p1 regulator. + 19 + 1 + read-write + + + SELREF_WEAK_LINREG_0 + Weak-linreg output tracks low-power-bandgap voltage + 0 + + + SELREF_WEAK_LINREG_1 + Weak-linreg output tracks VDD_SOC_IN voltage + 0x1 + + + + + + + REG_3P0 + Regulator 3P0 Register + 0x120 + 32 + read-write + 0xF74 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + VBUS_SEL + Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS + 7 + 1 + read-write + + + USB_OTG2_VBUS + Utilize VBUS OTG2 power + 0 + + + USB_OTG1_VBUS + Utilize VBUS OTG1 power + 0x1 + + + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.625V + 0 + + + OUTPUT_TRG_15 + 3.000V + 0xF + + + OUTPUT_TRG_31 + 3.400V + 0x1F + + + + + BO_VDD3P0 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD3P0 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + + + REG_3P0_SET + Regulator 3P0 Register + 0x124 + 32 + read-write + 0xF74 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + VBUS_SEL + Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS + 7 + 1 + read-write + + + USB_OTG2_VBUS + Utilize VBUS OTG2 power + 0 + + + USB_OTG1_VBUS + Utilize VBUS OTG1 power + 0x1 + + + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.625V + 0 + + + OUTPUT_TRG_15 + 3.000V + 0xF + + + OUTPUT_TRG_31 + 3.400V + 0x1F + + + + + BO_VDD3P0 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD3P0 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + + + REG_3P0_CLR + Regulator 3P0 Register + 0x128 + 32 + read-write + 0xF74 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + VBUS_SEL + Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS + 7 + 1 + read-write + + + USB_OTG2_VBUS + Utilize VBUS OTG2 power + 0 + + + USB_OTG1_VBUS + Utilize VBUS OTG1 power + 0x1 + + + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.625V + 0 + + + OUTPUT_TRG_15 + 3.000V + 0xF + + + OUTPUT_TRG_31 + 3.400V + 0x1F + + + + + BO_VDD3P0 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD3P0 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + + + REG_3P0_TOG + Regulator 3P0 Register + 0x12C + 32 + read-write + 0xF74 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output to be set by the programmed target voltage setting and internal bandgap reference + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + VBUS_SEL + Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS + 7 + 1 + read-write + + + USB_OTG2_VBUS + Utilize VBUS OTG2 power + 0 + + + USB_OTG1_VBUS + Utilize VBUS OTG1 power + 0x1 + + + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.625V + 0 + + + OUTPUT_TRG_15 + 3.000V + 0xF + + + OUTPUT_TRG_31 + 3.400V + 0x1F + + + + + BO_VDD3P0 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD3P0 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + + + REG_2P5 + Regulator 2P5 Register + 0x130 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.10V + 0 + + + OUTPUT_TRG_16 + 2.50V + 0x10 + + + OUTPUT_TRG_31 + 2.875V + 0x1F + + + + + BO_VDD2P5 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD2P5 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 2p5 regulator + 18 + 1 + read-write + + + + + REG_2P5_SET + Regulator 2P5 Register + 0x134 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.10V + 0 + + + OUTPUT_TRG_16 + 2.50V + 0x10 + + + OUTPUT_TRG_31 + 2.875V + 0x1F + + + + + BO_VDD2P5 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD2P5 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 2p5 regulator + 18 + 1 + read-write + + + + + REG_2P5_CLR + Regulator 2P5 Register + 0x138 + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.10V + 0 + + + OUTPUT_TRG_16 + 2.50V + 0x10 + + + OUTPUT_TRG_31 + 2.875V + 0x1F + + + + + BO_VDD2P5 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD2P5 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 2p5 regulator + 18 + 1 + read-write + + + + + REG_2P5_TOG + Regulator 2P5 Register + 0x13C + 32 + read-write + 0x1073 + 0xFFFFFFFF + + + ENABLE_LINREG + Control bit to enable the regulator output. + 0 + 1 + read-write + + + ENABLE_BO + Control bit to enable the brownout circuitry in the regulator. + 1 + 1 + read-write + + + ENABLE_ILIMIT + Control bit to enable the current-limit circuitry in the regulator. + 2 + 1 + read-write + + + ENABLE_PULLDOWN + Control bit to enable the pull-down circuitry in the regulator + 3 + 1 + read-write + + + BO_OFFSET + Control bits to adjust the regulator brownout offset voltage in 25mV steps + 4 + 3 + read-write + + + OUTPUT_TRG + Control bits to adjust the regulator output voltage + 8 + 5 + read-write + + + OUTPUT_TRG_0 + 2.10V + 0 + + + OUTPUT_TRG_16 + 2.50V + 0x10 + + + OUTPUT_TRG_31 + 2.875V + 0x1F + + + + + BO_VDD2P5 + Status bit that signals when a brownout is detected on the regulator output. + 16 + 1 + read-only + + + OK_VDD2P5 + Status bit that signals when the regulator output is ok. 1 = regulator output > brownout target + 17 + 1 + read-only + + + ENABLE_WEAK_LINREG + Enables the weak 2p5 regulator + 18 + 1 + read-write + + + + + REG_CORE + Digital Regulator Core Register + 0x140 + 32 + read-write + 0x482012 + 0xFFFFFFFF + + + REG0_TARG + This field defines the target voltage for the ARM core power domain + 0 + 5 + read-write + + + REG0_TARG_0 + Power gated off + 0 + + + REG0_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG0_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG0_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG0_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG0_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG0_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + + + REG2_TARG + This field defines the target voltage for the SOC power domain + 18 + 5 + read-write + + + REG2_TARG_0 + Power gated off + 0 + + + REG2_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG2_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG2_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG2_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG2_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG2_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + + + RAMP_RATE + Regulator voltage ramp rate. + 27 + 2 + read-write + + + RAMP_RATE_0 + Fast + 0 + + + RAMP_RATE_1 + Medium Fast + 0x1 + + + RAMP_RATE_2 + Medium Slow + 0x2 + + + RAMP_RATE_3 + Slow + 0x3 + + + + + FET_ODRIVE + If set, increases the gate drive on power gating FETs to reduce leakage in the off state + 29 + 1 + read-write + + + + + REG_CORE_SET + Digital Regulator Core Register + 0x144 + 32 + read-write + 0x482012 + 0xFFFFFFFF + + + REG0_TARG + This field defines the target voltage for the ARM core power domain + 0 + 5 + read-write + + + REG0_TARG_0 + Power gated off + 0 + + + REG0_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG0_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG0_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG0_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG0_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG0_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + + + REG2_TARG + This field defines the target voltage for the SOC power domain + 18 + 5 + read-write + + + REG2_TARG_0 + Power gated off + 0 + + + REG2_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG2_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG2_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG2_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG2_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG2_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + + + RAMP_RATE + Regulator voltage ramp rate. + 27 + 2 + read-write + + + RAMP_RATE_0 + Fast + 0 + + + RAMP_RATE_1 + Medium Fast + 0x1 + + + RAMP_RATE_2 + Medium Slow + 0x2 + + + RAMP_RATE_3 + Slow + 0x3 + + + + + FET_ODRIVE + If set, increases the gate drive on power gating FETs to reduce leakage in the off state + 29 + 1 + read-write + + + + + REG_CORE_CLR + Digital Regulator Core Register + 0x148 + 32 + read-write + 0x482012 + 0xFFFFFFFF + + + REG0_TARG + This field defines the target voltage for the ARM core power domain + 0 + 5 + read-write + + + REG0_TARG_0 + Power gated off + 0 + + + REG0_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG0_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG0_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG0_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG0_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG0_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + + + REG2_TARG + This field defines the target voltage for the SOC power domain + 18 + 5 + read-write + + + REG2_TARG_0 + Power gated off + 0 + + + REG2_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG2_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG2_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG2_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG2_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG2_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + + + RAMP_RATE + Regulator voltage ramp rate. + 27 + 2 + read-write + + + RAMP_RATE_0 + Fast + 0 + + + RAMP_RATE_1 + Medium Fast + 0x1 + + + RAMP_RATE_2 + Medium Slow + 0x2 + + + RAMP_RATE_3 + Slow + 0x3 + + + + + FET_ODRIVE + If set, increases the gate drive on power gating FETs to reduce leakage in the off state + 29 + 1 + read-write + + + + + REG_CORE_TOG + Digital Regulator Core Register + 0x14C + 32 + read-write + 0x482012 + 0xFFFFFFFF + + + REG0_TARG + This field defines the target voltage for the ARM core power domain + 0 + 5 + read-write + + + REG0_TARG_0 + Power gated off + 0 + + + REG0_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG0_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG0_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG0_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG0_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG0_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG0_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg0. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 5 + 4 + read-write + + + REG0_ADJ_0 + No adjustment + 0 + + + REG0_ADJ_1 + + 0.25% + 0x1 + + + REG0_ADJ_2 + + 0.50% + 0x2 + + + REG0_ADJ_3 + + 0.75% + 0x3 + + + REG0_ADJ_4 + + 1.00% + 0x4 + + + REG0_ADJ_5 + + 1.25% + 0x5 + + + REG0_ADJ_6 + + 1.50% + 0x6 + + + REG0_ADJ_7 + + 1.75% + 0x7 + + + REG0_ADJ_8 + - 0.25% + 0x8 + + + REG0_ADJ_9 + - 0.50% + 0x9 + + + REG0_ADJ_10 + - 0.75% + 0xA + + + REG0_ADJ_11 + - 1.00% + 0xB + + + REG0_ADJ_12 + - 1.25% + 0xC + + + REG0_ADJ_13 + - 1.50% + 0xD + + + REG0_ADJ_14 + - 1.75% + 0xE + + + REG0_ADJ_15 + - 2.00% + 0xF + + + + + REG1_TARG + This bit field defines the target voltage for the vpu/gpu power domain. Single bit increments reflect 25mV core voltage steps. Not all steps will make sense to use either because of input supply limitations or load operation. + 9 + 5 + read-write + + + REG1_TARG_0 + Power gated off + 0 + + + REG1_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG1_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG1_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG1_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG1_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG1_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG1_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg1. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 14 + 4 + read-write + + + REG1_ADJ_0 + No adjustment + 0 + + + REG1_ADJ_1 + + 0.25% + 0x1 + + + REG1_ADJ_2 + + 0.50% + 0x2 + + + REG1_ADJ_3 + + 0.75% + 0x3 + + + REG1_ADJ_4 + + 1.00% + 0x4 + + + REG1_ADJ_5 + + 1.25% + 0x5 + + + REG1_ADJ_6 + + 1.50% + 0x6 + + + REG1_ADJ_7 + + 1.75% + 0x7 + + + REG1_ADJ_8 + - 0.25% + 0x8 + + + REG1_ADJ_9 + - 0.50% + 0x9 + + + REG1_ADJ_10 + - 0.75% + 0xA + + + REG1_ADJ_11 + - 1.00% + 0xB + + + REG1_ADJ_12 + - 1.25% + 0xC + + + REG1_ADJ_13 + - 1.50% + 0xD + + + REG1_ADJ_14 + - 1.75% + 0xE + + + REG1_ADJ_15 + - 2.00% + 0xF + + + + + REG2_TARG + This field defines the target voltage for the SOC power domain + 18 + 5 + read-write + + + REG2_TARG_0 + Power gated off + 0 + + + REG2_TARG_1 + Target core voltage = 0.725V + 0x1 + + + REG2_TARG_2 + Target core voltage = 0.750V + 0x2 + + + REG2_TARG_3 + Target core voltage = 0.775V + 0x3 + + + REG2_TARG_16 + Target core voltage = 1.100V + 0x10 + + + REG2_TARG_30 + Target core voltage = 1.450V + 0x1E + + + REG2_TARG_31 + Power FET switched full on. No regulation. + 0x1F + + + + + REG2_ADJ + This bit field defines the adjustment bits to calibrate the target value of Reg2. The adjustment is applied on top on any adjustment applied to the global reference in the misc0 register. + 23 + 4 + read-write + + + REG2_ADJ_0 + No adjustment + 0 + + + REG2_ADJ_1 + + 0.25% + 0x1 + + + REG2_ADJ_2 + + 0.50% + 0x2 + + + REG2_ADJ_3 + + 0.75% + 0x3 + + + REG2_ADJ_4 + + 1.00% + 0x4 + + + REG2_ADJ_5 + + 1.25% + 0x5 + + + REG2_ADJ_6 + + 1.50% + 0x6 + + + REG2_ADJ_7 + + 1.75% + 0x7 + + + REG2_ADJ_8 + - 0.25% + 0x8 + + + REG2_ADJ_9 + - 0.50% + 0x9 + + + REG2_ADJ_10 + - 0.75% + 0xA + + + REG2_ADJ_11 + - 1.00% + 0xB + + + REG2_ADJ_12 + - 1.25% + 0xC + + + REG2_ADJ_13 + - 1.50% + 0xD + + + REG2_ADJ_14 + - 1.75% + 0xE + + + REG2_ADJ_15 + - 2.00% + 0xF + + + + + RAMP_RATE + Regulator voltage ramp rate. + 27 + 2 + read-write + + + RAMP_RATE_0 + Fast + 0 + + + RAMP_RATE_1 + Medium Fast + 0x1 + + + RAMP_RATE_2 + Medium Slow + 0x2 + + + RAMP_RATE_3 + Slow + 0x3 + + + + + FET_ODRIVE + If set, increases the gate drive on power gating FETs to reduce leakage in the off state + 29 + 1 + read-write + + + + + MISC0 + Miscellaneous Register 0 + 0x150 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + no description available + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + SUSPEND (DSM) + 0 + + + STANDBY + Analog regulators are ON. + 0x1 + + + STOP_MODE_CONFIG_2 + STOP (lower power) + 0x2 + + + STOP_MODE_CONFIG_3 + STOP (very lower power) + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_SET + Miscellaneous Register 0 + 0x154 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + no description available + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + SUSPEND (DSM) + 0 + + + STANDBY + Analog regulators are ON. + 0x1 + + + STOP_MODE_CONFIG_2 + STOP (lower power) + 0x2 + + + STOP_MODE_CONFIG_3 + STOP (very lower power) + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_CLR + Miscellaneous Register 0 + 0x158 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + no description available + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + SUSPEND (DSM) + 0 + + + STANDBY + Analog regulators are ON. + 0x1 + + + STOP_MODE_CONFIG_2 + STOP (lower power) + 0x2 + + + STOP_MODE_CONFIG_3 + STOP (very lower power) + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_TOG + Miscellaneous Register 0 + 0x15C + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + no description available + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable. 1 - Stable. + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + SUSPEND (DSM) + 0 + + + STANDBY + Analog regulators are ON. + 0x1 + + + STOP_MODE_CONFIG_2 + STOP (lower power) + 0x2 + + + STOP_MODE_CONFIG_3 + STOP (very lower power) + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC1 + Miscellaneous Register 1 + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b.Not related to PMU. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_SET + Miscellaneous Register 1 + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b.Not related to PMU. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_CLR + Miscellaneous Register 1 + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b.Not related to PMU. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC1_TOG + Miscellaneous Register 1 + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + LVDS1_CLK_SEL + This field selects the clk to be routed to anaclk1/1b.Not related to PMU. + 0 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + + + LVDS2_CLK_SEL + This field selects the clk to be routed to anaclk2/2b.Not related to PMU. + 5 + 5 + read-write + + + ARM_PLL + Arm PLL + 0 + + + SYS_PLL + System PLL + 0x1 + + + PFD4 + ref_pfd4_clk == pll2_pfd0_clk + 0x2 + + + PFD5 + ref_pfd5_clk == pll2_pfd1_clk + 0x3 + + + PFD6 + ref_pfd6_clk == pll2_pfd2_clk + 0x4 + + + PFD7 + ref_pfd7_clk == pll2_pfd3_clk + 0x5 + + + AUDIO_PLL + Audio PLL + 0x6 + + + VIDEO_PLL + Video PLL + 0x7 + + + MLB_PLL + MLB PLL + 0x8 + + + ETHERNET_REF + ethernet ref clock (ENET_PLL) + 0x9 + + + PCIE_REF + PCIe ref clock (125M) + 0xA + + + SATA_REF + SATA ref clock (100M) + 0xB + + + USB1_PLL + USB1 PLL clock + 0xC + + + USB2_PLL + USB2 PLL clock + 0xD + + + PFD0 + ref_pfd0_clk == pll3_pfd0_clk + 0xE + + + PFD1 + ref_pfd1_clk == pll3_pfd1_clk + 0xF + + + PFD2 + ref_pfd2_clk == pll3_pfd2_clk + 0x10 + + + PFD3 + ref_pfd3_clk == pll3_pfd3_clk + 0x11 + + + XTAL + xtal (24M) + 0x12 + + + LVDS1 + LVDS1 (loopback) + 0x13 + + + LVDS2 + LVDS2 (not useful) + 0x14 + + + + + LVDSCLK1_OBEN + This enables the LVDS output buffer for anaclk1/1b + 10 + 1 + read-write + + + LVDSCLK2_OBEN + This enables the LVDS output buffer for anaclk2/2b + 11 + 1 + read-write + + + LVDSCLK1_IBEN + This enables the LVDS input buffer for anaclk1/1b + 12 + 1 + read-write + + + LVDSCLK2_IBEN + This enables the LVDS input buffer for anaclk2/2b + 13 + 1 + read-write + + + PFD_480_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off + 16 + 1 + read-write + + + PFD_528_AUTOGATE_EN + This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off + 17 + 1 + read-write + + + IRQ_TEMPPANIC + This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature + 27 + 1 + read-write + oneToClear + + + IRQ_TEMPLOW + This status bit is set to one when the temperature sensor low interrupt asserts for low temperature + 28 + 1 + read-write + oneToClear + + + IRQ_TEMPHIGH + This status bit is set to one when the temperature sensor high interrupt asserts for high temperature + 29 + 1 + read-write + oneToClear + + + IRQ_ANA_BO + This status bit is set to one when when any of the analog regulator brownout interrupts assert + 30 + 1 + read-write + oneToClear + + + IRQ_DIG_BO + This status bit is set to one when when any of the digital regulator brownout interrupts assert + 31 + 1 + read-write + oneToClear + + + + + MISC2 + Miscellaneous Control Register + 0x170 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit. + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection. + 5 + 1 + read-write + + + PLL3_disable + Default value of "0" + 7 + 1 + read-write + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit. + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection. + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock). + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock). + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_SET + Miscellaneous Control Register + 0x174 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit. + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection. + 5 + 1 + read-write + + + PLL3_disable + Default value of "0" + 7 + 1 + read-write + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit. + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection. + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock). + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock). + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_CLR + Miscellaneous Control Register + 0x178 + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit. + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection. + 5 + 1 + read-write + + + PLL3_disable + Default value of "0" + 7 + 1 + read-write + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit. + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection. + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock). + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock). + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + MISC2_TOG + Miscellaneous Control Register + 0x17C + 32 + read-write + 0x272727 + 0xFFFFFFFF + + + REG0_BO_OFFSET + This field defines the brown out voltage offset for the CORE power domain + 0 + 3 + read-only + + + REG0_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG0_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG0_BO_STATUS + Reg0 brownout status bit. + 3 + 1 + read-only + + + REG0_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG0_ENABLE_BO + Enables the brownout detection. + 5 + 1 + read-write + + + PLL3_disable + Default value of "0" + 7 + 1 + read-write + + + REG1_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 8 + 3 + read-only + + + REG1_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG1_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG1_BO_STATUS + Reg1 brownout status bit. + 11 + 1 + read-only + + + REG1_BO_STATUS_1 + Brownout, supply is below target minus brownout offset. + 0x1 + + + + + REG1_ENABLE_BO + Enables the brownout detection. + 13 + 1 + read-write + + + AUDIO_DIV_LSB + LSB of Post-divider for Audio PLL + 15 + 1 + read-write + + + AUDIO_DIV_LSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_LSB_1 + divide by 2 + 0x1 + + + + + REG2_BO_OFFSET + This field defines the brown out voltage offset for the xPU power domain + 16 + 3 + read-only + + + REG2_BO_OFFSET_4 + Brownout offset = 0.100V + 0x4 + + + REG2_BO_OFFSET_7 + Brownout offset = 0.175V + 0x7 + + + + + REG2_BO_STATUS + Reg2 brownout status bit. + 19 + 1 + read-only + + + REG2_ENABLE_BO + Enables the brownout detection. + 21 + 1 + read-write + + + REG2_OK + Signals that the voltage is above the brownout level for the SOC supply + 22 + 1 + read-only + + + AUDIO_DIV_MSB + MSB of Post-divider for Audio PLL + 23 + 1 + read-write + + + AUDIO_DIV_MSB_0 + divide by 1 (Default) + 0 + + + AUDIO_DIV_MSB_1 + divide by 2 + 0x1 + + + + + REG0_STEP_TIME + Number of clock periods (24MHz clock). + 24 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG1_STEP_TIME + Number of clock periods (24MHz clock). + 26 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + REG2_STEP_TIME + Number of clock periods (24MHz clock). + 28 + 2 + read-write + + + 64_CLOCKS + 64 + 0 + + + 128_CLOCKS + 128 + 0x1 + + + 256_CLOCKS + 256 + 0x2 + + + 512_CLOCKS + 512 + 0x3 + + + + + VIDEO_DIV + Post-divider for video + 30 + 2 + read-write + + + VIDEO_DIV_0 + divide by 1 (Default) + 0 + + + VIDEO_DIV_1 + divide by 2 + 0x1 + + + VIDEO_DIV_2 + divide by 1 + 0x2 + + + VIDEO_DIV_3 + divide by 4 + 0x3 + + + + + + + + + TEMPMON + Temperature Monitor + CCM_ANALOG + TEMPMON + TEMPMON_ + 0x400D8000 + + 0 + 0x2A0 + registers + + + TEMP_LOW_HIGH + 63 + + + TEMP_PANIC + 64 + + + + TEMPSENSE0 + Tempsensor Control Register 0 + 0x180 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field + 20 + 12 + read-write + + + + + TEMPSENSE0_SET + Tempsensor Control Register 0 + 0x184 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field + 20 + 12 + read-write + + + + + TEMPSENSE0_CLR + Tempsensor Control Register 0 + 0x188 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field + 20 + 12 + read-write + + + + + TEMPSENSE0_TOG + Tempsensor Control Register 0 + 0x18C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + POWER_DOWN + This bit powers down the temperature sensor. + 0 + 1 + read-write + + + POWER_UP + Enable power to the temperature sensor. + 0 + + + POWER_DOWN + Power down the temperature sensor. + 0x1 + + + + + MEASURE_TEMP + Starts the measurement process + 1 + 1 + read-write + + + STOP + Do not start the measurement process. + 0 + + + START + Start the measurement process. + 0x1 + + + + + FINISHED + Indicates that the latest temp is valid + 2 + 1 + read-only + + + INVALID + Last measurement is not ready yet. + 0 + + + VALID + Last measurement is valid. + 0x1 + + + + + TEMP_CNT + This bit field contains the last measured temperature count. + 8 + 12 + read-only + + + ALARM_VALUE + This bit field contains the temperature count (raw sensor output) that will generate a high alarm when TEMP_CNT is smaller than this field + 20 + 12 + read-write + + + + + TEMPSENSE1 + Tempsensor Control Register 1 + 0x190 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE1_SET + Tempsensor Control Register 1 + 0x194 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE1_CLR + Tempsensor Control Register 1 + 0x198 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE1_TOG + Tempsensor Control Register 1 + 0x19C + 32 + read-write + 0x1 + 0xFFFFFFFF + + + MEASURE_FREQ + This bits determines how many RTC clocks to wait before automatically repeating a temperature measurement + 0 + 16 + read-write + + + + + TEMPSENSE2 + Tempsensor Control Register 2 + 0x290 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field + 16 + 12 + read-write + + + + + TEMPSENSE2_SET + Tempsensor Control Register 2 + 0x294 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field + 16 + 12 + read-write + + + + + TEMPSENSE2_CLR + Tempsensor Control Register 2 + 0x298 + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field + 16 + 12 + read-write + + + + + TEMPSENSE2_TOG + Tempsensor Control Register 2 + 0x29C + 32 + read-write + 0 + 0xFFFFFFFF + + + LOW_ALARM_VALUE + This bit field contains the temperature count that will generate a low alarm interrupt when the field is exceeded by TEMP_CNT + 0 + 12 + read-write + + + PANIC_ALARM_VALUE + This bit field contains the temperature count that will generate a panic interrupt when TEMP_CNT is smaller than this field + 16 + 12 + read-write + + + + + + + USB_ANALOG + USB Analog + CCM_ANALOG + USB_ANALOG + USB_ANALOG_ + 0x400D8000 + + 0 + 0x264 + registers + + + + USB1_VBUS_DETECT + USB VBUS Detect Register + 0x1A0 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB1_VBUS_DETECT_SET + USB VBUS Detect Register + 0x1A4 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB1_VBUS_DETECT_CLR + USB VBUS Detect Register + 0x1A8 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB1_VBUS_DETECT_TOG + USB VBUS Detect Register + 0x1AC + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB1_CHRG_DETECT + USB Charger Detect Register + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_CHRG_DETECT_SET + USB Charger Detect Register + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_CHRG_DETECT_CLR + USB Charger Detect Register + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_CHRG_DETECT_TOG + USB Charger Detect Register + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB1_VBUS_DETECT_STAT + USB VBUS Detect Status Register + 0x1C0 + 32 + read-only + 0 + 0xFFFFFFFF + + + SESSEND + Session End for USB OTG + 0 + 1 + read-only + + + BVALID + Indicates VBus is valid for a B-peripheral + 1 + 1 + read-only + + + AVALID + Indicates VBus is valid for a A-peripheral + 2 + 1 + read-only + + + VBUS_VALID + VBus valid for USB OTG + 3 + 1 + read-only + + + + + USB1_CHRG_DETECT_STAT + USB Charger Detect Status Register + 0x1D0 + 32 + read-only + 0 + 0xFFFFFFFF + + + PLUG_CONTACT + State of the USB plug contact detector. + 0 + 1 + read-only + + + NO_CONTACT + The USB plug has not made contact. + 0 + + + GOOD_CONTACT + The USB plug has made good contact. + 0x1 + + + + + CHRG_DETECTED + State of charger detection. This bit is a read only version of the state of the analog signal. + 1 + 1 + read-only + + + CHARGER_NOT_PRESENT + The USB port is not connected to a charger. + 0 + + + CHARGER_PRESENT + A charger (either a dedicated charger or a host charger) is connected to the USB port. + 0x1 + + + + + DM_STATE + DM line state output of the charger detector. + 2 + 1 + read-only + + + DP_STATE + DP line state output of the charger detector. + 3 + 1 + read-only + + + + + USB1_MISC + USB Misc Register + 0x1F0 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB1_MISC_SET + USB Misc Register + 0x1F4 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB1_MISC_CLR + USB Misc Register + 0x1F8 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB1_MISC_TOG + USB Misc Register + 0x1FC + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB2_VBUS_DETECT + USB VBUS Detect Register + 0x200 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB2_VBUS_DETECT_SET + USB VBUS Detect Register + 0x204 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB2_VBUS_DETECT_CLR + USB VBUS Detect Register + 0x208 + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB2_VBUS_DETECT_TOG + USB VBUS Detect Register + 0x20C + 32 + read-write + 0x100004 + 0xFFFFFFFF + + + VBUSVALID_THRESH + Set the threshold for the VBUSVALID comparator + 0 + 3 + read-write + + + 4V0 + 4.0V + 0 + + + 4V1 + 4.1V + 0x1 + + + 4V2 + 4.2V + 0x2 + + + 4V3 + 4.3V + 0x3 + + + 4V4 + 4.4V (default) + 0x4 + + + 4V5 + 4.5V + 0x5 + + + 4V6 + 4.6V + 0x6 + + + 4V7 + 4.7V + 0x7 + + + + + VBUSVALID_PWRUP_CMPS + Powers up comparators for vbus_valid detector. + 20 + 1 + read-write + + + DISCHARGE_VBUS + USB OTG discharge VBUS. + 26 + 1 + read-write + + + CHARGE_VBUS + USB OTG charge VBUS. + 27 + 1 + read-write + + + + + USB2_CHRG_DETECT + USB Charger Detect Register + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_CHRG_DETECT_SET + USB Charger Detect Register + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_CHRG_DETECT_CLR + USB Charger Detect Register + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_CHRG_DETECT_TOG + USB Charger Detect Register + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + CHK_CONTACT + Check the contact of USB plug + 18 + 1 + read-write + + + NO_CHECK + Do not check the contact of USB plug. + 0 + + + CHECK + Check whether the USB plug has been in contact with each other + 0x1 + + + + + CHK_CHRG_B + Check the charger connection + 19 + 1 + read-write + + + CHECK + Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. + 0 + + + NO_CHECK + Do not check whether a charger is connected to the USB port. + 0x1 + + + + + EN_B + Control the charger detector. + 20 + 1 + read-write + + + ENABLE + Enable the charger detector. + 0 + + + DISABLE + Disable the charger detector. + 0x1 + + + + + + + USB2_VBUS_DETECT_STAT + USB VBUS Detect Status Register + 0x220 + 32 + read-only + 0 + 0xFFFFFFFF + + + SESSEND + Session End for USB OTG + 0 + 1 + read-only + + + BVALID + Indicates VBus is valid for a B-peripheral + 1 + 1 + read-only + + + AVALID + Indicates VBus is valid for a A-peripheral + 2 + 1 + read-only + + + VBUS_VALID + VBus valid for USB OTG + 3 + 1 + read-only + + + + + USB2_CHRG_DETECT_STAT + USB Charger Detect Status Register + 0x230 + 32 + read-only + 0 + 0xFFFFFFFF + + + PLUG_CONTACT + State of the USB plug contact detector. + 0 + 1 + read-only + + + NO_CONTACT + The USB plug has not made contact. + 0 + + + GOOD_CONTACT + The USB plug has made good contact. + 0x1 + + + + + CHRG_DETECTED + State of charger detection. This bit is a read only version of the state of the analog signal. + 1 + 1 + read-only + + + CHARGER_NOT_PRESENT + The USB port is not connected to a charger. + 0 + + + CHARGER_PRESENT + A charger (either a dedicated charger or a host charger) is connected to the USB port. + 0x1 + + + + + DM_STATE + DM line state output of the charger detector. + 2 + 1 + read-only + + + DP_STATE + DP line state output of the charger detector. + 3 + 1 + read-only + + + + + USB2_MISC + USB Misc Register + 0x250 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB2_MISC_SET + USB Misc Register + 0x254 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB2_MISC_CLR + USB Misc Register + 0x258 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + USB2_MISC_TOG + USB Misc Register + 0x25C + 32 + read-write + 0x2 + 0xFFFFFFFF + + + HS_USE_EXTERNAL_R + Use external resistor to generate the current bias for the high speed transmitter + 0 + 1 + read-write + + + EN_DEGLITCH + Enable the deglitching circuit of the USB PLL output. + 1 + 1 + read-write + + + EN_CLK_UTMI + Enables the clk to the UTMI block. + 30 + 1 + read-write + + + + + DIGPROG + Chip Silicon Version + 0x260 + 32 + read-only + 0x6C0000 + 0xFFFFFFFF + + + SILICON_REVISION + Chip silicon revision + 0 + 32 + read-only + + + SILICON_REVISION_7077888 + Silicon revision 1.0 + 0x6C0000 + + + + + + + + + XTALOSC24M + XTALOSC24M + CCM_ANALOG + XTALOSC24M + XTALOSC24M_ + 0x400D8000 + + 0 + 0x2D0 + registers + + + + MISC0 + Miscellaneous Register 0 + 0x150 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to oscillator. + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode.Not related to oscillator. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable. + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. Not related to oscillator. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_SET + Miscellaneous Register 0 + 0x154 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to oscillator. + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode.Not related to oscillator. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable. + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. Not related to oscillator. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_CLR + Miscellaneous Register 0 + 0x158 + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to oscillator. + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode.Not related to oscillator. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable. + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. Not related to oscillator. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + MISC0_TOG + Miscellaneous Register 0 + 0x15C + 32 + read-write + 0x4000000 + 0xFFFFFFFF + + + REFTOP_PWD + Control bit to power-down the analog bandgap reference circuitry + 0 + 1 + read-write + + + REFTOP_SELFBIASOFF + Control bit to disable the self-bias circuit in the analog bandgap + 3 + 1 + read-write + + + REFTOP_SELFBIASOFF_0 + Uses coarse bias currents for startup + 0 + + + REFTOP_SELFBIASOFF_1 + Uses bandgap-based bias currents for best performance. + 0x1 + + + + + REFTOP_VBGADJ + Not related to oscillator. + 4 + 3 + read-write + + + REFTOP_VBGADJ_0 + Nominal VBG + 0 + + + REFTOP_VBGADJ_1 + VBG+0.78% + 0x1 + + + REFTOP_VBGADJ_2 + VBG+1.56% + 0x2 + + + REFTOP_VBGADJ_3 + VBG+2.34% + 0x3 + + + REFTOP_VBGADJ_4 + VBG-0.78% + 0x4 + + + REFTOP_VBGADJ_5 + VBG-1.56% + 0x5 + + + REFTOP_VBGADJ_6 + VBG-2.34% + 0x6 + + + REFTOP_VBGADJ_7 + VBG-3.12% + 0x7 + + + + + REFTOP_VBGUP + Status bit that signals the analog bandgap voltage is up and stable + 7 + 1 + read-write + + + STOP_MODE_CONFIG + Configure the analog behavior in stop mode.Not related to oscillator. + 10 + 2 + read-write + + + STOP_MODE_CONFIG_0 + All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off; + 0 + + + STOP_MODE_CONFIG_1 + Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off; + 0x1 + + + STOP_MODE_CONFIG_2 + XtalOsc=off, RCOsc=on, Old BG=on, New BG=off. + 0x2 + + + STOP_MODE_CONFIG_3 + XtalOsc=off, RCOsc=on, Old BG=off, New BG=on. + 0x3 + + + + + DISCON_HIGH_SNVS + This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN. + 12 + 1 + read-write + + + DISCON_HIGH_SNVS_0 + Turn on the switch + 0 + + + DISCON_HIGH_SNVS_1 + Turn off the switch + 0x1 + + + + + OSC_I + This field determines the bias current in the 24MHz oscillator + 13 + 2 + read-write + + + NOMINAL + Nominal + 0 + + + MINUS_12_5_PERCENT + Decrease current by 12.5% + 0x1 + + + MINUS_25_PERCENT + Decrease current by 25.0% + 0x2 + + + MINUS_37_5_PERCENT + Decrease current by 37.5% + 0x3 + + + + + OSC_XTALOK + Status bit that signals that the output of the 24-MHz crystal oscillator is stable + 15 + 1 + read-only + + + OSC_XTALOK_EN + This bit enables the detector that signals when the 24MHz crystal oscillator is stable. + 16 + 1 + read-write + + + CLKGATE_CTRL + This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block + 25 + 1 + read-write + + + ALLOW_AUTO_GATE + Allow the logic to automatically gate the clock when the XTAL is powered down. + 0 + + + NO_AUTO_GATE + Prevent the logic from ever gating off the clock. + 0x1 + + + + + CLKGATE_DELAY + This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block + 26 + 3 + read-write + + + CLKGATE_DELAY_0 + 0.5ms + 0 + + + CLKGATE_DELAY_1 + 1.0ms + 0x1 + + + CLKGATE_DELAY_2 + 2.0ms + 0x2 + + + CLKGATE_DELAY_3 + 3.0ms + 0x3 + + + CLKGATE_DELAY_4 + 4.0ms + 0x4 + + + CLKGATE_DELAY_5 + 5.0ms + 0x5 + + + CLKGATE_DELAY_6 + 6.0ms + 0x6 + + + CLKGATE_DELAY_7 + 7.0ms + 0x7 + + + + + RTC_XTAL_SOURCE + This field indicates which chip source is being used for the rtc clock. + 29 + 1 + read-only + + + RTC_XTAL_SOURCE_0 + Internal ring oscillator + 0 + + + RTC_XTAL_SOURCE_1 + RTC_XTAL + 0x1 + + + + + XTAL_24M_PWD + This field powers down the 24M crystal oscillator if set true. + 30 + 1 + read-write + + + VID_PLL_PREDIV + Predivider for the source clock of the PLL's. Not related to oscillator. + 31 + 1 + read-write + + + VID_PLL_PREDIV_0 + Divide by 1 + 0 + + + VID_PLL_PREDIV_1 + Divide by 2 + 0x1 + + + + + + + LOWPWR_CTRL + XTAL OSC (LP) Control Register + 0x270 + 32 + read-write + 0x4001 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + OSC_SEL + Select the source for the 24MHz clock. + 4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. Not related to oscillator. + 5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. Not related to oscillator. + 6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. Not related to oscillator. + 7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. Not related to oscillator. + 8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. Not related to oscillator. + 9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override. Test purpose only Not related to oscillator. + 10 + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. Not related to oscillator. + 11 + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 13 + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 14 + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. + 16 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 17 + 1 + read-write + + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + + + + + LOWPWR_CTRL_SET + XTAL OSC (LP) Control Register + 0x274 + 32 + read-write + 0x4001 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + OSC_SEL + Select the source for the 24MHz clock. + 4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. Not related to oscillator. + 5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. Not related to oscillator. + 6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. Not related to oscillator. + 7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. Not related to oscillator. + 8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. Not related to oscillator. + 9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override. Test purpose only Not related to oscillator. + 10 + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. Not related to oscillator. + 11 + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 13 + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 14 + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. + 16 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 17 + 1 + read-write + + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + + + + + LOWPWR_CTRL_CLR + XTAL OSC (LP) Control Register + 0x278 + 32 + read-write + 0x4001 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + OSC_SEL + Select the source for the 24MHz clock. + 4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. Not related to oscillator. + 5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. Not related to oscillator. + 6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. Not related to oscillator. + 7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. Not related to oscillator. + 8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. Not related to oscillator. + 9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override. Test purpose only Not related to oscillator. + 10 + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. Not related to oscillator. + 11 + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 13 + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 14 + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. + 16 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 17 + 1 + read-write + + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + + + + + LOWPWR_CTRL_TOG + XTAL OSC (LP) Control Register + 0x27C + 32 + read-write + 0x4001 + 0xFFFFFFFF + + + RC_OSC_EN + RC Osc. enable control. + 0 + 1 + read-write + + + RC_OSC_EN_0 + Use XTAL OSC to source the 24MHz clock + 0 + + + RC_OSC_EN_1 + Use RC OSC + 0x1 + + + + + OSC_SEL + Select the source for the 24MHz clock. + 4 + 1 + read-write + + + OSC_SEL_0 + XTAL OSC + 0 + + + OSC_SEL_1 + RC OSC + 0x1 + + + + + LPBG_SEL + Bandgap select. Not related to oscillator. + 5 + 1 + read-write + + + LPBG_SEL_0 + Normal power bandgap + 0 + + + LPBG_SEL_1 + Low power bandgap + 0x1 + + + + + LPBG_TEST + Low power bandgap test bit. Not related to oscillator. + 6 + 1 + read-write + + + REFTOP_IBIAS_OFF + Low power reftop ibias disable. Not related to oscillator. + 7 + 1 + read-write + + + L1_PWRGATE + L1 power gate control. Used as software override. Not related to oscillator. + 8 + 1 + read-write + + + L2_PWRGATE + L2 power gate control. Used as software override. Not related to oscillator. + 9 + 1 + read-write + + + CPU_PWRGATE + CPU power gate control. Used as software override. Test purpose only Not related to oscillator. + 10 + 1 + read-write + + + DISPLAY_PWRGATE + Display logic power gate control. Used as software override. Not related to oscillator. + 11 + 1 + read-write + + + RCOSC_CG_OVERRIDE + For debug purposes only + 13 + 1 + read-write + + + XTALOSC_PWRUP_DELAY + Specifies the time delay between when the 24MHz xtal is powered up until it is stable and ready to use + 14 + 2 + read-write + + + XTALOSC_PWRUP_DELAY_0 + 0.25ms + 0 + + + XTALOSC_PWRUP_DELAY_1 + 0.5ms + 0x1 + + + XTALOSC_PWRUP_DELAY_2 + 1ms + 0x2 + + + XTALOSC_PWRUP_DELAY_3 + 2ms + 0x3 + + + + + XTALOSC_PWRUP_STAT + Status of the 24MHz xtal oscillator. + 16 + 1 + read-only + + + XTALOSC_PWRUP_STAT_0 + Not stable + 0 + + + XTALOSC_PWRUP_STAT_1 + Stable and ready to use + 0x1 + + + + + MIX_PWRGATE + Display power gate control. Used as software mask. Set to zero to force ungated. + 17 + 1 + read-write + + + GPU_PWRGATE + GPU power gate control. Used as software mask. Set to zero to force ungated. + 18 + 1 + read-write + + + + + OSC_CONFIG0 + XTAL OSC Configuration 0 Register + 0x2A0 + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 12 + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 16 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 24 + 8 + read-write + + + + + OSC_CONFIG0_SET + XTAL OSC Configuration 0 Register + 0x2A4 + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 12 + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 16 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 24 + 8 + read-write + + + + + OSC_CONFIG0_CLR + XTAL OSC Configuration 0 Register + 0x2A8 + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 12 + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 16 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 24 + 8 + read-write + + + + + OSC_CONFIG0_TOG + XTAL OSC Configuration 0 Register + 0x2AC + 32 + read-write + 0x1020 + 0xFFFFFFFF + + + START + Start/stop bit for the RC tuning calculation logic. If stopped the tuning logic is reset. + 0 + 1 + read-write + + + ENABLE + Enables the tuning logic to calculate new RC tuning values + 1 + 1 + read-write + + + BYPASS + Bypasses any calculated RC tuning value and uses the programmed register value. + 2 + 1 + read-write + + + INVERT + Invert the stepping of the calculated RC tuning value. + 3 + 1 + read-write + + + RC_OSC_PROG + RC osc. tuning values. + 4 + 8 + read-write + + + HYST_PLUS + Positive hysteresis value + 12 + 4 + read-write + + + HYST_MINUS + Negative hysteresis value + 16 + 4 + read-write + + + RC_OSC_PROG_CUR + The current tuning value in use. + 24 + 8 + read-write + + + + + OSC_CONFIG1 + XTAL OSC Configuration 1 Register + 0x2B0 + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 20 + 12 + read-write + + + + + OSC_CONFIG1_SET + XTAL OSC Configuration 1 Register + 0x2B4 + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 20 + 12 + read-write + + + + + OSC_CONFIG1_CLR + XTAL OSC Configuration 1 Register + 0x2B8 + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 20 + 12 + read-write + + + + + OSC_CONFIG1_TOG + XTAL OSC Configuration 1 Register + 0x2BC + 32 + read-write + 0x2EE + 0xFFFFFFFF + + + COUNT_RC_TRG + The target count used to tune the RC OSC frequency + 0 + 12 + read-write + + + COUNT_RC_CUR + The current tuning value in use. + 20 + 12 + read-write + + + + + OSC_CONFIG2 + XTAL OSC Configuration 2 Register + 0x2C0 + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the 1MHz clock frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 16 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output + 17 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32kHz period + 31 + 1 + read-write + + + + + OSC_CONFIG2_SET + XTAL OSC Configuration 2 Register + 0x2C4 + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the 1MHz clock frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 16 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output + 17 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32kHz period + 31 + 1 + read-write + + + + + OSC_CONFIG2_CLR + XTAL OSC Configuration 2 Register + 0x2C8 + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the 1MHz clock frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 16 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output + 17 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32kHz period + 31 + 1 + read-write + + + + + OSC_CONFIG2_TOG + XTAL OSC Configuration 2 Register + 0x2CC + 32 + read-write + 0x102E2 + 0xFFFFFFFF + + + COUNT_1M_TRG + The target count used to tune the 1MHz clock frequency + 0 + 12 + read-write + + + ENABLE_1M + Enable the 1MHz clock output. 0 - disabled; 1 - enabled. + 16 + 1 + read-write + + + MUX_1M + Mux the corrected or uncorrected 1MHz clock to the output + 17 + 1 + read-write + + + CLK_1M_ERR_FL + Flag indicates that the count_1m count wasn't reached within 1 32kHz period + 31 + 1 + read-write + + + + + + + USBPHY1 + USBPHY Register Reference Index + USBPHY + USBPHY1_ + USBPHY + 0x400D9000 + + 0 + 0x84 + registers + + + USB_PHY1 + 65 + + + + PWD + USB PHY Power-Down Register + 0 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 10 + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 11 + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 17 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 18 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 19 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 20 + 1 + read-write + + + RSVD2 + Reserved. + 21 + 11 + read-only + + + + + PWD_SET + USB PHY Power-Down Register + 0x4 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 10 + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 11 + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 17 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 18 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 19 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 20 + 1 + read-write + + + RSVD2 + Reserved. + 21 + 11 + read-only + + + + + PWD_CLR + USB PHY Power-Down Register + 0x8 + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 10 + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 11 + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 17 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 18 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 19 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 20 + 1 + read-write + + + RSVD2 + Reserved. + 21 + 11 + read-only + + + + + PWD_TOG + USB PHY Power-Down Register + 0xC + 32 + read-write + 0x1E1C00 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 10 + read-only + + + TXPWDFS + 0 = Normal operation + 10 + 1 + read-write + + + TXPWDIBIAS + 0 = Normal operation + 11 + 1 + read-write + + + TXPWDV2I + 0 = Normal operation + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 4 + read-only + + + RXPWDENV + 0 = Normal operation + 17 + 1 + read-write + + + RXPWD1PT1 + 0 = Normal operation + 18 + 1 + read-write + + + RXPWDDIFF + 0 = Normal operation + 19 + 1 + read-write + + + RXPWDRX + 0 = Normal operation + 20 + 1 + read-write + + + RSVD2 + Reserved. + 21 + 11 + read-only + + + + + TX + USB PHY Transmitter Control Register + 0x10 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 12 + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 16 + 4 + read-write + + + RSVD2 + Reserved. + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 26 + 3 + read-write + + + RSVD5 + Reserved. + 29 + 3 + read-only + + + + + TX_SET + USB PHY Transmitter Control Register + 0x14 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 12 + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 16 + 4 + read-write + + + RSVD2 + Reserved. + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 26 + 3 + read-write + + + RSVD5 + Reserved. + 29 + 3 + read-only + + + + + TX_CLR + USB PHY Transmitter Control Register + 0x18 + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 12 + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 16 + 4 + read-write + + + RSVD2 + Reserved. + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 26 + 3 + read-write + + + RSVD5 + Reserved. + 29 + 3 + read-only + + + + + TX_TOG + USB PHY Transmitter Control Register + 0x1C + 32 + read-write + 0x10060607 + 0xFFFFFFFF + + + D_CAL + Resistor Trimming Code: 0000 = 0.16% 0111 = Nominal 1111 = +25% + 0 + 4 + read-write + + + RSVD0 + Reserved. Note: This bit should remain clear. + 4 + 4 + read-write + + + TXCAL45DN + Decode to select a 45-Ohm resistance to the USB_DN output pin + 8 + 4 + read-write + + + RSVD1 + Reserved. Note: This bit should remain clear. + 12 + 4 + read-write + + + TXCAL45DP + Decode to select a 45-Ohm resistance to the USB_DP output pin + 16 + 4 + read-write + + + RSVD2 + Reserved. + 20 + 6 + read-only + + + USBPHY_TX_EDGECTRL + Controls the edge-rate of the current sensing transistors used in HS transmit + 26 + 3 + read-write + + + RSVD5 + Reserved. + 29 + 3 + read-only + + + + + RX + USB PHY Receiver Control Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 4 + 3 + read-write + + + RSVD1 + Reserved. + 7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 22 + 1 + read-write + + + RSVD2 + Reserved. + 23 + 9 + read-only + + + + + RX_SET + USB PHY Receiver Control Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 4 + 3 + read-write + + + RSVD1 + Reserved. + 7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 22 + 1 + read-write + + + RSVD2 + Reserved. + 23 + 9 + read-only + + + + + RX_CLR + USB PHY Receiver Control Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 4 + 3 + read-write + + + RSVD1 + Reserved. + 7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 22 + 1 + read-write + + + RSVD2 + Reserved. + 23 + 9 + read-only + + + + + RX_TOG + USB PHY Receiver Control Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ENVADJ + The ENVADJ field adjusts the trip point for the envelope detector + 0 + 3 + read-write + + + RSVD0 + Reserved. + 3 + 1 + read-only + + + DISCONADJ + The DISCONADJ field adjusts the trip point for the disconnect detector: 000 = Trip-Level Voltage is 0 + 4 + 3 + read-write + + + RSVD1 + Reserved. + 7 + 15 + read-only + + + RXDBYPASS + 0 = Normal operation + 22 + 1 + read-write + + + RSVD2 + Reserved. + 23 + 9 + read-only + + + + + CTRL + USB PHY General Control Register + 0x30 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 13 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 15 + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 17 + 1 + read-write + + + ENAUTO_PWRON_PLL + Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 21 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 23 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + RSVD1 + Reserved. + 25 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 31 + 1 + read-write + + + + + CTRL_SET + USB PHY General Control Register + 0x34 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 13 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 15 + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 17 + 1 + read-write + + + ENAUTO_PWRON_PLL + Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 21 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 23 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + RSVD1 + Reserved. + 25 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 31 + 1 + read-write + + + + + CTRL_CLR + USB PHY General Control Register + 0x38 + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 13 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 15 + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 17 + 1 + read-write + + + ENAUTO_PWRON_PLL + Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 21 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 23 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + RSVD1 + Reserved. + 25 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 31 + 1 + read-write + + + + + CTRL_TOG + USB PHY General Control Register + 0x3C + 32 + read-write + 0xC0200000 + 0xFFFFFFFF + + + ENOTG_ID_CHG_IRQ + Enable OTG_ID_CHG_IRQ. + 0 + 1 + read-write + + + ENHOSTDISCONDETECT + For host mode, enables high-speed disconnect detector + 1 + 1 + read-write + + + ENIRQHOSTDISCON + Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + + + HOSTDISCONDETECT_IRQ + Indicates that the device has disconnected in high-speed mode + 3 + 1 + read-write + + + ENDEVPLUGINDETECT + For device mode, enables 200-KOhm pullups for detecting connectivity to the host. + 4 + 1 + read-write + + + DEVPLUGIN_POLARITY + For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + OTG_ID_CHG_IRQ + OTG ID change interrupt. Indicates the value of ID pin changed. + 6 + 1 + read-write + + + ENOTGIDDETECT + Enables circuit to detect resistance of MiniAB ID pin. + 7 + 1 + read-write + + + RESUMEIRQSTICKY + Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + ENIRQDEVPLUGIN + Enables interrupt for the detection of connectivity to the USB line. + 11 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 + 1 + read-write + + + DATA_ON_LRADC + Enables the LRADC to monitor USB_DP and USB_DM. This is for use in non-USB modes only. + 13 + 1 + read-write + + + ENUTMILEVEL2 + Enables UTMI+ Level2. This should be enabled if needs to support LS device + 14 + 1 + read-write + + + ENUTMILEVEL3 + Enables UTMI+ Level3 + 15 + 1 + read-write + + + ENIRQWAKEUP + Enables interrupt for the wakeup events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Indicates that there is a wakeup event + 17 + 1 + read-write + + + ENAUTO_PWRON_PLL + Enables the feature to auto-enable the POWER bit of HW_CLKCTRL_PLLxCTRL0 if there is wakeup event if USB is suspended + 18 + 1 + read-write + + + ENAUTOCLR_CLKGATE + Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended + 19 + 1 + read-write + + + ENAUTOCLR_PHY_PWD + Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended + 20 + 1 + read-write + + + ENDPDMCHG_WKUP + Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended + 21 + 1 + read-write + + + ENIDCHG_WKUP + Enables the feature to wakeup USB if ID is toggled when USB is suspended. + 22 + 1 + read-write + + + ENVBUSCHG_WKUP + Enables the feature to wakeup USB if VBUS is toggled when USB is suspended. + 23 + 1 + read-write + + + FSDLL_RST_EN + Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. + 24 + 1 + read-write + + + RSVD1 + Reserved. + 25 + 2 + read-only + + + OTG_ID_VALUE + Almost same as OTGID_STATUS in USBPHYx_STATUS Register + 27 + 1 + read-only + + + HOST_FORCE_LS_SE0 + Forces the next FS packet that is transmitted to have a EOP with LS timing + 28 + 1 + read-write + + + UTMI_SUSPENDM + Used by the PHY to indicate a powered-down state + 29 + 1 + read-only + + + CLKGATE + Gate UTMI Clocks + 30 + 1 + read-write + + + SFTRST + Writing a 1 to this bit will soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, and USBPHYx_CTRL registers + 31 + 1 + read-write + + + + + STATUS + USB PHY Status Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + RSVD0 + Reserved. + 0 + 3 + read-only + + + HOSTDISCONDETECT_STATUS + Indicates that the device has disconnected while in high-speed host mode. + 3 + 1 + read-only + + + RSVD1 + Reserved. + 4 + 2 + read-only + + + DEVPLUGIN_STATUS + Indicates that the device has been connected on the USB_DP and USB_DM lines. + 6 + 1 + read-only + + + RSVD2 + Reserved. + 7 + 1 + read-only + + + OTGID_STATUS + Indicates the results of ID pin on MiniAB plug + 8 + 1 + read-write + + + RSVD3 + Reserved. + 9 + 1 + read-only + + + RESUME_STATUS + Indicates that the host is sending a wake-up after suspend and has triggered an interrupt. + 10 + 1 + read-only + + + RSVD4 + Reserved. + 11 + 21 + read-only + + + + + DEBUG + USB PHY Debug Register + 0x50 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 4 + 2 + read-write + + + RSVD0 + Reserved. + 6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + RSVD2 + Reserved. + 21 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + RSVD3 + Reserved. + 31 + 1 + read-only + + + + + DEBUG_SET + USB PHY Debug Register + 0x54 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 4 + 2 + read-write + + + RSVD0 + Reserved. + 6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + RSVD2 + Reserved. + 21 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + RSVD3 + Reserved. + 31 + 1 + read-only + + + + + DEBUG_CLR + USB PHY Debug Register + 0x58 + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 4 + 2 + read-write + + + RSVD0 + Reserved. + 6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + RSVD2 + Reserved. + 21 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + RSVD3 + Reserved. + 31 + 1 + read-only + + + + + DEBUG_TOG + USB PHY Debug Register + 0x5C + 32 + read-write + 0x7F180000 + 0xFFFFFFFF + + + OTGIDPIOLOCK + Once OTG ID from USBPHYx_STATUS_OTGID_STATUS, use this to hold the value + 0 + 1 + read-write + + + DEBUG_INTERFACE_HOLD + Use holding registers to assist in timing for external UTMI interface. + 1 + 1 + read-write + + + HSTPULLDOWN + Set bit 3 to 1 to pull down 15-KOhm on USB_DP line + 2 + 2 + read-write + + + ENHSTPULLDOWN + Set bit 5 to 1 to override the control of the USB_DP 15-KOhm pulldown + 4 + 2 + read-write + + + RSVD0 + Reserved. + 6 + 2 + read-only + + + TX2RXCOUNT + Delay in between the end of transmit to the beginning of receive + 8 + 4 + read-write + + + ENTX2RXCOUNT + Set this bit to allow a countdown to transition in between TX and RX. + 12 + 1 + read-write + + + RSVD1 + Reserved. + 13 + 3 + read-only + + + SQUELCHRESETCOUNT + Delay in between the detection of squelch to the reset of high-speed RX. + 16 + 5 + read-write + + + RSVD2 + Reserved. + 21 + 3 + read-only + + + ENSQUELCHRESET + Set bit to allow squelch to reset high-speed receive. + 24 + 1 + read-write + + + SQUELCHRESETLENGTH + Duration of RESET in terms of the number of 480-MHz cycles. + 25 + 4 + read-write + + + HOST_RESUME_DEBUG + Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. + 29 + 1 + read-write + + + CLKGATE + Gate Test Clocks + 30 + 1 + read-write + + + RSVD3 + Reserved. + 31 + 1 + read-only + + + + + DEBUG0_STATUS + UTMI Debug Status Register 0 + 0x60 + 32 + read-only + 0 + 0xFFFFFFFF + + + LOOP_BACK_FAIL_COUNT + Running count of the failed pseudo-random generator loopback + 0 + 16 + read-only + + + UTMI_RXERROR_FAIL_COUNT + Running count of the UTMI_RXERROR. + 16 + 10 + read-only + + + SQUELCH_COUNT + Running count of the squelch reset instead of normal end for HS RX. + 26 + 6 + read-only + + + + + DEBUG1 + UTMI Debug Status Register 1 + 0x70 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 13 + 2 + read-write + + + RSVD1 + Reserved. + 15 + 17 + read-only + + + + + DEBUG1_SET + UTMI Debug Status Register 1 + 0x74 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 13 + 2 + read-write + + + RSVD1 + Reserved. + 15 + 17 + read-only + + + + + DEBUG1_CLR + UTMI Debug Status Register 1 + 0x78 + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 13 + 2 + read-write + + + RSVD1 + Reserved. + 15 + 17 + read-only + + + + + DEBUG1_TOG + UTMI Debug Status Register 1 + 0x7C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + RSVD0 + Reserved. Note: This bit should remain clear. + 0 + 13 + read-write + + + ENTAILADJVD + Delay increment of the rise of squelch: 00 = Delay is nominal 01 = Delay is +20% 10 = Delay is -20% 11 = Delay is -40% + 13 + 2 + read-write + + + RSVD1 + Reserved. + 15 + 17 + read-only + + + + + VERSION + UTMI RTL Version + 0x80 + 32 + read-only + 0x4030000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the RTL version. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR field of the RTL version. + 16 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR field of the RTL version. + 24 + 8 + read-only + + + + + + + USBPHY2 + USBPHY Register Reference Index + USBPHY + USBPHY2_ + 0x400DA000 + + 0 + 0x84 + registers + + + USB_PHY2 + 66 + + + + CSU + CSU registers + CSU + CSU_ + 0x400DC000 + + 0 + 0x35C + registers + + + CSU + 49 + + + + 32 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 + CSL%s + Config security level register + 0 + 32 + read-write + 0x330033 + 0xFFFFFFFF + + + SUR_S2 + Secure user read access control for the second slave + 0 + 1 + read-write + + + SUR_S2_0 + The secure user read access is disabled for the second slave. + 0 + + + SUR_S2_1 + The secure user read access is enabled for the second slave. + 0x1 + + + + + SSR_S2 + Secure supervisor read access control for the second slave + 1 + 1 + read-write + + + SSR_S2_0 + The secure supervisor read access is disabled for the second slave. + 0 + + + SSR_S2_1 + The secure supervisor read access is enabled for the second slave. + 0x1 + + + + + NUR_S2 + Non-secure user read access control for the second slave + 2 + 1 + read-write + + + NUR_S2_0 + The non-secure user read access is disabled for the second slave. + 0 + + + NUR_S2_1 + The non-secure user read access is enabled for the second slave. + 0x1 + + + + + NSR_S2 + Non-secure supervisor read access control for the second slave + 3 + 1 + read-write + + + NSR_S2_0 + The non-secure supervisor read access is disabled for the second slave. + 0 + + + NSR_S2_1 + The non-secure supervisor read access is enabled for the second slave. + 0x1 + + + + + SUW_S2 + Secure user write access control for the second slave + 4 + 1 + read-write + + + SUW_S2_0 + The secure user write access is disabled for the second slave. + 0 + + + SUW_S2_1 + The secure user write access is enabled for the second slave. + 0x1 + + + + + SSW_S2 + Secure supervisor write access control for the second slave + 5 + 1 + read-write + + + SSW_S2_0 + The secure supervisor write access is disabled for the second slave. + 0 + + + SSW_S2_1 + The secure supervisor write access is enabled for the second slave. + 0x1 + + + + + NUW_S2 + Non-secure user write access control for the second slave + 6 + 1 + read-write + + + NUW_S2_0 + The non-secure user write access is disabled for the second slave. + 0 + + + NUW_S2_1 + The non-secure user write access is enabled for the second slave. + 0x1 + + + + + NSW_S2 + Non-secure supervisor write access control for the second slave + 7 + 1 + read-write + + + NSW_S2_0 + The non-secure supervisor write access is disabled for the second slave. + 0 + + + NSW_S2_1 + The non-secure supervisor write access is enabled for the second slave. + 0x1 + + + + + LOCK_S2 + The lock bit corresponding to the second slave. It is written by the secure software. + 8 + 1 + read-write + + + LOCK_S2_0 + Not locked. Bits 7-0 can be written by the software. + 0 + + + LOCK_S2_1 + Bits 7-0 are locked and cannot be written by the software + 0x1 + + + + + SUR_S1 + Secure user read access control for the first slave + 16 + 1 + read-write + + + SUR_S1_0 + The secure user read access is disabled for the first slave. + 0 + + + SUR_S1_1 + The secure user read access is enabled for the first slave. + 0x1 + + + + + SSR_S1 + Secure supervisor read access control for the first slave + 17 + 1 + read-write + + + SSR_S1_0 + The secure supervisor read access is disabled for the first slave. + 0 + + + SSR_S1_1 + The secure supervisor read access is enabled for the first slave. + 0x1 + + + + + NUR_S1 + Non-secure user read access control for the first slave + 18 + 1 + read-write + + + NUR_S1_0 + The non-secure user read access is disabled for the first slave. + 0 + + + NUR_S1_1 + The non-secure user read access is enabled for the first slave. + 0x1 + + + + + NSR_S1 + Non-secure supervisor read access control for the first slave + 19 + 1 + read-write + + + NSR_S1_0 + The non-secure supervisor read access is disabled for the first slave. + 0 + + + NSR_S1_1 + The non-secure supervisor read access is enabled for the first slave. + 0x1 + + + + + SUW_S1 + Secure user write access control for the first slave + 20 + 1 + read-write + + + SUW_S1_0 + The secure user write access is disabled for the first slave. + 0 + + + SUW_S1_1 + The secure user write access is enabled for the first slave. + 0x1 + + + + + SSW_S1 + Secure supervisor write access control for the first slave + 21 + 1 + read-write + + + SSW_S1_0 + The secure supervisor write access is disabled for the first slave. + 0 + + + SSW_S1_1 + The secure supervisor write access is enabled for the first slave. + 0x1 + + + + + NUW_S1 + Non-secure user write access control for the first slave + 22 + 1 + read-write + + + NUW_S1_0 + The non-secure user write access is disabled for the first slave. + 0 + + + NUW_S1_1 + The non-secure user write access is enabled for the first slave. + 0x1 + + + + + NSW_S1 + Non-secure supervisor write access control for the first slave + 23 + 1 + read-write + + + NSW_S1_0 + The non-secure supervisor write access is disabled for the first slave. + 0 + + + NSW_S1_1 + The non-secure supervisor write access is enabled for the first slave + 0x1 + + + + + LOCK_S1 + The lock bit corresponding to the first slave. It is written by the secure software. + 24 + 1 + read-write + + + LOCK_S1_0 + Not locked. The bits 16-23 can be written by the software. + 0 + + + LOCK_S1_1 + The bits 16-23 are locked and can't be written by the software. + 0x1 + + + + + + + HP0 + HP0 register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + HP_DMA + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the eDMA + 2 + 1 + read-write + + + HP_DMA_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_DMA_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_DMA + Lock bit set by the TZ software for the eDMA + 3 + 1 + read-write + + + L_DMA_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DMA_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_LCDIF + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the LCDIF + 4 + 1 + read-write + + + HP_LCDIF_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_LCDIF_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_LCDIF + Lock bit set by the TZ software for the LCDIF + 5 + 1 + read-write + + + L_LCDIF_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_LCDIF_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_CSI + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the CSI + 6 + 1 + read-write + + + HP_CSI_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_CSI_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_CSI + Lock bit set by the TZ software for the CSI + 7 + 1 + read-write + + + L_CSI_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_CSI_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_PXP + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the PXP + 8 + 1 + read-write + + + HP_PXP_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_PXP_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_PXP + Lock bit set by the TZ software for the PXP + 9 + 1 + read-write + + + L_PXP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_PXP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_DCP + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the DCP + 10 + 1 + read-write + + + HP_DCP_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_DCP_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_DCP + Lock bit set by the TZ software for the DCP + 11 + 1 + read-write + + + L_DCP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DCP_1 + Lock-the adjacent (next lower) bit cannot be written by the software. + 0x1 + + + + + HP_ENET + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the ENET + 14 + 1 + read-write + + + HP_ENET_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_ENET_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_ENET + Lock bit set by the TZ software for the ENET + 15 + 1 + read-write + + + L_ENET_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_ENET_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_USDHC1 + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USDHC1 + 16 + 1 + read-write + + + HP_USDHC1_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_USDHC1_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_USDHC1 + Lock bit set by the TZ software for the USDHC1 + 17 + 1 + read-write + + + L_USDHC1_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC1_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_USDHC2 + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USDHC2 + 18 + 1 + read-write + + + HP_USDHC2_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_USDHC2_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_USDHC2 + Lock bit set by the TZ software for the USDHC2 + 19 + 1 + read-write + + + L_USDHC2_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC2_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_TPSMP + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the TPSMP + 20 + 1 + read-write + + + HP_TPSMP_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_TPSMP_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_TPSMP + Lock bit set by the TZ software for the TPSMP + 21 + 1 + read-write + + + L_TPSMP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_TPSMP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HP_USB + Determines whether the register value of the corresponding HP field is passed as the hprot[1] of the USB + 22 + 1 + read-write + + + HP_USB_0 + The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master. + 0 + + + HP_USB_1 + The HP register bit is routed to the csu_hprot1 output for the corresponding master. + 0x1 + + + + + L_USB + Lock bit set by the TZ software for the USB + 23 + 1 + read-write + + + L_USB_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USB_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + + + SA + Secure access register + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + NSA_DMA + Non-secure access policy indicator bit + 2 + 1 + read-write + + + NSA_DMA_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_DMA_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_DMA + Lock bit set by the TZ software for the eDMA + 3 + 1 + read-write + + + L_DMA_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DMA_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_LCDIF + Non-secure access policy indicator bit + 4 + 1 + read-write + + + NSA_LCDIF_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_LCDIF_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_LCDIF + Lock bit set by the TZ software for the LCDIF + 5 + 1 + read-write + + + L_LCDIF_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_LCDIF_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_CSI + Non-secure access policy indicator bit + 6 + 1 + read-write + + + NSA_CSI_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_CSI_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_CSI + Lock bit set by the TZ software for the CSI + 7 + 1 + read-write + + + L_CSI_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_CSI_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_PXP + Non-Secure Access Policy indicator bit + 8 + 1 + read-write + + + NSA_PXP_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_PXP_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_PXP + Lock bit set by the TZ software for the PXP + 9 + 1 + read-write + + + L_PXP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_PXP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_DCP + Non-secure access policy indicator bit + 10 + 1 + read-write + + + NSA_DCP_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_DCP_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_DCP + Lock bit set by the TZ software for the DCP + 11 + 1 + read-write + + + L_DCP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DCP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_ENET + Non-secure access policy indicator bit + 14 + 1 + read-write + + + NSA_ENET_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_ENET_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_ENET + Lock bit set by the TZ software for the ENET1 and ENET2 + 15 + 1 + read-write + + + L_ENET_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_ENET_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_USDHC1 + Non-secure access policy indicator bit + 16 + 1 + read-write + + + NSA_USDHC1_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_USDHC1_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_USDHC1 + Lock bit set by the TZ software for the USDHC1 + 17 + 1 + read-write + + + L_USDHC1_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC1_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_USDHC2 + Non-secure access policy indicator bit + 18 + 1 + read-write + + + NSA_USDHC2_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_USDHC2_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_USDHC2 + Lock bit set by the TZ software for the USDHC2 + 19 + 1 + read-write + + + L_USDHC2_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC2_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_TPSMP + Non-secure access policy indicator bit + 20 + 1 + read-write + + + NSA_TPSMP_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_TPSMP_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_TPSMP + Lock bit set by the TZ software for the TPSMP + 21 + 1 + read-write + + + L_TPSMP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_TPSMP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + NSA_USB + Non-secure access policy indicator bit + 22 + 1 + read-write + + + NSA_USB_0 + Secure access for the corresponding type-1 master + 0 + + + NSA_USB_1 + Non-secure access for the corresponding type-1 master + 0x1 + + + + + L_USB + Lock bit set by the TZ software for the USB + 23 + 1 + read-write + + + L_USB_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USB_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + + + HPCONTROL0 + HPCONTROL0 register + 0x358 + 32 + read-write + 0 + 0xFFFFFFFF + + + HPC_DMA + Indicates the privilege/user mode for the eDMA + 2 + 1 + read-write + + + HPC_DMA_0 + User mode for the corresponding master + 0 + + + HPC_DMA_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_DMA + Lock bit set by the TZ software for the eDMA + 3 + 1 + read-write + + + L_DMA_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DMA_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_LCDIF + Indicates the privilege/user mode for the LCDIF + 4 + 1 + read-write + + + HPC_LCDIF_0 + User mode for the corresponding master + 0 + + + HPC_LCDIF_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_LCDIF + Lock bit set by the TZ software for the LCDIF + 5 + 1 + read-write + + + L_LCDIF_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_LCDIF_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_CSI + Indicates the privilege/user mode for the CSI + 6 + 1 + read-write + + + HPC_CSI_0 + User mode for the corresponding master + 0 + + + HPC_CSI_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_CSI + Lock bit set by the TZ software for the CSI + 7 + 1 + read-write + + + L_CSI_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_CSI_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_PXP + Indicates the privilege/user mode for the PXP + 8 + 1 + read-write + + + HPC_PXP_0 + User mode for the corresponding master + 0 + + + HPC_PXP_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_PXP + Lock bit set by the TZ software for the PXP + 9 + 1 + read-write + + + L_PXP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_PXP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_DCP + Indicates the privilege/user mode for the DCP + 10 + 1 + read-write + + + HPC_DCP_0 + User mode for the corresponding master + 0 + + + HPC_DCP_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_DCP + Lock bit set by the TZ software for the DCP + 11 + 1 + read-write + + + L_DCP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_DCP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_ENET + Indicates the privilege/user mode for the ENET + 14 + 1 + read-write + + + HPC_ENET_0 + User mode for the corresponding master + 0 + + + HPC_ENET_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_ENET + Lock bit set by the TZ software for the ENET + 15 + 1 + read-write + + + L_ENET_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_ENET_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_USDHC1 + Indicates the privilege/user mode for the USDHC1 + 16 + 1 + read-write + + + HPC_USDHC1_0 + User mode for the corresponding master + 0 + + + HPC_USDHC1_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_USDHC1 + Lock bit set by the TZ software for the USDHC1 + 17 + 1 + read-write + + + L_USDHC1_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC1_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_USDHC2 + Indicates the privilege/user mode for the USDHC2 + 18 + 1 + read-write + + + HPC_USDHC2_0 + User mode for the corresponding master + 0 + + + HPC_USDHC2_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_USDHC2 + Lock bit set by the TZ software for the USDHC2. + 19 + 1 + read-write + + + L_USDHC2_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USDHC2_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_TPSMP + Indicates the privilege/user mode for the TPSMP + 20 + 1 + read-write + + + HPC_TPSMP_0 + User mode for the corresponding master + 0 + + + HPC_TPSMP_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_TPSMP + Lock bit set by the TZ software for the TPSMP. + 21 + 1 + read-write + + + L_TPSMP_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_TPSMP_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + HPC_USB + Indicates the privilege/user mode for the USB + 22 + 1 + read-write + + + HPC_USB_0 + User mode for the corresponding master + 0 + + + HPC_USB_1 + Supervisor mode for the corresponding master + 0x1 + + + + + L_USB + Lock bit set by the TZ software for the USB. + 23 + 1 + read-write + + + L_USB_0 + No lock-the adjacent (next lower) bit can be written by the software. + 0 + + + L_USB_1 + Lock-the adjacent (next lower) bit can't be written by the software. + 0x1 + + + + + + + + + TSC + Touch Screen Controller + TSC + TSC_ + 0x400E0000 + + 0 + 0x84 + registers + + + TSC_DIG + 40 + + + + BASIC_SETTING + no description available + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + AUTO_MEASURE + Auto Measure + 0 + 1 + read-write + + + AUTO_MEASURE_0 + Disable Auto Measure + 0 + + + AUTO_MEASURE_1 + Auto Measure + 0x1 + + + + + _4_5_WIRE + 4/5 Wire detection + 4 + 1 + read-write + + + 4_5_WIRE_0 + 4-Wire Detection Mode + 0 + + + 4_5_WIRE_1 + 5-Wire Detection Mode + 0x1 + + + + + MEASURE_DELAY_TIME + Measure Delay Time + 8 + 24 + read-write + + + + + PRE_CHARGE_TIME + no description available + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRE_CHARGE_TIME + Before detection, the top screen needs some time before being pulled up to a high voltage. + 0 + 32 + read-write + + + + + FLOW_CONTROL + Flow Control + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_RST + Soft Reset + 0 + 1 + read-write + + + START_MEASURE + Start Measure + 4 + 1 + read-write + + + START_MEASURE_0 + Do not start measure for now + 0 + + + START_MEASURE_1 + Start measure the X/Y coordinate value + 0x1 + + + + + DROP_MEASURE + Drop Measure + 8 + 1 + read-write + + + DROP_MEASURE_0 + Do not drop measure for now + 0 + + + DROP_MEASURE_1 + Drop the measure and controller return to idle status + 0x1 + + + + + START_SENSE + Start Sense + 12 + 1 + read-write + + + START_SENSE_0 + Stay at idle status + 0 + + + START_SENSE_1 + Start sense detection and (if auto_measure set to 1) measure after detect a touch + 0x1 + + + + + DISABLE + This bit is for SW disable registers + 16 + 1 + read-write + + + DISABLE_0 + Leave HW state machine control + 0 + + + DISABLE_1 + SW set to idle status + 0x1 + + + + + + + MEASEURE_VALUE + Measure Value + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + Y_VALUE + Y Value + 0 + 12 + read-only + + + X_VALUE + X Value + 16 + 12 + read-only + + + + + INT_EN + Interrupt Enable + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEASURE_INT_EN + Measure Interrupt Enable + 0 + 1 + read-write + + + MEASURE_INT_EN_0 + Disable measure interrupt + 0 + + + MEASURE_INT_EN_1 + Enable measure interrupt + 0x1 + + + + + DETECT_INT_EN + Detect Interrupt Enable + 4 + 1 + read-write + + + DETECT_INT_EN_0 + Disable detect interrupt + 0 + + + DETECT_INT_EN_1 + Enable detect interrupt + 0x1 + + + + + IDLE_SW_INT_EN + Idle Software Interrupt Enable + 12 + 1 + read-write + + + IDLE_SW_INT_EN_0 + Disable idle software interrupt + 0 + + + IDLE_SW_INT_EN_1 + Enable idle software interrupt + 0x1 + + + + + + + INT_SIG_EN + Interrupt Signal Enable + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEASURE_SIG_EN + Measure Signal Enable + 0 + 1 + read-write + + + DETECT_SIG_EN + Detect Signal Enable + 4 + 1 + read-write + + + DETECT_SIG_EN_0 + Disable detect signal + 0 + + + DETECT_SIG_EN_1 + Enable detect signal + 0x1 + + + + + VALID_SIG_EN + Valid Signal Enable + 8 + 1 + read-write + + + VALID_SIG_EN_0 + Disable valid signal + 0 + + + VALID_SIG_EN_1 + Enable valid signal + 0x1 + + + + + IDLE_SW_SIG_EN + Idle Software Signal Enable + 12 + 1 + read-write + + + IDLE_SW_SIG_EN_0 + Disable idle software signal + 0 + + + IDLE_SW_SIG_EN_1 + Enable idle software signal + 0x1 + + + + + + + INT_STATUS + Intterrupt Status + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEASURE + Measure Signal + 0 + 1 + read-write + + + MEASURE_0 + Does not exist a measure signal + 0 + + + MEASURE_1 + Exist a measure signal + 0x1 + + + + + DETECT + Detect Signal + 4 + 1 + read-write + + + DETECT_0 + Does not exist a detect signal + 0 + + + DETECT_1 + Exist detect signal + 0x1 + + + + + VALID + Valid Signal + 8 + 1 + read-write + + + VALID_0 + There is no touch detected after measurement, indicates that the measured value is not valid + 0 + + + VALID_1 + There is touch detection after measurement, indicates that the measure is valid + 0x1 + + + + + IDLE_SW + Idle Software + 12 + 1 + read-write + + + IDLE_SW_0 + Haven't return to idle status + 0 + + + IDLE_SW_1 + Already return to idle status + 0x1 + + + + + + + DEBUG_MODE + no description available + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADC_CONV_VALUE + ADC Conversion Value + 0 + 12 + read-only + + + ADC_COCO + ADC COCO Signal + 12 + 1 + read-only + + + EXT_HWTS + Hardware Trigger Select Signal + 16 + 5 + read-write + + + TRIGGER + Trigger + 24 + 1 + read-write + + + TRIGGER_0 + No hardware trigger signal + 0 + + + TRIGGER_1 + Hardware trigger signal, the signal must last at least 1 ips clock period + 0x1 + + + + + ADC_COCO_CLEAR + ADC Coco Clear + 25 + 1 + read-write + + + ADC_COCO_CLEAR_0 + No ADC COCO clear + 0 + + + ADC_COCO_CLEAR_1 + Set ADC COCO clear + 0x1 + + + + + ADC_COCO_CLEAR_DISABLE + ADC COCO Clear Disable + 26 + 1 + read-write + + + ADC_COCO_CLEAR_DISABLE_0 + Allow TSC hardware generates ADC COCO clear + 0 + + + ADC_COCO_CLEAR_DISABLE_1 + Prevent TSC from generate ADC COCO clear signal + 0x1 + + + + + DEBUG_EN + Debug Enable + 28 + 1 + read-write + + + DEBUG_EN_0 + Enable debug mode + 0 + + + DEBUG_EN_1 + Disable debug mode + 0x1 + + + + + + + DEBUG_MODE2 + no description available + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + XPUL_PULL_DOWN + XPUL Wire Pull Down Switch + 0 + 1 + read-write + + + XPUL_PULL_DOWN_0 + Close the switch + 0 + + + XPUL_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + XPUL_PULL_UP + XPUL Wire Pull Up Switch + 1 + 1 + read-write + + + XPUL_PULL_UP_0 + Close the switch + 0 + + + XPUL_PULL_UP_1 + Open up the switch + 0x1 + + + + + XPUL_200K_PULL_UP + XPUL Wire 200K Pull Up Switch + 2 + 1 + read-write + + + XPUL_200K_PULL_UP_0 + Close the switch + 0 + + + XPUL_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + XNUR_PULL_DOWN + XNUR Wire Pull Down Switch + 3 + 1 + read-write + + + XNUR_PULL_DOWN_0 + Close the switch + 0 + + + XNUR_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + XNUR_PULL_UP + XNUR Wire Pull Up Switch + 4 + 1 + read-write + + + XNUR_PULL_UP_0 + Close the switch + 0 + + + XNUR_PULL_UP_1 + Open up the switch + 0x1 + + + + + XNUR_200K_PULL_UP + XNUR Wire 200K Pull Up Switch + 5 + 1 + read-write + + + XNUR_200K_PULL_UP_0 + Close the switch + 0 + + + XNUR_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + YPLL_PULL_DOWN + YPLL Wire Pull Down Switch + 6 + 1 + read-write + + + YPLL_PULL_DOWN_0 + Close the switch + 0 + + + YPLL_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + YPLL_PULL_UP + YPLL Wire Pull Up Switch + 7 + 1 + read-write + + + YPLL_PULL_UP_0 + Close the switch + 0 + + + YPLL_PULL_UP_1 + Open the switch + 0x1 + + + + + YPLL_200K_PULL_UP + YPLL Wire 200K Pull Up Switch + 8 + 1 + read-write + + + YPLL_200K_PULL_UP_0 + Close the switch + 0 + + + YPLL_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + YNLR_PULL_DOWN + YNLR Wire Pull Down Switch + 9 + 1 + read-write + + + YNLR_PULL_DOWN_0 + Close the switch + 0 + + + YNLR_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + YNLR_PULL_UP + YNLR Wire Pull Up Switch + 10 + 1 + read-write + + + YNLR_PULL_UP_0 + Close the switch + 0 + + + YNLR_PULL_UP_1 + Open up the switch + 0x1 + + + + + YNLR_200K_PULL_UP + YNLR Wire 200K Pull Up Switch + 11 + 1 + read-write + + + YNLR_200K_PULL_UP_0 + Close the switch + 0 + + + YNLR_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + WIPER_PULL_DOWN + Wiper Wire Pull Down Switch + 12 + 1 + read-write + + + WIPER_PULL_DOWN_0 + Close the switch + 0 + + + WIPER_PULL_DOWN_1 + Open up the switch + 0x1 + + + + + WIPER_PULL_UP + Wiper Wire Pull Up Switch + 13 + 1 + read-write + + + WIPER_PULL_UP_0 + Close the switch + 0 + + + WIPER_PULL_UP_1 + Open up the switch + 0x1 + + + + + WIPER_200K_PULL_UP + Wiper Wire 200K Pull Up Switch + 14 + 1 + read-write + + + WIPER_200K_PULL_UP_0 + Close the switch + 0 + + + WIPER_200K_PULL_UP_1 + Open up the switch + 0x1 + + + + + DETECT_FOUR_WIRE + Detect Four Wire + 16 + 1 + read-only + + + DETECT_FOUR_WIRE_0 + No detect signal + 0 + + + DETECT_FOUR_WIRE_1 + Yes, there is a detect on the touch screen. + 0x1 + + + + + DETECT_FIVE_WIRE + Detect Five Wire + 17 + 1 + read-only + + + DETECT_FIVE_WIRE_0 + No detect signal + 0 + + + DETECT_FIVE_WIRE_1 + Yes, there is a detect on the touch screen. + 0x1 + + + + + STATE_MACHINE + State Machine + 20 + 3 + read-only + + + STATE_MACHINE_0 + Idle + 0 + + + STATE_MACHINE_1 + Pre-charge + 0x1 + + + STATE_MACHINE_2 + Detect + 0x2 + + + STATE_MACHINE_3 + X-measure + 0x3 + + + STATE_MACHINE_4 + Y-measure + 0x4 + + + STATE_MACHINE_5 + Pre-charge + 0x5 + + + STATE_MACHINE_6 + Detect + 0x6 + + + + + INTERMEDIATE + Intermediate State + 23 + 1 + read-only + + + INTERMEDIATE_0 + Not in intermedia + 0 + + + INTERMEDIATE_1 + Intermedia + 0x1 + + + + + DETECT_ENABLE_FOUR_WIRE + Detect Enable Four Wire + 24 + 1 + read-write + + + DETECT_ENABLE_FOUR_WIRE_0 + Do not read four wire detect value, read default value from analogue + 0 + + + DETECT_ENABLE_FOUR_WIRE_1 + Read four wire detect status from analogue + 0x1 + + + + + DETECT_ENABLE_FIVE_WIRE + Detect Enable Five Wire + 28 + 1 + read-write + + + DETECT_ENABLE_FIVE_WIRE_0 + Do not read five wire detect value, read default value from analogue + 0 + + + DETECT_ENABLE_FIVE_WIRE_1 + Read five wire detect status from analogue + 0x1 + + + + + DE_GLITCH + This field indicates glitch threshold + 29 + 2 + read-only + + + DE_GLITCH_0 + Normal function: 0x1fff ipg clock cycles; Low power mode: 0x9 low power clock cycles + 0 + + + DE_GLITCH_1 + Normal function: 0xfff ipg clock cycles; Low power mode: :0x7 low power clock cycles + 0x1 + + + DE_GLITCH_2 + Normal function: 0x7ff ipg clock cycles; Low power mode:0x5 low power clock cycles + 0x2 + + + DE_GLITCH_3 + Normal function: 0x3 ipg clock cycles; Low power mode:0x3 low power clock cycles + 0x3 + + + + + + + + + DMA0 + DMA + DMA + 0x400E8000 + + 0 + 0x1400 + registers + + + DMA0_DMA16 + 0 + + + DMA1_DMA17 + 1 + + + DMA2_DMA18 + 2 + + + DMA3_DMA19 + 3 + + + DMA4_DMA20 + 4 + + + DMA5_DMA21 + 5 + + + DMA6_DMA22 + 6 + + + DMA7_DMA23 + 7 + + + DMA8_DMA24 + 8 + + + DMA9_DMA25 + 9 + + + DMA10_DMA26 + 10 + + + DMA11_DMA27 + 11 + + + DMA12_DMA28 + 12 + + + DMA13_DMA29 + 13 + + + DMA14_DMA30 + 14 + + + DMA15_DMA31 + 15 + + + DMA_ERROR + 16 + + + + CR + Control Register + 0 + 32 + read-write + 0x400 + 0x80FFFFFF + + + EDBG + Enable Debug + 1 + 1 + read-write + + + EDBG_0 + When in debug mode, the DMA continues to operate. + 0 + + + EDBG_1 + When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. + 0x1 + + + + + ERCA + Enable Round Robin Channel Arbitration + 2 + 1 + read-write + + + ERCA_0 + Fixed priority arbitration is used for channel selection within each group. + 0 + + + ERCA_1 + Round robin arbitration is used for channel selection within each group. + 0x1 + + + + + ERGA + Enable Round Robin Group Arbitration + 3 + 1 + read-write + + + ERGA_0 + Fixed priority arbitration is used for selection among the groups. + 0 + + + ERGA_1 + Round robin arbitration is used for selection among the groups. + 0x1 + + + + + HOE + Halt On Error + 4 + 1 + read-write + + + HOE_0 + Normal operation + 0 + + + HOE_1 + Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. + 0x1 + + + + + HALT + Halt DMA Operations + 5 + 1 + read-write + + + HALT_0 + Normal operation + 0 + + + HALT_1 + Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. + 0x1 + + + + + CLM + Continuous Link Mode + 6 + 1 + read-write + + + CLM_0 + A minor loop channel link made to itself goes through channel arbitration before being activated again. + 0 + + + CLM_1 + A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. + 0x1 + + + + + EMLM + Enable Minor Loop Mapping + 7 + 1 + read-write + + + EMLM_0 + Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. + 0 + + + EMLM_1 + Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. + 0x1 + + + + + GRP0PRI + Channel Group 0 Priority + 8 + 1 + read-write + + + GRP1PRI + Channel Group 1 Priority + 10 + 1 + read-write + + + ECX + Error Cancel Transfer + 16 + 1 + read-write + + + ECX_0 + Normal operation + 0 + + + ECX_1 + Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. + 0x1 + + + + + CX + Cancel Transfer + 17 + 1 + read-write + + + CX_0 + Normal operation + 0 + + + CX_1 + Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. + 0x1 + + + + + ACTIVE + DMA Active Status + 31 + 1 + read-only + + + ACTIVE_0 + eDMA is idle. + 0 + + + ACTIVE_1 + eDMA is executing a channel. + 0x1 + + + + + + + ES + Error Status Register + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + DBE + Destination Bus Error + 0 + 1 + read-only + + + DBE_0 + No destination bus error + 0 + + + DBE_1 + The last recorded error was a bus error on a destination write + 0x1 + + + + + SBE + Source Bus Error + 1 + 1 + read-only + + + SBE_0 + No source bus error + 0 + + + SBE_1 + The last recorded error was a bus error on a source read + 0x1 + + + + + SGE + Scatter/Gather Configuration Error + 2 + 1 + read-only + + + SGE_0 + No scatter/gather configuration error + 0 + + + SGE_1 + The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. + 0x1 + + + + + NCE + NBYTES/CITER Configuration Error + 3 + 1 + read-only + + + NCE_0 + No NBYTES/CITER configuration error + 0 + + + NCE_1 + The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] + 0x1 + + + + + DOE + Destination Offset Error + 4 + 1 + read-only + + + DOE_0 + No destination offset configuration error + 0 + + + DOE_1 + The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. + 0x1 + + + + + DAE + Destination Address Error + 5 + 1 + read-only + + + DAE_0 + No destination address configuration error + 0 + + + DAE_1 + The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. + 0x1 + + + + + SOE + Source Offset Error + 6 + 1 + read-only + + + SOE_0 + No source offset configuration error + 0 + + + SOE_1 + The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. + 0x1 + + + + + SAE + Source Address Error + 7 + 1 + read-only + + + SAE_0 + No source address configuration error. + 0 + + + SAE_1 + The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. + 0x1 + + + + + ERRCHN + Error Channel Number or Canceled Channel Number + 8 + 5 + read-only + + + CPE + Channel Priority Error + 14 + 1 + read-only + + + CPE_0 + No channel priority error + 0 + + + CPE_1 + The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique. + 0x1 + + + + + GPE + Group Priority Error + 15 + 1 + read-only + + + GPE_0 + No group priority error + 0 + + + GPE_1 + The last recorded error was a configuration error among the group priorities. All group priorities are not unique. + 0x1 + + + + + ECX + Transfer Canceled + 16 + 1 + read-only + + + ECX_0 + No canceled transfers + 0 + + + ECX_1 + The last recorded entry was a canceled transfer by the error cancel transfer input + 0x1 + + + + + VLD + VLD + 31 + 1 + read-only + + + VLD_0 + No ERR bits are set. + 0 + + + VLD_1 + At least one ERR bit is set indicating a valid error exists that has not been cleared. + 0x1 + + + + + + + ERQ + Enable Request Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ERQ0 + Enable DMA Request 0 + 0 + 1 + read-write + + + ERQ0_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ0_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ1 + Enable DMA Request 1 + 1 + 1 + read-write + + + ERQ1_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ1_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ2 + Enable DMA Request 2 + 2 + 1 + read-write + + + ERQ2_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ2_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ3 + Enable DMA Request 3 + 3 + 1 + read-write + + + ERQ3_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ3_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ4 + Enable DMA Request 4 + 4 + 1 + read-write + + + ERQ4_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ4_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ5 + Enable DMA Request 5 + 5 + 1 + read-write + + + ERQ5_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ5_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ6 + Enable DMA Request 6 + 6 + 1 + read-write + + + ERQ6_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ6_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ7 + Enable DMA Request 7 + 7 + 1 + read-write + + + ERQ7_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ7_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ8 + Enable DMA Request 8 + 8 + 1 + read-write + + + ERQ8_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ8_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ9 + Enable DMA Request 9 + 9 + 1 + read-write + + + ERQ9_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ9_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ10 + Enable DMA Request 10 + 10 + 1 + read-write + + + ERQ10_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ10_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ11 + Enable DMA Request 11 + 11 + 1 + read-write + + + ERQ11_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ11_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ12 + Enable DMA Request 12 + 12 + 1 + read-write + + + ERQ12_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ12_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ13 + Enable DMA Request 13 + 13 + 1 + read-write + + + ERQ13_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ13_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ14 + Enable DMA Request 14 + 14 + 1 + read-write + + + ERQ14_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ14_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ15 + Enable DMA Request 15 + 15 + 1 + read-write + + + ERQ15_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ15_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ16 + Enable DMA Request 16 + 16 + 1 + read-write + + + ERQ16_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ16_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ17 + Enable DMA Request 17 + 17 + 1 + read-write + + + ERQ17_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ17_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ18 + Enable DMA Request 18 + 18 + 1 + read-write + + + ERQ18_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ18_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ19 + Enable DMA Request 19 + 19 + 1 + read-write + + + ERQ19_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ19_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ20 + Enable DMA Request 20 + 20 + 1 + read-write + + + ERQ20_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ20_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ21 + Enable DMA Request 21 + 21 + 1 + read-write + + + ERQ21_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ21_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ22 + Enable DMA Request 22 + 22 + 1 + read-write + + + ERQ22_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ22_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ23 + Enable DMA Request 23 + 23 + 1 + read-write + + + ERQ23_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ23_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ24 + Enable DMA Request 24 + 24 + 1 + read-write + + + ERQ24_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ24_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ25 + Enable DMA Request 25 + 25 + 1 + read-write + + + ERQ25_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ25_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ26 + Enable DMA Request 26 + 26 + 1 + read-write + + + ERQ26_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ26_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ27 + Enable DMA Request 27 + 27 + 1 + read-write + + + ERQ27_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ27_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ28 + Enable DMA Request 28 + 28 + 1 + read-write + + + ERQ28_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ28_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ29 + Enable DMA Request 29 + 29 + 1 + read-write + + + ERQ29_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ29_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ30 + Enable DMA Request 30 + 30 + 1 + read-write + + + ERQ30_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ30_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + ERQ31 + Enable DMA Request 31 + 31 + 1 + read-write + + + ERQ31_0 + The DMA request signal for the corresponding channel is disabled + 0 + + + ERQ31_1 + The DMA request signal for the corresponding channel is enabled + 0x1 + + + + + + + EEI + Enable Error Interrupt Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + EEI0 + Enable Error Interrupt 0 + 0 + 1 + read-write + + + EEI0_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI0_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI1 + Enable Error Interrupt 1 + 1 + 1 + read-write + + + EEI1_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI1_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI2 + Enable Error Interrupt 2 + 2 + 1 + read-write + + + EEI2_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI2_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI3 + Enable Error Interrupt 3 + 3 + 1 + read-write + + + EEI3_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI3_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI4 + Enable Error Interrupt 4 + 4 + 1 + read-write + + + EEI4_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI4_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI5 + Enable Error Interrupt 5 + 5 + 1 + read-write + + + EEI5_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI5_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI6 + Enable Error Interrupt 6 + 6 + 1 + read-write + + + EEI6_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI6_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI7 + Enable Error Interrupt 7 + 7 + 1 + read-write + + + EEI7_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI7_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI8 + Enable Error Interrupt 8 + 8 + 1 + read-write + + + EEI8_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI8_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI9 + Enable Error Interrupt 9 + 9 + 1 + read-write + + + EEI9_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI9_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI10 + Enable Error Interrupt 10 + 10 + 1 + read-write + + + EEI10_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI10_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI11 + Enable Error Interrupt 11 + 11 + 1 + read-write + + + EEI11_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI11_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI12 + Enable Error Interrupt 12 + 12 + 1 + read-write + + + EEI12_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI12_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI13 + Enable Error Interrupt 13 + 13 + 1 + read-write + + + EEI13_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI13_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI14 + Enable Error Interrupt 14 + 14 + 1 + read-write + + + EEI14_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI14_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI15 + Enable Error Interrupt 15 + 15 + 1 + read-write + + + EEI15_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI15_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI16 + Enable Error Interrupt 16 + 16 + 1 + read-write + + + EEI16_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI16_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI17 + Enable Error Interrupt 17 + 17 + 1 + read-write + + + EEI17_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI17_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI18 + Enable Error Interrupt 18 + 18 + 1 + read-write + + + EEI18_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI18_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI19 + Enable Error Interrupt 19 + 19 + 1 + read-write + + + EEI19_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI19_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI20 + Enable Error Interrupt 20 + 20 + 1 + read-write + + + EEI20_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI20_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI21 + Enable Error Interrupt 21 + 21 + 1 + read-write + + + EEI21_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI21_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI22 + Enable Error Interrupt 22 + 22 + 1 + read-write + + + EEI22_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI22_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI23 + Enable Error Interrupt 23 + 23 + 1 + read-write + + + EEI23_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI23_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI24 + Enable Error Interrupt 24 + 24 + 1 + read-write + + + EEI24_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI24_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI25 + Enable Error Interrupt 25 + 25 + 1 + read-write + + + EEI25_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI25_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI26 + Enable Error Interrupt 26 + 26 + 1 + read-write + + + EEI26_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI26_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI27 + Enable Error Interrupt 27 + 27 + 1 + read-write + + + EEI27_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI27_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI28 + Enable Error Interrupt 28 + 28 + 1 + read-write + + + EEI28_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI28_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI29 + Enable Error Interrupt 29 + 29 + 1 + read-write + + + EEI29_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI29_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI30 + Enable Error Interrupt 30 + 30 + 1 + read-write + + + EEI30_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI30_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + EEI31 + Enable Error Interrupt 31 + 31 + 1 + read-write + + + EEI31_0 + The error signal for corresponding channel does not generate an error interrupt + 0 + + + EEI31_1 + The assertion of the error signal for corresponding channel generates an error interrupt request + 0x1 + + + + + + + CEEI + Clear Enable Error Interrupt Register + 0x18 + 8 + read-write + 0 + 0xFF + + + CEEI + Clear Enable Error Interrupt + 0 + 5 + read-write + + + CAEE + Clear All Enable Error Interrupts + 6 + 1 + read-write + + + CAEE_0 + Clear only the EEI bit specified in the CEEI field + 0 + + + CAEE_1 + Clear all bits in EEI + 0x1 + + + + + NOP + No Op enable + 7 + 1 + read-write + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + SEEI + Set Enable Error Interrupt Register + 0x19 + 8 + read-write + 0 + 0xFF + + + SEEI + Set Enable Error Interrupt + 0 + 5 + read-write + + + SAEE + Sets All Enable Error Interrupts + 6 + 1 + read-write + + + SAEE_0 + Set only the EEI bit specified in the SEEI field. + 0 + + + SAEE_1 + Sets all bits in EEI + 0x1 + + + + + NOP + No Op enable + 7 + 1 + read-write + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + CERQ + Clear Enable Request Register + 0x1A + 8 + read-write + 0 + 0xFF + + + CERQ + Clear Enable Request + 0 + 5 + read-write + + + CAER + Clear All Enable Requests + 6 + 1 + read-write + + + CAER_0 + Clear only the ERQ bit specified in the CERQ field + 0 + + + CAER_1 + Clear all bits in ERQ + 0x1 + + + + + NOP + No Op enable + 7 + 1 + read-write + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + SERQ + Set Enable Request Register + 0x1B + 8 + read-write + 0 + 0xFF + + + SERQ + Set Enable Request + 0 + 5 + read-write + + + SAER + Set All Enable Requests + 6 + 1 + read-write + + + SAER_0 + Set only the ERQ bit specified in the SERQ field + 0 + + + SAER_1 + Set all bits in ERQ + 0x1 + + + + + NOP + No Op enable + 7 + 1 + read-write + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + CDNE + Clear DONE Status Bit Register + 0x1C + 8 + read-write + 0 + 0xFF + + + CDNE + Clear DONE Bit + 0 + 5 + read-write + + + CADN + Clears All DONE Bits + 6 + 1 + read-write + + + CADN_0 + Clears only the TCDn_CSR[DONE] bit specified in the CDNE field + 0 + + + CADN_1 + Clears all bits in TCDn_CSR[DONE] + 0x1 + + + + + NOP + No Op enable + 7 + 1 + read-write + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + SSRT + Set START Bit Register + 0x1D + 8 + read-write + 0 + 0xFF + + + SSRT + Set START Bit + 0 + 5 + read-write + + + SAST + Set All START Bits (activates all channels) + 6 + 1 + read-write + + + SAST_0 + Set only the TCDn_CSR[START] bit specified in the SSRT field + 0 + + + SAST_1 + Set all bits in TCDn_CSR[START] + 0x1 + + + + + NOP + No Op enable + 7 + 1 + read-write + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + CERR + Clear Error Register + 0x1E + 8 + read-write + 0 + 0xFF + + + CERR + Clear Error Indicator + 0 + 5 + read-write + + + CAEI + Clear All Error Indicators + 6 + 1 + read-write + + + CAEI_0 + Clear only the ERR bit specified in the CERR field + 0 + + + CAEI_1 + Clear all bits in ERR + 0x1 + + + + + NOP + No Op enable + 7 + 1 + read-write + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + CINT + Clear Interrupt Request Register + 0x1F + 8 + read-write + 0 + 0xFF + + + CINT + Clear Interrupt Request + 0 + 5 + read-write + + + CAIR + Clear All Interrupt Requests + 6 + 1 + read-write + + + CAIR_0 + Clear only the INT bit specified in the CINT field + 0 + + + CAIR_1 + Clear all bits in INT + 0x1 + + + + + NOP + No Op enable + 7 + 1 + read-write + + + NOP_0 + Normal operation + 0 + + + NOP_1 + No operation, ignore the other bits in this register + 0x1 + + + + + + + INT + Interrupt Request Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + INT0 + Interrupt Request 0 + 0 + 1 + read-write + oneToClear + + + INT0_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT0_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT1 + Interrupt Request 1 + 1 + 1 + read-write + oneToClear + + + INT1_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT1_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT2 + Interrupt Request 2 + 2 + 1 + read-write + oneToClear + + + INT2_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT2_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT3 + Interrupt Request 3 + 3 + 1 + read-write + oneToClear + + + INT3_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT3_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT4 + Interrupt Request 4 + 4 + 1 + read-write + oneToClear + + + INT4_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT4_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT5 + Interrupt Request 5 + 5 + 1 + read-write + oneToClear + + + INT5_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT5_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT6 + Interrupt Request 6 + 6 + 1 + read-write + oneToClear + + + INT6_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT6_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT7 + Interrupt Request 7 + 7 + 1 + read-write + oneToClear + + + INT7_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT7_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT8 + Interrupt Request 8 + 8 + 1 + read-write + oneToClear + + + INT8_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT8_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT9 + Interrupt Request 9 + 9 + 1 + read-write + oneToClear + + + INT9_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT9_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT10 + Interrupt Request 10 + 10 + 1 + read-write + oneToClear + + + INT10_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT10_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT11 + Interrupt Request 11 + 11 + 1 + read-write + oneToClear + + + INT11_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT11_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT12 + Interrupt Request 12 + 12 + 1 + read-write + oneToClear + + + INT12_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT12_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT13 + Interrupt Request 13 + 13 + 1 + read-write + oneToClear + + + INT13_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT13_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT14 + Interrupt Request 14 + 14 + 1 + read-write + oneToClear + + + INT14_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT14_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT15 + Interrupt Request 15 + 15 + 1 + read-write + oneToClear + + + INT15_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT15_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT16 + Interrupt Request 16 + 16 + 1 + read-write + oneToClear + + + INT16_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT16_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT17 + Interrupt Request 17 + 17 + 1 + read-write + oneToClear + + + INT17_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT17_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT18 + Interrupt Request 18 + 18 + 1 + read-write + oneToClear + + + INT18_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT18_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT19 + Interrupt Request 19 + 19 + 1 + read-write + oneToClear + + + INT19_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT19_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT20 + Interrupt Request 20 + 20 + 1 + read-write + oneToClear + + + INT20_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT20_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT21 + Interrupt Request 21 + 21 + 1 + read-write + oneToClear + + + INT21_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT21_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT22 + Interrupt Request 22 + 22 + 1 + read-write + oneToClear + + + INT22_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT22_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT23 + Interrupt Request 23 + 23 + 1 + read-write + oneToClear + + + INT23_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT23_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT24 + Interrupt Request 24 + 24 + 1 + read-write + oneToClear + + + INT24_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT24_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT25 + Interrupt Request 25 + 25 + 1 + read-write + oneToClear + + + INT25_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT25_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT26 + Interrupt Request 26 + 26 + 1 + read-write + oneToClear + + + INT26_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT26_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT27 + Interrupt Request 27 + 27 + 1 + read-write + oneToClear + + + INT27_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT27_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT28 + Interrupt Request 28 + 28 + 1 + read-write + oneToClear + + + INT28_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT28_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT29 + Interrupt Request 29 + 29 + 1 + read-write + oneToClear + + + INT29_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT29_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT30 + Interrupt Request 30 + 30 + 1 + read-write + oneToClear + + + INT30_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT30_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + INT31 + Interrupt Request 31 + 31 + 1 + read-write + oneToClear + + + INT31_0 + The interrupt request for corresponding channel is cleared + 0 + + + INT31_1 + The interrupt request for corresponding channel is active + 0x1 + + + + + + + ERR + Error Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ERR0 + Error In Channel 0 + 0 + 1 + read-write + oneToClear + + + ERR0_0 + An error in this channel has not occurred + 0 + + + ERR0_1 + An error in this channel has occurred + 0x1 + + + + + ERR1 + Error In Channel 1 + 1 + 1 + read-write + oneToClear + + + ERR1_0 + An error in this channel has not occurred + 0 + + + ERR1_1 + An error in this channel has occurred + 0x1 + + + + + ERR2 + Error In Channel 2 + 2 + 1 + read-write + oneToClear + + + ERR2_0 + An error in this channel has not occurred + 0 + + + ERR2_1 + An error in this channel has occurred + 0x1 + + + + + ERR3 + Error In Channel 3 + 3 + 1 + read-write + oneToClear + + + ERR3_0 + An error in this channel has not occurred + 0 + + + ERR3_1 + An error in this channel has occurred + 0x1 + + + + + ERR4 + Error In Channel 4 + 4 + 1 + read-write + oneToClear + + + ERR4_0 + An error in this channel has not occurred + 0 + + + ERR4_1 + An error in this channel has occurred + 0x1 + + + + + ERR5 + Error In Channel 5 + 5 + 1 + read-write + oneToClear + + + ERR5_0 + An error in this channel has not occurred + 0 + + + ERR5_1 + An error in this channel has occurred + 0x1 + + + + + ERR6 + Error In Channel 6 + 6 + 1 + read-write + oneToClear + + + ERR6_0 + An error in this channel has not occurred + 0 + + + ERR6_1 + An error in this channel has occurred + 0x1 + + + + + ERR7 + Error In Channel 7 + 7 + 1 + read-write + oneToClear + + + ERR7_0 + An error in this channel has not occurred + 0 + + + ERR7_1 + An error in this channel has occurred + 0x1 + + + + + ERR8 + Error In Channel 8 + 8 + 1 + read-write + oneToClear + + + ERR8_0 + An error in this channel has not occurred + 0 + + + ERR8_1 + An error in this channel has occurred + 0x1 + + + + + ERR9 + Error In Channel 9 + 9 + 1 + read-write + oneToClear + + + ERR9_0 + An error in this channel has not occurred + 0 + + + ERR9_1 + An error in this channel has occurred + 0x1 + + + + + ERR10 + Error In Channel 10 + 10 + 1 + read-write + oneToClear + + + ERR10_0 + An error in this channel has not occurred + 0 + + + ERR10_1 + An error in this channel has occurred + 0x1 + + + + + ERR11 + Error In Channel 11 + 11 + 1 + read-write + oneToClear + + + ERR11_0 + An error in this channel has not occurred + 0 + + + ERR11_1 + An error in this channel has occurred + 0x1 + + + + + ERR12 + Error In Channel 12 + 12 + 1 + read-write + oneToClear + + + ERR12_0 + An error in this channel has not occurred + 0 + + + ERR12_1 + An error in this channel has occurred + 0x1 + + + + + ERR13 + Error In Channel 13 + 13 + 1 + read-write + oneToClear + + + ERR13_0 + An error in this channel has not occurred + 0 + + + ERR13_1 + An error in this channel has occurred + 0x1 + + + + + ERR14 + Error In Channel 14 + 14 + 1 + read-write + oneToClear + + + ERR14_0 + An error in this channel has not occurred + 0 + + + ERR14_1 + An error in this channel has occurred + 0x1 + + + + + ERR15 + Error In Channel 15 + 15 + 1 + read-write + oneToClear + + + ERR15_0 + An error in this channel has not occurred + 0 + + + ERR15_1 + An error in this channel has occurred + 0x1 + + + + + ERR16 + Error In Channel 16 + 16 + 1 + read-write + oneToClear + + + ERR16_0 + An error in this channel has not occurred + 0 + + + ERR16_1 + An error in this channel has occurred + 0x1 + + + + + ERR17 + Error In Channel 17 + 17 + 1 + read-write + oneToClear + + + ERR17_0 + An error in this channel has not occurred + 0 + + + ERR17_1 + An error in this channel has occurred + 0x1 + + + + + ERR18 + Error In Channel 18 + 18 + 1 + read-write + oneToClear + + + ERR18_0 + An error in this channel has not occurred + 0 + + + ERR18_1 + An error in this channel has occurred + 0x1 + + + + + ERR19 + Error In Channel 19 + 19 + 1 + read-write + oneToClear + + + ERR19_0 + An error in this channel has not occurred + 0 + + + ERR19_1 + An error in this channel has occurred + 0x1 + + + + + ERR20 + Error In Channel 20 + 20 + 1 + read-write + oneToClear + + + ERR20_0 + An error in this channel has not occurred + 0 + + + ERR20_1 + An error in this channel has occurred + 0x1 + + + + + ERR21 + Error In Channel 21 + 21 + 1 + read-write + oneToClear + + + ERR21_0 + An error in this channel has not occurred + 0 + + + ERR21_1 + An error in this channel has occurred + 0x1 + + + + + ERR22 + Error In Channel 22 + 22 + 1 + read-write + oneToClear + + + ERR22_0 + An error in this channel has not occurred + 0 + + + ERR22_1 + An error in this channel has occurred + 0x1 + + + + + ERR23 + Error In Channel 23 + 23 + 1 + read-write + oneToClear + + + ERR23_0 + An error in this channel has not occurred + 0 + + + ERR23_1 + An error in this channel has occurred + 0x1 + + + + + ERR24 + Error In Channel 24 + 24 + 1 + read-write + oneToClear + + + ERR24_0 + An error in this channel has not occurred + 0 + + + ERR24_1 + An error in this channel has occurred + 0x1 + + + + + ERR25 + Error In Channel 25 + 25 + 1 + read-write + oneToClear + + + ERR25_0 + An error in this channel has not occurred + 0 + + + ERR25_1 + An error in this channel has occurred + 0x1 + + + + + ERR26 + Error In Channel 26 + 26 + 1 + read-write + oneToClear + + + ERR26_0 + An error in this channel has not occurred + 0 + + + ERR26_1 + An error in this channel has occurred + 0x1 + + + + + ERR27 + Error In Channel 27 + 27 + 1 + read-write + oneToClear + + + ERR27_0 + An error in this channel has not occurred + 0 + + + ERR27_1 + An error in this channel has occurred + 0x1 + + + + + ERR28 + Error In Channel 28 + 28 + 1 + read-write + oneToClear + + + ERR28_0 + An error in this channel has not occurred + 0 + + + ERR28_1 + An error in this channel has occurred + 0x1 + + + + + ERR29 + Error In Channel 29 + 29 + 1 + read-write + oneToClear + + + ERR29_0 + An error in this channel has not occurred + 0 + + + ERR29_1 + An error in this channel has occurred + 0x1 + + + + + ERR30 + Error In Channel 30 + 30 + 1 + read-write + oneToClear + + + ERR30_0 + An error in this channel has not occurred + 0 + + + ERR30_1 + An error in this channel has occurred + 0x1 + + + + + ERR31 + Error In Channel 31 + 31 + 1 + read-write + oneToClear + + + ERR31_0 + An error in this channel has not occurred + 0 + + + ERR31_1 + An error in this channel has occurred + 0x1 + + + + + + + HRS + Hardware Request Status Register + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + HRS0 + Hardware Request Status Channel 0 + 0 + 1 + read-only + + + HRS0_0 + A hardware service request for channel 0 is not present + 0 + + + HRS0_1 + A hardware service request for channel 0 is present + 0x1 + + + + + HRS1 + Hardware Request Status Channel 1 + 1 + 1 + read-only + + + HRS1_0 + A hardware service request for channel 1 is not present + 0 + + + HRS1_1 + A hardware service request for channel 1 is present + 0x1 + + + + + HRS2 + Hardware Request Status Channel 2 + 2 + 1 + read-only + + + HRS2_0 + A hardware service request for channel 2 is not present + 0 + + + HRS2_1 + A hardware service request for channel 2 is present + 0x1 + + + + + HRS3 + Hardware Request Status Channel 3 + 3 + 1 + read-only + + + HRS3_0 + A hardware service request for channel 3 is not present + 0 + + + HRS3_1 + A hardware service request for channel 3 is present + 0x1 + + + + + HRS4 + Hardware Request Status Channel 4 + 4 + 1 + read-only + + + HRS4_0 + A hardware service request for channel 4 is not present + 0 + + + HRS4_1 + A hardware service request for channel 4 is present + 0x1 + + + + + HRS5 + Hardware Request Status Channel 5 + 5 + 1 + read-only + + + HRS5_0 + A hardware service request for channel 5 is not present + 0 + + + HRS5_1 + A hardware service request for channel 5 is present + 0x1 + + + + + HRS6 + Hardware Request Status Channel 6 + 6 + 1 + read-only + + + HRS6_0 + A hardware service request for channel 6 is not present + 0 + + + HRS6_1 + A hardware service request for channel 6 is present + 0x1 + + + + + HRS7 + Hardware Request Status Channel 7 + 7 + 1 + read-only + + + HRS7_0 + A hardware service request for channel 7 is not present + 0 + + + HRS7_1 + A hardware service request for channel 7 is present + 0x1 + + + + + HRS8 + Hardware Request Status Channel 8 + 8 + 1 + read-only + + + HRS8_0 + A hardware service request for channel 8 is not present + 0 + + + HRS8_1 + A hardware service request for channel 8 is present + 0x1 + + + + + HRS9 + Hardware Request Status Channel 9 + 9 + 1 + read-only + + + HRS9_0 + A hardware service request for channel 9 is not present + 0 + + + HRS9_1 + A hardware service request for channel 9 is present + 0x1 + + + + + HRS10 + Hardware Request Status Channel 10 + 10 + 1 + read-only + + + HRS10_0 + A hardware service request for channel 10 is not present + 0 + + + HRS10_1 + A hardware service request for channel 10 is present + 0x1 + + + + + HRS11 + Hardware Request Status Channel 11 + 11 + 1 + read-only + + + HRS11_0 + A hardware service request for channel 11 is not present + 0 + + + HRS11_1 + A hardware service request for channel 11 is present + 0x1 + + + + + HRS12 + Hardware Request Status Channel 12 + 12 + 1 + read-only + + + HRS12_0 + A hardware service request for channel 12 is not present + 0 + + + HRS12_1 + A hardware service request for channel 12 is present + 0x1 + + + + + HRS13 + Hardware Request Status Channel 13 + 13 + 1 + read-only + + + HRS13_0 + A hardware service request for channel 13 is not present + 0 + + + HRS13_1 + A hardware service request for channel 13 is present + 0x1 + + + + + HRS14 + Hardware Request Status Channel 14 + 14 + 1 + read-only + + + HRS14_0 + A hardware service request for channel 14 is not present + 0 + + + HRS14_1 + A hardware service request for channel 14 is present + 0x1 + + + + + HRS15 + Hardware Request Status Channel 15 + 15 + 1 + read-only + + + HRS15_0 + A hardware service request for channel 15 is not present + 0 + + + HRS15_1 + A hardware service request for channel 15 is present + 0x1 + + + + + HRS16 + Hardware Request Status Channel 16 + 16 + 1 + read-only + + + HRS16_0 + A hardware service request for channel 16 is not present + 0 + + + HRS16_1 + A hardware service request for channel 16 is present + 0x1 + + + + + HRS17 + Hardware Request Status Channel 17 + 17 + 1 + read-only + + + HRS17_0 + A hardware service request for channel 17 is not present + 0 + + + HRS17_1 + A hardware service request for channel 17 is present + 0x1 + + + + + HRS18 + Hardware Request Status Channel 18 + 18 + 1 + read-only + + + HRS18_0 + A hardware service request for channel 18 is not present + 0 + + + HRS18_1 + A hardware service request for channel 18 is present + 0x1 + + + + + HRS19 + Hardware Request Status Channel 19 + 19 + 1 + read-only + + + HRS19_0 + A hardware service request for channel 19 is not present + 0 + + + HRS19_1 + A hardware service request for channel 19 is present + 0x1 + + + + + HRS20 + Hardware Request Status Channel 20 + 20 + 1 + read-only + + + HRS20_0 + A hardware service request for channel 20 is not present + 0 + + + HRS20_1 + A hardware service request for channel 20 is present + 0x1 + + + + + HRS21 + Hardware Request Status Channel 21 + 21 + 1 + read-only + + + HRS21_0 + A hardware service request for channel 21 is not present + 0 + + + HRS21_1 + A hardware service request for channel 21 is present + 0x1 + + + + + HRS22 + Hardware Request Status Channel 22 + 22 + 1 + read-only + + + HRS22_0 + A hardware service request for channel 22 is not present + 0 + + + HRS22_1 + A hardware service request for channel 22 is present + 0x1 + + + + + HRS23 + Hardware Request Status Channel 23 + 23 + 1 + read-only + + + HRS23_0 + A hardware service request for channel 23 is not present + 0 + + + HRS23_1 + A hardware service request for channel 23 is present + 0x1 + + + + + HRS24 + Hardware Request Status Channel 24 + 24 + 1 + read-only + + + HRS24_0 + A hardware service request for channel 24 is not present + 0 + + + HRS24_1 + A hardware service request for channel 24 is present + 0x1 + + + + + HRS25 + Hardware Request Status Channel 25 + 25 + 1 + read-only + + + HRS25_0 + A hardware service request for channel 25 is not present + 0 + + + HRS25_1 + A hardware service request for channel 25 is present + 0x1 + + + + + HRS26 + Hardware Request Status Channel 26 + 26 + 1 + read-only + + + HRS26_0 + A hardware service request for channel 26 is not present + 0 + + + HRS26_1 + A hardware service request for channel 26 is present + 0x1 + + + + + HRS27 + Hardware Request Status Channel 27 + 27 + 1 + read-only + + + HRS27_0 + A hardware service request for channel 27 is not present + 0 + + + HRS27_1 + A hardware service request for channel 27 is present + 0x1 + + + + + HRS28 + Hardware Request Status Channel 28 + 28 + 1 + read-only + + + HRS28_0 + A hardware service request for channel 28 is not present + 0 + + + HRS28_1 + A hardware service request for channel 28 is present + 0x1 + + + + + HRS29 + Hardware Request Status Channel 29 + 29 + 1 + read-only + + + HRS29_0 + A hardware service request for channel 29 is not preset + 0 + + + HRS29_1 + A hardware service request for channel 29 is present + 0x1 + + + + + HRS30 + Hardware Request Status Channel 30 + 30 + 1 + read-only + + + HRS30_0 + A hardware service request for channel 30 is not present + 0 + + + HRS30_1 + A hardware service request for channel 30 is present + 0x1 + + + + + HRS31 + Hardware Request Status Channel 31 + 31 + 1 + read-only + + + HRS31_0 + A hardware service request for channel 31 is not present + 0 + + + HRS31_1 + A hardware service request for channel 31 is present + 0x1 + + + + + + + EARS + Enable Asynchronous Request in Stop Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + EDREQ_0 + Enable asynchronous DMA request in stop mode for channel 0. + 0 + 1 + read-write + + + EDREQ_0_0 + Disable asynchronous DMA request for channel 0. + 0 + + + EDREQ_0_1 + Enable asynchronous DMA request for channel 0. + 0x1 + + + + + EDREQ_1 + Enable asynchronous DMA request in stop mode for channel 1. + 1 + 1 + read-write + + + EDREQ_1_0 + Disable asynchronous DMA request for channel 1 + 0 + + + EDREQ_1_1 + Enable asynchronous DMA request for channel 1. + 0x1 + + + + + EDREQ_2 + Enable asynchronous DMA request in stop mode for channel 2. + 2 + 1 + read-write + + + EDREQ_2_0 + Disable asynchronous DMA request for channel 2. + 0 + + + EDREQ_2_1 + Enable asynchronous DMA request for channel 2. + 0x1 + + + + + EDREQ_3 + Enable asynchronous DMA request in stop mode for channel 3. + 3 + 1 + read-write + + + EDREQ_3_0 + Disable asynchronous DMA request for channel 3. + 0 + + + EDREQ_3_1 + Enable asynchronous DMA request for channel 3. + 0x1 + + + + + EDREQ_4 + Enable asynchronous DMA request in stop mode for channel 4 + 4 + 1 + read-write + + + EDREQ_4_0 + Disable asynchronous DMA request for channel 4. + 0 + + + EDREQ_4_1 + Enable asynchronous DMA request for channel 4. + 0x1 + + + + + EDREQ_5 + Enable asynchronous DMA request in stop mode for channel 5 + 5 + 1 + read-write + + + EDREQ_5_0 + Disable asynchronous DMA request for channel 5. + 0 + + + EDREQ_5_1 + Enable asynchronous DMA request for channel 5. + 0x1 + + + + + EDREQ_6 + Enable asynchronous DMA request in stop mode for channel 6 + 6 + 1 + read-write + + + EDREQ_6_0 + Disable asynchronous DMA request for channel 6. + 0 + + + EDREQ_6_1 + Enable asynchronous DMA request for channel 6. + 0x1 + + + + + EDREQ_7 + Enable asynchronous DMA request in stop mode for channel 7 + 7 + 1 + read-write + + + EDREQ_7_0 + Disable asynchronous DMA request for channel 7. + 0 + + + EDREQ_7_1 + Enable asynchronous DMA request for channel 7. + 0x1 + + + + + EDREQ_8 + Enable asynchronous DMA request in stop mode for channel 8 + 8 + 1 + read-write + + + EDREQ_8_0 + Disable asynchronous DMA request for channel 8. + 0 + + + EDREQ_8_1 + Enable asynchronous DMA request for channel 8. + 0x1 + + + + + EDREQ_9 + Enable asynchronous DMA request in stop mode for channel 9 + 9 + 1 + read-write + + + EDREQ_9_0 + Disable asynchronous DMA request for channel 9. + 0 + + + EDREQ_9_1 + Enable asynchronous DMA request for channel 9. + 0x1 + + + + + EDREQ_10 + Enable asynchronous DMA request in stop mode for channel 10 + 10 + 1 + read-write + + + EDREQ_10_0 + Disable asynchronous DMA request for channel 10. + 0 + + + EDREQ_10_1 + Enable asynchronous DMA request for channel 10. + 0x1 + + + + + EDREQ_11 + Enable asynchronous DMA request in stop mode for channel 11 + 11 + 1 + read-write + + + EDREQ_11_0 + Disable asynchronous DMA request for channel 11. + 0 + + + EDREQ_11_1 + Enable asynchronous DMA request for channel 11. + 0x1 + + + + + EDREQ_12 + Enable asynchronous DMA request in stop mode for channel 12 + 12 + 1 + read-write + + + EDREQ_12_0 + Disable asynchronous DMA request for channel 12. + 0 + + + EDREQ_12_1 + Enable asynchronous DMA request for channel 12. + 0x1 + + + + + EDREQ_13 + Enable asynchronous DMA request in stop mode for channel 13 + 13 + 1 + read-write + + + EDREQ_13_0 + Disable asynchronous DMA request for channel 13. + 0 + + + EDREQ_13_1 + Enable asynchronous DMA request for channel 13. + 0x1 + + + + + EDREQ_14 + Enable asynchronous DMA request in stop mode for channel 14 + 14 + 1 + read-write + + + EDREQ_14_0 + Disable asynchronous DMA request for channel 14. + 0 + + + EDREQ_14_1 + Enable asynchronous DMA request for channel 14. + 0x1 + + + + + EDREQ_15 + Enable asynchronous DMA request in stop mode for channel 15 + 15 + 1 + read-write + + + EDREQ_15_0 + Disable asynchronous DMA request for channel 15. + 0 + + + EDREQ_15_1 + Enable asynchronous DMA request for channel 15. + 0x1 + + + + + EDREQ_16 + Enable asynchronous DMA request in stop mode for channel 16 + 16 + 1 + read-write + + + EDREQ_16_0 + Disable asynchronous DMA request for channel 16 + 0 + + + EDREQ_16_1 + Enable asynchronous DMA request for channel 16 + 0x1 + + + + + EDREQ_17 + Enable asynchronous DMA request in stop mode for channel 17 + 17 + 1 + read-write + + + EDREQ_17_0 + Disable asynchronous DMA request for channel 17 + 0 + + + EDREQ_17_1 + Enable asynchronous DMA request for channel 17 + 0x1 + + + + + EDREQ_18 + Enable asynchronous DMA request in stop mode for channel 18 + 18 + 1 + read-write + + + EDREQ_18_0 + Disable asynchronous DMA request for channel 18 + 0 + + + EDREQ_18_1 + Enable asynchronous DMA request for channel 18 + 0x1 + + + + + EDREQ_19 + Enable asynchronous DMA request in stop mode for channel 19 + 19 + 1 + read-write + + + EDREQ_19_0 + Disable asynchronous DMA request for channel 19 + 0 + + + EDREQ_19_1 + Enable asynchronous DMA request for channel 19 + 0x1 + + + + + EDREQ_20 + Enable asynchronous DMA request in stop mode for channel 20 + 20 + 1 + read-write + + + EDREQ_20_0 + Disable asynchronous DMA request for channel 20 + 0 + + + EDREQ_20_1 + Enable asynchronous DMA request for channel 20 + 0x1 + + + + + EDREQ_21 + Enable asynchronous DMA request in stop mode for channel 21 + 21 + 1 + read-write + + + EDREQ_21_0 + Disable asynchronous DMA request for channel 21 + 0 + + + EDREQ_21_1 + Enable asynchronous DMA request for channel 21 + 0x1 + + + + + EDREQ_22 + Enable asynchronous DMA request in stop mode for channel 22 + 22 + 1 + read-write + + + EDREQ_22_0 + Disable asynchronous DMA request for channel 22 + 0 + + + EDREQ_22_1 + Enable asynchronous DMA request for channel 22 + 0x1 + + + + + EDREQ_23 + Enable asynchronous DMA request in stop mode for channel 23 + 23 + 1 + read-write + + + EDREQ_23_0 + Disable asynchronous DMA request for channel 23 + 0 + + + EDREQ_23_1 + Enable asynchronous DMA request for channel 23 + 0x1 + + + + + EDREQ_24 + Enable asynchronous DMA request in stop mode for channel 24 + 24 + 1 + read-write + + + EDREQ_24_0 + Disable asynchronous DMA request for channel 24 + 0 + + + EDREQ_24_1 + Enable asynchronous DMA request for channel 24 + 0x1 + + + + + EDREQ_25 + Enable asynchronous DMA request in stop mode for channel 25 + 25 + 1 + read-write + + + EDREQ_25_0 + Disable asynchronous DMA request for channel 25 + 0 + + + EDREQ_25_1 + Enable asynchronous DMA request for channel 25 + 0x1 + + + + + EDREQ_26 + Enable asynchronous DMA request in stop mode for channel 26 + 26 + 1 + read-write + + + EDREQ_26_0 + Disable asynchronous DMA request for channel 26 + 0 + + + EDREQ_26_1 + Enable asynchronous DMA request for channel 26 + 0x1 + + + + + EDREQ_27 + Enable asynchronous DMA request in stop mode for channel 27 + 27 + 1 + read-write + + + EDREQ_27_0 + Disable asynchronous DMA request for channel 27 + 0 + + + EDREQ_27_1 + Enable asynchronous DMA request for channel 27 + 0x1 + + + + + EDREQ_28 + Enable asynchronous DMA request in stop mode for channel 28 + 28 + 1 + read-write + + + EDREQ_28_0 + Disable asynchronous DMA request for channel 28 + 0 + + + EDREQ_28_1 + Enable asynchronous DMA request for channel 28 + 0x1 + + + + + EDREQ_29 + Enable asynchronous DMA request in stop mode for channel 29 + 29 + 1 + read-write + + + EDREQ_29_0 + Disable asynchronous DMA request for channel 29 + 0 + + + EDREQ_29_1 + Enable asynchronous DMA request for channel 29 + 0x1 + + + + + EDREQ_30 + Enable asynchronous DMA request in stop mode for channel 30 + 30 + 1 + read-write + + + EDREQ_30_0 + Disable asynchronous DMA request for channel 30 + 0 + + + EDREQ_30_1 + Enable asynchronous DMA request for channel 30 + 0x1 + + + + + EDREQ_31 + Enable asynchronous DMA request in stop mode for channel 31 + 31 + 1 + read-write + + + EDREQ_31_0 + Disable asynchronous DMA request for channel 31 + 0 + + + EDREQ_31_1 + Enable asynchronous DMA request for channel 31 + 0x1 + + + + + + + DCHPRI3 + Channel n Priority Register + 0x100 + 8 + read-write + 0x3 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI2 + Channel n Priority Register + 0x101 + 8 + read-write + 0x2 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI1 + Channel n Priority Register + 0x102 + 8 + read-write + 0x1 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI0 + Channel n Priority Register + 0x103 + 8 + read-write + 0 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI7 + Channel n Priority Register + 0x104 + 8 + read-write + 0x7 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI6 + Channel n Priority Register + 0x105 + 8 + read-write + 0x6 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI5 + Channel n Priority Register + 0x106 + 8 + read-write + 0x5 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI4 + Channel n Priority Register + 0x107 + 8 + read-write + 0x4 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI11 + Channel n Priority Register + 0x108 + 8 + read-write + 0xB + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI10 + Channel n Priority Register + 0x109 + 8 + read-write + 0xA + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI9 + Channel n Priority Register + 0x10A + 8 + read-write + 0x9 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI8 + Channel n Priority Register + 0x10B + 8 + read-write + 0x8 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI15 + Channel n Priority Register + 0x10C + 8 + read-write + 0xF + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI14 + Channel n Priority Register + 0x10D + 8 + read-write + 0xE + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI13 + Channel n Priority Register + 0x10E + 8 + read-write + 0xD + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI12 + Channel n Priority Register + 0x10F + 8 + read-write + 0xC + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI19 + Channel n Priority Register + 0x110 + 8 + read-write + 0x13 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI18 + Channel n Priority Register + 0x111 + 8 + read-write + 0x12 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI17 + Channel n Priority Register + 0x112 + 8 + read-write + 0x11 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI16 + Channel n Priority Register + 0x113 + 8 + read-write + 0x10 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI23 + Channel n Priority Register + 0x114 + 8 + read-write + 0x17 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI22 + Channel n Priority Register + 0x115 + 8 + read-write + 0x16 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI21 + Channel n Priority Register + 0x116 + 8 + read-write + 0x15 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI20 + Channel n Priority Register + 0x117 + 8 + read-write + 0x14 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI27 + Channel n Priority Register + 0x118 + 8 + read-write + 0x1B + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI26 + Channel n Priority Register + 0x119 + 8 + read-write + 0x1A + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI25 + Channel n Priority Register + 0x11A + 8 + read-write + 0x19 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI24 + Channel n Priority Register + 0x11B + 8 + read-write + 0x18 + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI31 + Channel n Priority Register + 0x11C + 8 + read-write + 0x1F + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI30 + Channel n Priority Register + 0x11D + 8 + read-write + 0x1E + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI29 + Channel n Priority Register + 0x11E + 8 + read-write + 0x1D + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + DCHPRI28 + Channel n Priority Register + 0x11F + 8 + read-write + 0x1C + 0xFF + + + CHPRI + Channel n Arbitration Priority + 0 + 4 + read-write + + + GRPPRI + Channel n Current Group Priority + 4 + 2 + read-only + + + DPA + Disable Preempt Ability. This field resets to 0. + 6 + 1 + read-write + + + DPA_0 + Channel n can suspend a lower priority channel. + 0 + + + DPA_1 + Channel n cannot suspend any channel, regardless of channel priority. + 0x1 + + + + + ECP + Enable Channel Preemption. This field resets to 0. + 7 + 1 + read-write + + + ECP_0 + Channel n cannot be suspended by a higher priority channel's service request. + 0 + + + ECP_1 + Channel n can be temporarily suspended by the service request of a higher priority channel. + 0x1 + + + + + + + TCD0_SADDR + TCD Source Address + 0x1000 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD0_SOFF + TCD Signed Source Address Offset + 0x1004 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD0_ATTR + TCD Transfer Attributes + 0x1006 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD0_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1008 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD0_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1008 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD0_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1008 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD0_SLAST + TCD Last Source Address Adjustment + 0x100C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD0_DADDR + TCD Destination Address + 0x1010 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD0_DOFF + TCD Signed Destination Address Offset + 0x1014 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD0_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1016 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD0_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1016 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD0_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1018 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD0_CSR + TCD Control and Status + 0x101C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD0_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x101E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD0_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x101E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD1_SADDR + TCD Source Address + 0x1020 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD1_SOFF + TCD Signed Source Address Offset + 0x1024 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD1_ATTR + TCD Transfer Attributes + 0x1026 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD1_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1028 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD1_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1028 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD1_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1028 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD1_SLAST + TCD Last Source Address Adjustment + 0x102C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD1_DADDR + TCD Destination Address + 0x1030 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD1_DOFF + TCD Signed Destination Address Offset + 0x1034 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD1_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1036 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD1_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1036 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD1_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1038 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD1_CSR + TCD Control and Status + 0x103C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD1_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x103E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD1_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x103E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD2_SADDR + TCD Source Address + 0x1040 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD2_SOFF + TCD Signed Source Address Offset + 0x1044 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD2_ATTR + TCD Transfer Attributes + 0x1046 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD2_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1048 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD2_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1048 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD2_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1048 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD2_SLAST + TCD Last Source Address Adjustment + 0x104C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD2_DADDR + TCD Destination Address + 0x1050 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD2_DOFF + TCD Signed Destination Address Offset + 0x1054 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD2_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1056 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD2_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1056 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD2_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1058 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD2_CSR + TCD Control and Status + 0x105C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD2_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x105E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD2_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x105E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD3_SADDR + TCD Source Address + 0x1060 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD3_SOFF + TCD Signed Source Address Offset + 0x1064 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD3_ATTR + TCD Transfer Attributes + 0x1066 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD3_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1068 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD3_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1068 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD3_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1068 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD3_SLAST + TCD Last Source Address Adjustment + 0x106C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD3_DADDR + TCD Destination Address + 0x1070 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD3_DOFF + TCD Signed Destination Address Offset + 0x1074 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD3_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1076 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD3_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1076 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD3_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1078 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD3_CSR + TCD Control and Status + 0x107C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD3_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x107E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD3_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x107E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD4_SADDR + TCD Source Address + 0x1080 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD4_SOFF + TCD Signed Source Address Offset + 0x1084 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD4_ATTR + TCD Transfer Attributes + 0x1086 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD4_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1088 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD4_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1088 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD4_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1088 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD4_SLAST + TCD Last Source Address Adjustment + 0x108C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD4_DADDR + TCD Destination Address + 0x1090 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD4_DOFF + TCD Signed Destination Address Offset + 0x1094 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD4_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1096 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD4_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1096 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD4_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1098 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD4_CSR + TCD Control and Status + 0x109C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD4_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x109E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD4_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x109E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD5_SADDR + TCD Source Address + 0x10A0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD5_SOFF + TCD Signed Source Address Offset + 0x10A4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD5_ATTR + TCD Transfer Attributes + 0x10A6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD5_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x10A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD5_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x10A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD5_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x10A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD5_SLAST + TCD Last Source Address Adjustment + 0x10AC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD5_DADDR + TCD Destination Address + 0x10B0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD5_DOFF + TCD Signed Destination Address Offset + 0x10B4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD5_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x10B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD5_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x10B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD5_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x10B8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD5_CSR + TCD Control and Status + 0x10BC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD5_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x10BE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD5_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x10BE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD6_SADDR + TCD Source Address + 0x10C0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD6_SOFF + TCD Signed Source Address Offset + 0x10C4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD6_ATTR + TCD Transfer Attributes + 0x10C6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD6_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x10C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD6_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x10C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD6_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x10C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD6_SLAST + TCD Last Source Address Adjustment + 0x10CC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD6_DADDR + TCD Destination Address + 0x10D0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD6_DOFF + TCD Signed Destination Address Offset + 0x10D4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD6_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x10D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD6_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x10D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD6_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x10D8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD6_CSR + TCD Control and Status + 0x10DC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD6_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x10DE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD6_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x10DE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD7_SADDR + TCD Source Address + 0x10E0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD7_SOFF + TCD Signed Source Address Offset + 0x10E4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD7_ATTR + TCD Transfer Attributes + 0x10E6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD7_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x10E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD7_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x10E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD7_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x10E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD7_SLAST + TCD Last Source Address Adjustment + 0x10EC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD7_DADDR + TCD Destination Address + 0x10F0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD7_DOFF + TCD Signed Destination Address Offset + 0x10F4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD7_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x10F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD7_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x10F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD7_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x10F8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD7_CSR + TCD Control and Status + 0x10FC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD7_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x10FE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD7_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x10FE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD8_SADDR + TCD Source Address + 0x1100 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD8_SOFF + TCD Signed Source Address Offset + 0x1104 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD8_ATTR + TCD Transfer Attributes + 0x1106 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD8_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1108 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD8_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1108 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD8_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1108 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD8_SLAST + TCD Last Source Address Adjustment + 0x110C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD8_DADDR + TCD Destination Address + 0x1110 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD8_DOFF + TCD Signed Destination Address Offset + 0x1114 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD8_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1116 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD8_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1116 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD8_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1118 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD8_CSR + TCD Control and Status + 0x111C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD8_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x111E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD8_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x111E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD9_SADDR + TCD Source Address + 0x1120 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD9_SOFF + TCD Signed Source Address Offset + 0x1124 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD9_ATTR + TCD Transfer Attributes + 0x1126 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD9_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1128 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD9_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1128 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD9_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1128 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD9_SLAST + TCD Last Source Address Adjustment + 0x112C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD9_DADDR + TCD Destination Address + 0x1130 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD9_DOFF + TCD Signed Destination Address Offset + 0x1134 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD9_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1136 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD9_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1136 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD9_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1138 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD9_CSR + TCD Control and Status + 0x113C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD9_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x113E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD9_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x113E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD10_SADDR + TCD Source Address + 0x1140 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD10_SOFF + TCD Signed Source Address Offset + 0x1144 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD10_ATTR + TCD Transfer Attributes + 0x1146 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD10_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1148 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD10_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1148 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD10_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1148 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD10_SLAST + TCD Last Source Address Adjustment + 0x114C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD10_DADDR + TCD Destination Address + 0x1150 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD10_DOFF + TCD Signed Destination Address Offset + 0x1154 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD10_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1156 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD10_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1156 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD10_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1158 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD10_CSR + TCD Control and Status + 0x115C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD10_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x115E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD10_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x115E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD11_SADDR + TCD Source Address + 0x1160 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD11_SOFF + TCD Signed Source Address Offset + 0x1164 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD11_ATTR + TCD Transfer Attributes + 0x1166 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD11_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1168 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD11_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1168 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD11_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1168 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD11_SLAST + TCD Last Source Address Adjustment + 0x116C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD11_DADDR + TCD Destination Address + 0x1170 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD11_DOFF + TCD Signed Destination Address Offset + 0x1174 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD11_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1176 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD11_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1176 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD11_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1178 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD11_CSR + TCD Control and Status + 0x117C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD11_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x117E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD11_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x117E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD12_SADDR + TCD Source Address + 0x1180 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD12_SOFF + TCD Signed Source Address Offset + 0x1184 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD12_ATTR + TCD Transfer Attributes + 0x1186 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD12_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1188 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD12_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1188 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD12_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1188 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD12_SLAST + TCD Last Source Address Adjustment + 0x118C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD12_DADDR + TCD Destination Address + 0x1190 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD12_DOFF + TCD Signed Destination Address Offset + 0x1194 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD12_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1196 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD12_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1196 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD12_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1198 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD12_CSR + TCD Control and Status + 0x119C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD12_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x119E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD12_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x119E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD13_SADDR + TCD Source Address + 0x11A0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD13_SOFF + TCD Signed Source Address Offset + 0x11A4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD13_ATTR + TCD Transfer Attributes + 0x11A6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD13_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x11A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD13_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x11A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD13_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x11A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD13_SLAST + TCD Last Source Address Adjustment + 0x11AC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD13_DADDR + TCD Destination Address + 0x11B0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD13_DOFF + TCD Signed Destination Address Offset + 0x11B4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD13_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x11B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD13_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x11B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD13_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x11B8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD13_CSR + TCD Control and Status + 0x11BC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD13_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x11BE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD13_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x11BE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD14_SADDR + TCD Source Address + 0x11C0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD14_SOFF + TCD Signed Source Address Offset + 0x11C4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD14_ATTR + TCD Transfer Attributes + 0x11C6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD14_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x11C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD14_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x11C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD14_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x11C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD14_SLAST + TCD Last Source Address Adjustment + 0x11CC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD14_DADDR + TCD Destination Address + 0x11D0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD14_DOFF + TCD Signed Destination Address Offset + 0x11D4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD14_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x11D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD14_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x11D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD14_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x11D8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD14_CSR + TCD Control and Status + 0x11DC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD14_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x11DE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD14_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x11DE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD15_SADDR + TCD Source Address + 0x11E0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD15_SOFF + TCD Signed Source Address Offset + 0x11E4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD15_ATTR + TCD Transfer Attributes + 0x11E6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD15_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x11E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD15_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x11E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD15_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x11E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD15_SLAST + TCD Last Source Address Adjustment + 0x11EC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD15_DADDR + TCD Destination Address + 0x11F0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD15_DOFF + TCD Signed Destination Address Offset + 0x11F4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD15_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x11F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD15_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x11F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD15_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x11F8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD15_CSR + TCD Control and Status + 0x11FC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD15_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x11FE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD15_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x11FE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD16_SADDR + TCD Source Address + 0x1200 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD16_SOFF + TCD Signed Source Address Offset + 0x1204 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD16_ATTR + TCD Transfer Attributes + 0x1206 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD16_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1208 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD16_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1208 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD16_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1208 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD16_SLAST + TCD Last Source Address Adjustment + 0x120C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD16_DADDR + TCD Destination Address + 0x1210 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD16_DOFF + TCD Signed Destination Address Offset + 0x1214 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD16_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1216 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD16_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1216 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD16_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1218 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD16_CSR + TCD Control and Status + 0x121C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD16_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x121E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD16_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x121E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD17_SADDR + TCD Source Address + 0x1220 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD17_SOFF + TCD Signed Source Address Offset + 0x1224 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD17_ATTR + TCD Transfer Attributes + 0x1226 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD17_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1228 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD17_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1228 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD17_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1228 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD17_SLAST + TCD Last Source Address Adjustment + 0x122C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD17_DADDR + TCD Destination Address + 0x1230 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD17_DOFF + TCD Signed Destination Address Offset + 0x1234 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD17_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1236 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD17_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1236 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD17_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1238 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD17_CSR + TCD Control and Status + 0x123C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD17_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x123E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD17_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x123E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD18_SADDR + TCD Source Address + 0x1240 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD18_SOFF + TCD Signed Source Address Offset + 0x1244 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD18_ATTR + TCD Transfer Attributes + 0x1246 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD18_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1248 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD18_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1248 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD18_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1248 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD18_SLAST + TCD Last Source Address Adjustment + 0x124C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD18_DADDR + TCD Destination Address + 0x1250 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD18_DOFF + TCD Signed Destination Address Offset + 0x1254 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD18_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1256 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD18_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1256 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD18_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1258 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD18_CSR + TCD Control and Status + 0x125C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD18_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x125E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD18_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x125E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD19_SADDR + TCD Source Address + 0x1260 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD19_SOFF + TCD Signed Source Address Offset + 0x1264 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD19_ATTR + TCD Transfer Attributes + 0x1266 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD19_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1268 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD19_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1268 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD19_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1268 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD19_SLAST + TCD Last Source Address Adjustment + 0x126C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD19_DADDR + TCD Destination Address + 0x1270 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD19_DOFF + TCD Signed Destination Address Offset + 0x1274 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD19_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1276 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD19_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1276 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD19_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1278 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD19_CSR + TCD Control and Status + 0x127C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD19_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x127E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD19_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x127E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD20_SADDR + TCD Source Address + 0x1280 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD20_SOFF + TCD Signed Source Address Offset + 0x1284 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD20_ATTR + TCD Transfer Attributes + 0x1286 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD20_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1288 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD20_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1288 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD20_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1288 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD20_SLAST + TCD Last Source Address Adjustment + 0x128C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD20_DADDR + TCD Destination Address + 0x1290 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD20_DOFF + TCD Signed Destination Address Offset + 0x1294 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD20_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1296 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD20_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1296 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD20_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1298 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD20_CSR + TCD Control and Status + 0x129C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD20_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x129E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD20_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x129E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD21_SADDR + TCD Source Address + 0x12A0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD21_SOFF + TCD Signed Source Address Offset + 0x12A4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD21_ATTR + TCD Transfer Attributes + 0x12A6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD21_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x12A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD21_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x12A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD21_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x12A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD21_SLAST + TCD Last Source Address Adjustment + 0x12AC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD21_DADDR + TCD Destination Address + 0x12B0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD21_DOFF + TCD Signed Destination Address Offset + 0x12B4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD21_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x12B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD21_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x12B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD21_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x12B8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD21_CSR + TCD Control and Status + 0x12BC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD21_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x12BE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD21_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x12BE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD22_SADDR + TCD Source Address + 0x12C0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD22_SOFF + TCD Signed Source Address Offset + 0x12C4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD22_ATTR + TCD Transfer Attributes + 0x12C6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD22_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x12C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD22_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x12C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD22_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x12C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD22_SLAST + TCD Last Source Address Adjustment + 0x12CC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD22_DADDR + TCD Destination Address + 0x12D0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD22_DOFF + TCD Signed Destination Address Offset + 0x12D4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD22_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x12D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD22_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x12D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD22_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x12D8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD22_CSR + TCD Control and Status + 0x12DC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD22_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x12DE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD22_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x12DE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD23_SADDR + TCD Source Address + 0x12E0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD23_SOFF + TCD Signed Source Address Offset + 0x12E4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD23_ATTR + TCD Transfer Attributes + 0x12E6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD23_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x12E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD23_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x12E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD23_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x12E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD23_SLAST + TCD Last Source Address Adjustment + 0x12EC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD23_DADDR + TCD Destination Address + 0x12F0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD23_DOFF + TCD Signed Destination Address Offset + 0x12F4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD23_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x12F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD23_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x12F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD23_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x12F8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD23_CSR + TCD Control and Status + 0x12FC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD23_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x12FE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD23_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x12FE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD24_SADDR + TCD Source Address + 0x1300 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD24_SOFF + TCD Signed Source Address Offset + 0x1304 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD24_ATTR + TCD Transfer Attributes + 0x1306 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD24_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1308 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD24_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1308 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD24_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1308 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD24_SLAST + TCD Last Source Address Adjustment + 0x130C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD24_DADDR + TCD Destination Address + 0x1310 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD24_DOFF + TCD Signed Destination Address Offset + 0x1314 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD24_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1316 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD24_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1316 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD24_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1318 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD24_CSR + TCD Control and Status + 0x131C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD24_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x131E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD24_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x131E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD25_SADDR + TCD Source Address + 0x1320 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD25_SOFF + TCD Signed Source Address Offset + 0x1324 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD25_ATTR + TCD Transfer Attributes + 0x1326 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD25_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1328 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD25_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1328 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD25_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1328 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD25_SLAST + TCD Last Source Address Adjustment + 0x132C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD25_DADDR + TCD Destination Address + 0x1330 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD25_DOFF + TCD Signed Destination Address Offset + 0x1334 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD25_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1336 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD25_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1336 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD25_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1338 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD25_CSR + TCD Control and Status + 0x133C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD25_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x133E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD25_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x133E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD26_SADDR + TCD Source Address + 0x1340 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD26_SOFF + TCD Signed Source Address Offset + 0x1344 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD26_ATTR + TCD Transfer Attributes + 0x1346 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD26_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1348 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD26_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1348 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD26_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1348 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD26_SLAST + TCD Last Source Address Adjustment + 0x134C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD26_DADDR + TCD Destination Address + 0x1350 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD26_DOFF + TCD Signed Destination Address Offset + 0x1354 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD26_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1356 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD26_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1356 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD26_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1358 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD26_CSR + TCD Control and Status + 0x135C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD26_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x135E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD26_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x135E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD27_SADDR + TCD Source Address + 0x1360 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD27_SOFF + TCD Signed Source Address Offset + 0x1364 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD27_ATTR + TCD Transfer Attributes + 0x1366 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD27_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1368 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD27_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1368 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD27_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1368 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD27_SLAST + TCD Last Source Address Adjustment + 0x136C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD27_DADDR + TCD Destination Address + 0x1370 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD27_DOFF + TCD Signed Destination Address Offset + 0x1374 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD27_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1376 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD27_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1376 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD27_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1378 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD27_CSR + TCD Control and Status + 0x137C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD27_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x137E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD27_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x137E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD28_SADDR + TCD Source Address + 0x1380 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD28_SOFF + TCD Signed Source Address Offset + 0x1384 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD28_ATTR + TCD Transfer Attributes + 0x1386 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD28_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x1388 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD28_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x1388 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD28_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x1388 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD28_SLAST + TCD Last Source Address Adjustment + 0x138C + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD28_DADDR + TCD Destination Address + 0x1390 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD28_DOFF + TCD Signed Destination Address Offset + 0x1394 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD28_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x1396 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD28_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x1396 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD28_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x1398 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD28_CSR + TCD Control and Status + 0x139C + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD28_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x139E + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD28_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x139E + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD29_SADDR + TCD Source Address + 0x13A0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD29_SOFF + TCD Signed Source Address Offset + 0x13A4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD29_ATTR + TCD Transfer Attributes + 0x13A6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD29_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x13A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD29_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x13A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD29_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x13A8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD29_SLAST + TCD Last Source Address Adjustment + 0x13AC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD29_DADDR + TCD Destination Address + 0x13B0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD29_DOFF + TCD Signed Destination Address Offset + 0x13B4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD29_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x13B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD29_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x13B6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD29_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x13B8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD29_CSR + TCD Control and Status + 0x13BC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD29_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x13BE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD29_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x13BE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD30_SADDR + TCD Source Address + 0x13C0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD30_SOFF + TCD Signed Source Address Offset + 0x13C4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD30_ATTR + TCD Transfer Attributes + 0x13C6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD30_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x13C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD30_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x13C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD30_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x13C8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD30_SLAST + TCD Last Source Address Adjustment + 0x13CC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD30_DADDR + TCD Destination Address + 0x13D0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD30_DOFF + TCD Signed Destination Address Offset + 0x13D4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD30_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x13D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD30_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x13D6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD30_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x13D8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD30_CSR + TCD Control and Status + 0x13DC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD30_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x13DE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD30_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x13DE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD31_SADDR + TCD Source Address + 0x13E0 + 32 + read-write + 0 + 0 + + + SADDR + Source Address + 0 + 32 + read-write + + + + + TCD31_SOFF + TCD Signed Source Address Offset + 0x13E4 + 16 + read-write + 0 + 0 + + + SOFF + Source address signed offset + 0 + 16 + read-write + + + + + TCD31_ATTR + TCD Transfer Attributes + 0x13E6 + 16 + read-write + 0 + 0 + + + DSIZE + Destination data transfer size + 0 + 3 + read-write + + + DMOD + Destination Address Modulo + 3 + 5 + read-write + + + SSIZE + Source data transfer size + 8 + 3 + read-write + + + SSIZE_0 + 8-bit + 0 + + + SSIZE_1 + 16-bit + 0x1 + + + SSIZE_2 + 32-bit + 0x2 + + + SSIZE_3 + 64-bit + 0x3 + + + SSIZE_5 + 32-byte burst (4 beats of 64 bits) + 0x5 + + + + + SMOD + Source Address Modulo + 11 + 5 + read-write + + + SMOD_0 + Source address modulo feature is disabled + 0 + + + SMOD_1 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x1 + + + SMOD_2 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x2 + + + SMOD_3 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x3 + + + SMOD_4 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x4 + + + SMOD_5 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x5 + + + SMOD_6 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x6 + + + SMOD_7 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x7 + + + SMOD_8 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x8 + + + SMOD_9 + This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. + 0x9 + + + + + + + TCD31_NBYTES_MLNO + TCD Minor Byte Count (Minor Loop Mapping Disabled) + TCD_NBYTES + 0x13E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 32 + read-write + + + + + TCD31_NBYTES_MLOFFNO + TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) + TCD_NBYTES + 0x13E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 30 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD31_NBYTES_MLOFFYES + TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) + TCD_NBYTES + 0x13E8 + 32 + read-write + 0 + 0 + + + NBYTES + Minor Byte Transfer Count + 0 + 10 + read-write + + + MLOFF + If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. + 10 + 20 + read-write + + + DMLOE + Destination Minor Loop Offset enable + 30 + 1 + read-write + + + DMLOE_0 + The minor loop offset is not applied to the DADDR + 0 + + + DMLOE_1 + The minor loop offset is applied to the DADDR + 0x1 + + + + + SMLOE + Source Minor Loop Offset Enable + 31 + 1 + read-write + + + SMLOE_0 + The minor loop offset is not applied to the SADDR + 0 + + + SMLOE_1 + The minor loop offset is applied to the SADDR + 0x1 + + + + + + + TCD31_SLAST + TCD Last Source Address Adjustment + 0x13EC + 32 + read-write + 0 + 0 + + + SLAST + Last Source Address Adjustment + 0 + 32 + read-write + + + + + TCD31_DADDR + TCD Destination Address + 0x13F0 + 32 + read-write + 0 + 0 + + + DADDR + Destination Address + 0 + 32 + read-write + + + + + TCD31_DOFF + TCD Signed Destination Address Offset + 0x13F4 + 16 + read-write + 0 + 0 + + + DOFF + Destination Address Signed Offset + 0 + 16 + read-write + + + + + TCD31_CITER_ELINKNO + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_CITER_ELINK + 0x13F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD31_CITER_ELINKYES + TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_CITER_ELINK + 0x13F6 + 16 + read-write + 0 + 0 + + + CITER + Current Major Iteration Count + 0 + 9 + read-write + + + LINKCH + Minor Loop Link Channel Number + 9 + 5 + read-write + + + ELINK + Enable channel-to-channel linking on minor-loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD31_DLASTSGA + TCD Last Destination Address Adjustment/Scatter Gather Address + 0x13F8 + 32 + read-write + 0 + 0 + + + DLASTSGA + DLASTSGA + 0 + 32 + read-write + + + + + TCD31_CSR + TCD Control and Status + 0x13FC + 16 + read-write + 0 + 0 + + + START + Channel Start + 0 + 1 + read-write + + + START_0 + The channel is not explicitly started. + 0 + + + START_1 + The channel is explicitly started via a software initiated service request. + 0x1 + + + + + INTMAJOR + Enable an interrupt when major iteration count completes. + 1 + 1 + read-write + + + INTMAJOR_0 + The end-of-major loop interrupt is disabled. + 0 + + + INTMAJOR_1 + The end-of-major loop interrupt is enabled. + 0x1 + + + + + INTHALF + Enable an interrupt when major counter is half complete. + 2 + 1 + read-write + + + INTHALF_0 + The half-point interrupt is disabled. + 0 + + + INTHALF_1 + The half-point interrupt is enabled. + 0x1 + + + + + DREQ + Disable Request + 3 + 1 + read-write + + + DREQ_0 + The channel's ERQ bit is not affected. + 0 + + + DREQ_1 + The channel's ERQ bit is cleared when the major loop is complete. + 0x1 + + + + + ESG + Enable Scatter/Gather Processing + 4 + 1 + read-write + + + ESG_0 + The current channel's TCD is normal format. + 0 + + + ESG_1 + The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. + 0x1 + + + + + MAJORELINK + Enable channel-to-channel linking on major loop complete + 5 + 1 + read-write + + + MAJORELINK_0 + The channel-to-channel linking is disabled. + 0 + + + MAJORELINK_1 + The channel-to-channel linking is enabled. + 0x1 + + + + + ACTIVE + Channel Active + 6 + 1 + read-only + + + DONE + Channel Done + 7 + 1 + read-write + zeroToClear + + + MAJORLINKCH + Major Loop Link Channel Number + 8 + 5 + read-write + + + BWC + Bandwidth Control + 14 + 2 + read-write + + + BWC_0 + No eDMA engine stalls. + 0 + + + BWC_2 + eDMA engine stalls for 4 cycles after each R/W. + 0x2 + + + BWC_3 + eDMA engine stalls for 8 cycles after each R/W. + 0x3 + + + + + + + TCD31_BITER_ELINKNO + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) + TCD_BITER_ELINK + 0x13FE + 16 + read-write + 0 + 0 + + + BITER + Starting Major Iteration Count + 0 + 15 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + TCD31_BITER_ELINKYES + TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) + TCD_BITER_ELINK + 0x13FE + 16 + read-write + 0 + 0 + + + BITER + Starting major iteration count + 0 + 9 + read-write + + + LINKCH + Link Channel Number + 9 + 5 + read-write + + + ELINK + Enables channel-to-channel linking on minor loop complete + 15 + 1 + read-write + + + ELINK_0 + The channel-to-channel linking is disabled + 0 + + + ELINK_1 + The channel-to-channel linking is enabled + 0x1 + + + + + + + + + DMAMUX + DMA_CH_MUX + DMAMUX + 0x400EC000 + + 0 + 0x80 + registers + + + + 32 + 0x4 + CHCFG[%s] + Channel 0 Configuration Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SOURCE + DMA Channel Source (Slot Number) + 0 + 7 + read-write + + + A_ON + DMA Channel Always Enable + 29 + 1 + read-write + + + A_ON_0 + DMA Channel Always ON function is disabled + 0 + + + A_ON_1 + DMA Channel Always ON function is enabled + 0x1 + + + + + TRIG + DMA Channel Trigger Enable + 30 + 1 + read-write + + + TRIG_0 + Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) + 0 + + + TRIG_1 + Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. + 0x1 + + + + + ENBL + DMA Mux Channel Enable + 31 + 1 + read-write + + + ENBL_0 + DMA Mux channel is disabled + 0 + + + ENBL_1 + DMA Mux channel is enabled + 0x1 + + + + + + + + + GPC + GPC + GPC + GPC_ + 0x400F4000 + + 0 + 0x3C + registers + + + GPC + 97 + + + + CNTR + GPC Interface control register + 0 + 32 + read-write + 0x520000 + 0xFFFFFFFF + + + MEGA_PDN_REQ + MEGA domain power down request + 2 + 1 + read-write + + + MEGA_PDN_REQ_0 + No Request + 0 + + + MEGA_PDN_REQ_1 + Request power down sequence + 0x1 + + + + + MEGA_PUP_REQ + MEGA domain power up request + 3 + 1 + read-write + + + MEGA_PUP_REQ_0 + No Request + 0 + + + MEGA_PUP_REQ_1 + Request power up sequence + 0x1 + + + + + PDRAM0_PGE + FlexRAM PDRAM0 Power Gate Enable + 22 + 1 + read-write + + + PDRAM0_PGE_0 + FlexRAM PDRAM0 domain will keep power on even if CPU core is power down. + 0 + + + PDRAM0_PGE_1 + FlexRAM PDRAM0 domain will be power down once when CPU core is power down. + 0x1 + + + + + + + IMR1 + IRQ masking register 1 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR1 + IRQ[31:0] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + IMR2 + IRQ masking register 2 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR2 + IRQ[63:32] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + IMR3 + IRQ masking register 3 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR3 + IRQ[95:64] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + IMR4 + IRQ masking register 4 + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR4 + IRQ[127:96] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + ISR1 + IRQ status resister 1 + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR1 + IRQ[31:0] status, read only + 0 + 32 + read-only + + + + + ISR2 + IRQ status resister 2 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR2 + IRQ[63:32] status, read only + 0 + 32 + read-only + + + + + ISR3 + IRQ status resister 3 + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR3 + IRQ[95:64] status, read only + 0 + 32 + read-only + + + + + ISR4 + IRQ status resister 4 + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR4 + IRQ[127:96] status, read only + 0 + 32 + read-only + + + + + IMR5 + IRQ masking register 5 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR5 + IRQ[159:128] masking bits: 1-irq masked, 0-irq is not masked + 0 + 32 + read-write + + + + + ISR5 + IRQ status resister 5 + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + ISR4 + IRQ[159:128] status, read only + 0 + 32 + read-only + + + + + + + PGC + PGC + GPC + PGC + PGC_ + 0x400F4000 + + 0 + 0x2B0 + registers + + + + MEGA_CTRL + PGC Mega Control Register + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCR + Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + + + MEGA_PUPSCR + PGC Mega Power Up Sequence Control Register + 0x224 + 32 + read-write + 0xF01 + 0xFFFFFFFF + + + SW + After a power-up request (pup_req assertion), the PGC waits a number of IPG clocks equal to the value of SW before asserting power toggle on/off signal (switch_b) + 0 + 6 + read-write + + + SW2ISO + After asserting power toggle on/off signal (switch_b), the PGC waits a number of IPG clocks equal to the value of SW2ISO before negating isolation + 8 + 6 + read-write + + + + + MEGA_PDNSCR + PGC Mega Pull Down Sequence Control Register + 0x228 + 32 + read-write + 0x101 + 0xFFFFFFFF + + + ISO + After a power-down request (pdn_req assertion), the PGC waits a number of IPG clocks equal to the value of ISO before asserting isolation + 0 + 6 + read-write + + + ISO2SW + After asserting isolation, the PGC waits a number of IPG clocks equal to the value of ISO2SW before negating power toggle on/off signal (switch_b) + 8 + 6 + read-write + + + + + MEGA_SR + PGC Mega Power Gating Controller Status Register + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-write + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + + + CPU_CTRL + PGC CPU Control Register + 0x2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PCR + Power Control PCR must not change from power-down request (pdn_req) assertion until the target subsystem is completely powered up + 0 + 1 + read-write + + + PCR_0 + Do not switch off power even if pdn_req is asserted. + 0 + + + PCR_1 + Switch off power when pdn_req is asserted. + 0x1 + + + + + + + CPU_PUPSCR + PGC CPU Power Up Sequence Control Register + 0x2A4 + 32 + read-write + 0xF01 + 0xFFFFFFFF + + + SW + There are two different silicon revisions: 1 + 0 + 6 + read-write + + + SW2ISO + There are two different silicon revisions: 1 + 8 + 6 + read-write + + + + + CPU_PDNSCR + PGC CPU Pull Down Sequence Control Register + 0x2A8 + 32 + read-write + 0x101 + 0xFFFFFFFF + + + ISO + After a power-down request (pdn_req assertion), the PGC waits a number of 32k clocks equal to the value of ISO before asserting isolation + 0 + 6 + read-write + + + ISO2SW + After asserting isolation, the PGC waits a number of 32k clocks equal to the value of ISO2SW before negating + 8 + 6 + read-write + + + + + CPU_SR + PGC CPU Power Gating Controller Status Register + 0x2AC + 32 + read-write + 0 + 0xFFFFFFFF + + + PSR + Power status + 0 + 1 + read-write + + + PSR_0 + The target subsystem was not powered down for the previous power-down request. + 0 + + + PSR_1 + The target subsystem was powered down for the previous power-down request. + 0x1 + + + + + + + + + SRC + SRC + SRC + SRC_ + 0x400F8000 + + 0 + 0x48 + registers + + + SRC + 98 + + + + SCR + SRC Control Register + 0 + 32 + read-write + 0xA0480520 + 0xFFFFFFFF + + + mask_wdog_rst + Mask wdog_rst_b source + 7 + 4 + read-write + + + mask_wdog_rst_5 + wdog_rst_b is masked + 0x5 + + + mask_wdog_rst_10 + wdog_rst_b is not masked (default) + 0xA + + + + + core0_rst + Software reset for core0 only + 13 + 1 + read-write + + + core0_rst_0 + do not assert core0 reset + 0 + + + core0_rst_1 + assert core0 reset + 0x1 + + + + + core0_dbg_rst + Software reset for core0 debug only + 17 + 1 + read-write + + + core0_dbg_rst_0 + do not assert core0 debug reset + 0 + + + core0_dbg_rst_1 + assert core0 debug reset + 0x1 + + + + + dbg_rst_msk_pg + Do not assert debug resets after power gating event of core + 25 + 1 + read-write + + + dbg_rst_msk_pg_0 + do not mask core debug resets (debug resets will be asserted after power gating event) + 0 + + + dbg_rst_msk_pg_1 + mask core debug resets (debug resets won't be asserted after power gating event) + 0x1 + + + + + mask_wdog3_rst + Mask wdog3_rst_b source + 28 + 4 + read-write + + + mask_wdog3_rst_5 + wdog3_rst_b is masked + 0x5 + + + mask_wdog3_rst_10 + wdog3_rst_b is not masked + 0xA + + + + + + + SBMR1 + SRC Boot Mode Register 1 + 0x4 + 32 + read-only + 0 + 0xFFFFFFFF + + + BOOT_CFG1 + Refer to fusemap. + 0 + 8 + read-only + + + BOOT_CFG2 + Refer to fusemap. + 8 + 8 + read-only + + + BOOT_CFG3 + Refer to fusemap. + 16 + 8 + read-only + + + BOOT_CFG4 + Refer to fusemap. + 24 + 8 + read-only + + + + + SRSR + SRC Reset Status Register + 0x8 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + ipp_reset_b + Indicates whether reset was the result of ipp_reset_b pin (Power-up sequence) + 0 + 1 + read-write + oneToClear + + + ipp_reset_b_0 + Reset is not a result of ipp_reset_b pin. + 0 + + + ipp_reset_b_1 + Reset is a result of ipp_reset_b pin. + 0x1 + + + + + lockup_sysresetreq + Indicates a reset has been caused by CPU lockup or software setting of SYSRESETREQ bit in Application Interrupt and Reset Control Register of the ARM core + 1 + 1 + read-write + oneToClear + + + lockup_sysresetreq_0 + Reset is not a result of the mentioned case. + 0 + + + lockup_sysresetreq_1 + Reset is a result of the mentioned case. + 0x1 + + + + + csu_reset_b + Indicates whether the reset was the result of the csu_reset_b input. + 2 + 1 + read-write + oneToClear + + + csu_reset_b_0 + Reset is not a result of the csu_reset_b event. + 0 + + + csu_reset_b_1 + Reset is a result of the csu_reset_b event. + 0x1 + + + + + ipp_user_reset_b + Indicates whether the reset was the result of the ipp_user_reset_b qualified reset. + 3 + 1 + read-write + oneToClear + + + ipp_user_reset_b_0 + Reset is not a result of the ipp_user_reset_b qualified as COLD reset event. + 0 + + + ipp_user_reset_b_1 + Reset is a result of the ipp_user_reset_b qualified as COLD reset event. + 0x1 + + + + + wdog_rst_b + IC Watchdog Time-out reset + 4 + 1 + read-write + oneToClear + + + wdog_rst_b_0 + Reset is not a result of the watchdog time-out event. + 0 + + + wdog_rst_b_1 + Reset is a result of the watchdog time-out event. + 0x1 + + + + + jtag_rst_b + HIGH - Z JTAG reset. Indicates whether the reset was the result of HIGH-Z reset from JTAG. + 5 + 1 + read-write + oneToClear + + + jtag_rst_b_0 + Reset is not a result of HIGH-Z reset from JTAG. + 0 + + + jtag_rst_b_1 + Reset is a result of HIGH-Z reset from JTAG. + 0x1 + + + + + jtag_sw_rst + JTAG software reset. Indicates whether the reset was the result of software reset from JTAG. + 6 + 1 + read-write + oneToClear + + + jtag_sw_rst_0 + Reset is not a result of software reset from JTAG. + 0 + + + jtag_sw_rst_1 + Reset is a result of software reset from JTAG. + 0x1 + + + + + wdog3_rst_b + IC Watchdog3 Time-out reset + 7 + 1 + read-write + oneToClear + + + wdog3_rst_b_0 + Reset is not a result of the watchdog3 time-out event. + 0 + + + wdog3_rst_b_1 + Reset is a result of the watchdog3 time-out event. + 0x1 + + + + + tempsense_rst_b + Temper Sensor software reset + 8 + 1 + read-write + + + tempsense_rst_b_0 + Reset is not a result of software reset from Temperature Sensor. + 0 + + + tempsense_rst_b_1 + Reset is a result of software reset from Temperature Sensor. + 0x1 + + + + + + + SBMR2 + SRC Boot Mode Register 2 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + SEC_CONFIG + SECONFIG[1] shows the state of the SECONFIG[1] fuse + 0 + 2 + read-only + + + DIR_BT_DIS + DIR_BT_DIS shows the state of the DIR_BT_DIS fuse + 3 + 1 + read-only + + + BT_FUSE_SEL + BT_FUSE_SEL (connected to gpio bt_fuse_sel) shows the state of the BT_FUSE_SEL fuse + 4 + 1 + read-only + + + BMOD + BMOD[1:0] shows the latched state of the BOOT_MODE1 and BOOT_MODE0 signals on the rising edge of POR_B + 24 + 2 + read-only + + + + + GPR1 + SRC General Purpose Register 1 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ENTRY0 + Holds entry function for core0 for waking-up from low power mode + 0 + 32 + read-write + + + + + GPR2 + SRC General Purpose Register 2 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERSISTENT_ARG0 + Holds argument of entry function for core0 for waking-up from low power mode + 0 + 32 + read-write + + + + + GPR3 + SRC General Purpose Register 3 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR4 + SRC General Purpose Register 4 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR5 + SRC General Purpose Register 5 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR6 + SRC General Purpose Register 6 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR7 + SRC General Purpose Register 7 + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR8 + SRC General Purpose Register 8 + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPR9 + SRC General Purpose Register 9 + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + GPR10 + SRC General Purpose Register 10 + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + + + CCM + CCM + CCM + CCM_ + 0x400FC000 + + 0 + 0x8C + registers + + + CCM_1 + 95 + + + CCM_2 + 96 + + + + CCR + CCM Control Register + 0 + 32 + read-write + 0x401107F + 0xFFFFFFFF + + + OSCNT + Oscillator ready counter value. These bits define value of 32KHz counter, that serve as counter for oscillator lock time (count to n+1 ckil's). This is used for oscillator lock time. Current estimation is ~5ms. This counter will be used in ignition sequence and in wake from stop sequence if sbyos bit was defined, to notify that on chip oscillator output is ready for the dpll_ip to use and only then the gate in dpll_ip can be opened. + 0 + 8 + read-write + + + COSC_EN + On chip oscillator enable bit - this bit value is reflected on the output cosc_en + 12 + 1 + read-write + + + COSC_EN_0 + disable on chip oscillator + 0 + + + COSC_EN_1 + enable on chip oscillator + 0x1 + + + + + REG_BYPASS_COUNT + Counter for analog_reg_bypass signal assertion after standby voltage request by PMIC_STBY_REQ + 21 + 6 + read-write + + + REG_BYPASS_COUNT_0 + no delay + 0 + + + REG_BYPASS_COUNT_1 + 1 CKIL clock period delay + 0x1 + + + REG_BYPASS_COUNT_63 + 63 CKIL clock periods delay + 0x3F + + + + + RBC_EN + Enable for REG_BYPASS_COUNTER + 27 + 1 + read-write + + + RBC_EN_0 + REG_BYPASS_COUNTER disabled + 0 + + + RBC_EN_1 + REG_BYPASS_COUNTER enabled. + 0x1 + + + + + + + CSR + CCM Status Register + 0x8 + 32 + read-only + 0x10 + 0xFFFFFFFF + + + REF_EN_B + Status of the value of CCM_REF_EN_B output of ccm + 0 + 1 + read-only + + + REF_EN_B_0 + value of CCM_REF_EN_B is '0' + 0 + + + REF_EN_B_1 + value of CCM_REF_EN_B is '1' + 0x1 + + + + + CAMP2_READY + Status indication of CAMP2. + 3 + 1 + read-only + + + CAMP2_READY_0 + CAMP2 is not ready. + 0 + + + CAMP2_READY_1 + CAMP2 is ready. + 0x1 + + + + + COSC_READY + Status indication of on board oscillator + 5 + 1 + read-only + + + COSC_READY_0 + on board oscillator is not ready. + 0 + + + COSC_READY_1 + on board oscillator is ready. + 0x1 + + + + + + + CCSR + CCM Clock Switcher Register + 0xC + 32 + read-write + 0x100 + 0xFFFFFFFF + + + PLL3_SW_CLK_SEL + Selects source to generate pll3_sw_clk. This bit should only be used for testing purposes. + 0 + 1 + read-write + + + PLL3_SW_CLK_SEL_0 + pll3_main_clk + 0 + + + PLL3_SW_CLK_SEL_1 + pll3 bypass clock + 0x1 + + + + + + + CACRR + CCM Arm Clock Root Register + 0x10 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + ARM_PODF + Divider for ARM clock root + 0 + 3 + read-write + + + ARM_PODF_0 + divide by 1 + 0 + + + ARM_PODF_1 + divide by 2 + 0x1 + + + ARM_PODF_2 + divide by 3 + 0x2 + + + ARM_PODF_3 + divide by 4 + 0x3 + + + ARM_PODF_4 + divide by 5 + 0x4 + + + ARM_PODF_5 + divide by 6 + 0x5 + + + ARM_PODF_6 + divide by 7 + 0x6 + + + ARM_PODF_7 + divide by 8 + 0x7 + + + + + + + CBCDR + CCM Bus Clock Divider Register + 0x14 + 32 + read-write + 0xA8300 + 0xFFFFFFFF + + + SEMC_CLK_SEL + SEMC clock source select + 6 + 1 + read-write + + + SEMC_CLK_SEL_0 + Periph_clk output will be used as SEMC clock root + 0 + + + SEMC_CLK_SEL_1 + SEMC alternative clock will be used as SEMC clock root + 0x1 + + + + + SEMC_ALT_CLK_SEL + SEMC alternative clock select + 7 + 1 + read-write + + + SEMC_ALT_CLK_SEL_0 + PLL2 PFD2 will be selected as alternative clock for SEMC root clock + 0 + + + SEMC_ALT_CLK_SEL_1 + PLL3 PFD1 will be selected as alternative clock for SEMC root clock + 0x1 + + + + + IPG_PODF + Divider for ipg podf. + 8 + 2 + read-write + + + IPG_PODF_0 + divide by 1 + 0 + + + IPG_PODF_1 + divide by 2 + 0x1 + + + IPG_PODF_2 + divide by 3 + 0x2 + + + IPG_PODF_3 + divide by 4 + 0x3 + + + + + AHB_PODF + Divider for AHB PODF + 10 + 3 + read-write + + + AHB_PODF_0 + divide by 1 + 0 + + + AHB_PODF_1 + divide by 2 + 0x1 + + + AHB_PODF_2 + divide by 3 + 0x2 + + + AHB_PODF_3 + divide by 4 + 0x3 + + + AHB_PODF_4 + divide by 5 + 0x4 + + + AHB_PODF_5 + divide by 6 + 0x5 + + + AHB_PODF_6 + divide by 7 + 0x6 + + + AHB_PODF_7 + divide by 8 + 0x7 + + + + + SEMC_PODF + Post divider for SEMC clock + 16 + 3 + read-write + + + SEMC_PODF_0 + divide by 1 + 0 + + + SEMC_PODF_1 + divide by 2 + 0x1 + + + SEMC_PODF_2 + divide by 3 + 0x2 + + + SEMC_PODF_3 + divide by 4 + 0x3 + + + SEMC_PODF_4 + divide by 5 + 0x4 + + + SEMC_PODF_5 + divide by 6 + 0x5 + + + SEMC_PODF_6 + divide by 7 + 0x6 + + + SEMC_PODF_7 + divide by 8 + 0x7 + + + + + PERIPH_CLK_SEL + Selector for peripheral main clock + 25 + 1 + read-write + + + PERIPH_CLK_SEL_0 + derive clock from pre_periph_clk_sel + 0 + + + PERIPH_CLK_SEL_1 + derive clock from periph_clk2_clk_divided + 0x1 + + + + + PERIPH_CLK2_PODF + Divider for periph_clk2_podf. + 27 + 3 + read-write + + + PERIPH_CLK2_PODF_0 + divide by 1 + 0 + + + PERIPH_CLK2_PODF_1 + divide by 2 + 0x1 + + + PERIPH_CLK2_PODF_2 + divide by 3 + 0x2 + + + PERIPH_CLK2_PODF_3 + divide by 4 + 0x3 + + + PERIPH_CLK2_PODF_4 + divide by 5 + 0x4 + + + PERIPH_CLK2_PODF_5 + divide by 6 + 0x5 + + + PERIPH_CLK2_PODF_6 + divide by 7 + 0x6 + + + PERIPH_CLK2_PODF_7 + divide by 8 + 0x7 + + + + + + + CBCMR + CCM Bus Clock Multiplexer Register + 0x18 + 32 + read-write + 0x2DAE8324 + 0xFFFFFFFF + + + LPSPI_CLK_SEL + Selector for lpspi clock multiplexer + 4 + 2 + read-write + + + LPSPI_CLK_SEL_0 + derive clock from PLL3 PFD1 clk + 0 + + + LPSPI_CLK_SEL_1 + derive clock from PLL3 PFD0 + 0x1 + + + LPSPI_CLK_SEL_2 + derive clock from PLL2 + 0x2 + + + LPSPI_CLK_SEL_3 + derive clock from PLL2 PFD2 + 0x3 + + + + + FLEXSPI2_CLK_SEL + Selector for flexspi2 clock multiplexer + 8 + 2 + read-write + + + FLEXSPI2_CLK_SEL_0 + derive clock from PLL2 PFD2 + 0 + + + FLEXSPI2_CLK_SEL_1 + derive clock from PLL3 PFD0 + 0x1 + + + FLEXSPI2_CLK_SEL_2 + derive clock from PLL3 PFD1 + 0x2 + + + FLEXSPI2_CLK_SEL_3 + derive clock from PLL2 (pll2_main_clk) + 0x3 + + + + + PERIPH_CLK2_SEL + Selector for peripheral clk2 clock multiplexer + 12 + 2 + read-write + + + PERIPH_CLK2_SEL_0 + derive clock from pll3_sw_clk + 0 + + + PERIPH_CLK2_SEL_1 + derive clock from osc_clk (pll1_ref_clk) + 0x1 + + + PERIPH_CLK2_SEL_2 + derive clock from pll2_bypass_clk + 0x2 + + + + + TRACE_CLK_SEL + Selector for Trace clock multiplexer + 14 + 2 + read-write + + + TRACE_CLK_SEL_0 + derive clock from PLL2 + 0 + + + TRACE_CLK_SEL_1 + derive clock from PLL2 PFD2 + 0x1 + + + TRACE_CLK_SEL_2 + derive clock from PLL2 PFD0 + 0x2 + + + TRACE_CLK_SEL_3 + derive clock from PLL2 PFD1 + 0x3 + + + + + PRE_PERIPH_CLK_SEL + Selector for pre_periph clock multiplexer + 18 + 2 + read-write + + + PRE_PERIPH_CLK_SEL_0 + derive clock from PLL2 + 0 + + + PRE_PERIPH_CLK_SEL_1 + derive clock from PLL2 PFD2 + 0x1 + + + PRE_PERIPH_CLK_SEL_2 + derive clock from PLL2 PFD0 + 0x2 + + + PRE_PERIPH_CLK_SEL_3 + derive clock from divided PLL1 + 0x3 + + + + + LCDIF_PODF + Post-divider for LCDIF clock. + 23 + 3 + read-write + + + LCDIF_PODF_0 + divide by 1 + 0 + + + LCDIF_PODF_1 + divide by 2 + 0x1 + + + LCDIF_PODF_2 + divide by 3 + 0x2 + + + LCDIF_PODF_3 + divide by 4 + 0x3 + + + LCDIF_PODF_4 + divide by 5 + 0x4 + + + LCDIF_PODF_5 + divide by 6 + 0x5 + + + LCDIF_PODF_6 + divide by 7 + 0x6 + + + LCDIF_PODF_7 + divide by 8 + 0x7 + + + + + LPSPI_PODF + Divider for LPSPI. Divider should be updated when output clock is gated. + 26 + 3 + read-write + + + LPSPI_PODF_0 + divide by 1 + 0 + + + LPSPI_PODF_1 + divide by 2 + 0x1 + + + LPSPI_PODF_2 + divide by 3 + 0x2 + + + LPSPI_PODF_3 + divide by 4 + 0x3 + + + LPSPI_PODF_4 + divide by 5 + 0x4 + + + LPSPI_PODF_5 + divide by 6 + 0x5 + + + LPSPI_PODF_6 + divide by 7 + 0x6 + + + LPSPI_PODF_7 + divide by 8 + 0x7 + + + + + FLEXSPI2_PODF + Divider for flexspi2 clock root. + 29 + 3 + read-write + + + FLEXSPI2_PODF_0 + divide by 1 + 0 + + + FLEXSPI2_PODF_1 + divide by 2 + 0x1 + + + FLEXSPI2_PODF_2 + divide by 3 + 0x2 + + + FLEXSPI2_PODF_3 + divide by 4 + 0x3 + + + FLEXSPI2_PODF_4 + divide by 5 + 0x4 + + + FLEXSPI2_PODF_5 + divide by 6 + 0x5 + + + FLEXSPI2_PODF_6 + divide by 7 + 0x6 + + + FLEXSPI2_PODF_7 + divide by 8 + 0x7 + + + + + + + CSCMR1 + CCM Serial Clock Multiplexer Register 1 + 0x1C + 32 + read-write + 0x4900000 + 0xFFFFFFFF + + + PERCLK_PODF + Divider for perclk podf. + 0 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + PERCLK_CLK_SEL + Selector for the perclk clock multiplexor + 6 + 1 + read-write + + + PERCLK_CLK_SEL_0 + derive clock from ipg clk root + 0 + + + PERCLK_CLK_SEL_1 + derive clock from osc_clk + 0x1 + + + + + SAI1_CLK_SEL + Selector for sai1 clock multiplexer + 10 + 2 + read-write + + + SAI1_CLK_SEL_0 + derive clock from PLL3 PFD2 + 0 + + + SAI1_CLK_SEL_1 + derive clock from PLL5 + 0x1 + + + SAI1_CLK_SEL_2 + derive clock from PLL4 + 0x2 + + + + + SAI2_CLK_SEL + Selector for sai2 clock multiplexer + 12 + 2 + read-write + + + SAI2_CLK_SEL_0 + derive clock from PLL3 PFD2 + 0 + + + SAI2_CLK_SEL_1 + derive clock from PLL5 + 0x1 + + + SAI2_CLK_SEL_2 + derive clock from PLL4 + 0x2 + + + + + SAI3_CLK_SEL + Selector for sai3/adc1/adc2 clock multiplexer + 14 + 2 + read-write + + + SAI3_CLK_SEL_0 + derive clock from PLL3 PFD2 + 0 + + + SAI3_CLK_SEL_1 + derive clock from PLL5 + 0x1 + + + SAI3_CLK_SEL_2 + derive clock from PLL4 + 0x2 + + + + + USDHC1_CLK_SEL + Selector for usdhc1 clock multiplexer + 16 + 1 + read-write + + + USDHC1_CLK_SEL_0 + derive clock from PLL2 PFD2 + 0 + + + USDHC1_CLK_SEL_1 + derive clock from PLL2 PFD0 + 0x1 + + + + + USDHC2_CLK_SEL + Selector for usdhc2 clock multiplexer + 17 + 1 + read-write + + + USDHC2_CLK_SEL_0 + derive clock from PLL2 PFD2 + 0 + + + USDHC2_CLK_SEL_1 + derive clock from PLL2 PFD0 + 0x1 + + + + + FLEXSPI_PODF + Divider for flexspi clock root. + 23 + 3 + read-write + + + FLEXSPI_PODF_0 + divide by 1 + 0 + + + FLEXSPI_PODF_1 + divide by 2 + 0x1 + + + FLEXSPI_PODF_2 + divide by 3 + 0x2 + + + FLEXSPI_PODF_3 + divide by 4 + 0x3 + + + FLEXSPI_PODF_4 + divide by 5 + 0x4 + + + FLEXSPI_PODF_5 + divide by 6 + 0x5 + + + FLEXSPI_PODF_6 + divide by 7 + 0x6 + + + FLEXSPI_PODF_7 + divide by 8 + 0x7 + + + + + FLEXSPI_CLK_SEL + Selector for flexspi clock multiplexer + 29 + 2 + read-write + + + FLEXSPI_CLK_SEL_0 + derive clock from semc_clk_root_pre + 0 + + + FLEXSPI_CLK_SEL_1 + derive clock from pll3_sw_clk + 0x1 + + + FLEXSPI_CLK_SEL_2 + derive clock from PLL2 PFD2 + 0x2 + + + FLEXSPI_CLK_SEL_3 + derive clock from PLL3 PFD0 + 0x3 + + + + + + + CSCMR2 + CCM Serial Clock Multiplexer Register 2 + 0x20 + 32 + read-write + 0x13192F06 + 0xFFFFFFFF + + + CAN_CLK_PODF + Divider for CAN/CANFD clock podf. + 2 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + CAN_CLK_SEL + Selector for CAN/CANFD clock multiplexer + 8 + 2 + read-write + + + CAN_CLK_SEL_0 + derive clock from pll3_sw_clk divided clock (60M) + 0 + + + CAN_CLK_SEL_1 + derive clock from osc_clk (24M) + 0x1 + + + CAN_CLK_SEL_2 + derive clock from pll3_sw_clk divided clock (80M) + 0x2 + + + CAN_CLK_SEL_3 + Disable FlexCAN clock + 0x3 + + + + + FLEXIO2_CLK_SEL + Selector for flexio2/flexio3 clock multiplexer + 19 + 2 + read-write + + + FLEXIO2_CLK_SEL_0 + derive clock from PLL4 divided clock + 0 + + + FLEXIO2_CLK_SEL_1 + derive clock from PLL3 PFD2 clock + 0x1 + + + FLEXIO2_CLK_SEL_2 + derive clock from PLL5 clock + 0x2 + + + FLEXIO2_CLK_SEL_3 + derive clock from pll3_sw_clk + 0x3 + + + + + + + CSCDR1 + CCM Serial Clock Divider Register 1 + 0x24 + 32 + read-write + 0x6490B00 + 0xFFFFFFFF + + + UART_CLK_PODF + Divider for uart clock podf. + 0 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + UART_CLK_SEL + Selector for the UART clock multiplexor + 6 + 1 + read-write + + + UART_CLK_SEL_0 + derive clock from pll3_80m + 0 + + + UART_CLK_SEL_1 + derive clock from osc_clk + 0x1 + + + + + USDHC1_PODF + Divider for usdhc1 clock podf. Divider should be updated when output clock is gated. + 11 + 3 + read-write + + + USDHC1_PODF_0 + divide by 1 + 0 + + + USDHC1_PODF_1 + divide by 2 + 0x1 + + + USDHC1_PODF_2 + divide by 3 + 0x2 + + + USDHC1_PODF_3 + divide by 4 + 0x3 + + + USDHC1_PODF_4 + divide by 5 + 0x4 + + + USDHC1_PODF_5 + divide by 6 + 0x5 + + + USDHC1_PODF_6 + divide by 7 + 0x6 + + + USDHC1_PODF_7 + divide by 8 + 0x7 + + + + + USDHC2_PODF + Divider for usdhc2 clock. Divider should be updated when output clock is gated. + 16 + 3 + read-write + + + USDHC2_PODF_0 + divide by 1 + 0 + + + USDHC2_PODF_1 + divide by 2 + 0x1 + + + USDHC2_PODF_2 + divide by 3 + 0x2 + + + USDHC2_PODF_3 + divide by 4 + 0x3 + + + USDHC2_PODF_4 + divide by 5 + 0x4 + + + USDHC2_PODF_5 + divide by 6 + 0x5 + + + USDHC2_PODF_6 + divide by 7 + 0x6 + + + USDHC2_PODF_7 + divide by 8 + 0x7 + + + + + TRACE_PODF + Divider for trace clock. Divider should be updated when output clock is gated. + 25 + 2 + read-write + + + TRACE_PODF_0 + divide by 1 + 0 + + + TRACE_PODF_1 + divide by 2 + 0x1 + + + TRACE_PODF_2 + divide by 3 + 0x2 + + + TRACE_PODF_3 + divide by 4 + 0x3 + + + + + + + CS1CDR + CCM Clock Divider Register + 0x28 + 32 + read-write + 0xEC102C1 + 0xFFFFFFFF + + + SAI1_CLK_PODF + Divider for sai1 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. + 0 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + SAI1_CLK_PRED + Divider for sai1 clock pred. + 6 + 3 + read-write + + + SAI1_CLK_PRED_0 + divide by 1 + 0 + + + SAI1_CLK_PRED_1 + divide by 2 + 0x1 + + + SAI1_CLK_PRED_2 + divide by 3 + 0x2 + + + SAI1_CLK_PRED_3 + divide by 4 + 0x3 + + + SAI1_CLK_PRED_4 + divide by 5 + 0x4 + + + SAI1_CLK_PRED_5 + divide by 6 + 0x5 + + + SAI1_CLK_PRED_6 + divide by 7 + 0x6 + + + SAI1_CLK_PRED_7 + divide by 8 + 0x7 + + + + + FLEXIO2_CLK_PRED + Divider for flexio2/flexio3 clock. + 9 + 3 + read-write + + + FLEXIO2_CLK_PRED_0 + divide by 1 + 0 + + + FLEXIO2_CLK_PRED_1 + divide by 2 + 0x1 + + + FLEXIO2_CLK_PRED_2 + divide by 3 + 0x2 + + + FLEXIO2_CLK_PRED_3 + divide by 4 + 0x3 + + + FLEXIO2_CLK_PRED_4 + divide by 5 + 0x4 + + + FLEXIO2_CLK_PRED_5 + divide by 6 + 0x5 + + + FLEXIO2_CLK_PRED_6 + divide by 7 + 0x6 + + + FLEXIO2_CLK_PRED_7 + divide by 8 + 0x7 + + + + + SAI3_CLK_PODF + Divider for sai3 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. + 16 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + SAI3_CLK_PRED + Divider for sai3/adc1/adc2 clock pred. + 22 + 3 + read-write + + + SAI3_CLK_PRED_0 + divide by 1 + 0 + + + SAI3_CLK_PRED_1 + divide by 2 + 0x1 + + + SAI3_CLK_PRED_2 + divide by 3 + 0x2 + + + SAI3_CLK_PRED_3 + divide by 4 + 0x3 + + + SAI3_CLK_PRED_4 + divide by 5 + 0x4 + + + SAI3_CLK_PRED_5 + divide by 6 + 0x5 + + + SAI3_CLK_PRED_6 + divide by 7 + 0x6 + + + SAI3_CLK_PRED_7 + divide by 8 + 0x7 + + + + + FLEXIO2_CLK_PODF + Divider for flexio2/flexio3 clock. Divider should be updated when output clock is gated. + 25 + 3 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + + + + + CS2CDR + CCM Clock Divider Register + 0x2C + 32 + read-write + 0x7336C1 + 0xFFFFFFFF + + + SAI2_CLK_PODF + Divider for sai2 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. + 0 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + SAI2_CLK_PRED + Divider for sai2 clock pred.Divider should be updated when output clock is gated. + 6 + 3 + read-write + + + SAI2_CLK_PRED_0 + divide by 1 + 0 + + + SAI2_CLK_PRED_1 + divide by 2 + 0x1 + + + SAI2_CLK_PRED_2 + divide by 3 + 0x2 + + + SAI2_CLK_PRED_3 + divide by 4 + 0x3 + + + SAI2_CLK_PRED_4 + divide by 5 + 0x4 + + + SAI2_CLK_PRED_5 + divide by 6 + 0x5 + + + SAI2_CLK_PRED_6 + divide by 7 + 0x6 + + + SAI2_CLK_PRED_7 + divide by 8 + 0x7 + + + + + + + CDCDR + CCM D1 Clock Divider Register + 0x30 + 32 + read-write + 0x33F71F92 + 0xFFFFFFFF + + + FLEXIO1_CLK_SEL + Selector for flexio1 clock multiplexer + 7 + 2 + read-write + + + FLEXIO1_CLK_SEL_0 + derive clock from PLL4 + 0 + + + FLEXIO1_CLK_SEL_1 + derive clock from PLL3 PFD2 + 0x1 + + + FLEXIO1_CLK_SEL_2 + derive clock from PLL5 + 0x2 + + + FLEXIO1_CLK_SEL_3 + derive clock from pll3_sw_clk + 0x3 + + + + + FLEXIO1_CLK_PODF + Divider for flexio1 clock podf. Divider should be updated when output clock is gated. + 9 + 3 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + + + FLEXIO1_CLK_PRED + Divider for flexio1 clock pred. Divider should be updated when output clock is gated. + 12 + 3 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + + + SPDIF0_CLK_SEL + Selector for spdif0 clock multiplexer + 20 + 2 + read-write + + + SPDIF0_CLK_SEL_0 + derive clock from PLL4 + 0 + + + SPDIF0_CLK_SEL_1 + derive clock from PLL3 PFD2 + 0x1 + + + SPDIF0_CLK_SEL_2 + derive clock from PLL5 + 0x2 + + + SPDIF0_CLK_SEL_3 + derive clock from pll3_sw_clk + 0x3 + + + + + SPDIF0_CLK_PODF + Divider for spdif0 clock podf. Divider should be updated when output clock is gated. + 22 + 3 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + + + SPDIF0_CLK_PRED + Divider for spdif0 clock pred. Divider should be updated when output clock is gated. + 25 + 3 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + + + + + CSCDR2 + CCM Serial Clock Divider Register 2 + 0x38 + 32 + read-write + 0x29150 + 0xFFFFFFFF + + + LCDIF_PRED + Pre-divider for lcdif clock. Divider should be updated when output clock is gated. + 12 + 3 + read-write + + + LCDIF_PRED_0 + divide by 1 + 0 + + + LCDIF_PRED_1 + divide by 2 + 0x1 + + + LCDIF_PRED_2 + divide by 3 + 0x2 + + + LCDIF_PRED_3 + divide by 4 + 0x3 + + + LCDIF_PRED_4 + divide by 5 + 0x4 + + + LCDIF_PRED_5 + divide by 6 + 0x5 + + + LCDIF_PRED_6 + divide by 7 + 0x6 + + + LCDIF_PRED_7 + divide by 8 + 0x7 + + + + + LCDIF_PRE_CLK_SEL + Selector for lcdif root clock pre-multiplexer + 15 + 3 + read-write + + + LCDIF_PRE_CLK_SEL_0 + derive clock from PLL2 + 0 + + + LCDIF_PRE_CLK_SEL_1 + derive clock from PLL3 PFD3 + 0x1 + + + LCDIF_PRE_CLK_SEL_2 + derive clock from PLL5 + 0x2 + + + LCDIF_PRE_CLK_SEL_3 + derive clock from PLL2 PFD0 + 0x3 + + + LCDIF_PRE_CLK_SEL_4 + derive clock from PLL2 PFD1 + 0x4 + + + LCDIF_PRE_CLK_SEL_5 + derive clock from PLL3 PFD1 + 0x5 + + + + + LPI2C_CLK_SEL + Selector for the LPI2C clock multiplexor + 18 + 1 + read-write + + + LPI2C_CLK_SEL_0 + derive clock from pll3_60m + 0 + + + LPI2C_CLK_SEL_1 + derive clock from osc_clk + 0x1 + + + + + LPI2C_CLK_PODF + Divider for lpi2c clock podf. Divider should be updated when output clock is gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. + 19 + 6 + read-write + + + DIVIDE_1 + Divide by 1 + 0 + + + DIVIDE_2 + Divide by 2 + 0x1 + + + DIVIDE_3 + Divide by 3 + 0x2 + + + DIVIDE_4 + Divide by 4 + 0x3 + + + DIVIDE_5 + Divide by 5 + 0x4 + + + DIVIDE_6 + Divide by 6 + 0x5 + + + DIVIDE_7 + Divide by 7 + 0x6 + + + DIVIDE_8 + Divide by 8 + 0x7 + + + DIVIDE_9 + Divide by 9 + 0x8 + + + DIVIDE_10 + Divide by 10 + 0x9 + + + DIVIDE_11 + Divide by 11 + 0xA + + + DIVIDE_12 + Divide by 12 + 0xB + + + DIVIDE_13 + Divide by 13 + 0xC + + + DIVIDE_14 + Divide by 14 + 0xD + + + DIVIDE_15 + Divide by 15 + 0xE + + + DIVIDE_16 + Divide by 16 + 0xF + + + DIVIDE_17 + Divide by 17 + 0x10 + + + DIVIDE_18 + Divide by 18 + 0x11 + + + DIVIDE_19 + Divide by 19 + 0x12 + + + DIVIDE_20 + Divide by 20 + 0x13 + + + DIVIDE_21 + Divide by 21 + 0x14 + + + DIVIDE_22 + Divide by 22 + 0x15 + + + DIVIDE_23 + Divide by 23 + 0x16 + + + DIVIDE_24 + Divide by 24 + 0x17 + + + DIVIDE_25 + Divide by 25 + 0x18 + + + DIVIDE_26 + Divide by 26 + 0x19 + + + DIVIDE_27 + Divide by 27 + 0x1A + + + DIVIDE_28 + Divide by 28 + 0x1B + + + DIVIDE_29 + Divide by 29 + 0x1C + + + DIVIDE_30 + Divide by 30 + 0x1D + + + DIVIDE_31 + Divide by 31 + 0x1E + + + DIVIDE_32 + Divide by 32 + 0x1F + + + DIVIDE_33 + Divide by 33 + 0x20 + + + DIVIDE_34 + Divide by 34 + 0x21 + + + DIVIDE_35 + Divide by 35 + 0x22 + + + DIVIDE_36 + Divide by 36 + 0x23 + + + DIVIDE_37 + Divide by 37 + 0x24 + + + DIVIDE_38 + Divide by 38 + 0x25 + + + DIVIDE_39 + Divide by 39 + 0x26 + + + DIVIDE_40 + Divide by 40 + 0x27 + + + DIVIDE_41 + Divide by 41 + 0x28 + + + DIVIDE_42 + Divide by 42 + 0x29 + + + DIVIDE_43 + Divide by 43 + 0x2A + + + DIVIDE_44 + Divide by 44 + 0x2B + + + DIVIDE_45 + Divide by 45 + 0x2C + + + DIVIDE_46 + Divide by 46 + 0x2D + + + DIVIDE_47 + Divide by 47 + 0x2E + + + DIVIDE_48 + Divide by 48 + 0x2F + + + DIVIDE_49 + Divide by 49 + 0x30 + + + DIVIDE_50 + Divide by 50 + 0x31 + + + DIVIDE_51 + Divide by 51 + 0x32 + + + DIVIDE_52 + Divide by 52 + 0x33 + + + DIVIDE_53 + Divide by 53 + 0x34 + + + DIVIDE_54 + Divide by 54 + 0x35 + + + DIVIDE_55 + Divide by 55 + 0x36 + + + DIVIDE_56 + Divide by 56 + 0x37 + + + DIVIDE_57 + Divide by 57 + 0x38 + + + DIVIDE_58 + Divide by 58 + 0x39 + + + DIVIDE_59 + Divide by 59 + 0x3A + + + DIVIDE_60 + Divide by 60 + 0x3B + + + DIVIDE_61 + Divide by 61 + 0x3C + + + DIVIDE_62 + Divide by 62 + 0x3D + + + DIVIDE_63 + Divide by 63 + 0x3E + + + DIVIDE_64 + Divide by 64 + 0x3F + + + + + + + CSCDR3 + CCM Serial Clock Divider Register 3 + 0x3C + 32 + read-write + 0x30841 + 0xFFFFFFFF + + + CSI_CLK_SEL + Selector for csi_mclk multiplexer + 9 + 2 + read-write + + + CSI_CLK_SEL_0 + derive clock from osc_clk (24M) + 0 + + + CSI_CLK_SEL_1 + derive clock from PLL2 PFD2 + 0x1 + + + CSI_CLK_SEL_2 + derive clock from pll3_120M + 0x2 + + + CSI_CLK_SEL_3 + derive clock from PLL3 PFD1 + 0x3 + + + + + CSI_PODF + Post divider for csi_mclk. Divider should be updated when output clock is gated. + 11 + 3 + read-write + + + CSI_PODF_0 + divide by 1 + 0 + + + CSI_PODF_1 + divide by 2 + 0x1 + + + CSI_PODF_2 + divide by 3 + 0x2 + + + CSI_PODF_3 + divide by 4 + 0x3 + + + CSI_PODF_4 + divide by 5 + 0x4 + + + CSI_PODF_5 + divide by 6 + 0x5 + + + CSI_PODF_6 + divide by 7 + 0x6 + + + CSI_PODF_7 + divide by 8 + 0x7 + + + + + + + CDHIPR + CCM Divider Handshake In-Process Register + 0x48 + 32 + read-only + 0 + 0xFFFFFFFF + + + SEMC_PODF_BUSY + Busy indicator for semc_podf. + 0 + 1 + read-only + + + SEMC_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + SEMC_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the semc_podf will be applied. + 0x1 + + + + + AHB_PODF_BUSY + Busy indicator for ahb_podf. + 1 + 1 + read-only + + + AHB_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + AHB_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the ahb_podf will be applied. + 0x1 + + + + + PERIPH2_CLK_SEL_BUSY + Busy indicator for periph2_clk_sel mux control. + 3 + 1 + read-only + + + PERIPH2_CLK_SEL_BUSY_0 + mux is not busy and its value represents the actual division. + 0 + + + PERIPH2_CLK_SEL_BUSY_1 + mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the previous value of select, and after the handshake periph2_clk_sel value will be applied. + 0x1 + + + + + PERIPH_CLK_SEL_BUSY + Busy indicator for periph_clk_sel mux control. + 5 + 1 + read-only + + + PERIPH_CLK_SEL_BUSY_0 + mux is not busy and its value represents the actual division. + 0 + + + PERIPH_CLK_SEL_BUSY_1 + mux is busy with handshake process with module. The value read in the periph_clk_sel represents the previous value of select, and after the handshake periph_clk_sel value will be applied. + 0x1 + + + + + ARM_PODF_BUSY + Busy indicator for arm_podf. + 16 + 1 + read-only + + + ARM_PODF_BUSY_0 + divider is not busy and its value represents the actual division. + 0 + + + ARM_PODF_BUSY_1 + divider is busy with handshake process with module. The value read in the divider represents the previous value of the division factor, and after the handshake the written value of the arm_podf will be applied. + 0x1 + + + + + + + CLPCR + CCM Low Power Control Register + 0x54 + 32 + read-write + 0x79 + 0xFFFFFFFF + + + LPM + Setting the low power mode that system will enter on next assertion of dsm_request signal. + 0 + 2 + read-write + + + LPM_0 + Remain in run mode + 0 + + + LPM_1 + Transfer to wait mode + 0x1 + + + LPM_2 + Transfer to stop mode + 0x2 + + + + + ARM_CLK_DIS_ON_LPM + Define if ARM clocks (arm_clk, soc_mxclk, soc_pclk, soc_dbg_pclk, vl_wrck) will be disabled on wait mode + 5 + 1 + read-write + + + ARM_CLK_DIS_ON_LPM_0 + ARM clock enabled on wait mode. + 0 + + + ARM_CLK_DIS_ON_LPM_1 + ARM clock disabled on wait mode. . + 0x1 + + + + + SBYOS + Standby clock oscillator bit + 6 + 1 + read-write + + + SBYOS_0 + On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain asserted - '0' and cosc_pwrdown will remain de asserted - '0') + 0 + + + SBYOS_1 + On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will continue with the exit from the STOP mode process. + 0x1 + + + + + DIS_REF_OSC + dis_ref_osc - in run mode, software can manually control closing of external reference oscillator clock, i + 7 + 1 + read-write + + + DIS_REF_OSC_0 + external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'. + 0 + + + DIS_REF_OSC_1 + external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1' + 0x1 + + + + + VSTBY + Voltage standby request bit + 8 + 1 + read-write + + + VSTBY_0 + Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0') + 0 + + + VSTBY_1 + Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1'). + 0x1 + + + + + STBY_COUNT + Standby counter definition + 9 + 2 + read-write + + + STBY_COUNT_0 + CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles + 0 + + + STBY_COUNT_1 + CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles + 0x1 + + + STBY_COUNT_2 + CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles + 0x2 + + + STBY_COUNT_3 + CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles + 0x3 + + + + + COSC_PWRDOWN + In run mode, software can manually control powering down of on chip oscillator, i + 11 + 1 + read-write + + + COSC_PWRDOWN_0 + On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'. + 0 + + + COSC_PWRDOWN_1 + On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'. + 0x1 + + + + + BYPASS_LPM_HS1 + Bypass low power mode handshake. This bit should always be set to 1'b1 by software. + 19 + 1 + read-write + + + BYPASS_LPM_HS0 + Bypass low power mode handshake. This bit should always be set to 1'b1 by software. + 21 + 1 + read-write + + + MASK_CORE0_WFI + Mask WFI of core0 for entering low power mode Assertion of all bits[27:22] will generate low power mode request + 22 + 1 + read-write + + + MASK_CORE0_WFI_0 + WFI of core0 is not masked + 0 + + + MASK_CORE0_WFI_1 + WFI of core0 is masked + 0x1 + + + + + MASK_SCU_IDLE + Mask SCU IDLE for entering low power mode Assertion of all bits[27:22] will generate low power mode request + 26 + 1 + read-write + + + MASK_SCU_IDLE_0 + SCU IDLE is not masked + 0 + + + MASK_SCU_IDLE_1 + SCU IDLE is masked + 0x1 + + + + + MASK_L2CC_IDLE + Mask L2CC IDLE for entering low power mode + 27 + 1 + read-write + + + MASK_L2CC_IDLE_0 + L2CC IDLE is not masked + 0 + + + MASK_L2CC_IDLE_1 + L2CC IDLE is masked + 0x1 + + + + + + + CISR + CCM Interrupt Status Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + LRF_PLL + CCM interrupt request 2 generated due to lock of all enabled and not bypaseed PLLs + 0 + 1 + read-write + oneToClear + + + LRF_PLL_0 + interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs + 0 + + + LRF_PLL_1 + interrupt generated due to lock ready of all enabled and not bypaseed PLLs + 0x1 + + + + + COSC_READY + CCM interrupt request 2 generated due to on board oscillator ready, i + 6 + 1 + read-write + oneToClear + + + COSC_READY_0 + interrupt is not generated due to on board oscillator ready + 0 + + + COSC_READY_1 + interrupt generated due to on board oscillator ready + 0x1 + + + + + SEMC_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of semc_podf + 17 + 1 + read-write + oneToClear + + + SEMC_PODF_LOADED_0 + interrupt is not generated due to frequency change of semc_podf + 0 + + + SEMC_PODF_LOADED_1 + interrupt generated due to frequency change of semc_podf + 0x1 + + + + + PERIPH2_CLK_SEL_LOADED + CCM interrupt request 1 generated due to frequency change of periph2_clk_sel + 19 + 1 + read-write + oneToClear + + + PERIPH2_CLK_SEL_LOADED_0 + interrupt is not generated due to frequency change of periph2_clk_sel + 0 + + + PERIPH2_CLK_SEL_LOADED_1 + interrupt generated due to frequency change of periph2_clk_sel + 0x1 + + + + + AHB_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of ahb_podf + 20 + 1 + read-write + oneToClear + + + AHB_PODF_LOADED_0 + interrupt is not generated due to frequency change of ahb_podf + 0 + + + AHB_PODF_LOADED_1 + interrupt generated due to frequency change of ahb_podf + 0x1 + + + + + PERIPH_CLK_SEL_LOADED + CCM interrupt request 1 generated due to update of periph_clk_sel. + 22 + 1 + read-write + oneToClear + + + PERIPH_CLK_SEL_LOADED_0 + interrupt is not generated due to update of periph_clk_sel. + 0 + + + PERIPH_CLK_SEL_LOADED_1 + interrupt generated due to update of periph_clk_sel. + 0x1 + + + + + ARM_PODF_LOADED + CCM interrupt request 1 generated due to frequency change of arm_podf + 26 + 1 + read-write + oneToClear + + + ARM_PODF_LOADED_0 + interrupt is not generated due to frequency change of arm_podf + 0 + + + ARM_PODF_LOADED_1 + interrupt generated due to frequency change of arm_podf + 0x1 + + + + + + + CIMR + CCM Interrupt Mask Register + 0x5C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MASK_LRF_PLL + mask interrupt generation due to lrf of PLLs + 0 + 1 + read-write + + + MASK_LRF_PLL_0 + don't mask interrupt due to lrf of PLLs - interrupt will be created + 0 + + + MASK_LRF_PLL_1 + mask interrupt due to lrf of PLLs + 0x1 + + + + + MASK_COSC_READY + mask interrupt generation due to on board oscillator ready + 6 + 1 + read-write + + + MASK_COSC_READY_0 + don't mask interrupt due to on board oscillator ready - interrupt will be created + 0 + + + MASK_COSC_READY_1 + mask interrupt due to on board oscillator ready + 0x1 + + + + + MASK_SEMC_PODF_LOADED + mask interrupt generation due to frequency change of semc_podf + 17 + 1 + read-write + + + MASK_SEMC_PODF_LOADED_0 + don't mask interrupt due to frequency change of semc_podf - interrupt will be created + 0 + + + MASK_SEMC_PODF_LOADED_1 + mask interrupt due to frequency change of semc_podf + 0x1 + + + + + MASK_PERIPH2_CLK_SEL_LOADED + mask interrupt generation due to update of periph2_clk_sel. + 19 + 1 + read-write + + + MASK_PERIPH2_CLK_SEL_LOADED_0 + don't mask interrupt due to update of periph2_clk_sel - interrupt will be created + 0 + + + MASK_PERIPH2_CLK_SEL_LOADED_1 + mask interrupt due to update of periph2_clk_sel + 0x1 + + + + + MASK_AHB_PODF_LOADED + mask interrupt generation due to frequency change of ahb_podf + 20 + 1 + read-write + + + MASK_AHB_PODF_LOADED_0 + don't mask interrupt due to frequency change of ahb_podf - interrupt will be created + 0 + + + MASK_AHB_PODF_LOADED_1 + mask interrupt due to frequency change of ahb_podf + 0x1 + + + + + MASK_PERIPH_CLK_SEL_LOADED + mask interrupt generation due to update of periph_clk_sel. + 22 + 1 + read-write + + + MASK_PERIPH_CLK_SEL_LOADED_0 + don't mask interrupt due to update of periph_clk_sel - interrupt will be created + 0 + + + MASK_PERIPH_CLK_SEL_LOADED_1 + mask interrupt due to update of periph_clk_sel + 0x1 + + + + + ARM_PODF_LOADED + mask interrupt generation due to frequency change of arm_podf + 26 + 1 + read-write + + + ARM_PODF_LOADED_0 + don't mask interrupt due to frequency change of arm_podf - interrupt will be created + 0 + + + ARM_PODF_LOADED_1 + mask interrupt due to frequency change of arm_podf + 0x1 + + + + + + + CCOSR + CCM Clock Output Source Register + 0x60 + 32 + read-write + 0xA0001 + 0xFFFFFFFF + + + CLKO1_SEL + Selection of the clock to be generated on CCM_CLKO1 + 0 + 4 + read-write + + + CLKO1_SEL_0 + USB1 PLL clock (divided by 2) + 0 + + + CLKO1_SEL_1 + SYS PLL clock (divided by 2) + 0x1 + + + CLKO1_SEL_3 + VIDEO PLL clock (divided by 2) + 0x3 + + + CLKO1_SEL_5 + semc_clk_root + 0x5 + + + CLKO1_SEL_10 + lcdif_pix_clk_root + 0xA + + + CLKO1_SEL_11 + ahb_clk_root + 0xB + + + CLKO1_SEL_12 + ipg_clk_root + 0xC + + + CLKO1_SEL_13 + perclk_root + 0xD + + + CLKO1_SEL_14 + ckil_sync_clk_root + 0xE + + + CLKO1_SEL_15 + pll4_main_clk + 0xF + + + + + CLKO1_DIV + Setting the divider of CCM_CLKO1 + 4 + 3 + read-write + + + CLKO1_DIV_0 + divide by 1 + 0 + + + CLKO1_DIV_1 + divide by 2 + 0x1 + + + CLKO1_DIV_2 + divide by 3 + 0x2 + + + CLKO1_DIV_3 + divide by 4 + 0x3 + + + CLKO1_DIV_4 + divide by 5 + 0x4 + + + CLKO1_DIV_5 + divide by 6 + 0x5 + + + CLKO1_DIV_6 + divide by 7 + 0x6 + + + CLKO1_DIV_7 + divide by 8 + 0x7 + + + + + CLKO1_EN + Enable of CCM_CLKO1 clock + 7 + 1 + read-write + + + CLKO1_EN_0 + CCM_CLKO1 disabled. + 0 + + + CLKO1_EN_1 + CCM_CLKO1 enabled. + 0x1 + + + + + CLK_OUT_SEL + CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks + 8 + 1 + read-write + + + CLK_OUT_SEL_0 + CCM_CLKO1 output drives CCM_CLKO1 clock + 0 + + + CLK_OUT_SEL_1 + CCM_CLKO1 output drives CCM_CLKO2 clock + 0x1 + + + + + CLKO2_SEL + Selection of the clock to be generated on CCM_CLKO2 + 16 + 5 + read-write + + + CLKO2_SEL_3 + usdhc1_clk_root + 0x3 + + + CLKO2_SEL_6 + lpi2c_clk_root + 0x6 + + + CLKO2_SEL_11 + csi_clk_root + 0xB + + + CLKO2_SEL_14 + osc_clk + 0xE + + + CLKO2_SEL_17 + usdhc2_clk_root + 0x11 + + + CLKO2_SEL_18 + sai1_clk_root + 0x12 + + + CLKO2_SEL_19 + sai2_clk_root + 0x13 + + + CLKO2_SEL_20 + sai3_clk_root (shared with ADC1 and ADC2 alt_clk root) + 0x14 + + + CLKO2_SEL_23 + can_clk_root (FlexCAN, shared with CANFD) + 0x17 + + + CLKO2_SEL_27 + flexspi_clk_root + 0x1B + + + CLKO2_SEL_28 + uart_clk_root + 0x1C + + + CLKO2_SEL_29 + spdif0_clk_root + 0x1D + + + + + CLKO2_DIV + Setting the divider of CCM_CLKO2 + 21 + 3 + read-write + + + CLKO2_DIV_0 + divide by 1 + 0 + + + CLKO2_DIV_1 + divide by 2 + 0x1 + + + CLKO2_DIV_2 + divide by 3 + 0x2 + + + CLKO2_DIV_3 + divide by 4 + 0x3 + + + CLKO2_DIV_4 + divide by 5 + 0x4 + + + CLKO2_DIV_5 + divide by 6 + 0x5 + + + CLKO2_DIV_6 + divide by 7 + 0x6 + + + CLKO2_DIV_7 + divide by 8 + 0x7 + + + + + CLKO2_EN + Enable of CCM_CLKO2 clock + 24 + 1 + read-write + + + CLKO2_EN_0 + CCM_CLKO2 disabled. + 0 + + + CLKO2_EN_1 + CCM_CLKO2 enabled. + 0x1 + + + + + + + CGPR + CCM General Purpose Register + 0x64 + 32 + read-write + 0xFE62 + 0xFFFFFFFF + + + PMIC_DELAY_SCALER + Defines clock dividion of clock for stby_count (pmic delay counter) + 0 + 1 + read-write + + + PMIC_DELAY_SCALER_0 + clock is not divided + 0 + + + PMIC_DELAY_SCALER_1 + clock is divided /8 + 0x1 + + + + + EFUSE_PROG_SUPPLY_GATE + Defines the value of the output signal cgpr_dout[4]. Gate of program supply for efuse programing + 4 + 1 + read-write + + + EFUSE_PROG_SUPPLY_GATE_0 + fuse programing supply voltage is gated off to the efuse module + 0 + + + EFUSE_PROG_SUPPLY_GATE_1 + allow fuse programing. + 0x1 + + + + + SYS_MEM_DS_CTRL + System memory DS control + 14 + 2 + read-write + + + SYS_MEM_DS_CTRL_0 + Disable memory DS mode always + 0 + + + SYS_MEM_DS_CTRL_1 + Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled + 0x1 + + + SYS_MEM_DS_CTRL_2 + enable memory (outside ARM platform) DS mode when system is in STOP mode + #1x + + + + + FPL + Fast PLL enable. + 16 + 1 + read-write + + + FPL_0 + Engage PLL enable default way. + 0 + + + FPL_1 + Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode. + 0x1 + + + + + INT_MEM_CLK_LPM + Control for the Deep Sleep signal to the ARM Platform memories with additional control logic based on the ARM WFI signal + 17 + 1 + read-write + + + INT_MEM_CLK_LPM_0 + Disable the clock to the ARM platform memories when entering Low Power Mode + 0 + + + INT_MEM_CLK_LPM_1 + Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low Power Modes (WAIT and STOP without power gating) + 0x1 + + + + + + + CCGR0 + CCM Clock Gating Register 0 + 0x68 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + aips_tz1 clocks (aips_tz1_clk_enable) + 0 + 2 + read-write + + + CG1 + aips_tz2 clocks (aips_tz2_clk_enable) + 2 + 2 + read-write + + + CG2 + mqs clock ( mqs_hmclk_clock_enable) + 4 + 2 + read-write + + + CG3 + flexspi_exsc clock (flexspi_exsc_clk_enable) + 6 + 2 + read-write + + + CG4 + sim_m or sim_main register access clock (sim_m_mainclk_r_enable) + 8 + 2 + read-write + + + CG5 + dcp clock (dcp_clk_enable) + 10 + 2 + read-write + + + CG6 + lpuart3 clock (lpuart3_clk_enable) + 12 + 2 + read-write + + + CG7 + can1 clock (can1_clk_enable) + 14 + 2 + read-write + + + CG8 + can1_serial clock (can1_serial_clk_enable) + 16 + 2 + read-write + + + CG9 + can2 clock (can2_clk_enable) + 18 + 2 + read-write + + + CG10 + can2_serial clock (can2_serial_clk_enable) + 20 + 2 + read-write + + + CG11 + trace clock (trace_clk_enable) + 22 + 2 + read-write + + + CG12 + gpt2 bus clocks (gpt2_bus_clk_enable) + 24 + 2 + read-write + + + CG13 + gpt2 serial clocks (gpt2_serial_clk_enable) + 26 + 2 + read-write + + + CG14 + lpuart2 clock (lpuart2_clk_enable) + 28 + 2 + read-write + + + CG15 + gpio2_clocks (gpio2_clk_enable) + 30 + 2 + read-write + + + + + CCGR1 + CCM Clock Gating Register 1 + 0x6C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + lpspi1 clocks (lpspi1_clk_enable) + 0 + 2 + read-write + + + CG1 + lpspi2 clocks (lpspi2_clk_enable) + 2 + 2 + read-write + + + CG2 + lpspi3 clocks (lpspi3_clk_enable) + 4 + 2 + read-write + + + CG3 + lpspi4 clocks (lpspi4_clk_enable) + 6 + 2 + read-write + + + CG4 + adc2 clock (adc2_clk_enable) + 8 + 2 + read-write + + + CG5 + enet clock (enet_clk_enable) + 10 + 2 + read-write + + + CG6 + pit clocks (pit_clk_enable) + 12 + 2 + read-write + + + CG7 + aoi2 clocks (aoi2_clk_enable) + 14 + 2 + read-write + + + CG8 + adc1 clock (adc1_clk_enable) + 16 + 2 + read-write + + + CG9 + semc_exsc clock (semc_exsc_clk_enable) + 18 + 2 + read-write + + + CG10 + gpt1 bus clock (gpt_clk_enable) + 20 + 2 + read-write + + + CG11 + gpt1 serial clock (gpt_serial_clk_enable) + 22 + 2 + read-write + + + CG12 + lpuart4 clock (lpuart4_clk_enable) + 24 + 2 + read-write + + + CG13 + gpio1 clock (gpio1_clk_enable) + 26 + 2 + read-write + + + CG14 + csu clock (csu_clk_enable) + 28 + 2 + read-write + + + CG15 + Reserved + 30 + 2 + read-write + + + + + CCGR2 + CCM Clock Gating Register 2 + 0x70 + 32 + read-write + 0xFC3FFFFF + 0xFFFFFFFF + + + CG0 + ocram_exsc clock (ocram_exsc_clk_enable) + 0 + 2 + read-write + + + CG1 + csi clock (csi_clk_enable) + 2 + 2 + read-write + + + CG2 + iomuxc_snvs clock (iomuxc_snvs_clk_enable) + 4 + 2 + read-write + + + CG3 + lpi2c1 clock (lpi2c1_clk_enable) + 6 + 2 + read-write + + + CG4 + lpi2c2 clock (lpi2c2_clk_enable) + 8 + 2 + read-write + + + CG5 + lpi2c3 clock (lpi2c3_clk_enable) + 10 + 2 + read-write + + + CG6 + OCOTP_CTRL clock (iim_clk_enable) + 12 + 2 + read-write + + + CG7 + xbar3 clock (xbar3_clk_enable) + 14 + 2 + read-write + + + CG8 + ipmux1 clock (ipmux1_clk_enable) + 16 + 2 + read-write + + + CG9 + ipmux2 clock (ipmux2_clk_enable) + 18 + 2 + read-write + + + CG10 + ipmux3 clock (ipmux3_clk_enable) + 20 + 2 + read-write + + + CG11 + xbar1 clock (xbar1_clk_enable) + 22 + 2 + read-write + + + CG12 + xbar2 clock (xbar2_clk_enable) + 24 + 2 + read-write + + + CG13 + gpio3 clock (gpio3_clk_enable) + 26 + 2 + read-write + + + CG14 + lcd clocks (lcd_clk_enable) + 28 + 2 + read-write + + + CG15 + pxp clocks (pxp_clk_enable) + 30 + 2 + read-write + + + + + CCGR3 + CCM Clock Gating Register 3 + 0x74 + 32 + read-write + 0xFFFFFFCF + 0xFFFFFFFF + + + CG0 + flexio2 clocks (flexio2_clk_enable) + 0 + 2 + read-write + + + CG1 + lpuart5 clock (lpuart5_clk_enable) + 2 + 2 + read-write + + + CG2 + semc clocks (semc_clk_enable) + 4 + 2 + read-write + + + CG3 + lpuart6 clock (lpuart6_clk_enable) + 6 + 2 + read-write + + + CG4 + aoi1 clock (aoi1_clk_enable) + 8 + 2 + read-write + + + CG5 + lcdif pix clock (lcdif_pix_clk_enable) + 10 + 2 + read-write + + + CG6 + gpio4 clock (gpio4_clk_enable) + 12 + 2 + read-write + + + CG7 + ewm clocks (ewm_clk_enable) + 14 + 2 + read-write + + + CG8 + wdog1 clock (wdog1_clk_enable) + 16 + 2 + read-write + + + CG9 + flexram clock (flexram_clk_enable) + 18 + 2 + read-write + + + CG10 + acmp1 clocks (acmp1_clk_enable) + 20 + 2 + read-write + + + CG11 + acmp2 clocks (acmp2_clk_enable) + 22 + 2 + read-write + + + CG12 + acmp3 clocks (acmp3_clk_enable) + 24 + 2 + read-write + + + CG13 + acmp4 clocks (acmp4_clk_enable) + 26 + 2 + read-write + + + CG14 + The OCRAM clock cannot be turned off when the CM cache is running on this device. + 28 + 2 + read-write + + + CG15 + iomuxc_snvs_gpr clock (iomuxc_snvs_gpr_clk_enable) + 30 + 2 + read-write + + + + + CCGR4 + CCM Clock Gating Register 4 + 0x78 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + sim_m7 register access clock (sim_m7_mainclk_r_enable) + 0 + 2 + read-write + + + CG1 + iomuxc clock (iomuxc_clk_enable) + 2 + 2 + read-write + + + CG2 + iomuxc gpr clock (iomuxc_gpr_clk_enable) + 4 + 2 + read-write + + + CG3 + bee clock(bee_clk_enable) + 6 + 2 + read-write + + + CG4 + sim_m7 clock (sim_m7_clk_enable) + 8 + 2 + read-write + + + CG5 + tsc_dig clock (tsc_clk_enable) + 10 + 2 + read-write + + + CG6 + sim_m clocks (sim_m_clk_enable) + 12 + 2 + read-write + + + CG7 + sim_ems clocks (sim_ems_clk_enable) + 14 + 2 + read-write + + + CG8 + pwm1 clocks (pwm1_clk_enable) + 16 + 2 + read-write + + + CG9 + pwm2 clocks (pwm2_clk_enable) + 18 + 2 + read-write + + + CG10 + pwm3 clocks (pwm3_clk_enable) + 20 + 2 + read-write + + + CG11 + pwm4 clocks (pwm4_clk_enable) + 22 + 2 + read-write + + + CG12 + enc1 clocks (enc1_clk_enable) + 24 + 2 + read-write + + + CG13 + enc2 clocks (enc2_clk_enable) + 26 + 2 + read-write + + + CG14 + enc3 clocks (enc3_clk_enable) + 28 + 2 + read-write + + + CG15 + enc4 clocks (enc4_clk_enable) + 30 + 2 + read-write + + + + + CCGR5 + CCM Clock Gating Register 5 + 0x7C + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + rom clock (rom_clk_enable) + 0 + 2 + read-write + + + CG1 + flexio1 clock (flexio1_clk_enable) + 2 + 2 + read-write + + + CG2 + wdog3 clock (wdog3_clk_enable) + 4 + 2 + read-write + + + CG3 + dma clock (dma_clk_enable) + 6 + 2 + read-write + + + CG4 + kpp clock (kpp_clk_enable) + 8 + 2 + read-write + + + CG5 + wdog2 clock (wdog2_clk_enable) + 10 + 2 + read-write + + + CG6 + aipstz4 clocks (aips_tz4_clk_enable) + 12 + 2 + read-write + + + CG7 + spdif clock (spdif_clk_enable) + 14 + 2 + read-write + + + CG8 + sim_main clock (sim_main_clk_enable) + 16 + 2 + read-write + + + CG9 + sai1 clock (sai1_clk_enable) + 18 + 2 + read-write + + + CG10 + sai2 clock (sai2_clk_enable) + 20 + 2 + read-write + + + CG11 + sai3 clock (sai3_clk_enable) + 22 + 2 + read-write + + + CG12 + lpuart1 clock (lpuart1_clk_enable) + 24 + 2 + read-write + + + CG13 + lpuart7 clock (lpuart7_clk_enable) + 26 + 2 + read-write + + + CG14 + snvs_hp clock (snvs_hp_clk_enable) + 28 + 2 + read-write + + + CG15 + snvs_lp clock (snvs_lp_clk_enable) + 30 + 2 + read-write + + + + + CCGR6 + CCM Clock Gating Register 6 + 0x80 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + usboh3 clock (usboh3_clk_enable) + 0 + 2 + read-write + + + CG1 + usdhc1 clocks (usdhc1_clk_enable) + 2 + 2 + read-write + + + CG2 + usdhc2 clocks (usdhc2_clk_enable) + 4 + 2 + read-write + + + CG3 + dcdc clocks (dcdc_clk_enable) + 6 + 2 + read-write + + + CG4 + ipmux4 clock (ipmux4_clk_enable) + 8 + 2 + read-write + + + CG5 + flexspi clocks (flexspi_clk_enable) sim_ems_clk_enable must also be cleared, when flexspi_clk_enable is cleared + 10 + 2 + read-write + + + CG6 + trng clock (trng_clk_enable) + 12 + 2 + read-write + + + CG7 + lpuart8 clocks (lpuart8_clk_enable) + 14 + 2 + read-write + + + CG8 + timer4 clocks (timer4_clk_enable) + 16 + 2 + read-write + + + CG9 + aips_tz3 clock (aips_tz3_clk_enable) + 18 + 2 + read-write + + + CG10 + sim_axbs_p_clk_enable + 20 + 2 + read-write + + + CG11 + anadig clocks (anadig_clk_enable) + 22 + 2 + read-write + + + CG12 + lpi2c4 serial clock (lpi2c4_serial_clk_enable) + 24 + 2 + read-write + + + CG13 + timer1 clocks (timer1_clk_enable) + 26 + 2 + read-write + + + CG14 + timer2 clocks (timer2_clk_enable) + 28 + 2 + read-write + + + CG15 + timer3 clocks (timer3_clk_enable) + 30 + 2 + read-write + + + + + CCGR7 + CCM Clock Gating Register 7 + 0x84 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + CG0 + enet2_clk_enable + 0 + 2 + read-write + + + CG1 + flexspi2_clk_enable + 2 + 2 + read-write + + + CG2 + axbs_l_clk_enable + 4 + 2 + read-write + + + CG3 + can3_clk_enable + 6 + 2 + read-write + + + CG4 + can3_serial_clk_enable + 8 + 2 + read-write + + + CG5 + aips_lite_clk_enable + 10 + 2 + read-write + + + CG6 + flexio3_clk_enable + 12 + 2 + read-write + + + + + CMEOR + CCM Module Enable Overide Register + 0x88 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MOD_EN_OV_GPT + Overide clock enable signal from GPT - clock will not be gated based on GPT's signal 'ipg_enable_clk' + 5 + 1 + read-write + + + MOD_EN_OV_GPT_0 + don't override module enable signal + 0 + + + MOD_EN_OV_GPT_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_PIT + Overide clock enable signal from PIT - clock will not be gated based on PIT's signal 'ipg_enable_clk' + 6 + 1 + read-write + + + MOD_EN_OV_PIT_0 + don't override module enable signal + 0 + + + MOD_EN_OV_PIT_1 + override module enable signal + 0x1 + + + + + MOD_EN_USDHC + overide clock enable signal from USDHC. + 7 + 1 + read-write + + + MOD_EN_USDHC_0 + don't override module enable signal + 0 + + + MOD_EN_USDHC_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_TRNG + Overide clock enable signal from TRNG + 9 + 1 + read-write + + + MOD_EN_OV_TRNG_0 + don't override module enable signal + 0 + + + MOD_EN_OV_TRNG_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_CANFD_CPI + Overide clock enable signal from FlexCAN3(CANFD) - clock will not be gated based on CAN's signal 'enable_clk_cpi' + 10 + 1 + read-write + + + MOD_EN_OV_CANFD_CPI_0 + don't override module enable signal + 0 + + + MOD_EN_OV_CANFD_CPI_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_CAN2_CPI + Overide clock enable signal from CAN2 - clock will not be gated based on CAN's signal 'enable_clk_cpi' + 28 + 1 + read-write + + + MOD_EN_OV_CAN2_CPI_0 + don't override module enable signal + 0 + + + MOD_EN_OV_CAN2_CPI_1 + override module enable signal + 0x1 + + + + + MOD_EN_OV_CAN1_CPI + Overide clock enable signal from CAN1 - clock will not be gated based on CAN's signal 'enable_clk_cpi' + 30 + 1 + read-write + + + MOD_EN_OV_CAN1_CPI_0 + don't overide module enable signal + 0 + + + MOD_EN_OV_CAN1_CPI_1 + overide module enable signal + 0x1 + + + + + + + + + ROMC + ROMC + ROMC + ROMC_ + 0x40180000 + + 0 + 0x20C + registers + + + + 8 + 0x4 + 7,6,5,4,3,2,1,0 + ROMPATCH%sD + ROMC Data Registers + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATAX + Data Fix Registers - Stores the data used for 1-word data fix operations + 0 + 32 + read-write + + + + + ROMPATCHCNTL + ROMC Control Register + 0xF4 + 32 + read-write + 0x8400000 + 0xFFFFFFFF + + + DATAFIX + Data Fix Enable - Controls the use of the first 8 address comparators for 1-word data fix or for code patch routine + 0 + 8 + read-write + + + DATAFIX_0 + Address comparator triggers a opcode patch + 0 + + + DATAFIX_1 + Address comparator triggers a data fix + 0x1 + + + + + DIS + ROMC Disable -- This bit, when set, disables all ROMC operations + 29 + 1 + read-write + + + DIS_0 + Does not affect any ROMC functions (default) + 0 + + + DIS_1 + Disable all ROMC functions: data fixing, and opcode patching + 0x1 + + + + + + + ROMPATCHENH + ROMC Enable Register High + 0xF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + ROMPATCHENL + ROMC Enable Register Low + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Enable Address Comparator - This bit enables the corresponding address comparator to trigger an event + 0 + 16 + read-write + + + ENABLE_0 + Address comparator disabled + 0 + + + ENABLE_1 + Address comparator enabled, ROMC will trigger a opcode patch or data fix event upon matching of the associated address + 0x1 + + + + + + + 16 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 + ROMPATCH%sA + ROMC Address Registers + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + THUMBX + THUMB Comparator Select - Indicates that this address will trigger a THUMB opcode patch or an Arm opcode patch + 0 + 1 + read-write + + + THUMBX_0 + Arm patch + 0 + + + THUMBX_1 + THUMB patch (ignore if data fix) + 0x1 + + + + + ADDRX + Address Comparator Registers - Indicates the memory address to be watched + 1 + 22 + read-write + + + + + ROMPATCHSR + ROMC Status Register + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + SOURCE + ROMC Source Number - Binary encoding of the number of the address comparator which has an address match in the most recent patch event on ROMC AHB + 0 + 6 + read-only + + + SOURCE_0 + Address Comparator 0 matched + 0 + + + SOURCE_1 + Address Comparator 1 matched + 0x1 + + + SOURCE_15 + Address Comparator 15 matched + 0xF + + + + + SW + ROMC AHB Multiple Address Comparator matches Indicator - Indicates that multiple address comparator matches occurred + 17 + 1 + read-write + oneToClear + + + SW_0 + no event or comparator collisions + 0 + + + SW_1 + a collision has occurred + 0x1 + + + + + + + + + LPUART1 + LPUART + LPUART + LPUART + 0x40184000 + + 0 + 0x30 + registers + + + LPUART1 + 20 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x4010003 + 0xFFFFFFFF + + + FEATURE + Feature Identification Number + 0 + 16 + read-only + + + FEATURE_1 + Standard feature set. + 0x1 + + + FEATURE_3 + Standard feature set with MODEM/IrDA support. + 0x3 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x202 + 0xFFFFFFFF + + + TXFIFO + Transmit FIFO Size + 0 + 8 + read-only + + + RXFIFO + Receive FIFO Size + 8 + 8 + read-only + + + + + GLOBAL + LPUART Global Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RST + Software Reset + 1 + 1 + read-write + + + RST_0 + Module is not reset. + 0 + + + RST_1 + Module is reset. + 0x1 + + + + + + + PINCFG + LPUART Pin Configuration Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TRGSEL + Trigger Select + 0 + 2 + read-write + + + TRGSEL_0 + Input trigger is disabled. + 0 + + + TRGSEL_1 + Input trigger is used instead of RXD pin input. + 0x1 + + + TRGSEL_2 + Input trigger is used instead of CTS_B pin input. + 0x2 + + + TRGSEL_3 + Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. + 0x3 + + + + + + + BAUD + LPUART Baud Rate Register + 0x10 + 32 + read-write + 0xF000004 + 0xFFFFFFFF + + + SBR + Baud Rate Modulo Divisor. + 0 + 13 + read-write + + + SBNS + Stop Bit Number Select + 13 + 1 + read-write + + + SBNS_0 + One stop bit. + 0 + + + SBNS_1 + Two stop bits. + 0x1 + + + + + RXEDGIE + RX Input Active Edge Interrupt Enable + 14 + 1 + read-write + + + RXEDGIE_0 + Hardware interrupts from STAT[RXEDGIF] are disabled. + 0 + + + RXEDGIE_1 + Hardware interrupt is requested when STAT[RXEDGIF] flag is 1. + 0x1 + + + + + LBKDIE + LIN Break Detect Interrupt Enable + 15 + 1 + read-write + + + LBKDIE_0 + Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). + 0 + + + LBKDIE_1 + Hardware interrupt requested when STAT[LBKDIF] flag is 1. + 0x1 + + + + + RESYNCDIS + Resynchronization Disable + 16 + 1 + read-write + + + RESYNCDIS_0 + Resynchronization during received data word is supported + 0 + + + RESYNCDIS_1 + Resynchronization during received data word is disabled + 0x1 + + + + + BOTHEDGE + Both Edge Sampling + 17 + 1 + read-write + + + BOTHEDGE_0 + Receiver samples input data using the rising edge of the baud rate clock. + 0 + + + BOTHEDGE_1 + Receiver samples input data using the rising and falling edge of the baud rate clock. + 0x1 + + + + + MATCFG + Match Configuration + 18 + 2 + read-write + + + MATCFG_0 + Address Match Wakeup + 0 + + + MATCFG_1 + Idle Match Wakeup + 0x1 + + + MATCFG_2 + Match On and Match Off + 0x2 + + + MATCFG_3 + Enables RWU on Data Match and Match On/Off for transmitter CTS input + 0x3 + + + + + RIDMAE + Receiver Idle DMA Enable + 20 + 1 + read-write + + + RIDMAE_0 + DMA request disabled. + 0 + + + RIDMAE_1 + DMA request enabled. + 0x1 + + + + + RDMAE + Receiver Full DMA Enable + 21 + 1 + read-write + + + RDMAE_0 + DMA request disabled. + 0 + + + RDMAE_1 + DMA request enabled. + 0x1 + + + + + TDMAE + Transmitter DMA Enable + 23 + 1 + read-write + + + TDMAE_0 + DMA request disabled. + 0 + + + TDMAE_1 + DMA request enabled. + 0x1 + + + + + OSR + Oversampling Ratio + 24 + 5 + read-write + + + OSR_0 + Writing 0 to this field will result in an oversampling ratio of 16 + 0 + + + OSR_3 + Oversampling ratio of 4, requires BOTHEDGE to be set. + 0x3 + + + OSR_4 + Oversampling ratio of 5, requires BOTHEDGE to be set. + 0x4 + + + OSR_5 + Oversampling ratio of 6, requires BOTHEDGE to be set. + 0x5 + + + OSR_6 + Oversampling ratio of 7, requires BOTHEDGE to be set. + 0x6 + + + OSR_7 + Oversampling ratio of 8. + 0x7 + + + OSR_8 + Oversampling ratio of 9. + 0x8 + + + OSR_9 + Oversampling ratio of 10. + 0x9 + + + OSR_10 + Oversampling ratio of 11. + 0xA + + + OSR_11 + Oversampling ratio of 12. + 0xB + + + OSR_12 + Oversampling ratio of 13. + 0xC + + + OSR_13 + Oversampling ratio of 14. + 0xD + + + OSR_14 + Oversampling ratio of 15. + 0xE + + + OSR_15 + Oversampling ratio of 16. + 0xF + + + OSR_16 + Oversampling ratio of 17. + 0x10 + + + OSR_17 + Oversampling ratio of 18. + 0x11 + + + OSR_18 + Oversampling ratio of 19. + 0x12 + + + OSR_19 + Oversampling ratio of 20. + 0x13 + + + OSR_20 + Oversampling ratio of 21. + 0x14 + + + OSR_21 + Oversampling ratio of 22. + 0x15 + + + OSR_22 + Oversampling ratio of 23. + 0x16 + + + OSR_23 + Oversampling ratio of 24. + 0x17 + + + OSR_24 + Oversampling ratio of 25. + 0x18 + + + OSR_25 + Oversampling ratio of 26. + 0x19 + + + OSR_26 + Oversampling ratio of 27. + 0x1A + + + OSR_27 + Oversampling ratio of 28. + 0x1B + + + OSR_28 + Oversampling ratio of 29. + 0x1C + + + OSR_29 + Oversampling ratio of 30. + 0x1D + + + OSR_30 + Oversampling ratio of 31. + 0x1E + + + OSR_31 + Oversampling ratio of 32. + 0x1F + + + + + M10 + 10-bit Mode select + 29 + 1 + read-write + + + M10_0 + Receiver and transmitter use 7-bit to 9-bit data characters. + 0 + + + M10_1 + Receiver and transmitter use 10-bit data characters. + 0x1 + + + + + MAEN2 + Match Address Mode Enable 2 + 30 + 1 + read-write + + + MAEN2_0 + Normal operation. + 0 + + + MAEN2_1 + Enables automatic address matching or data matching mode for MATCH[MA2]. + 0x1 + + + + + MAEN1 + Match Address Mode Enable 1 + 31 + 1 + read-write + + + MAEN1_0 + Normal operation. + 0 + + + MAEN1_1 + Enables automatic address matching or data matching mode for MATCH[MA1]. + 0x1 + + + + + + + STAT + LPUART Status Register + 0x14 + 32 + read-write + 0xC00000 + 0xFFFFFFFF + + + MA2F + Match 2 Flag + 14 + 1 + read-write + oneToClear + + + MA2F_0 + Received data is not equal to MA2 + 0 + + + MA2F_1 + Received data is equal to MA2 + 0x1 + + + + + MA1F + Match 1 Flag + 15 + 1 + read-write + oneToClear + + + MA1F_0 + Received data is not equal to MA1 + 0 + + + MA1F_1 + Received data is equal to MA1 + 0x1 + + + + + PF + Parity Error Flag + 16 + 1 + read-write + oneToClear + + + PF_0 + No parity error. + 0 + + + PF_1 + Parity error. + 0x1 + + + + + FE + Framing Error Flag + 17 + 1 + read-write + oneToClear + + + FE_0 + No framing error detected. This does not guarantee the framing is correct. + 0 + + + FE_1 + Framing error. + 0x1 + + + + + NF + Noise Flag + 18 + 1 + read-write + oneToClear + + + NF_0 + No noise detected. + 0 + + + NF_1 + Noise detected in the received character in the DATA register. + 0x1 + + + + + OR + Receiver Overrun Flag + 19 + 1 + read-write + oneToClear + + + OR_0 + No overrun. + 0 + + + OR_1 + Receive overrun (new LPUART data lost). + 0x1 + + + + + IDLE + Idle Line Flag + 20 + 1 + read-write + oneToClear + + + IDLE_0 + No idle line detected. + 0 + + + IDLE_1 + Idle line was detected. + 0x1 + + + + + RDRF + Receive Data Register Full Flag + 21 + 1 + read-only + + + RDRF_0 + Receive data buffer empty. + 0 + + + RDRF_1 + Receive data buffer full. + 0x1 + + + + + TC + Transmission Complete Flag + 22 + 1 + read-only + + + TC_0 + Transmitter active (sending data, a preamble, or a break). + 0 + + + TC_1 + Transmitter idle (transmission activity complete). + 0x1 + + + + + TDRE + Transmit Data Register Empty Flag + 23 + 1 + read-only + + + TDRE_0 + Transmit data buffer full. + 0 + + + TDRE_1 + Transmit data buffer empty. + 0x1 + + + + + RAF + Receiver Active Flag + 24 + 1 + read-only + + + RAF_0 + LPUART receiver idle waiting for a start bit. + 0 + + + RAF_1 + LPUART receiver active (RXD input not idle). + 0x1 + + + + + LBKDE + LIN Break Detection Enable + 25 + 1 + read-write + + + LBKDE_0 + LIN break detect is disabled, normal break character can be detected. + 0 + + + LBKDE_1 + LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). + 0x1 + + + + + BRK13 + Break Character Generation Length + 26 + 1 + read-write + + + BRK13_0 + Break character is transmitted with length of 9 to 13 bit times. + 0 + + + BRK13_1 + Break character is transmitted with length of 12 to 15 bit times. + 0x1 + + + + + RWUID + Receive Wake Up Idle Detect + 27 + 1 + read-write + + + RWUID_0 + During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. + 0 + + + RWUID_1 + During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match. + 0x1 + + + + + RXINV + Receive Data Inversion + 28 + 1 + read-write + + + RXINV_0 + Receive data not inverted. + 0 + + + RXINV_1 + Receive data inverted. + 0x1 + + + + + MSBF + MSB First + 29 + 1 + read-write + + + MSBF_0 + LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. + 0 + + + MSBF_1 + MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. + 0x1 + + + + + RXEDGIF + RXD Pin Active Edge Interrupt Flag + 30 + 1 + read-write + oneToClear + + + RXEDGIF_0 + No active edge on the receive pin has occurred. + 0 + + + RXEDGIF_1 + An active edge on the receive pin has occurred. + 0x1 + + + + + LBKDIF + LIN Break Detect Interrupt Flag + 31 + 1 + read-write + oneToClear + + + LBKDIF_0 + No LIN break character has been detected. + 0 + + + LBKDIF_1 + LIN break character has been detected. + 0x1 + + + + + + + CTRL + LPUART Control Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + PT + Parity Type + 0 + 1 + read-write + + + PT_0 + Even parity. + 0 + + + PT_1 + Odd parity. + 0x1 + + + + + PE + Parity Enable + 1 + 1 + read-write + + + PE_0 + No hardware parity generation or checking. + 0 + + + PE_1 + Parity enabled. + 0x1 + + + + + ILT + Idle Line Type Select + 2 + 1 + read-write + + + ILT_0 + Idle character bit count starts after start bit. + 0 + + + ILT_1 + Idle character bit count starts after stop bit. + 0x1 + + + + + WAKE + Receiver Wakeup Method Select + 3 + 1 + read-write + + + WAKE_0 + Configures RWU for idle-line wakeup. + 0 + + + WAKE_1 + Configures RWU with address-mark wakeup. + 0x1 + + + + + M + 9-Bit or 8-Bit Mode Select + 4 + 1 + read-write + + + M_0 + Receiver and transmitter use 8-bit data characters. + 0 + + + M_1 + Receiver and transmitter use 9-bit data characters. + 0x1 + + + + + RSRC + Receiver Source Select + 5 + 1 + read-write + + + RSRC_0 + Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. + 0 + + + RSRC_1 + Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. + 0x1 + + + + + DOZEEN + Doze Enable + 6 + 1 + read-write + + + DOZEEN_0 + LPUART is enabled in Doze mode. + 0 + + + DOZEEN_1 + LPUART is disabled in Doze mode. + 0x1 + + + + + LOOPS + Loop Mode Select + 7 + 1 + read-write + + + LOOPS_0 + Normal operation - RXD and TXD use separate pins. + 0 + + + LOOPS_1 + Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). + 0x1 + + + + + IDLECFG + Idle Configuration + 8 + 3 + read-write + + + IDLECFG_0 + 1 idle character + 0 + + + IDLECFG_1 + 2 idle characters + 0x1 + + + IDLECFG_2 + 4 idle characters + 0x2 + + + IDLECFG_3 + 8 idle characters + 0x3 + + + IDLECFG_4 + 16 idle characters + 0x4 + + + IDLECFG_5 + 32 idle characters + 0x5 + + + IDLECFG_6 + 64 idle characters + 0x6 + + + IDLECFG_7 + 128 idle characters + 0x7 + + + + + M7 + 7-Bit Mode Select + 11 + 1 + read-write + + + M7_0 + Receiver and transmitter use 8-bit to 10-bit data characters. + 0 + + + M7_1 + Receiver and transmitter use 7-bit data characters. + 0x1 + + + + + MA2IE + Match 2 Interrupt Enable + 14 + 1 + read-write + + + MA2IE_0 + MA2F interrupt disabled + 0 + + + MA2IE_1 + MA2F interrupt enabled + 0x1 + + + + + MA1IE + Match 1 Interrupt Enable + 15 + 1 + read-write + + + MA1IE_0 + MA1F interrupt disabled + 0 + + + MA1IE_1 + MA1F interrupt enabled + 0x1 + + + + + SBK + Send Break + 16 + 1 + read-write + + + SBK_0 + Normal transmitter operation. + 0 + + + SBK_1 + Queue break character(s) to be sent. + 0x1 + + + + + RWU + Receiver Wakeup Control + 17 + 1 + read-write + + + RWU_0 + Normal receiver operation. + 0 + + + RWU_1 + LPUART receiver in standby waiting for wakeup condition. + 0x1 + + + + + RE + Receiver Enable + 18 + 1 + read-write + + + RE_0 + Receiver disabled. + 0 + + + RE_1 + Receiver enabled. + 0x1 + + + + + TE + Transmitter Enable + 19 + 1 + read-write + + + TE_0 + Transmitter disabled. + 0 + + + TE_1 + Transmitter enabled. + 0x1 + + + + + ILIE + Idle Line Interrupt Enable + 20 + 1 + read-write + + + ILIE_0 + Hardware interrupts from IDLE disabled; use polling. + 0 + + + ILIE_1 + Hardware interrupt requested when IDLE flag is 1. + 0x1 + + + + + RIE + Receiver Interrupt Enable + 21 + 1 + read-write + + + RIE_0 + Hardware interrupts from RDRF disabled; use polling. + 0 + + + RIE_1 + Hardware interrupt requested when RDRF flag is 1. + 0x1 + + + + + TCIE + Transmission Complete Interrupt Enable for + 22 + 1 + read-write + + + TCIE_0 + Hardware interrupts from TC disabled; use polling. + 0 + + + TCIE_1 + Hardware interrupt requested when TC flag is 1. + 0x1 + + + + + TIE + Transmit Interrupt Enable + 23 + 1 + read-write + + + TIE_0 + Hardware interrupts from TDRE disabled; use polling. + 0 + + + TIE_1 + Hardware interrupt requested when TDRE flag is 1. + 0x1 + + + + + PEIE + Parity Error Interrupt Enable + 24 + 1 + read-write + + + PEIE_0 + PF interrupts disabled; use polling). + 0 + + + PEIE_1 + Hardware interrupt requested when PF is set. + 0x1 + + + + + FEIE + Framing Error Interrupt Enable + 25 + 1 + read-write + + + FEIE_0 + FE interrupts disabled; use polling. + 0 + + + FEIE_1 + Hardware interrupt requested when FE is set. + 0x1 + + + + + NEIE + Noise Error Interrupt Enable + 26 + 1 + read-write + + + NEIE_0 + NF interrupts disabled; use polling. + 0 + + + NEIE_1 + Hardware interrupt requested when NF is set. + 0x1 + + + + + ORIE + Overrun Interrupt Enable + 27 + 1 + read-write + + + ORIE_0 + OR interrupts disabled; use polling. + 0 + + + ORIE_1 + Hardware interrupt requested when OR is set. + 0x1 + + + + + TXINV + Transmit Data Inversion + 28 + 1 + read-write + + + TXINV_0 + Transmit data not inverted. + 0 + + + TXINV_1 + Transmit data inverted. + 0x1 + + + + + TXDIR + TXD Pin Direction in Single-Wire Mode + 29 + 1 + read-write + + + TXDIR_0 + TXD pin is an input in single-wire mode. + 0 + + + TXDIR_1 + TXD pin is an output in single-wire mode. + 0x1 + + + + + R9T8 + Receive Bit 9 / Transmit Bit 8 + 30 + 1 + read-write + + + R8T9 + Receive Bit 8 / Transmit Bit 9 + 31 + 1 + read-write + + + + + DATA + LPUART Data Register + 0x1C + 32 + read-write + 0x1000 + 0xFFFFFFFF + + + R0T0 + R0T0 + 0 + 1 + read-write + + + R1T1 + R1T1 + 1 + 1 + read-write + + + R2T2 + R2T2 + 2 + 1 + read-write + + + R3T3 + R3T3 + 3 + 1 + read-write + + + R4T4 + R4T4 + 4 + 1 + read-write + + + R5T5 + R5T5 + 5 + 1 + read-write + + + R6T6 + R6T6 + 6 + 1 + read-write + + + R7T7 + R7T7 + 7 + 1 + read-write + + + R8T8 + R8T8 + 8 + 1 + read-write + + + R9T9 + R9T9 + 9 + 1 + read-write + + + IDLINE + Idle Line + 11 + 1 + read-only + + + IDLINE_0 + Receiver was not idle before receiving this character. + 0 + + + IDLINE_1 + Receiver was idle before receiving this character. + 0x1 + + + + + RXEMPT + Receive Buffer Empty + 12 + 1 + read-only + + + RXEMPT_0 + Receive buffer contains valid data. + 0 + + + RXEMPT_1 + Receive buffer is empty, data returned on read is not valid. + 0x1 + + + + + FRETSC + Frame Error / Transmit Special Character + 13 + 1 + read-write + + + FRETSC_0 + The dataword was received without a frame error on read, or transmit a normal character on write. + 0 + + + FRETSC_1 + The dataword was received with a frame error, or transmit an idle or break character on transmit. + 0x1 + + + + + PARITYE + PARITYE + 14 + 1 + read-only + + + PARITYE_0 + The dataword was received without a parity error. + 0 + + + PARITYE_1 + The dataword was received with a parity error. + 0x1 + + + + + NOISY + NOISY + 15 + 1 + read-only + + + NOISY_0 + The dataword was received without noise. + 0 + + + NOISY_1 + The data was received with noise. + 0x1 + + + + + + + MATCH + LPUART Match Address Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + MA1 + Match Address 1 + 0 + 10 + read-write + + + MA2 + Match Address 2 + 16 + 10 + read-write + + + + + MODIR + LPUART Modem IrDA Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXCTSE + Transmitter clear-to-send enable + 0 + 1 + read-write + + + TXCTSE_0 + CTS has no effect on the transmitter. + 0 + + + TXCTSE_1 + Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. + 0x1 + + + + + TXRTSE + Transmitter request-to-send enable + 1 + 1 + read-write + + + TXRTSE_0 + The transmitter has no effect on RTS. + 0 + + + TXRTSE_1 + When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. + 0x1 + + + + + TXRTSPOL + Transmitter request-to-send polarity + 2 + 1 + read-write + + + TXRTSPOL_0 + Transmitter RTS is active low. + 0 + + + TXRTSPOL_1 + Transmitter RTS is active high. + 0x1 + + + + + RXRTSE + Receiver request-to-send enable + 3 + 1 + read-write + + + RXRTSE_0 + The receiver has no effect on RTS. + 0 + + + RXRTSE_1 + RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full. + 0x1 + + + + + TXCTSC + Transmit CTS Configuration + 4 + 1 + read-write + + + TXCTSC_0 + CTS input is sampled at the start of each character. + 0 + + + TXCTSC_1 + CTS input is sampled when the transmitter is idle. + 0x1 + + + + + TXCTSSRC + Transmit CTS Source + 5 + 1 + read-write + + + TXCTSSRC_0 + CTS input is the CTS_B pin. + 0 + + + TXCTSSRC_1 + CTS input is the inverted Receiver Match result. + 0x1 + + + + + RTSWATER + Receive RTS Configuration + 8 + 2 + read-write + + + TNP + Transmitter narrow pulse + 16 + 2 + read-write + + + TNP_0 + 1/OSR. + 0 + + + TNP_1 + 2/OSR. + 0x1 + + + TNP_2 + 3/OSR. + 0x2 + + + TNP_3 + 4/OSR. + 0x3 + + + + + IREN + Infrared enable + 18 + 1 + read-write + + + IREN_0 + IR disabled. + 0 + + + IREN_1 + IR enabled. + 0x1 + + + + + + + FIFO + LPUART FIFO Register + 0x28 + 32 + read-write + 0xC00011 + 0xFFFFFFFF + + + RXFIFOSIZE + Receive FIFO Buffer Depth + 0 + 3 + read-only + + + RXFIFOSIZE_0 + Receive FIFO/Buffer depth = 1 dataword. + 0 + + + RXFIFOSIZE_1 + Receive FIFO/Buffer depth = 4 datawords. + 0x1 + + + RXFIFOSIZE_2 + Receive FIFO/Buffer depth = 8 datawords. + 0x2 + + + RXFIFOSIZE_3 + Receive FIFO/Buffer depth = 16 datawords. + 0x3 + + + RXFIFOSIZE_4 + Receive FIFO/Buffer depth = 32 datawords. + 0x4 + + + RXFIFOSIZE_5 + Receive FIFO/Buffer depth = 64 datawords. + 0x5 + + + RXFIFOSIZE_6 + Receive FIFO/Buffer depth = 128 datawords. + 0x6 + + + RXFIFOSIZE_7 + Receive FIFO/Buffer depth = 256 datawords. + 0x7 + + + + + RXFE + Receive FIFO Enable + 3 + 1 + read-write + + + RXFE_0 + Receive FIFO is not enabled. Buffer is depth 1. + 0 + + + RXFE_1 + Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. + 0x1 + + + + + TXFIFOSIZE + Transmit FIFO Buffer Depth + 4 + 3 + read-only + + + TXFIFOSIZE_0 + Transmit FIFO/Buffer depth = 1 dataword. + 0 + + + TXFIFOSIZE_1 + Transmit FIFO/Buffer depth = 4 datawords. + 0x1 + + + TXFIFOSIZE_2 + Transmit FIFO/Buffer depth = 8 datawords. + 0x2 + + + TXFIFOSIZE_3 + Transmit FIFO/Buffer depth = 16 datawords. + 0x3 + + + TXFIFOSIZE_4 + Transmit FIFO/Buffer depth = 32 datawords. + 0x4 + + + TXFIFOSIZE_5 + Transmit FIFO/Buffer depth = 64 datawords. + 0x5 + + + TXFIFOSIZE_6 + Transmit FIFO/Buffer depth = 128 datawords. + 0x6 + + + TXFIFOSIZE_7 + Transmit FIFO/Buffer depth = 256 datawords + 0x7 + + + + + TXFE + Transmit FIFO Enable + 7 + 1 + read-write + + + TXFE_0 + Transmit FIFO is not enabled. Buffer is depth 1. + 0 + + + TXFE_1 + Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. + 0x1 + + + + + RXUFE + Receive FIFO Underflow Interrupt Enable + 8 + 1 + read-write + + + RXUFE_0 + RXUF flag does not generate an interrupt to the host. + 0 + + + RXUFE_1 + RXUF flag generates an interrupt to the host. + 0x1 + + + + + TXOFE + Transmit FIFO Overflow Interrupt Enable + 9 + 1 + read-write + + + TXOFE_0 + TXOF flag does not generate an interrupt to the host. + 0 + + + TXOFE_1 + TXOF flag generates an interrupt to the host. + 0x1 + + + + + RXIDEN + Receiver Idle Empty Enable + 10 + 3 + read-write + + + RXIDEN_0 + Disable RDRF assertion due to partially filled FIFO when receiver is idle. + 0 + + + RXIDEN_1 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. + 0x1 + + + RXIDEN_2 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. + 0x2 + + + RXIDEN_3 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. + 0x3 + + + RXIDEN_4 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. + 0x4 + + + RXIDEN_5 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. + 0x5 + + + RXIDEN_6 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. + 0x6 + + + RXIDEN_7 + Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. + 0x7 + + + + + RXFLUSH + Receive FIFO/Buffer Flush + 14 + 1 + read-write + + + RXFLUSH_0 + No flush operation occurs. + 0 + + + RXFLUSH_1 + All data in the receive FIFO/buffer is cleared out. + 0x1 + + + + + TXFLUSH + Transmit FIFO/Buffer Flush + 15 + 1 + read-write + + + TXFLUSH_0 + No flush operation occurs. + 0 + + + TXFLUSH_1 + All data in the transmit FIFO/Buffer is cleared out. + 0x1 + + + + + RXUF + Receiver Buffer Underflow Flag + 16 + 1 + read-write + oneToClear + + + RXUF_0 + No receive buffer underflow has occurred since the last time the flag was cleared. + 0 + + + RXUF_1 + At least one receive buffer underflow has occurred since the last time the flag was cleared. + 0x1 + + + + + TXOF + Transmitter Buffer Overflow Flag + 17 + 1 + read-write + oneToClear + + + TXOF_0 + No transmit buffer overflow has occurred since the last time the flag was cleared. + 0 + + + TXOF_1 + At least one transmit buffer overflow has occurred since the last time the flag was cleared. + 0x1 + + + + + RXEMPT + Receive Buffer/FIFO Empty + 22 + 1 + read-only + + + RXEMPT_0 + Receive buffer is not empty. + 0 + + + RXEMPT_1 + Receive buffer is empty. + 0x1 + + + + + TXEMPT + Transmit Buffer/FIFO Empty + 23 + 1 + read-only + + + TXEMPT_0 + Transmit buffer is not empty. + 0 + + + TXEMPT_1 + Transmit buffer is empty. + 0x1 + + + + + + + WATER + LPUART Watermark Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + TXWATER + Transmit Watermark + 0 + 2 + read-write + + + TXCOUNT + Transmit Counter + 8 + 3 + read-only + + + RXWATER + Receive Watermark + 16 + 2 + read-write + + + RXCOUNT + Receive Counter + 24 + 3 + read-only + + + + + + + LPUART2 + LPUART + LPUART + 0x40188000 + + 0 + 0x30 + registers + + + LPUART2 + 21 + + + + LPUART3 + LPUART + LPUART + 0x4018C000 + + 0 + 0x30 + registers + + + LPUART3 + 22 + + + + LPUART4 + LPUART + LPUART + 0x40190000 + + 0 + 0x30 + registers + + + LPUART4 + 23 + + + + LPUART5 + LPUART + LPUART + 0x40194000 + + 0 + 0x30 + registers + + + LPUART5 + 24 + + + + LPUART6 + LPUART + LPUART + 0x40198000 + + 0 + 0x30 + registers + + + LPUART6 + 25 + + + + LPUART7 + LPUART + LPUART + 0x4019C000 + + 0 + 0x30 + registers + + + LPUART7 + 26 + + + + LPUART8 + LPUART + LPUART + 0x401A0000 + + 0 + 0x30 + registers + + + LPUART8 + 27 + + + + FLEXIO1 + FLEXIO + FLEXIO + FLEXIO + 0x401AC000 + + 0 + 0x790 + registers + + + FLEXIO1 + 90 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x1010001 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + FEATURE_0 + Standard features implemented. + 0 + + + FEATURE_1 + Supports state, logic and parallel modes. + 0x1 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x2100404 + 0xFFFFFFFF + + + SHIFTER + Shifter Number + 0 + 8 + read-only + + + TIMER + Timer Number + 8 + 8 + read-only + + + PIN + Pin Number + 16 + 8 + read-only + + + TRIGGER + Trigger Number + 24 + 8 + read-only + + + + + CTRL + FlexIO Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FLEXEN + FlexIO Enable + 0 + 1 + read-write + + + FLEXEN_0 + FlexIO module is disabled. + 0 + + + FLEXEN_1 + FlexIO module is enabled. + 0x1 + + + + + SWRST + Software Reset + 1 + 1 + read-write + + + SWRST_0 + Software reset is disabled + 0 + + + SWRST_1 + Software reset is enabled, all FlexIO registers except the Control Register are reset. + 0x1 + + + + + FASTACC + Fast Access + 2 + 1 + read-write + + + FASTACC_0 + Configures for normal register accesses to FlexIO + 0 + + + FASTACC_1 + Configures for fast register accesses to FlexIO + 0x1 + + + + + DBGE + Debug Enable + 30 + 1 + read-write + + + DBGE_0 + FlexIO is disabled in debug modes. + 0 + + + DBGE_1 + FlexIO is enabled in debug modes + 0x1 + + + + + DOZEN + Doze Enable + 31 + 1 + read-write + + + DOZEN_0 + FlexIO enabled in Doze modes. + 0 + + + DOZEN_1 + FlexIO disabled in Doze modes. + 0x1 + + + + + + + PIN + Pin State Register + 0xC + 32 + read-only + 0 + 0xFFFFFFFF + + + PDI + Pin Data Input + 0 + 16 + read-only + + + + + SHIFTSTAT + Shifter Status Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSF + Shifter Status Flag + 0 + 4 + read-write + oneToClear + + + + + SHIFTERR + Shifter Error Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEF + Shifter Error Flags + 0 + 4 + read-write + oneToClear + + + + + TIMSTAT + Timer Status Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSF + Timer Status Flags + 0 + 4 + read-write + oneToClear + + + + + SHIFTSIEN + Shifter Status Interrupt Enable + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSIE + Shifter Status Interrupt Enable + 0 + 4 + read-write + + + + + SHIFTEIEN + Shifter Error Interrupt Enable + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEIE + Shifter Error Interrupt Enable + 0 + 4 + read-write + + + + + TIMIEN + Timer Interrupt Enable Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + TEIE + Timer Status Interrupt Enable + 0 + 4 + read-write + + + + + SHIFTSDEN + Shifter Status DMA Enable + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSDE + Shifter Status DMA Enable + 0 + 4 + read-write + + + + + SHIFTSTATE + Shifter State Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + STATE + Current State Pointer + 0 + 3 + read-write + + + + + 4 + 0x4 + SHIFTCTL[%s] + Shifter Control N Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + SMOD + Shifter Mode + 0 + 3 + read-write + + + SMOD_0 + Disabled. + 0 + + + SMOD_1 + Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. + 0x1 + + + SMOD_2 + Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. + 0x2 + + + SMOD_4 + Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. + 0x4 + + + SMOD_5 + Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. + 0x5 + + + SMOD_6 + State mode. SHIFTBUF contents are used for storing programmable state attributes. + 0x6 + + + SMOD_7 + Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. + 0x7 + + + + + PINPOL + Shifter Pin Polarity + 7 + 1 + read-write + + + PINPOL_0 + Pin is active high + 0 + + + PINPOL_1 + Pin is active low + 0x1 + + + + + PINSEL + Shifter Pin Select + 8 + 4 + read-write + + + PINCFG + Shifter Pin Configuration + 16 + 2 + read-write + + + PINCFG_0 + Shifter pin output disabled + 0 + + + PINCFG_1 + Shifter pin open drain or bidirectional output enable + 0x1 + + + PINCFG_2 + Shifter pin bidirectional output data + 0x2 + + + PINCFG_3 + Shifter pin output + 0x3 + + + + + TIMPOL + Timer Polarity + 23 + 1 + read-write + + + TIMPOL_0 + Shift on posedge of Shift clock + 0 + + + TIMPOL_1 + Shift on negedge of Shift clock + 0x1 + + + + + TIMSEL + Timer Select + 24 + 2 + read-write + + + + + 4 + 0x4 + SHIFTCFG[%s] + Shifter Configuration N Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SSTART + Shifter Start bit + 0 + 2 + read-write + + + SSTART_0 + Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable + 0 + + + SSTART_1 + Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift + 0x1 + + + SSTART_2 + Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 + 0x2 + + + SSTART_3 + Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 + 0x3 + + + + + SSTOP + Shifter Stop bit + 4 + 2 + read-write + + + SSTOP_0 + Stop bit disabled for transmitter/receiver/match store + 0 + + + SSTOP_2 + Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 + 0x2 + + + SSTOP_3 + Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 + 0x3 + + + + + INSRC + Input Source + 8 + 1 + read-write + + + INSRC_0 + Pin + 0 + + + INSRC_1 + Shifter N+1 Output + 0x1 + + + + + PWIDTH + Parallel Width + 16 + 4 + read-write + + + + + 4 + 0x4 + SHIFTBUF[%s] + Shifter Buffer N Register + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUF + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFBIS[%s] + Shifter Buffer N Bit Swapped Register + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFBIS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFBYS[%s] + Shifter Buffer N Byte Swapped Register + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFBYS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFBBS[%s] + Shifter Buffer N Bit Byte Swapped Register + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFBBS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + TIMCTL[%s] + Timer Control N Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMOD + Timer Mode + 0 + 2 + read-write + + + TIMOD_0 + Timer Disabled. + 0 + + + TIMOD_1 + Dual 8-bit counters baud mode. + 0x1 + + + TIMOD_2 + Dual 8-bit counters PWM high mode. + 0x2 + + + TIMOD_3 + Single 16-bit counter mode. + 0x3 + + + + + PINPOL + Timer Pin Polarity + 7 + 1 + read-write + + + PINPOL_0 + Pin is active high + 0 + + + PINPOL_1 + Pin is active low + 0x1 + + + + + PINSEL + Timer Pin Select + 8 + 4 + read-write + + + PINCFG + Timer Pin Configuration + 16 + 2 + read-write + + + PINCFG_0 + Timer pin output disabled + 0 + + + PINCFG_1 + Timer pin open drain or bidirectional output enable + 0x1 + + + PINCFG_2 + Timer pin bidirectional output data + 0x2 + + + PINCFG_3 + Timer pin output + 0x3 + + + + + TRGSRC + Trigger Source + 22 + 1 + read-write + + + TRGSRC_0 + External trigger selected + 0 + + + TRGSRC_1 + Internal trigger selected + 0x1 + + + + + TRGPOL + Trigger Polarity + 23 + 1 + read-write + + + TRGPOL_0 + Trigger active high + 0 + + + TRGPOL_1 + Trigger active low + 0x1 + + + + + TRGSEL + Trigger Select + 24 + 5 + read-write + + + + + 4 + 0x4 + TIMCFG[%s] + Timer Configuration N Register + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + TSTART + Timer Start Bit + 1 + 1 + read-write + + + TSTART_0 + Start bit disabled + 0 + + + TSTART_1 + Start bit enabled + 0x1 + + + + + TSTOP + Timer Stop Bit + 4 + 2 + read-write + + + TSTOP_0 + Stop bit disabled + 0 + + + TSTOP_1 + Stop bit is enabled on timer compare + 0x1 + + + TSTOP_2 + Stop bit is enabled on timer disable + 0x2 + + + TSTOP_3 + Stop bit is enabled on timer compare and timer disable + 0x3 + + + + + TIMENA + Timer Enable + 8 + 3 + read-write + + + TIMENA_0 + Timer always enabled + 0 + + + TIMENA_1 + Timer enabled on Timer N-1 enable + 0x1 + + + TIMENA_2 + Timer enabled on Trigger high + 0x2 + + + TIMENA_3 + Timer enabled on Trigger high and Pin high + 0x3 + + + TIMENA_4 + Timer enabled on Pin rising edge + 0x4 + + + TIMENA_5 + Timer enabled on Pin rising edge and Trigger high + 0x5 + + + TIMENA_6 + Timer enabled on Trigger rising edge + 0x6 + + + TIMENA_7 + Timer enabled on Trigger rising or falling edge + 0x7 + + + + + TIMDIS + Timer Disable + 12 + 3 + read-write + + + TIMDIS_0 + Timer never disabled + 0 + + + TIMDIS_1 + Timer disabled on Timer N-1 disable + 0x1 + + + TIMDIS_2 + Timer disabled on Timer compare (upper 8-bits match and decrement) + 0x2 + + + TIMDIS_3 + Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low + 0x3 + + + TIMDIS_4 + Timer disabled on Pin rising or falling edge + 0x4 + + + TIMDIS_5 + Timer disabled on Pin rising or falling edge provided Trigger is high + 0x5 + + + TIMDIS_6 + Timer disabled on Trigger falling edge + 0x6 + + + + + TIMRST + Timer Reset + 16 + 3 + read-write + + + TIMRST_0 + Timer never reset + 0 + + + TIMRST_2 + Timer reset on Timer Pin equal to Timer Output + 0x2 + + + TIMRST_3 + Timer reset on Timer Trigger equal to Timer Output + 0x3 + + + TIMRST_4 + Timer reset on Timer Pin rising edge + 0x4 + + + TIMRST_6 + Timer reset on Trigger rising edge + 0x6 + + + TIMRST_7 + Timer reset on Trigger rising or falling edge + 0x7 + + + + + TIMDEC + Timer Decrement + 20 + 2 + read-write + + + TIMDEC_0 + Decrement counter on FlexIO clock, Shift clock equals Timer output. + 0 + + + TIMDEC_1 + Decrement counter on Trigger input (both edges), Shift clock equals Timer output. + 0x1 + + + TIMDEC_2 + Decrement counter on Pin input (both edges), Shift clock equals Pin input. + 0x2 + + + TIMDEC_3 + Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. + 0x3 + + + + + TIMOUT + Timer Output + 24 + 2 + read-write + + + TIMOUT_0 + Timer output is logic one when enabled and is not affected by timer reset + 0 + + + TIMOUT_1 + Timer output is logic zero when enabled and is not affected by timer reset + 0x1 + + + TIMOUT_2 + Timer output is logic one when enabled and on timer reset + 0x2 + + + TIMOUT_3 + Timer output is logic zero when enabled and on timer reset + 0x3 + + + + + + + 4 + 0x4 + TIMCMP[%s] + Timer Compare N Register + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMP + Timer Compare Value + 0 + 16 + read-write + + + + + 4 + 0x4 + SHIFTBUFNBS[%s] + Shifter Buffer N Nibble Byte Swapped Register + 0x680 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFNBS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFHWS[%s] + Shifter Buffer N Half Word Swapped Register + 0x700 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFHWS + Shift Buffer + 0 + 32 + read-write + + + + + 4 + 0x4 + SHIFTBUFNIS[%s] + Shifter Buffer N Nibble Swapped Register + 0x780 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFTBUFNIS + Shift Buffer + 0 + 32 + read-write + + + + + + + FLEXIO2 + FLEXIO + FLEXIO + 0x401B0000 + + 0 + 0x790 + registers + + + FLEXIO2 + 91 + + + + FLEXIO3 + FLEXIO + FLEXIO + 0x42020000 + + 0 + 0x790 + registers + + + FLEXIO3 + 156 + + + + GPIO1 + GPIO + GPIO + GPIO + 0x401B8000 + + 0 + 0x90 + registers + + + GPIO1_INT0 + 72 + + + GPIO1_INT1 + 73 + + + GPIO1_INT2 + 74 + + + GPIO1_INT3 + 75 + + + GPIO1_INT4 + 76 + + + GPIO1_INT5 + 77 + + + GPIO1_INT6 + 78 + + + GPIO1_INT7 + 79 + + + GPIO1_Combined_0_15 + 80 + + + GPIO1_Combined_16_31 + 81 + + + + DR + GPIO data register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DR + DR + 0 + 32 + read-write + + + + + GDIR + GPIO direction register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + GDIR + GDIR + 0 + 32 + read-write + + + + + PSR + GPIO pad status register + 0x8 + 32 + read-only + 0 + 0xFFFFFFFF + + + PSR + PSR + 0 + 32 + read-only + + + + + ICR1 + GPIO interrupt configuration register1 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ICR0 + ICR0 + 0 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR1 + ICR1 + 2 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR2 + ICR2 + 4 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR3 + ICR3 + 6 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR4 + ICR4 + 8 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR5 + ICR5 + 10 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR6 + ICR6 + 12 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR7 + ICR7 + 14 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR8 + ICR8 + 16 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR9 + ICR9 + 18 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR10 + ICR10 + 20 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR11 + ICR11 + 22 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR12 + ICR12 + 24 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR13 + ICR13 + 26 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR14 + ICR14 + 28 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR15 + ICR15 + 30 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + + + ICR2 + GPIO interrupt configuration register2 + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICR16 + ICR16 + 0 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR17 + ICR17 + 2 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR18 + ICR18 + 4 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR19 + ICR19 + 6 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR20 + ICR20 + 8 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR21 + ICR21 + 10 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR22 + ICR22 + 12 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR23 + ICR23 + 14 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR24 + ICR24 + 16 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR25 + ICR25 + 18 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR26 + ICR26 + 20 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR27 + ICR27 + 22 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR28 + ICR28 + 24 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR29 + ICR29 + 26 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR30 + ICR30 + 28 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + ICR31 + ICR31 + 30 + 2 + read-write + + + LOW_LEVEL + Interrupt n is low-level sensitive. + 0 + + + HIGH_LEVEL + Interrupt n is high-level sensitive. + 0x1 + + + RISING_EDGE + Interrupt n is rising-edge sensitive. + 0x2 + + + FALLING_EDGE + Interrupt n is falling-edge sensitive. + 0x3 + + + + + + + IMR + GPIO interrupt mask register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + IMR + IMR + 0 + 32 + read-write + + + + + ISR + GPIO interrupt status register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + ISR + ISR + 0 + 32 + read-write + oneToClear + + + + + EDGE_SEL + GPIO edge select register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPIO_EDGE_SEL + GPIO_EDGE_SEL + 0 + 32 + read-write + + + + + DR_SET + GPIO data register SET + 0x84 + 32 + write-only + 0 + 0xFFFFFFFF + + + DR_SET + DR_SET + 0 + 32 + write-only + + + + + DR_CLEAR + GPIO data register CLEAR + 0x88 + 32 + write-only + 0 + 0xFFFFFFFF + + + DR_CLEAR + DR_CLEAR + 0 + 32 + write-only + + + + + DR_TOGGLE + GPIO data register TOGGLE + 0x8C + 32 + write-only + 0 + 0xFFFFFFFF + + + DR_TOGGLE + DR_TOGGLE + 0 + 32 + write-only + + + + + + + GPIO5 + GPIO + GPIO + 0x400C0000 + + 0 + 0x90 + registers + + + GPIO5_Combined_0_15 + 88 + + + GPIO5_Combined_16_31 + 89 + + + + GPIO2 + GPIO + GPIO + 0x401BC000 + + 0 + 0x90 + registers + + + GPIO2_Combined_0_15 + 82 + + + GPIO2_Combined_16_31 + 83 + + + + GPIO3 + GPIO + GPIO + 0x401C0000 + + 0 + 0x90 + registers + + + GPIO3_Combined_0_15 + 84 + + + GPIO3_Combined_16_31 + 85 + + + + GPIO4 + GPIO + GPIO + 0x401C4000 + + 0 + 0x90 + registers + + + GPIO4_Combined_0_15 + 86 + + + GPIO4_Combined_16_31 + 87 + + + + GPIO6 + GPIO + GPIO + 0x42000000 + + 0 + 0x90 + registers + + + GPIO6_7_8_9 + 157 + + + + GPIO7 + GPIO + GPIO + 0x42004000 + + 0 + 0x90 + registers + + + GPIO6_7_8_9 + 157 + + + + GPIO8 + GPIO + GPIO + 0x42008000 + + 0 + 0x90 + registers + + + GPIO6_7_8_9 + 157 + + + + GPIO9 + GPIO + GPIO + 0x4200C000 + + 0 + 0x90 + registers + + + GPIO6_7_8_9 + 157 + + + + CAN1 + FLEXCAN + CAN + FLEXCAN1_ + CAN + 0x401D0000 + + 0 + 0x9E4 + registers + + + CAN1 + 36 + + + + MCR + Module Configuration Register + 0 + 32 + read-write + 0x5980000F + 0xFFFFFFFF + + + MAXMB + This 7-bit field defines the number of the last Message Buffers that will take part in the matching and arbitration processes + 0 + 7 + read-write + + + IDAM + This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown below + 8 + 2 + read-write + + + IDAM_0 + Format A One full ID (standard or extended) per ID filter Table element. + 0 + + + IDAM_1 + Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element. + 0x1 + + + IDAM_2 + Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element. + 0x2 + + + IDAM_3 + Format D All frames rejected. + 0x3 + + + + + AEN + This bit is supplied for backwards compatibility reasons + 12 + 1 + read-write + + + AEN_0 + Abort disabled + 0 + + + AEN_1 + Abort enabled + 0x1 + + + + + LPRIOEN + This bit is provided for backwards compatibility reasons + 13 + 1 + read-write + + + LPRIOEN_0 + Local Priority disabled + 0 + + + LPRIOEN_1 + Local Priority enabled + 0x1 + + + + + IRMQ + This bit indicates whether Rx matching process will be based either on individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and RX15MASK, RXFGMASK + 16 + 1 + read-write + + + IRMQ_0 + Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY. + 0 + + + IRMQ_1 + Individual Rx masking and queue feature are enabled. + 0x1 + + + + + SRXDIS + This bit defines whether FlexCAN is allowed to receive frames transmitted by itself + 17 + 1 + read-write + + + SRXDIS_0 + Self reception enabled + 0 + + + SRXDIS_1 + Self reception disabled + 0x1 + + + + + WAKSRC + This bit defines whether the integrated low-pass filter is applied to protect the FLEXCAN_RX input from spurious wake up + 19 + 1 + read-write + + + WAKSRC_0 + FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus. + 0 + + + WAKSRC_1 + FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus + 0x1 + + + + + LPMACK + This read-only bit indicates that FLEXCAN is either in Disable Mode or Stop Mode + 20 + 1 + read-only + + + LPMACK_0 + FLEXCAN not in any of the low power modes + 0 + + + LPMACK_1 + FLEXCAN is either in Disable Mode, or Stop mode + 0x1 + + + + + WRNEN + When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and Status Register + 21 + 1 + read-write + + + WRNEN_0 + TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters. + 0 + + + WRNEN_1 + TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96. + 0x1 + + + + + SLFWAK + This bit enables the Self Wake Up feature when FLEXCAN is in Stop Mode + 22 + 1 + read-write + + + SLFWAK_0 + FLEXCAN Self Wake Up feature is disabled + 0 + + + SLFWAK_1 + FLEXCAN Self Wake Up feature is enabled + 0x1 + + + + + SUPV + This bit configures some of the FLEXCAN registers to be either in Supervisor or User Mode + 23 + 1 + read-write + + + SUPV_0 + FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses + 0 + + + SUPV_1 + FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location + 0x1 + + + + + FRZACK + This read-only bit indicates that FLEXCAN is in Freeze Mode and its prescaler is stopped + 24 + 1 + read-only + + + FRZACK_0 + FLEXCAN not in Freeze Mode, prescaler running + 0 + + + FRZACK_1 + FLEXCAN in Freeze Mode, prescaler stopped + 0x1 + + + + + SOFTRST + When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped registers + 25 + 1 + read-write + + + SOFTRST_0 + No reset request + 0 + + + SOFTRST_1 + Reset the registers + 0x1 + + + + + WAKMSK + This bit enables the Wake Up Interrupt generation. + 26 + 1 + read-write + + + WAKMSK_0 + Wake Up Interrupt is disabled + 0 + + + WAKMSK_1 + Wake Up Interrupt is enabled + 0x1 + + + + + NOTRDY + This read-only bit indicates that FLEXCAN is either in Disable Mode, Stop Mode or Freeze Mode + 27 + 1 + read-only + + + NOTRDY_0 + FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode + 0 + + + NOTRDY_1 + FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode + 0x1 + + + + + HALT + Assertion of this bit puts the FLEXCAN module into Freeze Mode + 28 + 1 + read-write + + + HALT_0 + No Freeze Mode request. + 0 + + + HALT_1 + Enters Freeze Mode if the FRZ bit is asserted. + 0x1 + + + + + RFEN + This bit controls whether the Rx FIFO feature is enabled or not + 29 + 1 + read-write + + + RFEN_0 + FIFO not enabled + 0 + + + RFEN_1 + FIFO enabled + 0x1 + + + + + FRZ + The FRZ bit specifies the FLEXCAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at Arm level + 30 + 1 + read-write + + + FRZ_0 + Not enabled to enter Freeze Mode + 0 + + + FRZ_1 + Enabled to enter Freeze Mode + 0x1 + + + + + MDIS + This bit controls whether FLEXCAN is enabled or not + 31 + 1 + read-write + + + MDIS_0 + Enable the FLEXCAN module + 0 + + + MDIS_1 + Disable the FLEXCAN module + 0x1 + + + + + + + CTRL1 + Control 1 Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PROPSEG + This 3-bit field defines the length of the Propagation Segment in the bit time + 0 + 3 + read-write + + + LOM + This bit configures FLEXCAN to operate in Listen Only Mode + 3 + 1 + read-write + + + LOM_0 + Listen Only Mode is deactivated + 0 + + + LOM_1 + FLEXCAN module operates in Listen Only Mode + 0x1 + + + + + LBUF + This bit defines the ordering mechanism for Message Buffer transmission + 4 + 1 + read-write + + + LBUF_0 + Buffer with highest priority is transmitted first + 0 + + + LBUF_1 + Lowest number buffer is transmitted first + 0x1 + + + + + TSYN + This bit enables a mechanism that resets the free-running timer each time a message is received in Message Buffer 0 + 5 + 1 + read-write + + + TSYN_0 + Timer Sync feature disabled + 0 + + + TSYN_1 + Timer Sync feature enabled + 0x1 + + + + + BOFFREC + This bit defines how FLEXCAN recovers from Bus Off state + 6 + 1 + read-write + + + BOFFREC_0 + Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B + 0 + + + BOFFREC_1 + Automatic recovering from Bus Off state disabled + 0x1 + + + + + SMP + This bit defines the sampling mode of CAN bits at the FLEXCAN_RX + 7 + 1 + read-write + + + SMP_0 + Just one sample is used to determine the bit value + 0 + + + SMP_1 + Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used + 0x1 + + + + + RWRNMSK + This bit provides a mask for the Rx Warning Interrupt associated with the RWRN_INT flag in the Error and Status Register + 10 + 1 + read-write + + + RWRNMSK_0 + Rx Warning Interrupt disabled + 0 + + + RWRNMSK_1 + Rx Warning Interrupt enabled + 0x1 + + + + + TWRNMSK + This bit provides a mask for the Tx Warning Interrupt associated with the TWRN_INT flag in the Error and Status Register + 11 + 1 + read-write + + + TWRNMSK_0 + Tx Warning Interrupt disabled + 0 + + + TWRNMSK_1 + Tx Warning Interrupt enabled + 0x1 + + + + + LPB + This bit configures FlexCAN to operate in Loop-Back Mode + 12 + 1 + read-write + + + LPB_0 + Loop Back disabled + 0 + + + LPB_1 + Loop Back enabled + 0x1 + + + + + ERRMSK + This bit provides a mask for the Error Interrupt. + 14 + 1 + read-write + + + ERRMSK_0 + Error interrupt disabled + 0 + + + ERRMSK_1 + Error interrupt enabled + 0x1 + + + + + BOFFMSK + This bit provides a mask for the Bus Off Interrupt. + 15 + 1 + read-write + + + BOFFMSK_0 + Bus Off interrupt disabled + 0 + + + BOFFMSK_1 + Bus Off interrupt enabled + 0x1 + + + + + PSEG2 + This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time + 16 + 3 + read-write + + + PSEG1 + This 3-bit field defines the length of Phase Buffer Segment 1 in the bit time + 19 + 3 + read-write + + + RJW + This 2-bit field defines the maximum number of time quanta One time quantum is equal to the Sclock period + 22 + 2 + read-write + + + PRESDIV + This 8-bit field defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency + 24 + 8 + read-write + + + + + TIMER + Free Running Timer Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMER + TIMER + 0 + 16 + read-write + + + + + RXMGMASK + Rx Mailboxes Global Mask Register + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + MG + These bits mask the Mailbox filter bits as shown in the figure above + 0 + 32 + read-write + + + MG_0 + the corresponding bit in the filter is "don't care" + 0 + + + MG_1 + The corresponding bit in the filter is checked against the one received + 0x1 + + + + + + + RX14MASK + Rx Buffer 14 Mask Register + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + RX14M + These bits mask Mailbox 14 filter bits in the same fashion as RXMGMASK masks other Mailboxes filters (see RXMGMASKRx Mailboxes Global Mask Register ) + 0 + 32 + read-write + + + RX14M_0 + the corresponding bit in the filter is "don't care" + 0 + + + RX14M_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + RX15MASK + Rx Buffer 15 Mask Register + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + RX15M + These bits mask Mailbox 15 filter bits in the same fashion as RXMGMASK masks other Mailboxes filters (see RXMGMASKRx Mailboxes Global Mask Register ) + 0 + 32 + read-write + + + RX15M_0 + the corresponding bit in the filter is "don't care" + 0 + + + RX15M_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + ECR + Error Counter Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_ERR_COUNTER + Tx_Err_Counter + 0 + 8 + read-write + + + RX_ERR_COUNTER + Rx_Err_Counter + 8 + 8 + read-write + + + + + ESR1 + Error and Status 1 Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAKINT + When FLEXCAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the Arm + 0 + 1 + read-write + + + WAKINT_0 + No such occurrence + 0 + + + WAKINT_1 + Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode + 0x1 + + + + + ERRINT + This bit indicates that at least one of the Error Bits (bits 15-10) is set + 1 + 1 + read-write + + + ERRINT_0 + No such occurrence + 0 + + + ERRINT_1 + Indicates setting of any Error Bit in the Error and Status Register + 0x1 + + + + + BOFFINT + This bit is set when FLEXCAN enters 'Bus Off' state + 2 + 1 + read-write + + + BOFFINT_0 + No such occurrence + 0 + + + BOFFINT_1 + FLEXCAN module entered 'Bus Off' state + 0x1 + + + + + RX + This bit indicates if FlexCAN is receiving a message. Refer to . + 3 + 1 + read-only + + + RX_0 + FLEXCAN is receiving a message + 0 + + + RX_1 + FLEXCAN is transmitting a message + 0x1 + + + + + FLTCONF + If the LOM bit in the Control Register is asserted, after some delay that depends on the CAN bit timing the FLT_CONF field will indicate "Error Passive" + 4 + 2 + read-only + + + FLTCONF_0 + Error Active + 0 + + + FLTCONF_1 + Error Passive + 0x1 + + + FLTCONF_2 + Bus off + #1x + + + + + TX + This bit indicates if FLEXCAN is transmitting a message.Refer to . + 6 + 1 + read-only + + + TX_0 + FLEXCAN is receiving a message + 0 + + + TX_1 + FLEXCAN is transmitting a message + 0x1 + + + + + IDLE + This bit indicates when CAN bus is in IDLE state.Refer to . + 7 + 1 + read-only + + + IDLE_0 + No such occurrence + 0 + + + IDLE_1 + CAN bus is now IDLE + 0x1 + + + + + RXWRN + This bit indicates when repetitive errors are occurring during message reception. + 8 + 1 + read-only + + + RXWRN_0 + No such occurrence + 0 + + + RXWRN_1 + Rx_Err_Counter >= 96 + 0x1 + + + + + TXWRN + This bit indicates when repetitive errors are occurring during message transmission. + 9 + 1 + read-only + + + TXWRN_0 + No such occurrence + 0 + + + TXWRN_1 + TX_Err_Counter >= 96 + 0x1 + + + + + STFERR + This bit indicates that a Stuffing Error has been detected. + 10 + 1 + read-only + + + STFERR_0 + No such occurrence. + 0 + + + STFERR_1 + A Stuffing Error occurred since last read of this register. + 0x1 + + + + + FRMERR + This bit indicates that a Form Error has been detected by the receiver node, i + 11 + 1 + read-only + + + FRMERR_0 + No such occurrence + 0 + + + FRMERR_1 + A Form Error occurred since last read of this register + 0x1 + + + + + CRCERR + This bit indicates that a CRC Error has been detected by the receiver node, i + 12 + 1 + read-only + + + CRCERR_0 + No such occurrence + 0 + + + CRCERR_1 + A CRC error occurred since last read of this register. + 0x1 + + + + + ACKERR + This bit indicates that an Acknowledge Error has been detected by the transmitter node, i + 13 + 1 + read-only + + + ACKERR_0 + No such occurrence + 0 + + + ACKERR_1 + An ACK error occurred since last read of this register + 0x1 + + + + + BIT0ERR + This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message + 14 + 1 + read-only + + + BIT0ERR_0 + No such occurrence + 0 + + + BIT0ERR_1 + At least one bit sent as dominant is received as recessive + 0x1 + + + + + BIT1ERR + This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message + 15 + 1 + read-only + + + BIT1ERR_0 + No such occurrence + 0 + + + BIT1ERR_1 + At least one bit sent as recessive is received as dominant + 0x1 + + + + + RWRNINT + If the WRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition from '0' to '1', meaning that the Rx error counters reached 96 + 16 + 1 + read-write + + + RWRNINT_0 + No such occurrence + 0 + + + RWRNINT_1 + The Rx error counter transition from < 96 to >= 96 + 0x1 + + + + + TWRNINT + If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition from '0' to '1', meaning that the Tx error counter reached 96 + 17 + 1 + read-write + + + TWRNINT_0 + No such occurrence + 0 + + + TWRNINT_1 + The Tx error counter transition from < 96 to >= 96 + 0x1 + + + + + SYNCH + This read-only flag indicates whether the FlexCAN is synchronized to the CAN bus and able to participate in the communication process + 18 + 1 + read-only + + + SYNCH_0 + FlexCAN is not synchronized to the CAN bus + 0 + + + SYNCH_1 + FlexCAN is synchronized to the CAN bus + 0x1 + + + + + + + IMASK2 + Interrupt Masks 2 Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFHM + Each bit enables or disables the respective FLEXCAN Message Buffer (MB32 to MB63) Interrupt + 0 + 32 + read-write + + + BUFHM_0 + The corresponding buffer Interrupt is disabled + 0 + + + BUFHM_1 + The corresponding buffer Interrupt is enabled + 0x1 + + + + + + + IMASK1 + Interrupt Masks 1 Register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFLM + Each bit enables or disables the respective FLEXCAN Message Buffer (MB0 to MB31) Interrupt + 0 + 32 + read-write + + + BUFLM_0 + The corresponding buffer Interrupt is disabled + 0 + + + BUFLM_1 + The corresponding buffer Interrupt is enabled + 0x1 + + + + + + + IFLAG2 + Interrupt Flags 2 Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + BUFHI + Each bit flags the respective FLEXCAN Message Buffer (MB32 to MB63) interrupt. + 0 + 32 + read-write + + + BUFHI_0 + No such occurrence + 0 + + + BUFHI_1 + The corresponding buffer has successfully completed transmission or reception + 0x1 + + + + + + + IFLAG1 + Interrupt Flags 1 Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUF4TO0I + If the Rx FIFO is not enabled, these bits flag the interrupts for MB0 to MB4 + 0 + 5 + read-write + + + BUF4TO0I_0 + No such occurrence + 0 + + + BUF4TO0I_1 + Corresponding MB completed transmission/reception + 0x1 + + + + + BUF5I + If the Rx FIFO is not enabled, this bit flags the interrupt for MB5 + 5 + 1 + read-write + + + BUF5I_0 + No such occurrence + 0 + + + BUF5I_1 + MB5 completed transmission/reception or frames available in the FIFO + 0x1 + + + + + BUF6I + If the Rx FIFO is not enabled, this bit flags the interrupt for MB6 + 6 + 1 + read-write + + + BUF6I_0 + No such occurrence + 0 + + + BUF6I_1 + MB6 completed transmission/reception or FIFO almost full + 0x1 + + + + + BUF7I + If the Rx FIFO is not enabled, this bit flags the interrupt for MB7 + 7 + 1 + read-write + + + BUF7I_0 + No such occurrence + 0 + + + BUF7I_1 + MB7 completed transmission/reception or FIFO overflow + 0x1 + + + + + BUF31TO8I + Each bit flags the respective FLEXCAN Message Buffer (MB8 to MB31) interrupt. + 8 + 24 + read-write + + + BUF31TO8I_0 + No such occurrence + 0 + + + BUF31TO8I_1 + The corresponding MB has successfully completed transmission or reception + 0x1 + + + + + + + CTRL2 + Control 2 Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + EACEN + This bit controls the comparison of IDE and RTR bits within Rx Mailboxes filters with their corresponding bits in the incoming frame by the matching process + 16 + 1 + read-write + + + EACEN_0 + Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. + 0 + + + EACEN_1 + Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. + 0x1 + + + + + RRS + If this bit is asserted Remote Request Frame is submitted to a matching process and stored in the corresponding Message Buffer in the same fashion of a Data Frame + 17 + 1 + read-write + + + RRS_0 + Remote Response Frame is generated + 0 + + + RRS_1 + Remote Request Frame is stored + 0x1 + + + + + MRP + If this bit is set the matching process starts from the Mailboxes and if no match occurs the matching continues on the Rx FIFO + 18 + 1 + read-write + + + MRP_0 + Matching starts from Rx FIFO and continues on Mailboxes + 0 + + + MRP_1 + Matching starts from Mailboxes and continues on Rx FIFO + 0x1 + + + + + TASD + This 5-bit field indicates how many CAN bits the Tx arbitration process start point can be delayed from the first bit of CRC field on CAN bus + 19 + 5 + read-write + + + RFFN + This 4-bit field defines the number of Rx FIFO filters according to + 24 + 4 + read-write + + + WRMFRZ + Enable unrestricted write access to FlexCAN memory in Freeze mode + 28 + 1 + read-write + + + WRMFRZ_0 + Keep the write access restricted in some regions of FlexCAN memory + 0 + + + WRMFRZ_1 + Enable unrestricted write access to FlexCAN memory + 0x1 + + + + + + + ESR2 + Error and Status 2 Register + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + IMB + If ESR2[VPS] is asserted, this bit indicates whether there is any inactive Mailbox (CODE field is either 0b1000 or 0b0000) + 13 + 1 + read-only + + + IMB_0 + If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. + 0 + + + IMB_1 + If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. + 0x1 + + + + + VPS + This bit indicates whether IMB and LPTM contents are currently valid or not + 14 + 1 + read-only + + + VPS_0 + Contents of IMB and LPTM are invalid + 0 + + + VPS_1 + Contents of IMB and LPTM are valid + 0x1 + + + + + LPTM + If ESR2[VPS] is asserted, his 7-bit field indicates the lowest number inactive Mailbox (refer to IMB bit description) + 16 + 7 + read-only + + + + + CRCR + CRC Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXCRC + This field indicates the CRC value of the last message transmitted + 0 + 15 + read-only + + + MBCRC + This field indicates the number of the Mailbox corresponding to the value in TXCRC field. + 16 + 7 + read-only + + + + + RXFGMASK + Rx FIFO Global Mask Register + 0x48 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + FGM + These bits mask the ID Filter Table elements bits in a perfect alignment + 0 + 32 + read-write + + + FGM_0 + The corresponding bit in the filter is "don't care" + 0 + + + FGM_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + RXFIR + Rx FIFO Information Register + 0x4C + 32 + read-only + 0 + 0xFFFFFFFF + + + IDHIT + This 9-bit field indicates which Identifier Acceptance Filter (see Rx FIFO Structure) was hit by the received message that is in the output of the Rx FIFO + 0 + 9 + read-only + + + + + DBG1 + Debug 1 register + 0x58 + 32 + read-only + 0x10000 + 0xFFFFFFFF + + + CFSM + CAN Finite State Machine + 0 + 6 + read-only + + + CBN + CAN Bit Number + 24 + 5 + read-only + + + + + DBG2 + Debug 2 register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + RMP + Rx Matching Pointer + 0 + 7 + read-only + + + MPP + Matching Process in Progress + 7 + 1 + read-only + + + MPP_0 + No matching process ongoing. + 0 + + + MPP_1 + Matching process is in progress. + 0x1 + + + + + TAP + Tx Arbitration Pointer + 8 + 7 + read-only + + + APP + Arbitration Process in Progress + 15 + 1 + read-only + + + APP_0 + No matching process ongoing. + 0 + + + APP_1 + Matching process is in progress. + 0x1 + + + + + + + 64 + 0x4 + 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63 + RXIMR%s + Rx Individual Mask Registers + 0x880 + 32 + read-write + 0 + 0xFFFFFFFF + + + MI + These bits mask both Mailbox filter and Rx FIFO ID Filter Table element in distinct ways + 0 + 32 + read-write + + + MI_0 + the corresponding bit in the filter is "don't care" + 0 + + + MI_1 + The corresponding bit in the filter is checked + 0x1 + + + + + + + GFWR + Glitch Filter Width Registers + 0x9E0 + 32 + read-write + 0x7F + 0xFFFFFFFF + + + GFWR + It determines the Glitch Filter Width + 0 + 8 + read-write + + + + + + + CAN2 + FLEXCAN + CAN + FLEXCAN2_ + 0x401D4000 + + 0 + 0x9E4 + registers + + + CAN2 + 37 + + + + CAN3 + CAN + CAN + 0x401D8000 + + 0 + 0x3200 + registers + + + CAN3 + 154 + + + + MCR + Module Configuration Register + 0 + 32 + read-write + 0x5980000F + 0xFFFFFFFF + + + MAXMB + Number Of The Last Message Buffer + 0 + 7 + read-write + + + IDAM + ID Acceptance Mode + 8 + 2 + read-write + + + IDAM_0 + Format A: One full ID (standard and extended) per ID Filter Table element. + 0 + + + IDAM_1 + Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. + 0x1 + + + IDAM_2 + Format C: Four partial 8-bit Standard IDs per ID Filter Table element. + 0x2 + + + IDAM_3 + Format D: All frames rejected. + 0x3 + + + + + FDEN + CAN FD operation enable + 11 + 1 + read-write + + + FDEN_0 + CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format. + 0 + + + FDEN_1 + CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats. + 0x1 + + + + + AEN + Abort Enable + 12 + 1 + read-write + + + AEN_0 + Abort disabled. + 0 + + + AEN_1 + Abort enabled. + 0x1 + + + + + LPRIOEN + Local Priority Enable + 13 + 1 + read-write + + + LPRIOEN_0 + Local Priority disabled. + 0 + + + LPRIOEN_1 + Local Priority enabled. + 0x1 + + + + + DMA + DMA Enable + 15 + 1 + read-write + + + DMA_0 + DMA feature for Legacy RX FIFO or Enhanced Rx FIFO are disabled. + 0 + + + DMA_1 + DMA feature for Legacy RX FIFO or Enhanced Rx FIFO are enabled. + 0x1 + + + + + IRMQ + Individual Rx Masking And Queue Enable + 16 + 1 + read-write + + + IRMQ_0 + Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY. + 0 + + + IRMQ_1 + Individual Rx masking and queue feature are enabled. + 0x1 + + + + + SRXDIS + Self Reception Disable + 17 + 1 + read-write + + + SRXDIS_0 + Self reception enabled. + 0 + + + SRXDIS_1 + Self reception disabled. + 0x1 + + + + + DOZE + Doze Mode Enable + 18 + 1 + read-write + + + DOZE_0 + FlexCAN is not enabled to enter low-power mode when Doze mode is requested. + 0 + + + DOZE_1 + FlexCAN is enabled to enter low-power mode when Doze mode is requested. + 0x1 + + + + + WAKSRC + Wake Up Source + 19 + 1 + read-write + + + WAKSRC_0 + FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus. + 0 + + + WAKSRC_1 + FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. + 0x1 + + + + + LPMACK + Low-Power Mode Acknowledge + 20 + 1 + read-only + + + LPMACK_0 + FlexCAN is not in a low-power mode. + 0 + + + LPMACK_1 + FlexCAN is in a low-power mode. + 0x1 + + + + + WRNEN + Warning Interrupt Enable + 21 + 1 + read-write + + + WRNEN_0 + TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. + 0 + + + WRNEN_1 + TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. + 0x1 + + + + + SLFWAK + Self Wake Up + 22 + 1 + read-write + + + SLFWAK_0 + FlexCAN Self Wake Up feature is disabled. + 0 + + + SLFWAK_1 + FlexCAN Self Wake Up feature is enabled. + 0x1 + + + + + SUPV + Supervisor Mode + 23 + 1 + read-write + + + SUPV_0 + FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses. + 0 + + + SUPV_1 + FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location. + 0x1 + + + + + FRZACK + Freeze Mode Acknowledge + 24 + 1 + read-only + + + FRZACK_0 + FlexCAN not in Freeze mode, prescaler running. + 0 + + + FRZACK_1 + FlexCAN in Freeze mode, prescaler stopped. + 0x1 + + + + + SOFTRST + Soft Reset + 25 + 1 + read-write + + + SOFTRST_0 + No reset request. + 0 + + + SOFTRST_1 + Resets the registers affected by soft reset. + 0x1 + + + + + WAKMSK + Wake Up Interrupt Mask + 26 + 1 + read-write + + + WAKMSK_0 + Wake Up Interrupt is disabled. + 0 + + + WAKMSK_1 + Wake Up Interrupt is enabled. + 0x1 + + + + + NOTRDY + FlexCAN Not Ready + 27 + 1 + read-only + + + NOTRDY_0 + FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode. + 0 + + + NOTRDY_1 + FlexCAN module is either in Disable mode, Doze mode , Stop mode or Freeze mode. + 0x1 + + + + + HALT + Halt FlexCAN + 28 + 1 + read-write + + + HALT_0 + No Freeze mode request. + 0 + + + HALT_1 + Enters Freeze mode if the FRZ bit is asserted. + 0x1 + + + + + RFEN + Legacy Rx FIFO Enable + 29 + 1 + read-write + + + RFEN_0 + Legacy Rx FIFO not enabled. + 0 + + + RFEN_1 + Legacy Rx FIFO enabled. + 0x1 + + + + + FRZ + Freeze Enable + 30 + 1 + read-write + + + FRZ_0 + Not enabled to enter Freeze mode. + 0 + + + FRZ_1 + Enabled to enter Freeze mode. + 0x1 + + + + + MDIS + Module Disable + 31 + 1 + read-write + + + MDIS_0 + Enable the FlexCAN module. + 0 + + + MDIS_1 + Disable the FlexCAN module. + 0x1 + + + + + + + CTRL1 + Control 1 register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PROPSEG + Propagation Segment + 0 + 3 + read-write + + + LOM + Listen-Only Mode + 3 + 1 + read-write + + + LOM_0 + Listen-Only mode is deactivated. + 0 + + + LOM_1 + FlexCAN module operates in Listen-Only mode. + 0x1 + + + + + LBUF + Lowest Buffer Transmitted First + 4 + 1 + read-write + + + LBUF_0 + Buffer with highest priority is transmitted first. + 0 + + + LBUF_1 + Lowest number buffer is transmitted first. + 0x1 + + + + + TSYN + Timer Sync + 5 + 1 + read-write + + + TSYN_0 + Timer Sync feature disabled + 0 + + + TSYN_1 + Timer Sync feature enabled + 0x1 + + + + + BOFFREC + Bus Off Recovery + 6 + 1 + read-write + + + BOFFREC_0 + Automatic recovering from Bus Off state enabled. + 0 + + + BOFFREC_1 + Automatic recovering from Bus Off state disabled. + 0x1 + + + + + SMP + CAN Bit Sampling + 7 + 1 + read-write + + + SMP_0 + Just one sample is used to determine the bit value. + 0 + + + SMP_1 + Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used. + 0x1 + + + + + RWRNMSK + Rx Warning Interrupt Mask + 10 + 1 + read-write + + + RWRNMSK_0 + Rx Warning Interrupt disabled. + 0 + + + RWRNMSK_1 + Rx Warning Interrupt enabled. + 0x1 + + + + + TWRNMSK + Tx Warning Interrupt Mask + 11 + 1 + read-write + + + TWRNMSK_0 + Tx Warning Interrupt disabled. + 0 + + + TWRNMSK_1 + Tx Warning Interrupt enabled. + 0x1 + + + + + LPB + Loop Back Mode + 12 + 1 + read-write + + + LPB_0 + Loop Back disabled. + 0 + + + LPB_1 + Loop Back enabled. + 0x1 + + + + + CLKSRC + CAN Engine Clock Source + 13 + 1 + read-write + + + CLKSRC_0 + The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. + 0 + + + CLKSRC_1 + The CAN engine clock source is the peripheral clock. + 0x1 + + + + + ERRMSK + Error Interrupt Mask + 14 + 1 + read-write + + + ERRMSK_0 + Error interrupt disabled. + 0 + + + ERRMSK_1 + Error interrupt enabled. + 0x1 + + + + + BOFFMSK + Bus Off Interrupt Mask + 15 + 1 + read-write + + + BOFFMSK_0 + Bus Off interrupt disabled. + 0 + + + BOFFMSK_1 + Bus Off interrupt enabled. + 0x1 + + + + + PSEG2 + Phase Segment 2 + 16 + 3 + read-write + + + PSEG1 + Phase Segment 1 + 19 + 3 + read-write + + + RJW + Resync Jump Width + 22 + 2 + read-write + + + PRESDIV + Prescaler Division Factor + 24 + 8 + read-write + + + + + TIMER + Free Running Timer + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIMER + Timer Value + 0 + 16 + read-write + + + + + RXMGMASK + Rx Mailboxes Global Mask Register + 0x10 + 32 + read-write + 0 + 0 + + + MG + Rx Mailboxes Global Mask Bits + 0 + 32 + read-write + + + + + RX14MASK + Rx 14 Mask register + 0x14 + 32 + read-write + 0 + 0 + + + RX14M + Rx Buffer 14 Mask Bits + 0 + 32 + read-write + + + + + RX15MASK + Rx 15 Mask register + 0x18 + 32 + read-write + 0 + 0 + + + RX15M + Rx Buffer 15 Mask Bits + 0 + 32 + read-write + + + + + ECR + Error Counter + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TXERRCNT + Transmit Error Counter + 0 + 8 + read-write + + + RXERRCNT + Receive Error Counter + 8 + 8 + read-write + + + TXERRCNT_FAST + Transmit Error Counter for fast bits + 16 + 8 + read-write + + + RXERRCNT_FAST + Receive Error Counter for fast bits + 24 + 8 + read-write + + + + + ESR1 + Error and Status 1 register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + WAKINT + Wake-Up Interrupt + 0 + 1 + read-write + oneToClear + + + WAKINT_0 + No such occurrence. + 0 + + + WAKINT_1 + Indicates a recessive to dominant transition was received on the CAN bus. + 0x1 + + + + + ERRINT + Error Interrupt + 1 + 1 + read-write + oneToClear + + + ERRINT_0 + No such occurrence. + 0 + + + ERRINT_1 + Indicates setting of any Error Bit in the Error and Status Register. + 0x1 + + + + + BOFFINT + Bus Off Interrupt + 2 + 1 + read-write + oneToClear + + + BOFFINT_0 + No such occurrence. + 0 + + + BOFFINT_1 + FlexCAN module entered Bus Off state. + 0x1 + + + + + RX + FlexCAN In Reception + 3 + 1 + read-only + + + RX_0 + FlexCAN is not receiving a message. + 0 + + + RX_1 + FlexCAN is receiving a message. + 0x1 + + + + + FLTCONF + Fault Confinement State + 4 + 2 + read-only + + + FLTCONF_0 + Error Active + 0 + + + FLTCONF_1 + Error Passive + 0x1 + + + FLTCONF_2 + Bus Off + #1x + + + + + TX + FlexCAN In Transmission + 6 + 1 + read-only + + + TX_0 + FlexCAN is not transmitting a message. + 0 + + + TX_1 + FlexCAN is transmitting a message. + 0x1 + + + + + IDLE + IDLE + 7 + 1 + read-only + + + IDLE_0 + No such occurrence. + 0 + + + IDLE_1 + CAN bus is now IDLE. + 0x1 + + + + + RXWRN + Rx Error Warning + 8 + 1 + read-only + + + RXWRN_0 + No such occurrence. + 0 + + + RXWRN_1 + RXERRCNT is greater than or equal to 96. + 0x1 + + + + + TXWRN + TX Error Warning + 9 + 1 + read-only + + + TXWRN_0 + No such occurrence. + 0 + + + TXWRN_1 + TXERRCNT is greater than or equal to 96. + 0x1 + + + + + STFERR + Stuffing Error + 10 + 1 + read-only + + + STFERR_0 + No such occurrence. + 0 + + + STFERR_1 + A Stuffing Error occurred since last read of this register. + 0x1 + + + + + FRMERR + Form Error + 11 + 1 + read-only + + + FRMERR_0 + No such occurrence. + 0 + + + FRMERR_1 + A Form Error occurred since last read of this register. + 0x1 + + + + + CRCERR + Cyclic Redundancy Check Error + 12 + 1 + read-only + + + CRCERR_0 + No such occurrence. + 0 + + + CRCERR_1 + A CRC error occurred since last read of this register. + 0x1 + + + + + ACKERR + Acknowledge Error + 13 + 1 + read-only + + + ACKERR_0 + No such occurrence. + 0 + + + ACKERR_1 + An ACK error occurred since last read of this register. + 0x1 + + + + + BIT0ERR + Bit0 Error + 14 + 1 + read-only + + + BIT0ERR_0 + No such occurrence. + 0 + + + BIT0ERR_1 + At least one bit sent as dominant is received as recessive. + 0x1 + + + + + BIT1ERR + Bit1 Error + 15 + 1 + read-only + + + BIT1ERR_0 + No such occurrence. + 0 + + + BIT1ERR_1 + At least one bit sent as recessive is received as dominant. + 0x1 + + + + + RWRNINT + Rx Warning Interrupt Flag + 16 + 1 + read-write + oneToClear + + + RWRNINT_0 + No such occurrence. + 0 + + + RWRNINT_1 + The Rx error counter transitioned from less than 96 to greater than or equal to 96. + 0x1 + + + + + TWRNINT + Tx Warning Interrupt Flag + 17 + 1 + read-write + oneToClear + + + TWRNINT_0 + No such occurrence. + 0 + + + TWRNINT_1 + The Tx error counter transitioned from less than 96 to greater than or equal to 96. + 0x1 + + + + + SYNCH + CAN Synchronization Status + 18 + 1 + read-only + + + SYNCH_0 + FlexCAN is not synchronized to the CAN bus. + 0 + + + SYNCH_1 + FlexCAN is synchronized to the CAN bus. + 0x1 + + + + + BOFFDONEINT + Bus Off Done Interrupt + 19 + 1 + read-write + oneToClear + + + BOFFDONEINT_0 + No such occurrence. + 0 + + + BOFFDONEINT_1 + FlexCAN module has completed Bus Off process. + 0x1 + + + + + ERRINT_FAST + Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set + 20 + 1 + read-write + oneToClear + + + ERRINT_FAST_0 + No such occurrence. + 0 + + + ERRINT_FAST_1 + Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set. + 0x1 + + + + + ERROVR + Error Overrun bit + 21 + 1 + read-write + oneToClear + + + ERROVR_0 + Overrun has not occurred. + 0 + + + ERROVR_1 + Overrun has occurred. + 0x1 + + + + + STFERR_FAST + Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set + 26 + 1 + read-only + + + STFERR_FAST_0 + No such occurrence. + 0 + + + STFERR_FAST_1 + A Stuffing Error occurred since last read of this register. + 0x1 + + + + + FRMERR_FAST + Form Error in the Data Phase of CAN FD frames with the BRS bit set + 27 + 1 + read-only + + + FRMERR_FAST_0 + No such occurrence. + 0 + + + FRMERR_FAST_1 + A Form Error occurred since last read of this register. + 0x1 + + + + + CRCERR_FAST + Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set + 28 + 1 + read-only + + + CRCERR_FAST_0 + No such occurrence. + 0 + + + CRCERR_FAST_1 + A CRC error occurred since last read of this register. + 0x1 + + + + + BIT0ERR_FAST + Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set + 30 + 1 + read-only + + + BIT0ERR_FAST_0 + No such occurrence. + 0 + + + BIT0ERR_FAST_1 + At least one bit sent as dominant is received as recessive. + 0x1 + + + + + BIT1ERR_FAST + Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set + 31 + 1 + read-only + + + BIT1ERR_FAST_0 + No such occurrence. + 0 + + + BIT1ERR_FAST_1 + At least one bit sent as recessive is received as dominant. + 0x1 + + + + + + + IMASK2 + Interrupt Masks 2 register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUF63TO32M + Buffer MB i Mask + 0 + 32 + read-write + + + + + IMASK1 + Interrupt Masks 1 register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUF31TO0M + Buffer MB i Mask + 0 + 32 + read-write + + + + + IFLAG2 + Interrupt Flags 2 register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + BUF63TO32I + Buffer MB i Interrupt + 0 + 32 + read-write + oneToClear + + + + + IFLAG1 + Interrupt Flags 1 register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUF0I + Buffer MB0 Interrupt Or Clear Legacy FIFO bit + 0 + 1 + read-write + oneToClear + + + BUF0I_0 + The corresponding buffer has no occurrence of successfully completed transmission or reception when CAN_MCR[RFEN]=0. + 0 + + + BUF0I_1 + The corresponding buffer has successfully completed transmission or reception when CAN_MCR[RFEN]=0. + 0x1 + + + + + BUF4TO1I + Buffer MB i Interrupt Or "reserved" + 1 + 4 + read-write + oneToClear + + + BUF5I + Buffer MB5 Interrupt Or "Frames available in Legacy Rx FIFO" + 5 + 1 + read-write + oneToClear + + + BUF5I_0 + No occurrence of MB5 completing transmission/reception when CAN_MCR[RFEN]=0, or of frame(s) available in the Legacy FIFO, when CAN_MCR[RFEN]=1 + 0 + + + BUF5I_1 + MB5 completed transmission/reception when CAN_MCR[RFEN]=0, or frame(s) available in the Legacy Rx FIFO when CAN_MCR[RFEN]=1. It generates a DMA request in case of CAN_MCR[RFEN] and CAN_MCR[DMA] are enabled. + 0x1 + + + + + BUF6I + Buffer MB6 Interrupt Or "Legacy Rx FIFO Warning" + 6 + 1 + read-write + oneToClear + + + BUF6I_0 + No occurrence of MB6 completing transmission/reception when CAN_MCR[RFEN]=0, or of Legacy Rx FIFO almost full when CAN_MCR[RFEN]=1 + 0 + + + BUF6I_1 + MB6 completed transmission/reception when CAN_MCR[RFEN]=0, or Legacy Rx FIFO almost full when CAN_MCR[RFEN]=1 + 0x1 + + + + + BUF7I + Buffer MB7 Interrupt Or "Legacy Rx FIFO Overflow" + 7 + 1 + read-write + oneToClear + + + BUF7I_0 + No occurrence of MB7 completing transmission/reception when CAN_MCR[RFEN]=0, or of Legacy Rx FIFO overflow when CAN_MCR[RFEN]=1 + 0 + + + BUF7I_1 + MB7 completed transmission/reception when CAN_MCR[RFEN]=0, or Legacy Rx FIFO overflow when CAN_MCR[RFEN]=1 + 0x1 + + + + + BUF31TO8I + Buffer MBi Interrupt + 8 + 24 + read-write + oneToClear + + + + + CTRL2 + Control 2 register + 0x34 + 32 + read-write + 0x800000 + 0xFFFFFFFF + + + TSTAMPCAP + Time Stamp Capture Point + 6 + 2 + read-write + + + TSTAMPCAP_0 + The high resolution time stamp capture is disabled + 0 + + + TSTAMPCAP_1 + The high resolution time stamp is captured in the end of the CAN frame + 0x1 + + + TSTAMPCAP_2 + The high resolution time stamp is captured in the start of the CAN frame + 0x2 + + + TSTAMPCAP_3 + The high resolution time stamp is captured in the start of frame for classical CAN frames and in res bit for CAN FD frames + 0x3 + + + + + MBTSBASE + Message Buffer Time Stamp Base + 8 + 2 + read-write + + + MBTSBASE_0 + Message Buffer Time Stamp base is CAN_TIMER + 0 + + + MBTSBASE_1 + Message Buffer Time Stamp base is lower 16-bits of high resolution timer + 0x1 + + + MBTSBASE_2 + Message Buffer Time Stamp base is upper 16-bits of high resolution timerT + 0x2 + + + + + EDFLTDIS + Edge Filter Disable + 11 + 1 + read-write + + + EDFLTDIS_0 + Edge Filter is enabled + 0 + + + EDFLTDIS_1 + Edge Filter is disabled + 0x1 + + + + + ISOCANFDEN + ISO CAN FD Enable + 12 + 1 + read-write + + + ISOCANFDEN_0 + FlexCAN operates using the non-ISO CAN FD protocol. + 0 + + + ISOCANFDEN_1 + FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1). + 0x1 + + + + + BTE + Bit Timing Expansion enable + 13 + 1 + read-write + + + BTE_0 + CAN Bit timing expansion is disabled. + 0 + + + BTE_1 + CAN bit timing expansion is enabled. + 0x1 + + + + + PREXCEN + Protocol Exception Enable + 14 + 1 + read-write + + + PREXCEN_0 + Protocol Exception is disabled. + 0 + + + PREXCEN_1 + Protocol Exception is enabled. + 0x1 + + + + + TIMER_SRC + Timer Source + 15 + 1 + read-write + + + TIMER_SRC_0 + The Free Running Timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus. + 0 + + + TIMER_SRC_1 + The Free Running Timer is clocked by an external time tick. The period can be either adjusted to be equal to the baud rate on the CAN bus, or a different value as required. See the device specific section for details about the external time tick. + 0x1 + + + + + EACEN + Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes + 16 + 1 + read-write + + + EACEN_0 + Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. + 0 + + + EACEN_1 + Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. + 0x1 + + + + + RRS + Remote Request Storing + 17 + 1 + read-write + + + RRS_0 + Remote Response Frame is generated. + 0 + + + RRS_1 + Remote Request Frame is stored. + 0x1 + + + + + MRP + Mailboxes Reception Priority + 18 + 1 + read-write + + + MRP_0 + Matching starts from Legacy Rx FIFO or Enhanced Rx FIFO and continues on Mailboxes. + 0 + + + MRP_1 + Matching starts from Mailboxes and continues on Legacy Rx FIFO or Enhanced Rx FIFO . + 0x1 + + + + + TASD + Tx Arbitration Start Delay + 19 + 5 + read-write + + + RFFN + Number Of Legacy Rx FIFO Filters + 24 + 4 + read-write + + + BOFFDONEMSK + Bus Off Done Interrupt Mask + 30 + 1 + read-write + + + BOFFDONEMSK_0 + Bus Off Done interrupt disabled. + 0 + + + BOFFDONEMSK_1 + Bus Off Done interrupt enabled. + 0x1 + + + + + ERRMSK_FAST + Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames + 31 + 1 + read-write + + + ERRMSK_FAST_0 + ERRINT_FAST Error interrupt disabled. + 0 + + + ERRMSK_FAST_1 + ERRINT_FAST Error interrupt enabled. + 0x1 + + + + + + + ESR2 + Error and Status 2 register + 0x38 + 32 + read-only + 0 + 0xFFFFFFFF + + + IMB + Inactive Mailbox + 13 + 1 + read-only + + + IMB_0 + If CAN_ESR2[VPS] is asserted, the CAN_ESR2[LPTM] is not an inactive Mailbox. + 0 + + + IMB_1 + If CAN_ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. + 0x1 + + + + + VPS + Valid Priority Status + 14 + 1 + read-only + + + VPS_0 + Contents of IMB and LPTM are invalid. + 0 + + + VPS_1 + Contents of IMB and LPTM are valid. + 0x1 + + + + + LPTM + Lowest Priority Tx Mailbox + 16 + 7 + read-only + + + + + CRCR + CRC Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXCRC + Transmitted CRC value + 0 + 15 + read-only + + + MBCRC + CRC Mailbox + 16 + 7 + read-only + + + + + RXFGMASK + Legacy Rx FIFO Global Mask register + 0x48 + 32 + read-write + 0 + 0 + + + FGM + Legacy Rx FIFO Global Mask Bits + 0 + 32 + read-write + + + + + RXFIR + Legacy Rx FIFO Information Register + 0x4C + 32 + read-only + 0 + 0 + + + IDHIT + Identifier Acceptance Filter Hit Indicator + 0 + 9 + read-only + + + + + CBT + CAN Bit Timing Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + EPSEG2 + Extended Phase Segment 2 + 0 + 5 + read-write + + + EPSEG1 + Extended Phase Segment 1 + 5 + 5 + read-write + + + EPROPSEG + Extended Propagation Segment + 10 + 6 + read-write + + + ERJW + Extended Resync Jump Width + 16 + 5 + read-write + + + EPRESDIV + Extended Prescaler Division Factor + 21 + 10 + read-write + + + BTF + Bit Timing Format Enable + 31 + 1 + read-write + + + BTF_0 + Extended bit time definitions disabled. + 0 + + + BTF_1 + Extended bit time definitions enabled. + 0x1 + + + + + + + CS0 + Message Buffer 0 CS Register + MB_SIZE + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB0_16B_CS + Message Buffer 0 CS Register + MB_SIZE + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB0_32B_CS + Message Buffer 0 CS Register + MB_SIZE + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB0_64B_CS + Message Buffer 0 CS Register + MB_SIZE + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB0_8B_CS + Message Buffer 0 CS Register + MB_SIZE + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID0 + Message Buffer 0 ID Register + MB_SIZE + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_16B_ID + Message Buffer 0 ID Register + MB_SIZE + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_32B_ID + Message Buffer 0 ID Register + MB_SIZE + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_64B_ID + Message Buffer 0 ID Register + MB_SIZE + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_8B_ID + Message Buffer 0 ID Register + MB_SIZE + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_16B_WORD0 + Message Buffer 0 WORD_16B Register + MB_SIZE + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_32B_WORD0 + Message Buffer 0 WORD_32B Register + MB_SIZE + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD0 + Message Buffer 0 WORD_64B Register + MB_SIZE + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_8B_WORD0 + Message Buffer 0 WORD_8B Register + MB_SIZE + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD00 + Message Buffer 0 WORD0 Register + MB_SIZE + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_16B_WORD1 + Message Buffer 0 WORD_16B Register + MB_SIZE + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_32B_WORD1 + Message Buffer 0 WORD_32B Register + MB_SIZE + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD1 + Message Buffer 0 WORD_64B Register + MB_SIZE + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_8B_WORD1 + Message Buffer 0 WORD_8B Register + MB_SIZE + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD10 + Message Buffer 0 WORD1 Register + MB_SIZE + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS1 + Message Buffer 1 CS Register + MB_SIZE + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB0_16B_WORD2 + Message Buffer 0 WORD_16B Register + MB_SIZE + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_32B_WORD2 + Message Buffer 0 WORD_32B Register + MB_SIZE + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD2 + Message Buffer 0 WORD_64B Register + MB_SIZE + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_8B_CS + Message Buffer 1 CS Register + MB_SIZE + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID1 + Message Buffer 1 ID Register + MB_SIZE + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_16B_WORD3 + Message Buffer 0 WORD_16B Register + MB_SIZE + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_32B_WORD3 + Message Buffer 0 WORD_32B Register + MB_SIZE + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD3 + Message Buffer 0 WORD_64B Register + MB_SIZE + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_8B_ID + Message Buffer 1 ID Register + MB_SIZE + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_32B_WORD4 + Message Buffer 0 WORD_32B Register + MB_SIZE + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD4 + Message Buffer 0 WORD_64B Register + MB_SIZE + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_16B_CS + Message Buffer 1 CS Register + MB_SIZE + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB1_8B_WORD0 + Message Buffer 1 WORD_8B Register + MB_SIZE + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD01 + Message Buffer 1 WORD0 Register + MB_SIZE + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_32B_WORD5 + Message Buffer 0 WORD_32B Register + MB_SIZE + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD5 + Message Buffer 0 WORD_64B Register + MB_SIZE + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_16B_ID + Message Buffer 1 ID Register + MB_SIZE + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_8B_WORD1 + Message Buffer 1 WORD_8B Register + MB_SIZE + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD11 + Message Buffer 1 WORD1 Register + MB_SIZE + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS2 + Message Buffer 2 CS Register + MB_SIZE + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB0_32B_WORD6 + Message Buffer 0 WORD_32B Register + MB_SIZE + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD6 + Message Buffer 0 WORD_64B Register + MB_SIZE + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_16B_WORD0 + Message Buffer 1 WORD_16B Register + MB_SIZE + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_8B_CS + Message Buffer 2 CS Register + MB_SIZE + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID2 + Message Buffer 2 ID Register + MB_SIZE + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_32B_WORD7 + Message Buffer 0 WORD_32B Register + MB_SIZE + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD7 + Message Buffer 0 WORD_64B Register + MB_SIZE + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_16B_WORD1 + Message Buffer 1 WORD_16B Register + MB_SIZE + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_8B_ID + Message Buffer 2 ID Register + MB_SIZE + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_64B_WORD8 + Message Buffer 0 WORD_64B Register + MB_SIZE + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_16B_WORD2 + Message Buffer 1 WORD_16B Register + MB_SIZE + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_32B_CS + Message Buffer 1 CS Register + MB_SIZE + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB2_8B_WORD0 + Message Buffer 2 WORD_8B Register + MB_SIZE + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD02 + Message Buffer 2 WORD0 Register + MB_SIZE + 0xA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD9 + Message Buffer 0 WORD_64B Register + MB_SIZE + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_16B_WORD3 + Message Buffer 1 WORD_16B Register + MB_SIZE + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_32B_ID + Message Buffer 1 ID Register + MB_SIZE + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB2_8B_WORD1 + Message Buffer 2 WORD_8B Register + MB_SIZE + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD12 + Message Buffer 2 WORD1 Register + MB_SIZE + 0xAC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS3 + Message Buffer 3 CS Register + MB_SIZE + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB0_64B_WORD10 + Message Buffer 0 WORD_64B Register + MB_SIZE + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_32B_WORD0 + Message Buffer 1 WORD_32B Register + MB_SIZE + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_16B_CS + Message Buffer 2 CS Register + MB_SIZE + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB3_8B_CS + Message Buffer 3 CS Register + MB_SIZE + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID3 + Message Buffer 3 ID Register + MB_SIZE + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_64B_WORD11 + Message Buffer 0 WORD_64B Register + MB_SIZE + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_32B_WORD1 + Message Buffer 1 WORD_32B Register + MB_SIZE + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_16B_ID + Message Buffer 2 ID Register + MB_SIZE + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB3_8B_ID + Message Buffer 3 ID Register + MB_SIZE + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_64B_WORD12 + Message Buffer 0 WORD_64B Register + MB_SIZE + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_32B_WORD2 + Message Buffer 1 WORD_32B Register + MB_SIZE + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_16B_WORD0 + Message Buffer 2 WORD_16B Register + MB_SIZE + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_8B_WORD0 + Message Buffer 3 WORD_8B Register + MB_SIZE + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD03 + Message Buffer 3 WORD0 Register + MB_SIZE + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB0_64B_WORD13 + Message Buffer 0 WORD_64B Register + MB_SIZE + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_32B_WORD3 + Message Buffer 1 WORD_32B Register + MB_SIZE + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_16B_WORD1 + Message Buffer 2 WORD_16B Register + MB_SIZE + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_8B_WORD1 + Message Buffer 3 WORD_8B Register + MB_SIZE + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD13 + Message Buffer 3 WORD1 Register + MB_SIZE + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS4 + Message Buffer 4 CS Register + MB_SIZE + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB0_64B_WORD14 + Message Buffer 0 WORD_64B Register + MB_SIZE + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_32B_WORD4 + Message Buffer 1 WORD_32B Register + MB_SIZE + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_16B_WORD2 + Message Buffer 2 WORD_16B Register + MB_SIZE + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_8B_CS + Message Buffer 4 CS Register + MB_SIZE + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID4 + Message Buffer 4 ID Register + MB_SIZE + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB0_64B_WORD15 + Message Buffer 0 WORD_64B Register + MB_SIZE + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_32B_WORD5 + Message Buffer 1 WORD_32B Register + MB_SIZE + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_16B_WORD3 + Message Buffer 2 WORD_16B Register + MB_SIZE + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_8B_ID + Message Buffer 4 ID Register + MB_SIZE + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_32B_WORD6 + Message Buffer 1 WORD_32B Register + MB_SIZE + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_64B_CS + Message Buffer 1 CS Register + MB_SIZE + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB3_16B_CS + Message Buffer 3 CS Register + MB_SIZE + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB4_8B_WORD0 + Message Buffer 4 WORD_8B Register + MB_SIZE + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD04 + Message Buffer 4 WORD0 Register + MB_SIZE + 0xC8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_32B_WORD7 + Message Buffer 1 WORD_32B Register + MB_SIZE + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_64B_ID + Message Buffer 1 ID Register + MB_SIZE + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB3_16B_ID + Message Buffer 3 ID Register + MB_SIZE + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB4_8B_WORD1 + Message Buffer 4 WORD_8B Register + MB_SIZE + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD14 + Message Buffer 4 WORD1 Register + MB_SIZE + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS5 + Message Buffer 5 CS Register + MB_SIZE + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB1_64B_WORD0 + Message Buffer 1 WORD_64B Register + MB_SIZE + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_CS + Message Buffer 2 CS Register + MB_SIZE + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB3_16B_WORD0 + Message Buffer 3 WORD_16B Register + MB_SIZE + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_8B_CS + Message Buffer 5 CS Register + MB_SIZE + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID5 + Message Buffer 5 ID Register + MB_SIZE + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_64B_WORD1 + Message Buffer 1 WORD_64B Register + MB_SIZE + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_ID + Message Buffer 2 ID Register + MB_SIZE + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB3_16B_WORD1 + Message Buffer 3 WORD_16B Register + MB_SIZE + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_8B_ID + Message Buffer 5 ID Register + MB_SIZE + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_64B_WORD2 + Message Buffer 1 WORD_64B Register + MB_SIZE + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_WORD0 + Message Buffer 2 WORD_32B Register + MB_SIZE + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_16B_WORD2 + Message Buffer 3 WORD_16B Register + MB_SIZE + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_8B_WORD0 + Message Buffer 5 WORD_8B Register + MB_SIZE + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD05 + Message Buffer 5 WORD0 Register + MB_SIZE + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_64B_WORD3 + Message Buffer 1 WORD_64B Register + MB_SIZE + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_WORD1 + Message Buffer 2 WORD_32B Register + MB_SIZE + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_16B_WORD3 + Message Buffer 3 WORD_16B Register + MB_SIZE + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_8B_WORD1 + Message Buffer 5 WORD_8B Register + MB_SIZE + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD15 + Message Buffer 5 WORD1 Register + MB_SIZE + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS6 + Message Buffer 6 CS Register + MB_SIZE + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB1_64B_WORD4 + Message Buffer 1 WORD_64B Register + MB_SIZE + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_WORD2 + Message Buffer 2 WORD_32B Register + MB_SIZE + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_16B_CS + Message Buffer 4 CS Register + MB_SIZE + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB6_8B_CS + Message Buffer 6 CS Register + MB_SIZE + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID6 + Message Buffer 6 ID Register + MB_SIZE + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_64B_WORD5 + Message Buffer 1 WORD_64B Register + MB_SIZE + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_WORD3 + Message Buffer 2 WORD_32B Register + MB_SIZE + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_16B_ID + Message Buffer 4 ID Register + MB_SIZE + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB6_8B_ID + Message Buffer 6 ID Register + MB_SIZE + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_64B_WORD6 + Message Buffer 1 WORD_64B Register + MB_SIZE + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_WORD4 + Message Buffer 2 WORD_32B Register + MB_SIZE + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_16B_WORD0 + Message Buffer 4 WORD_16B Register + MB_SIZE + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_8B_WORD0 + Message Buffer 6 WORD_8B Register + MB_SIZE + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD06 + Message Buffer 6 WORD0 Register + MB_SIZE + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_64B_WORD7 + Message Buffer 1 WORD_64B Register + MB_SIZE + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_WORD5 + Message Buffer 2 WORD_32B Register + MB_SIZE + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_16B_WORD1 + Message Buffer 4 WORD_16B Register + MB_SIZE + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_8B_WORD1 + Message Buffer 6 WORD_8B Register + MB_SIZE + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD16 + Message Buffer 6 WORD1 Register + MB_SIZE + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS7 + Message Buffer 7 CS Register + MB_SIZE + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB1_64B_WORD8 + Message Buffer 1 WORD_64B Register + MB_SIZE + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_WORD6 + Message Buffer 2 WORD_32B Register + MB_SIZE + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_16B_WORD2 + Message Buffer 4 WORD_16B Register + MB_SIZE + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_8B_CS + Message Buffer 7 CS Register + MB_SIZE + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID7 + Message Buffer 7 ID Register + MB_SIZE + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_64B_WORD9 + Message Buffer 1 WORD_64B Register + MB_SIZE + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_32B_WORD7 + Message Buffer 2 WORD_32B Register + MB_SIZE + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_16B_WORD3 + Message Buffer 4 WORD_16B Register + MB_SIZE + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_8B_ID + Message Buffer 7 ID Register + MB_SIZE + 0xF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_64B_WORD10 + Message Buffer 1 WORD_64B Register + MB_SIZE + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_32B_CS + Message Buffer 3 CS Register + MB_SIZE + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB5_16B_CS + Message Buffer 5 CS Register + MB_SIZE + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB7_8B_WORD0 + Message Buffer 7 WORD_8B Register + MB_SIZE + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD07 + Message Buffer 7 WORD0 Register + MB_SIZE + 0xF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_64B_WORD11 + Message Buffer 1 WORD_64B Register + MB_SIZE + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_32B_ID + Message Buffer 3 ID Register + MB_SIZE + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB5_16B_ID + Message Buffer 5 ID Register + MB_SIZE + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB7_8B_WORD1 + Message Buffer 7 WORD_8B Register + MB_SIZE + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD17 + Message Buffer 7 WORD1 Register + MB_SIZE + 0xFC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS8 + Message Buffer 8 CS Register + MB_SIZE + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB1_64B_WORD12 + Message Buffer 1 WORD_64B Register + MB_SIZE + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_32B_WORD0 + Message Buffer 3 WORD_32B Register + MB_SIZE + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_16B_WORD0 + Message Buffer 5 WORD_16B Register + MB_SIZE + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_8B_CS + Message Buffer 8 CS Register + MB_SIZE + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID8 + Message Buffer 8 ID Register + MB_SIZE + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_64B_WORD13 + Message Buffer 1 WORD_64B Register + MB_SIZE + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_32B_WORD1 + Message Buffer 3 WORD_32B Register + MB_SIZE + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_16B_WORD1 + Message Buffer 5 WORD_16B Register + MB_SIZE + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_8B_ID + Message Buffer 8 ID Register + MB_SIZE + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB1_64B_WORD14 + Message Buffer 1 WORD_64B Register + MB_SIZE + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_32B_WORD2 + Message Buffer 3 WORD_32B Register + MB_SIZE + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_16B_WORD2 + Message Buffer 5 WORD_16B Register + MB_SIZE + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_8B_WORD0 + Message Buffer 8 WORD_8B Register + MB_SIZE + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD08 + Message Buffer 8 WORD0 Register + MB_SIZE + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB1_64B_WORD15 + Message Buffer 1 WORD_64B Register + MB_SIZE + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_32B_WORD3 + Message Buffer 3 WORD_32B Register + MB_SIZE + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_16B_WORD3 + Message Buffer 5 WORD_16B Register + MB_SIZE + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_8B_WORD1 + Message Buffer 8 WORD_8B Register + MB_SIZE + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD18 + Message Buffer 8 WORD1 Register + MB_SIZE + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS9 + Message Buffer 9 CS Register + MB_SIZE + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB2_64B_CS + Message Buffer 2 CS Register + MB_SIZE + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB3_32B_WORD4 + Message Buffer 3 WORD_32B Register + MB_SIZE + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_16B_CS + Message Buffer 6 CS Register + MB_SIZE + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB9_8B_CS + Message Buffer 9 CS Register + MB_SIZE + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID9 + Message Buffer 9 ID Register + MB_SIZE + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB2_64B_ID + Message Buffer 2 ID Register + MB_SIZE + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB3_32B_WORD5 + Message Buffer 3 WORD_32B Register + MB_SIZE + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_16B_ID + Message Buffer 6 ID Register + MB_SIZE + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB9_8B_ID + Message Buffer 9 ID Register + MB_SIZE + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB2_64B_WORD0 + Message Buffer 2 WORD_64B Register + MB_SIZE + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_32B_WORD6 + Message Buffer 3 WORD_32B Register + MB_SIZE + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_16B_WORD0 + Message Buffer 6 WORD_16B Register + MB_SIZE + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_8B_WORD0 + Message Buffer 9 WORD_8B Register + MB_SIZE + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD09 + Message Buffer 9 WORD0 Register + MB_SIZE + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_64B_WORD1 + Message Buffer 2 WORD_64B Register + MB_SIZE + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_32B_WORD7 + Message Buffer 3 WORD_32B Register + MB_SIZE + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_16B_WORD1 + Message Buffer 6 WORD_16B Register + MB_SIZE + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_8B_WORD1 + Message Buffer 9 WORD_8B Register + MB_SIZE + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD19 + Message Buffer 9 WORD1 Register + MB_SIZE + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS10 + Message Buffer 10 CS Register + MB_SIZE + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB10_8B_CS + Message Buffer 10 CS Register + MB_SIZE + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB2_64B_WORD2 + Message Buffer 2 WORD_64B Register + MB_SIZE + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_CS + Message Buffer 4 CS Register + MB_SIZE + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB6_16B_WORD2 + Message Buffer 6 WORD_16B Register + MB_SIZE + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID10 + Message Buffer 10 ID Register + MB_SIZE + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_8B_ID + Message Buffer 10 ID Register + MB_SIZE + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB2_64B_WORD3 + Message Buffer 2 WORD_64B Register + MB_SIZE + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_ID + Message Buffer 4 ID Register + MB_SIZE + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB6_16B_WORD3 + Message Buffer 6 WORD_16B Register + MB_SIZE + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB10_8B_WORD0 + Message Buffer 10 WORD_8B Register + MB_SIZE + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_64B_WORD4 + Message Buffer 2 WORD_64B Register + MB_SIZE + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_WORD0 + Message Buffer 4 WORD_32B Register + MB_SIZE + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_16B_CS + Message Buffer 7 CS Register + MB_SIZE + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + WORD010 + Message Buffer 10 WORD0 Register + MB_SIZE + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB10_8B_WORD1 + Message Buffer 10 WORD_8B Register + MB_SIZE + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_64B_WORD5 + Message Buffer 2 WORD_64B Register + MB_SIZE + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_WORD1 + Message Buffer 4 WORD_32B Register + MB_SIZE + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_16B_ID + Message Buffer 7 ID Register + MB_SIZE + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD110 + Message Buffer 10 WORD1 Register + MB_SIZE + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS11 + Message Buffer 11 CS Register + MB_SIZE + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB11_8B_CS + Message Buffer 11 CS Register + MB_SIZE + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB2_64B_WORD6 + Message Buffer 2 WORD_64B Register + MB_SIZE + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_WORD2 + Message Buffer 4 WORD_32B Register + MB_SIZE + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_16B_WORD0 + Message Buffer 7 WORD_16B Register + MB_SIZE + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID11 + Message Buffer 11 ID Register + MB_SIZE + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB11_8B_ID + Message Buffer 11 ID Register + MB_SIZE + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB2_64B_WORD7 + Message Buffer 2 WORD_64B Register + MB_SIZE + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_WORD3 + Message Buffer 4 WORD_32B Register + MB_SIZE + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_16B_WORD1 + Message Buffer 7 WORD_16B Register + MB_SIZE + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_8B_WORD0 + Message Buffer 11 WORD_8B Register + MB_SIZE + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_64B_WORD8 + Message Buffer 2 WORD_64B Register + MB_SIZE + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_WORD4 + Message Buffer 4 WORD_32B Register + MB_SIZE + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_16B_WORD2 + Message Buffer 7 WORD_16B Register + MB_SIZE + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD011 + Message Buffer 11 WORD0 Register + MB_SIZE + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_8B_WORD1 + Message Buffer 11 WORD_8B Register + MB_SIZE + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_64B_WORD9 + Message Buffer 2 WORD_64B Register + MB_SIZE + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_WORD5 + Message Buffer 4 WORD_32B Register + MB_SIZE + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_16B_WORD3 + Message Buffer 7 WORD_16B Register + MB_SIZE + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD111 + Message Buffer 11 WORD1 Register + MB_SIZE + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS12 + Message Buffer 12 CS Register + MB_SIZE + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB12_8B_CS + Message Buffer 12 CS Register + MB_SIZE + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB2_64B_WORD10 + Message Buffer 2 WORD_64B Register + MB_SIZE + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_WORD6 + Message Buffer 4 WORD_32B Register + MB_SIZE + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_16B_CS + Message Buffer 8 CS Register + MB_SIZE + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID12 + Message Buffer 12 ID Register + MB_SIZE + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_8B_ID + Message Buffer 12 ID Register + MB_SIZE + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB2_64B_WORD11 + Message Buffer 2 WORD_64B Register + MB_SIZE + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_32B_WORD7 + Message Buffer 4 WORD_32B Register + MB_SIZE + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_16B_ID + Message Buffer 8 ID Register + MB_SIZE + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_8B_WORD0 + Message Buffer 12 WORD_8B Register + MB_SIZE + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_64B_WORD12 + Message Buffer 2 WORD_64B Register + MB_SIZE + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_32B_CS + Message Buffer 5 CS Register + MB_SIZE + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB8_16B_WORD0 + Message Buffer 8 WORD_16B Register + MB_SIZE + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD012 + Message Buffer 12 WORD0 Register + MB_SIZE + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB12_8B_WORD1 + Message Buffer 12 WORD_8B Register + MB_SIZE + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB2_64B_WORD13 + Message Buffer 2 WORD_64B Register + MB_SIZE + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_32B_ID + Message Buffer 5 ID Register + MB_SIZE + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB8_16B_WORD1 + Message Buffer 8 WORD_16B Register + MB_SIZE + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD112 + Message Buffer 12 WORD1 Register + MB_SIZE + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS13 + Message Buffer 13 CS Register + MB_SIZE + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB13_8B_CS + Message Buffer 13 CS Register + MB_SIZE + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB2_64B_WORD14 + Message Buffer 2 WORD_64B Register + MB_SIZE + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_32B_WORD0 + Message Buffer 5 WORD_32B Register + MB_SIZE + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_16B_WORD2 + Message Buffer 8 WORD_16B Register + MB_SIZE + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID13 + Message Buffer 13 ID Register + MB_SIZE + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB13_8B_ID + Message Buffer 13 ID Register + MB_SIZE + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB2_64B_WORD15 + Message Buffer 2 WORD_64B Register + MB_SIZE + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_32B_WORD1 + Message Buffer 5 WORD_32B Register + MB_SIZE + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_16B_WORD3 + Message Buffer 8 WORD_16B Register + MB_SIZE + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_8B_WORD0 + Message Buffer 13 WORD_8B Register + MB_SIZE + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_CS + Message Buffer 3 CS Register + MB_SIZE + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB5_32B_WORD2 + Message Buffer 5 WORD_32B Register + MB_SIZE + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_16B_CS + Message Buffer 9 CS Register + MB_SIZE + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + WORD013 + Message Buffer 13 WORD0 Register + MB_SIZE + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_8B_WORD1 + Message Buffer 13 WORD_8B Register + MB_SIZE + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_ID + Message Buffer 3 ID Register + MB_SIZE + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB5_32B_WORD3 + Message Buffer 5 WORD_32B Register + MB_SIZE + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_16B_ID + Message Buffer 9 ID Register + MB_SIZE + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD113 + Message Buffer 13 WORD1 Register + MB_SIZE + 0x15C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS14 + Message Buffer 14 CS Register + MB_SIZE + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB14_8B_CS + Message Buffer 14 CS Register + MB_SIZE + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB3_64B_WORD0 + Message Buffer 3 WORD_64B Register + MB_SIZE + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_32B_WORD4 + Message Buffer 5 WORD_32B Register + MB_SIZE + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_16B_WORD0 + Message Buffer 9 WORD_16B Register + MB_SIZE + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID14 + Message Buffer 14 ID Register + MB_SIZE + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB14_8B_ID + Message Buffer 14 ID Register + MB_SIZE + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB3_64B_WORD1 + Message Buffer 3 WORD_64B Register + MB_SIZE + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_32B_WORD5 + Message Buffer 5 WORD_32B Register + MB_SIZE + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_16B_WORD1 + Message Buffer 9 WORD_16B Register + MB_SIZE + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB14_8B_WORD0 + Message Buffer 14 WORD_8B Register + MB_SIZE + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_WORD2 + Message Buffer 3 WORD_64B Register + MB_SIZE + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_32B_WORD6 + Message Buffer 5 WORD_32B Register + MB_SIZE + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_16B_WORD2 + Message Buffer 9 WORD_16B Register + MB_SIZE + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD014 + Message Buffer 14 WORD0 Register + MB_SIZE + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB14_8B_WORD1 + Message Buffer 14 WORD_8B Register + MB_SIZE + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_WORD3 + Message Buffer 3 WORD_64B Register + MB_SIZE + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_32B_WORD7 + Message Buffer 5 WORD_32B Register + MB_SIZE + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_16B_WORD3 + Message Buffer 9 WORD_16B Register + MB_SIZE + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD114 + Message Buffer 14 WORD1 Register + MB_SIZE + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS15 + Message Buffer 15 CS Register + MB_SIZE + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB10_16B_CS + Message Buffer 10 CS Register + MB_SIZE + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB15_8B_CS + Message Buffer 15 CS Register + MB_SIZE + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB3_64B_WORD4 + Message Buffer 3 WORD_64B Register + MB_SIZE + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_CS + Message Buffer 6 CS Register + MB_SIZE + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID15 + Message Buffer 15 ID Register + MB_SIZE + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_16B_ID + Message Buffer 10 ID Register + MB_SIZE + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB15_8B_ID + Message Buffer 15 ID Register + MB_SIZE + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB3_64B_WORD5 + Message Buffer 3 WORD_64B Register + MB_SIZE + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_ID + Message Buffer 6 ID Register + MB_SIZE + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_16B_WORD0 + Message Buffer 10 WORD_16B Register + MB_SIZE + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB15_8B_WORD0 + Message Buffer 15 WORD_8B Register + MB_SIZE + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_WORD6 + Message Buffer 3 WORD_64B Register + MB_SIZE + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_WORD0 + Message Buffer 6 WORD_32B Register + MB_SIZE + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD015 + Message Buffer 15 WORD0 Register + MB_SIZE + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB10_16B_WORD1 + Message Buffer 10 WORD_16B Register + MB_SIZE + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB15_8B_WORD1 + Message Buffer 15 WORD_8B Register + MB_SIZE + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_WORD7 + Message Buffer 3 WORD_64B Register + MB_SIZE + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_WORD1 + Message Buffer 6 WORD_32B Register + MB_SIZE + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD115 + Message Buffer 15 WORD1 Register + MB_SIZE + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS16 + Message Buffer 16 CS Register + MB_SIZE + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB10_16B_WORD2 + Message Buffer 10 WORD_16B Register + MB_SIZE + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB16_8B_CS + Message Buffer 16 CS Register + MB_SIZE + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB3_64B_WORD8 + Message Buffer 3 WORD_64B Register + MB_SIZE + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_WORD2 + Message Buffer 6 WORD_32B Register + MB_SIZE + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID16 + Message Buffer 16 ID Register + MB_SIZE + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_16B_WORD3 + Message Buffer 10 WORD_16B Register + MB_SIZE + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB16_8B_ID + Message Buffer 16 ID Register + MB_SIZE + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB3_64B_WORD9 + Message Buffer 3 WORD_64B Register + MB_SIZE + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_WORD3 + Message Buffer 6 WORD_32B Register + MB_SIZE + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_16B_CS + Message Buffer 11 CS Register + MB_SIZE + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB16_8B_WORD0 + Message Buffer 16 WORD_8B Register + MB_SIZE + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_WORD10 + Message Buffer 3 WORD_64B Register + MB_SIZE + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_WORD4 + Message Buffer 6 WORD_32B Register + MB_SIZE + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD016 + Message Buffer 16 WORD0 Register + MB_SIZE + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_16B_ID + Message Buffer 11 ID Register + MB_SIZE + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB16_8B_WORD1 + Message Buffer 16 WORD_8B Register + MB_SIZE + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_WORD11 + Message Buffer 3 WORD_64B Register + MB_SIZE + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_WORD5 + Message Buffer 6 WORD_32B Register + MB_SIZE + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD116 + Message Buffer 16 WORD1 Register + MB_SIZE + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS17 + Message Buffer 17 CS Register + MB_SIZE + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB11_16B_WORD0 + Message Buffer 11 WORD_16B Register + MB_SIZE + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_8B_CS + Message Buffer 17 CS Register + MB_SIZE + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB3_64B_WORD12 + Message Buffer 3 WORD_64B Register + MB_SIZE + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_WORD6 + Message Buffer 6 WORD_32B Register + MB_SIZE + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID17 + Message Buffer 17 ID Register + MB_SIZE + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB11_16B_WORD1 + Message Buffer 11 WORD_16B Register + MB_SIZE + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_8B_ID + Message Buffer 17 ID Register + MB_SIZE + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB3_64B_WORD13 + Message Buffer 3 WORD_64B Register + MB_SIZE + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_32B_WORD7 + Message Buffer 6 WORD_32B Register + MB_SIZE + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_16B_WORD2 + Message Buffer 11 WORD_16B Register + MB_SIZE + 0x198 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_8B_WORD0 + Message Buffer 17 WORD_8B Register + MB_SIZE + 0x198 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_WORD14 + Message Buffer 3 WORD_64B Register + MB_SIZE + 0x198 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_32B_CS + Message Buffer 7 CS Register + MB_SIZE + 0x198 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + WORD017 + Message Buffer 17 WORD0 Register + MB_SIZE + 0x198 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_16B_WORD3 + Message Buffer 11 WORD_16B Register + MB_SIZE + 0x19C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_8B_WORD1 + Message Buffer 17 WORD_8B Register + MB_SIZE + 0x19C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB3_64B_WORD15 + Message Buffer 3 WORD_64B Register + MB_SIZE + 0x19C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_32B_ID + Message Buffer 7 ID Register + MB_SIZE + 0x19C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD117 + Message Buffer 17 WORD1 Register + MB_SIZE + 0x19C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS18 + Message Buffer 18 CS Register + MB_SIZE + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB12_16B_CS + Message Buffer 12 CS Register + MB_SIZE + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB18_8B_CS + Message Buffer 18 CS Register + MB_SIZE + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB4_64B_CS + Message Buffer 4 CS Register + MB_SIZE + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB7_32B_WORD0 + Message Buffer 7 WORD_32B Register + MB_SIZE + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID18 + Message Buffer 18 ID Register + MB_SIZE + 0x1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_16B_ID + Message Buffer 12 ID Register + MB_SIZE + 0x1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB18_8B_ID + Message Buffer 18 ID Register + MB_SIZE + 0x1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB4_64B_ID + Message Buffer 4 ID Register + MB_SIZE + 0x1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB7_32B_WORD1 + Message Buffer 7 WORD_32B Register + MB_SIZE + 0x1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB12_16B_WORD0 + Message Buffer 12 WORD_16B Register + MB_SIZE + 0x1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_8B_WORD0 + Message Buffer 18 WORD_8B Register + MB_SIZE + 0x1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_64B_WORD0 + Message Buffer 4 WORD_64B Register + MB_SIZE + 0x1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_32B_WORD2 + Message Buffer 7 WORD_32B Register + MB_SIZE + 0x1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD018 + Message Buffer 18 WORD0 Register + MB_SIZE + 0x1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB12_16B_WORD1 + Message Buffer 12 WORD_16B Register + MB_SIZE + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_8B_WORD1 + Message Buffer 18 WORD_8B Register + MB_SIZE + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_64B_WORD1 + Message Buffer 4 WORD_64B Register + MB_SIZE + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_32B_WORD3 + Message Buffer 7 WORD_32B Register + MB_SIZE + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD118 + Message Buffer 18 WORD1 Register + MB_SIZE + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS19 + Message Buffer 19 CS Register + MB_SIZE + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB12_16B_WORD2 + Message Buffer 12 WORD_16B Register + MB_SIZE + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_8B_CS + Message Buffer 19 CS Register + MB_SIZE + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB4_64B_WORD2 + Message Buffer 4 WORD_64B Register + MB_SIZE + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_32B_WORD4 + Message Buffer 7 WORD_32B Register + MB_SIZE + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID19 + Message Buffer 19 ID Register + MB_SIZE + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_16B_WORD3 + Message Buffer 12 WORD_16B Register + MB_SIZE + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_8B_ID + Message Buffer 19 ID Register + MB_SIZE + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB4_64B_WORD3 + Message Buffer 4 WORD_64B Register + MB_SIZE + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_32B_WORD5 + Message Buffer 7 WORD_32B Register + MB_SIZE + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_16B_CS + Message Buffer 13 CS Register + MB_SIZE + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB19_8B_WORD0 + Message Buffer 19 WORD_8B Register + MB_SIZE + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_64B_WORD4 + Message Buffer 4 WORD_64B Register + MB_SIZE + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_32B_WORD6 + Message Buffer 7 WORD_32B Register + MB_SIZE + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD019 + Message Buffer 19 WORD0 Register + MB_SIZE + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_16B_ID + Message Buffer 13 ID Register + MB_SIZE + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB19_8B_WORD1 + Message Buffer 19 WORD_8B Register + MB_SIZE + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_64B_WORD5 + Message Buffer 4 WORD_64B Register + MB_SIZE + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_32B_WORD7 + Message Buffer 7 WORD_32B Register + MB_SIZE + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD119 + Message Buffer 19 WORD1 Register + MB_SIZE + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS20 + Message Buffer 20 CS Register + MB_SIZE + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB13_16B_WORD0 + Message Buffer 13 WORD_16B Register + MB_SIZE + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_8B_CS + Message Buffer 20 CS Register + MB_SIZE + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB4_64B_WORD6 + Message Buffer 4 WORD_64B Register + MB_SIZE + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_CS + Message Buffer 8 CS Register + MB_SIZE + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID20 + Message Buffer 20 ID Register + MB_SIZE + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB13_16B_WORD1 + Message Buffer 13 WORD_16B Register + MB_SIZE + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_8B_ID + Message Buffer 20 ID Register + MB_SIZE + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB4_64B_WORD7 + Message Buffer 4 WORD_64B Register + MB_SIZE + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_ID + Message Buffer 8 ID Register + MB_SIZE + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB13_16B_WORD2 + Message Buffer 13 WORD_16B Register + MB_SIZE + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_8B_WORD0 + Message Buffer 20 WORD_8B Register + MB_SIZE + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_64B_WORD8 + Message Buffer 4 WORD_64B Register + MB_SIZE + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_WORD0 + Message Buffer 8 WORD_32B Register + MB_SIZE + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD020 + Message Buffer 20 WORD0 Register + MB_SIZE + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_16B_WORD3 + Message Buffer 13 WORD_16B Register + MB_SIZE + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_8B_WORD1 + Message Buffer 20 WORD_8B Register + MB_SIZE + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_64B_WORD9 + Message Buffer 4 WORD_64B Register + MB_SIZE + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_WORD1 + Message Buffer 8 WORD_32B Register + MB_SIZE + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD120 + Message Buffer 20 WORD1 Register + MB_SIZE + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS21 + Message Buffer 21 CS Register + MB_SIZE + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB14_16B_CS + Message Buffer 14 CS Register + MB_SIZE + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB21_8B_CS + Message Buffer 21 CS Register + MB_SIZE + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB4_64B_WORD10 + Message Buffer 4 WORD_64B Register + MB_SIZE + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_WORD2 + Message Buffer 8 WORD_32B Register + MB_SIZE + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID21 + Message Buffer 21 ID Register + MB_SIZE + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB14_16B_ID + Message Buffer 14 ID Register + MB_SIZE + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB21_8B_ID + Message Buffer 21 ID Register + MB_SIZE + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB4_64B_WORD11 + Message Buffer 4 WORD_64B Register + MB_SIZE + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_WORD3 + Message Buffer 8 WORD_32B Register + MB_SIZE + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB14_16B_WORD0 + Message Buffer 14 WORD_16B Register + MB_SIZE + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB21_8B_WORD0 + Message Buffer 21 WORD_8B Register + MB_SIZE + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_64B_WORD12 + Message Buffer 4 WORD_64B Register + MB_SIZE + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_WORD4 + Message Buffer 8 WORD_32B Register + MB_SIZE + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD021 + Message Buffer 21 WORD0 Register + MB_SIZE + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB14_16B_WORD1 + Message Buffer 14 WORD_16B Register + MB_SIZE + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB21_8B_WORD1 + Message Buffer 21 WORD_8B Register + MB_SIZE + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB4_64B_WORD13 + Message Buffer 4 WORD_64B Register + MB_SIZE + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_WORD5 + Message Buffer 8 WORD_32B Register + MB_SIZE + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD121 + Message Buffer 21 WORD1 Register + MB_SIZE + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS22 + Message Buffer 22 CS Register + MB_SIZE + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB14_16B_WORD2 + Message Buffer 14 WORD_16B Register + MB_SIZE + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_8B_CS + Message Buffer 22 CS Register + MB_SIZE + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB4_64B_WORD14 + Message Buffer 4 WORD_64B Register + MB_SIZE + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_WORD6 + Message Buffer 8 WORD_32B Register + MB_SIZE + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID22 + Message Buffer 22 ID Register + MB_SIZE + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB14_16B_WORD3 + Message Buffer 14 WORD_16B Register + MB_SIZE + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_8B_ID + Message Buffer 22 ID Register + MB_SIZE + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB4_64B_WORD15 + Message Buffer 4 WORD_64B Register + MB_SIZE + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_32B_WORD7 + Message Buffer 8 WORD_32B Register + MB_SIZE + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB15_16B_CS + Message Buffer 15 CS Register + MB_SIZE + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB22_8B_WORD0 + Message Buffer 22 WORD_8B Register + MB_SIZE + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_CS + Message Buffer 5 CS Register + MB_SIZE + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB9_32B_CS + Message Buffer 9 CS Register + MB_SIZE + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + WORD022 + Message Buffer 22 WORD0 Register + MB_SIZE + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB15_16B_ID + Message Buffer 15 ID Register + MB_SIZE + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB22_8B_WORD1 + Message Buffer 22 WORD_8B Register + MB_SIZE + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_ID + Message Buffer 5 ID Register + MB_SIZE + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB9_32B_ID + Message Buffer 9 ID Register + MB_SIZE + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD122 + Message Buffer 22 WORD1 Register + MB_SIZE + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS23 + Message Buffer 23 CS Register + MB_SIZE + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB15_16B_WORD0 + Message Buffer 15 WORD_16B Register + MB_SIZE + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_8B_CS + Message Buffer 23 CS Register + MB_SIZE + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB5_64B_WORD0 + Message Buffer 5 WORD_64B Register + MB_SIZE + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_32B_WORD0 + Message Buffer 9 WORD_32B Register + MB_SIZE + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID23 + Message Buffer 23 ID Register + MB_SIZE + 0x1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB15_16B_WORD1 + Message Buffer 15 WORD_16B Register + MB_SIZE + 0x1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_8B_ID + Message Buffer 23 ID Register + MB_SIZE + 0x1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB5_64B_WORD1 + Message Buffer 5 WORD_64B Register + MB_SIZE + 0x1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_32B_WORD1 + Message Buffer 9 WORD_32B Register + MB_SIZE + 0x1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB15_16B_WORD2 + Message Buffer 15 WORD_16B Register + MB_SIZE + 0x1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_8B_WORD0 + Message Buffer 23 WORD_8B Register + MB_SIZE + 0x1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_WORD2 + Message Buffer 5 WORD_64B Register + MB_SIZE + 0x1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_32B_WORD2 + Message Buffer 9 WORD_32B Register + MB_SIZE + 0x1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD023 + Message Buffer 23 WORD0 Register + MB_SIZE + 0x1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB15_16B_WORD3 + Message Buffer 15 WORD_16B Register + MB_SIZE + 0x1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_8B_WORD1 + Message Buffer 23 WORD_8B Register + MB_SIZE + 0x1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_WORD3 + Message Buffer 5 WORD_64B Register + MB_SIZE + 0x1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_32B_WORD3 + Message Buffer 9 WORD_32B Register + MB_SIZE + 0x1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD123 + Message Buffer 23 WORD1 Register + MB_SIZE + 0x1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS24 + Message Buffer 24 CS Register + MB_SIZE + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB16_16B_CS + Message Buffer 16 CS Register + MB_SIZE + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB24_8B_CS + Message Buffer 24 CS Register + MB_SIZE + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB5_64B_WORD4 + Message Buffer 5 WORD_64B Register + MB_SIZE + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_32B_WORD4 + Message Buffer 9 WORD_32B Register + MB_SIZE + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID24 + Message Buffer 24 ID Register + MB_SIZE + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB16_16B_ID + Message Buffer 16 ID Register + MB_SIZE + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB24_8B_ID + Message Buffer 24 ID Register + MB_SIZE + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB5_64B_WORD5 + Message Buffer 5 WORD_64B Register + MB_SIZE + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_32B_WORD5 + Message Buffer 9 WORD_32B Register + MB_SIZE + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB16_16B_WORD0 + Message Buffer 16 WORD_16B Register + MB_SIZE + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB24_8B_WORD0 + Message Buffer 24 WORD_8B Register + MB_SIZE + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_WORD6 + Message Buffer 5 WORD_64B Register + MB_SIZE + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_32B_WORD6 + Message Buffer 9 WORD_32B Register + MB_SIZE + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD024 + Message Buffer 24 WORD0 Register + MB_SIZE + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB16_16B_WORD1 + Message Buffer 16 WORD_16B Register + MB_SIZE + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB24_8B_WORD1 + Message Buffer 24 WORD_8B Register + MB_SIZE + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_WORD7 + Message Buffer 5 WORD_64B Register + MB_SIZE + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_32B_WORD7 + Message Buffer 9 WORD_32B Register + MB_SIZE + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD124 + Message Buffer 24 WORD1 Register + MB_SIZE + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS25 + Message Buffer 25 CS Register + MB_SIZE + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB10_32B_CS + Message Buffer 10 CS Register + MB_SIZE + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB16_16B_WORD2 + Message Buffer 16 WORD_16B Register + MB_SIZE + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB25_8B_CS + Message Buffer 25 CS Register + MB_SIZE + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB5_64B_WORD8 + Message Buffer 5 WORD_64B Register + MB_SIZE + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID25 + Message Buffer 25 ID Register + MB_SIZE + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_32B_ID + Message Buffer 10 ID Register + MB_SIZE + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB16_16B_WORD3 + Message Buffer 16 WORD_16B Register + MB_SIZE + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB25_8B_ID + Message Buffer 25 ID Register + MB_SIZE + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB5_64B_WORD9 + Message Buffer 5 WORD_64B Register + MB_SIZE + 0x214 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB10_32B_WORD0 + Message Buffer 10 WORD_32B Register + MB_SIZE + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_16B_CS + Message Buffer 17 CS Register + MB_SIZE + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB25_8B_WORD0 + Message Buffer 25 WORD_8B Register + MB_SIZE + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_WORD10 + Message Buffer 5 WORD_64B Register + MB_SIZE + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD025 + Message Buffer 25 WORD0 Register + MB_SIZE + 0x218 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB10_32B_WORD1 + Message Buffer 10 WORD_32B Register + MB_SIZE + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_16B_ID + Message Buffer 17 ID Register + MB_SIZE + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB25_8B_WORD1 + Message Buffer 25 WORD_8B Register + MB_SIZE + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_WORD11 + Message Buffer 5 WORD_64B Register + MB_SIZE + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD125 + Message Buffer 25 WORD1 Register + MB_SIZE + 0x21C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS26 + Message Buffer 26 CS Register + MB_SIZE + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB10_32B_WORD2 + Message Buffer 10 WORD_32B Register + MB_SIZE + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_16B_WORD0 + Message Buffer 17 WORD_16B Register + MB_SIZE + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB26_8B_CS + Message Buffer 26 CS Register + MB_SIZE + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB5_64B_WORD12 + Message Buffer 5 WORD_64B Register + MB_SIZE + 0x220 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID26 + Message Buffer 26 ID Register + MB_SIZE + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_32B_WORD3 + Message Buffer 10 WORD_32B Register + MB_SIZE + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_16B_WORD1 + Message Buffer 17 WORD_16B Register + MB_SIZE + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB26_8B_ID + Message Buffer 26 ID Register + MB_SIZE + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB5_64B_WORD13 + Message Buffer 5 WORD_64B Register + MB_SIZE + 0x224 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB10_32B_WORD4 + Message Buffer 10 WORD_32B Register + MB_SIZE + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_16B_WORD2 + Message Buffer 17 WORD_16B Register + MB_SIZE + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB26_8B_WORD0 + Message Buffer 26 WORD_8B Register + MB_SIZE + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_WORD14 + Message Buffer 5 WORD_64B Register + MB_SIZE + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD026 + Message Buffer 26 WORD0 Register + MB_SIZE + 0x228 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB10_32B_WORD5 + Message Buffer 10 WORD_32B Register + MB_SIZE + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_16B_WORD3 + Message Buffer 17 WORD_16B Register + MB_SIZE + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB26_8B_WORD1 + Message Buffer 26 WORD_8B Register + MB_SIZE + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB5_64B_WORD15 + Message Buffer 5 WORD_64B Register + MB_SIZE + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD126 + Message Buffer 26 WORD1 Register + MB_SIZE + 0x22C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS27 + Message Buffer 27 CS Register + MB_SIZE + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB10_32B_WORD6 + Message Buffer 10 WORD_32B Register + MB_SIZE + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_16B_CS + Message Buffer 18 CS Register + MB_SIZE + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB27_8B_CS + Message Buffer 27 CS Register + MB_SIZE + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB6_64B_CS + Message Buffer 6 CS Register + MB_SIZE + 0x230 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID27 + Message Buffer 27 ID Register + MB_SIZE + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_32B_WORD7 + Message Buffer 10 WORD_32B Register + MB_SIZE + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_16B_ID + Message Buffer 18 ID Register + MB_SIZE + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB27_8B_ID + Message Buffer 27 ID Register + MB_SIZE + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB6_64B_ID + Message Buffer 6 ID Register + MB_SIZE + 0x234 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB11_32B_CS + Message Buffer 11 CS Register + MB_SIZE + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB18_16B_WORD0 + Message Buffer 18 WORD_16B Register + MB_SIZE + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB27_8B_WORD0 + Message Buffer 27 WORD_8B Register + MB_SIZE + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_64B_WORD0 + Message Buffer 6 WORD_64B Register + MB_SIZE + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD027 + Message Buffer 27 WORD0 Register + MB_SIZE + 0x238 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_32B_ID + Message Buffer 11 ID Register + MB_SIZE + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB18_16B_WORD1 + Message Buffer 18 WORD_16B Register + MB_SIZE + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB27_8B_WORD1 + Message Buffer 27 WORD_8B Register + MB_SIZE + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_64B_WORD1 + Message Buffer 6 WORD_64B Register + MB_SIZE + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD127 + Message Buffer 27 WORD1 Register + MB_SIZE + 0x23C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS28 + Message Buffer 28 CS Register + MB_SIZE + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB11_32B_WORD0 + Message Buffer 11 WORD_32B Register + MB_SIZE + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_16B_WORD2 + Message Buffer 18 WORD_16B Register + MB_SIZE + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB28_8B_CS + Message Buffer 28 CS Register + MB_SIZE + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB6_64B_WORD2 + Message Buffer 6 WORD_64B Register + MB_SIZE + 0x240 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID28 + Message Buffer 28 ID Register + MB_SIZE + 0x244 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB11_32B_WORD1 + Message Buffer 11 WORD_32B Register + MB_SIZE + 0x244 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_16B_WORD3 + Message Buffer 18 WORD_16B Register + MB_SIZE + 0x244 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB28_8B_ID + Message Buffer 28 ID Register + MB_SIZE + 0x244 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB6_64B_WORD3 + Message Buffer 6 WORD_64B Register + MB_SIZE + 0x244 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_32B_WORD2 + Message Buffer 11 WORD_32B Register + MB_SIZE + 0x248 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_16B_CS + Message Buffer 19 CS Register + MB_SIZE + 0x248 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB28_8B_WORD0 + Message Buffer 28 WORD_8B Register + MB_SIZE + 0x248 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_64B_WORD4 + Message Buffer 6 WORD_64B Register + MB_SIZE + 0x248 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD028 + Message Buffer 28 WORD0 Register + MB_SIZE + 0x248 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_32B_WORD3 + Message Buffer 11 WORD_32B Register + MB_SIZE + 0x24C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_16B_ID + Message Buffer 19 ID Register + MB_SIZE + 0x24C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB28_8B_WORD1 + Message Buffer 28 WORD_8B Register + MB_SIZE + 0x24C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_64B_WORD5 + Message Buffer 6 WORD_64B Register + MB_SIZE + 0x24C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD128 + Message Buffer 28 WORD1 Register + MB_SIZE + 0x24C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS29 + Message Buffer 29 CS Register + MB_SIZE + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB11_32B_WORD4 + Message Buffer 11 WORD_32B Register + MB_SIZE + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_16B_WORD0 + Message Buffer 19 WORD_16B Register + MB_SIZE + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB29_8B_CS + Message Buffer 29 CS Register + MB_SIZE + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB6_64B_WORD6 + Message Buffer 6 WORD_64B Register + MB_SIZE + 0x250 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID29 + Message Buffer 29 ID Register + MB_SIZE + 0x254 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB11_32B_WORD5 + Message Buffer 11 WORD_32B Register + MB_SIZE + 0x254 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_16B_WORD1 + Message Buffer 19 WORD_16B Register + MB_SIZE + 0x254 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB29_8B_ID + Message Buffer 29 ID Register + MB_SIZE + 0x254 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB6_64B_WORD7 + Message Buffer 6 WORD_64B Register + MB_SIZE + 0x254 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_32B_WORD6 + Message Buffer 11 WORD_32B Register + MB_SIZE + 0x258 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_16B_WORD2 + Message Buffer 19 WORD_16B Register + MB_SIZE + 0x258 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB29_8B_WORD0 + Message Buffer 29 WORD_8B Register + MB_SIZE + 0x258 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_64B_WORD8 + Message Buffer 6 WORD_64B Register + MB_SIZE + 0x258 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD029 + Message Buffer 29 WORD0 Register + MB_SIZE + 0x258 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_32B_WORD7 + Message Buffer 11 WORD_32B Register + MB_SIZE + 0x25C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_16B_WORD3 + Message Buffer 19 WORD_16B Register + MB_SIZE + 0x25C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB29_8B_WORD1 + Message Buffer 29 WORD_8B Register + MB_SIZE + 0x25C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_64B_WORD9 + Message Buffer 6 WORD_64B Register + MB_SIZE + 0x25C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD129 + Message Buffer 29 WORD1 Register + MB_SIZE + 0x25C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS30 + Message Buffer 30 CS Register + MB_SIZE + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB12_32B_CS + Message Buffer 12 CS Register + MB_SIZE + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB20_16B_CS + Message Buffer 20 CS Register + MB_SIZE + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB30_8B_CS + Message Buffer 30 CS Register + MB_SIZE + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB6_64B_WORD10 + Message Buffer 6 WORD_64B Register + MB_SIZE + 0x260 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID30 + Message Buffer 30 ID Register + MB_SIZE + 0x264 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_32B_ID + Message Buffer 12 ID Register + MB_SIZE + 0x264 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB20_16B_ID + Message Buffer 20 ID Register + MB_SIZE + 0x264 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB30_8B_ID + Message Buffer 30 ID Register + MB_SIZE + 0x264 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB6_64B_WORD11 + Message Buffer 6 WORD_64B Register + MB_SIZE + 0x264 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB12_32B_WORD0 + Message Buffer 12 WORD_32B Register + MB_SIZE + 0x268 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_16B_WORD0 + Message Buffer 20 WORD_16B Register + MB_SIZE + 0x268 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB30_8B_WORD0 + Message Buffer 30 WORD_8B Register + MB_SIZE + 0x268 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_64B_WORD12 + Message Buffer 6 WORD_64B Register + MB_SIZE + 0x268 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD030 + Message Buffer 30 WORD0 Register + MB_SIZE + 0x268 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB12_32B_WORD1 + Message Buffer 12 WORD_32B Register + MB_SIZE + 0x26C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_16B_WORD1 + Message Buffer 20 WORD_16B Register + MB_SIZE + 0x26C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB30_8B_WORD1 + Message Buffer 30 WORD_8B Register + MB_SIZE + 0x26C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB6_64B_WORD13 + Message Buffer 6 WORD_64B Register + MB_SIZE + 0x26C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD130 + Message Buffer 30 WORD1 Register + MB_SIZE + 0x26C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS31 + Message Buffer 31 CS Register + MB_SIZE + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB12_32B_WORD2 + Message Buffer 12 WORD_32B Register + MB_SIZE + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_16B_WORD2 + Message Buffer 20 WORD_16B Register + MB_SIZE + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB31_8B_CS + Message Buffer 31 CS Register + MB_SIZE + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB6_64B_WORD14 + Message Buffer 6 WORD_64B Register + MB_SIZE + 0x270 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID31 + Message Buffer 31 ID Register + MB_SIZE + 0x274 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_32B_WORD3 + Message Buffer 12 WORD_32B Register + MB_SIZE + 0x274 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_16B_WORD3 + Message Buffer 20 WORD_16B Register + MB_SIZE + 0x274 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB31_8B_ID + Message Buffer 31 ID Register + MB_SIZE + 0x274 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB6_64B_WORD15 + Message Buffer 6 WORD_64B Register + MB_SIZE + 0x274 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB12_32B_WORD4 + Message Buffer 12 WORD_32B Register + MB_SIZE + 0x278 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB21_16B_CS + Message Buffer 21 CS Register + MB_SIZE + 0x278 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB31_8B_WORD0 + Message Buffer 31 WORD_8B Register + MB_SIZE + 0x278 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_64B_CS + Message Buffer 7 CS Register + MB_SIZE + 0x278 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + WORD031 + Message Buffer 31 WORD0 Register + MB_SIZE + 0x278 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB12_32B_WORD5 + Message Buffer 12 WORD_32B Register + MB_SIZE + 0x27C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB21_16B_ID + Message Buffer 21 ID Register + MB_SIZE + 0x27C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB31_8B_WORD1 + Message Buffer 31 WORD_8B Register + MB_SIZE + 0x27C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_64B_ID + Message Buffer 7 ID Register + MB_SIZE + 0x27C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD131 + Message Buffer 31 WORD1 Register + MB_SIZE + 0x27C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS32 + Message Buffer 32 CS Register + MB_SIZE + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB12_32B_WORD6 + Message Buffer 12 WORD_32B Register + MB_SIZE + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB21_16B_WORD0 + Message Buffer 21 WORD_16B Register + MB_SIZE + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB32_8B_CS + Message Buffer 32 CS Register + MB_SIZE + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB7_64B_WORD0 + Message Buffer 7 WORD_64B Register + MB_SIZE + 0x280 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID32 + Message Buffer 32 ID Register + MB_SIZE + 0x284 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_32B_WORD7 + Message Buffer 12 WORD_32B Register + MB_SIZE + 0x284 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB21_16B_WORD1 + Message Buffer 21 WORD_16B Register + MB_SIZE + 0x284 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB32_8B_ID + Message Buffer 32 ID Register + MB_SIZE + 0x284 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB7_64B_WORD1 + Message Buffer 7 WORD_64B Register + MB_SIZE + 0x284 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_32B_CS + Message Buffer 13 CS Register + MB_SIZE + 0x288 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB21_16B_WORD2 + Message Buffer 21 WORD_16B Register + MB_SIZE + 0x288 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB32_8B_WORD0 + Message Buffer 32 WORD_8B Register + MB_SIZE + 0x288 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_64B_WORD2 + Message Buffer 7 WORD_64B Register + MB_SIZE + 0x288 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD032 + Message Buffer 32 WORD0 Register + MB_SIZE + 0x288 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_32B_ID + Message Buffer 13 ID Register + MB_SIZE + 0x28C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB21_16B_WORD3 + Message Buffer 21 WORD_16B Register + MB_SIZE + 0x28C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB32_8B_WORD1 + Message Buffer 32 WORD_8B Register + MB_SIZE + 0x28C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_64B_WORD3 + Message Buffer 7 WORD_64B Register + MB_SIZE + 0x28C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD132 + Message Buffer 32 WORD1 Register + MB_SIZE + 0x28C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS33 + Message Buffer 33 CS Register + MB_SIZE + 0x290 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB13_32B_WORD0 + Message Buffer 13 WORD_32B Register + MB_SIZE + 0x290 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_16B_CS + Message Buffer 22 CS Register + MB_SIZE + 0x290 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB33_8B_CS + Message Buffer 33 CS Register + MB_SIZE + 0x290 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB7_64B_WORD4 + Message Buffer 7 WORD_64B Register + MB_SIZE + 0x290 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID33 + Message Buffer 33 ID Register + MB_SIZE + 0x294 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB13_32B_WORD1 + Message Buffer 13 WORD_32B Register + MB_SIZE + 0x294 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_16B_ID + Message Buffer 22 ID Register + MB_SIZE + 0x294 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB33_8B_ID + Message Buffer 33 ID Register + MB_SIZE + 0x294 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB7_64B_WORD5 + Message Buffer 7 WORD_64B Register + MB_SIZE + 0x294 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_32B_WORD2 + Message Buffer 13 WORD_32B Register + MB_SIZE + 0x298 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_16B_WORD0 + Message Buffer 22 WORD_16B Register + MB_SIZE + 0x298 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB33_8B_WORD0 + Message Buffer 33 WORD_8B Register + MB_SIZE + 0x298 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_64B_WORD6 + Message Buffer 7 WORD_64B Register + MB_SIZE + 0x298 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD033 + Message Buffer 33 WORD0 Register + MB_SIZE + 0x298 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_32B_WORD3 + Message Buffer 13 WORD_32B Register + MB_SIZE + 0x29C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_16B_WORD1 + Message Buffer 22 WORD_16B Register + MB_SIZE + 0x29C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB33_8B_WORD1 + Message Buffer 33 WORD_8B Register + MB_SIZE + 0x29C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_64B_WORD7 + Message Buffer 7 WORD_64B Register + MB_SIZE + 0x29C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD133 + Message Buffer 33 WORD1 Register + MB_SIZE + 0x29C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS34 + Message Buffer 34 CS Register + MB_SIZE + 0x2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB13_32B_WORD4 + Message Buffer 13 WORD_32B Register + MB_SIZE + 0x2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_16B_WORD2 + Message Buffer 22 WORD_16B Register + MB_SIZE + 0x2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB34_8B_CS + Message Buffer 34 CS Register + MB_SIZE + 0x2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB7_64B_WORD8 + Message Buffer 7 WORD_64B Register + MB_SIZE + 0x2A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID34 + Message Buffer 34 ID Register + MB_SIZE + 0x2A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB13_32B_WORD5 + Message Buffer 13 WORD_32B Register + MB_SIZE + 0x2A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_16B_WORD3 + Message Buffer 22 WORD_16B Register + MB_SIZE + 0x2A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB34_8B_ID + Message Buffer 34 ID Register + MB_SIZE + 0x2A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB7_64B_WORD9 + Message Buffer 7 WORD_64B Register + MB_SIZE + 0x2A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_32B_WORD6 + Message Buffer 13 WORD_32B Register + MB_SIZE + 0x2A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_16B_CS + Message Buffer 23 CS Register + MB_SIZE + 0x2A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB34_8B_WORD0 + Message Buffer 34 WORD_8B Register + MB_SIZE + 0x2A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_64B_WORD10 + Message Buffer 7 WORD_64B Register + MB_SIZE + 0x2A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD034 + Message Buffer 34 WORD0 Register + MB_SIZE + 0x2A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_32B_WORD7 + Message Buffer 13 WORD_32B Register + MB_SIZE + 0x2AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_16B_ID + Message Buffer 23 ID Register + MB_SIZE + 0x2AC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB34_8B_WORD1 + Message Buffer 34 WORD_8B Register + MB_SIZE + 0x2AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_64B_WORD11 + Message Buffer 7 WORD_64B Register + MB_SIZE + 0x2AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD134 + Message Buffer 34 WORD1 Register + MB_SIZE + 0x2AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS35 + Message Buffer 35 CS Register + MB_SIZE + 0x2B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB14_32B_CS + Message Buffer 14 CS Register + MB_SIZE + 0x2B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB23_16B_WORD0 + Message Buffer 23 WORD_16B Register + MB_SIZE + 0x2B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB35_8B_CS + Message Buffer 35 CS Register + MB_SIZE + 0x2B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB7_64B_WORD12 + Message Buffer 7 WORD_64B Register + MB_SIZE + 0x2B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID35 + Message Buffer 35 ID Register + MB_SIZE + 0x2B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB14_32B_ID + Message Buffer 14 ID Register + MB_SIZE + 0x2B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB23_16B_WORD1 + Message Buffer 23 WORD_16B Register + MB_SIZE + 0x2B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB35_8B_ID + Message Buffer 35 ID Register + MB_SIZE + 0x2B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB7_64B_WORD13 + Message Buffer 7 WORD_64B Register + MB_SIZE + 0x2B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB14_32B_WORD0 + Message Buffer 14 WORD_32B Register + MB_SIZE + 0x2B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_16B_WORD2 + Message Buffer 23 WORD_16B Register + MB_SIZE + 0x2B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB35_8B_WORD0 + Message Buffer 35 WORD_8B Register + MB_SIZE + 0x2B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_64B_WORD14 + Message Buffer 7 WORD_64B Register + MB_SIZE + 0x2B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD035 + Message Buffer 35 WORD0 Register + MB_SIZE + 0x2B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB14_32B_WORD1 + Message Buffer 14 WORD_32B Register + MB_SIZE + 0x2BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_16B_WORD3 + Message Buffer 23 WORD_16B Register + MB_SIZE + 0x2BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB35_8B_WORD1 + Message Buffer 35 WORD_8B Register + MB_SIZE + 0x2BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB7_64B_WORD15 + Message Buffer 7 WORD_64B Register + MB_SIZE + 0x2BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD135 + Message Buffer 35 WORD1 Register + MB_SIZE + 0x2BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS36 + Message Buffer 36 CS Register + MB_SIZE + 0x2C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB14_32B_WORD2 + Message Buffer 14 WORD_32B Register + MB_SIZE + 0x2C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB24_16B_CS + Message Buffer 24 CS Register + MB_SIZE + 0x2C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB36_8B_CS + Message Buffer 36 CS Register + MB_SIZE + 0x2C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB8_64B_CS + Message Buffer 8 CS Register + MB_SIZE + 0x2C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID36 + Message Buffer 36 ID Register + MB_SIZE + 0x2C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB14_32B_WORD3 + Message Buffer 14 WORD_32B Register + MB_SIZE + 0x2C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB24_16B_ID + Message Buffer 24 ID Register + MB_SIZE + 0x2C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB36_8B_ID + Message Buffer 36 ID Register + MB_SIZE + 0x2C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB8_64B_ID + Message Buffer 8 ID Register + MB_SIZE + 0x2C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB14_32B_WORD4 + Message Buffer 14 WORD_32B Register + MB_SIZE + 0x2C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB24_16B_WORD0 + Message Buffer 24 WORD_16B Register + MB_SIZE + 0x2C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB36_8B_WORD0 + Message Buffer 36 WORD_8B Register + MB_SIZE + 0x2C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_64B_WORD0 + Message Buffer 8 WORD_64B Register + MB_SIZE + 0x2C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD036 + Message Buffer 36 WORD0 Register + MB_SIZE + 0x2C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB14_32B_WORD5 + Message Buffer 14 WORD_32B Register + MB_SIZE + 0x2CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB24_16B_WORD1 + Message Buffer 24 WORD_16B Register + MB_SIZE + 0x2CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB36_8B_WORD1 + Message Buffer 36 WORD_8B Register + MB_SIZE + 0x2CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_64B_WORD1 + Message Buffer 8 WORD_64B Register + MB_SIZE + 0x2CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD136 + Message Buffer 36 WORD1 Register + MB_SIZE + 0x2CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS37 + Message Buffer 37 CS Register + MB_SIZE + 0x2D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB14_32B_WORD6 + Message Buffer 14 WORD_32B Register + MB_SIZE + 0x2D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB24_16B_WORD2 + Message Buffer 24 WORD_16B Register + MB_SIZE + 0x2D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB37_8B_CS + Message Buffer 37 CS Register + MB_SIZE + 0x2D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB8_64B_WORD2 + Message Buffer 8 WORD_64B Register + MB_SIZE + 0x2D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID37 + Message Buffer 37 ID Register + MB_SIZE + 0x2D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB14_32B_WORD7 + Message Buffer 14 WORD_32B Register + MB_SIZE + 0x2D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB24_16B_WORD3 + Message Buffer 24 WORD_16B Register + MB_SIZE + 0x2D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB37_8B_ID + Message Buffer 37 ID Register + MB_SIZE + 0x2D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB8_64B_WORD3 + Message Buffer 8 WORD_64B Register + MB_SIZE + 0x2D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB15_32B_CS + Message Buffer 15 CS Register + MB_SIZE + 0x2D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB25_16B_CS + Message Buffer 25 CS Register + MB_SIZE + 0x2D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB37_8B_WORD0 + Message Buffer 37 WORD_8B Register + MB_SIZE + 0x2D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_64B_WORD4 + Message Buffer 8 WORD_64B Register + MB_SIZE + 0x2D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD037 + Message Buffer 37 WORD0 Register + MB_SIZE + 0x2D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB15_32B_ID + Message Buffer 15 ID Register + MB_SIZE + 0x2DC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB25_16B_ID + Message Buffer 25 ID Register + MB_SIZE + 0x2DC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB37_8B_WORD1 + Message Buffer 37 WORD_8B Register + MB_SIZE + 0x2DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_64B_WORD5 + Message Buffer 8 WORD_64B Register + MB_SIZE + 0x2DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD137 + Message Buffer 37 WORD1 Register + MB_SIZE + 0x2DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS38 + Message Buffer 38 CS Register + MB_SIZE + 0x2E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB15_32B_WORD0 + Message Buffer 15 WORD_32B Register + MB_SIZE + 0x2E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB25_16B_WORD0 + Message Buffer 25 WORD_16B Register + MB_SIZE + 0x2E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB38_8B_CS + Message Buffer 38 CS Register + MB_SIZE + 0x2E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB8_64B_WORD6 + Message Buffer 8 WORD_64B Register + MB_SIZE + 0x2E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID38 + Message Buffer 38 ID Register + MB_SIZE + 0x2E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB15_32B_WORD1 + Message Buffer 15 WORD_32B Register + MB_SIZE + 0x2E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB25_16B_WORD1 + Message Buffer 25 WORD_16B Register + MB_SIZE + 0x2E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB38_8B_ID + Message Buffer 38 ID Register + MB_SIZE + 0x2E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB8_64B_WORD7 + Message Buffer 8 WORD_64B Register + MB_SIZE + 0x2E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB15_32B_WORD2 + Message Buffer 15 WORD_32B Register + MB_SIZE + 0x2E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB25_16B_WORD2 + Message Buffer 25 WORD_16B Register + MB_SIZE + 0x2E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB38_8B_WORD0 + Message Buffer 38 WORD_8B Register + MB_SIZE + 0x2E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_64B_WORD8 + Message Buffer 8 WORD_64B Register + MB_SIZE + 0x2E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD038 + Message Buffer 38 WORD0 Register + MB_SIZE + 0x2E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB15_32B_WORD3 + Message Buffer 15 WORD_32B Register + MB_SIZE + 0x2EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB25_16B_WORD3 + Message Buffer 25 WORD_16B Register + MB_SIZE + 0x2EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB38_8B_WORD1 + Message Buffer 38 WORD_8B Register + MB_SIZE + 0x2EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_64B_WORD9 + Message Buffer 8 WORD_64B Register + MB_SIZE + 0x2EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD138 + Message Buffer 38 WORD1 Register + MB_SIZE + 0x2EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS39 + Message Buffer 39 CS Register + MB_SIZE + 0x2F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB15_32B_WORD4 + Message Buffer 15 WORD_32B Register + MB_SIZE + 0x2F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB26_16B_CS + Message Buffer 26 CS Register + MB_SIZE + 0x2F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB39_8B_CS + Message Buffer 39 CS Register + MB_SIZE + 0x2F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB8_64B_WORD10 + Message Buffer 8 WORD_64B Register + MB_SIZE + 0x2F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID39 + Message Buffer 39 ID Register + MB_SIZE + 0x2F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB15_32B_WORD5 + Message Buffer 15 WORD_32B Register + MB_SIZE + 0x2F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB26_16B_ID + Message Buffer 26 ID Register + MB_SIZE + 0x2F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB39_8B_ID + Message Buffer 39 ID Register + MB_SIZE + 0x2F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB8_64B_WORD11 + Message Buffer 8 WORD_64B Register + MB_SIZE + 0x2F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB15_32B_WORD6 + Message Buffer 15 WORD_32B Register + MB_SIZE + 0x2F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB26_16B_WORD0 + Message Buffer 26 WORD_16B Register + MB_SIZE + 0x2F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB39_8B_WORD0 + Message Buffer 39 WORD_8B Register + MB_SIZE + 0x2F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_64B_WORD12 + Message Buffer 8 WORD_64B Register + MB_SIZE + 0x2F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD039 + Message Buffer 39 WORD0 Register + MB_SIZE + 0x2F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB15_32B_WORD7 + Message Buffer 15 WORD_32B Register + MB_SIZE + 0x2FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB26_16B_WORD1 + Message Buffer 26 WORD_16B Register + MB_SIZE + 0x2FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB39_8B_WORD1 + Message Buffer 39 WORD_8B Register + MB_SIZE + 0x2FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB8_64B_WORD13 + Message Buffer 8 WORD_64B Register + MB_SIZE + 0x2FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD139 + Message Buffer 39 WORD1 Register + MB_SIZE + 0x2FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS40 + Message Buffer 40 CS Register + MB_SIZE + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB16_32B_CS + Message Buffer 16 CS Register + MB_SIZE + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB26_16B_WORD2 + Message Buffer 26 WORD_16B Register + MB_SIZE + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB40_8B_CS + Message Buffer 40 CS Register + MB_SIZE + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB8_64B_WORD14 + Message Buffer 8 WORD_64B Register + MB_SIZE + 0x300 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID40 + Message Buffer 40 ID Register + MB_SIZE + 0x304 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB16_32B_ID + Message Buffer 16 ID Register + MB_SIZE + 0x304 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB26_16B_WORD3 + Message Buffer 26 WORD_16B Register + MB_SIZE + 0x304 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB40_8B_ID + Message Buffer 40 ID Register + MB_SIZE + 0x304 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB8_64B_WORD15 + Message Buffer 8 WORD_64B Register + MB_SIZE + 0x304 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB16_32B_WORD0 + Message Buffer 16 WORD_32B Register + MB_SIZE + 0x308 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB27_16B_CS + Message Buffer 27 CS Register + MB_SIZE + 0x308 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB40_8B_WORD0 + Message Buffer 40 WORD_8B Register + MB_SIZE + 0x308 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_64B_CS + Message Buffer 9 CS Register + MB_SIZE + 0x308 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + WORD040 + Message Buffer 40 WORD0 Register + MB_SIZE + 0x308 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB16_32B_WORD1 + Message Buffer 16 WORD_32B Register + MB_SIZE + 0x30C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB27_16B_ID + Message Buffer 27 ID Register + MB_SIZE + 0x30C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB40_8B_WORD1 + Message Buffer 40 WORD_8B Register + MB_SIZE + 0x30C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_64B_ID + Message Buffer 9 ID Register + MB_SIZE + 0x30C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + WORD140 + Message Buffer 40 WORD1 Register + MB_SIZE + 0x30C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS41 + Message Buffer 41 CS Register + MB_SIZE + 0x310 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB16_32B_WORD2 + Message Buffer 16 WORD_32B Register + MB_SIZE + 0x310 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB27_16B_WORD0 + Message Buffer 27 WORD_16B Register + MB_SIZE + 0x310 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB41_8B_CS + Message Buffer 41 CS Register + MB_SIZE + 0x310 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB9_64B_WORD0 + Message Buffer 9 WORD_64B Register + MB_SIZE + 0x310 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID41 + Message Buffer 41 ID Register + MB_SIZE + 0x314 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB16_32B_WORD3 + Message Buffer 16 WORD_32B Register + MB_SIZE + 0x314 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB27_16B_WORD1 + Message Buffer 27 WORD_16B Register + MB_SIZE + 0x314 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB41_8B_ID + Message Buffer 41 ID Register + MB_SIZE + 0x314 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB9_64B_WORD1 + Message Buffer 9 WORD_64B Register + MB_SIZE + 0x314 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB16_32B_WORD4 + Message Buffer 16 WORD_32B Register + MB_SIZE + 0x318 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB27_16B_WORD2 + Message Buffer 27 WORD_16B Register + MB_SIZE + 0x318 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB41_8B_WORD0 + Message Buffer 41 WORD_8B Register + MB_SIZE + 0x318 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_64B_WORD2 + Message Buffer 9 WORD_64B Register + MB_SIZE + 0x318 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD041 + Message Buffer 41 WORD0 Register + MB_SIZE + 0x318 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB16_32B_WORD5 + Message Buffer 16 WORD_32B Register + MB_SIZE + 0x31C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB27_16B_WORD3 + Message Buffer 27 WORD_16B Register + MB_SIZE + 0x31C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB41_8B_WORD1 + Message Buffer 41 WORD_8B Register + MB_SIZE + 0x31C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_64B_WORD3 + Message Buffer 9 WORD_64B Register + MB_SIZE + 0x31C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD141 + Message Buffer 41 WORD1 Register + MB_SIZE + 0x31C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS42 + Message Buffer 42 CS Register + MB_SIZE + 0x320 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB16_32B_WORD6 + Message Buffer 16 WORD_32B Register + MB_SIZE + 0x320 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB28_16B_CS + Message Buffer 28 CS Register + MB_SIZE + 0x320 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB42_8B_CS + Message Buffer 42 CS Register + MB_SIZE + 0x320 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB9_64B_WORD4 + Message Buffer 9 WORD_64B Register + MB_SIZE + 0x320 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID42 + Message Buffer 42 ID Register + MB_SIZE + 0x324 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB16_32B_WORD7 + Message Buffer 16 WORD_32B Register + MB_SIZE + 0x324 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB28_16B_ID + Message Buffer 28 ID Register + MB_SIZE + 0x324 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB42_8B_ID + Message Buffer 42 ID Register + MB_SIZE + 0x324 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB9_64B_WORD5 + Message Buffer 9 WORD_64B Register + MB_SIZE + 0x324 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_32B_CS + Message Buffer 17 CS Register + MB_SIZE + 0x328 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB28_16B_WORD0 + Message Buffer 28 WORD_16B Register + MB_SIZE + 0x328 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB42_8B_WORD0 + Message Buffer 42 WORD_8B Register + MB_SIZE + 0x328 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_64B_WORD6 + Message Buffer 9 WORD_64B Register + MB_SIZE + 0x328 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD042 + Message Buffer 42 WORD0 Register + MB_SIZE + 0x328 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_32B_ID + Message Buffer 17 ID Register + MB_SIZE + 0x32C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB28_16B_WORD1 + Message Buffer 28 WORD_16B Register + MB_SIZE + 0x32C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB42_8B_WORD1 + Message Buffer 42 WORD_8B Register + MB_SIZE + 0x32C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_64B_WORD7 + Message Buffer 9 WORD_64B Register + MB_SIZE + 0x32C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD142 + Message Buffer 42 WORD1 Register + MB_SIZE + 0x32C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS43 + Message Buffer 43 CS Register + MB_SIZE + 0x330 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB17_32B_WORD0 + Message Buffer 17 WORD_32B Register + MB_SIZE + 0x330 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB28_16B_WORD2 + Message Buffer 28 WORD_16B Register + MB_SIZE + 0x330 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB43_8B_CS + Message Buffer 43 CS Register + MB_SIZE + 0x330 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB9_64B_WORD8 + Message Buffer 9 WORD_64B Register + MB_SIZE + 0x330 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID43 + Message Buffer 43 ID Register + MB_SIZE + 0x334 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB17_32B_WORD1 + Message Buffer 17 WORD_32B Register + MB_SIZE + 0x334 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB28_16B_WORD3 + Message Buffer 28 WORD_16B Register + MB_SIZE + 0x334 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB43_8B_ID + Message Buffer 43 ID Register + MB_SIZE + 0x334 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB9_64B_WORD9 + Message Buffer 9 WORD_64B Register + MB_SIZE + 0x334 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_32B_WORD2 + Message Buffer 17 WORD_32B Register + MB_SIZE + 0x338 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB29_16B_CS + Message Buffer 29 CS Register + MB_SIZE + 0x338 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB43_8B_WORD0 + Message Buffer 43 WORD_8B Register + MB_SIZE + 0x338 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_64B_WORD10 + Message Buffer 9 WORD_64B Register + MB_SIZE + 0x338 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD043 + Message Buffer 43 WORD0 Register + MB_SIZE + 0x338 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_32B_WORD3 + Message Buffer 17 WORD_32B Register + MB_SIZE + 0x33C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB29_16B_ID + Message Buffer 29 ID Register + MB_SIZE + 0x33C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB43_8B_WORD1 + Message Buffer 43 WORD_8B Register + MB_SIZE + 0x33C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_64B_WORD11 + Message Buffer 9 WORD_64B Register + MB_SIZE + 0x33C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD143 + Message Buffer 43 WORD1 Register + MB_SIZE + 0x33C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS44 + Message Buffer 44 CS Register + MB_SIZE + 0x340 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB17_32B_WORD4 + Message Buffer 17 WORD_32B Register + MB_SIZE + 0x340 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB29_16B_WORD0 + Message Buffer 29 WORD_16B Register + MB_SIZE + 0x340 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB44_8B_CS + Message Buffer 44 CS Register + MB_SIZE + 0x340 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB9_64B_WORD12 + Message Buffer 9 WORD_64B Register + MB_SIZE + 0x340 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + ID44 + Message Buffer 44 ID Register + MB_SIZE + 0x344 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB17_32B_WORD5 + Message Buffer 17 WORD_32B Register + MB_SIZE + 0x344 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB29_16B_WORD1 + Message Buffer 29 WORD_16B Register + MB_SIZE + 0x344 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB44_8B_ID + Message Buffer 44 ID Register + MB_SIZE + 0x344 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB9_64B_WORD13 + Message Buffer 9 WORD_64B Register + MB_SIZE + 0x344 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_32B_WORD6 + Message Buffer 17 WORD_32B Register + MB_SIZE + 0x348 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB29_16B_WORD2 + Message Buffer 29 WORD_16B Register + MB_SIZE + 0x348 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB44_8B_WORD0 + Message Buffer 44 WORD_8B Register + MB_SIZE + 0x348 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_64B_WORD14 + Message Buffer 9 WORD_64B Register + MB_SIZE + 0x348 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD044 + Message Buffer 44 WORD0 Register + MB_SIZE + 0x348 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB17_32B_WORD7 + Message Buffer 17 WORD_32B Register + MB_SIZE + 0x34C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB29_16B_WORD3 + Message Buffer 29 WORD_16B Register + MB_SIZE + 0x34C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB44_8B_WORD1 + Message Buffer 44 WORD_8B Register + MB_SIZE + 0x34C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB9_64B_WORD15 + Message Buffer 9 WORD_64B Register + MB_SIZE + 0x34C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD144 + Message Buffer 44 WORD1 Register + MB_SIZE + 0x34C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS45 + Message Buffer 45 CS Register + MB_SIZE + 0x350 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB10_64B_CS + Message Buffer 10 CS Register + MB_SIZE + 0x350 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB18_32B_CS + Message Buffer 18 CS Register + MB_SIZE + 0x350 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB30_16B_CS + Message Buffer 30 CS Register + MB_SIZE + 0x350 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB45_8B_CS + Message Buffer 45 CS Register + MB_SIZE + 0x350 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID45 + Message Buffer 45 ID Register + MB_SIZE + 0x354 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_64B_ID + Message Buffer 10 ID Register + MB_SIZE + 0x354 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB18_32B_ID + Message Buffer 18 ID Register + MB_SIZE + 0x354 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB30_16B_ID + Message Buffer 30 ID Register + MB_SIZE + 0x354 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB45_8B_ID + Message Buffer 45 ID Register + MB_SIZE + 0x354 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_64B_WORD0 + Message Buffer 10 WORD_64B Register + MB_SIZE + 0x358 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_32B_WORD0 + Message Buffer 18 WORD_32B Register + MB_SIZE + 0x358 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB30_16B_WORD0 + Message Buffer 30 WORD_16B Register + MB_SIZE + 0x358 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB45_8B_WORD0 + Message Buffer 45 WORD_8B Register + MB_SIZE + 0x358 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD045 + Message Buffer 45 WORD0 Register + MB_SIZE + 0x358 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB10_64B_WORD1 + Message Buffer 10 WORD_64B Register + MB_SIZE + 0x35C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_32B_WORD1 + Message Buffer 18 WORD_32B Register + MB_SIZE + 0x35C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB30_16B_WORD1 + Message Buffer 30 WORD_16B Register + MB_SIZE + 0x35C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB45_8B_WORD1 + Message Buffer 45 WORD_8B Register + MB_SIZE + 0x35C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD145 + Message Buffer 45 WORD1 Register + MB_SIZE + 0x35C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS46 + Message Buffer 46 CS Register + MB_SIZE + 0x360 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB10_64B_WORD2 + Message Buffer 10 WORD_64B Register + MB_SIZE + 0x360 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_32B_WORD2 + Message Buffer 18 WORD_32B Register + MB_SIZE + 0x360 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB30_16B_WORD2 + Message Buffer 30 WORD_16B Register + MB_SIZE + 0x360 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB46_8B_CS + Message Buffer 46 CS Register + MB_SIZE + 0x360 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID46 + Message Buffer 46 ID Register + MB_SIZE + 0x364 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_64B_WORD3 + Message Buffer 10 WORD_64B Register + MB_SIZE + 0x364 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_32B_WORD3 + Message Buffer 18 WORD_32B Register + MB_SIZE + 0x364 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB30_16B_WORD3 + Message Buffer 30 WORD_16B Register + MB_SIZE + 0x364 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB46_8B_ID + Message Buffer 46 ID Register + MB_SIZE + 0x364 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_64B_WORD4 + Message Buffer 10 WORD_64B Register + MB_SIZE + 0x368 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_32B_WORD4 + Message Buffer 18 WORD_32B Register + MB_SIZE + 0x368 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB31_16B_CS + Message Buffer 31 CS Register + MB_SIZE + 0x368 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB46_8B_WORD0 + Message Buffer 46 WORD_8B Register + MB_SIZE + 0x368 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD046 + Message Buffer 46 WORD0 Register + MB_SIZE + 0x368 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB10_64B_WORD5 + Message Buffer 10 WORD_64B Register + MB_SIZE + 0x36C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_32B_WORD5 + Message Buffer 18 WORD_32B Register + MB_SIZE + 0x36C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB31_16B_ID + Message Buffer 31 ID Register + MB_SIZE + 0x36C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB46_8B_WORD1 + Message Buffer 46 WORD_8B Register + MB_SIZE + 0x36C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD146 + Message Buffer 46 WORD1 Register + MB_SIZE + 0x36C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS47 + Message Buffer 47 CS Register + MB_SIZE + 0x370 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB10_64B_WORD6 + Message Buffer 10 WORD_64B Register + MB_SIZE + 0x370 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_32B_WORD6 + Message Buffer 18 WORD_32B Register + MB_SIZE + 0x370 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB31_16B_WORD0 + Message Buffer 31 WORD_16B Register + MB_SIZE + 0x370 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB47_8B_CS + Message Buffer 47 CS Register + MB_SIZE + 0x370 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID47 + Message Buffer 47 ID Register + MB_SIZE + 0x374 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_64B_WORD7 + Message Buffer 10 WORD_64B Register + MB_SIZE + 0x374 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB18_32B_WORD7 + Message Buffer 18 WORD_32B Register + MB_SIZE + 0x374 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB31_16B_WORD1 + Message Buffer 31 WORD_16B Register + MB_SIZE + 0x374 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB47_8B_ID + Message Buffer 47 ID Register + MB_SIZE + 0x374 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_64B_WORD8 + Message Buffer 10 WORD_64B Register + MB_SIZE + 0x378 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_32B_CS + Message Buffer 19 CS Register + MB_SIZE + 0x378 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB31_16B_WORD2 + Message Buffer 31 WORD_16B Register + MB_SIZE + 0x378 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB47_8B_WORD0 + Message Buffer 47 WORD_8B Register + MB_SIZE + 0x378 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD047 + Message Buffer 47 WORD0 Register + MB_SIZE + 0x378 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB10_64B_WORD9 + Message Buffer 10 WORD_64B Register + MB_SIZE + 0x37C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_32B_ID + Message Buffer 19 ID Register + MB_SIZE + 0x37C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB31_16B_WORD3 + Message Buffer 31 WORD_16B Register + MB_SIZE + 0x37C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB47_8B_WORD1 + Message Buffer 47 WORD_8B Register + MB_SIZE + 0x37C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD147 + Message Buffer 47 WORD1 Register + MB_SIZE + 0x37C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS48 + Message Buffer 48 CS Register + MB_SIZE + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB10_64B_WORD10 + Message Buffer 10 WORD_64B Register + MB_SIZE + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_32B_WORD0 + Message Buffer 19 WORD_32B Register + MB_SIZE + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB32_16B_CS + Message Buffer 32 CS Register + MB_SIZE + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB48_8B_CS + Message Buffer 48 CS Register + MB_SIZE + 0x380 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID48 + Message Buffer 48 ID Register + MB_SIZE + 0x384 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_64B_WORD11 + Message Buffer 10 WORD_64B Register + MB_SIZE + 0x384 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_32B_WORD1 + Message Buffer 19 WORD_32B Register + MB_SIZE + 0x384 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB32_16B_ID + Message Buffer 32 ID Register + MB_SIZE + 0x384 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB48_8B_ID + Message Buffer 48 ID Register + MB_SIZE + 0x384 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_64B_WORD12 + Message Buffer 10 WORD_64B Register + MB_SIZE + 0x388 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_32B_WORD2 + Message Buffer 19 WORD_32B Register + MB_SIZE + 0x388 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB32_16B_WORD0 + Message Buffer 32 WORD_16B Register + MB_SIZE + 0x388 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB48_8B_WORD0 + Message Buffer 48 WORD_8B Register + MB_SIZE + 0x388 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD048 + Message Buffer 48 WORD0 Register + MB_SIZE + 0x388 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB10_64B_WORD13 + Message Buffer 10 WORD_64B Register + MB_SIZE + 0x38C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_32B_WORD3 + Message Buffer 19 WORD_32B Register + MB_SIZE + 0x38C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB32_16B_WORD1 + Message Buffer 32 WORD_16B Register + MB_SIZE + 0x38C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB48_8B_WORD1 + Message Buffer 48 WORD_8B Register + MB_SIZE + 0x38C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD148 + Message Buffer 48 WORD1 Register + MB_SIZE + 0x38C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS49 + Message Buffer 49 CS Register + MB_SIZE + 0x390 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB10_64B_WORD14 + Message Buffer 10 WORD_64B Register + MB_SIZE + 0x390 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_32B_WORD4 + Message Buffer 19 WORD_32B Register + MB_SIZE + 0x390 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB32_16B_WORD2 + Message Buffer 32 WORD_16B Register + MB_SIZE + 0x390 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB49_8B_CS + Message Buffer 49 CS Register + MB_SIZE + 0x390 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID49 + Message Buffer 49 ID Register + MB_SIZE + 0x394 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB10_64B_WORD15 + Message Buffer 10 WORD_64B Register + MB_SIZE + 0x394 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB19_32B_WORD5 + Message Buffer 19 WORD_32B Register + MB_SIZE + 0x394 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB32_16B_WORD3 + Message Buffer 32 WORD_16B Register + MB_SIZE + 0x394 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB49_8B_ID + Message Buffer 49 ID Register + MB_SIZE + 0x394 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB11_64B_CS + Message Buffer 11 CS Register + MB_SIZE + 0x398 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB19_32B_WORD6 + Message Buffer 19 WORD_32B Register + MB_SIZE + 0x398 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB33_16B_CS + Message Buffer 33 CS Register + MB_SIZE + 0x398 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB49_8B_WORD0 + Message Buffer 49 WORD_8B Register + MB_SIZE + 0x398 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD049 + Message Buffer 49 WORD0 Register + MB_SIZE + 0x398 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_64B_ID + Message Buffer 11 ID Register + MB_SIZE + 0x39C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB19_32B_WORD7 + Message Buffer 19 WORD_32B Register + MB_SIZE + 0x39C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB33_16B_ID + Message Buffer 33 ID Register + MB_SIZE + 0x39C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB49_8B_WORD1 + Message Buffer 49 WORD_8B Register + MB_SIZE + 0x39C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD149 + Message Buffer 49 WORD1 Register + MB_SIZE + 0x39C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS50 + Message Buffer 50 CS Register + MB_SIZE + 0x3A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB11_64B_WORD0 + Message Buffer 11 WORD_64B Register + MB_SIZE + 0x3A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_32B_CS + Message Buffer 20 CS Register + MB_SIZE + 0x3A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB33_16B_WORD0 + Message Buffer 33 WORD_16B Register + MB_SIZE + 0x3A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB50_8B_CS + Message Buffer 50 CS Register + MB_SIZE + 0x3A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID50 + Message Buffer 50 ID Register + MB_SIZE + 0x3A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB11_64B_WORD1 + Message Buffer 11 WORD_64B Register + MB_SIZE + 0x3A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_32B_ID + Message Buffer 20 ID Register + MB_SIZE + 0x3A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB33_16B_WORD1 + Message Buffer 33 WORD_16B Register + MB_SIZE + 0x3A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB50_8B_ID + Message Buffer 50 ID Register + MB_SIZE + 0x3A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB11_64B_WORD2 + Message Buffer 11 WORD_64B Register + MB_SIZE + 0x3A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_32B_WORD0 + Message Buffer 20 WORD_32B Register + MB_SIZE + 0x3A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB33_16B_WORD2 + Message Buffer 33 WORD_16B Register + MB_SIZE + 0x3A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB50_8B_WORD0 + Message Buffer 50 WORD_8B Register + MB_SIZE + 0x3A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD050 + Message Buffer 50 WORD0 Register + MB_SIZE + 0x3A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_64B_WORD3 + Message Buffer 11 WORD_64B Register + MB_SIZE + 0x3AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_32B_WORD1 + Message Buffer 20 WORD_32B Register + MB_SIZE + 0x3AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB33_16B_WORD3 + Message Buffer 33 WORD_16B Register + MB_SIZE + 0x3AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB50_8B_WORD1 + Message Buffer 50 WORD_8B Register + MB_SIZE + 0x3AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD150 + Message Buffer 50 WORD1 Register + MB_SIZE + 0x3AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS51 + Message Buffer 51 CS Register + MB_SIZE + 0x3B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB11_64B_WORD4 + Message Buffer 11 WORD_64B Register + MB_SIZE + 0x3B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_32B_WORD2 + Message Buffer 20 WORD_32B Register + MB_SIZE + 0x3B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB34_16B_CS + Message Buffer 34 CS Register + MB_SIZE + 0x3B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB51_8B_CS + Message Buffer 51 CS Register + MB_SIZE + 0x3B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID51 + Message Buffer 51 ID Register + MB_SIZE + 0x3B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB11_64B_WORD5 + Message Buffer 11 WORD_64B Register + MB_SIZE + 0x3B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_32B_WORD3 + Message Buffer 20 WORD_32B Register + MB_SIZE + 0x3B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB34_16B_ID + Message Buffer 34 ID Register + MB_SIZE + 0x3B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB51_8B_ID + Message Buffer 51 ID Register + MB_SIZE + 0x3B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB11_64B_WORD6 + Message Buffer 11 WORD_64B Register + MB_SIZE + 0x3B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_32B_WORD4 + Message Buffer 20 WORD_32B Register + MB_SIZE + 0x3B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB34_16B_WORD0 + Message Buffer 34 WORD_16B Register + MB_SIZE + 0x3B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB51_8B_WORD0 + Message Buffer 51 WORD_8B Register + MB_SIZE + 0x3B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD051 + Message Buffer 51 WORD0 Register + MB_SIZE + 0x3B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_64B_WORD7 + Message Buffer 11 WORD_64B Register + MB_SIZE + 0x3BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_32B_WORD5 + Message Buffer 20 WORD_32B Register + MB_SIZE + 0x3BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB34_16B_WORD1 + Message Buffer 34 WORD_16B Register + MB_SIZE + 0x3BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB51_8B_WORD1 + Message Buffer 51 WORD_8B Register + MB_SIZE + 0x3BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD151 + Message Buffer 51 WORD1 Register + MB_SIZE + 0x3BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS52 + Message Buffer 52 CS Register + MB_SIZE + 0x3C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB11_64B_WORD8 + Message Buffer 11 WORD_64B Register + MB_SIZE + 0x3C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_32B_WORD6 + Message Buffer 20 WORD_32B Register + MB_SIZE + 0x3C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB34_16B_WORD2 + Message Buffer 34 WORD_16B Register + MB_SIZE + 0x3C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB52_8B_CS + Message Buffer 52 CS Register + MB_SIZE + 0x3C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID52 + Message Buffer 52 ID Register + MB_SIZE + 0x3C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB11_64B_WORD9 + Message Buffer 11 WORD_64B Register + MB_SIZE + 0x3C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB20_32B_WORD7 + Message Buffer 20 WORD_32B Register + MB_SIZE + 0x3C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB34_16B_WORD3 + Message Buffer 34 WORD_16B Register + MB_SIZE + 0x3C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB52_8B_ID + Message Buffer 52 ID Register + MB_SIZE + 0x3C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB11_64B_WORD10 + Message Buffer 11 WORD_64B Register + MB_SIZE + 0x3C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB21_32B_CS + Message Buffer 21 CS Register + MB_SIZE + 0x3C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB35_16B_CS + Message Buffer 35 CS Register + MB_SIZE + 0x3C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB52_8B_WORD0 + Message Buffer 52 WORD_8B Register + MB_SIZE + 0x3C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD052 + Message Buffer 52 WORD0 Register + MB_SIZE + 0x3C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_64B_WORD11 + Message Buffer 11 WORD_64B Register + MB_SIZE + 0x3CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB21_32B_ID + Message Buffer 21 ID Register + MB_SIZE + 0x3CC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB35_16B_ID + Message Buffer 35 ID Register + MB_SIZE + 0x3CC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB52_8B_WORD1 + Message Buffer 52 WORD_8B Register + MB_SIZE + 0x3CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD152 + Message Buffer 52 WORD1 Register + MB_SIZE + 0x3CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS53 + Message Buffer 53 CS Register + MB_SIZE + 0x3D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB11_64B_WORD12 + Message Buffer 11 WORD_64B Register + MB_SIZE + 0x3D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB21_32B_WORD0 + Message Buffer 21 WORD_32B Register + MB_SIZE + 0x3D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB35_16B_WORD0 + Message Buffer 35 WORD_16B Register + MB_SIZE + 0x3D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB53_8B_CS + Message Buffer 53 CS Register + MB_SIZE + 0x3D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID53 + Message Buffer 53 ID Register + MB_SIZE + 0x3D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB11_64B_WORD13 + Message Buffer 11 WORD_64B Register + MB_SIZE + 0x3D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB21_32B_WORD1 + Message Buffer 21 WORD_32B Register + MB_SIZE + 0x3D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB35_16B_WORD1 + Message Buffer 35 WORD_16B Register + MB_SIZE + 0x3D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB53_8B_ID + Message Buffer 53 ID Register + MB_SIZE + 0x3D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB11_64B_WORD14 + Message Buffer 11 WORD_64B Register + MB_SIZE + 0x3D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB21_32B_WORD2 + Message Buffer 21 WORD_32B Register + MB_SIZE + 0x3D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB35_16B_WORD2 + Message Buffer 35 WORD_16B Register + MB_SIZE + 0x3D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB53_8B_WORD0 + Message Buffer 53 WORD_8B Register + MB_SIZE + 0x3D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD053 + Message Buffer 53 WORD0 Register + MB_SIZE + 0x3D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB11_64B_WORD15 + Message Buffer 11 WORD_64B Register + MB_SIZE + 0x3DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB21_32B_WORD3 + Message Buffer 21 WORD_32B Register + MB_SIZE + 0x3DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB35_16B_WORD3 + Message Buffer 35 WORD_16B Register + MB_SIZE + 0x3DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB53_8B_WORD1 + Message Buffer 53 WORD_8B Register + MB_SIZE + 0x3DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD153 + Message Buffer 53 WORD1 Register + MB_SIZE + 0x3DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS54 + Message Buffer 54 CS Register + MB_SIZE + 0x3E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB12_64B_CS + Message Buffer 12 CS Register + MB_SIZE + 0x3E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB21_32B_WORD4 + Message Buffer 21 WORD_32B Register + MB_SIZE + 0x3E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB36_16B_CS + Message Buffer 36 CS Register + MB_SIZE + 0x3E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB54_8B_CS + Message Buffer 54 CS Register + MB_SIZE + 0x3E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID54 + Message Buffer 54 ID Register + MB_SIZE + 0x3E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_64B_ID + Message Buffer 12 ID Register + MB_SIZE + 0x3E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB21_32B_WORD5 + Message Buffer 21 WORD_32B Register + MB_SIZE + 0x3E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB36_16B_ID + Message Buffer 36 ID Register + MB_SIZE + 0x3E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB54_8B_ID + Message Buffer 54 ID Register + MB_SIZE + 0x3E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_64B_WORD0 + Message Buffer 12 WORD_64B Register + MB_SIZE + 0x3E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB21_32B_WORD6 + Message Buffer 21 WORD_32B Register + MB_SIZE + 0x3E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB36_16B_WORD0 + Message Buffer 36 WORD_16B Register + MB_SIZE + 0x3E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB54_8B_WORD0 + Message Buffer 54 WORD_8B Register + MB_SIZE + 0x3E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD054 + Message Buffer 54 WORD0 Register + MB_SIZE + 0x3E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB12_64B_WORD1 + Message Buffer 12 WORD_64B Register + MB_SIZE + 0x3EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB21_32B_WORD7 + Message Buffer 21 WORD_32B Register + MB_SIZE + 0x3EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB36_16B_WORD1 + Message Buffer 36 WORD_16B Register + MB_SIZE + 0x3EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB54_8B_WORD1 + Message Buffer 54 WORD_8B Register + MB_SIZE + 0x3EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD154 + Message Buffer 54 WORD1 Register + MB_SIZE + 0x3EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS55 + Message Buffer 55 CS Register + MB_SIZE + 0x3F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB12_64B_WORD2 + Message Buffer 12 WORD_64B Register + MB_SIZE + 0x3F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_32B_CS + Message Buffer 22 CS Register + MB_SIZE + 0x3F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB36_16B_WORD2 + Message Buffer 36 WORD_16B Register + MB_SIZE + 0x3F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB55_8B_CS + Message Buffer 55 CS Register + MB_SIZE + 0x3F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID55 + Message Buffer 55 ID Register + MB_SIZE + 0x3F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_64B_WORD3 + Message Buffer 12 WORD_64B Register + MB_SIZE + 0x3F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_32B_ID + Message Buffer 22 ID Register + MB_SIZE + 0x3F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB36_16B_WORD3 + Message Buffer 36 WORD_16B Register + MB_SIZE + 0x3F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB55_8B_ID + Message Buffer 55 ID Register + MB_SIZE + 0x3F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_64B_WORD4 + Message Buffer 12 WORD_64B Register + MB_SIZE + 0x3F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_32B_WORD0 + Message Buffer 22 WORD_32B Register + MB_SIZE + 0x3F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB37_16B_CS + Message Buffer 37 CS Register + MB_SIZE + 0x3F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB55_8B_WORD0 + Message Buffer 55 WORD_8B Register + MB_SIZE + 0x3F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD055 + Message Buffer 55 WORD0 Register + MB_SIZE + 0x3F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB12_64B_WORD5 + Message Buffer 12 WORD_64B Register + MB_SIZE + 0x3FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_32B_WORD1 + Message Buffer 22 WORD_32B Register + MB_SIZE + 0x3FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB37_16B_ID + Message Buffer 37 ID Register + MB_SIZE + 0x3FC + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB55_8B_WORD1 + Message Buffer 55 WORD_8B Register + MB_SIZE + 0x3FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD155 + Message Buffer 55 WORD1 Register + MB_SIZE + 0x3FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS56 + Message Buffer 56 CS Register + MB_SIZE + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB12_64B_WORD6 + Message Buffer 12 WORD_64B Register + MB_SIZE + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_32B_WORD2 + Message Buffer 22 WORD_32B Register + MB_SIZE + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB37_16B_WORD0 + Message Buffer 37 WORD_16B Register + MB_SIZE + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB56_8B_CS + Message Buffer 56 CS Register + MB_SIZE + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID56 + Message Buffer 56 ID Register + MB_SIZE + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_64B_WORD7 + Message Buffer 12 WORD_64B Register + MB_SIZE + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_32B_WORD3 + Message Buffer 22 WORD_32B Register + MB_SIZE + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB37_16B_WORD1 + Message Buffer 37 WORD_16B Register + MB_SIZE + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB56_8B_ID + Message Buffer 56 ID Register + MB_SIZE + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_64B_WORD8 + Message Buffer 12 WORD_64B Register + MB_SIZE + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_32B_WORD4 + Message Buffer 22 WORD_32B Register + MB_SIZE + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB37_16B_WORD2 + Message Buffer 37 WORD_16B Register + MB_SIZE + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB56_8B_WORD0 + Message Buffer 56 WORD_8B Register + MB_SIZE + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD056 + Message Buffer 56 WORD0 Register + MB_SIZE + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB12_64B_WORD9 + Message Buffer 12 WORD_64B Register + MB_SIZE + 0x40C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_32B_WORD5 + Message Buffer 22 WORD_32B Register + MB_SIZE + 0x40C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB37_16B_WORD3 + Message Buffer 37 WORD_16B Register + MB_SIZE + 0x40C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB56_8B_WORD1 + Message Buffer 56 WORD_8B Register + MB_SIZE + 0x40C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD156 + Message Buffer 56 WORD1 Register + MB_SIZE + 0x40C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS57 + Message Buffer 57 CS Register + MB_SIZE + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB12_64B_WORD10 + Message Buffer 12 WORD_64B Register + MB_SIZE + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_32B_WORD6 + Message Buffer 22 WORD_32B Register + MB_SIZE + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB38_16B_CS + Message Buffer 38 CS Register + MB_SIZE + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB57_8B_CS + Message Buffer 57 CS Register + MB_SIZE + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID57 + Message Buffer 57 ID Register + MB_SIZE + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_64B_WORD11 + Message Buffer 12 WORD_64B Register + MB_SIZE + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB22_32B_WORD7 + Message Buffer 22 WORD_32B Register + MB_SIZE + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB38_16B_ID + Message Buffer 38 ID Register + MB_SIZE + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB57_8B_ID + Message Buffer 57 ID Register + MB_SIZE + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_64B_WORD12 + Message Buffer 12 WORD_64B Register + MB_SIZE + 0x418 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_32B_CS + Message Buffer 23 CS Register + MB_SIZE + 0x418 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB38_16B_WORD0 + Message Buffer 38 WORD_16B Register + MB_SIZE + 0x418 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB57_8B_WORD0 + Message Buffer 57 WORD_8B Register + MB_SIZE + 0x418 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD057 + Message Buffer 57 WORD0 Register + MB_SIZE + 0x418 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB12_64B_WORD13 + Message Buffer 12 WORD_64B Register + MB_SIZE + 0x41C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_32B_ID + Message Buffer 23 ID Register + MB_SIZE + 0x41C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB38_16B_WORD1 + Message Buffer 38 WORD_16B Register + MB_SIZE + 0x41C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB57_8B_WORD1 + Message Buffer 57 WORD_8B Register + MB_SIZE + 0x41C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD157 + Message Buffer 57 WORD1 Register + MB_SIZE + 0x41C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS58 + Message Buffer 58 CS Register + MB_SIZE + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB12_64B_WORD14 + Message Buffer 12 WORD_64B Register + MB_SIZE + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_32B_WORD0 + Message Buffer 23 WORD_32B Register + MB_SIZE + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB38_16B_WORD2 + Message Buffer 38 WORD_16B Register + MB_SIZE + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB58_8B_CS + Message Buffer 58 CS Register + MB_SIZE + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID58 + Message Buffer 58 ID Register + MB_SIZE + 0x424 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB12_64B_WORD15 + Message Buffer 12 WORD_64B Register + MB_SIZE + 0x424 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_32B_WORD1 + Message Buffer 23 WORD_32B Register + MB_SIZE + 0x424 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB38_16B_WORD3 + Message Buffer 38 WORD_16B Register + MB_SIZE + 0x424 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB58_8B_ID + Message Buffer 58 ID Register + MB_SIZE + 0x424 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB13_64B_CS + Message Buffer 13 CS Register + MB_SIZE + 0x428 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB23_32B_WORD2 + Message Buffer 23 WORD_32B Register + MB_SIZE + 0x428 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB39_16B_CS + Message Buffer 39 CS Register + MB_SIZE + 0x428 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB58_8B_WORD0 + Message Buffer 58 WORD_8B Register + MB_SIZE + 0x428 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD058 + Message Buffer 58 WORD0 Register + MB_SIZE + 0x428 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_64B_ID + Message Buffer 13 ID Register + MB_SIZE + 0x42C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB23_32B_WORD3 + Message Buffer 23 WORD_32B Register + MB_SIZE + 0x42C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB39_16B_ID + Message Buffer 39 ID Register + MB_SIZE + 0x42C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB58_8B_WORD1 + Message Buffer 58 WORD_8B Register + MB_SIZE + 0x42C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD158 + Message Buffer 58 WORD1 Register + MB_SIZE + 0x42C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS59 + Message Buffer 59 CS Register + MB_SIZE + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB13_64B_WORD0 + Message Buffer 13 WORD_64B Register + MB_SIZE + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_32B_WORD4 + Message Buffer 23 WORD_32B Register + MB_SIZE + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB39_16B_WORD0 + Message Buffer 39 WORD_16B Register + MB_SIZE + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB59_8B_CS + Message Buffer 59 CS Register + MB_SIZE + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID59 + Message Buffer 59 ID Register + MB_SIZE + 0x434 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB13_64B_WORD1 + Message Buffer 13 WORD_64B Register + MB_SIZE + 0x434 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_32B_WORD5 + Message Buffer 23 WORD_32B Register + MB_SIZE + 0x434 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB39_16B_WORD1 + Message Buffer 39 WORD_16B Register + MB_SIZE + 0x434 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB59_8B_ID + Message Buffer 59 ID Register + MB_SIZE + 0x434 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB13_64B_WORD2 + Message Buffer 13 WORD_64B Register + MB_SIZE + 0x438 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_32B_WORD6 + Message Buffer 23 WORD_32B Register + MB_SIZE + 0x438 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB39_16B_WORD2 + Message Buffer 39 WORD_16B Register + MB_SIZE + 0x438 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB59_8B_WORD0 + Message Buffer 59 WORD_8B Register + MB_SIZE + 0x438 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD059 + Message Buffer 59 WORD0 Register + MB_SIZE + 0x438 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_64B_WORD3 + Message Buffer 13 WORD_64B Register + MB_SIZE + 0x43C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB23_32B_WORD7 + Message Buffer 23 WORD_32B Register + MB_SIZE + 0x43C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB39_16B_WORD3 + Message Buffer 39 WORD_16B Register + MB_SIZE + 0x43C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB59_8B_WORD1 + Message Buffer 59 WORD_8B Register + MB_SIZE + 0x43C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD159 + Message Buffer 59 WORD1 Register + MB_SIZE + 0x43C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS60 + Message Buffer 60 CS Register + MB_SIZE + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB13_64B_WORD4 + Message Buffer 13 WORD_64B Register + MB_SIZE + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_19 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_18 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_17 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_16 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB40_16B_CS + Message Buffer 40 CS Register + MB_SIZE + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB60_8B_CS + Message Buffer 60 CS Register + MB_SIZE + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID60 + Message Buffer 60 ID Register + MB_SIZE + 0x444 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB13_64B_WORD5 + Message Buffer 13 WORD_64B Register + MB_SIZE + 0x444 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_23 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_22 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_21 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_20 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB40_16B_ID + Message Buffer 40 ID Register + MB_SIZE + 0x444 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB60_8B_ID + Message Buffer 60 ID Register + MB_SIZE + 0x444 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB13_64B_WORD6 + Message Buffer 13 WORD_64B Register + MB_SIZE + 0x448 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_27 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_26 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_25 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_24 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB40_16B_WORD0 + Message Buffer 40 WORD_16B Register + MB_SIZE + 0x448 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB60_8B_WORD0 + Message Buffer 60 WORD_8B Register + MB_SIZE + 0x448 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD060 + Message Buffer 60 WORD0 Register + MB_SIZE + 0x448 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_64B_WORD7 + Message Buffer 13 WORD_64B Register + MB_SIZE + 0x44C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_31 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_30 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_29 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_28 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB40_16B_WORD1 + Message Buffer 40 WORD_16B Register + MB_SIZE + 0x44C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB60_8B_WORD1 + Message Buffer 60 WORD_8B Register + MB_SIZE + 0x44C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD160 + Message Buffer 60 WORD1 Register + MB_SIZE + 0x44C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS61 + Message Buffer 61 CS Register + MB_SIZE + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB13_64B_WORD8 + Message Buffer 13 WORD_64B Register + MB_SIZE + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_35 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_34 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_33 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_32 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB40_16B_WORD2 + Message Buffer 40 WORD_16B Register + MB_SIZE + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB61_8B_CS + Message Buffer 61 CS Register + MB_SIZE + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID61 + Message Buffer 61 ID Register + MB_SIZE + 0x454 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB13_64B_WORD9 + Message Buffer 13 WORD_64B Register + MB_SIZE + 0x454 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_39 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_38 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_37 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_36 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB40_16B_WORD3 + Message Buffer 40 WORD_16B Register + MB_SIZE + 0x454 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB61_8B_ID + Message Buffer 61 ID Register + MB_SIZE + 0x454 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB13_64B_WORD10 + Message Buffer 13 WORD_64B Register + MB_SIZE + 0x458 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_43 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_42 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_41 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_40 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB41_16B_CS + Message Buffer 41 CS Register + MB_SIZE + 0x458 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB61_8B_WORD0 + Message Buffer 61 WORD_8B Register + MB_SIZE + 0x458 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD061 + Message Buffer 61 WORD0 Register + MB_SIZE + 0x458 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_64B_WORD11 + Message Buffer 13 WORD_64B Register + MB_SIZE + 0x45C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_47 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_46 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_45 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_44 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB41_16B_ID + Message Buffer 41 ID Register + MB_SIZE + 0x45C + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB61_8B_WORD1 + Message Buffer 61 WORD_8B Register + MB_SIZE + 0x45C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD161 + Message Buffer 61 WORD1 Register + MB_SIZE + 0x45C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS62 + Message Buffer 62 CS Register + MB_SIZE + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB13_64B_WORD12 + Message Buffer 13 WORD_64B Register + MB_SIZE + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_51 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_50 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_49 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_48 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB41_16B_WORD0 + Message Buffer 41 WORD_16B Register + MB_SIZE + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB62_8B_CS + Message Buffer 62 CS Register + MB_SIZE + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID62 + Message Buffer 62 ID Register + MB_SIZE + 0x464 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB13_64B_WORD13 + Message Buffer 13 WORD_64B Register + MB_SIZE + 0x464 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_55 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_54 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_53 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_52 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB41_16B_WORD1 + Message Buffer 41 WORD_16B Register + MB_SIZE + 0x464 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB62_8B_ID + Message Buffer 62 ID Register + MB_SIZE + 0x464 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB13_64B_WORD14 + Message Buffer 13 WORD_64B Register + MB_SIZE + 0x468 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_59 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_58 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_57 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_56 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB41_16B_WORD2 + Message Buffer 41 WORD_16B Register + MB_SIZE + 0x468 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_11 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_10 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_9 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_8 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB62_8B_WORD0 + Message Buffer 62 WORD_8B Register + MB_SIZE + 0x468 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD062 + Message Buffer 62 WORD0 Register + MB_SIZE + 0x468 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB13_64B_WORD15 + Message Buffer 13 WORD_64B Register + MB_SIZE + 0x46C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_63 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_62 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_61 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_60 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB41_16B_WORD3 + Message Buffer 41 WORD_16B Register + MB_SIZE + 0x46C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_15 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_14 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_13 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_12 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB62_8B_WORD1 + Message Buffer 62 WORD_8B Register + MB_SIZE + 0x46C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD162 + Message Buffer 62 WORD1 Register + MB_SIZE + 0x46C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + CS63 + Message Buffer 63 CS Register + MB_SIZE + 0x470 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + MB63_8B_CS + Message Buffer 63 CS Register + MB_SIZE + 0x470 + 32 + read-write + 0 + 0xFFFFFFFF + + + TIME_STAMP + Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. + 0 + 16 + read-write + + + DLC + Length of the data to be stored/transmitted. + 16 + 4 + read-write + + + RTR + Remote Transmission Request. One/zero for remote/data frame. + 20 + 1 + read-write + + + IDE + ID Extended. One/zero for extended/standard format frame. + 21 + 1 + read-write + + + SRR + Substitute Remote Request. Contains a fixed recessive bit. + 22 + 1 + read-write + + + CODE + Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. + 24 + 4 + read-write + + + ESI + Error State Indicator. This bit indicates if the transmitting node is error active or error passive. + 29 + 1 + read-write + + + BRS + Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. + 30 + 1 + read-write + + + EDL + Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + 31 + 1 + read-write + + + + + ID63 + Message Buffer 63 ID Register + MB_SIZE + 0x474 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB63_8B_ID + Message Buffer 63 ID Register + MB_SIZE + 0x474 + 32 + read-write + 0 + 0xFFFFFFFF + + + EXT + Contains extended (LOW word) identifier of message buffer. + 0 + 18 + read-write + + + STD + Contains standard/extended (HIGH word) identifier of message buffer. + 18 + 11 + read-write + + + PRIO + Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. + 29 + 3 + read-write + + + + + MB63_8B_WORD0 + Message Buffer 63 WORD_8B Register + MB_SIZE + 0x478 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD063 + Message Buffer 63 WORD0 Register + MB_SIZE + 0x478 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_3 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_2 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_1 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_0 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + MB63_8B_WORD1 + Message Buffer 63 WORD_8B Register + MB_SIZE + 0x47C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + WORD163 + Message Buffer 63 WORD1 Register + MB_SIZE + 0x47C + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_BYTE_7 + Data byte 0 of Rx/Tx frame. + 0 + 8 + read-write + + + DATA_BYTE_6 + Data byte 1 of Rx/Tx frame. + 8 + 8 + read-write + + + DATA_BYTE_5 + Data byte 2 of Rx/Tx frame. + 16 + 8 + read-write + + + DATA_BYTE_4 + Data byte 3 of Rx/Tx frame. + 24 + 8 + read-write + + + + + 64 + 0x4 + RXIMR[%s] + Rx Individual Mask Registers + 0x880 + 32 + read-write + 0 + 0 + + + MI + Individual Mask Bits + 0 + 32 + read-write + + + + + EPRS + Enhanced CAN Bit Timing Prescalers + 0xBF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENPRESDIV + Extended Nominal Prescaler Division Factor + 0 + 10 + read-write + + + EDPRESDIV + Extended Data Phase Prescaler Division Factor + 16 + 10 + read-write + + + + + ENCBT + Enhanced Nominal CAN Bit Timing + 0xBF4 + 32 + read-write + 0 + 0xFFFFFFFF + + + NTSEG1 + Nominal Time Segment 1 + 0 + 8 + read-write + + + NTSEG2 + Nominal Time Segment 2 + 12 + 7 + read-write + + + NRJW + Nominal Resynchronization Jump Width + 22 + 7 + read-write + + + + + EDCBT + Enhanced Data Phase CAN bit Timing + 0xBF8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DTSEG1 + Data Phase Segment 1 + 0 + 5 + read-write + + + DTSEG2 + Data Phase Time Segment 2 + 12 + 4 + read-write + + + DRJW + Data Phase Resynchronization Jump Width + 22 + 4 + read-write + + + + + ETDC + Enhanced Transceiver Delay Compensation + 0xBFC + 32 + read-write + 0 + 0xFFFFFFFF + + + ETDCVAL + Enhanced Transceiver Delay Compensation Value + 0 + 8 + read-only + + + ETDCOFF + Enhanced Transceiver Delay Compensation Offset + 16 + 7 + read-write + + + TDMDIS + Transceiver Delay Measurement Disable + 31 + 1 + read-write + + + TDMDIS_0 + TDC measurement is enabled + 0 + + + TDMDIS_1 + TDC measurement is disabled + 0x1 + + + + + + + FDCTRL + CAN FD Control Register + 0xC00 + 32 + read-write + 0x80000100 + 0xFFFFFFFF + + + TDCVAL + Transceiver Delay Compensation Value + 0 + 6 + read-only + + + TDCOFF + Transceiver Delay Compensation Offset + 8 + 5 + read-write + + + TDCFAIL + Transceiver Delay Compensation Fail + 14 + 1 + read-write + oneToClear + + + TDCFAIL_0 + Measured loop delay is in range. + 0 + + + TDCFAIL_1 + Measured loop delay is out of range. + 0x1 + + + + + TDCEN + Transceiver Delay Compensation Enable + 15 + 1 + read-write + + + TDCEN_0 + TDC is disabled + 0 + + + TDCEN_1 + TDC is enabled + 0x1 + + + + + MBDSR0 + Message Buffer Data Size for Region 0 + 16 + 2 + read-write + + + MBDSR0_0 + Selects 8 bytes per Message Buffer. + 0 + + + MBDSR0_1 + Selects 16 bytes per Message Buffer. + 0x1 + + + MBDSR0_2 + Selects 32 bytes per Message Buffer. + 0x2 + + + MBDSR0_3 + Selects 64 bytes per Message Buffer. + 0x3 + + + + + MBDSR1 + Message Buffer Data Size for Region 1 + 19 + 2 + read-write + + + MBDSR1_0 + Selects 8 bytes per Message Buffer. + 0 + + + MBDSR1_1 + Selects 16 bytes per Message Buffer. + 0x1 + + + MBDSR1_2 + Selects 32 bytes per Message Buffer. + 0x2 + + + MBDSR1_3 + Selects 64 bytes per Message Buffer. + 0x3 + + + + + FDRATE + Bit Rate Switch Enable + 31 + 1 + read-write + + + FDRATE_0 + Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect. + 0 + + + FDRATE_1 + Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive. + 0x1 + + + + + + + FDCBT + CAN FD Bit Timing Register + 0xC04 + 32 + read-write + 0 + 0xFFFFFFFF + + + FPSEG2 + Fast Phase Segment 2 + 0 + 3 + read-write + + + FPSEG1 + Fast Phase Segment 1 + 5 + 3 + read-write + + + FPROPSEG + Fast Propagation Segment + 10 + 5 + read-write + + + FRJW + Fast Resync Jump Width + 16 + 3 + read-write + + + FPRESDIV + Fast Prescaler Division Factor + 20 + 10 + read-write + + + + + FDCRC + CAN FD CRC Register + 0xC08 + 32 + read-only + 0 + 0xFFFFFFFF + + + FD_TXCRC + Extended Transmitted CRC value + 0 + 21 + read-only + + + FD_MBCRC + CRC Mailbox Number for FD_TXCRC + 24 + 7 + read-only + + + + + ERFCR + Enhanced Rx FIFO Control Register + 0xC0C + 32 + read-write + 0 + 0xFFFFFFFF + + + ERFWM + Enhanced Rx FIFO Watermark + 0 + 5 + read-write + + + NFE + Number of Enhanced Rx FIFO Filter Elements + 8 + 6 + read-write + + + NEXIF + Number of Extended ID Filter Elements + 16 + 7 + read-write + + + DMALW + DMA Last Word + 26 + 5 + read-write + + + ERFEN + Enhanced Rx FIFO enable + 31 + 1 + read-write + + + ERFEN_0 + Enhanced Rx FIFO is disabled + 0 + + + ERFEN_1 + Enhanced Rx FIFO is enabled + 0x1 + + + + + + + ERFIER + Enhanced Rx FIFO Interrupt Enable register + 0xC10 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERFDAIE + Enhanced Rx FIFO Data Available Interrupt Enable + 28 + 1 + read-write + + + ERFDAIE_0 + Enhanced Rx FIFO Data Available Interrupt is disabled + 0 + + + ERFDAIE_1 + Enhanced Rx FIFO Data Available Interrupt is enabled + 0x1 + + + + + ERFWMIIE + Enhanced Rx FIFO Watermark Indication Interrupt Enable + 29 + 1 + read-write + + + ERFWMIIE_0 + Enhanced Rx FIFO Watermark Interrupt is disabled + 0 + + + ERFWMIIE_1 + Enhanced Rx FIFO Watermark Interrupt is enabled + 0x1 + + + + + ERFOVFIE + Enhanced Rx FIFO Overflow Interrupt Enable + 30 + 1 + read-write + + + ERFOVFIE_0 + Enhanced Rx FIFO Overflow is disabled + 0 + + + ERFOVFIE_1 + Enhanced Rx FIFO Overflow is enabled + 0x1 + + + + + ERFUFWIE + Enhanced Rx FIFO Underflow Interrupt Enable + 31 + 1 + read-write + + + ERFUFWIE_0 + Enhanced Rx FIFO Underflow interrupt is disabled + 0 + + + ERFUFWIE_1 + Enhanced Rx FIFO Underflow interrupt is enabled + 0x1 + + + + + + + ERFSR + Enhanced Rx FIFO Status Register + 0xC14 + 32 + read-write + 0 + 0xFFFFFFFF + + + ERFEL + Enhanced Rx FIFO Elements + 0 + 6 + read-only + + + ERFF + Enhanced Rx FIFO full + 16 + 1 + read-only + + + ERFF_0 + Enhanced Rx FIFO is not full + 0 + + + ERFF_1 + Enhanced Rx FIFO is full + 0x1 + + + + + ERFE + Enhanced Rx FIFO empty + 17 + 1 + read-only + + + ERFE_0 + Enhanced Rx FIFO is not empty + 0 + + + ERFE_1 + Enhanced Rx FIFO is empty + 0x1 + + + + + ERFCLR + Enhanced Rx FIFO Clear + 27 + 1 + read-write + + + ERFCLR_0 + No effect + 0 + + + ERFCLR_1 + Clear Enhanced Rx FIFO content + 0x1 + + + + + ERFDA + Enhanced Rx FIFO Data Available + 28 + 1 + read-write + oneToClear + + + ERFDA_0 + No such occurrence + 0 + + + ERFDA_1 + There is at least one message stored in Enhanced Rx FIFO + 0x1 + + + + + ERFWMI + Enhanced Rx FIFO Watermark Indication + 29 + 1 + read-write + oneToClear + + + ERFWMI_0 + No such occurrence + 0 + + + ERFWMI_1 + The number of messages in FIFO is greater than the watermark + 0x1 + + + + + ERFOVF + Enhanced Rx FIFO Overflow + 30 + 1 + read-write + oneToClear + + + ERFOVF_0 + No such occurrence + 0 + + + ERFOVF_1 + Enhanced Rx FIFO overflow + 0x1 + + + + + ERFUFW + Enhanced Rx FIFO Underflow + 31 + 1 + read-write + oneToClear + + + ERFUFW_0 + No such occurrence + 0 + + + ERFUFW_1 + Enhanced Rx FIFO underflow + 0x1 + + + + + + + 64 + 0x4 + HR_TIME_STAMP[%s] + High Resolution Time Stamp + 0xC30 + 32 + read-only + 0 + 0 + + + TS + High Resolution Time Stamp + 0 + 32 + read-only + + + + + 128 + 0x4 + ERFFEL[%s] + Enhanced Rx FIFO Filter Element + 0x3000 + 32 + read-write + 0 + 0 + + + FEL + Filter Element Bits + 0 + 32 + read-write + + + + + + + TMR1 + Quad Timer + TMR + TMR1_ + TMR + 0x401DC000 + + 0 + 0x7A + registers + + + TMR1 + 133 + + + + 4 + 0x20 + 0,1,2,3 + COMP1%s + Timer Channel Compare Register 1 + 0 + 16 + read-write + 0 + 0xFFFF + + + COMPARISON_1 + Comparison Value 1 + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + COMP2%s + Timer Channel Compare Register 2 + 0x2 + 16 + read-write + 0 + 0xFFFF + + + COMPARISON_2 + Comparison Value 2 + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CAPT%s + Timer Channel Capture Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + CAPTURE + Capture Value + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + LOAD%s + Timer Channel Load Register + 0x6 + 16 + read-write + 0 + 0xFFFF + + + LOAD + Timer Load Register + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + HOLD%s + Timer Channel Hold Register + 0x8 + 16 + read-write + 0 + 0xFFFF + + + HOLD + This read/write register stores the counter's values of specific channels whenever any of the four counters within a module is read + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CNTR%s + Timer Channel Counter Register + 0xA + 16 + read-write + 0 + 0xFFFF + + + COUNTER + This read/write register is the counter for the corresponding channel in a timer module. + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CTRL%s + Timer Channel Control Register + 0xC + 16 + read-write + 0 + 0xFFFF + + + OUTMODE + Output Mode + 0 + 3 + read-write + + + OUTMODE_0 + Asserted while counter is active + 0 + + + OUTMODE_1 + Clear OFLAG output on successful compare + 0x1 + + + OUTMODE_2 + Set OFLAG output on successful compare + 0x2 + + + OUTMODE_3 + Toggle OFLAG output on successful compare + 0x3 + + + OUTMODE_4 + Toggle OFLAG output using alternating compare registers + 0x4 + + + OUTMODE_5 + Set on compare, cleared on secondary source input edge + 0x5 + + + OUTMODE_6 + Set on compare, cleared on counter rollover + 0x6 + + + OUTMODE_7 + Enable gated clock output while counter is active + 0x7 + + + + + COINIT + Co-Channel Initialization + 3 + 1 + read-write + + + COINIT_0 + Co-channel counter/timers cannot force a re-initialization of this counter/timer + 0 + + + COINIT_1 + Co-channel counter/timers may force a re-initialization of this counter/timer + 0x1 + + + + + DIR + Count Direction + 4 + 1 + read-write + + + DIR_0 + Count up. + 0 + + + DIR_1 + Count down. + 0x1 + + + + + LENGTH + Count Length + 5 + 1 + read-write + + + LENGTH_0 + Count until roll over at $FFFF and continue from $0000. + 0 + + + LENGTH_1 + Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on. + 0x1 + + + + + ONCE + Count Once + 6 + 1 + read-write + + + ONCE_0 + Count repeatedly. + 0 + + + ONCE_1 + Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops. + 0x1 + + + + + SCS + Secondary Count Source + 7 + 2 + read-write + + + SCS_0 + Counter 0 input pin + 0 + + + SCS_1 + Counter 1 input pin + 0x1 + + + SCS_2 + Counter 2 input pin + 0x2 + + + SCS_3 + Counter 3 input pin + 0x3 + + + + + PCS + Primary Count Source + 9 + 4 + read-write + + + PCS_0 + Counter 0 input pin + 0 + + + PCS_1 + Counter 1 input pin + 0x1 + + + PCS_2 + Counter 2 input pin + 0x2 + + + PCS_3 + Counter 3 input pin + 0x3 + + + PCS_4 + Counter 0 output + 0x4 + + + PCS_5 + Counter 1 output + 0x5 + + + PCS_6 + Counter 2 output + 0x6 + + + PCS_7 + Counter 3 output + 0x7 + + + PCS_8 + IP bus clock divide by 1 prescaler + 0x8 + + + PCS_9 + IP bus clock divide by 2 prescaler + 0x9 + + + PCS_10 + IP bus clock divide by 4 prescaler + 0xA + + + PCS_11 + IP bus clock divide by 8 prescaler + 0xB + + + PCS_12 + IP bus clock divide by 16 prescaler + 0xC + + + PCS_13 + IP bus clock divide by 32 prescaler + 0xD + + + PCS_14 + IP bus clock divide by 64 prescaler + 0xE + + + PCS_15 + IP bus clock divide by 128 prescaler + 0xF + + + + + CM + Count Mode + 13 + 3 + read-write + + + CM_0 + No operation + 0 + + + CM_1 + Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS]. + 0x1 + + + CM_2 + Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. + 0x2 + + + CM_3 + Count rising edges of primary source while secondary input high active + 0x3 + + + CM_4 + Quadrature count mode, uses primary and secondary sources + 0x4 + + + CM_5 + Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. + 0x5 + + + CM_6 + Edge of secondary source triggers primary count until compare + 0x6 + + + CM_7 + Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs. + 0x7 + + + + + + + 4 + 0x20 + 0,1,2,3 + SCTRL%s + Timer Channel Status and Control Register + 0xE + 16 + read-write + 0 + 0xFFFF + + + OEN + Output Enable + 0 + 1 + read-write + + + OEN_0 + The external pin is configured as an input. + 0 + + + OEN_1 + The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS. + 0x1 + + + + + OPS + Output Polarity Select + 1 + 1 + read-write + + + OPS_0 + True polarity. + 0 + + + OPS_1 + Inverted polarity. + 0x1 + + + + + FORCE + Force OFLAG Output + 2 + 1 + read-write + + + VAL + Forced OFLAG Value + 3 + 1 + read-write + + + EEOF + Enable External OFLAG Force + 4 + 1 + read-write + + + MSTR + Master Mode + 5 + 1 + read-write + + + CAPTURE_MODE + Input Capture Mode + 6 + 2 + read-write + + + CAPTURE_MODE_0 + Capture function is disabled + 0 + + + CAPTURE_MODE_1 + Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input + 0x1 + + + CAPTURE_MODE_2 + Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input + 0x2 + + + CAPTURE_MODE_3 + Load capture register on both edges of input + 0x3 + + + + + INPUT + External Input Signal + 8 + 1 + read-only + + + IPS + Input Polarity Select + 9 + 1 + read-write + + + IEFIE + Input Edge Flag Interrupt Enable + 10 + 1 + read-write + + + IEF + Input Edge Flag + 11 + 1 + read-write + + + TOFIE + Timer Overflow Flag Interrupt Enable + 12 + 1 + read-write + + + TOF + Timer Overflow Flag + 13 + 1 + read-write + + + TCFIE + Timer Compare Flag Interrupt Enable + 14 + 1 + read-write + + + TCF + Timer Compare Flag + 15 + 1 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CMPLD1%s + Timer Channel Comparator Load Register 1 + 0x10 + 16 + read-write + 0 + 0xFFFF + + + COMPARATOR_LOAD_1 + This read/write register is the comparator 1 preload value for the COMP1 register for the corresponding channel in a timer module + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CMPLD2%s + Timer Channel Comparator Load Register 2 + 0x12 + 16 + read-write + 0 + 0xFFFF + + + COMPARATOR_LOAD_2 + This read/write register is the comparator 2 preload value for the COMP2 register for the corresponding channel in a timer module + 0 + 16 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + CSCTRL%s + Timer Channel Comparator Status and Control Register + 0x14 + 16 + read-write + 0 + 0xFFFF + + + CL1 + Compare Load Control 1 + 0 + 2 + read-write + + + CL1_0 + Never preload + 0 + + + CL1_1 + Load upon successful compare with the value in COMP1 + 0x1 + + + CL1_2 + Load upon successful compare with the value in COMP2 + 0x2 + + + + + CL2 + Compare Load Control 2 + 2 + 2 + read-write + + + CL2_0 + Never preload + 0 + + + CL2_1 + Load upon successful compare with the value in COMP1 + 0x1 + + + CL2_2 + Load upon successful compare with the value in COMP2 + 0x2 + + + + + TCF1 + Timer Compare 1 Interrupt Flag + 4 + 1 + read-write + + + TCF2 + Timer Compare 2 Interrupt Flag + 5 + 1 + read-write + + + TCF1EN + Timer Compare 1 Interrupt Enable + 6 + 1 + read-write + + + TCF2EN + Timer Compare 2 Interrupt Enable + 7 + 1 + read-write + + + UP + Counting Direction Indicator + 9 + 1 + read-only + + + UP_0 + The last count was in the DOWN direction. + 0 + + + UP_1 + The last count was in the UP direction. + 0x1 + + + + + TCI + Triggered Count Initialization Control + 10 + 1 + read-write + + + TCI_0 + Stop counter upon receiving a second trigger event while still counting from the first trigger event. + 0 + + + TCI_1 + Reload the counter upon receiving a second trigger event while still counting from the first trigger event. + 0x1 + + + + + ROC + Reload on Capture + 11 + 1 + read-write + + + ROC_0 + Do not reload the counter on a capture event. + 0 + + + ROC_1 + Reload the counter on a capture event. + 0x1 + + + + + ALT_LOAD + Alternative Load Enable + 12 + 1 + read-write + + + ALT_LOAD_0 + Counter can be re-initialized only with the LOAD register. + 0 + + + ALT_LOAD_1 + Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction. + 0x1 + + + + + FAULT + Fault Enable + 13 + 1 + read-write + + + FAULT_0 + Fault function disabled. + 0 + + + FAULT_1 + Fault function enabled. + 0x1 + + + + + DBG_EN + Debug Actions Enable + 14 + 2 + read-write + + + DBG_EN_0 + Continue with normal operation during debug mode. (default) + 0 + + + DBG_EN_1 + Halt TMR counter during debug mode. + 0x1 + + + DBG_EN_2 + Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). + 0x2 + + + DBG_EN_3 + Both halt counter and force output to 0 during debug mode. + 0x3 + + + + + + + 4 + 0x20 + 0,1,2,3 + FILT%s + Timer Channel Input Filter Register + 0x16 + 16 + read-write + 0 + 0xFFFF + + + FILT_PER + Input Filter Sample Period + 0 + 8 + read-write + + + FILT_CNT + Input Filter Sample Count + 8 + 3 + read-write + + + + + 4 + 0x20 + 0,1,2,3 + DMA%s + Timer Channel DMA Enable Register + 0x18 + 16 + read-write + 0 + 0xFFFF + + + IEFDE + Input Edge Flag DMA Enable + 0 + 1 + read-write + + + CMPLD1DE + Comparator Preload Register 1 DMA Enable + 1 + 1 + read-write + + + CMPLD2DE + Comparator Preload Register 2 DMA Enable + 2 + 1 + read-write + + + + + ENBL + Timer Channel Enable Register + 0x1E + 16 + read-write + 0xF + 0xFFFF + + + ENBL + Timer Channel Enable + 0 + 4 + read-write + + + ENBL_0 + Timer channel is disabled. + 0 + + + ENBL_1 + Timer channel is enabled. (default) + 0x1 + + + + + + + + + TMR2 + Quad Timer + TMR + TMR2_ + 0x401E0000 + + 0 + 0x7A + registers + + + TMR2 + 134 + + + + TMR3 + Quad Timer + TMR + TMR3_ + 0x401E4000 + + 0 + 0x7A + registers + + + TMR3 + 135 + + + + TMR4 + Quad Timer + TMR + TMR4_ + 0x401E8000 + + 0 + 0x7A + registers + + + TMR4 + 136 + + + + GPT1 + GPT + GPT + GPT1_ + GPT + 0x401EC000 + + 0 + 0x28 + registers + + + GPT1 + 100 + + + + CR + GPT Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + GPT Enable + 0 + 1 + read-write + + + EN_0 + GPT is disabled. + 0 + + + EN_1 + GPT is enabled. + 0x1 + + + + + ENMOD + GPT Enable mode + 1 + 1 + read-write + + + ENMOD_0 + GPT counter will retain its value when it is disabled. + 0 + + + ENMOD_1 + GPT counter value is reset to 0 when it is disabled. + 0x1 + + + + + DBGEN + GPT debug mode enable + 2 + 1 + read-write + + + DBGEN_0 + GPT is disabled in debug mode. + 0 + + + DBGEN_1 + GPT is enabled in debug mode. + 0x1 + + + + + WAITEN + GPT Wait Mode enable + 3 + 1 + read-write + + + WAITEN_0 + GPT is disabled in wait mode. + 0 + + + WAITEN_1 + GPT is enabled in wait mode. + 0x1 + + + + + DOZEEN + GPT Doze Mode Enable + 4 + 1 + read-write + + + DOZEEN_0 + GPT is disabled in doze mode. + 0 + + + DOZEEN_1 + GPT is enabled in doze mode. + 0x1 + + + + + STOPEN + GPT Stop Mode enable + 5 + 1 + read-write + + + STOPEN_0 + GPT is disabled in Stop mode. + 0 + + + STOPEN_1 + GPT is enabled in Stop mode. + 0x1 + + + + + CLKSRC + Clock Source select + 6 + 3 + read-write + + + CLKSRC_0 + No clock + 0 + + + CLKSRC_1 + Peripheral Clock (ipg_clk) + 0x1 + + + CLKSRC_2 + High Frequency Reference Clock (ipg_clk_highfreq) + 0x2 + + + CLKSRC_3 + External Clock + 0x3 + + + CLKSRC_4 + Low Frequency Reference Clock (ipg_clk_32k) + 0x4 + + + CLKSRC_5 + Crystal oscillator as Reference Clock (ipg_clk_24M) + 0x5 + + + + + FRR + Free-Run or Restart mode + 9 + 1 + read-write + + + FRR_0 + Restart mode + 0 + + + FRR_1 + Free-Run mode + 0x1 + + + + + EN_24M + Enable 24 MHz clock input from crystal + 10 + 1 + read-write + + + EN_24M_0 + 24M clock disabled + 0 + + + EN_24M_1 + 24M clock enabled + 0x1 + + + + + SWR + Software reset + 15 + 1 + read-write + + + SWR_0 + GPT is not in reset state + 0 + + + SWR_1 + GPT is in reset state + 0x1 + + + + + IM1 + See IM2 + 16 + 2 + read-write + + + IM2 + IM2 (bits 19-18, Input Capture Channel 2 operating mode) IM1 (bits 17-16, Input Capture Channel 1 operating mode) The IMn bit field determines the transition on the input pin (for Input capture channel n), which will trigger a capture event + 18 + 2 + read-write + + + IM2_0 + capture disabled + 0 + + + IM2_1 + capture on rising edge only + 0x1 + + + IM2_2 + capture on falling edge only + 0x2 + + + IM2_3 + capture on both edges + 0x3 + + + + + OM1 + See OM3 + 20 + 3 + read-write + + + OM2 + See OM3 + 23 + 3 + read-write + + + OM3 + OM3 (bits 28-26) controls the Output Compare Channel 3 operating mode + 26 + 3 + read-write + + + OM3_0 + Output disconnected. No response on pin. + 0 + + + OM3_1 + Toggle output pin + 0x1 + + + OM3_2 + Clear output pin + 0x2 + + + OM3_3 + Set output pin + 0x3 + + + OM3_4 + Generate an active low pulse (that is one input clock wide) on the output pin. + #1xx + + + + + FO1 + See F03 + 29 + 1 + read-write + + + FO2 + See F03 + 30 + 1 + read-write + + + FO3 + FO3 Force Output Compare Channel 3 FO2 Force Output Compare Channel 2 FO1 Force Output Compare Channel 1 The FOn bit causes the pin action programmed for the timer Output Compare n pin (according to the OMn bits in this register) + 31 + 1 + read-write + + + FO3_0 + Writing a 0 has no effect. + 0 + + + FO3_1 + Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set. + 0x1 + + + + + + + PR + GPT Prescaler Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRESCALER + Prescaler bits + 0 + 12 + read-write + + + PRESCALER_0 + Divide by 1 + 0 + + + PRESCALER_1 + Divide by 2 + 0x1 + + + PRESCALER_4095 + Divide by 4096 + 0xFFF + + + + + PRESCALER24M + Prescaler bits + 12 + 4 + read-write + + + PRESCALER24M_0 + Divide by 1 + 0 + + + PRESCALER24M_1 + Divide by 2 + 0x1 + + + PRESCALER24M_15 + Divide by 16 + 0xF + + + + + + + SR + GPT Status Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + OF1 + See OF3 + 0 + 1 + read-write + oneToClear + + + OF2 + See OF3 + 1 + 1 + read-write + oneToClear + + + OF3 + OF3 Output Compare 3 Flag OF2 Output Compare 2 Flag OF1 Output Compare 1 Flag The OFn bit indicates that a compare event has occurred on Output Compare channel n + 2 + 1 + read-write + oneToClear + + + OF3_0 + Compare event has not occurred. + 0 + + + OF3_1 + Compare event has occurred. + 0x1 + + + + + IF1 + See IF2 + 3 + 1 + read-write + oneToClear + + + IF2 + IF2 Input capture 2 Flag IF1 Input capture 1 Flag The IFn bit indicates that a capture event has occurred on Input Capture channel n + 4 + 1 + read-write + oneToClear + + + IF2_0 + Capture event has not occurred. + 0 + + + IF2_1 + Capture event has occurred. + 0x1 + + + + + ROV + Rollover Flag + 5 + 1 + read-write + oneToClear + + + ROV_0 + Rollover has not occurred. + 0 + + + ROV_1 + Rollover has occurred. + 0x1 + + + + + + + IR + GPT Interrupt Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + OF1IE + See OF3IE + 0 + 1 + read-write + + + OF2IE + See OF3IE + 1 + 1 + read-write + + + OF3IE + OF3IE Output Compare 3 Interrupt Enable OF2IE Output Compare 2 Interrupt Enable OF1IE Output Compare 1 Interrupt Enable The OFnIE bit controls the Output Compare Channel n interrupt + 2 + 1 + read-write + + + OF3IE_0 + Output Compare Channel n interrupt is disabled. + 0 + + + OF3IE_1 + Output Compare Channel n interrupt is enabled. + 0x1 + + + + + IF1IE + See IF2IE + 3 + 1 + read-write + + + IF2IE + IF2IE Input capture 2 Interrupt Enable IF1IE Input capture 1 Interrupt Enable The IFnIE bit controls the IFnIE Input Capture n Interrupt Enable + 4 + 1 + read-write + + + IF2IE_0 + IF2IE Input Capture n Interrupt Enable is disabled. + 0 + + + IF2IE_1 + IF2IE Input Capture n Interrupt Enable is enabled. + 0x1 + + + + + ROVIE + Rollover Interrupt Enable. The ROVIE bit controls the Rollover interrupt. + 5 + 1 + read-write + + + ROVIE_0 + Rollover interrupt is disabled. + 0 + + + ROVIE_1 + Rollover interrupt enabled. + 0x1 + + + + + + + OCR1 + GPT Output Compare Register 1 + 0x10 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + OCR2 + GPT Output Compare Register 2 + 0x14 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + OCR3 + GPT Output Compare Register 3 + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + COMP + Compare Value + 0 + 32 + read-write + + + + + ICR1 + GPT Input Capture Register 1 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPT + Capture Value + 0 + 32 + read-only + + + + + ICR2 + GPT Input Capture Register 2 + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + CAPT + Capture Value + 0 + 32 + read-only + + + + + CNT + GPT Counter Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Counter Value. The COUNT bits show the current count value of the GPT counter. + 0 + 32 + read-only + + + + + + + GPT2 + GPT + GPT + GPT2_ + 0x401F0000 + + 0 + 0x28 + registers + + + GPT2 + 101 + + + + OCOTP + OCOTP + OCOTP + 0x401F4000 + + 0 + 0x8F4 + registers + + + + CTRL + OTP Controller Control Register + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + ADDR + 0 + 6 + read-write + + + RSVD0 + RSVD0 + 6 + 2 + read-only + + + BUSY + BUSY + 8 + 1 + read-only + + + ERROR + ERROR + 9 + 1 + read-write + + + RELOAD_SHADOWS + RELOAD_SHADOWS + 10 + 1 + read-write + + + CRC_TEST + CRC_TEST + 11 + 1 + read-write + + + CRC_FAIL + CRC_FAIL + 12 + 1 + read-write + + + RSVD1 + RSVD1 + 13 + 3 + read-only + + + WR_UNLOCK + WR_UNLOCK + 16 + 16 + read-write + + + KEY + Key needed to unlock HW_OCOTP_DATA register. + 0x3E77 + + + + + + + CTRL_SET + OTP Controller Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + ADDR + 0 + 6 + read-write + oneToSet + + + RSVD0 + RSVD0 + 6 + 2 + read-only + oneToSet + + + BUSY + BUSY + 8 + 1 + read-only + oneToSet + + + ERROR + ERROR + 9 + 1 + read-write + oneToSet + + + RELOAD_SHADOWS + RELOAD_SHADOWS + 10 + 1 + read-write + oneToSet + + + CRC_TEST + CRC_TEST + 11 + 1 + read-write + oneToSet + + + CRC_FAIL + CRC_FAIL + 12 + 1 + read-write + oneToSet + + + RSVD1 + RSVD1 + 13 + 3 + read-only + oneToSet + + + WR_UNLOCK + WR_UNLOCK + 16 + 16 + read-write + oneToSet + + + + + CTRL_CLR + OTP Controller Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + ADDR + 0 + 6 + read-write + oneToClear + + + RSVD0 + RSVD0 + 6 + 2 + read-only + oneToClear + + + BUSY + BUSY + 8 + 1 + read-only + oneToClear + + + ERROR + ERROR + 9 + 1 + read-write + oneToClear + + + RELOAD_SHADOWS + RELOAD_SHADOWS + 10 + 1 + read-write + oneToClear + + + CRC_TEST + CRC_TEST + 11 + 1 + read-write + oneToClear + + + CRC_FAIL + CRC_FAIL + 12 + 1 + read-write + oneToClear + + + RSVD1 + RSVD1 + 13 + 3 + read-only + oneToClear + + + WR_UNLOCK + WR_UNLOCK + 16 + 16 + read-write + oneToClear + + + + + CTRL_TOG + OTP Controller Control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + ADDR + 0 + 6 + read-write + oneToToggle + + + RSVD0 + RSVD0 + 6 + 2 + read-only + oneToToggle + + + BUSY + BUSY + 8 + 1 + read-only + oneToToggle + + + ERROR + ERROR + 9 + 1 + read-write + oneToToggle + + + RELOAD_SHADOWS + RELOAD_SHADOWS + 10 + 1 + read-write + oneToToggle + + + CRC_TEST + CRC_TEST + 11 + 1 + read-write + oneToToggle + + + CRC_FAIL + CRC_FAIL + 12 + 1 + read-write + oneToToggle + + + RSVD1 + RSVD1 + 13 + 3 + read-only + oneToToggle + + + WR_UNLOCK + WR_UNLOCK + 16 + 16 + read-write + oneToToggle + + + + + TIMING + OTP Controller Timing Register + 0x10 + 32 + read-write + 0xC0D9755 + 0xFFFFFFFF + + + STROBE_PROG + STROBE_PROG + 0 + 12 + read-write + + + RELAX + RELAX + 12 + 4 + read-write + + + STROBE_READ + STROBE_READ + 16 + 6 + read-write + + + WAIT + WAIT + 22 + 6 + read-write + + + RSRVD0 + RSRVD0 + 28 + 4 + read-only + + + + + DATA + OTP Controller Write Data Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + DATA + 0 + 32 + read-write + + + + + READ_CTRL + OTP Controller Write Data Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + READ_FUSE + READ_FUSE + 0 + 1 + read-write + + + RSVD0 + RSVD0 + 1 + 31 + read-only + + + + + READ_FUSE_DATA + OTP Controller Read Data Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + DATA + 0 + 32 + read-write + + + + + SW_STICKY + Sticky bit Register + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + BLOCK_DTCP_KEY + BLOCK_DTCP_KEY + 0 + 1 + read-write + + + SRK_REVOKE_LOCK + SRK_REVOKE_LOCK + 1 + 1 + read-write + + + FIELD_RETURN_LOCK + FIELD_RETURN_LOCK + 2 + 1 + read-write + + + BLOCK_ROM_PART + BLOCK_ROM_PART + 3 + 1 + read-write + + + JTAG_BLOCK_RELEASE + JTAG_BLOCK_RELEASE + 4 + 1 + read-write + + + RSVD0 + RSVD0 + 5 + 27 + read-only + + + + + SCS + Software Controllable Signals Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB_JDE + 0 + 1 + read-write + + + SPARE + SPARE + 1 + 30 + read-write + + + LOCK + LOCK + 31 + 1 + read-write + + + + + SCS_SET + Software Controllable Signals Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB_JDE + 0 + 1 + read-write + oneToSet + + + SPARE + SPARE + 1 + 30 + read-write + oneToSet + + + LOCK + LOCK + 31 + 1 + read-write + oneToSet + + + + + SCS_CLR + Software Controllable Signals Register + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB_JDE + 0 + 1 + read-write + oneToClear + + + SPARE + SPARE + 1 + 30 + read-write + oneToClear + + + LOCK + LOCK + 31 + 1 + read-write + oneToClear + + + + + SCS_TOG + Software Controllable Signals Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + HAB_JDE + HAB_JDE + 0 + 1 + read-write + oneToToggle + + + SPARE + SPARE + 1 + 30 + read-write + oneToToggle + + + LOCK + LOCK + 31 + 1 + read-write + oneToToggle + + + + + CRC_ADDR + OTP Controller CRC test address + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA_START_ADDR + DATA_START_ADDR + 0 + 8 + read-write + + + DATA_END_ADDR + DATA_END_ADDR + 8 + 8 + read-write + + + CRC_ADDR + CRC_ADDR + 16 + 8 + read-write + + + OTPMK_CRC + OTPMK_CRC + 24 + 1 + read-write + + + RSVD0 + RSVD0 + 25 + 7 + read-only + + + + + CRC_VALUE + OTP Controller CRC Value Register + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + DATA + 0 + 32 + read-write + + + + + VERSION + OTP Controller Version Register + 0x90 + 32 + read-only + 0x3000000 + 0xFFFFFFFF + + + STEP + STEP + 0 + 16 + read-only + + + MINOR + MINOR + 16 + 8 + read-only + + + MAJOR + MAJOR + 24 + 8 + read-only + + + + + TIMING2 + OTP Controller Timing Register + 0x100 + 32 + read-write + 0x1C30092 + 0xFFFFFFFF + + + RELAX_PROG + RELAX_PROG + 0 + 12 + read-write + + + RSRVD0 + RSRVD0 + 12 + 4 + read-only + + + RELAX_READ + RELAX_READ + 16 + 6 + read-write + + + RSRVD1 + RSRVD0 + 22 + 10 + read-only + + + + + LOCK + Value of OTP Bank0 Word0 (Lock controls) + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + TESTER + TESTER + 0 + 2 + read-only + + + BOOT_CFG + BOOT_CFG + 2 + 2 + read-only + + + MEM_TRIM + MEM_TRIM + 4 + 2 + read-only + + + SJC_RESP + SJC_RESP + 6 + 1 + read-only + + + GP4_RLOCK + GP4_RLOCK + 7 + 1 + read-only + + + MAC_ADDR + MAC_ADDR + 8 + 2 + read-only + + + GP1 + GP1 + 10 + 2 + read-only + + + GP2 + GP2 + 12 + 2 + read-only + + + ROM_PATCH + ROM_PATCH + 15 + 1 + read-only + + + SW_GP1 + SW_GP1 + 16 + 1 + read-only + + + OTPMK + OTPMK + 17 + 1 + read-only + + + ANALOG + ANALOG + 18 + 2 + read-only + + + OTPMK_CRC + OTPMK_CRC + 20 + 1 + read-only + + + SW_GP2_LOCK + SW_GP2_LOCK + 21 + 1 + read-only + + + MISC_CONF + MISC_CONF + 22 + 1 + read-only + + + SW_GP2_RLOCK + SW_GP2_RLOCK + 23 + 1 + read-only + + + GP4 + GP4 + 24 + 2 + read-only + + + GP3 + GP3 + 26 + 2 + read-only + + + FIELD_RETURN + FIELD_RETURN + 28 + 4 + read-write + + + + + CFG0 + Value of OTP Bank0 Word1 (Configuration and Manufacturing Info.) + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + CFG1 + Value of OTP Bank0 Word2 (Configuration and Manufacturing Info.) + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + CFG2 + Value of OTP Bank0 Word3 (Configuration and Manufacturing Info.) + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + CFG3 + Value of OTP Bank0 Word4 (Configuration and Manufacturing Info.) + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + CFG4 + Value of OTP Bank0 Word5 (Configuration and Manufacturing Info.) + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + CFG5 + Value of OTP Bank0 Word6 (Configuration and Manufacturing Info.) + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + CFG6 + Value of OTP Bank0 Word7 (Configuration and Manufacturing Info.) + 0x470 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + MEM0 + Value of OTP Bank1 Word0 (Memory Related Info.) + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + MEM1 + Value of OTP Bank1 Word1 (Memory Related Info.) + 0x490 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + MEM2 + Value of OTP Bank1 Word2 (Memory Related Info.) + 0x4A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + MEM3 + Value of OTP Bank1 Word3 (Memory Related Info.) + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + MEM4 + Value of OTP Bank1 Word4 (Memory Related Info.) + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + ANA0 + Value of OTP Bank1 Word5 (Memory Related Info.) + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + ANA1 + Value of OTP Bank1 Word6 (General Purpose Customer Defined Info.) + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + ANA2 + Value of OTP Bank1 Word7 (General Purpose Customer Defined Info.) + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + OTPMK0 + Value of OTP Bank2 Word0 (OTPMK Key) + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + OTPMK1 + Value of OTP Bank2 Word1 (OTPMK Key) + 0x510 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + OTPMK2 + Value of OTP Bank2 Word2 (OTPMK Key) + 0x520 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + OTPMK3 + Value of OTP Bank2 Word3 (OTPMK Key) + 0x530 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + OTPMK4 + Value of OTP Bank2 Word4 (OTPMK Key) + 0x540 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + OTPMK5 + Value of OTP Bank2 Word5 (OTPMK Key) + 0x550 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + OTPMK6 + Value of OTP Bank2 Word6 (OTPMK Key) + 0x560 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + OTPMK7 + Value of OTP Bank2 Word7 (OTPMK Key) + 0x570 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + SRK0 + Shadow Register for OTP Bank3 Word0 (SRK Hash) + 0x580 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + SRK1 + Shadow Register for OTP Bank3 Word1 (SRK Hash) + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + SRK2 + Shadow Register for OTP Bank3 Word2 (SRK Hash) + 0x5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + SRK3 + Shadow Register for OTP Bank3 Word3 (SRK Hash) + 0x5B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + SRK4 + Shadow Register for OTP Bank3 Word4 (SRK Hash) + 0x5C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + SRK5 + Shadow Register for OTP Bank3 Word5 (SRK Hash) + 0x5D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + SRK6 + Shadow Register for OTP Bank3 Word6 (SRK Hash) + 0x5E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + SRK7 + Shadow Register for OTP Bank3 Word7 (SRK Hash) + 0x5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + SJC_RESP0 + Value of OTP Bank4 Word0 (Secure JTAG Response Field) + 0x600 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + SJC_RESP1 + Value of OTP Bank4 Word1 (Secure JTAG Response Field) + 0x610 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + MAC0 + Value of OTP Bank4 Word2 (MAC Address) + 0x620 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + MAC1 + Value of OTP Bank4 Word3 (MAC Address) + 0x630 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + MAC2 + Value of OTP Bank4 Word4 (MAC2 Address) + 0x640 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + OTPMK_CRC32 + Value of OTP Bank4 Word5 (CRC Key) + 0x650 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + GP1 + Value of OTP Bank4 Word6 (General Purpose Customer Defined Info) + 0x660 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + GP2 + Value of OTP Bank4 Word7 (General Purpose Customer Defined Info) + 0x670 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + SW_GP1 + Value of OTP Bank5 Word0 (SW GP1) + 0x680 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + SW_GP20 + Value of OTP Bank5 Word1 (SW GP2) + 0x690 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + SW_GP21 + Value of OTP Bank5 Word2 (SW GP2) + 0x6A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + SW_GP22 + Value of OTP Bank5 Word3 (SW GP2) + 0x6B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + SW_GP23 + Value of OTP Bank5 Word4 (SW GP2) + 0x6C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + MISC_CONF0 + Value of OTP Bank5 Word5 (Misc Conf) + 0x6D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + MISC_CONF1 + Value of OTP Bank5 Word6 (Misc Conf) + 0x6E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + SRK_REVOKE + Value of OTP Bank5 Word7 (SRK Revoke) + 0x6F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + ROM_PATCH0 + Value of OTP Bank6 Word0 (ROM Patch) + 0x800 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + ROM_PATCH1 + Value of OTP Bank6 Word1 (ROM Patch) + 0x810 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + ROM_PATCH2 + Value of OTP Bank6 Word2 (ROM Patch) + 0x820 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + ROM_PATCH3 + Value of OTP Bank6 Word3 (ROM Patch) + 0x830 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + ROM_PATCH4 + Value of OTP Bank6 Word4 (ROM Patch) + 0x840 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + ROM_PATCH5 + Value of OTP Bank6 Word5 (ROM Patch) + 0x850 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + ROM_PATCH6 + Value of OTP Bank6 Word6 (ROM Patch) + 0x860 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + ROM_PATCH7 + Value of OTP Bank6 Word7 (ROM Patch) + 0x870 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + GP30 + Value of OTP Bank7 Word0 (GP3) + 0x880 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + GP31 + Value of OTP Bank7 Word1 (GP3) + 0x890 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + GP32 + Value of OTP Bank7 Word2 (GP3) + 0x8A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + GP33 + Value of OTP Bank7 Word3 (GP3) + 0x8B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + GP40 + Value of OTP Bank7 Word4 (GP4) + 0x8C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + GP41 + Value of OTP Bank7 Word5 (GP4) + 0x8D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + GP42 + Value of OTP Bank7 Word6 (GP4) + 0x8E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + GP43 + Value of OTP Bank7 Word7 (GP4) + 0x8F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + BITS + BITS + 0 + 32 + read-write + + + + + + + IOMUXC + IOMUXC + IOMUXC + IOMUXC_ + 0x401F8000 + + 0 + 0x790 + registers + + + + SW_MUX_CTL_PAD_GPIO_EMC_00 + SW_MUX_CTL_PAD_GPIO_EMC_00 SW MUX Control Register + 0x14 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA00 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMA00 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI2_SCK of instance: lpspi2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_XBAR_IN02 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO00 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO00 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_01 + SW_MUX_CTL_PAD_GPIO_EMC_01 SW MUX Control Register + 0x18 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA01 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMB00 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI2_PCS0 of instance: lpspi2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_IN03 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO01 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO01 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_02 + SW_MUX_CTL_PAD_GPIO_EMC_02 SW MUX Control Register + 0x1C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA02 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMA01 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI2_SDO of instance: lpspi2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT04 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO02 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO02 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_03 + SW_MUX_CTL_PAD_GPIO_EMC_03 SW MUX Control Register + 0x20 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA03 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMB01 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI2_SDI of instance: lpspi2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT05 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO03 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO03 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_04 + SW_MUX_CTL_PAD_GPIO_EMC_04 SW MUX Control Register + 0x24 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA04 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMA02 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_DATA of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT06 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO04 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO04 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_05 + SW_MUX_CTL_PAD_GPIO_EMC_05 SW MUX Control Register + 0x28 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA05 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMB02 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_SYNC of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT07 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO05 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO05 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_06 + SW_MUX_CTL_PAD_GPIO_EMC_06 SW MUX Control Register + 0x2C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA06 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWMA00 of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_TX_BCLK of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT08 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO06 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO06 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_07 + SW_MUX_CTL_PAD_GPIO_EMC_07 SW MUX Control Register + 0x30 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA07 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWMB00 of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_MCLK of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT09 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO07 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO07 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_08 + SW_MUX_CTL_PAD_GPIO_EMC_08 SW MUX Control Register + 0x34 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DM00 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWMA01 of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_RX_DATA of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT17 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO08 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO08 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_09 + SW_MUX_CTL_PAD_GPIO_EMC_09 SW MUX Control Register + 0x38 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR00 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWMB01 of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_RX_SYNC of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN2_TX of instance: flexcan2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO09 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO09 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXSPI2_B_SS1_B of instance: flexspi2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_10 + SW_MUX_CTL_PAD_GPIO_EMC_10 SW MUX Control Register + 0x3C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR01 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWMA02 of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: SAI2_RX_BCLK of instance: sai2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN2_RX of instance: flexcan2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO10 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO10 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXSPI2_B_SS0_B of instance: flexspi2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_11 + SW_MUX_CTL_PAD_GPIO_EMC_11 SW MUX Control Register + 0x40 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR02 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWMB02 of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C4_SDA of instance: lpi2c4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USDHC2_RESET_B of instance: usdhc2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO11 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO11 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXSPI2_B_DQS of instance: flexspi2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_12 + SW_MUX_CTL_PAD_GPIO_EMC_12 SW MUX Control Register + 0x44 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR03 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN24 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C4_SCL of instance: lpi2c4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USDHC1_WP of instance: usdhc1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXPWM1_PWMA03 of instance: flexpwm1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO12 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXSPI2_B_SCLK of instance: flexspi2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_13 + SW_MUX_CTL_PAD_GPIO_EMC_13 SW MUX Control Register + 0x48 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR04 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN25 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_TX of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: MQS_RIGHT of instance: mqs + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXPWM1_PWMB03 of instance: flexpwm1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO13 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXSPI2_B_DATA00 of instance: flexspi2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_14 + SW_MUX_CTL_PAD_GPIO_EMC_14 SW MUX Control Register + 0x4C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR05 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT19 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_RX of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: MQS_LEFT of instance: mqs + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_PCS1 of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO14 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXSPI2_B_DATA01 of instance: flexspi2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_15 + SW_MUX_CTL_PAD_GPIO_EMC_15 SW MUX Control Register + 0x50 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR06 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN20 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_CTS_B of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_OUT of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: QTIMER3_TIMER0 of instance: qtimer3 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO15 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXSPI2_B_DATA02 of instance: flexspi2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_16 + SW_MUX_CTL_PAD_GPIO_EMC_16 SW MUX Control Register + 0x54 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR07 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN21 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_RTS_B of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_IN of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: QTIMER3_TIMER1 of instance: qtimer3 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO16 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXSPI2_B_DATA03 of instance: flexspi2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_16 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_17 + SW_MUX_CTL_PAD_GPIO_EMC_17 SW MUX Control Register + 0x58 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR08 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMA03 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_CTS_B of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: QTIMER3_TIMER2 of instance: qtimer3 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO17 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_17 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_18 + SW_MUX_CTL_PAD_GPIO_EMC_18 SW MUX Control Register + 0x5C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR09 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMB03 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_RTS_B of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: QTIMER3_TIMER3 of instance: qtimer3 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO18 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SNVS_VIO_5_CTL of instance: snvs_hp + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_18 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_19 + SW_MUX_CTL_PAD_GPIO_EMC_19 SW MUX Control Register + 0x60 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR11 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_TX of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RDATA01 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: QTIMER2_TIMER0 of instance: qtimer2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO19 of instance: gpio4 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SNVS_VIO_5 of instance: snvs_hp + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_19 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_20 + SW_MUX_CTL_PAD_GPIO_EMC_20 SW MUX Control Register + 0x64 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR12 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWMB03 of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_RX of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RDATA00 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: QTIMER2_TIMER1 of instance: qtimer2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO20 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_20 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_21 + SW_MUX_CTL_PAD_GPIO_EMC_21 SW MUX Control Register + 0x68 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_BA0 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWMA03 of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C3_SDA of instance: lpi2c3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TDATA01 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: QTIMER2_TIMER2 of instance: qtimer2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO21 of instance: gpio4 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_21 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_22 + SW_MUX_CTL_PAD_GPIO_EMC_22 SW MUX Control Register + 0x6C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_BA1 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWMB03 of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C3_SCL of instance: lpi2c3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TDATA00 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: QTIMER2_TIMER3 of instance: qtimer2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO22 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXSPI2_A_SS1_B of instance: flexspi2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_22 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_23 + SW_MUX_CTL_PAD_GPIO_EMC_23 SW MUX Control Register + 0x70 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_ADDR10 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA00 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART5_TX of instance: lpuart5 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_EN of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: GPT1_CAPTURE2 of instance: gpt1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO23 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXSPI2_A_DQS of instance: flexspi2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_23 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_24 + SW_MUX_CTL_PAD_GPIO_EMC_24 SW MUX Control Register + 0x74 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_CAS of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB00 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART5_RX of instance: lpuart5 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_EN of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: GPT1_CAPTURE1 of instance: gpt1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO24 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXSPI2_A_SS0_B of instance: flexspi2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_24 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_25 + SW_MUX_CTL_PAD_GPIO_EMC_25 SW MUX Control Register + 0x78 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_RAS of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA01 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART6_TX of instance: lpuart6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_CLK of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET_REF_CLK of instance: enet + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO25 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXSPI2_A_SCLK of instance: flexspi2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_25 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_26 + SW_MUX_CTL_PAD_GPIO_EMC_26 SW MUX Control Register + 0x7C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_CLK of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB01 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART6_RX of instance: lpuart6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_ER of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO12 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO26 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXSPI2_A_DATA00 of instance: flexspi2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_26 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_27 + SW_MUX_CTL_PAD_GPIO_EMC_27 SW MUX Control Register + 0x80 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_CKE of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA02 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART5_RTS_B of instance: lpuart5 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI1_SCK of instance: lpspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO13 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO27 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXSPI2_A_DATA01 of instance: flexspi2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_27 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_28 + SW_MUX_CTL_PAD_GPIO_EMC_28 SW MUX Control Register + 0x84 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_WE of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB02 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART5_CTS_B of instance: lpuart5 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI1_SDO of instance: lpspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO14 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO28 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXSPI2_A_DATA02 of instance: flexspi2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_28 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_29 + SW_MUX_CTL_PAD_GPIO_EMC_29 SW MUX Control Register + 0x88 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_CS0 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWMA00 of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART6_RTS_B of instance: lpuart6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI1_SDI of instance: lpspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO15 of instance: flexio1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO29 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXSPI2_A_DATA03 of instance: flexspi2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_29 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_30 + SW_MUX_CTL_PAD_GPIO_EMC_30 SW MUX Control Register + 0x8C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA08 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWMB00 of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART6_CTS_B of instance: lpuart6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI1_PCS0 of instance: lpspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA23 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO30 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_TDATA00 of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_30 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_31 + SW_MUX_CTL_PAD_GPIO_EMC_31 SW MUX Control Register + 0x90 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA09 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWMA01 of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART7_TX of instance: lpuart7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI1_PCS1 of instance: lpspi1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA22 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO4_IO31 of instance: gpio4 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_TDATA01 of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_31 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_32 + SW_MUX_CTL_PAD_GPIO_EMC_32 SW MUX Control Register + 0x94 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA10 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWMB01 of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART7_RX of instance: lpuart7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CCM_PMIC_RDY of instance: ccm + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA21 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO18 of instance: gpio3 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_TX_EN of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_32 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_33 + SW_MUX_CTL_PAD_GPIO_EMC_33 SW MUX Control Register + 0x98 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA11 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWMA02 of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USDHC1_RESET_B of instance: usdhc1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_RX_DATA of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA20 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO19 of instance: gpio3 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_TX_CLK of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ENET2_REF_CLK2 of instance: enet2 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_33 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_34 + SW_MUX_CTL_PAD_GPIO_EMC_34 SW MUX Control Register + 0x9C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA12 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM3_PWMB02 of instance: flexpwm3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: USDHC1_VSELECT of instance: usdhc1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_RX_SYNC of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA19 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO20 of instance: gpio3 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_RX_ER of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_34 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_35 + SW_MUX_CTL_PAD_GPIO_EMC_35 SW MUX Control Register + 0xA0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA13 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT18 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: GPT1_COMPARE1 of instance: gpt1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_RX_BCLK of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA18 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO21 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_CD_B of instance: usdhc1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_RDATA00 of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_35 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_36 + SW_MUX_CTL_PAD_GPIO_EMC_36 SW MUX Control Register + 0xA4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA14 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN22 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: GPT1_COMPARE2 of instance: gpt1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_DATA of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA17 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO22 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_WP of instance: usdhc1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_RDATA01 of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXCAN3_TX of instance: flexcan3/canfd + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_36 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_37 + SW_MUX_CTL_PAD_GPIO_EMC_37 SW MUX Control Register + 0xA8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DATA15 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN23 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: GPT1_COMPARE3 of instance: gpt1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_MCLK of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA16 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO23 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_WP of instance: usdhc2 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_RX_EN of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXCAN3_RX of instance: flexcan3/canfd + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_37 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_38 + SW_MUX_CTL_PAD_GPIO_EMC_38 SW MUX Control Register + 0xAC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DM01 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA03 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_TX of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_BCLK of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_FIELD of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO24 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_VSELECT of instance: usdhc2 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_MDC of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_38 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_39 + SW_MUX_CTL_PAD_GPIO_EMC_39 SW MUX Control Register + 0xB0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_DQS of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB03 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_RX of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI3_TX_SYNC of instance: sai3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: WDOG1_WDOG_B of instance: wdog1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO25 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_CD_B of instance: usdhc2 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_MDIO of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: SEMC_DQS4 of instance: semc + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_39 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_40 + SW_MUX_CTL_PAD_GPIO_EMC_40 SW MUX Control Register + 0xB4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_RDY of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_CAPTURE2 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI1_PCS2 of instance: lpspi1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USB_OTG2_OC of instance: usb + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET_MDC of instance: enet + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO26 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_RESET_B of instance: usdhc2 + 0x6 + + + ALT9 + Select mux mode: ALT9 mux port: SEMC_CLK5 of instance: semc + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_40 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_EMC_41 + SW_MUX_CTL_PAD_GPIO_EMC_41 SW MUX Control Register + 0xB8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_CSX00 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_CAPTURE1 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI1_PCS3 of instance: lpspi1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USB_OTG2_PWR of instance: usb + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET_MDIO of instance: enet + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO27 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_VSELECT of instance: usdhc1 + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_EMC_41 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_00 + SW_MUX_CTL_PAD_GPIO_AD_B0_00 SW MUX Control Register + 0xBC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT14 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: REF_CLK_32K of instance: xtalosc + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USB_OTG2_ID of instance: usb + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPI2C1_SCLS of instance: lpi2c1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO00 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_RESET_B of instance: usdhc1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_SCK of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_01 + SW_MUX_CTL_PAD_GPIO_AD_B0_01 SW MUX Control Register + 0xC0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXPWM2_PWMB03 of instance: flexpwm2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT15 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: REF_CLK_24M of instance: anatop + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USB_OTG1_ID of instance: anatop + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPI2C1_SDAS of instance: lpi2c1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO01 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: EWM_OUT_B of instance: ewm + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_SDO of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_02 + SW_MUX_CTL_PAD_GPIO_AD_B0_02 SW MUX Control Register + 0xC4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXCAN2_TX of instance: flexcan2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT16 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART6_TX of instance: lpuart6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USB_OTG1_PWR of instance: usb + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXPWM1_PWMX00 of instance: flexpwm1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO02 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: LPI2C1_HREQ of instance: lpi2c1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_SDI of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_03 + SW_MUX_CTL_PAD_GPIO_AD_B0_03 SW MUX Control Register + 0xC8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXCAN2_RX of instance: flexcan2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT17 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART6_RX of instance: lpuart6 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: USB_OTG1_OC of instance: usb + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXPWM1_PWMX01 of instance: flexpwm1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO03 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: REF_CLK_24M of instance: anatop + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_PCS0 of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_04 + SW_MUX_CTL_PAD_GPIO_AD_B0_04 SW MUX Control Register + 0xCC + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SRC_BOOT_MODE00 of instance: src + 0 + + + ALT1 + Select mux mode: ALT1 mux port: MQS_RIGHT of instance: mqs + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_TX_DATA03 of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_TX_SYNC of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA09 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO04 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: PIT_TRIGGER00 of instance: pit + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_PCS1 of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_05 + SW_MUX_CTL_PAD_GPIO_AD_B0_05 SW MUX Control Register + 0xD0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SRC_BOOT_MODE01 of instance: src + 0 + + + ALT1 + Select mux mode: ALT1 mux port: MQS_LEFT of instance: mqs + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_TX_DATA02 of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_TX_BCLK of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA08 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO05 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_INOUT17 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_PCS2 of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_06 + SW_MUX_CTL_PAD_GPIO_AD_B0_06 SW MUX Control Register + 0xD4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_TMS of instance: jtag_mux + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE1 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_RX_CLK of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_RX_BCLK of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA07 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO06 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_INOUT18 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: LPSPI3_PCS3 of instance: lpspi3 + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_07 + SW_MUX_CTL_PAD_GPIO_AD_B0_07 SW MUX Control Register + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_TCK of instance: jtag_mux + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE2 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_TX_ER of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_RX_SYNC of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA06 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO07 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_INOUT19 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: ENET_1588_EVENT3_OUT of instance: enet + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_08 + SW_MUX_CTL_PAD_GPIO_AD_B0_08 SW MUX Control Register + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_MOD of instance: jtag_mux + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT2_COMPARE3 of instance: gpt2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_RX_DATA03 of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_RX_DATA of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA05 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO08 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_IN20 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: ENET_1588_EVENT3_IN of instance: enet + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_09 + SW_MUX_CTL_PAD_GPIO_AD_B0_09 SW MUX Control Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_TDI of instance: jtag_mux + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_RX_DATA02 of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_TX_DATA of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA04 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO09 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_IN21 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: GPT2_CLK of instance: gpt2 + 0x7 + + + ALT9 + Select mux mode: ALT9 mux port: SEMC_DQS4 of instance: semc + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_10 + SW_MUX_CTL_PAD_GPIO_AD_B0_10 SW MUX Control Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_TDO of instance: jtag_mux + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA03 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_CRS of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI2_MCLK of instance: sai2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA03 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO10 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_IN22 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: ENET_1588_EVENT0_OUT of instance: enet + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXCAN3_TX of instance: flexcan3/canfd + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ARM_TRACE_SWO of instance: cm7_mx6rt + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_11 + SW_MUX_CTL_PAD_GPIO_AD_B0_11 SW MUX Control Register + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: JTAG_TRSTB of instance: jtag_mux + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB03 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ENET_COL of instance: enet + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: WDOG1_WDOG_B of instance: wdog1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA02 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO11 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: XBAR1_IN23 of instance: xbar1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: ENET_1588_EVENT0_IN of instance: enet + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXCAN3_RX of instance: flexcan3/canfd + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: SEMC_CLK6 of instance: semc + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_12 + SW_MUX_CTL_PAD_GPIO_AD_B0_12 SW MUX Control Register + 0xEC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LPI2C4_SCL of instance: lpi2c4 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: CCM_PMIC_READY of instance: ccm + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART1_TX of instance: lpuart1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: WDOG2_WDOG_B of instance: wdog2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXPWM1_PWMX02 of instance: flexpwm1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO12 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: ENET_1588_EVENT1_OUT of instance: enet + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: nmi_glue + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_13 + SW_MUX_CTL_PAD_GPIO_AD_B0_13 SW MUX Control Register + 0xF0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LPI2C4_SDA of instance: lpi2c4 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: GPT1_CLK of instance: gpt1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART1_RX of instance: lpuart1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: EWM_OUT_B of instance: ewm + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXPWM1_PWMX03 of instance: flexpwm1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO13 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: ENET_1588_EVENT1_IN of instance: enet + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: REF_CLK_24M of instance: anatop + 0x7 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_14 + SW_MUX_CTL_PAD_GPIO_AD_B0_14 SW MUX Control Register + 0xF4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG2_OC of instance: usb + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN24 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART1_CTS_B of instance: lpuart1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_1588_EVENT0_OUT of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_VSYNC of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO14 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXCAN2_TX of instance: flexcan2 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXCAN3_TX of instance: flexcan3/canfd + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B0_15 + SW_MUX_CTL_PAD_GPIO_AD_B0_15 SW MUX Control Register + 0xF8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG2_PWR of instance: usb + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_IN25 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART1_RTS_B of instance: lpuart1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_1588_EVENT0_IN of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_HSYNC of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO15 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXCAN2_RX of instance: flexcan2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: WDOG1_WDOG_RST_B_DEB of instance: wdog1 + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: FLEXCAN3_RX of instance: flexcan3/canfd + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B0_15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_00 + SW_MUX_CTL_PAD_GPIO_AD_B1_00 SW MUX Control Register + 0xFC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG2_ID of instance: anatop + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER3_TIMER0 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_CTS_B of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPI2C1_SCL of instance: lpi2c1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: WDOG1_B of instance: wdog1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO16 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_WP of instance: usdhc1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW07 of instance: kpp + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_1588_EVENT0_OUT of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO00 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_01 + SW_MUX_CTL_PAD_GPIO_AD_B1_01 SW MUX Control Register + 0x100 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG1_PWR of instance: usb + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER3_TIMER1 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_RTS_B of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPI2C1_SDA of instance: lpi2c1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CCM_PMIC_READY of instance: ccm + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO17 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_VSELECT of instance: usdhc1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL07 of instance: kpp + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_1588_EVENT0_IN of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO01 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_02 + SW_MUX_CTL_PAD_GPIO_AD_B1_02 SW MUX Control Register + 0x104 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG1_ID of instance: anatop + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER3_TIMER2 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_TX of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_OUT of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET_1588_EVENT2_OUT of instance: enet + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO18 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_CD_B of instance: usdhc1 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW06 of instance: kpp + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: GPT2_CLK of instance: gpt2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO02 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_03 + SW_MUX_CTL_PAD_GPIO_AD_B1_03 SW MUX Control Register + 0x108 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USB_OTG1_OC of instance: usb + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER3_TIMER3 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_RX of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_IN of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: ENET_1588_EVENT2_IN of instance: enet + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO19 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_CD_B of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL06 of instance: kpp + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: GPT2_CAPTURE1 of instance: gpt2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO03 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_04 + SW_MUX_CTL_PAD_GPIO_AD_B1_04 SW MUX Control Register + 0x10C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIB_DATA03 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET_MDC of instance: enet + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_CTS_B of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_SR_CLK of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_PIXCLK of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO20 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA0 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW05 of instance: kpp + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: GPT2_CAPTURE2 of instance: gpt2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO04 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_05 + SW_MUX_CTL_PAD_GPIO_AD_B1_05 SW MUX Control Register + 0x110 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIB_DATA02 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ENET_MDIO of instance: enet + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_RTS_B of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_OUT of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_MCLK of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO21 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA1 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL05 of instance: kpp + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: GPT2_COMPARE1 of instance: gpt2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO05 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_06 + SW_MUX_CTL_PAD_GPIO_AD_B1_06 SW MUX Control Register + 0x114 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIB_DATA01 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPI2C3_SDA of instance: lpi2c3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_TX of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_LOCK of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_VSYNC of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO22 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA2 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW04 of instance: kpp + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: GPT2_COMPARE2 of instance: gpt2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO06 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_07 + SW_MUX_CTL_PAD_GPIO_AD_B1_07 SW MUX Control Register + 0x118 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIB_DATA00 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPI2C3_SCL of instance: lpi2c3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART3_RX of instance: lpuart3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SPDIF_EXT_CLK of instance: spdif + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_HSYNC of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO23 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA3 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL04 of instance: kpp + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: GPT2_COMPARE3 of instance: gpt2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO07 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_08 + SW_MUX_CTL_PAD_GPIO_AD_B1_08 SW MUX Control Register + 0x11C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIA_SS1_B of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMA00 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: CCM_PMIC_READY of instance: ccm + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA09 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO24 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_CMD of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW03 of instance: kpp + 0x7 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO08 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_09 + SW_MUX_CTL_PAD_GPIO_AD_B1_09 SW MUX Control Register + 0x120 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIA_DQS of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMA01 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA08 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO25 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_CLK of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL03 of instance: kpp + 0x7 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO09 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_10 + SW_MUX_CTL_PAD_GPIO_AD_B1_10 SW MUX Control Register + 0x124 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIA_DATA03 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: WDOG1_B of instance: wdog1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_TX of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA07 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO26 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_WP of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW02 of instance: kpp + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_1588_EVENT1_OUT of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO10 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_11 + SW_MUX_CTL_PAD_GPIO_AD_B1_11 SW MUX Control Register + 0x128 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIA_DATA02 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: EWM_OUT_B of instance: ewm + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_RX of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA06 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO27 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_RESET_B of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL02 of instance: kpp + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_1588_EVENT1_IN of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO11 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_12 + SW_MUX_CTL_PAD_GPIO_AD_B1_12 SW MUX Control Register + 0x12C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIA_DATA01 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ACMP_OUT00 of instance: acmp + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI3_PCS0 of instance: lpspi3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA05 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO28 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA4 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW01 of instance: kpp + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_1588_EVENT2_OUT of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO12 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_13 + SW_MUX_CTL_PAD_GPIO_AD_B1_13 SW MUX Control Register + 0x130 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIA_DATA00 of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ACMP_OUT01 of instance: acmp + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI3_SDI of instance: lpspi3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA04 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO29 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA5 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL01 of instance: kpp + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_1588_EVENT2_IN of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO13 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_14 + SW_MUX_CTL_PAD_GPIO_AD_B1_14 SW MUX Control Register + 0x134 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIA_SCLK of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ACMP_OUT02 of instance: acmp + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI3_SDO of instance: lpspi3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA03 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO30 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA6 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_ROW00 of instance: kpp + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_1588_EVENT3_OUT of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO14 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_AD_B1_15 + SW_MUX_CTL_PAD_GPIO_AD_B1_15 SW MUX Control Register + 0x138 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPIA_SS0_B of instance: flexspi + 0 + + + ALT1 + Select mux mode: ALT1 mux port: ACMP_OUT03 of instance: acmp + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI3_SCK of instance: lpspi3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: CSI_DATA02 of instance: csi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO1_IO31 of instance: gpio1 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC2_DATA7 of instance: usdhc2 + 0x6 + + + ALT7 + Select mux mode: ALT7 mux port: KPP_COL00 of instance: kpp + 0x7 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_1588_EVENT3_IN of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO15 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_AD_B1_15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_00 + SW_MUX_CTL_PAD_GPIO_B0_00 SW MUX Control Register + 0x13C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_CLK of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER1_TIMER0 of instance: qtimer1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: MQS_RIGHT of instance: mqs + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI4_PCS0 of instance: lpspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO00 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO00 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SEMC_CSX01 of instance: semc + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_MDC of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_01 + SW_MUX_CTL_PAD_GPIO_B0_01 SW MUX Control Register + 0x140 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_ENABLE of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER1_TIMER1 of instance: qtimer1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: MQS_LEFT of instance: mqs + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI4_SDI of instance: lpspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO01 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO01 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SEMC_CSX02 of instance: semc + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_MDIO of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_02 + SW_MUX_CTL_PAD_GPIO_B0_02 SW MUX Control Register + 0x144 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_HSYNC of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER1_TIMER2 of instance: qtimer1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI4_SDO of instance: lpspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO02 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO02 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SEMC_CSX03 of instance: semc + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_1588_EVENT0_OUT of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_03 + SW_MUX_CTL_PAD_GPIO_B0_03 SW MUX Control Register + 0x148 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_VSYNC of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER2_TIMER0 of instance: qtimer2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPSPI4_SCK of instance: lpspi4 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO03 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO03 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: WDOG2_RESET_B_DEB of instance: wdog2 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_1588_EVENT0_IN of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_04 + SW_MUX_CTL_PAD_GPIO_B0_04 SW MUX Control Register + 0x14C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA00 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER2_TIMER1 of instance: qtimer2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C2_SCL of instance: lpi2c2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ARM_TRACE0 of instance: cm7_mx6rt + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO04 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO04 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG00 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_TDATA03 of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_05 + SW_MUX_CTL_PAD_GPIO_B0_05 SW MUX Control Register + 0x150 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA01 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER2_TIMER2 of instance: qtimer2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C2_SDA of instance: lpi2c2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ARM_TRACE1 of instance: cm7_mx6rt + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO05 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO05 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG01 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_TDATA02 of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_06 + SW_MUX_CTL_PAD_GPIO_B0_06 SW MUX Control Register + 0x154 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA02 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER3_TIMER0 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWMA00 of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ARM_TRACE2 of instance: cm7_mx6rt + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO06 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO06 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG02 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_RX_CLK of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_07 + SW_MUX_CTL_PAD_GPIO_B0_07 SW MUX Control Register + 0x158 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA03 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER3_TIMER1 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWMB00 of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ARM_TRACE3 of instance: cm7_mx6rt + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO07 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO07 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG03 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_TX_ER of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_08 + SW_MUX_CTL_PAD_GPIO_B0_08 SW MUX Control Register + 0x15C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA04 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER3_TIMER2 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWMA01 of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPUART3_TX of instance: lpuart3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO08 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO08 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG04 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_RDATA03 of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_09 + SW_MUX_CTL_PAD_GPIO_B0_09 SW MUX Control Register + 0x160 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA05 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER4_TIMER0 of instance: qtimer4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWMB01 of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPUART3_RX of instance: lpuart3 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO09 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO09 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG05 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_RDATA02 of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_10 + SW_MUX_CTL_PAD_GPIO_B0_10 SW MUX Control Register + 0x164 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA06 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER4_TIMER1 of instance: qtimer4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWMA02 of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA03 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO10 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO10 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG06 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_CRS of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_11 + SW_MUX_CTL_PAD_GPIO_B0_11 SW MUX Control Register + 0x168 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA07 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER4_TIMER2 of instance: qtimer4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWMB02 of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA02 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO11 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO11 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG07 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_COL of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_12 + SW_MUX_CTL_PAD_GPIO_B0_12 SW MUX Control Register + 0x16C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA08 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT10 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ARM_TRACE_CLK of instance: cm7_mx6rt + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA01 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO12 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO12 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG08 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_TDATA00 of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_13 + SW_MUX_CTL_PAD_GPIO_B0_13 SW MUX Control Register + 0x170 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA09 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT11 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ARM_TRACE_SWO of instance: cm7_mx6rt + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO13 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO13 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG09 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_TDATA01 of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_14 + SW_MUX_CTL_PAD_GPIO_B0_14 SW MUX Control Register + 0x174 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA10 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT12 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ARM_TXEV of instance: cm7_mx6rt + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO14 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO14 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG10 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_TX_EN of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B0_15 + SW_MUX_CTL_PAD_GPIO_B0_15 SW MUX Control Register + 0x178 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA11 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT13 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: ARM_RXEV of instance: cm7_mx6rt + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO15 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO15 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SRC_BOOT_CFG11 of instance: src + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_TX_CLK of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ENET2_REF_CLK2 of instance: enet2 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B0_15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_00 + SW_MUX_CTL_PAD_GPIO_B1_00 SW MUX Control Register + 0x17C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA12 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT14 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_TX of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO16 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO16 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXPWM1_PWMA03 of instance: flexpwm1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_RX_ER of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO16 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_01 + SW_MUX_CTL_PAD_GPIO_B1_01 SW MUX Control Register + 0x180 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA13 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT15 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART4_RX of instance: lpuart4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO17 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO17 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXPWM1_PWMB03 of instance: flexpwm1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_RDATA00 of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO17 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_02 + SW_MUX_CTL_PAD_GPIO_B1_02 SW MUX Control Register + 0x184 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA14 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT16 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI4_PCS2 of instance: lpspi4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO18 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO18 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_RDATA01 of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO18 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_03 + SW_MUX_CTL_PAD_GPIO_B1_03 SW MUX Control Register + 0x188 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA15 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: XBAR1_INOUT17 of instance: xbar1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPSPI4_PCS1 of instance: lpspi4 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO19 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO19 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXPWM2_PWMB03 of instance: flexpwm2 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_RX_EN of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO19 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_04 + SW_MUX_CTL_PAD_GPIO_B1_04 SW MUX Control Register + 0x18C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA16 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPSPI4_PCS0 of instance: lpspi4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA15 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_DATA00 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO20 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO20 of instance: gpio2 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: GPT1_CLK of instance: gpt1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO20 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_05 + SW_MUX_CTL_PAD_GPIO_B1_05 SW MUX Control Register + 0x190 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA17 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPSPI4_SDI of instance: lpspi4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA14 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_DATA01 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO21 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO21 of instance: gpio2 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: GPT1_CAPTURE1 of instance: gpt1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO21 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_06 + SW_MUX_CTL_PAD_GPIO_B1_06 SW MUX Control Register + 0x194 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA18 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPSPI4_SDO of instance: lpspi4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA13 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_EN of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO22 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO22 of instance: gpio2 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: GPT1_CAPTURE2 of instance: gpt1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO22 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_07 + SW_MUX_CTL_PAD_GPIO_B1_07 SW MUX Control Register + 0x198 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA19 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPSPI4_SCK of instance: lpspi4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA12 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_DATA00 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO23 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO23 of instance: gpio2 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: GPT1_COMPARE1 of instance: gpt1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO23 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_08 + SW_MUX_CTL_PAD_GPIO_B1_08 SW MUX Control Register + 0x19C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA20 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER1_TIMER3 of instance: qtimer1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA11 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_DATA01 of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO24 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO24 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXCAN2_TX of instance: flexcan2 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: GPT1_COMPARE2 of instance: gpt1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO24 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_09 + SW_MUX_CTL_PAD_GPIO_B1_09 SW MUX Control Register + 0x1A0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA21 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER2_TIMER3 of instance: qtimer2 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA10 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_EN of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO25 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO25 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXCAN2_RX of instance: flexcan2 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: GPT1_COMPARE3 of instance: gpt1 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO25 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_10 + SW_MUX_CTL_PAD_GPIO_B1_10 SW MUX Control Register + 0x1A4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA22 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER3_TIMER3 of instance: qtimer3 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA00 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_TX_CLK of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO26 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO26 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: ENET_REF_CLK of instance: enet + 0x6 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO26 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_11 + SW_MUX_CTL_PAD_GPIO_B1_11 SW MUX Control Register + 0x1A8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: LCD_DATA23 of instance: lcdif + 0 + + + ALT1 + Select mux mode: ALT1 mux port: QTIMER4_TIMER3 of instance: qtimer4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_DATA01 of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_RX_ER of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO27 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO27 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: LPSPI4_PCS3 of instance: lpspi4 + 0x6 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO27 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_12 + SW_MUX_CTL_PAD_GPIO_B1_12 SW MUX Control Register + 0x1AC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT1 + Select mux mode: ALT1 mux port: LPUART5_TX of instance: lpuart5 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_PIXCLK of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_1588_EVENT0_IN of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO28 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO28 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_CD_B of instance: usdhc1 + 0x6 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO28 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_13 + SW_MUX_CTL_PAD_GPIO_B1_13 SW MUX Control Register + 0x1B0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: WDOG1_B of instance: wdog1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: LPUART5_RX of instance: lpuart5 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_VSYNC of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: ENET_1588_EVENT0_OUT of instance: enet + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO29 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO29 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_WP of instance: usdhc1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: SEMC_DQS4 of instance: semc + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO29 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_14 + SW_MUX_CTL_PAD_GPIO_B1_14 SW MUX Control Register + 0x1B4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET_MDC of instance: enet + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMA02 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_HSYNC of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_IN02 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO30 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO30 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_VSELECT of instance: usdhc1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_TDATA00 of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO30 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_14 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_B1_15 + SW_MUX_CTL_PAD_GPIO_B1_15 SW MUX Control Register + 0x1B8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: ENET_MDIO of instance: enet + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM4_PWMA03 of instance: flexpwm4 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: CSI_MCLK of instance: csi + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_IN03 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXIO2_FLEXIO31 of instance: flexio2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO2_IO31 of instance: gpio2 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: USDHC1_RESET_B of instance: usdhc1 + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_TDATA01 of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: FLEXIO3_FLEXIO31 of instance: flexio3 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_B1_15 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B0_00 + SW_MUX_CTL_PAD_GPIO_SD_B0_00 SW MUX Control Register + 0x1BC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_CMD of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA00 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C3_SCL of instance: lpi2c3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT04 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI1_SCK of instance: lpspi1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO12 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXSPIA_SS1_B of instance: flexspi + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_TX_EN of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: SEMC_DQS4 of instance: semc + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B0_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B0_01 + SW_MUX_CTL_PAD_GPIO_SD_B0_01 SW MUX Control Register + 0x1C0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_CLK of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB00 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C3_SDA of instance: lpi2c3 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT05 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI1_PCS0 of instance: lpspi1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO13 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: FLEXSPIB_SS1_B of instance: flexspi + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_TX_CLK of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: ENET2_REF_CLK2 of instance: enet2 + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B0_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B0_02 + SW_MUX_CTL_PAD_GPIO_SD_B0_02 SW MUX Control Register + 0x1C4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA0 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA01 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_CTS_B of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT06 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI1_SDO of instance: lpspi1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO14 of instance: gpio3 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_RX_ER of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: SEMC_CLK5 of instance: semc + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B0_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B0_03 + SW_MUX_CTL_PAD_GPIO_SD_B0_03 SW MUX Control Register + 0x1C8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA1 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB01 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_RTS_B of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT07 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI1_SDI of instance: lpspi1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO15 of instance: gpio3 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_RDATA00 of instance: enet2 + 0x8 + + + ALT9 + Select mux mode: ALT9 mux port: SEMC_CLK6 of instance: semc + 0x9 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B0_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B0_04 + SW_MUX_CTL_PAD_GPIO_SD_B0_04 SW MUX Control Register + 0x1CC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA2 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMA02 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_TX of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT08 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXSPIB_SS0_B of instance: flexspi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO16 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_CLKO1 of instance: ccm + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_RDATA01 of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B0_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B0_05 + SW_MUX_CTL_PAD_GPIO_SD_B0_05 SW MUX Control Register + 0x1D0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC1_DATA3 of instance: usdhc1 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXPWM1_PWMB02 of instance: flexpwm1 + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART8_RX of instance: lpuart8 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: XBAR1_INOUT09 of instance: xbar1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXSPIB_DQS of instance: flexspi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO17 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_CLKO2 of instance: ccm + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: ENET2_RX_EN of instance: enet2 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B0_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_00 + SW_MUX_CTL_PAD_GPIO_SD_B1_00 SW MUX Control Register + 0x1D4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA3 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIB_DATA03 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM1_PWMA03 of instance: flexpwm1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA03 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPUART4_TX of instance: lpuart4 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO00 of instance: gpio3 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: SAI3_RX_DATA of instance: sai3 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_01 + SW_MUX_CTL_PAD_GPIO_SD_B1_01 SW MUX Control Register + 0x1D8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA2 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIB_DATA02 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM1_PWMB03 of instance: flexpwm1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA02 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPUART4_RX of instance: lpuart4 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO01 of instance: gpio3 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: SAI3_TX_DATA of instance: sai3 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_02 + SW_MUX_CTL_PAD_GPIO_SD_B1_02 SW MUX Control Register + 0x1DC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA1 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIB_DATA01 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWMA03 of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA01 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXCAN1_TX of instance: flexcan1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO02 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_WAIT of instance: ccm + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: SAI3_TX_SYNC of instance: sai3 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_03 + SW_MUX_CTL_PAD_GPIO_SD_B1_03 SW MUX Control Register + 0x1E0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA0 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIB_DATA00 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: FLEXPWM2_PWMB03 of instance: flexpwm2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_MCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXCAN1_RX of instance: flexcan1 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO03 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_PMIC_READY of instance: ccm + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: SAI3_TX_BCLK of instance: sai3 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_04 + SW_MUX_CTL_PAD_GPIO_SD_B1_04 SW MUX Control Register + 0x1E4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_CLK of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIB_SCLK of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C1_SCL of instance: lpi2c1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXSPIA_SS1_B of instance: flexspi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO04 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: CCM_STOP of instance: ccm + 0x6 + + + ALT8 + Select mux mode: ALT8 mux port: SAI3_MCLK of instance: sai3 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_05 + SW_MUX_CTL_PAD_GPIO_SD_B1_05 SW MUX Control Register + 0x1E8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_CMD of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIA_DQS of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPI2C1_SDA of instance: lpi2c1 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: FLEXSPIB_SS0_B of instance: flexspi + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO05 of instance: gpio3 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: SAI3_RX_SYNC of instance: sai3 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_06 + SW_MUX_CTL_PAD_GPIO_SD_B1_06 SW MUX Control Register + 0x1EC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 4 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_RESET_B of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIA_SS0_B of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART7_CTS_B of instance: lpuart7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_RX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_PCS0 of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO06 of instance: gpio3 + 0x5 + + + ALT8 + Select mux mode: ALT8 mux port: SAI3_RX_BCLK of instance: sai3 + 0x8 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_07 + SW_MUX_CTL_PAD_GPIO_SD_B1_07 SW MUX Control Register + 0x1F0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: SEMC_CSX01 of instance: semc + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIA_SCLK of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART7_RTS_B of instance: lpuart7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_DATA00 of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_SCK of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO07 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_08 + SW_MUX_CTL_PAD_GPIO_SD_B1_08 SW MUX Control Register + 0x1F4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA4 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIA_DATA00 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART7_TX of instance: lpuart7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_BCLK of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_SD0 of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO08 of instance: gpio3 + 0x5 + + + ALT6 + Select mux mode: ALT6 mux port: SEMC_CSX02 of instance: semc + 0x6 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_09 + SW_MUX_CTL_PAD_GPIO_SD_B1_09 SW MUX Control Register + 0x1F8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA5 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIA_DATA01 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART7_RX of instance: lpuart7 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: SAI1_TX_SYNC of instance: sai1 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_SDI of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO09 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_10 + SW_MUX_CTL_PAD_GPIO_SD_B1_10 SW MUX Control Register + 0x1FC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA6 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIA_DATA02 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_RX of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPI2C2_SDA of instance: lpi2c2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_PCS2 of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO10 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SD_B1_11 + SW_MUX_CTL_PAD_GPIO_SD_B1_11 SW MUX Control Register + 0x200 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: USDHC2_DATA7 of instance: usdhc2 + 0 + + + ALT1 + Select mux mode: ALT1 mux port: FLEXSPIA_DATA03 of instance: flexspi + 0x1 + + + ALT2 + Select mux mode: ALT2 mux port: LPUART2_TX of instance: lpuart2 + 0x2 + + + ALT3 + Select mux mode: ALT3 mux port: LPI2C2_SCL of instance: lpi2c2 + 0x3 + + + ALT4 + Select mux mode: ALT4 mux port: LPSPI2_PCS3 of instance: lpspi2 + 0x4 + + + ALT5 + Select mux mode: ALT5 mux port: GPIO3_IO11 of instance: gpio3 + 0x5 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SD_B1_11 + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_00 + SW_PAD_CTL_PAD_GPIO_EMC_00 SW PAD Control Register + 0x204 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_01 + SW_PAD_CTL_PAD_GPIO_EMC_01 SW PAD Control Register + 0x208 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_02 + SW_PAD_CTL_PAD_GPIO_EMC_02 SW PAD Control Register + 0x20C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_03 + SW_PAD_CTL_PAD_GPIO_EMC_03 SW PAD Control Register + 0x210 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_04 + SW_PAD_CTL_PAD_GPIO_EMC_04 SW PAD Control Register + 0x214 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_05 + SW_PAD_CTL_PAD_GPIO_EMC_05 SW PAD Control Register + 0x218 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_06 + SW_PAD_CTL_PAD_GPIO_EMC_06 SW PAD Control Register + 0x21C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_07 + SW_PAD_CTL_PAD_GPIO_EMC_07 SW PAD Control Register + 0x220 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_08 + SW_PAD_CTL_PAD_GPIO_EMC_08 SW PAD Control Register + 0x224 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_09 + SW_PAD_CTL_PAD_GPIO_EMC_09 SW PAD Control Register + 0x228 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_10 + SW_PAD_CTL_PAD_GPIO_EMC_10 SW PAD Control Register + 0x22C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_11 + SW_PAD_CTL_PAD_GPIO_EMC_11 SW PAD Control Register + 0x230 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_12 + SW_PAD_CTL_PAD_GPIO_EMC_12 SW PAD Control Register + 0x234 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_13 + SW_PAD_CTL_PAD_GPIO_EMC_13 SW PAD Control Register + 0x238 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_14 + SW_PAD_CTL_PAD_GPIO_EMC_14 SW PAD Control Register + 0x23C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_15 + SW_PAD_CTL_PAD_GPIO_EMC_15 SW PAD Control Register + 0x240 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_16 + SW_PAD_CTL_PAD_GPIO_EMC_16 SW PAD Control Register + 0x244 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_17 + SW_PAD_CTL_PAD_GPIO_EMC_17 SW PAD Control Register + 0x248 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_18 + SW_PAD_CTL_PAD_GPIO_EMC_18 SW PAD Control Register + 0x24C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_19 + SW_PAD_CTL_PAD_GPIO_EMC_19 SW PAD Control Register + 0x250 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_20 + SW_PAD_CTL_PAD_GPIO_EMC_20 SW PAD Control Register + 0x254 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_21 + SW_PAD_CTL_PAD_GPIO_EMC_21 SW PAD Control Register + 0x258 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_22 + SW_PAD_CTL_PAD_GPIO_EMC_22 SW PAD Control Register + 0x25C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_23 + SW_PAD_CTL_PAD_GPIO_EMC_23 SW PAD Control Register + 0x260 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_24 + SW_PAD_CTL_PAD_GPIO_EMC_24 SW PAD Control Register + 0x264 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_25 + SW_PAD_CTL_PAD_GPIO_EMC_25 SW PAD Control Register + 0x268 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_26 + SW_PAD_CTL_PAD_GPIO_EMC_26 SW PAD Control Register + 0x26C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_27 + SW_PAD_CTL_PAD_GPIO_EMC_27 SW PAD Control Register + 0x270 + 32 + read-write + 0x30B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_28 + SW_PAD_CTL_PAD_GPIO_EMC_28 SW PAD Control Register + 0x274 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_29 + SW_PAD_CTL_PAD_GPIO_EMC_29 SW PAD Control Register + 0x278 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_30 + SW_PAD_CTL_PAD_GPIO_EMC_30 SW PAD Control Register + 0x27C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_31 + SW_PAD_CTL_PAD_GPIO_EMC_31 SW PAD Control Register + 0x280 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_32 + SW_PAD_CTL_PAD_GPIO_EMC_32 SW PAD Control Register + 0x284 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_33 + SW_PAD_CTL_PAD_GPIO_EMC_33 SW PAD Control Register + 0x288 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_34 + SW_PAD_CTL_PAD_GPIO_EMC_34 SW PAD Control Register + 0x28C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_35 + SW_PAD_CTL_PAD_GPIO_EMC_35 SW PAD Control Register + 0x290 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_36 + SW_PAD_CTL_PAD_GPIO_EMC_36 SW PAD Control Register + 0x294 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_37 + SW_PAD_CTL_PAD_GPIO_EMC_37 SW PAD Control Register + 0x298 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_38 + SW_PAD_CTL_PAD_GPIO_EMC_38 SW PAD Control Register + 0x29C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_39 + SW_PAD_CTL_PAD_GPIO_EMC_39 SW PAD Control Register + 0x2A0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_40 + SW_PAD_CTL_PAD_GPIO_EMC_40 SW PAD Control Register + 0x2A4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_EMC_41 + SW_PAD_CTL_PAD_GPIO_EMC_41 SW PAD Control Register + 0x2A8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_00 + SW_PAD_CTL_PAD_GPIO_AD_B0_00 SW PAD Control Register + 0x2AC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_01 + SW_PAD_CTL_PAD_GPIO_AD_B0_01 SW PAD Control Register + 0x2B0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_02 + SW_PAD_CTL_PAD_GPIO_AD_B0_02 SW PAD Control Register + 0x2B4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_03 + SW_PAD_CTL_PAD_GPIO_AD_B0_03 SW PAD Control Register + 0x2B8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_04 + SW_PAD_CTL_PAD_GPIO_AD_B0_04 SW PAD Control Register + 0x2BC + 32 + read-write + 0x30B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_05 + SW_PAD_CTL_PAD_GPIO_AD_B0_05 SW PAD Control Register + 0x2C0 + 32 + read-write + 0x30B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_06 + SW_PAD_CTL_PAD_GPIO_AD_B0_06 SW PAD Control Register + 0x2C4 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_07 + SW_PAD_CTL_PAD_GPIO_AD_B0_07 SW PAD Control Register + 0x2C8 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_08 + SW_PAD_CTL_PAD_GPIO_AD_B0_08 SW PAD Control Register + 0x2CC + 32 + read-write + 0xB0A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_09 + SW_PAD_CTL_PAD_GPIO_AD_B0_09 SW PAD Control Register + 0x2D0 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_10 + SW_PAD_CTL_PAD_GPIO_AD_B0_10 SW PAD Control Register + 0x2D4 + 32 + read-write + 0x90B1 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_11 + SW_PAD_CTL_PAD_GPIO_AD_B0_11 SW PAD Control Register + 0x2D8 + 32 + read-write + 0x70A0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_12 + SW_PAD_CTL_PAD_GPIO_AD_B0_12 SW PAD Control Register + 0x2DC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_13 + SW_PAD_CTL_PAD_GPIO_AD_B0_13 SW PAD Control Register + 0x2E0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_14 + SW_PAD_CTL_PAD_GPIO_AD_B0_14 SW PAD Control Register + 0x2E4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B0_15 + SW_PAD_CTL_PAD_GPIO_AD_B0_15 SW PAD Control Register + 0x2E8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_00 + SW_PAD_CTL_PAD_GPIO_AD_B1_00 SW PAD Control Register + 0x2EC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_01 + SW_PAD_CTL_PAD_GPIO_AD_B1_01 SW PAD Control Register + 0x2F0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_02 + SW_PAD_CTL_PAD_GPIO_AD_B1_02 SW PAD Control Register + 0x2F4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_03 + SW_PAD_CTL_PAD_GPIO_AD_B1_03 SW PAD Control Register + 0x2F8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_04 + SW_PAD_CTL_PAD_GPIO_AD_B1_04 SW PAD Control Register + 0x2FC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_05 + SW_PAD_CTL_PAD_GPIO_AD_B1_05 SW PAD Control Register + 0x300 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_06 + SW_PAD_CTL_PAD_GPIO_AD_B1_06 SW PAD Control Register + 0x304 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_07 + SW_PAD_CTL_PAD_GPIO_AD_B1_07 SW PAD Control Register + 0x308 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_08 + SW_PAD_CTL_PAD_GPIO_AD_B1_08 SW PAD Control Register + 0x30C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_09 + SW_PAD_CTL_PAD_GPIO_AD_B1_09 SW PAD Control Register + 0x310 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_10 + SW_PAD_CTL_PAD_GPIO_AD_B1_10 SW PAD Control Register + 0x314 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_11 + SW_PAD_CTL_PAD_GPIO_AD_B1_11 SW PAD Control Register + 0x318 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_12 + SW_PAD_CTL_PAD_GPIO_AD_B1_12 SW PAD Control Register + 0x31C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_13 + SW_PAD_CTL_PAD_GPIO_AD_B1_13 SW PAD Control Register + 0x320 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_14 + SW_PAD_CTL_PAD_GPIO_AD_B1_14 SW PAD Control Register + 0x324 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_AD_B1_15 + SW_PAD_CTL_PAD_GPIO_AD_B1_15 SW PAD Control Register + 0x328 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_00 + SW_PAD_CTL_PAD_GPIO_B0_00 SW PAD Control Register + 0x32C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_01 + SW_PAD_CTL_PAD_GPIO_B0_01 SW PAD Control Register + 0x330 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_02 + SW_PAD_CTL_PAD_GPIO_B0_02 SW PAD Control Register + 0x334 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_03 + SW_PAD_CTL_PAD_GPIO_B0_03 SW PAD Control Register + 0x338 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_04 + SW_PAD_CTL_PAD_GPIO_B0_04 SW PAD Control Register + 0x33C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_05 + SW_PAD_CTL_PAD_GPIO_B0_05 SW PAD Control Register + 0x340 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_06 + SW_PAD_CTL_PAD_GPIO_B0_06 SW PAD Control Register + 0x344 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_07 + SW_PAD_CTL_PAD_GPIO_B0_07 SW PAD Control Register + 0x348 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_08 + SW_PAD_CTL_PAD_GPIO_B0_08 SW PAD Control Register + 0x34C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_09 + SW_PAD_CTL_PAD_GPIO_B0_09 SW PAD Control Register + 0x350 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_10 + SW_PAD_CTL_PAD_GPIO_B0_10 SW PAD Control Register + 0x354 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_11 + SW_PAD_CTL_PAD_GPIO_B0_11 SW PAD Control Register + 0x358 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_12 + SW_PAD_CTL_PAD_GPIO_B0_12 SW PAD Control Register + 0x35C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_13 + SW_PAD_CTL_PAD_GPIO_B0_13 SW PAD Control Register + 0x360 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_14 + SW_PAD_CTL_PAD_GPIO_B0_14 SW PAD Control Register + 0x364 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B0_15 + SW_PAD_CTL_PAD_GPIO_B0_15 SW PAD Control Register + 0x368 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_00 + SW_PAD_CTL_PAD_GPIO_B1_00 SW PAD Control Register + 0x36C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_01 + SW_PAD_CTL_PAD_GPIO_B1_01 SW PAD Control Register + 0x370 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_02 + SW_PAD_CTL_PAD_GPIO_B1_02 SW PAD Control Register + 0x374 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_03 + SW_PAD_CTL_PAD_GPIO_B1_03 SW PAD Control Register + 0x378 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_04 + SW_PAD_CTL_PAD_GPIO_B1_04 SW PAD Control Register + 0x37C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_05 + SW_PAD_CTL_PAD_GPIO_B1_05 SW PAD Control Register + 0x380 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_06 + SW_PAD_CTL_PAD_GPIO_B1_06 SW PAD Control Register + 0x384 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_07 + SW_PAD_CTL_PAD_GPIO_B1_07 SW PAD Control Register + 0x388 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_08 + SW_PAD_CTL_PAD_GPIO_B1_08 SW PAD Control Register + 0x38C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_09 + SW_PAD_CTL_PAD_GPIO_B1_09 SW PAD Control Register + 0x390 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_10 + SW_PAD_CTL_PAD_GPIO_B1_10 SW PAD Control Register + 0x394 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_11 + SW_PAD_CTL_PAD_GPIO_B1_11 SW PAD Control Register + 0x398 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_12 + SW_PAD_CTL_PAD_GPIO_B1_12 SW PAD Control Register + 0x39C + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_13 + SW_PAD_CTL_PAD_GPIO_B1_13 SW PAD Control Register + 0x3A0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_14 + SW_PAD_CTL_PAD_GPIO_B1_14 SW PAD Control Register + 0x3A4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_B1_15 + SW_PAD_CTL_PAD_GPIO_B1_15 SW PAD Control Register + 0x3A8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B0_00 + SW_PAD_CTL_PAD_GPIO_SD_B0_00 SW PAD Control Register + 0x3AC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B0_01 + SW_PAD_CTL_PAD_GPIO_SD_B0_01 SW PAD Control Register + 0x3B0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B0_02 + SW_PAD_CTL_PAD_GPIO_SD_B0_02 SW PAD Control Register + 0x3B4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B0_03 + SW_PAD_CTL_PAD_GPIO_SD_B0_03 SW PAD Control Register + 0x3B8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B0_04 + SW_PAD_CTL_PAD_GPIO_SD_B0_04 SW PAD Control Register + 0x3BC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B0_05 + SW_PAD_CTL_PAD_GPIO_SD_B0_05 SW PAD Control Register + 0x3C0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_00 + SW_PAD_CTL_PAD_GPIO_SD_B1_00 SW PAD Control Register + 0x3C4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_01 + SW_PAD_CTL_PAD_GPIO_SD_B1_01 SW PAD Control Register + 0x3C8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_02 + SW_PAD_CTL_PAD_GPIO_SD_B1_02 SW PAD Control Register + 0x3CC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_03 + SW_PAD_CTL_PAD_GPIO_SD_B1_03 SW PAD Control Register + 0x3D0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_04 + SW_PAD_CTL_PAD_GPIO_SD_B1_04 SW PAD Control Register + 0x3D4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_05 + SW_PAD_CTL_PAD_GPIO_SD_B1_05 SW PAD Control Register + 0x3D8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_06 + SW_PAD_CTL_PAD_GPIO_SD_B1_06 SW PAD Control Register + 0x3DC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_07 + SW_PAD_CTL_PAD_GPIO_SD_B1_07 SW PAD Control Register + 0x3E0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_08 + SW_PAD_CTL_PAD_GPIO_SD_B1_08 SW PAD Control Register + 0x3E4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_09 + SW_PAD_CTL_PAD_GPIO_SD_B1_09 SW PAD Control Register + 0x3E8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_10 + SW_PAD_CTL_PAD_GPIO_SD_B1_10 SW PAD Control Register + 0x3EC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SD_B1_11 + SW_PAD_CTL_PAD_GPIO_SD_B1_11 SW PAD Control Register + 0x3F0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm_3_3V_260_Ohm_1_8V + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz + low(50MHz) + 0 + + + SPEED_1_medium_100MHz + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + ANATOP_USB_OTG1_ID_SELECT_INPUT + ANATOP_USB_OTG1_ID_SELECT_INPUT DAISY Register + 0x3F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_01_ALT3 + Selecting Pad: GPIO_AD_B0_01 for Mode: ALT3 + 0 + + + GPIO_AD_B1_02_ALT0 + Selecting Pad: GPIO_AD_B1_02 for Mode: ALT0 + 0x1 + + + + + + + ANATOP_USB_OTG2_ID_SELECT_INPUT + ANATOP_USB_OTG2_ID_SELECT_INPUT DAISY Register + 0x3F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_00_ALT3 + Selecting Pad: GPIO_AD_B0_00 for Mode: ALT3 + 0 + + + GPIO_AD_B1_00_ALT0 + Selecting Pad: GPIO_AD_B1_00 for Mode: ALT0 + 0x1 + + + + + + + CCM_PMIC_READY_SELECT_INPUT + CCM_PMIC_READY_SELECT_INPUT DAISY Register + 0x3FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 3 + read-write + + + GPIO_SD_B1_03_ALT6 + Selecting Pad: GPIO_SD_B1_03 for Mode: ALT6 + 0 + + + GPIO_AD_B0_12_ALT1 + Selecting Pad: GPIO_AD_B0_12 for Mode: ALT1 + 0x1 + + + GPIO_AD_B1_01_ALT4 + Selecting Pad: GPIO_AD_B1_01 for Mode: ALT4 + 0x2 + + + GPIO_AD_B1_08_ALT3 + Selecting Pad: GPIO_AD_B1_08 for Mode: ALT3 + 0x3 + + + GPIO_EMC_32_ALT3 + Selecting Pad: GPIO_EMC_32 for Mode: ALT3 + 0x4 + + + + + + + CSI_DATA02_SELECT_INPUT + CSI_DATA02_SELECT_INPUT DAISY Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_15_ALT4 + Selecting Pad: GPIO_AD_B1_15 for Mode: ALT4 + 0 + + + GPIO_AD_B0_11_ALT4 + Selecting Pad: GPIO_AD_B0_11 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA03_SELECT_INPUT + CSI_DATA03_SELECT_INPUT DAISY Register + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_14_ALT4 + Selecting Pad: GPIO_AD_B1_14 for Mode: ALT4 + 0 + + + GPIO_AD_B0_10_ALT4 + Selecting Pad: GPIO_AD_B0_10 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA04_SELECT_INPUT + CSI_DATA04_SELECT_INPUT DAISY Register + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_13_ALT4 + Selecting Pad: GPIO_AD_B1_13 for Mode: ALT4 + 0 + + + GPIO_AD_B0_09_ALT4 + Selecting Pad: GPIO_AD_B0_09 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA05_SELECT_INPUT + CSI_DATA05_SELECT_INPUT DAISY Register + 0x40C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_12_ALT4 + Selecting Pad: GPIO_AD_B1_12 for Mode: ALT4 + 0 + + + GPIO_AD_B0_08_ALT4 + Selecting Pad: GPIO_AD_B0_08 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA06_SELECT_INPUT + CSI_DATA06_SELECT_INPUT DAISY Register + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_11_ALT4 + Selecting Pad: GPIO_AD_B1_11 for Mode: ALT4 + 0 + + + GPIO_AD_B0_07_ALT4 + Selecting Pad: GPIO_AD_B0_07 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA07_SELECT_INPUT + CSI_DATA07_SELECT_INPUT DAISY Register + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_10_ALT4 + Selecting Pad: GPIO_AD_B1_10 for Mode: ALT4 + 0 + + + GPIO_AD_B0_06_ALT4 + Selecting Pad: GPIO_AD_B0_06 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA08_SELECT_INPUT + CSI_DATA08_SELECT_INPUT DAISY Register + 0x418 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_09_ALT4 + Selecting Pad: GPIO_AD_B1_09 for Mode: ALT4 + 0 + + + GPIO_AD_B0_05_ALT4 + Selecting Pad: GPIO_AD_B0_05 for Mode: ALT4 + 0x1 + + + + + + + CSI_DATA09_SELECT_INPUT + CSI_DATA09_SELECT_INPUT DAISY Register + 0x41C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_08_ALT4 + Selecting Pad: GPIO_AD_B1_08 for Mode: ALT4 + 0 + + + GPIO_AD_B0_04_ALT4 + Selecting Pad: GPIO_AD_B0_04 for Mode: ALT4 + 0x1 + + + + + + + CSI_HSYNC_SELECT_INPUT + CSI_HSYNC_SELECT_INPUT DAISY Register + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B0_15_ALT4 + Selecting Pad: GPIO_AD_B0_15 for Mode: ALT4 + 0 + + + GPIO_AD_B1_07_ALT4 + Selecting Pad: GPIO_AD_B1_07 for Mode: ALT4 + 0x1 + + + GPIO_B1_14_ALT2 + Selecting Pad: GPIO_B1_14 for Mode: ALT2 + 0x2 + + + + + + + CSI_PIXCLK_SELECT_INPUT + CSI_PIXCLK_SELECT_INPUT DAISY Register + 0x424 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_04_ALT4 + Selecting Pad: GPIO_AD_B1_04 for Mode: ALT4 + 0 + + + GPIO_B1_12_ALT2 + Selecting Pad: GPIO_B1_12 for Mode: ALT2 + 0x1 + + + + + + + CSI_VSYNC_SELECT_INPUT + CSI_VSYNC_SELECT_INPUT DAISY Register + 0x428 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B0_14_ALT4 + Selecting Pad: GPIO_AD_B0_14 for Mode: ALT4 + 0 + + + GPIO_AD_B1_06_ALT4 + Selecting Pad: GPIO_AD_B1_06 for Mode: ALT4 + 0x1 + + + GPIO_B1_13_ALT2 + Selecting Pad: GPIO_B1_13 for Mode: ALT2 + 0x2 + + + + + + + ENET_IPG_CLK_RMII_SELECT_INPUT + ENET_IPG_CLK_RMII_SELECT_INPUT DAISY Register + 0x42C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_25_ALT4 + Selecting Pad: GPIO_EMC_25 for Mode: ALT4 + 0 + + + GPIO_B1_10_ALT6 + Selecting Pad: GPIO_B1_10 for Mode: ALT6 + 0x1 + + + + + + + ENET_MDIO_SELECT_INPUT + ENET_MDIO_SELECT_INPUT DAISY Register + 0x430 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B1_05_ALT1 + Selecting Pad: GPIO_AD_B1_05 for Mode: ALT1 + 0 + + + GPIO_EMC_41_ALT4 + Selecting Pad: GPIO_EMC_41 for Mode: ALT4 + 0x1 + + + GPIO_B1_15_ALT0 + Selecting Pad: GPIO_B1_15 for Mode: ALT0 + 0x2 + + + + + + + ENET0_RXDATA_SELECT_INPUT + ENET0_RXDATA_SELECT_INPUT DAISY Register + 0x434 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_20_ALT3 + Selecting Pad: GPIO_EMC_20 for Mode: ALT3 + 0 + + + GPIO_B1_04_ALT3 + Selecting Pad: GPIO_B1_04 for Mode: ALT3 + 0x1 + + + + + + + ENET1_RXDATA_SELECT_INPUT + ENET1_RXDATA_SELECT_INPUT DAISY Register + 0x438 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_19_ALT3 + Selecting Pad: GPIO_EMC_19 for Mode: ALT3 + 0 + + + GPIO_B1_05_ALT3 + Selecting Pad: GPIO_B1_05 for Mode: ALT3 + 0x1 + + + + + + + ENET_RXEN_SELECT_INPUT + ENET_RXEN_SELECT_INPUT DAISY Register + 0x43C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_23_ALT3 + Selecting Pad: GPIO_EMC_23 for Mode: ALT3 + 0 + + + GPIO_B1_06_ALT3 + Selecting Pad: GPIO_B1_06 for Mode: ALT3 + 0x1 + + + + + + + ENET_RXERR_SELECT_INPUT + ENET_RXERR_SELECT_INPUT DAISY Register + 0x440 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_26_ALT3 + Selecting Pad: GPIO_EMC_26 for Mode: ALT3 + 0 + + + GPIO_B1_11_ALT3 + Selecting Pad: GPIO_B1_11 for Mode: ALT3 + 0x1 + + + + + + + ENET0_TIMER_SELECT_INPUT + ENET0_TIMER_SELECT_INPUT DAISY Register + 0x444 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B0_15_ALT3 + Selecting Pad: GPIO_AD_B0_15 for Mode: ALT3 + 0 + + + GPIO_AD_B0_11_ALT7 + Selecting Pad: GPIO_AD_B0_11 for Mode: ALT7 + 0x1 + + + GPIO_B1_12_ALT3 + Selecting Pad: GPIO_B1_12 for Mode: ALT3 + 0x2 + + + + + + + ENET_TXCLK_SELECT_INPUT + ENET_TXCLK_SELECT_INPUT DAISY Register + 0x448 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_25_ALT3 + Selecting Pad: GPIO_EMC_25 for Mode: ALT3 + 0 + + + GPIO_B1_10_ALT3 + Selecting Pad: GPIO_B1_10 for Mode: ALT3 + 0x1 + + + + + + + FLEXCAN1_RX_SELECT_INPUT + FLEXCAN1_RX_SELECT_INPUT DAISY Register + 0x44C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_03_ALT4 + Selecting Pad: GPIO_SD_B1_03 for Mode: ALT4 + 0 + + + GPIO_EMC_18_ALT3 + Selecting Pad: GPIO_EMC_18 for Mode: ALT3 + 0x1 + + + GPIO_AD_B1_09_ALT2 + Selecting Pad: GPIO_AD_B1_09 for Mode: ALT2 + 0x2 + + + GPIO_B0_03_ALT2 + Selecting Pad: GPIO_B0_03 for Mode: ALT2 + 0x3 + + + + + + + FLEXCAN2_RX_SELECT_INPUT + FLEXCAN2_RX_SELECT_INPUT DAISY Register + 0x450 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_10_ALT3 + Selecting Pad: GPIO_EMC_10 for Mode: ALT3 + 0 + + + GPIO_AD_B0_03_ALT0 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT0 + 0x1 + + + GPIO_AD_B0_15_ALT6 + Selecting Pad: GPIO_AD_B0_15 for Mode: ALT6 + 0x2 + + + GPIO_B1_09_ALT6 + Selecting Pad: GPIO_B1_09 for Mode: ALT6 + 0x3 + + + + + + + FLEXPWM1_PWMA3_SELECT_INPUT + FLEXPWM1_PWMA3_SELECT_INPUT DAISY Register + 0x454 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 3 + read-write + + + GPIO_SD_B1_00_ALT2 + Selecting Pad: GPIO_SD_B1_00 for Mode: ALT2 + 0 + + + GPIO_EMC_12_ALT4 + Selecting Pad: GPIO_EMC_12 for Mode: ALT4 + 0x1 + + + GPIO_EMC_38_ALT1 + Selecting Pad: GPIO_EMC_38 for Mode: ALT1 + 0x2 + + + GPIO_AD_B0_10_ALT1 + Selecting Pad: GPIO_AD_B0_10 for Mode: ALT1 + 0x3 + + + GPIO_B1_00_ALT6 + Selecting Pad: GPIO_B1_00 for Mode: ALT6 + 0x4 + + + + + + + FLEXPWM1_PWMA0_SELECT_INPUT + FLEXPWM1_PWMA0_SELECT_INPUT DAISY Register + 0x458 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_23_ALT1 + Selecting Pad: GPIO_EMC_23 for Mode: ALT1 + 0 + + + GPIO_SD_B0_00_ALT1 + Selecting Pad: GPIO_SD_B0_00 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_PWMA1_SELECT_INPUT + FLEXPWM1_PWMA1_SELECT_INPUT DAISY Register + 0x45C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_25_ALT1 + Selecting Pad: GPIO_EMC_25 for Mode: ALT1 + 0 + + + GPIO_SD_B0_02_ALT1 + Selecting Pad: GPIO_SD_B0_02 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_PWMA2_SELECT_INPUT + FLEXPWM1_PWMA2_SELECT_INPUT DAISY Register + 0x460 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_27_ALT1 + Selecting Pad: GPIO_EMC_27 for Mode: ALT1 + 0 + + + GPIO_SD_B0_04_ALT1 + Selecting Pad: GPIO_SD_B0_04 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_PWMB3_SELECT_INPUT + FLEXPWM1_PWMB3_SELECT_INPUT DAISY Register + 0x464 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 3 + read-write + + + GPIO_SD_B1_01_ALT2 + Selecting Pad: GPIO_SD_B1_01 for Mode: ALT2 + 0 + + + GPIO_EMC_13_ALT4 + Selecting Pad: GPIO_EMC_13 for Mode: ALT4 + 0x1 + + + GPIO_EMC_39_ALT1 + Selecting Pad: GPIO_EMC_39 for Mode: ALT1 + 0x2 + + + GPIO_AD_B0_11_ALT1 + Selecting Pad: GPIO_AD_B0_11 for Mode: ALT1 + 0x3 + + + GPIO_B1_01_ALT6 + Selecting Pad: GPIO_B1_01 for Mode: ALT6 + 0x4 + + + + + + + FLEXPWM1_PWMB0_SELECT_INPUT + FLEXPWM1_PWMB0_SELECT_INPUT DAISY Register + 0x468 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_24_ALT1 + Selecting Pad: GPIO_EMC_24 for Mode: ALT1 + 0 + + + GPIO_SD_B0_01_ALT1 + Selecting Pad: GPIO_SD_B0_01 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_PWMB1_SELECT_INPUT + FLEXPWM1_PWMB1_SELECT_INPUT DAISY Register + 0x46C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_26_ALT1 + Selecting Pad: GPIO_EMC_26 for Mode: ALT1 + 0 + + + GPIO_SD_B0_03_ALT1 + Selecting Pad: GPIO_SD_B0_03 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM1_PWMB2_SELECT_INPUT + FLEXPWM1_PWMB2_SELECT_INPUT DAISY Register + 0x470 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_28_ALT1 + Selecting Pad: GPIO_EMC_28 for Mode: ALT1 + 0 + + + GPIO_SD_B0_05_ALT1 + Selecting Pad: GPIO_SD_B0_05 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM2_PWMA3_SELECT_INPUT + FLEXPWM2_PWMA3_SELECT_INPUT DAISY Register + 0x474 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 3 + read-write + + + GPIO_SD_B1_02_ALT2 + Selecting Pad: GPIO_SD_B1_02 for Mode: ALT2 + 0 + + + GPIO_EMC_19_ALT1 + Selecting Pad: GPIO_EMC_19 for Mode: ALT1 + 0x1 + + + GPIO_AD_B0_00_ALT0 + Selecting Pad: GPIO_AD_B0_00 for Mode: ALT0 + 0x2 + + + GPIO_AD_B0_09_ALT1 + Selecting Pad: GPIO_AD_B0_09 for Mode: ALT1 + 0x3 + + + GPIO_B1_02_ALT6 + Selecting Pad: GPIO_B1_02 for Mode: ALT6 + 0x4 + + + + + + + FLEXPWM2_PWMA0_SELECT_INPUT + FLEXPWM2_PWMA0_SELECT_INPUT DAISY Register + 0x478 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_06_ALT1 + Selecting Pad: GPIO_EMC_06 for Mode: ALT1 + 0 + + + GPIO_B0_06_ALT2 + Selecting Pad: GPIO_B0_06 for Mode: ALT2 + 0x1 + + + + + + + FLEXPWM2_PWMA1_SELECT_INPUT + FLEXPWM2_PWMA1_SELECT_INPUT DAISY Register + 0x47C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_08_ALT1 + Selecting Pad: GPIO_EMC_08 for Mode: ALT1 + 0 + + + GPIO_B0_08_ALT2 + Selecting Pad: GPIO_B0_08 for Mode: ALT2 + 0x1 + + + + + + + FLEXPWM2_PWMA2_SELECT_INPUT + FLEXPWM2_PWMA2_SELECT_INPUT DAISY Register + 0x480 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_10_ALT1 + Selecting Pad: GPIO_EMC_10 for Mode: ALT1 + 0 + + + GPIO_B0_10_ALT2 + Selecting Pad: GPIO_B0_10 for Mode: ALT2 + 0x1 + + + + + + + FLEXPWM2_PWMB3_SELECT_INPUT + FLEXPWM2_PWMB3_SELECT_INPUT DAISY Register + 0x484 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_03_ALT2 + Selecting Pad: GPIO_SD_B1_03 for Mode: ALT2 + 0 + + + GPIO_EMC_20_ALT1 + Selecting Pad: GPIO_EMC_20 for Mode: ALT1 + 0x1 + + + GPIO_AD_B0_01_ALT0 + Selecting Pad: GPIO_AD_B0_01 for Mode: ALT0 + 0x2 + + + GPIO_B1_03_ALT6 + Selecting Pad: GPIO_B1_03 for Mode: ALT6 + 0x3 + + + + + + + FLEXPWM2_PWMB0_SELECT_INPUT + FLEXPWM2_PWMB0_SELECT_INPUT DAISY Register + 0x488 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_07_ALT1 + Selecting Pad: GPIO_EMC_07 for Mode: ALT1 + 0 + + + GPIO_B0_07_ALT2 + Selecting Pad: GPIO_B0_07 for Mode: ALT2 + 0x1 + + + + + + + FLEXPWM2_PWMB1_SELECT_INPUT + FLEXPWM2_PWMB1_SELECT_INPUT DAISY Register + 0x48C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_09_ALT1 + Selecting Pad: GPIO_EMC_09 for Mode: ALT1 + 0 + + + GPIO_B0_09_ALT2 + Selecting Pad: GPIO_B0_09 for Mode: ALT2 + 0x1 + + + + + + + FLEXPWM2_PWMB2_SELECT_INPUT + FLEXPWM2_PWMB2_SELECT_INPUT DAISY Register + 0x490 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_11_ALT1 + Selecting Pad: GPIO_EMC_11 for Mode: ALT1 + 0 + + + GPIO_B0_11_ALT2 + Selecting Pad: GPIO_B0_11 for Mode: ALT2 + 0x1 + + + + + + + FLEXPWM4_PWMA0_SELECT_INPUT + FLEXPWM4_PWMA0_SELECT_INPUT DAISY Register + 0x494 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_00_ALT1 + Selecting Pad: GPIO_EMC_00 for Mode: ALT1 + 0 + + + GPIO_AD_B1_08_ALT1 + Selecting Pad: GPIO_AD_B1_08 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM4_PWMA1_SELECT_INPUT + FLEXPWM4_PWMA1_SELECT_INPUT DAISY Register + 0x498 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_02_ALT1 + Selecting Pad: GPIO_EMC_02 for Mode: ALT1 + 0 + + + GPIO_AD_B1_09_ALT1 + Selecting Pad: GPIO_AD_B1_09 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM4_PWMA2_SELECT_INPUT + FLEXPWM4_PWMA2_SELECT_INPUT DAISY Register + 0x49C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_04_ALT1 + Selecting Pad: GPIO_EMC_04 for Mode: ALT1 + 0 + + + GPIO_B1_14_ALT1 + Selecting Pad: GPIO_B1_14 for Mode: ALT1 + 0x1 + + + + + + + FLEXPWM4_PWMA3_SELECT_INPUT + FLEXPWM4_PWMA3_SELECT_INPUT DAISY Register + 0x4A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_17_ALT1 + Selecting Pad: GPIO_EMC_17 for Mode: ALT1 + 0 + + + GPIO_B1_15_ALT1 + Selecting Pad: GPIO_B1_15 for Mode: ALT1 + 0x1 + + + + + + + FLEXSPIA_DQS_SELECT_INPUT + FLEXSPIA_DQS_SELECT_INPUT DAISY Register + 0x4A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_05_ALT1 + Selecting Pad: GPIO_SD_B1_05 for Mode: ALT1 + 0 + + + GPIO_AD_B1_09_ALT0 + Selecting Pad: GPIO_AD_B1_09 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPIA_DATA0_SELECT_INPUT + FLEXSPIA_DATA0_SELECT_INPUT DAISY Register + 0x4A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_08_ALT1 + Selecting Pad: GPIO_SD_B1_08 for Mode: ALT1 + 0 + + + GPIO_AD_B1_13_ALT0 + Selecting Pad: GPIO_AD_B1_13 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPIA_DATA1_SELECT_INPUT + FLEXSPIA_DATA1_SELECT_INPUT DAISY Register + 0x4AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_09_ALT1 + Selecting Pad: GPIO_SD_B1_09 for Mode: ALT1 + 0 + + + GPIO_AD_B1_12_ALT0 + Selecting Pad: GPIO_AD_B1_12 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPIA_DATA2_SELECT_INPUT + FLEXSPIA_DATA2_SELECT_INPUT DAISY Register + 0x4B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_10_ALT1 + Selecting Pad: GPIO_SD_B1_10 for Mode: ALT1 + 0 + + + GPIO_AD_B1_11_ALT0 + Selecting Pad: GPIO_AD_B1_11 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPIA_DATA3_SELECT_INPUT + FLEXSPIA_DATA3_SELECT_INPUT DAISY Register + 0x4B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_11_ALT1 + Selecting Pad: GPIO_SD_B1_11 for Mode: ALT1 + 0 + + + GPIO_AD_B1_10_ALT0 + Selecting Pad: GPIO_AD_B1_10 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPIB_DATA0_SELECT_INPUT + FLEXSPIB_DATA0_SELECT_INPUT DAISY Register + 0x4B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_03_ALT1 + Selecting Pad: GPIO_SD_B1_03 for Mode: ALT1 + 0 + + + GPIO_AD_B1_07_ALT0 + Selecting Pad: GPIO_AD_B1_07 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPIB_DATA1_SELECT_INPUT + FLEXSPIB_DATA1_SELECT_INPUT DAISY Register + 0x4BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_02_ALT1 + Selecting Pad: GPIO_SD_B1_02 for Mode: ALT1 + 0 + + + GPIO_AD_B1_06_ALT0 + Selecting Pad: GPIO_AD_B1_06 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPIB_DATA2_SELECT_INPUT + FLEXSPIB_DATA2_SELECT_INPUT DAISY Register + 0x4C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_01_ALT1 + Selecting Pad: GPIO_SD_B1_01 for Mode: ALT1 + 0 + + + GPIO_AD_B1_05_ALT0 + Selecting Pad: GPIO_AD_B1_05 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPIB_DATA3_SELECT_INPUT + FLEXSPIB_DATA3_SELECT_INPUT DAISY Register + 0x4C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_00_ALT1 + Selecting Pad: GPIO_SD_B1_00 for Mode: ALT1 + 0 + + + GPIO_AD_B1_04_ALT0 + Selecting Pad: GPIO_AD_B1_04 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPIA_SCK_SELECT_INPUT + FLEXSPIA_SCK_SELECT_INPUT DAISY Register + 0x4C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_07_ALT1 + Selecting Pad: GPIO_SD_B1_07 for Mode: ALT1 + 0 + + + GPIO_AD_B1_14_ALT0 + Selecting Pad: GPIO_AD_B1_14 for Mode: ALT0 + 0x1 + + + + + + + LPI2C1_SCL_SELECT_INPUT + LPI2C1_SCL_SELECT_INPUT DAISY Register + 0x4CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_04_ALT2 + Selecting Pad: GPIO_SD_B1_04 for Mode: ALT2 + 0 + + + GPIO_AD_B1_00_ALT3 + Selecting Pad: GPIO_AD_B1_00 for Mode: ALT3 + 0x1 + + + + + + + LPI2C1_SDA_SELECT_INPUT + LPI2C1_SDA_SELECT_INPUT DAISY Register + 0x4D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_05_ALT2 + Selecting Pad: GPIO_SD_B1_05 for Mode: ALT2 + 0 + + + GPIO_AD_B1_01_ALT3 + Selecting Pad: GPIO_AD_B1_01 for Mode: ALT3 + 0x1 + + + + + + + LPI2C2_SCL_SELECT_INPUT + LPI2C2_SCL_SELECT_INPUT DAISY Register + 0x4D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_11_ALT3 + Selecting Pad: GPIO_SD_B1_11 for Mode: ALT3 + 0 + + + GPIO_B0_04_ALT2 + Selecting Pad: GPIO_B0_04 for Mode: ALT2 + 0x1 + + + + + + + LPI2C2_SDA_SELECT_INPUT + LPI2C2_SDA_SELECT_INPUT DAISY Register + 0x4D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_10_ALT3 + Selecting Pad: GPIO_SD_B1_10 for Mode: ALT3 + 0 + + + GPIO_B0_05_ALT2 + Selecting Pad: GPIO_B0_05 for Mode: ALT2 + 0x1 + + + + + + + LPI2C3_SCL_SELECT_INPUT + LPI2C3_SCL_SELECT_INPUT DAISY Register + 0x4DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_22_ALT2 + Selecting Pad: GPIO_EMC_22 for Mode: ALT2 + 0 + + + GPIO_SD_B0_00_ALT2 + Selecting Pad: GPIO_SD_B0_00 for Mode: ALT2 + 0x1 + + + GPIO_AD_B1_07_ALT1 + Selecting Pad: GPIO_AD_B1_07 for Mode: ALT1 + 0x2 + + + + + + + LPI2C3_SDA_SELECT_INPUT + LPI2C3_SDA_SELECT_INPUT DAISY Register + 0x4E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_21_ALT2 + Selecting Pad: GPIO_EMC_21 for Mode: ALT2 + 0 + + + GPIO_SD_B0_01_ALT2 + Selecting Pad: GPIO_SD_B0_01 for Mode: ALT2 + 0x1 + + + GPIO_AD_B1_06_ALT1 + Selecting Pad: GPIO_AD_B1_06 for Mode: ALT1 + 0x2 + + + + + + + LPI2C4_SCL_SELECT_INPUT + LPI2C4_SCL_SELECT_INPUT DAISY Register + 0x4E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_12_ALT2 + Selecting Pad: GPIO_EMC_12 for Mode: ALT2 + 0 + + + GPIO_AD_B0_12_ALT0 + Selecting Pad: GPIO_AD_B0_12 for Mode: ALT0 + 0x1 + + + + + + + LPI2C4_SDA_SELECT_INPUT + LPI2C4_SDA_SELECT_INPUT DAISY Register + 0x4E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_11_ALT2 + Selecting Pad: GPIO_EMC_11 for Mode: ALT2 + 0 + + + GPIO_AD_B0_13_ALT0 + Selecting Pad: GPIO_AD_B0_13 for Mode: ALT0 + 0x1 + + + + + + + LPSPI1_PCS0_SELECT_INPUT + LPSPI1_PCS0_SELECT_INPUT DAISY Register + 0x4EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B0_01_ALT4 + Selecting Pad: GPIO_SD_B0_01 for Mode: ALT4 + 0 + + + GPIO_EMC_30_ALT3 + Selecting Pad: GPIO_EMC_30 for Mode: ALT3 + 0x1 + + + + + + + LPSPI1_SCK_SELECT_INPUT + LPSPI1_SCK_SELECT_INPUT DAISY Register + 0x4F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_27_ALT3 + Selecting Pad: GPIO_EMC_27 for Mode: ALT3 + 0 + + + GPIO_SD_B0_00_ALT4 + Selecting Pad: GPIO_SD_B0_00 for Mode: ALT4 + 0x1 + + + + + + + LPSPI1_SDI_SELECT_INPUT + LPSPI1_SDI_SELECT_INPUT DAISY Register + 0x4F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_29_ALT3 + Selecting Pad: GPIO_EMC_29 for Mode: ALT3 + 0 + + + GPIO_SD_B0_03_ALT4 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT4 + 0x1 + + + + + + + LPSPI1_SDO_SELECT_INPUT + LPSPI1_SDO_SELECT_INPUT DAISY Register + 0x4F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_28_ALT3 + Selecting Pad: GPIO_EMC_28 for Mode: ALT3 + 0 + + + GPIO_SD_B0_02_ALT4 + Selecting Pad: GPIO_SD_B0_02 for Mode: ALT4 + 0x1 + + + + + + + LPSPI2_PCS0_SELECT_INPUT + LPSPI2_PCS0_SELECT_INPUT DAISY Register + 0x4FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_06_ALT4 + Selecting Pad: GPIO_SD_B1_06 for Mode: ALT4 + 0 + + + GPIO_EMC_01_ALT2 + Selecting Pad: GPIO_EMC_01 for Mode: ALT2 + 0x1 + + + + + + + LPSPI2_SCK_SELECT_INPUT + LPSPI2_SCK_SELECT_INPUT DAISY Register + 0x500 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_07_ALT4 + Selecting Pad: GPIO_SD_B1_07 for Mode: ALT4 + 0 + + + GPIO_EMC_00_ALT2 + Selecting Pad: GPIO_EMC_00 for Mode: ALT2 + 0x1 + + + + + + + LPSPI2_SDI_SELECT_INPUT + LPSPI2_SDI_SELECT_INPUT DAISY Register + 0x504 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_09_ALT4 + Selecting Pad: GPIO_SD_B1_09 for Mode: ALT4 + 0 + + + GPIO_EMC_03_ALT2 + Selecting Pad: GPIO_EMC_03 for Mode: ALT2 + 0x1 + + + + + + + LPSPI2_SDO_SELECT_INPUT + LPSPI2_SDO_SELECT_INPUT DAISY Register + 0x508 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_08_ALT4 + Selecting Pad: GPIO_SD_B1_08 for Mode: ALT4 + 0 + + + GPIO_EMC_02_ALT2 + Selecting Pad: GPIO_EMC_02 for Mode: ALT2 + 0x1 + + + + + + + LPSPI3_PCS0_SELECT_INPUT + LPSPI3_PCS0_SELECT_INPUT DAISY Register + 0x50C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_03_ALT7 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT7 + 0 + + + GPIO_AD_B1_12_ALT2 + Selecting Pad: GPIO_AD_B1_12 for Mode: ALT2 + 0x1 + + + + + + + LPSPI3_SCK_SELECT_INPUT + LPSPI3_SCK_SELECT_INPUT DAISY Register + 0x510 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_00_ALT7 + Selecting Pad: GPIO_AD_B0_00 for Mode: ALT7 + 0 + + + GPIO_AD_B1_15 + Selecting Pad: GPIO_AD_B1_15 for Mode: ALT2 + 0x1 + + + + + + + LPSPI3_SDI_SELECT_INPUT + LPSPI3_SDI_SELECT_INPUT DAISY Register + 0x514 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_02_ALT7 + Selecting Pad: GPIO_AD_B0_02 for Mode: ALT7 + 0 + + + GPIO_AD_B1_13_ALT2 + Selecting Pad: GPIO_AD_B1_13 for Mode: ALT2 + 0x1 + + + + + + + LPSPI3_SDO_SELECT_INPUT + LPSPI3_SDO_SELECT_INPUT DAISY Register + 0x518 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_01_ALT7 + Selecting Pad: GPIO_AD_B0_01 for Mode: ALT7 + 0 + + + GPIO_AD_B1_14_ALT2 + Selecting Pad: GPIO_AD_B1_14 for Mode: ALT2 + 0x1 + + + + + + + LPSPI4_PCS0_SELECT_INPUT + LPSPI4_PCS0_SELECT_INPUT DAISY Register + 0x51C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_B0_00_ALT3 + Selecting Pad: GPIO_B0_00 for Mode: ALT3 + 0 + + + GPIO_B1_04_ALT1 + Selecting Pad:GPIO_B1_04 for Mode: ALT1 + 0x1 + + + + + + + LPSPI4_SCK_SELECT_INPUT + LPSPI4_SCK_SELECT_INPUT DAISY Register + 0x520 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_B0_03_ALT3 + Selecting Pad: GPIO_B0_03 for Mode: ALT3 + 0 + + + GPIO_B1_07_ALT1 + Selecting Pad: GPIO_B1_07 for Mode: ALT1 + 0x1 + + + + + + + LPSPI4_SDI_SELECT_INPUT + LPSPI4_SDI_SELECT_INPUT DAISY Register + 0x524 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_B0_01_ALT3 + Selecting Pad: GPIO_B0_01 for Mode: ALT3 + 0 + + + GPIO_B1_05_ALT1 + Selecting Pad: GPIO_B1_05 for Mode: ALT1 + 0x1 + + + + + + + LPSPI4_SDO_SELECT_INPUT + LPSPI4_SDO_SELECT_INPUT DAISY Register + 0x528 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_B0_02_ALT3 + Selecting Pad: GPIO_B0_02 for Mode: ALT3 + 0 + + + GPIO_B1_06_ALT1 + Selecting Pad: GPIO_B1_06 for Mode: ALT1 + 0x1 + + + + + + + LPUART2_RX_SELECT_INPUT + LPUART2_RX_SELECT_INPUT DAISY Register + 0x52C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_10_ALT2 + Selecting Pad: GPIO_SD_B1_10 for Mode: ALT2 + 0 + + + GPIO_AD_B1_03_ALT2 + Selecting Pad: GPIO_AD_B1_03 for Mode: ALT2 + 0x1 + + + + + + + LPUART2_TX_SELECT_INPUT + LPUART2_TX_SELECT_INPUT DAISY Register + 0x530 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_11_ALT2 + Selecting Pad: GPIO_SD_B1_11 for Mode: ALT2 + 0 + + + GPIO_AD_B1_02_ALT2 + Selecting Pad: GPIO_AD_B1_02 for Mode: ALT2 + 0x1 + + + + + + + LPUART3_CTS_B_SELECT_INPUT + LPUART3_CTS_B_SELECT_INPUT DAISY Register + 0x534 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_15_ALT2 + Selecting Pad: GPIO_EMC_15 for Mode: ALT2 + 0 + + + GPIO_AD_B1_04_ALT2 + Selecting Pad: GPIO_AD_B1_04 for Mode: ALT2 + 0x1 + + + + + + + LPUART3_RX_SELECT_INPUT + LPUART3_RX_SELECT_INPUT DAISY Register + 0x538 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B1_07_ALT2 + Selecting Pad: GPIO_AD_B1_07 for Mode: ALT2 + 0 + + + GPIO_EMC_14_ALT2 + Selecting Pad: GPIO_EMC_14 for Mode: ALT2 + 0x1 + + + GPIO_B0_09_ALT3 + Selecting Pad: GPIO_B0_09 for Mode: ALT3 + 0x2 + + + + + + + LPUART3_TX_SELECT_INPUT + LPUART3_TX_SELECT_INPUT DAISY Register + 0x53C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B1_06_ALT2 + Selecting Pad: GPIO_AD_B1_06 for Mode: ALT2 + 0 + + + GPIO_EMC_13_ALT2 + Selecting Pad: GPIO_EMC_13 for Mode: ALT2 + 0x1 + + + GPIO_B0_08_ALT3 + Selecting Pad: GPIO_B0_08 for Mode: ALT3 + 0x2 + + + + + + + LPUART4_RX_SELECT_INPUT + LPUART4_RX_SELECT_INPUT DAISY Register + 0x540 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_01_ALT4 + Selecting Pad: GPIO_SD_B1_01 for Mode: ALT4 + 0 + + + GPIO_EMC_20_ALT2 + Selecting Pad: GPIO_EMC_20 for Mode: ALT2 + 0x1 + + + GPIO_B1_01_ALT2 + Selecting Pad: GPIO_B1_01 for Mode: ALT2 + 0x2 + + + + + + + LPUART4_TX_SELECT_INPUT + LPUART4_TX_SELECT_INPUT DAISY Register + 0x544 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_00_ALT4 + Selecting Pad: GPIO_SD_B1_00 for Mode: ALT4 + 0 + + + GPIO_EMC_19_ALT2 + Selecting Pad: GPIO_EMC_19 for Mode: ALT2 + 0x1 + + + GPIO_B1_00_ALT2 + Selecting Pad: GPIO_B1_00 for Mode: ALT2 + 0x2 + + + + + + + LPUART5_RX_SELECT_INPUT + LPUART5_RX_SELECT_INPUT DAISY Register + 0x548 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_24_ALT2 + Selecting Pad: GPIO_EMC_24 for Mode: ALT2 + 0 + + + GPIO_B1_13_ALT1 + Selecting Pad: GPIO_B1_13 for Mode: ALT1 + 0x1 + + + + + + + LPUART5_TX_SELECT_INPUT + LPUART5_TX_SELECT_INPUT DAISY Register + 0x54C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_23_ALT2 + Selecting Pad: GPIO_EMC_23 for Mode: ALT2 + 0 + + + GPIO_B1_12_ALT1 + Selecting Pad: GPIO_B1_12 for Mode: ALT1 + 0x1 + + + + + + + LPUART6_RX_SELECT_INPUT + LPUART6_RX_SELECT_INPUT DAISY Register + 0x550 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_26_ALT2 + Selecting Pad: GPIO_EMC_26 for Mode: ALT2 + 0 + + + GPIO_AD_B0_03_ALT2 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT2 + 0x1 + + + + + + + LPUART6_TX_SELECT_INPUT + LPUART6_TX_SELECT_INPUT DAISY Register + 0x554 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_25_ALT2 + Selecting Pad: GPIO_EMC_25 for Mode: ALT2 + 0 + + + GPIO_AD_B0_02_ALT2 + Selecting Pad: GPIO_AD_B0_02 for Mode: ALT2 + 0x1 + + + + + + + LPUART7_RX_SELECT_INPUT + LPUART7_RX_SELECT_INPUT DAISY Register + 0x558 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_09_ALT2 + Selecting Pad: GPIO_SD_B1_09 for Mode: ALT2 + 0 + + + GPIO_EMC_32_ALT2 + Selecting Pad: GPIO_EMC_32 for Mode: ALT2 + 0x1 + + + + + + + LPUART7_TX_SELECT_INPUT + LPUART7_TX_SELECT_INPUT DAISY Register + 0x55C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_08_ALT2 + Selecting Pad: GPIO_SD_B1_08 for Mode: ALT2 + 0 + + + GPIO_EMC_31_ALT2 + Selecting Pad:GPIO_EMC_31 for Mode: ALT2 + 0x1 + + + + + + + LPUART8_RX_SELECT_INPUT + LPUART8_RX_SELECT_INPUT DAISY Register + 0x560 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B0_05_ALT2 + Selecting Pad: GPIO_SD_B0_05 for Mode: ALT2 + 0 + + + GPIO_AD_B1_11_ALT2 + Selecting Pad: GPIO_AD_B1_11 for Mode: ALT2 + 0x1 + + + GPIO_EMC_39_ALT2 + Selecting Pad: GPIO_EMC_39 for Mode: ALT2 + 0x2 + + + + + + + LPUART8_TX_SELECT_INPUT + LPUART8_TX_SELECT_INPUT DAISY Register + 0x564 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B0_04_ALT2 + Selecting Pad: GPIO_SD_B0_04 for Mode: ALT2 + 0 + + + GPIO_AD_B1_10_ALT2 + Selecting Pad: GPIO_AD_B1_10 for Mode: ALT2 + 0x1 + + + GPIO_EMC_38_ALT2 + Selecting Pad: GPIO_EMC_38 for Mode: ALT2 + 0x2 + + + + + + + NMI_SELECT_INPUT + NMI_GLUE_NMI_SELECT_INPUT DAISY Register + 0x568 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_12_ALT7 + Selecting Pad: GPIO_AD_B0_12 for Mode: ALT7 + 0 + + + WAKEUP_ALT7 + Selecting Pad: WAKEUP for Mode: ALT7 + 0x1 + + + + + + + QTIMER2_TIMER0_SELECT_INPUT + QTIMER2_TIMER0_SELECT_INPUT DAISY Register + 0x56C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_19_ALT4 + Selecting Pad: GPIO_EMC_19 for Mode: ALT4 + 0 + + + GPIO_B0_03_ALT1 + Selecting Pad: GPIO_B0_03 for Mode: ALT1 + 0x1 + + + + + + + QTIMER2_TIMER1_SELECT_INPUT + QTIMER2_TIMER1_SELECT_INPUT DAISY Register + 0x570 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_20_ALT4 + Selecting Pad: GPIO_EMC_20 for Mode: ALT4 + 0 + + + GPIO_B0_04_ALT1 + Selecting Pad: GPIO_B0_04 for Mode: ALT1 + 0x1 + + + + + + + QTIMER2_TIMER2_SELECT_INPUT + QTIMER2_TIMER2_SELECT_INPUT DAISY Register + 0x574 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_21_ALT4 + Selecting Pad: GPIO_EMC_21 for Mode: ALT4 + 0 + + + GPIO_B0_05_ALT1 + Selecting Pad: GPIO_B0_05 for Mode: ALT1 + 0x1 + + + + + + + QTIMER2_TIMER3_SELECT_INPUT + QTIMER2_TIMER3_SELECT_INPUT DAISY Register + 0x578 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_22_ALT4 + Selecting Pad: GPIO_EMC_22 for Mode: ALT4 + 0 + + + GPIO_B1_09_ALT1 + Selecting Pad: GPIO_B1_09 for Mode: ALT1 + 0x1 + + + + + + + QTIMER3_TIMER0_SELECT_INPUT + QTIMER3_TIMER0_SELECT_INPUT DAISY Register + 0x57C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_15_ALT4 + Selecting Pad: GPIO_EMC_15 for Mode: ALT4 + 0 + + + GPIO_AD_B1_00_ALT1 + Selecting Pad: GPIO_AD_B1_00 for Mode: ALT1 + 0x1 + + + GPIO_B0_06_ALT1 + Selecting Pad: GPIO_B0_06 for Mode: ALT1 + 0x2 + + + + + + + QTIMER3_TIMER1_SELECT_INPUT + QTIMER3_TIMER1_SELECT_INPUT DAISY Register + 0x580 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_AD_B1_01_ALT1 + Selecting Pad: GPIO_AD_B1_01 for Mode: ALT1 + 0 + + + GPIO_EMC_16_ALT4 + Selecting Pad: GPIO_EMC_16 for Mode: ALT4 + 0x1 + + + GPIO_B0_07_ALT1 + Selecting Pad: GPIO_B0_07 for Mode: ALT1 + 0x2 + + + + + + + QTIMER3_TIMER2_SELECT_INPUT + QTIMER3_TIMER2_SELECT_INPUT DAISY Register + 0x584 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_17_ALT4 + Selecting Pad: GPIO_EMC_17 for Mode: ALT4 + 0 + + + GPIO_AD_B1_02_ALT1 + Selecting Pad: GPIO_AD_B1_02 for Mode: ALT1 + 0x1 + + + GPIO_B0_08_ALT1 + Selecting Pad: GPIO_B0_08 for Mode: ALT1 + 0x2 + + + + + + + QTIMER3_TIMER3_SELECT_INPUT + QTIMER3_TIMER3_SELECT_INPUT DAISY Register + 0x588 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_18_ALT4 + Selecting Pad: GPIO_EMC_18 for Mode: ALT4 + 0 + + + GPIO_AD_B1_03_ALT1 + Selecting Pad: GPIO_AD_B1_03 for Mode: ALT1 + 0x1 + + + GPIO_B1_10_ALT1 + Selecting Pad: GPIO_B1_10 for Mode: ALT1 + 0x2 + + + + + + + SAI1_MCLK2_SELECT_INPUT + SAI1_MCLK2_SELECT_INPUT DAISY Register + 0x58C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_03_ALT3 + Selecting Pad: GPIO_SD_B1_03 for Mode: ALT3 + 0 + + + GPIO_AD_B1_09_ALT3 + Selecting Pad: GPIO_AD_B1_09 for Mode: ALT3 + 0x1 + + + GPIO_B0_13_ALT3 + Selecting Pad: GPIO_B0_13 for Mode: ALT3 + 0x2 + + + + + + + SAI1_RX_BCLK_SELECT_INPUT + SAI1_RX_BCLK_SELECT_INPUT DAISY Register + 0x590 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_05_ALT3 + Selecting Pad: GPIO_SD_B1_05 for Mode: ALT3 + 0 + + + GPIO_AD_B1_11_ALT3 + Selecting Pad: GPIO_AD_B1_11 for Mode: ALT3 + 0x1 + + + GPIO_B0_15_ALT3 + Selecting Pad: GPIO_B0_15 for Mode: ALT3 + 0x2 + + + + + + + SAI1_RX_DATA0_SELECT_INPUT + SAI1_RX_DATA0_SELECT_INPUT DAISY Register + 0x594 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_06_ALT3 + Selecting Pad: GPIO_SD_B1_06 for Mode: ALT3 + 0 + + + GPIO_AD_B1_12_ALT3 + Selecting Pad: GPIO_AD_B1_12 for Mode: ALT3 + 0x1 + + + GPIO_B1_00_ALT3 + Selecting Pad: GPIO_B1_00 for Mode: ALT3 + 0x2 + + + + + + + SAI1_RX_DATA1_SELECT_INPUT + SAI1_RX_DATA1_SELECT_INPUT DAISY Register + 0x598 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_00_ALT3 + Selecting Pad: GPIO_SD_B1_00 for Mode: ALT3 + 0 + + + GPIO_B0_10_ALT3 + Selecting Pad: GPIO_B0_10 for Mode: ALT3 + 0x1 + + + + + + + SAI1_RX_DATA2_SELECT_INPUT + SAI1_RX_DATA2_SELECT_INPUT DAISY Register + 0x59C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_01_ALT3 + Selecting Pad: GPIO_SD_B1_01 for Mode: ALT3 + 0 + + + GPIO_B0_11_ALT3 + Selecting Pad: GPIO_B0_11 for Mode: ALT3 + 0x1 + + + + + + + SAI1_RX_DATA3_SELECT_INPUT + SAI1_RX_DATA3_SELECT_INPUT DAISY Register + 0x5A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_02_ALT3 + Selecting Pad: GPIO_SD_B1_02 for Mode: ALT3 + 0 + + + GPIO_B0_12_ALT3 + Selecting Pad: GPIO_B0_12 for Mode: ALT3 + 0x1 + + + + + + + SAI1_RX_SYNC_SELECT_INPUT + SAI1_RX_SYNC_SELECT_INPUT DAISY Register + 0x5A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_04_ALT3 + Selecting Pad: GPIO_SD_B1_04 for Mode: ALT3 + 0 + + + GPIO_AD_B1_10_ALT3 + Selecting Pad: GPIO_AD_B1_10 for Mode: ALT3 + 0x1 + + + GPIO_B0_14_ALT3 + Selecting Pad: GPIO_B0_14 for Mode: ALT3 + 0x2 + + + + + + + SAI1_TX_BCLK_SELECT_INPUT + SAI1_TX_BCLK_SELECT_INPUT DAISY Register + 0x5A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_08_ALT3 + Selecting Pad: GPIO_SD_B1_08 for Mode: ALT3 + 0 + + + GPIO_AD_B1_14_ALT3 + Selecting Pad: GPIO_AD_B1_14 for Mode: ALT3 + 0x1 + + + GPIO_B1_02_ALT3 + Selecting Pad: GPIO_B1_02 for Mode: ALT3 + 0x2 + + + + + + + SAI1_TX_SYNC_SELECT_INPUT + SAI1_TX_SYNC_SELECT_INPUT DAISY Register + 0x5AC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B1_09_ALT3 + Selecting Pad: GPIO_SD_B1_09 for Mode: ALT3 + 0 + + + GPIO_AD_B1_15_ALT3 + Selecting Pad: GPIO_AD_B1_15 for Mode: ALT3 + 0x1 + + + GPIO_B1_03_ALT3 + Selecting Pad: GPIO_B1_03 for Mode: ALT3 + 0x2 + + + + + + + SAI2_MCLK2_SELECT_INPUT + SAI2_MCLK2_SELECT_INPUT DAISY Register + 0x5B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_07_ALT2 + Selecting Pad: GPIO_EMC_07 for Mode: ALT2 + 0 + + + GPIO_AD_B0_10_ALT3 + Selecting Pad: GPIO_AD_B0_10 for Mode: ALT3 + 0x1 + + + + + + + SAI2_RX_BCLK_SELECT_INPUT + SAI2_RX_BCLK_SELECT_INPUT DAISY Register + 0x5B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_10_ALT2 + Selecting Pad: GPIO_EMC_10 for Mode: ALT2 + 0 + + + GPIO_AD_B0_06_ALT3 + Selecting Pad: GPIO_AD_B0_06 for Mode: ALT3 + 0x1 + + + + + + + SAI2_RX_DATA0_SELECT_INPUT + SAI2_RX_DATA0_SELECT_INPUT DAISY Register + 0x5B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_08_ALT2 + Selecting Pad: GPIO_EMC_08 for Mode: ALT2 + 0 + + + GPIO_AD_B0_08_ALT3 + Selecting Pad: GPIO_AD_B0_08 for Mode: ALT3 + 0x1 + + + + + + + SAI2_RX_SYNC_SELECT_INPUT + SAI2_RX_SYNC_SELECT_INPUT DAISY Register + 0x5BC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_09_ALT2 + Selecting Pad: GPIO_EMC_09 for Mode: ALT2 + 0 + + + GPIO_AD_B0_07_ALT3 + Selecting Pad: GPIO_AD_B0_07 for Mode: ALT3 + 0x1 + + + + + + + SAI2_TX_BCLK_SELECT_INPUT + SAI2_TX_BCLK_SELECT_INPUT DAISY Register + 0x5C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_06_ALT2 + Selecting Pad: GPIO_EMC_06 for Mode: ALT2 + 0 + + + GPIO_AD_B0_05_ALT3 + Selecting Pad: GPIO_AD_B0_05 for Mode: ALT3 + 0x1 + + + + + + + SAI2_TX_SYNC_SELECT_INPUT + SAI2_TX_SYNC_SELECT_INPUT DAISY Register + 0x5C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_05_ALT2 + Selecting Pad: GPIO_EMC_05 for Mode: ALT2 + 0 + + + GPIO_AD_B0_04_ALT3 + Selecting Pad: GPIO_AD_B0_04 for Mode: ALT3 + 0x1 + + + + + + + SPDIF_IN_SELECT_INPUT + SPDIF_IN_SELECT_INPUT DAISY Register + 0x5C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_03_ALT3 + Selecting Pad: GPIO_AD_B1_03 for Mode: ALT3 + 0 + + + GPIO_EMC_16_ALT3 + Selecting Pad: GPIO_EMC_16 for Mode: ALT3 + 0x1 + + + + + + + USB_OTG2_OC_SELECT_INPUT + USB_OTG2_OC_SELECT_INPUT DAISY Register + 0x5CC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_14_ALT0 + Selecting Pad: GPIO_AD_B0_14 for Mode: ALT0 + 0 + + + GPIO_EMC_40_ALT3 + Selecting Pad: GPIO_EMC_40 for Mode: ALT3 + 0x1 + + + + + + + USB_OTG1_OC_SELECT_INPUT + USB_OTG1_OC_SELECT_INPUT DAISY Register + 0x5D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_03_ALT3 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT3 + 0 + + + GPIO_AD_B1_03_ALT0 + Selecting Pad: GPIO_AD_B1_03 for Mode: ALT0 + 0x1 + + + + + + + USDHC1_CD_B_SELECT_INPUT + USDHC1_CD_B_SELECT_INPUT DAISY Register + 0x5D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_35_ALT6 + Selecting Pad: GPIO_EMC_35 for Mode: ALT6 + 0 + + + GPIO_AD_B1_02_ALT6 + Selecting Pad: GPIO_AD_B1_02 for Mode: ALT6 + 0x1 + + + GPIO_B1_12_ALT6 + Selecting Pad: GPIO_B1_12 for Mode: ALT6 + 0x2 + + + + + + + USDHC1_WP_SELECT_INPUT + USDHC1_WP_SELECT_INPUT DAISY Register + 0x5D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_12_ALT3 + Selecting Pad: GPIO_EMC_12 for Mode: ALT3 + 0 + + + GPIO_EMC_36_ALT6 + Selecting Pad: GPIO_EMC_36for Mode: ALT6 + 0x1 + + + GPIO_AD_B1_00_ALT6 + Selecting Pad:GPIO_AD_B1_00 for Mode: ALT6 + 0x2 + + + GPIO_B1_13_ALT6 + Selecting Pad: GPIO_B1_13 for Mode: ALT6 + 0x3 + + + + + + + USDHC2_CLK_SELECT_INPUT + USDHC2_CLK_SELECT_INPUT DAISY Register + 0x5DC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_04_ALT0 + Selecting Pad: GPIO_SD_B1_04 for Mode: ALT0 + 0 + + + GPIO_AD_B1_09_ALT6 + Selecting Pad: GPIO_AD_B1_09 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_CD_B_SELECT_INPUT + USDHC2_CD_B_SELECT_INPUT DAISY Register + 0x5E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_03_ALT6 + Selecting Pad:GPIO_AD_B1_03 for Mode: ALT6 + 0 + + + GPIO_EMC_39_ALT6 + Selecting Pad: GPIO_EMC_39 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_CMD_SELECT_INPUT + USDHC2_CMD_SELECT_INPUT DAISY Register + 0x5E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_05_ALT0 + Selecting Pad: GPIO_SD_B1_05 for Mode: ALT0 + 0 + + + GPIO_AD_B1_08_ALT6 + Selecting Pad: GPIO_AD_B1_08 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA0_SELECT_INPUT + USDHC2_DATA0_SELECT_INPUT DAISY Register + 0x5E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_03_ALT0 + Selecting Pad: GPIO_SD_B1_03 for Mode: ALT0 + 0 + + + GPIO_AD_B1_04_ALT6 + Selecting Pad:GPIO_AD_B1_04 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA1_SELECT_INPUT + USDHC2_DATA1_SELECT_INPUT DAISY Register + 0x5EC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_02_ALT0 + Selecting Pad: GPIO_SD_B1_02 for Mode: ALT0 + 0 + + + GPIO_AD_B1_05_ALT6 + Selecting Pad: GPIO_AD_B1_05 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA2_SELECT_INPUT + USDHC2_DATA2_SELECT_INPUT DAISY Register + 0x5F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_01_ALT0 + Selecting Pad: GPIO_SD_B1_01 for Mode: ALT0 + 0 + + + GPIO_AD_B1_06_ALT6 + Selecting Pad: GPIO_AD_B1_06 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA3_SELECT_INPUT + USDHC2_DATA3_SELECT_INPUT DAISY Register + 0x5F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_00_ALT0 + Selecting Pad: GPIO_SD_B1_00 for Mode: ALT0 + 0 + + + GPIO_AD_B1_07_ALT6 + Selecting Pad: GPIO_AD_B1_07 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA4_SELECT_INPUT + USDHC2_DATA4_SELECT_INPUT DAISY Register + 0x5F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_08_ALT0 + Selecting Pad: GPIO_SD_B1_08 for Mode: ALT0 + 0 + + + GPIO_AD_B1_12_ALT6 + Selecting Pad: GPIO_AD_B1_12 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA5_SELECT_INPUT + USDHC2_DATA5_SELECT_INPUT DAISY Register + 0x5FC + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_09_ALT0 + Selecting Pad: GPIO_SD_B1_09 for Mode: ALT0 + 0 + + + GPIO_AD_B1_13_ALT6 + Selecting Pad: GPIO_AD_B1_13 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA6_SELECT_INPUT + USDHC2_DATA6_SELECT_INPUT DAISY Register + 0x600 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_10_ALT0 + Selecting Pad: GPIO_SD_B1_10 for Mode: ALT0 + 0 + + + GPIO_AD_B1_14_ALT6 + Selecting Pad: GPIO_AD_B1_14 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_DATA7_SELECT_INPUT + USDHC2_DATA7_SELECT_INPUT DAISY Register + 0x604 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_SD_B1_11_ALT0 + Selecting Pad: GPIO_SD_B1_11 for Mode: ALT0 + 0 + + + GPIO_AD_B1_15_ALT6 + Selecting Pad: GPIO_AD_B1_15 for Mode: ALT6 + 0x1 + + + + + + + USDHC2_WP_SELECT_INPUT + USDHC2_WP_SELECT_INPUT DAISY Register + 0x608 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_37_ALT6 + Selecting Pad: GPIO_EMC_37 for Mode: ALT6 + 0 + + + GPIO_AD_B1_10_ALT6 + Selecting Pad: GPIO_AD_B1_10 for Mode: ALT6 + 0x1 + + + + + + + XBAR1_IN02_SELECT_INPUT + XBAR1_IN02_SELECT_INPUT DAISY Register + 0x60C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_00_ALT3 + Selecting Pad: GPIO_EMC_00 for Mode: ALT3 + 0 + + + GPIO_B1_14_ALT3 + Selecting Pad: GPIO_B1_14 for Mode: ALT3 + 0x1 + + + + + + + XBAR1_IN03_SELECT_INPUT + XBAR1_IN03_SELECT_INPUT DAISY Register + 0x610 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_01_ALT3 + Selecting Pad: GPIO_EMC_01 for Mode: ALT3 + 0 + + + GPIO_B1_15_ALT3 + Selecting Pad: GPIO_B1_15 for Mode: ALT3 + 0x1 + + + + + + + XBAR1_IN04_SELECT_INPUT + XBAR1_IN04_SELECT_INPUT DAISY Register + 0x614 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_02_ALT3 + Selecting Pad: GPIO_EMC_02 for Mode: ALT3 + 0 + + + GPIO_SD_B0_00_ALT3 + Selecting Pad: GPIO_SD_B0_00 for Mode: ALT3 + 0x1 + + + + + + + XBAR1_IN05_SELECT_INPUT + XBAR1_IN05_SELECT_INPUT DAISY Register + 0x618 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_03_ALT3 + Selecting Pad: GPIO_EMC_03 for Mode: ALT3 + 0 + + + GPIO_SD_B0_01_ALT3 + Selecting Pad: GPIO_SD_B0_01 for Mode: ALT3 + 0x1 + + + + + + + XBAR1_IN06_SELECT_INPUT + XBAR1_IN06_SELECT_INPUT DAISY Register + 0x61C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_04_ALT3 + Selecting Pad: GPIO_EMC_04 for Mode: ALT3 + 0 + + + GPIO_SD_B0_02_ALT3 + Selecting Pad: GPIO_SD_B0_02 for Mode: ALT3 + 0x1 + + + + + + + XBAR1_IN07_SELECT_INPUT + XBAR1_IN07_SELECT_INPUT DAISY Register + 0x620 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_05_ALT3 + Selecting Pad: GPIO_EMC_05 for Mode: ALT3 + 0 + + + GPIO_SD_B0_03_ALT3 + Selecting Pad: GPIO_SD_B0_03 for Mode: ALT3 + 0x1 + + + + + + + XBAR1_IN08_SELECT_INPUT + XBAR1_IN08_SELECT_INPUT DAISY Register + 0x624 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_06_ALT3 + Selecting Pad: GPIO_EMC_06 for Mode: ALT3 + 0 + + + GPIO_SD_B0_04_ALT3 + Selecting Pad: GPIO_SD_B0_04 for Mode: ALT3 + 0x1 + + + + + + + XBAR1_IN09_SELECT_INPUT + XBAR1_IN09_SELECT_INPUT DAISY Register + 0x628 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_07_ALT3 + Selecting Pad: GPIO_EMC_07 for Mode: ALT3 + 0 + + + GPIO_SD_B0_05_ALT3 + Selecting Pad: GPIO_SD_B0_05 for Mode: ALT3 + 0x1 + + + + + + + XBAR1_IN17_SELECT_INPUT + XBAR1_IN17_SELECT_INPUT DAISY Register + 0x62C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_08_ALT3 + Selecting Pad: GPIO_EMC_08 for Mode: ALT3 + 0 + + + GPIO_AD_B0_03_ALT1 + Selecting Pad: GPIO_AD_B0_03 for Mode: ALT1 + 0x1 + + + GPIO_AD_B0_05_ALT6 + Selecting Pad: GPIO_AD_B0_05 for Mode: ALT6 + 0x2 + + + GPIO_B1_03_ALT1 + Selecting Pad: GPIO_B1_03 for Mode: ALT1 + 0x3 + + + + + + + XBAR1_IN18_SELECT_INPUT + XBAR1_IN18_SELECT_INPUT DAISY Register + 0x630 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_35_ALT1 + Selecting Pad: GPIO_EMC_35 for Mode: ALT1 + 0 + + + GPIO_AD_B0_06_ALT6 + Selecting Pad: GPIO_AD_B0_06 for Mode: ALT6 + 0x1 + + + + + + + XBAR1_IN20_SELECT_INPUT + XBAR1_IN20_SELECT_INPUT DAISY Register + 0x634 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_15_ALT1 + Selecting Pad: GPIO_EMC_15 for Mode: ALT1 + 0 + + + GPIO_AD_B0_08_ALT6 + Selecting Pad: GPIO_AD_B0_08 for Mode: ALT6 + 0x1 + + + + + + + XBAR1_IN22_SELECT_INPUT + XBAR1_IN22_SELECT_INPUT DAISY Register + 0x638 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_36_ALT1 + Selecting Pad: GPIO_EMC_36 for Mode: ALT1 + 0 + + + GPIO_AD_B0_10_ALT6 + Selecting Pad: GPIO_AD_B0_10 for Mode: ALT6 + 0x1 + + + + + + + XBAR1_IN23_SELECT_INPUT + XBAR1_IN23_SELECT_INPUT DAISY Register + 0x63C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_37_ALT1 + Selecting Pad: GPIO_EMC_37 for Mode: ALT1 + 0 + + + GPIO_AD_B0_11_ALT6 + Selecting Pad: GPIO_AD_B0_11 for Mode: ALT6 + 0x1 + + + + + + + XBAR1_IN24_SELECT_INPUT + XBAR1_IN24_SELECT_INPUT DAISY Register + 0x640 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_12_ALT1 + Selecting Pad: GPIO_EMC_12 for Mode: ALT1 + 0 + + + GPIO_AD_B0_14_ALT1 + Selecting Pad: GPIO_AD_B0_14 for Mode: ALT1 + 0x1 + + + + + + + XBAR1_IN14_SELECT_INPUT + XBAR1_IN14_SELECT_INPUT DAISY Register + 0x644 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_00_ALT1 + Selecting Pad: GPIO_AD_B0_00 for Mode: ALT1 + 0 + + + GPIO_B1_00_ALT1 + Selecting Pad:GPIO_B1_00 for Mode: ALT1 + 0x1 + + + + + + + XBAR1_IN15_SELECT_INPUT + XBAR1_IN15_SELECT_INPUT DAISY Register + 0x648 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_01_ALT1 + Selecting Pad: GPIO_AD_B0_01 for Mode: ALT1 + 0 + + + GPIO_B1_01_ALT1 + Selecting Pad: GPIO_B1_01 for Mode: ALT1 + 0x1 + + + + + + + XBAR1_IN16_SELECT_INPUT + XBAR1_IN16_SELECT_INPUT DAISY Register + 0x64C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_02_ALT1 + Selecting Pad: GPIO_AD_B0_02 for Mode: ALT1 + 0 + + + GPIO_B1_02_ALT1 + Selecting Pad: GPIO_B1_02 for Mode: ALT1 + 0x1 + + + + + + + XBAR1_IN25_SELECT_INPUT + XBAR1_IN25_SELECT_INPUT DAISY Register + 0x650 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_15_ALT1 + Selecting Pad: GPIO_AD_B0_15 for Mode: ALT1 + 0 + + + GPIO_EMC_13_ALT1 + Selecting Pad: GPIO_EMC_13 for Mode: ALT1 + 0x1 + + + + + + + XBAR1_IN19_SELECT_INPUT + XBAR1_IN19_SELECT_INPUT DAISY Register + 0x654 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_14_ALT1 + Selecting Pad: GPIO_EMC_14 for Mode: ALT1 + 0 + + + GPIO_AD_B0_07_ALT6 + Selecting Pad: GPIO_AD_B0_07 for Mode: ALT6 + 0x1 + + + + + + + XBAR1_IN21_SELECT_INPUT + XBAR1_IN23_SELECT_INPUT DAISY Register + 0x658 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_16_ALT1 + Selecting Pad: GPIO_EMC_16 for Mode: ALT1 + 0 + + + GPIO_AD_B0_09_ALT6 + Selecting Pad: GPIO_AD_B0_09 for Mode: ALT6 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B0_00 + SW_MUX_CTL_PAD_GPIO_SPI_B0_00 SW MUX Control Register + 0x65C + 32 + read-write + 0 + 0xFFFFFFFF + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B0_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B0_01 + SW_MUX_CTL_PAD_GPIO_SPI_B0_01 SW MUX Control Register + 0x660 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI2_B_SCLK of instance: flexspi2 + 0 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B0_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B0_02 + SW_MUX_CTL_PAD_GPIO_SPI_B0_02 SW MUX Control Register + 0x664 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA00 of instance: flexspi2 + 0 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B0_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B0_03 + SW_MUX_CTL_PAD_GPIO_SPI_B0_03 SW MUX Control Register + 0x668 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI2_B_DATA02 of instance: flexspi2 + 0 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B0_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B0_04 + SW_MUX_CTL_PAD_GPIO_SPI_B0_04 SW MUX Control Register + 0x66C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI2_B_DATA03 of instance: flexspi2 + 0 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B0_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B0_05 + SW_MUX_CTL_PAD_GPIO_SPI_B0_05 SW MUX Control Register + 0x670 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI2_A_SS0_B of instance: flexspi2 + 0 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B0_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B0_06 + SW_MUX_CTL_PAD_GPIO_SPI_B0_06 SW MUX Control Register + 0x674 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA02 of instance: flexspi2 + 0 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B0_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B0_07 + SW_MUX_CTL_PAD_GPIO_SPI_B0_07 SW MUX Control Register + 0x678 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI2_B_DATA01 of instance: flexspi2 + 0 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B0_07 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B0_08 + SW_MUX_CTL_PAD_GPIO_SPI_B0_08 SW MUX Control Register + 0x67C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI2_A_SCLK of instance: flexspi2 + 0 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B0_08 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B0_09 + SW_MUX_CTL_PAD_GPIO_SPI_B0_09 SW MUX Control Register + 0x680 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI2_A_DQS of instance: flexspi2 + 0 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B0_09 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B0_10 + SW_MUX_CTL_PAD_GPIO_SPI_B0_10 SW MUX Control Register + 0x684 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA03 of instance: flexspi2 + 0 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B0_10 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B0_11 + SW_MUX_CTL_PAD_GPIO_SPI_B0_11 SW MUX Control Register + 0x688 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI2_B_DATA00 of instance: flexspi2 + 0 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B0_11 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B0_12 + SW_MUX_CTL_PAD_GPIO_SPI_B0_12 SW MUX Control Register + 0x68C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA01 of instance: flexspi2 + 0 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B0_12 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B0_13 + SW_MUX_CTL_PAD_GPIO_SPI_B0_13 SW MUX Control Register + 0x690 + 32 + read-write + 0 + 0xFFFFFFFF + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B0_13 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B1_00 + SW_MUX_CTL_PAD_GPIO_SPI_B1_00 SW MUX Control Register + 0x694 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI2_A_DQS of instance: flexspi2 + 0 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B1_00 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B1_01 + SW_MUX_CTL_PAD_GPIO_SPI_B1_01 SW MUX Control Register + 0x698 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA03 of instance: flexspi2 + 0 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B1_01 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B1_02 + SW_MUX_CTL_PAD_GPIO_SPI_B1_02 SW MUX Control Register + 0x69C + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA02 of instance: flexspi2 + 0 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B1_02 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B1_03 + SW_MUX_CTL_PAD_GPIO_SPI_B1_03 SW MUX Control Register + 0x6A0 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA01 of instance: flexspi2 + 0 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B1_03 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B1_04 + SW_MUX_CTL_PAD_GPIO_SPI_B1_04 SW MUX Control Register + 0x6A4 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI2_A_DATA00 of instance: flexspi2 + 0 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B1_04 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B1_05 + SW_MUX_CTL_PAD_GPIO_SPI_B1_05 SW MUX Control Register + 0x6A8 + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI2_A_SCLK of instance: flexspi2 + 0 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B1_05 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B1_06 + SW_MUX_CTL_PAD_GPIO_SPI_B1_06 SW MUX Control Register + 0x6AC + 32 + read-write + 0x5 + 0xFFFFFFFF + + + MUX_MODE + MUX Mode Select Field. + 0 + 3 + read-write + + + ALT0 + Select mux mode: ALT0 mux port: FLEXSPI2_A_SS0_B of instance: flexspi2 + 0 + + + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B1_06 + 0x1 + + + + + + + SW_MUX_CTL_PAD_GPIO_SPI_B1_07 + SW_MUX_CTL_PAD_GPIO_SPI_B1_07 SW MUX Control Register + 0x6B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SION + Software Input On Field. + 4 + 1 + read-write + + + DISABLED + Input Path is determined by functionality + 0 + + + ENABLED + Force input path of pad GPIO_SPI_B1_07 + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B0_00 + SW_PAD_CTL_PAD_GPIO_SPI_B0_00 SW PAD Control Register + 0x6B4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B0_01 + SW_PAD_CTL_PAD_GPIO_SPI_B0_01 SW PAD Control Register + 0x6B8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B0_02 + SW_PAD_CTL_PAD_GPIO_SPI_B0_02 SW PAD Control Register + 0x6BC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B0_03 + SW_PAD_CTL_PAD_GPIO_SPI_B0_03 SW PAD Control Register + 0x6C0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B0_04 + SW_PAD_CTL_PAD_GPIO_SPI_B0_04 SW PAD Control Register + 0x6C4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B0_05 + SW_PAD_CTL_PAD_GPIO_SPI_B0_05 SW PAD Control Register + 0x6C8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B0_06 + SW_PAD_CTL_PAD_GPIO_SPI_B0_06 SW PAD Control Register + 0x6CC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B0_07 + SW_PAD_CTL_PAD_GPIO_SPI_B0_07 SW PAD Control Register + 0x6D0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B0_08 + SW_PAD_CTL_PAD_GPIO_SPI_B0_08 SW PAD Control Register + 0x6D4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B0_09 + SW_PAD_CTL_PAD_GPIO_SPI_B0_09 SW PAD Control Register + 0x6D8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B0_10 + SW_PAD_CTL_PAD_GPIO_SPI_B0_10 SW PAD Control Register + 0x6DC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B0_11 + SW_PAD_CTL_PAD_GPIO_SPI_B0_11 SW PAD Control Register + 0x6E0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B0_12 + SW_PAD_CTL_PAD_GPIO_SPI_B0_12 SW PAD Control Register + 0x6E4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B0_13 + SW_PAD_CTL_PAD_GPIO_SPI_B0_13 SW PAD Control Register + 0x6E8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B1_00 + SW_PAD_CTL_PAD_GPIO_SPI_B1_00 SW PAD Control Register + 0x6EC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B1_01 + SW_PAD_CTL_PAD_GPIO_SPI_B1_01 SW PAD Control Register + 0x6F0 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B1_02 + SW_PAD_CTL_PAD_GPIO_SPI_B1_02 SW PAD Control Register + 0x6F4 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B1_03 + SW_PAD_CTL_PAD_GPIO_SPI_B1_03 SW PAD Control Register + 0x6F8 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B1_04 + SW_PAD_CTL_PAD_GPIO_SPI_B1_04 SW PAD Control Register + 0x6FC + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B1_05 + SW_PAD_CTL_PAD_GPIO_SPI_B1_05 SW PAD Control Register + 0x700 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B1_06 + SW_PAD_CTL_PAD_GPIO_SPI_B1_06 SW PAD Control Register + 0x704 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + SW_PAD_CTL_PAD_GPIO_SPI_B1_07 + SW_PAD_CTL_PAD_GPIO_SPI_B1_07 SW PAD Control Register + 0x708 + 32 + read-write + 0x10B0 + 0xFFFFFFFF + + + SRE + Slew Rate Field + 0 + 1 + read-write + + + SRE_0_Slow_Slew_Rate + Slow Slew Rate + 0 + + + SRE_1_Fast_Slew_Rate + Fast Slew Rate + 0x1 + + + + + DSE + Drive Strength Field + 3 + 3 + read-write + + + DSE_0_output_driver_disabled_ + output driver disabled; + 0 + + + DSE_1_R0_150_Ohm___3_3V__260_Ohm_1_8V_ + R0(150 Ohm @ 3.3V, 260 Ohm@1.8V) + 0x1 + + + DSE_2_R0_2 + R0/2 + 0x2 + + + DSE_3_R0_3 + R0/3 + 0x3 + + + DSE_4_R0_4 + R0/4 + 0x4 + + + DSE_5_R0_5 + R0/5 + 0x5 + + + DSE_6_R0_6 + R0/6 + 0x6 + + + DSE_7_R0_7 + R0/7 + 0x7 + + + + + SPEED + Speed Field + 6 + 2 + read-write + + + SPEED_0_low_50MHz_ + low(50MHz) + 0 + + + SPEED_1_medium_100MHz_ + medium(100MHz) + 0x1 + + + SPEED_2_medium_100MHz_ + medium(100MHz) + 0x2 + + + SPEED_3_max_200MHz_ + max(200MHz) + 0x3 + + + + + ODE + Open Drain Enable Field + 11 + 1 + read-write + + + ODE_0_Open_Drain_Disabled + Open Drain Disabled + 0 + + + ODE_1_Open_Drain_Enabled + Open Drain Enabled + 0x1 + + + + + PKE + Pull / Keep Enable Field + 12 + 1 + read-write + + + PKE_0_Pull_Keeper_Disabled + Pull/Keeper Disabled + 0 + + + PKE_1_Pull_Keeper_Enabled + Pull/Keeper Enabled + 0x1 + + + + + PUE + Pull / Keep Select Field + 13 + 1 + read-write + + + PUE_0_Keeper + Keeper + 0 + + + PUE_1_Pull + Pull + 0x1 + + + + + PUS + Pull Up / Down Config. Field + 14 + 2 + read-write + + + PUS_0_100K_Ohm_Pull_Down + 100K Ohm Pull Down + 0 + + + PUS_1_47K_Ohm_Pull_Up + 47K Ohm Pull Up + 0x1 + + + PUS_2_100K_Ohm_Pull_Up + 100K Ohm Pull Up + 0x2 + + + PUS_3_22K_Ohm_Pull_Up + 22K Ohm Pull Up + 0x3 + + + + + HYS + Hyst. Enable Field + 16 + 1 + read-write + + + HYS_0_Hysteresis_Disabled + Hysteresis Disabled + 0 + + + HYS_1_Hysteresis_Enabled + Hysteresis Enabled + 0x1 + + + + + + + ENET2_IPG_CLK_RMII_SELECT_INPUT + ENET2_IPG_CLK_RMII_SELECT_INPUT DAISY Register + 0x70C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_33_ALT9 + Selecting Pad: GPIO_EMC_33 for Mode: ALT9 + 0 + + + GPIO_SD_B0_01_ALT9 + Selecting Pad: GPIO_SD_B0_01 for Mode: ALT9 + 0x1 + + + GPIO_B0_15_ALT9 + Selecting Pad: GPIO_B0_15 for Mode: ALT9 + 0x2 + + + + + + + ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT + ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT DAISY Register + 0x710 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_39_ALT8 + Selecting Pad: GPIO_EMC_39 for Mode: ALT8 + 0 + + + GPIO_B0_01_ALT8 + Selecting Pad: GPIO_B0_01 for Mode: ALT8 + 0x1 + + + + + + + ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_0 + ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_0 DAISY Register + 0x714 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_35_ALT8 + Selecting Pad: GPIO_EMC_35 for Mode: ALT8 + 0 + + + GPIO_SD_B0_03_ALT8 + Selecting Pad: GPIO_SD_B0_03 for Mode: ALT8 + 0x1 + + + GPIO_B1_01_ALT8 + Selecting Pad: GPIO_B1_01 for Mode: ALT8 + 0x2 + + + + + + + ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_1 + ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_1 DAISY Register + 0x718 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_36_ALT8 + Selecting Pad: GPIO_EMC_36 for Mode: ALT8 + 0 + + + GPIO_SD_B0_04_ALT8 + Selecting Pad: GPIO_SD_B0_04 for Mode: ALT8 + 0x1 + + + GPIO_B1_02_ALT8 + Selecting Pad: GPIO_B1_02 for Mode: ALT8 + 0x2 + + + + + + + ENET2_IPP_IND_MAC0_RXEN_SELECT_INPUT + ENET2_IPP_IND_MAC0_RXEN_SELECT_INPUT DAISY Register + 0x71C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_37_ALT8 + Selecting Pad: GPIO_EMC_37 for Mode: ALT8 + 0 + + + GPIO_SD_B0_05_ALT8 + Selecting Pad: GPIO_SD_B0_05 for Mode: ALT8 + 0x1 + + + GPIO_B1_03_ALT8 + Selecting Pad: GPIO_B1_03 for Mode: ALT8 + 0x2 + + + + + + + ENET2_IPP_IND_MAC0_RXERR_SELECT_INPUT + ENET2_IPP_IND_MAC0_RXERR_SELECT_INPUT DAISY Register + 0x720 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_34_ALT8 + Selecting Pad: GPIO_EMC_34 for Mode: ALT8 + 0 + + + GPIO_SD_B0_02_ALT8 + Selecting Pad: GPIO_SD_B0_02 for Mode: ALT8 + 0x1 + + + GPIO_B1_00_ALT8 + Selecting Pad: GPIO_B1_00 for Mode: ALT8 + 0x2 + + + + + + + ENET2_IPP_IND_MAC0_TIMER_SELECT_INPUT_0 + ENET2_IPP_IND_MAC0_TIMER_SELECT_INPUT_0 DAISY Register + 0x724 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B1_01_ALT8 + Selecting Pad: GPIO_AD_B1_01 for Mode: ALT8 + 0 + + + GPIO_B0_03_ALT8 + Selecting Pad: GPIO_B0_03 for Mode: ALT8 + 0x1 + + + + + + + ENET2_IPP_IND_MAC0_TXCLK_SELECT_INPUT + ENET2_IPP_IND_MAC0_TXCLK_SELECT_INPUT DAISY Register + 0x728 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_33_ALT8 + Selecting Pad: GPIO_EMC_33 for Mode: ALT8 + 0 + + + GPIO_SD_B0_01_ALT8 + Selecting Pad: GPIO_SD_B0_01 for Mode: ALT8 + 0x1 + + + GPIO_B0_15_ALT8 + Selecting Pad: GPIO_B0_15 for Mode: ALT8 + 0x2 + + + + + + + FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT + FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT DAISY Register + 0x72C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SPI_B1_00_ALT0 + Selecting Pad: GPIO_SPI_B1_00 for Mode: ALT0 + 0 + + + GPIO_EMC_23_ALT8 + Selecting Pad: GPIO_EMC_23 for Mode: ALT8 + 0x1 + + + GPIO_SPI_B0_09_ALT0 + Selecting Pad: GPIO_SPI_B0_09 for Mode: ALT0 + 0x2 + + + + + + + FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT + FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT DAISY Register + 0x730 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SPI_B1_04_ALT0 + Selecting Pad: GPIO_SPI_B1_04 for Mode: ALT0 + 0 + + + GPIO_EMC_26_ALT8 + Selecting Pad: GPIO_EMC_26 for Mode: ALT8 + 0x1 + + + GPIO_SPI_B0_02_ALT0 + Selecting Pad: GPIO_SPI_B0_02 for Mode: ALT0 + 0x2 + + + + + + + FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT + FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT DAISY Register + 0x734 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SPI_B1_03_ALT0 + Selecting Pad: GPIO_SPI_B1_03 for Mode: ALT0 + 0 + + + GPIO_EMC_27_ALT8 + Selecting Pad: GPIO_EMC_27 for Mode: ALT8 + 0x1 + + + GPIO_SPI_B0_12_ALT0 + Selecting Pad: GPIO_SPI_B0_12 for Mode: ALT0 + 0x2 + + + + + + + FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT + FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT DAISY Register + 0x738 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SPI_B1_02_ALT0 + Selecting Pad: GPIO_SPI_B1_02 for Mode: ALT0 + 0 + + + GPIO_EMC_28_ALT8 + Selecting Pad: GPIO_EMC_28 for Mode: ALT8 + 0x1 + + + GPIO_SPI_B0_06_ALT0 + Selecting Pad: GPIO_SPI_B0_06 for Mode: ALT0 + 0x2 + + + + + + + FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT + FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT DAISY Register + 0x73C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SPI_B1_01_ALT0 + Selecting Pad: GPIO_SPI_B1_01 for Mode: ALT0 + 0 + + + GPIO_EMC_29_ALT8 + Selecting Pad: GPIO_EMC_29 for Mode: ALT8 + 0x1 + + + GPIO_SPI_B0_10_ALT0 + Selecting Pad: GPIO_SPI_B0_10 for Mode: ALT0 + 0x2 + + + + + + + FLEXSPI2_IPP_IND_IO_FB_BIT0_SELECT_INPUT + FLEXSPI2_IPP_IND_IO_FB_BIT0_SELECT_INPUT DAISY Register + 0x740 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_13_ALT8 + Selecting Pad: GPIO_EMC_13 for Mode: ALT8 + 0 + + + GPIO_SPI_B0_11_ALT0 + Selecting Pad: GPIO_SPI_B0_11 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPI2_IPP_IND_IO_FB_BIT1_SELECT_INPUT + FLEXSPI2_IPP_IND_IO_FB_BIT1_SELECT_INPUT DAISY Register + 0x744 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_14_ALT8 + Selecting Pad: GPIO_EMC_14 for Mode: ALT8 + 0 + + + GPIO_SPI_B0_07_ALT0 + Selecting Pad: GPIO_SPI_B0_07 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPI2_IPP_IND_IO_FB_BIT2_SELECT_INPUT + FLEXSPI2_IPP_IND_IO_FB_BIT2_SELECT_INPUT DAISY Register + 0x748 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_15_ALT8 + Selecting Pad: GPIO_EMC_15 for Mode: ALT8 + 0 + + + GPIO_SPI_B0_03_ALT0 + Selecting Pad: GPIO_SPI_B0_03 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPI2_IPP_IND_IO_FB_BIT3_SELECT_INPUT + FLEXSPI2_IPP_IND_IO_FB_BIT3_SELECT_INPUT DAISY Register + 0x74C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_16_ALT8 + Selecting Pad: GPIO_EMC_16 for Mode: ALT8 + 0 + + + GPIO_SPI_B0_04_ALT0 + Selecting Pad: GPIO_SPI_B0_04 for Mode: ALT0 + 0x1 + + + + + + + FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT + FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT DAISY Register + 0x750 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SPI_B1_05_ALT0 + Selecting Pad: GPIO_SPI_B1_05 for Mode: ALT0 + 0 + + + GPIO_EMC_25_ALT8 + Selecting Pad: GPIO_EMC_25 for Mode: ALT8 + 0x1 + + + GPIO_SPI_B0_08_ALT0 + Selecting Pad: GPIO_SPI_B0_08 for Mode: ALT0 + 0x2 + + + + + + + FLEXSPI2_IPP_IND_SCK_FB_SELECT_INPUT + FLEXSPI2_IPP_IND_SCK_FB_SELECT_INPUT DAISY Register + 0x754 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_12_ALT8 + Selecting Pad: GPIO_EMC_12 for Mode: ALT8 + 0 + + + GPIO_SPI_B0_01_ALT0 + Selecting Pad: GPIO_SPI_B0_01 for Mode: ALT0 + 0x1 + + + + + + + GPT1_IPP_IND_CAPIN1_SELECT_INPUT + GPT1_IPP_IND_CAPIN1_SELECT_INPUT DAISY Register + 0x758 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_24_ALT4 + Selecting Pad: GPIO_EMC_24 for Mode: ALT4 + 0 + + + GPIO_B1_05_ALT8 + Selecting Pad: GPIO_B1_05 for Mode: ALT8 + 0x1 + + + + + + + GPT1_IPP_IND_CAPIN2_SELECT_INPUT + GPT1_IPP_IND_CAPIN2_SELECT_INPUT DAISY Register + 0x75C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_23_ALT4 + Selecting Pad: GPIO_EMC_23 for Mode: ALT4 + 0 + + + GPIO_B1_06_ALT8 + Selecting Pad: GPIO_B1_06 for Mode: ALT8 + 0x1 + + + + + + + GPT1_IPP_IND_CLKIN_SELECT_INPUT + GPT1_IPP_IND_CLKIN_SELECT_INPUT DAISY Register + 0x760 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_13_ALT1 + Selecting Pad: GPIO_AD_B0_13 for Mode: ALT1 + 0 + + + GPIO_B1_04_ALT8 + Selecting Pad: GPIO_B1_04 for Mode: ALT8 + 0x1 + + + + + + + GPT2_IPP_IND_CAPIN1_SELECT_INPUT + GPT2_IPP_IND_CAPIN1_SELECT_INPUT DAISY Register + 0x764 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_41_ALT1 + Selecting Pad: GPIO_EMC_41 for Mode: ALT1 + 0 + + + GPIO_AD_B1_03_ALT8 + Selecting Pad: GPIO_AD_B1_03 for Mode: ALT8 + 0x1 + + + + + + + GPT2_IPP_IND_CAPIN2_SELECT_INPUT + GPT2_IPP_IND_CAPIN2_SELECT_INPUT DAISY Register + 0x768 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_40_ALT1 + Selecting Pad: GPIO_EMC_40 for Mode: ALT1 + 0 + + + GPIO_AD_B1_04_ALT8 + Selecting Pad: GPIO_AD_B1_04 for Mode: ALT8 + 0x1 + + + + + + + GPT2_IPP_IND_CLKIN_SELECT_INPUT + GPT2_IPP_IND_CLKIN_SELECT_INPUT DAISY Register + 0x76C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_AD_B0_09_ALT7 + Selecting Pad: GPIO_AD_B0_09 for Mode: ALT7 + 0 + + + GPIO_AD_B1_02_ALT8 + Selecting Pad: GPIO_AD_B1_02 for Mode: ALT8 + 0x1 + + + + + + + SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 + SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 DAISY Register + 0x770 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_37_ALT3 + Selecting Pad: GPIO_EMC_37 for Mode: ALT3 + 0 + + + GPIO_SD_B1_04_ALT8 + Selecting Pad: GPIO_SD_B1_04 for Mode: ALT8 + 0x1 + + + + + + + SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT + SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT DAISY Register + 0x774 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_35_ALT3 + Selecting Pad: GPIO_EMC_35 for Mode: ALT3 + 0 + + + GPIO_SD_B1_06_ALT8 + Selecting Pad: GPIO_SD_B1_06 for Mode: ALT8 + 0x1 + + + + + + + SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 + SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 DAISY Register + 0x778 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_33_ALT3 + Selecting Pad: GPIO_EMC_33 for Mode: ALT3 + 0 + + + GPIO_SD_B1_00_ALT8 + Selecting Pad: GPIO_SD_B1_00 for Mode: ALT8 + 0x1 + + + + + + + SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT + SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT DAISY Register + 0x77C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_34_ALT3 + Selecting Pad: GPIO_EMC_34 for Mode: ALT3 + 0 + + + GPIO_SD_B1_05_ALT8 + Selecting Pad: GPIO_SD_B1_05 for Mode: ALT8 + 0x1 + + + + + + + SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT + SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT DAISY Register + 0x780 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_38_ALT3 + Selecting Pad: GPIO_EMC_38 for Mode: ALT3 + 0 + + + GPIO_SD_B1_03_ALT8 + Selecting Pad: GPIO_SD_B1_03 for Mode: ALT8 + 0x1 + + + + + + + SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT + SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register + 0x784 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 1 + read-write + + + GPIO_EMC_39_ALT3 + Selecting Pad: GPIO_EMC_39 for Mode: ALT3 + 0 + + + GPIO_SD_B1_02_ALT8 + Selecting Pad: GPIO_SD_B1_02 for Mode: ALT8 + 0x1 + + + + + + + SEMC_I_IPP_IND_DQS4_SELECT_INPUT + SEMC_I_IPP_IND_DQS4_SELECT_INPUT DAISY Register + 0x788 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_SD_B0_00_ALT9 + Selecting Pad: GPIO_SD_B0_00 for Mode: ALT9 + 0 + + + GPIO_EMC_39_ALT9 + Selecting Pad: GPIO_EMC_39 for Mode: ALT9 + 0x1 + + + GPIO_AD_B0_09_ALT9 + Selecting Pad: GPIO_AD_B0_09 for Mode: ALT9 + 0x2 + + + GPIO_B1_13_ALT8 + Selecting Pad: GPIO_B1_13 for Mode: ALT8 + 0x3 + + + + + + + CANFD_IPP_IND_CANRX_SELECT_INPUT + CANFD_IPP_IND_CANRX_SELECT_INPUT DAISY Register + 0x78C + 32 + read-write + 0 + 0xFFFFFFFF + + + DAISY + Selecting Pads Involved in Daisy Chain. + 0 + 2 + read-write + + + GPIO_EMC_37_ALT9 + Selecting Pad: GPIO_EMC_37 for Mode: ALT9 + 0 + + + GPIO_AD_B0_15_ALT8 + Selecting Pad: GPIO_AD_B0_15 for Mode: ALT8 + 0x1 + + + GPIO_AD_B0_11_ALT8 + Selecting Pad: GPIO_AD_B0_11 for Mode: ALT8 + 0x2 + + + + + + + + + KPP + KPP Registers + KPP + KPP_ + 0x401FC000 + + 0 + 0x8 + registers + + + KPP + 39 + + + + KPCR + Keypad Control Register + 0 + 16 + read-write + 0 + 0xFFFF + + + KRE + Keypad Row Enable + 0 + 8 + read-write + + + KRE_0 + Row is not included in the keypad key press detect. + 0 + + + KRE_1 + Row is included in the keypad key press detect. + 0x1 + + + + + KCO + Keypad Column Strobe Open-Drain Enable + 8 + 8 + read-write + + + TOTEM_POLE + Column strobe output is totem pole drive. + 0 + + + OPEN_DRAIN + Column strobe output is open drain. + 0x1 + + + + + + + KPSR + Keypad Status Register + 0x2 + 16 + read-write + 0x400 + 0xFFFF + + + KPKD + Keypad Key Depress + 0 + 1 + read-write + oneToClear + + + KPKD_0 + No key presses detected + 0 + + + KPKD_1 + A key has been depressed + 0x1 + + + + + KPKR + Keypad Key Release + 1 + 1 + read-write + oneToClear + + + KPKR_0 + No key release detected + 0 + + + KPKR_1 + All keys have been released + 0x1 + + + + + KDSC + Key Depress Synchronizer Clear + 2 + 1 + read-write + + + KDSC_0 + No effect + 0 + + + KDSC_1 + Set bits that clear the keypad depress synchronizer chain + 0x1 + + + + + KRSS + Key Release Synchronizer Set + 3 + 1 + read-write + + + KRSS_0 + No effect + 0 + + + KRSS_1 + Set bits which sets keypad release synchronizer chain + 0x1 + + + + + KDIE + Keypad Key Depress Interrupt Enable + 8 + 1 + read-write + + + KDIE_0 + No interrupt request is generated when KPKD is set. + 0 + + + KDIE_1 + An interrupt request is generated when KPKD is set. + 0x1 + + + + + KRIE + Keypad Release Interrupt Enable + 9 + 1 + read-write + + + KRIE_0 + No interrupt request is generated when KPKR is set. + 0 + + + KRIE_1 + An interrupt request is generated when KPKR is set. + 0x1 + + + + + + + KDDR + Keypad Data Direction Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + KRDD + Keypad Row Data Direction + 0 + 8 + read-write + + + INPUT + ROWn pin configured as an input. + 0 + + + OUTPUT + ROWn pin configured as an output. + 0x1 + + + + + KCDD + Keypad Column Data Direction Register + 8 + 8 + read-write + + + INPUT + COLn pin is configured as an input. + 0 + + + OUTPUT + COLn pin is configured as an output. + 0x1 + + + + + + + KPDR + Keypad Data Register + 0x6 + 16 + read-write + 0 + 0xFFFF + + + KRD + Keypad Row Data + 0 + 8 + read-write + + + KCD + Keypad Column Data + 8 + 8 + read-write + + + + + + + FLEXSPI + FlexSPI + FlexSPI + FlexSPI + 0x402A8000 + + 0 + 0x400 + registers + + + FLEXSPI + 108 + + + + MCR0 + Module Control Register 0 + 0 + 32 + read-write + 0xFFFF80C2 + 0xFFFFFFFF + + + SWRESET + Software Reset + 0 + 1 + read-write + + + MDIS + Module Disable + 1 + 1 + read-write + + + RXCLKSRC + Sample Clock source selection for Flash Reading + 4 + 2 + read-write + + + RXCLKSRC_0 + Dummy Read strobe generated by FlexSPI Controller and loopback internally. + 0 + + + RXCLKSRC_1 + Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. + 0x1 + + + RXCLKSRC_3 + Flash provided Read strobe and input from DQS pad + 0x3 + + + + + ARDFEN + Enable AHB bus Read Access to IP RX FIFO. + 6 + 1 + read-write + + + ARDFEN_0 + IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. + 0 + + + ARDFEN_1 + IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response. + 0x1 + + + + + ATDFEN + Enable AHB bus Write Access to IP TX FIFO. + 7 + 1 + read-write + + + ATDFEN_0 + IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. + 0 + + + ATDFEN_1 + IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response. + 0x1 + + + + + HSEN + Half Speed Serial Flash access Enable. + 11 + 1 + read-write + + + HSEN_0 + Disable divide by 2 of serial flash clock for half speed commands. + 0 + + + HSEN_1 + Enable divide by 2 of serial flash clock for half speed commands. + 0x1 + + + + + DOZEEN + Doze mode enable bit + 12 + 1 + read-write + + + DOZEEN_0 + Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. + 0 + + + DOZEEN_1 + Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system. + 0x1 + + + + + COMBINATIONEN + This bit is to support Flash Octal mode access by combining Port A and B Data pins (SIOA[3:0] and SIOB[3:0]). + 13 + 1 + read-write + + + COMBINATIONEN_0 + Disable. + 0 + + + COMBINATIONEN_1 + Enable. + 0x1 + + + + + SCKFREERUNEN + This bit is used to force SCK output free-running. For FPGA applications, external device may use SCK clock as reference clock to its internal PLL. If SCK free-running is enabled, data sampling with loopback clock from SCK pad is not supported (MCR0[RXCLKSRC]=2). + 14 + 1 + read-write + + + SCKFREERUNEN_0 + Disable. + 0 + + + SCKFREERUNEN_1 + Enable. + 0x1 + + + + + IPGRANTWAIT + Time out wait cycle for IP command grant. + 16 + 8 + read-write + + + AHBGRANTWAIT + Timeout wait cycle for AHB command grant. + 24 + 8 + read-write + + + + + MCR1 + Module Control Register 1 + 0x4 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + AHBBUSWAIT + AHB Read/Write access to Serial Flash Memory space will timeout if not data received from Flash or data not transmited after AHBBUSWAIT * 1024 ahb clock cycles, AHB Bus will get an error response + 0 + 16 + read-write + + + SEQWAIT + Command Sequence Execution will timeout and abort after SEQWAIT * 1024 Serial Root Clock cycles + 16 + 16 + read-write + + + + + MCR2 + Module Control Register 2 + 0x8 + 32 + read-write + 0x200081F7 + 0xFFFFFFFF + + + CLRAHBBUFOPT + This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automaticaly when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. + 11 + 1 + read-write + + + CLRAHBBUFOPT_0 + AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. + 0 + + + CLRAHBBUFOPT_1 + AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. + 0x1 + + + + + CLRLEARNPHASE + The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately. + 14 + 1 + read-write + + + SAMEDEVICEEN + All external devices are same devices (both in types and size) for A1/A2/B1/B2. + 15 + 1 + read-write + + + SAMEDEVICEEN_0 + In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 seperately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored. + 0 + + + SAMEDEVICEEN_1 + FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. + 0x1 + + + + + SCKBDIFFOPT + SCKB pad can be used as SCKA differential clock output (inverted clock to SCKA). In this case, port B flash access is not available. After change the value of this feild, MCR0[SWRESET] should be set. + 19 + 1 + read-write + + + SCKBDIFFOPT_0 + SCKB pad is used as port B SCK clock output. Port B flash access is available. + 0 + + + SCKBDIFFOPT_1 + SCKB pad is used as port A SCK inverted clock output (Differential clock to SCKA). Port B flash access is not available. + 0x1 + + + + + RESUMEWAIT + Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed. + 24 + 8 + read-write + + + + + AHBCR + AHB Bus Control Register + 0xC + 32 + read-write + 0x18 + 0xFFFFFFFF + + + APAREN + Parallel mode enabled for AHB triggered Command (both read and write) . + 0 + 1 + read-write + + + APAREN_0 + Flash will be accessed in Individual mode. + 0 + + + APAREN_1 + Flash will be accessed in Parallel mode. + 0x1 + + + + + CACHABLEEN + Enable AHB bus cachable read access support. + 3 + 1 + read-write + + + CACHABLEEN_0 + Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. + 0 + + + CACHABLEEN_1 + Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. + 0x1 + + + + + BUFFERABLEEN + Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write. + 4 + 1 + read-write + + + BUFFERABLEEN_0 + Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished. + 0 + + + BUFFERABLEEN_1 + Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished. + 0x1 + + + + + PREFETCHEN + AHB Read Prefetch Enable. + 5 + 1 + read-write + + + READADDROPT + AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. + 6 + 1 + read-write + + + READADDROPT_0 + There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable. + 0 + + + READADDROPT_1 + There is no AHB read burst start address alignment limitation. FlexSPI will fetch more datas than AHB burst required to meet the alignment requirement. + 0x1 + + + + + + + INTEN + Interrupt Enable Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + IPCMDDONEEN + IP triggered Command Sequences Execution finished interrupt enable. + 0 + 1 + read-write + + + IPCMDGEEN + IP triggered Command Sequences Grant Timeout interrupt enable. + 1 + 1 + read-write + + + AHBCMDGEEN + AHB triggered Command Sequences Grant Timeout interrupt enable. + 2 + 1 + read-write + + + IPCMDERREN + IP triggered Command Sequences Error Detected interrupt enable. + 3 + 1 + read-write + + + AHBCMDERREN + AHB triggered Command Sequences Error Detected interrupt enable. + 4 + 1 + read-write + + + IPRXWAEN + IP RX FIFO WaterMark available interrupt enable. + 5 + 1 + read-write + + + IPTXWEEN + IP TX FIFO WaterMark empty interrupt enable. + 6 + 1 + read-write + + + SCKSTOPBYRDEN + SCK is stopped during command sequence because Async RX FIFO full interrupt enable. + 8 + 1 + read-write + + + SCKSTOPBYWREN + SCK is stopped during command sequence because Async TX FIFO empty interrupt enable. + 9 + 1 + read-write + + + AHBBUSTIMEOUTEN + AHB Bus timeout interrupt.Refer Interrupts chapter for more details. + 10 + 1 + read-write + + + SEQTIMEOUTEN + Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details. + 11 + 1 + read-write + + + + + INTR + Interrupt Register + 0x14 + 32 + read-write + 0x40 + 0xFFFFFFFF + + + IPCMDDONE + IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated. + 0 + 1 + read-write + oneToClear + + + IPCMDGE + IP triggered Command Sequences Grant Timeout interrupt. + 1 + 1 + read-write + oneToClear + + + AHBCMDGE + AHB triggered Command Sequences Grant Timeout interrupt. + 2 + 1 + read-write + oneToClear + + + IPCMDERR + IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all. + 3 + 1 + read-write + oneToClear + + + AHBCMDERR + AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all. + 4 + 1 + read-write + oneToClear + + + IPRXWA + IP RX FIFO watermark available interrupt. + 5 + 1 + read-write + oneToClear + + + IPTXWE + IP TX FIFO watermark empty interrupt. + 6 + 1 + read-write + oneToClear + + + SCKSTOPBYRD + SCK is stopped during command sequence because Async RX FIFO full interrupt. + 8 + 1 + read-write + oneToClear + + + SCKSTOPBYWR + SCK is stopped during command sequence because Async TX FIFO empty interrupt. + 9 + 1 + read-write + oneToClear + + + AHBBUSTIMEOUT + AHB Bus timeout interrupt.Refer Interrupts chapter for more details. + 10 + 1 + read-write + oneToClear + + + SEQTIMEOUT + Sequence execution timeout interrupt. + 11 + 1 + read-write + oneToClear + + + + + LUTKEY + LUT Key Register + 0x18 + 32 + read-write + 0x5AF05AF0 + 0xFFFFFFFF + + + KEY + The Key to lock or unlock LUT. + 0 + 32 + read-write + + + + + LUTCR + LUT Control Register + 0x1C + 32 + read-write + 0x2 + 0xFFFFFFFF + + + LOCK + Lock LUT + 0 + 1 + read-write + + + UNLOCK + Unlock LUT + 1 + 1 + read-write + + + + + AHBRXBUF0CR0 + AHB RX Buffer 0 Control Register 0 + 0x20 + 32 + read-write + 0x80000020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation. + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + AHBRXBUF1CR0 + AHB RX Buffer 1 Control Register 0 + 0x24 + 32 + read-write + 0x80010020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation. + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + AHBRXBUF2CR0 + AHB RX Buffer 2 Control Register 0 + 0x28 + 32 + read-write + 0x80020020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation. + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + AHBRXBUF3CR0 + AHB RX Buffer 3 Control Register 0 + 0x2C + 32 + read-write + 0x80030020 + 0xFFFFFFFF + + + BUFSZ + AHB RX Buffer Size in 64 bits.Refer AHB RX Buffer Management for more details. + 0 + 8 + read-write + + + MSTRID + This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). Please refer to for AHB RX Buffer allocation. + 16 + 4 + read-write + + + PRIORITY + This priority for AHB Master Read which this AHB RX Buffer is assigned. Refer for more details. + 24 + 2 + read-write + + + PREFETCHEN + AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. + 31 + 1 + read-write + + + + + FLSHA1CR0 + Flash A1 Control Register 0 + 0x60 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + FLSHA2CR0 + Flash A2 Control Register 0 + 0x64 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + FLSHB1CR0 + Flash B1 Control Register 0 + 0x68 + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + FLSHB2CR0 + Flash B2 Control Register 0 + 0x6C + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + FLSHSZ + Flash Size in KByte. + 0 + 23 + read-write + + + + + 4 + 0x4 + A1,A2,B1,B2 + FLSHCR1%s + Flash A1 Control Register 1 + 0x70 + 32 + read-write + 0x63 + 0xFFFFFFFF + + + TCSS + Serial Flash CS setup time. + 0 + 5 + read-write + + + TCSH + Serial Flash CS Hold time. + 5 + 5 + read-write + + + WA + Word Addressable. + 10 + 1 + read-write + + + CAS + Column Address Size. + 11 + 4 + read-write + + + CSINTERVALUNIT + CS interval unit + 15 + 1 + read-write + + + CSINTERVALUNIT_0 + The CS interval unit is 1 serial clock cycle + 0 + + + CSINTERVALUNIT_1 + The CS interval unit is 256 serial clock cycle + 0x1 + + + + + CSINTERVAL + This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0. + 16 + 16 + read-write + + + + + 4 + 0x4 + A1,A2,B1,B2 + FLSHCR2%s + Flash A1 Control Register 2 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + ARDSEQID + Sequence Index for AHB Read triggered Command in LUT. + 0 + 4 + read-write + + + ARDSEQNUM + Sequence Number for AHB Read triggered Command in LUT. + 5 + 3 + read-write + + + AWRSEQID + Sequence Index for AHB Write triggered Command. + 8 + 4 + read-write + + + AWRSEQNUM + Sequence Number for AHB Write triggered Command. + 13 + 3 + read-write + + + AWRWAIT + For certain devices (such as FPGA), it need some time to write data into internal memory after the command sequences finished on FlexSPI interface + 16 + 12 + read-write + + + AWRWAITUNIT + AWRWAIT unit + 28 + 3 + read-write + + + AWRWAITUNIT_0 + The AWRWAIT unit is 2 ahb clock cycle + 0 + + + AWRWAITUNIT_1 + The AWRWAIT unit is 8 ahb clock cycle + 0x1 + + + AWRWAITUNIT_2 + The AWRWAIT unit is 32 ahb clock cycle + 0x2 + + + AWRWAITUNIT_3 + The AWRWAIT unit is 128 ahb clock cycle + 0x3 + + + AWRWAITUNIT_4 + The AWRWAIT unit is 512 ahb clock cycle + 0x4 + + + AWRWAITUNIT_5 + The AWRWAIT unit is 2048 ahb clock cycle + 0x5 + + + AWRWAITUNIT_6 + The AWRWAIT unit is 8192 ahb clock cycle + 0x6 + + + AWRWAITUNIT_7 + The AWRWAIT unit is 32768 ahb clock cycle + 0x7 + + + + + CLRINSTRPTR + Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details. + 31 + 1 + read-write + + + + + FLSHCR4 + Flash Control Register 4 + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + WMOPT1 + Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. + 0 + 1 + read-write + + + WMOPT1_0 + DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode. + 0 + + + WMOPT1_1 + DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode. + 0x1 + + + + + WMENA + Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set. + 2 + 1 + read-write + + + WMENA_0 + Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + 0 + + + WMENA_1 + Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + 0x1 + + + + + WMENB + Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set. + 3 + 1 + read-write + + + WMENB_0 + Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. + 0 + + + WMENB_1 + Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. + 0x1 + + + + + + + IPCR0 + IP Control Register 0 + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SFAR + Serial Flash Address for IP command. + 0 + 32 + read-write + + + + + IPCR1 + IP Control Register 1 + 0xA4 + 32 + read-write + 0 + 0xFFFFFFFF + + + IDATSZ + Flash Read/Program Data Size (in Bytes) for IP command. + 0 + 16 + read-write + + + ISEQID + Sequence Index in LUT for IP command. + 16 + 4 + read-write + + + ISEQNUM + Sequence Number for IP command: ISEQNUM+1. + 24 + 3 + read-write + + + IPAREN + Parallel mode Enabled for IP command. + 31 + 1 + read-write + + + IPAREN_0 + Flash will be accessed in Individual mode. + 0 + + + IPAREN_1 + Flash will be accessed in Parallel mode. + 0x1 + + + + + + + IPCMD + IP Command Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRG + Setting this bit will trigger an IP Command. + 0 + 1 + read-write + + + + + IPRXFCR + IP RX FIFO Control Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRIPRXF + Clear all valid data entries in IP RX FIFO. + 0 + 1 + read-write + + + RXDMAEN + IP RX FIFO reading by DMA enabled. + 1 + 1 + read-write + + + RXDMAEN_0 + IP RX FIFO would be read by processor. + 0 + + + RXDMAEN_1 + IP RX FIFO would be read by DMA. + 0x1 + + + + + RXWMRK + Watermark level is (RXWMRK+1)*64 Bits. + 2 + 4 + read-write + + + + + IPTXFCR + IP TX FIFO Control Register + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRIPTXF + Clear all valid data entries in IP TX FIFO. + 0 + 1 + read-write + + + TXDMAEN + IP TX FIFO filling by DMA enabled. + 1 + 1 + read-write + + + TXDMAEN_0 + IP TX FIFO would be filled by processor. + 0 + + + TXDMAEN_1 + IP TX FIFO would be filled by DMA. + 0x1 + + + + + TXWMRK + Watermark level is (TXWMRK+1)*64 Bits. + 2 + 4 + read-write + + + + + 2 + 0x4 + A,B + DLLCR%s + DLL Control Register 0 + 0xC0 + 32 + read-write + 0x100 + 0xFFFFFFFF + + + DLLEN + DLL calibration enable. + 0 + 1 + read-write + + + DLLRESET + Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation). + 1 + 1 + read-write + + + SLVDLYTARGET + The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial clock). + 3 + 4 + read-write + + + OVRDEN + Slave clock delay line delay cell number selection override enable. + 8 + 1 + read-write + + + OVRDVAL + Slave clock delay line delay cell number selection override value. + 9 + 6 + read-write + + + + + STS0 + Status Register 0 + 0xE0 + 32 + read-only + 0x3 + 0xFFFFFFFF + + + SEQIDLE + This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface. + 0 + 1 + read-only + + + ARBIDLE + This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE. + 1 + 1 + read-only + + + ARBCMDSRC + This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). + 2 + 2 + read-only + + + ARBCMDSRC_0 + Triggered by AHB read command (triggered by AHB read). + 0 + + + ARBCMDSRC_1 + Triggered by AHB write command (triggered by AHB Write). + 0x1 + + + ARBCMDSRC_2 + Triggered by IP command (triggered by setting register bit IPCMD.TRG). + 0x2 + + + ARBCMDSRC_3 + Triggered by suspended command (resumed). + 0x3 + + + + + + + STS1 + Status Register 1 + 0xE4 + 32 + read-only + 0 + 0xFFFFFFFF + + + AHBCMDERRID + Indicates the sequence index when an AHB command error is detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). + 0 + 4 + read-only + + + AHBCMDERRCODE + Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). + 8 + 4 + read-only + + + AHBCMDERRCODE_0 + No error. + 0 + + + AHBCMDERRCODE_2 + AHB Write command with JMP_ON_CS instruction used in the sequence. + 0x2 + + + AHBCMDERRCODE_3 + There is unknown instruction opcode in the sequence. + 0x3 + + + AHBCMDERRCODE_4 + Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + 0x4 + + + AHBCMDERRCODE_5 + Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + 0x5 + + + AHBCMDERRCODE_14 + Sequence execution timeout. + 0xE + + + + + IPCMDERRID + Indicates the sequence Index when IP command error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c). + 16 + 4 + read-only + + + IPCMDERRCODE + Indicates the Error Code when IP command Error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c). + 24 + 4 + read-only + + + IPCMDERRCODE_0 + No error. + 0 + + + IPCMDERRCODE_2 + IP command with JMP_ON_CS instruction used in the sequence. + 0x2 + + + IPCMDERRCODE_3 + There is unknown instruction opcode in the sequence. + 0x3 + + + IPCMDERRCODE_4 + Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. + 0x4 + + + IPCMDERRCODE_5 + Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. + 0x5 + + + IPCMDERRCODE_6 + Flash access start address exceed the whole flash address range (A1/A2/B1/B2). + 0x6 + + + IPCMDERRCODE_14 + Sequence execution timeout. + 0xE + + + IPCMDERRCODE_15 + Flash boundary crossed. + 0xF + + + + + + + STS2 + Status Register 2 + 0xE8 + 32 + read-only + 0x1000100 + 0xFFFFFFFF + + + ASLVLOCK + Flash A sample clock slave delay line locked. + 0 + 1 + read-only + + + AREFLOCK + Flash A sample clock reference delay line locked. + 1 + 1 + read-only + + + ASLVSEL + Flash A sample clock slave delay line delay cell number selection . + 2 + 6 + read-only + + + AREFSEL + Flash A sample clock reference delay line delay cell number selection. + 8 + 6 + read-only + + + BSLVLOCK + Flash B sample clock slave delay line locked. + 16 + 1 + read-only + + + BREFLOCK + Flash B sample clock reference delay line locked. + 17 + 1 + read-only + + + BSLVSEL + Flash B sample clock slave delay line delay cell number selection. + 18 + 6 + read-only + + + BREFSEL + Flash B sample clock reference delay line delay cell number selection. + 24 + 6 + read-only + + + + + AHBSPNDSTS + AHB Suspend Status Register + 0xEC + 32 + read-only + 0 + 0xFFFFFFFF + + + ACTIVE + Indicates if an AHB read prefetch command sequence has been suspended. + 0 + 1 + read-only + + + BUFID + AHB RX BUF ID for suspended command sequence. + 1 + 3 + read-only + + + DATLFT + Left Data size for suspended command sequence (in byte). + 16 + 16 + read-only + + + + + IPRXFSTS + IP RX FIFO Status Register + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + FILL + Fill level of IP RX FIFO. + 0 + 8 + read-only + + + RDCNTR + Total Read Data Counter: RDCNTR * 64 Bits. + 16 + 16 + read-only + + + + + IPTXFSTS + IP TX FIFO Status Register + 0xF4 + 32 + read-only + 0 + 0xFFFFFFFF + + + FILL + Fill level of IP TX FIFO. + 0 + 8 + read-only + + + WRCNTR + Total Write Data Counter: WRCNTR * 64 Bits. + 16 + 16 + read-only + + + + + 32 + 0x4 + RFDR[%s] + IP RX FIFO Data Register 0 + 0x100 + 32 + read-only + 0 + 0xFFFFFFFF + + + RXDATA + RX Data + 0 + 32 + read-only + + + + + 32 + 0x4 + TFDR[%s] + IP TX FIFO Data Register 0 + 0x180 + 32 + write-only + 0 + 0xFFFFFFFF + + + TXDATA + TX Data + 0 + 32 + write-only + + + + + 64 + 0x4 + LUT[%s] + LUT 0 + 0x200 + 32 + read-write + 0 + 0 + + + OPERAND0 + OPERAND0 + 0 + 8 + read-write + + + NUM_PADS0 + NUM_PADS0 + 8 + 2 + read-write + + + OPCODE0 + OPCODE + 10 + 6 + read-write + + + OPERAND1 + OPERAND1 + 16 + 8 + read-write + + + NUM_PADS1 + NUM_PADS1 + 24 + 2 + read-write + + + OPCODE1 + OPCODE1 + 26 + 6 + read-write + + + + + + + FLEXSPI2 + FlexSPI + FlexSPI + 0x402A4000 + + 0 + 0x400 + registers + + + FLEXSPI2 + 107 + + + + USDHC1 + uSDHC + USDHC + USDHC + 0x402C0000 + + 0 + 0xD0 + registers + + + USDHC1 + 110 + + + + DS_ADDR + DMA System Address + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DS_ADDR + DS_ADDR + 0 + 32 + read-write + + + + + BLK_ATT + Block Attributes + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + BLKSIZE + Block Size + 0 + 13 + read-write + + + BLKSIZE_0 + No data transfer + 0 + + + BLKSIZE_1 + 1 Byte + 0x1 + + + BLKSIZE_2 + 2 Bytes + 0x2 + + + BLKSIZE_3 + 3 Bytes + 0x3 + + + BLKSIZE_4 + 4 Bytes + 0x4 + + + BLKSIZE_511 + 511 Bytes + 0x1FF + + + BLKSIZE_512 + 512 Bytes + 0x200 + + + BLKSIZE_2048 + 2048 Bytes + 0x800 + + + BLKSIZE_4096 + 4096 Bytes + 0x1000 + + + + + BLKCNT + Block Count + 16 + 16 + read-write + + + BLKCNT_0 + Stop Count + 0 + + + BLKCNT_1 + 1 block + 0x1 + + + BLKCNT_2 + 2 blocks + 0x2 + + + BLKCNT_65535 + 65535 blocks + 0xFFFF + + + + + + + CMD_ARG + Command Argument + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CMDARG + Command Argument + 0 + 32 + read-write + + + + + CMD_XFR_TYP + Command Transfer Type + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RSPTYP + Response Type Select + 16 + 2 + read-write + + + RSPTYP_0 + No Response + 0 + + + RSPTYP_1 + Response Length 136 + 0x1 + + + RSPTYP_2 + Response Length 48 + 0x2 + + + RSPTYP_3 + Response Length 48, check Busy after response + 0x3 + + + + + CCCEN + Command CRC Check Enable + 19 + 1 + read-write + + + CCCEN_0 + Disable + 0 + + + CCCEN_1 + Enable + 0x1 + + + + + CICEN + Command Index Check Enable + 20 + 1 + read-write + + + CICEN_0 + Disable + 0 + + + CICEN_1 + Enable + 0x1 + + + + + DPSEL + Data Present Select + 21 + 1 + read-write + + + DPSEL_0 + No Data Present + 0 + + + DPSEL_1 + Data Present + 0x1 + + + + + CMDTYP + Command Type + 22 + 2 + read-write + + + CMDTYP_0 + Normal Other commands + 0 + + + CMDTYP_1 + Suspend CMD52 for writing Bus Suspend in CCCR + 0x1 + + + CMDTYP_2 + Resume CMD52 for writing Function Select in CCCR + 0x2 + + + CMDTYP_3 + Abort CMD12, CMD52 for writing I/O Abort in CCCR + 0x3 + + + + + CMDINX + Command Index + 24 + 6 + read-write + + + + + CMD_RSP0 + Command Response0 + 0x10 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP0 + Command Response 0 + 0 + 32 + read-only + + + + + CMD_RSP1 + Command Response1 + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP1 + Command Response 1 + 0 + 32 + read-only + + + + + CMD_RSP2 + Command Response2 + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP2 + Command Response 2 + 0 + 32 + read-only + + + + + CMD_RSP3 + Command Response3 + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + CMDRSP3 + Command Response 3 + 0 + 32 + read-only + + + + + DATA_BUFF_ACC_PORT + Data Buffer Access Port + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATCONT + Data Content + 0 + 32 + read-write + + + + + PRES_STATE + Present State + 0x24 + 32 + read-only + 0x8080 + 0x72FFFF + + + CIHB + Command Inhibit (CMD) + 0 + 1 + read-only + + + CIHB_0 + Can issue command using only CMD line + 0 + + + CIHB_1 + Cannot issue command + 0x1 + + + + + CDIHB + Command Inhibit (DATA) + 1 + 1 + read-only + + + CDIHB_0 + Can issue command which uses the DATA line + 0 + + + CDIHB_1 + Cannot issue command which uses the DATA line + 0x1 + + + + + DLA + Data Line Active + 2 + 1 + read-only + + + DLA_0 + DATA Line Inactive + 0 + + + DLA_1 + DATA Line Active + 0x1 + + + + + SDSTB + SD Clock Stable + 3 + 1 + read-only + + + SDSTB_0 + Clock is changing frequency and not stable. + 0 + + + SDSTB_1 + Clock is stable. + 0x1 + + + + + IPGOFF + IPG_CLK Gated Off Internally + 4 + 1 + read-only + + + IPGOFF_0 + IPG_CLK is active. + 0 + + + IPGOFF_1 + IPG_CLK is gated off. + 0x1 + + + + + HCKOFF + HCLK Gated Off Internally + 5 + 1 + read-only + + + HCKOFF_0 + HCLK is active. + 0 + + + HCKOFF_1 + HCLK is gated off. + 0x1 + + + + + PEROFF + IPG_PERCLK Gated Off Internally + 6 + 1 + read-only + + + PEROFF_0 + IPG_PERCLK is active. + 0 + + + PEROFF_1 + IPG_PERCLK is gated off. + 0x1 + + + + + SDOFF + SD Clock Gated Off Internally + 7 + 1 + read-only + + + SDOFF_0 + SD Clock is active. + 0 + + + SDOFF_1 + SD Clock is gated off. + 0x1 + + + + + WTA + Write Transfer Active + 8 + 1 + read-only + + + WTA_0 + No valid data + 0 + + + WTA_1 + Transferring data + 0x1 + + + + + RTA + Read Transfer Active + 9 + 1 + read-only + + + RTA_0 + No valid data + 0 + + + RTA_1 + Transferring data + 0x1 + + + + + BWEN + Buffer Write Enable + 10 + 1 + read-only + + + BWEN_0 + Write disable + 0 + + + BWEN_1 + Write enable + 0x1 + + + + + BREN + Buffer Read Enable + 11 + 1 + read-only + + + BREN_0 + Read disable + 0 + + + BREN_1 + Read enable + 0x1 + + + + + RTR + Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode) + 12 + 1 + read-only + + + RTR_0 + Fixed or well tuned sampling clock + 0 + + + RTR_1 + Sampling clock needs re-tuning + 0x1 + + + + + TSCD + Tape Select Change Done + 15 + 1 + read-only + + + TSCD_0 + Delay cell select change is not finished. + 0 + + + TSCD_1 + Delay cell select change is finished. + 0x1 + + + + + CINST + Card Inserted + 16 + 1 + read-only + + + CINST_0 + Power on Reset or No Card + 0 + + + CINST_1 + Card Inserted + 0x1 + + + + + CDPL + Card Detect Pin Level + 18 + 1 + read-only + + + CDPL_0 + No card present (CD_B = 1) + 0 + + + CDPL_1 + Card present (CD_B = 0) + 0x1 + + + + + WPSPL + Write Protect Switch Pin Level + 19 + 1 + read-only + + + WPSPL_0 + Write protected (WP = 1) + 0 + + + WPSPL_1 + Write enabled (WP = 0) + 0x1 + + + + + CLSL + CMD Line Signal Level + 23 + 1 + read-only + + + DLSL + DATA[7:0] Line Signal Level + 24 + 8 + read-only + + + DATA0 + Data 0 line signal level + 0 + + + DATA1 + Data 1 line signal level + 0x1 + + + DATA2 + Data 2 line signal level + 0x2 + + + DATA3 + Data 3 line signal level + 0x3 + + + DATA4 + Data 4 line signal level + 0x4 + + + DATA5 + Data 5 line signal level + 0x5 + + + DATA6 + Data 6 line signal level + 0x6 + + + DATA7 + Data 7 line signal level + 0x7 + + + + + + + PROT_CTRL + Protocol Control + 0x28 + 32 + read-write + 0x8800020 + 0xFFFFFFFF + + + LCTL + LED Control + 0 + 1 + read-write + + + LCTL_0 + LED off + 0 + + + LCTL_1 + LED on + 0x1 + + + + + DTW + Data Transfer Width + 1 + 2 + read-write + + + DTW_0 + 1-bit mode + 0 + + + DTW_1 + 4-bit mode + 0x1 + + + DTW_2 + 8-bit mode + 0x2 + + + + + D3CD + DATA3 as Card Detection Pin + 3 + 1 + read-write + + + D3CD_0 + DATA3 does not monitor Card Insertion + 0 + + + D3CD_1 + DATA3 as Card Detection Pin + 0x1 + + + + + EMODE + Endian Mode + 4 + 2 + read-write + + + EMODE_0 + Big Endian Mode + 0 + + + EMODE_1 + Half Word Big Endian Mode + 0x1 + + + EMODE_2 + Little Endian Mode + 0x2 + + + + + CDTL + Card Detect Test Level + 6 + 1 + read-write + + + CDTL_0 + Card Detect Test Level is 0, no card inserted + 0 + + + CDTL_1 + Card Detect Test Level is 1, card inserted + 0x1 + + + + + CDSS + Card Detect Signal Selection + 7 + 1 + read-write + + + CDSS_0 + Card Detection Level is selected (for normal purpose). + 0 + + + CDSS_1 + Card Detection Test Level is selected (for test purpose). + 0x1 + + + + + DMASEL + DMA Select + 8 + 2 + read-write + + + DMASEL_0 + No DMA or Simple DMA is selected + 0 + + + DMASEL_1 + ADMA1 is selected + 0x1 + + + DMASEL_2 + ADMA2 is selected + 0x2 + + + + + SABGREQ + Stop At Block Gap Request + 16 + 1 + read-write + + + SABGREQ_0 + Transfer + 0 + + + SABGREQ_1 + Stop + 0x1 + + + + + CREQ + Continue Request + 17 + 1 + read-write + + + CREQ_0 + No effect + 0 + + + CREQ_1 + Restart + 0x1 + + + + + RWCTL + Read Wait Control + 18 + 1 + read-write + + + RWCTL_0 + Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set + 0 + + + RWCTL_1 + Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set + 0x1 + + + + + IABG + Interrupt At Block Gap + 19 + 1 + read-write + + + IABG_0 + Disabled + 0 + + + IABG_1 + Enabled + 0x1 + + + + + RD_DONE_NO_8CLK + RD_DONE_NO_8CLK + 20 + 1 + read-write + + + WECINT + Wakeup Event Enable On Card Interrupt + 24 + 1 + read-write + + + WECINT_0 + Disable + 0 + + + WECINT_1 + Enable + 0x1 + + + + + WECINS + Wakeup Event Enable On SD Card Insertion + 25 + 1 + read-write + + + WECINS_0 + Disable + 0 + + + WECINS_1 + Enable + 0x1 + + + + + WECRM + Wakeup Event Enable On SD Card Removal + 26 + 1 + read-write + + + WECRM_0 + Disable + 0 + + + WECRM_1 + Enable + 0x1 + + + + + BURST_LEN_EN + BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP + 27 + 3 + read-write + + + BURST_LEN_EN_1 + Burst length is enabled for INCR + #xx1 + + + + + NON_EXACT_BLK_RD + NON_EXACT_BLK_RD + 30 + 1 + read-write + + + NON_EXACT_BLK_RD_0 + The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read. + 0 + + + NON_EXACT_BLK_RD_1 + The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. + 0x1 + + + + + + + SYS_CTRL + System Control + 0x2C + 32 + read-write + 0x80800F + 0xFFFFFFFF + + + DVS + Divisor + 4 + 4 + read-write + + + DVS_0 + Divide-by-1 + 0 + + + DVS_1 + Divide-by-2 + 0x1 + + + DVS_14 + Divide-by-15 + 0xE + + + DVS_15 + Divide-by-16 + 0xF + + + + + SDCLKFS + SDCLK Frequency Select + 8 + 8 + read-write + + + DTOCV + Data Timeout Counter Value + 16 + 4 + read-write + + + DTOCV_0 + SDCLK x 2 14 + 0 + + + DTOCV_1 + SDCLK x 2 15 + 0x1 + + + DTOCV_13 + SDCLK x 2 27 + 0xD + + + DTOCV_14 + SDCLK x 2 28 + 0xE + + + DTOCV_15 + SDCLK x 2 29 + 0xF + + + + + IPP_RST_N + IPP_RST_N + 23 + 1 + read-write + + + RSTA + Software Reset For ALL + 24 + 1 + read-write + + + RSTA_0 + No Reset + 0 + + + RSTA_1 + Reset + 0x1 + + + + + RSTC + Software Reset For CMD Line + 25 + 1 + read-write + + + RSTC_0 + No Reset + 0 + + + RSTC_1 + Reset + 0x1 + + + + + RSTD + Software Reset For DATA Line + 26 + 1 + read-write + + + RSTD_0 + No Reset + 0 + + + RSTD_1 + Reset + 0x1 + + + + + INITA + Initialization Active + 27 + 1 + read-write + + + RSTT + Reset Tuning + 28 + 1 + read-write + + + + + INT_STATUS + Interrupt Status + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + CC + Command Complete + 0 + 1 + read-write + oneToClear + + + CC_0 + Command not complete + 0 + + + CC_1 + Command complete + 0x1 + + + + + TC + Transfer Complete + 1 + 1 + read-write + oneToClear + + + TC_0 + Transfer not complete + 0 + + + TC_1 + Transfer complete + 0x1 + + + + + BGE + Block Gap Event + 2 + 1 + read-write + oneToClear + + + BGE_0 + No block gap event + 0 + + + BGE_1 + Transaction stopped at block gap + 0x1 + + + + + DINT + DMA Interrupt + 3 + 1 + read-write + oneToClear + + + DINT_0 + No DMA Interrupt + 0 + + + DINT_1 + DMA Interrupt is generated + 0x1 + + + + + BWR + Buffer Write Ready + 4 + 1 + read-write + oneToClear + + + BWR_0 + Not ready to write buffer + 0 + + + BWR_1 + Ready to write buffer: + 0x1 + + + + + BRR + Buffer Read Ready + 5 + 1 + read-write + oneToClear + + + BRR_0 + Not ready to read buffer + 0 + + + BRR_1 + Ready to read buffer + 0x1 + + + + + CINS + Card Insertion + 6 + 1 + read-write + oneToClear + + + CINS_0 + Card state unstable or removed + 0 + + + CINS_1 + Card inserted + 0x1 + + + + + CRM + Card Removal + 7 + 1 + read-write + oneToClear + + + CRM_0 + Card state unstable or inserted + 0 + + + CRM_1 + Card removed + 0x1 + + + + + CINT + Card Interrupt + 8 + 1 + read-write + oneToClear + + + CINT_0 + No Card Interrupt + 0 + + + CINT_1 + Generate Card Interrupt + 0x1 + + + + + RTE + Re-Tuning Event: (only for SD3.0 SDR104 mode and EMMC HS200 mode) + 12 + 1 + read-write + oneToClear + + + RTE_0 + Re-Tuning is not required + 0 + + + RTE_1 + Re-Tuning should be performed + 0x1 + + + + + TP + Tuning Pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode) + 14 + 1 + read-write + oneToClear + + + CTOE + Command Timeout Error + 16 + 1 + read-write + oneToClear + + + CTOE_0 + No Error + 0 + + + CTOE_1 + Time out + 0x1 + + + + + CCE + Command CRC Error + 17 + 1 + read-write + oneToClear + + + CCE_0 + No Error + 0 + + + CCE_1 + CRC Error Generated. + 0x1 + + + + + CEBE + Command End Bit Error + 18 + 1 + read-write + oneToClear + + + CEBE_0 + No Error + 0 + + + CEBE_1 + End Bit Error Generated + 0x1 + + + + + CIE + Command Index Error + 19 + 1 + read-write + oneToClear + + + CIE_0 + No Error + 0 + + + CIE_1 + Error + 0x1 + + + + + DTOE + Data Timeout Error + 20 + 1 + read-write + oneToClear + + + DTOE_0 + No Error + 0 + + + DTOE_1 + Time out + 0x1 + + + + + DCE + Data CRC Error + 21 + 1 + read-write + oneToClear + + + DCE_0 + No Error + 0 + + + DCE_1 + Error + 0x1 + + + + + DEBE + Data End Bit Error + 22 + 1 + read-write + oneToClear + + + DEBE_0 + No Error + 0 + + + DEBE_1 + Error + 0x1 + + + + + AC12E + Auto CMD12 Error + 24 + 1 + read-write + oneToClear + + + AC12E_0 + No Error + 0 + + + AC12E_1 + Error + 0x1 + + + + + TNE + Tuning Error: (only for SD3.0 SDR104 mode and EMMC HS200 mode) + 26 + 1 + read-write + oneToClear + + + DMAE + DMA Error + 28 + 1 + read-write + oneToClear + + + DMAE_0 + No Error + 0 + + + DMAE_1 + Error + 0x1 + + + + + + + INT_STATUS_EN + Interrupt Status Enable + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + CCSEN + Command Complete Status Enable + 0 + 1 + read-write + + + CCSEN_0 + Masked + 0 + + + CCSEN_1 + Enabled + 0x1 + + + + + TCSEN + Transfer Complete Status Enable + 1 + 1 + read-write + + + TCSEN_0 + Masked + 0 + + + TCSEN_1 + Enabled + 0x1 + + + + + BGESEN + Block Gap Event Status Enable + 2 + 1 + read-write + + + BGESEN_0 + Masked + 0 + + + BGESEN_1 + Enabled + 0x1 + + + + + DINTSEN + DMA Interrupt Status Enable + 3 + 1 + read-write + + + DINTSEN_0 + Masked + 0 + + + DINTSEN_1 + Enabled + 0x1 + + + + + BWRSEN + Buffer Write Ready Status Enable + 4 + 1 + read-write + + + BWRSEN_0 + Masked + 0 + + + BWRSEN_1 + Enabled + 0x1 + + + + + BRRSEN + Buffer Read Ready Status Enable + 5 + 1 + read-write + + + BRRSEN_0 + Masked + 0 + + + BRRSEN_1 + Enabled + 0x1 + + + + + CINSSEN + Card Insertion Status Enable + 6 + 1 + read-write + + + CINSSEN_0 + Masked + 0 + + + CINSSEN_1 + Enabled + 0x1 + + + + + CRMSEN + Card Removal Status Enable + 7 + 1 + read-write + + + CRMSEN_0 + Masked + 0 + + + CRMSEN_1 + Enabled + 0x1 + + + + + CINTSEN + Card Interrupt Status Enable + 8 + 1 + read-write + + + CINTSEN_0 + Masked + 0 + + + CINTSEN_1 + Enabled + 0x1 + + + + + RTESEN + Re-Tuning Event Status Enable + 12 + 1 + read-write + + + RTESEN_0 + Masked + 0 + + + RTESEN_1 + Enabled + 0x1 + + + + + TPSEN + Tuning Pass Status Enable + 14 + 1 + read-write + + + TPSEN_0 + Masked + 0 + + + TPSEN_1 + Enabled + 0x1 + + + + + CTOESEN + Command Timeout Error Status Enable + 16 + 1 + read-write + + + CTOESEN_0 + Masked + 0 + + + CTOESEN_1 + Enabled + 0x1 + + + + + CCESEN + Command CRC Error Status Enable + 17 + 1 + read-write + + + CCESEN_0 + Masked + 0 + + + CCESEN_1 + Enabled + 0x1 + + + + + CEBESEN + Command End Bit Error Status Enable + 18 + 1 + read-write + + + CEBESEN_0 + Masked + 0 + + + CEBESEN_1 + Enabled + 0x1 + + + + + CIESEN + Command Index Error Status Enable + 19 + 1 + read-write + + + CIESEN_0 + Masked + 0 + + + CIESEN_1 + Enabled + 0x1 + + + + + DTOESEN + Data Timeout Error Status Enable + 20 + 1 + read-write + + + DTOESEN_0 + Masked + 0 + + + DTOESEN_1 + Enabled + 0x1 + + + + + DCESEN + Data CRC Error Status Enable + 21 + 1 + read-write + + + DCESEN_0 + Masked + 0 + + + DCESEN_1 + Enabled + 0x1 + + + + + DEBESEN + Data End Bit Error Status Enable + 22 + 1 + read-write + + + DEBESEN_0 + Masked + 0 + + + DEBESEN_1 + Enabled + 0x1 + + + + + AC12ESEN + Auto CMD12 Error Status Enable + 24 + 1 + read-write + + + AC12ESEN_0 + Masked + 0 + + + AC12ESEN_1 + Enabled + 0x1 + + + + + TNESEN + Tuning Error Status Enable + 26 + 1 + read-write + + + TNESEN_0 + Masked + 0 + + + TNESEN_1 + Enabled + 0x1 + + + + + DMAESEN + DMA Error Status Enable + 28 + 1 + read-write + + + DMAESEN_0 + Masked + 0 + + + DMAESEN_1 + Enabled + 0x1 + + + + + + + INT_SIGNAL_EN + Interrupt Signal Enable + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + CCIEN + Command Complete Interrupt Enable + 0 + 1 + read-write + + + CCIEN_0 + Masked + 0 + + + CCIEN_1 + Enabled + 0x1 + + + + + TCIEN + Transfer Complete Interrupt Enable + 1 + 1 + read-write + + + TCIEN_0 + Masked + 0 + + + TCIEN_1 + Enabled + 0x1 + + + + + BGEIEN + Block Gap Event Interrupt Enable + 2 + 1 + read-write + + + BGEIEN_0 + Masked + 0 + + + BGEIEN_1 + Enabled + 0x1 + + + + + DINTIEN + DMA Interrupt Enable + 3 + 1 + read-write + + + DINTIEN_0 + Masked + 0 + + + DINTIEN_1 + Enabled + 0x1 + + + + + BWRIEN + Buffer Write Ready Interrupt Enable + 4 + 1 + read-write + + + BWRIEN_0 + Masked + 0 + + + BWRIEN_1 + Enabled + 0x1 + + + + + BRRIEN + Buffer Read Ready Interrupt Enable + 5 + 1 + read-write + + + BRRIEN_0 + Masked + 0 + + + BRRIEN_1 + Enabled + 0x1 + + + + + CINSIEN + Card Insertion Interrupt Enable + 6 + 1 + read-write + + + CINSIEN_0 + Masked + 0 + + + CINSIEN_1 + Enabled + 0x1 + + + + + CRMIEN + Card Removal Interrupt Enable + 7 + 1 + read-write + + + CRMIEN_0 + Masked + 0 + + + CRMIEN_1 + Enabled + 0x1 + + + + + CINTIEN + Card Interrupt Interrupt Enable + 8 + 1 + read-write + + + CINTIEN_0 + Masked + 0 + + + CINTIEN_1 + Enabled + 0x1 + + + + + RTEIEN + Re-Tuning Event Interrupt Enable + 12 + 1 + read-write + + + RTEIEN_0 + Masked + 0 + + + RTEIEN_1 + Enabled + 0x1 + + + + + TPIEN + Tuning Pass Interrupt Enable + 14 + 1 + read-write + + + TPIEN_0 + Masked + 0 + + + TPIEN_1 + Enabled + 0x1 + + + + + CTOEIEN + Command Timeout Error Interrupt Enable + 16 + 1 + read-write + + + CTOEIEN_0 + Masked + 0 + + + CTOEIEN_1 + Enabled + 0x1 + + + + + CCEIEN + Command CRC Error Interrupt Enable + 17 + 1 + read-write + + + CCEIEN_0 + Masked + 0 + + + CCEIEN_1 + Enabled + 0x1 + + + + + CEBEIEN + Command End Bit Error Interrupt Enable + 18 + 1 + read-write + + + CEBEIEN_0 + Masked + 0 + + + CEBEIEN_1 + Enabled + 0x1 + + + + + CIEIEN + Command Index Error Interrupt Enable + 19 + 1 + read-write + + + CIEIEN_0 + Masked + 0 + + + CIEIEN_1 + Enabled + 0x1 + + + + + DTOEIEN + Data Timeout Error Interrupt Enable + 20 + 1 + read-write + + + DTOEIEN_0 + Masked + 0 + + + DTOEIEN_1 + Enabled + 0x1 + + + + + DCEIEN + Data CRC Error Interrupt Enable + 21 + 1 + read-write + + + DCEIEN_0 + Masked + 0 + + + DCEIEN_1 + Enabled + 0x1 + + + + + DEBEIEN + Data End Bit Error Interrupt Enable + 22 + 1 + read-write + + + DEBEIEN_0 + Masked + 0 + + + DEBEIEN_1 + Enabled + 0x1 + + + + + AC12EIEN + Auto CMD12 Error Interrupt Enable + 24 + 1 + read-write + + + AC12EIEN_0 + Masked + 0 + + + AC12EIEN_1 + Enabled + 0x1 + + + + + TNEIEN + Tuning Error Interrupt Enable + 26 + 1 + read-write + + + TNEIEN_0 + Masked + 0 + + + TNEIEN_1 + Enabled + 0x1 + + + + + DMAEIEN + DMA Error Interrupt Enable + 28 + 1 + read-write + + + DMAEIEN_0 + Masked + 0 + + + DMAEIEN_1 + Enable + 0x1 + + + + + + + AUTOCMD12_ERR_STATUS + Auto CMD12 Error Status + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + AC12NE + Auto CMD12 Not Executed + 0 + 1 + read-only + + + AC12NE_0 + Executed + 0 + + + AC12NE_1 + Not executed + 0x1 + + + + + AC12TOE + Auto CMD12 / 23 Timeout Error + 1 + 1 + read-only + + + AC12TOE_0 + No error + 0 + + + AC12TOE_1 + Time out + 0x1 + + + + + AC12EBE + Auto CMD12 / 23 End Bit Error + 2 + 1 + read-only + + + AC12EBE_0 + No error + 0 + + + AC12EBE_1 + End Bit Error Generated + 0x1 + + + + + AC12CE + Auto CMD12 / 23 CRC Error + 3 + 1 + read-only + + + AC12CE_0 + No CRC error + 0 + + + AC12CE_1 + CRC Error Met in Auto CMD12/23 Response + 0x1 + + + + + AC12IE + Auto CMD12 / 23 Index Error + 4 + 1 + read-only + + + AC12IE_0 + No error + 0 + + + AC12IE_1 + Error, the CMD index in response is not CMD12/23 + 0x1 + + + + + CNIBAC12E + Command Not Issued By Auto CMD12 Error + 7 + 1 + read-only + + + CNIBAC12E_0 + No error + 0 + + + CNIBAC12E_1 + Not Issued + 0x1 + + + + + EXECUTE_TUNING + Execute Tuning + 22 + 1 + read-write + + + SMP_CLK_SEL + Sample Clock Select + 23 + 1 + read-write + + + SMP_CLK_SEL_0 + Fixed clock is used to sample data + 0 + + + SMP_CLK_SEL_1 + Tuned clock is used to sample data + 0x1 + + + + + + + HOST_CTRL_CAP + Host Controller Capabilities + 0x40 + 32 + read-write + 0x7F3B407 + 0xFFFFFFFF + + + SDR50_SUPPORT + SDR50 support + 0 + 1 + read-only + + + SDR104_SUPPORT + SDR104 support + 1 + 1 + read-only + + + DDR50_SUPPORT + DDR50 support + 2 + 1 + read-only + + + TIME_COUNT_RETUNING + Time Counter for Retuning + 8 + 4 + read-write + + + USE_TUNING_SDR50 + Use Tuning for SDR50 + 13 + 1 + read-write + + + USE_TUNING_SDR50_0 + SDR does not require tuning + 0 + + + USE_TUNING_SDR50_1 + SDR50 requires tuning + 0x1 + + + + + RETUNING_MODE + Retuning Mode + 14 + 2 + read-only + + + RETUNING_MODE_0 + Mode 1 + 0 + + + RETUNING_MODE_1 + Mode 2 + 0x1 + + + RETUNING_MODE_2 + Mode 3 + 0x2 + + + + + MBL + Max Block Length + 16 + 3 + read-only + + + MBL_0 + 512 bytes + 0 + + + MBL_1 + 1024 bytes + 0x1 + + + MBL_2 + 2048 bytes + 0x2 + + + MBL_3 + 4096 bytes + 0x3 + + + + + ADMAS + ADMA Support + 20 + 1 + read-only + + + ADMAS_0 + Advanced DMA Not supported + 0 + + + ADMAS_1 + Advanced DMA Supported + 0x1 + + + + + HSS + High Speed Support + 21 + 1 + read-only + + + HSS_0 + High Speed Not Supported + 0 + + + HSS_1 + High Speed Supported + 0x1 + + + + + DMAS + DMA Support + 22 + 1 + read-only + + + DMAS_0 + DMA not supported + 0 + + + DMAS_1 + DMA Supported + 0x1 + + + + + SRS + Suspend / Resume Support + 23 + 1 + read-only + + + SRS_0 + Not supported + 0 + + + SRS_1 + Supported + 0x1 + + + + + VS33 + Voltage Support 3.3V + 24 + 1 + read-only + + + VS33_0 + 3.3V not supported + 0 + + + VS33_1 + 3.3V supported + 0x1 + + + + + VS30 + Voltage Support 3.0 V + 25 + 1 + read-only + + + VS30_0 + 3.0V not supported + 0 + + + VS30_1 + 3.0V supported + 0x1 + + + + + VS18 + Voltage Support 1.8 V + 26 + 1 + read-only + + + VS18_0 + 1.8V not supported + 0 + + + VS18_1 + 1.8V supported + 0x1 + + + + + + + WTMK_LVL + Watermark Level + 0x44 + 32 + read-write + 0x8100810 + 0xFFFFFFFF + + + RD_WML + Read Watermark Level + 0 + 8 + read-write + + + RD_BRST_LEN + Read Burst Length Due to system restriction, the actual burst length may not exceed 16. + 8 + 5 + read-write + + + WR_WML + Write Watermark Level + 16 + 8 + read-write + + + WR_BRST_LEN + Write Burst Length Due to system restriction, the actual burst length may not exceed 16. + 24 + 5 + read-write + + + + + MIX_CTRL + Mixer Control + 0x48 + 32 + read-write + 0x80000000 + 0xFFFFFFFF + + + DMAEN + DMA Enable + 0 + 1 + read-write + + + DMAEN_0 + Disable + 0 + + + DMAEN_1 + Enable + 0x1 + + + + + BCEN + Block Count Enable + 1 + 1 + read-write + + + BCEN_0 + Disable + 0 + + + BCEN_1 + Enable + 0x1 + + + + + AC12EN + Auto CMD12 Enable + 2 + 1 + read-write + + + AC12EN_0 + Disable + 0 + + + AC12EN_1 + Enable + 0x1 + + + + + DDR_EN + Dual Data Rate mode selection + 3 + 1 + read-write + + + DTDSEL + Data Transfer Direction Select + 4 + 1 + read-write + + + DTDSEL_0 + Write (Host to Card) + 0 + + + DTDSEL_1 + Read (Card to Host) + 0x1 + + + + + MSBSEL + Multi / Single Block Select + 5 + 1 + read-write + + + MSBSEL_0 + Single Block + 0 + + + MSBSEL_1 + Multiple Blocks + 0x1 + + + + + NIBBLE_POS + NIBBLE_POS + 6 + 1 + read-write + + + AC23EN + Auto CMD23 Enable + 7 + 1 + read-write + + + EXE_TUNE + Execute Tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) + 22 + 1 + read-write + + + EXE_TUNE_0 + Not Tuned or Tuning Completed + 0 + + + EXE_TUNE_1 + Execute Tuning + 0x1 + + + + + SMP_CLK_SEL + SMP_CLK_SEL + 23 + 1 + read-write + + + SMP_CLK_SEL_0 + Fixed clock is used to sample data / cmd + 0 + + + SMP_CLK_SEL_1 + Tuned clock is used to sample data / cmd + 0x1 + + + + + AUTO_TUNE_EN + Auto Tuning Enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode) + 24 + 1 + read-write + + + AUTO_TUNE_EN_0 + Disable auto tuning + 0 + + + AUTO_TUNE_EN_1 + Enable auto tuning + 0x1 + + + + + FBCLK_SEL + Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) + 25 + 1 + read-write + + + FBCLK_SEL_0 + Feedback clock comes from the loopback CLK + 0 + + + FBCLK_SEL_1 + Feedback clock comes from the ipp_card_clk_out + 0x1 + + + + + + + FORCE_EVENT + Force Event + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + FEVTAC12NE + Force Event Auto Command 12 Not Executed + 0 + 1 + read-write + + + FEVTAC12TOE + Force Event Auto Command 12 Time Out Error + 1 + 1 + read-write + + + FEVTAC12CE + Force Event Auto Command 12 CRC Error + 2 + 1 + read-write + + + FEVTAC12EBE + Force Event Auto Command 12 End Bit Error + 3 + 1 + read-write + + + FEVTAC12IE + Force Event Auto Command 12 Index Error + 4 + 1 + read-write + + + FEVTCNIBAC12E + Force Event Command Not Executed By Auto Command 12 Error + 7 + 1 + read-write + + + FEVTCTOE + Force Event Command Time Out Error + 16 + 1 + read-write + + + FEVTCCE + Force Event Command CRC Error + 17 + 1 + read-write + + + FEVTCEBE + Force Event Command End Bit Error + 18 + 1 + read-write + + + FEVTCIE + Force Event Command Index Error + 19 + 1 + read-write + + + FEVTDTOE + Force Event Data Time Out Error + 20 + 1 + read-write + + + FEVTDCE + Force Event Data CRC Error + 21 + 1 + read-write + + + FEVTDEBE + Force Event Data End Bit Error + 22 + 1 + read-write + + + FEVTAC12E + Force Event Auto Command 12 Error + 24 + 1 + read-write + + + FEVTTNE + Force Tuning Error + 26 + 1 + read-write + + + FEVTDMAE + Force Event DMA Error + 28 + 1 + read-write + + + FEVTCINT + Force Event Card Interrupt + 31 + 1 + read-write + + + + + ADMA_ERR_STATUS + ADMA Error Status Register + 0x54 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADMAES + ADMA Error State (when ADMA Error is occurred) + 0 + 2 + read-only + + + ADMALME + ADMA Length Mismatch Error + 2 + 1 + read-only + + + ADMALME_0 + No Error + 0 + + + ADMALME_1 + Error + 0x1 + + + + + ADMADCE + ADMA Descriptor Error + 3 + 1 + read-only + + + ADMADCE_0 + No Error + 0 + + + ADMADCE_1 + Error + 0x1 + + + + + + + ADMA_SYS_ADDR + ADMA System Address + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADS_ADDR + ADMA System Address + 2 + 30 + read-write + + + + + DLL_CTRL + DLL (Delay Line) Control + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + DLL_CTRL_ENABLE + DLL_CTRL_ENABLE + 0 + 1 + read-write + + + DLL_CTRL_RESET + DLL_CTRL_RESET + 1 + 1 + read-write + + + DLL_CTRL_SLV_FORCE_UPD + DLL_CTRL_SLV_FORCE_UPD + 2 + 1 + read-write + + + DLL_CTRL_SLV_DLY_TARGET0 + DLL_CTRL_SLV_DLY_TARGET0 + 3 + 4 + read-write + + + DLL_CTRL_GATE_UPDATE + DLL_CTRL_GATE_UPDATE + 7 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE + DLL_CTRL_SLV_OVERRIDE + 8 + 1 + read-write + + + DLL_CTRL_SLV_OVERRIDE_VAL + DLL_CTRL_SLV_OVERRIDE_VAL + 9 + 7 + read-write + + + DLL_CTRL_SLV_DLY_TARGET1 + DLL_CTRL_SLV_DLY_TARGET1 + 16 + 3 + read-write + + + DLL_CTRL_SLV_UPDATE_INT + DLL_CTRL_SLV_UPDATE_INT + 20 + 8 + read-write + + + DLL_CTRL_REF_UPDATE_INT + DLL_CTRL_REF_UPDATE_INT + 28 + 4 + read-write + + + + + DLL_STATUS + DLL Status + 0x64 + 32 + read-only + 0x200 + 0xFFFFFFFF + + + DLL_STS_SLV_LOCK + DLL_STS_SLV_LOCK + 0 + 1 + read-only + + + DLL_STS_REF_LOCK + DLL_STS_REF_LOCK + 1 + 1 + read-only + + + DLL_STS_SLV_SEL + DLL_STS_SLV_SEL + 2 + 7 + read-only + + + DLL_STS_REF_SEL + DLL_STS_REF_SEL + 9 + 7 + read-only + + + + + CLK_TUNE_CTRL_STATUS + CLK Tuning Control and Status + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + DLY_CELL_SET_POST + DLY_CELL_SET_POST + 0 + 4 + read-write + + + DLY_CELL_SET_OUT + DLY_CELL_SET_OUT + 4 + 4 + read-write + + + DLY_CELL_SET_PRE + DLY_CELL_SET_PRE + 8 + 7 + read-write + + + NXT_ERR + NXT_ERR + 15 + 1 + read-only + + + TAP_SEL_POST + TAP_SEL_POST + 16 + 4 + read-only + + + TAP_SEL_OUT + TAP_SEL_OUT + 20 + 4 + read-only + + + TAP_SEL_PRE + TAP_SEL_PRE + 24 + 7 + read-only + + + PRE_ERR + PRE_ERR + 31 + 1 + read-only + + + + + VEND_SPEC + Vendor Specific Register + 0xC0 + 32 + read-write + 0x20007809 + 0xFFFFFFFF + + + VSELECT + Voltage Selection + 1 + 1 + read-write + + + VSELECT_0 + Change the voltage to high voltage range, around 3.0 V + 0 + + + VSELECT_1 + Change the voltage to low voltage range, around 1.8 V + 0x1 + + + + + CONFLICT_CHK_EN + Conflict check enable. + 2 + 1 + read-write + + + CONFLICT_CHK_EN_0 + Conflict check disable + 0 + + + CONFLICT_CHK_EN_1 + Conflict check enable + 0x1 + + + + + AC12_WR_CHKBUSY_EN + AC12_WR_CHKBUSY_EN + 3 + 1 + read-write + + + AC12_WR_CHKBUSY_EN_0 + Do not check busy after auto CMD12 for write data packet + 0 + + + AC12_WR_CHKBUSY_EN_1 + Check busy after auto CMD12 for write data packet + 0x1 + + + + + FRC_SDCLK_ON + FRC_SDCLK_ON + 8 + 1 + read-write + + + FRC_SDCLK_ON_0 + CLK active or inactive is fully controlled by the hardware. + 0 + + + FRC_SDCLK_ON_1 + Force CLK active. + 0x1 + + + + + CRC_CHK_DIS + CRC Check Disable + 15 + 1 + read-write + + + CRC_CHK_DIS_0 + Check CRC16 for every read data packet and check CRC bits for every write data packet + 0 + + + CRC_CHK_DIS_1 + Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet + 0x1 + + + + + CMD_BYTE_EN + CMD_BYTE_EN + 31 + 1 + read-write + + + CMD_BYTE_EN_0 + Disable + 0 + + + CMD_BYTE_EN_1 + Enable + 0x1 + + + + + + + MMC_BOOT + MMC Boot Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + DTOCV_ACK + DTOCV_ACK + 0 + 4 + read-write + + + DTOCV_ACK_0 + SDCLK x 2^14 + 0 + + + DTOCV_ACK_1 + SDCLK x 2^15 + 0x1 + + + DTOCV_ACK_2 + SDCLK x 2^16 + 0x2 + + + DTOCV_ACK_3 + SDCLK x 2^17 + 0x3 + + + DTOCV_ACK_4 + SDCLK x 2^18 + 0x4 + + + DTOCV_ACK_5 + SDCLK x 2^19 + 0x5 + + + DTOCV_ACK_6 + SDCLK x 2^20 + 0x6 + + + DTOCV_ACK_7 + SDCLK x 2^21 + 0x7 + + + DTOCV_ACK_14 + SDCLK x 2^28 + 0xE + + + DTOCV_ACK_15 + SDCLK x 2^29 + 0xF + + + + + BOOT_ACK + BOOT_ACK + 4 + 1 + read-write + + + BOOT_ACK_0 + No ack + 0 + + + BOOT_ACK_1 + Ack + 0x1 + + + + + BOOT_MODE + BOOT_MODE + 5 + 1 + read-write + + + BOOT_MODE_0 + Normal boot + 0 + + + BOOT_MODE_1 + Alternative boot + 0x1 + + + + + BOOT_EN + BOOT_EN + 6 + 1 + read-write + + + BOOT_EN_0 + Fast boot disable + 0 + + + BOOT_EN_1 + Fast boot enable + 0x1 + + + + + AUTO_SABG_EN + AUTO_SABG_EN + 7 + 1 + read-write + + + DISABLE_TIME_OUT + Disable Time Out + 8 + 1 + read-write + + + DISABLE_TIME_OUT_0 + Enable time out + 0 + + + DISABLE_TIME_OUT_1 + Disable time out + 0x1 + + + + + BOOT_BLK_CNT + BOOT_BLK_CNT + 16 + 16 + read-write + + + + + VEND_SPEC2 + Vendor Specific 2 Register + 0xC8 + 32 + read-write + 0x1006 + 0xFFFFFFFF + + + CARD_INT_D3_TEST + Card Interrupt Detection Test + 3 + 1 + read-write + + + CARD_INT_D3_TEST_0 + Check the card interrupt only when DATA3 is high. + 0 + + + CARD_INT_D3_TEST_1 + Check the card interrupt by ignoring the status of DATA3. + 0x1 + + + + + TUNING_8bit_EN + TUNING_8bit_EN + 4 + 1 + read-write + + + TUNING_1bit_EN + TUNING_1bit_EN + 5 + 1 + read-write + + + TUNING_CMD_EN + TUNING_CMD_EN + 6 + 1 + read-write + + + TUNING_CMD_EN_0 + Auto tuning circuit does not check the CMD line. + 0 + + + TUNING_CMD_EN_1 + Auto tuning circuit checks the CMD line. + 0x1 + + + + + ACMD23_ARGU2_EN + Argument2 register enable for ACMD23 + 12 + 1 + read-write + + + ACMD23_ARGU2_EN_0 + Disable + 0 + + + ACMD23_ARGU2_EN_1 + Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable. + 0x1 + + + + + PART_DLL_DEBUG + debug for part dll + 13 + 1 + read-write + + + BUS_RST + BUS reset + 14 + 1 + read-write + + + + + TUNING_CTRL + Tuning Control Register + 0xCC + 32 + read-write + 0x212800 + 0xFFFFFFFF + + + TUNING_START_TAP + TUNING_START_TAP + 0 + 8 + read-write + + + TUNING_COUNTER + TUNING_COUNTER + 8 + 8 + read-write + + + TUNING_STEP + TUNING_STEP + 16 + 3 + read-write + + + TUNING_WINDOW + TUNING_WINDOW + 20 + 3 + read-write + + + STD_TUNING_EN + STD_TUNING_EN + 24 + 1 + read-write + + + + + + + USDHC2 + uSDHC + USDHC + 0x402C4000 + + 0 + 0xD0 + registers + + + USDHC2 + 111 + + + + ENET + Ethernet MAC-NET Core + ENET + ENET_ + ENET + 0x402D8000 + + 0 + 0x628 + registers + + + ENET + 114 + + + ENET_1588_Timer + 115 + + + + EIR + Interrupt Event Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TS_TIMER + Timestamp Timer + 15 + 1 + read-write + oneToClear + + + TS_AVAIL + Transmit Timestamp Available + 16 + 1 + read-write + oneToClear + + + WAKEUP + Node Wakeup Request Indication + 17 + 1 + read-write + oneToClear + + + PLR + Payload Receive Error + 18 + 1 + read-write + oneToClear + + + UN + Transmit FIFO Underrun + 19 + 1 + read-write + oneToClear + + + RL + Collision Retry Limit + 20 + 1 + read-write + oneToClear + + + LC + Late Collision + 21 + 1 + read-write + oneToClear + + + EBERR + Ethernet Bus Error + 22 + 1 + read-write + oneToClear + + + MII + MII Interrupt. + 23 + 1 + read-write + oneToClear + + + RXB + Receive Buffer Interrupt + 24 + 1 + read-write + oneToClear + + + RXF + Receive Frame Interrupt + 25 + 1 + read-write + oneToClear + + + TXB + Transmit Buffer Interrupt + 26 + 1 + read-write + oneToClear + + + TXF + Transmit Frame Interrupt + 27 + 1 + read-write + oneToClear + + + GRA + Graceful Stop Complete + 28 + 1 + read-write + oneToClear + + + BABT + Babbling Transmit Error + 29 + 1 + read-write + oneToClear + + + BABR + Babbling Receive Error + 30 + 1 + read-write + oneToClear + + + + + EIMR + Interrupt Mask Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TS_TIMER + TS_TIMER Interrupt Mask + 15 + 1 + read-write + + + TS_AVAIL + TS_AVAIL Interrupt Mask + 16 + 1 + read-write + + + WAKEUP + WAKEUP Interrupt Mask + 17 + 1 + read-write + + + PLR + PLR Interrupt Mask + 18 + 1 + read-write + + + UN + UN Interrupt Mask + 19 + 1 + read-write + + + RL + RL Interrupt Mask + 20 + 1 + read-write + + + LC + LC Interrupt Mask + 21 + 1 + read-write + + + EBERR + EBERR Interrupt Mask + 22 + 1 + read-write + + + MII + MII Interrupt Mask + 23 + 1 + read-write + + + RXB + RXB Interrupt Mask + 24 + 1 + read-write + + + RXF + RXF Interrupt Mask + 25 + 1 + read-write + + + TXB + TXB Interrupt Mask + 26 + 1 + read-write + + + TXB_0 + The corresponding interrupt source is masked. + 0 + + + TXB_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + TXF + TXF Interrupt Mask + 27 + 1 + read-write + + + TXF_0 + The corresponding interrupt source is masked. + 0 + + + TXF_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + GRA + GRA Interrupt Mask + 28 + 1 + read-write + + + GRA_0 + The corresponding interrupt source is masked. + 0 + + + GRA_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + BABT + BABT Interrupt Mask + 29 + 1 + read-write + + + BABT_0 + The corresponding interrupt source is masked. + 0 + + + BABT_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + BABR + BABR Interrupt Mask + 30 + 1 + read-write + + + BABR_0 + The corresponding interrupt source is masked. + 0 + + + BABR_1 + The corresponding interrupt source is not masked. + 0x1 + + + + + + + RDAR + Receive Descriptor Active Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + RDAR + Receive Descriptor Active + 24 + 1 + read-write + + + + + TDAR + Transmit Descriptor Active Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDAR + Transmit Descriptor Active + 24 + 1 + read-write + + + + + ECR + Ethernet Control Register + 0x24 + 32 + read-write + 0x70000000 + 0xFFFFFFFF + + + RESET + Ethernet MAC Reset + 0 + 1 + read-write + + + ETHEREN + Ethernet Enable + 1 + 1 + read-write + + + ETHEREN_0 + Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame. + 0 + + + ETHEREN_1 + MAC is enabled, and reception and transmission are possible. + 0x1 + + + + + MAGICEN + Magic Packet Detection Enable + 2 + 1 + read-write + + + MAGICEN_0 + Magic detection logic disabled. + 0 + + + MAGICEN_1 + The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. + 0x1 + + + + + SLEEP + Sleep Mode Enable + 3 + 1 + read-write + + + SLEEP_0 + Normal operating mode. + 0 + + + SLEEP_1 + Sleep mode. + 0x1 + + + + + EN1588 + EN1588 Enable + 4 + 1 + read-write + + + EN1588_0 + Legacy FEC buffer descriptors and functions enabled. + 0 + + + EN1588_1 + Enhanced frame time-stamping functions enabled. + 0x1 + + + + + DBGEN + Debug Enable + 6 + 1 + read-write + + + DBGEN_0 + MAC continues operation in debug mode. + 0 + + + DBGEN_1 + MAC enters hardware freeze mode when the processor is in debug mode. + 0x1 + + + + + DBSWP + Descriptor Byte Swapping Enable + 8 + 1 + read-write + + + DBSWP_0 + The buffer descriptor bytes are not swapped to support big-endian devices. + 0 + + + DBSWP_1 + The buffer descriptor bytes are swapped to support little-endian devices. + 0x1 + + + + + + + MMFR + MII Management Frame Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Management Frame Data + 0 + 16 + read-write + + + TA + Turn Around + 16 + 2 + read-write + + + RA + Register Address + 18 + 5 + read-write + + + PA + PHY Address + 23 + 5 + read-write + + + OP + Operation Code + 28 + 2 + read-write + + + ST + Start Of Frame Delimiter + 30 + 2 + read-write + + + + + MSCR + MII Speed Control Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + MII_SPEED + MII Speed + 1 + 6 + read-write + + + DIS_PRE + Disable Preamble + 7 + 1 + read-write + + + DIS_PRE_0 + Preamble enabled. + 0 + + + DIS_PRE_1 + Preamble (32 ones) is not prepended to the MII management frame. + 0x1 + + + + + HOLDTIME + Hold time On MDIO Output + 8 + 3 + read-write + + + HOLDTIME_0 + 1 internal module clock cycle + 0 + + + HOLDTIME_1 + 2 internal module clock cycles + 0x1 + + + HOLDTIME_2 + 3 internal module clock cycles + 0x2 + + + HOLDTIME_7 + 8 internal module clock cycles + 0x7 + + + + + + + MIBC + MIB Control Register + 0x64 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + MIB_CLEAR + MIB Clear + 29 + 1 + read-write + + + MIB_CLEAR_0 + See note above. + 0 + + + MIB_CLEAR_1 + All statistics counters are reset to 0. + 0x1 + + + + + MIB_IDLE + MIB Idle + 30 + 1 + read-only + + + MIB_IDLE_0 + The MIB block is updating MIB counters. + 0 + + + MIB_IDLE_1 + The MIB block is not currently updating any MIB counters. + 0x1 + + + + + MIB_DIS + Disable MIB Logic + 31 + 1 + read-write + + + MIB_DIS_0 + MIB logic is enabled. + 0 + + + MIB_DIS_1 + MIB logic is disabled. The MIB logic halts and does not update any MIB counters. + 0x1 + + + + + + + RCR + Receive Control Register + 0x84 + 32 + read-write + 0x5EE0001 + 0xFFFFFFFF + + + LOOP + Internal Loopback + 0 + 1 + read-write + + + LOOP_0 + Loopback disabled. + 0 + + + LOOP_1 + Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. + 0x1 + + + + + DRT + Disable Receive On Transmit + 1 + 1 + read-write + + + DRT_0 + Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode. + 0 + + + DRT_1 + Disable reception of frames while transmitting. (Normally used for half-duplex mode.) + 0x1 + + + + + MII_MODE + Media Independent Interface Mode + 2 + 1 + read-write + + + MII_MODE_1 + MII or RMII mode, as indicated by the RMII_MODE field. + 0x1 + + + + + PROM + Promiscuous Mode + 3 + 1 + read-write + + + PROM_0 + Disabled. + 0 + + + PROM_1 + Enabled. + 0x1 + + + + + BC_REJ + Broadcast Frame Reject + 4 + 1 + read-write + + + FCE + Flow Control Enable + 5 + 1 + read-write + + + RMII_MODE + RMII Mode Enable + 8 + 1 + read-write + + + RMII_MODE_0 + MAC configured for MII mode. + 0 + + + RMII_MODE_1 + MAC configured for RMII operation. + 0x1 + + + + + RMII_10T + Enables 10-Mbit/s mode of the RMII . + 9 + 1 + read-write + + + RMII_10T_0 + 100-Mbit/s operation. + 0 + + + RMII_10T_1 + 10-Mbit/s operation. + 0x1 + + + + + PADEN + Enable Frame Padding Remove On Receive + 12 + 1 + read-write + + + PADEN_0 + No padding is removed on receive by the MAC. + 0 + + + PADEN_1 + Padding is removed from received frames. + 0x1 + + + + + PAUFWD + Terminate/Forward Pause Frames + 13 + 1 + read-write + + + PAUFWD_0 + Pause frames are terminated and discarded in the MAC. + 0 + + + PAUFWD_1 + Pause frames are forwarded to the user application. + 0x1 + + + + + CRCFWD + Terminate/Forward Received CRC + 14 + 1 + read-write + + + CRCFWD_0 + The CRC field of received frames is transmitted to the user application. + 0 + + + CRCFWD_1 + The CRC field is stripped from the frame. + 0x1 + + + + + CFEN + MAC Control Frame Enable + 15 + 1 + read-write + + + CFEN_0 + MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface. + 0 + + + CFEN_1 + MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. + 0x1 + + + + + MAX_FL + Maximum Frame Length + 16 + 14 + read-write + + + NLC + Payload Length Check Disable + 30 + 1 + read-write + + + NLC_0 + The payload length check is disabled. + 0 + + + NLC_1 + The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field. + 0x1 + + + + + GRS + Graceful Receive Stopped + 31 + 1 + read-only + + + + + TCR + Transmit Control Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + GTS + Graceful Transmit Stop + 0 + 1 + read-write + + + FDEN + Full-Duplex Enable + 2 + 1 + read-write + + + TFC_PAUSE + Transmit Frame Control Pause + 3 + 1 + read-write + + + TFC_PAUSE_0 + No PAUSE frame transmitted. + 0 + + + TFC_PAUSE_1 + The MAC stops transmission of data frames after the current transmission is complete. + 0x1 + + + + + RFC_PAUSE + Receive Frame Control Pause + 4 + 1 + read-only + + + ADDSEL + Source MAC Address Select On Transmit + 5 + 3 + read-write + + + ADDSEL_0 + Node MAC address programmed on PADDR1/2 registers. + 0 + + + + + ADDINS + Set MAC Address On Transmit + 8 + 1 + read-write + + + ADDINS_0 + The source MAC address is not modified by the MAC. + 0 + + + ADDINS_1 + The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. + 0x1 + + + + + CRCFWD + Forward Frame From Application With CRC + 9 + 1 + read-write + + + CRCFWD_0 + TxBD[TC] controls whether the frame has a CRC from the application. + 0 + + + CRCFWD_1 + The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application. + 0x1 + + + + + + + PALR + Physical Address Lower Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PADDR1 + Pause Address + 0 + 32 + read-write + + + + + PAUR + Physical Address Upper Register + 0xE8 + 32 + read-write + 0x8808 + 0xFFFFFFFF + + + TYPE + Type Field In PAUSE Frames + 0 + 16 + read-only + + + PADDR2 + Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address field in PAUSE frames + 16 + 16 + read-write + + + + + OPD + Opcode/Pause Duration Register + 0xEC + 32 + read-write + 0x10000 + 0xFFFFFFFF + + + PAUSE_DUR + Pause Duration + 0 + 16 + read-write + + + OPCODE + Opcode Field In PAUSE Frames + 16 + 16 + read-only + + + + + TXIC + Transmit Interrupt Coalescing Register + 0xF0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICTT + Interrupt coalescing timer threshold + 0 + 16 + read-write + + + ICFT + Interrupt coalescing frame count threshold + 20 + 8 + read-write + + + ICCS + Interrupt Coalescing Timer Clock Source Select + 30 + 1 + read-write + + + ICCS_0 + Use MII/GMII TX clocks. + 0 + + + ICCS_1 + Use ENET system clock. + 0x1 + + + + + ICEN + Interrupt Coalescing Enable + 31 + 1 + read-write + + + ICEN_0 + Disable Interrupt coalescing. + 0 + + + ICEN_1 + Enable Interrupt coalescing. + 0x1 + + + + + + + RXIC + Receive Interrupt Coalescing Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + ICTT + Interrupt coalescing timer threshold + 0 + 16 + read-write + + + ICFT + Interrupt coalescing frame count threshold + 20 + 8 + read-write + + + ICCS + Interrupt Coalescing Timer Clock Source Select + 30 + 1 + read-write + + + ICCS_0 + Use MII/GMII TX clocks. + 0 + + + ICCS_1 + Use ENET system clock. + 0x1 + + + + + ICEN + Interrupt Coalescing Enable + 31 + 1 + read-write + + + ICEN_0 + Disable Interrupt coalescing. + 0 + + + ICEN_1 + Enable Interrupt coalescing. + 0x1 + + + + + + + IAUR + Descriptor Individual Upper Address Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + IADDR1 + Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address + 0 + 32 + read-write + + + + + IALR + Descriptor Individual Lower Address Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + IADDR2 + Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address + 0 + 32 + read-write + + + + + GAUR + Descriptor Group Upper Address Register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + GADDR1 + Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address + 0 + 32 + read-write + + + + + GALR + Descriptor Group Lower Address Register + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + GADDR2 + Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address + 0 + 32 + read-write + + + + + TFWR + Transmit FIFO Watermark Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + TFWR + Transmit FIFO Write + 0 + 6 + read-write + + + TFWR_0 + 64 bytes written. + 0 + + + TFWR_1 + 64 bytes written. + 0x1 + + + TFWR_2 + 128 bytes written. + 0x2 + + + TFWR_3 + 192 bytes written. + 0x3 + + + TFWR_31 + 1984 bytes written. + 0x1F + + + + + STRFWD + Store And Forward Enable + 8 + 1 + read-write + + + STRFWD_0 + Reset. The transmission start threshold is programmed in TFWR[TFWR]. + 0 + + + STRFWD_1 + Enabled. + 0x1 + + + + + + + RDSR + Receive Descriptor Ring Start Register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + R_DES_START + Pointer to the beginning of the receive buffer descriptor queue. + 3 + 29 + read-write + + + + + TDSR + Transmit Buffer Descriptor Ring Start Register + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + X_DES_START + Pointer to the beginning of the transmit buffer descriptor queue. + 3 + 29 + read-write + + + + + MRBR + Maximum Receive Buffer Size Register + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + R_BUF_SIZE + Receive buffer size in bytes + 4 + 10 + read-write + + + + + RSFL + Receive FIFO Section Full Threshold + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_SECTION_FULL + Value Of Receive FIFO Section Full Threshold + 0 + 8 + read-write + + + + + RSEM + Receive FIFO Section Empty Threshold + 0x194 + 32 + read-write + 0 + 0xFFFFFFFF + + + RX_SECTION_EMPTY + Value Of The Receive FIFO Section Empty Threshold + 0 + 8 + read-write + + + STAT_SECTION_EMPTY + RX Status FIFO Section Empty Threshold + 16 + 5 + read-write + + + + + RAEM + Receive FIFO Almost Empty Threshold + 0x198 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + RX_ALMOST_EMPTY + Value Of The Receive FIFO Almost Empty Threshold + 0 + 8 + read-write + + + + + RAFL + Receive FIFO Almost Full Threshold + 0x19C + 32 + read-write + 0x4 + 0xFFFFFFFF + + + RX_ALMOST_FULL + Value Of The Receive FIFO Almost Full Threshold + 0 + 8 + read-write + + + + + TSEM + Transmit FIFO Section Empty Threshold + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + TX_SECTION_EMPTY + Value Of The Transmit FIFO Section Empty Threshold + 0 + 8 + read-write + + + + + TAEM + Transmit FIFO Almost Empty Threshold + 0x1A4 + 32 + read-write + 0x4 + 0xFFFFFFFF + + + TX_ALMOST_EMPTY + Value of Transmit FIFO Almost Empty Threshold + 0 + 8 + read-write + + + + + TAFL + Transmit FIFO Almost Full Threshold + 0x1A8 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + TX_ALMOST_FULL + Value Of The Transmit FIFO Almost Full Threshold + 0 + 8 + read-write + + + + + TIPG + Transmit Inter-Packet Gap + 0x1AC + 32 + read-write + 0xC + 0xFFFFFFFF + + + IPG + Transmit Inter-Packet Gap + 0 + 5 + read-write + + + + + FTRL + Frame Truncation Length + 0x1B0 + 32 + read-write + 0x7FF + 0xFFFFFFFF + + + TRUNC_FL + Frame Truncation Length + 0 + 14 + read-write + + + + + TACC + Transmit Accelerator Function Configuration + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SHIFT16 + TX FIFO Shift-16 + 0 + 1 + read-write + + + SHIFT16_0 + Disabled. + 0 + + + SHIFT16_1 + Indicates to the transmit data FIFO that the written frames contain two additional octets before the frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is extended to a 16-byte header. + 0x1 + + + + + IPCHK + Enables insertion of IP header checksum. + 3 + 1 + read-write + + + IPCHK_0 + Checksum is not inserted. + 0 + + + IPCHK_1 + If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must be cleared. If a non-IP frame is transmitted the frame is not modified. + 0x1 + + + + + PROCHK + Enables insertion of protocol checksum. + 4 + 1 + read-write + + + PROCHK_0 + Checksum not inserted. + 0 + + + PROCHK_1 + If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the frame. The checksum field must be cleared. The other frames are not modified. + 0x1 + + + + + + + RACC + Receive Accelerator Function Configuration + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + PADREM + Enable Padding Removal For Short IP Frames + 0 + 1 + read-write + + + PADREM_0 + Padding not removed. + 0 + + + PADREM_1 + Any bytes following the IP payload section of the frame are removed from the frame. + 0x1 + + + + + IPDIS + Enable Discard Of Frames With Wrong IPv4 Header Checksum + 1 + 1 + read-write + + + IPDIS_0 + Frames with wrong IPv4 header checksum are not discarded. + 0 + + + IPDIS_1 + If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + 0x1 + + + + + PRODIS + Enable Discard Of Frames With Wrong Protocol Checksum + 2 + 1 + read-write + + + PRODIS_0 + Frames with wrong checksum are not discarded. + 0 + + + PRODIS_1 + If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL cleared). + 0x1 + + + + + LINEDIS + Enable Discard Of Frames With MAC Layer Errors + 6 + 1 + read-write + + + LINEDIS_0 + Frames with errors are not discarded. + 0 + + + LINEDIS_1 + Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. + 0x1 + + + + + SHIFT16 + RX FIFO Shift-16 + 7 + 1 + read-write + + + SHIFT16_0 + Disabled. + 0 + + + SHIFT16_1 + Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO. + 0x1 + + + + + + + RMON_T_DROP + Reserved Statistic Register + 0x200 + 32 + read-only + 0 + 0xFFFFFFFF + + + RMON_T_PACKETS + Tx Packet Count Statistic Register + 0x204 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Packet count + 0 + 16 + read-only + + + + + RMON_T_BC_PKT + Tx Broadcast Packets Statistic Register + 0x208 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Broadcast packets + 0 + 16 + read-only + + + + + RMON_T_MC_PKT + Tx Multicast Packets Statistic Register + 0x20C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Multicast packets + 0 + 16 + read-only + + + + + RMON_T_CRC_ALIGN + Tx Packets with CRC/Align Error Statistic Register + 0x210 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Packets with CRC/align error + 0 + 16 + read-only + + + + + RMON_T_UNDERSIZE + Tx Packets Less Than Bytes and Good CRC Statistic Register + 0x214 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets less than 64 bytes with good CRC + 0 + 16 + read-only + + + + + RMON_T_OVERSIZE + Tx Packets GT MAX_FL bytes and Good CRC Statistic Register + 0x218 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets greater than MAX_FL bytes with good CRC + 0 + 16 + read-only + + + + + RMON_T_FRAG + Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register + 0x21C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of packets less than 64 bytes with bad CRC + 0 + 16 + read-only + + + + + RMON_T_JAB + Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register + 0x220 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets greater than MAX_FL bytes and bad CRC + 0 + 16 + read-only + + + + + RMON_T_COL + Tx Collision Count Statistic Register + 0x224 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit collisions + 0 + 16 + read-only + + + + + RMON_T_P64 + Tx 64-Byte Packets Statistic Register + 0x228 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 64-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P65TO127 + Tx 65- to 127-byte Packets Statistic Register + 0x22C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 65- to 127-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P128TO255 + Tx 128- to 255-byte Packets Statistic Register + 0x230 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 128- to 255-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P256TO511 + Tx 256- to 511-byte Packets Statistic Register + 0x234 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 256- to 511-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P512TO1023 + Tx 512- to 1023-byte Packets Statistic Register + 0x238 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 512- to 1023-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P1024TO2047 + Tx 1024- to 2047-byte Packets Statistic Register + 0x23C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of 1024- to 2047-byte transmit packets + 0 + 16 + read-only + + + + + RMON_T_P_GTE2048 + Tx Packets Greater Than 2048 Bytes Statistic Register + 0x240 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXPKTS + Number of transmit packets greater than 2048 bytes + 0 + 16 + read-only + + + + + RMON_T_OCTETS + Tx Octets Statistic Register + 0x244 + 32 + read-only + 0 + 0xFFFFFFFF + + + TXOCTS + Number of transmit octets + 0 + 32 + read-only + + + + + IEEE_T_DROP + Reserved Statistic Register + 0x248 + 32 + read-only + 0 + 0xFFFFFFFF + + + IEEE_T_FRAME_OK + Frames Transmitted OK Statistic Register + 0x24C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted OK + 0 + 16 + read-only + + + + + IEEE_T_1COL + Frames Transmitted with Single Collision Statistic Register + 0x250 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with one collision + 0 + 16 + read-only + + + + + IEEE_T_MCOL + Frames Transmitted with Multiple Collisions Statistic Register + 0x254 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with multiple collisions + 0 + 16 + read-only + + + + + IEEE_T_DEF + Frames Transmitted after Deferral Delay Statistic Register + 0x258 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with deferral delay + 0 + 16 + read-only + + + + + IEEE_T_LCOL + Frames Transmitted with Late Collision Statistic Register + 0x25C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with late collision + 0 + 16 + read-only + + + + + IEEE_T_EXCOL + Frames Transmitted with Excessive Collisions Statistic Register + 0x260 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with excessive collisions + 0 + 16 + read-only + + + + + IEEE_T_MACERR + Frames Transmitted with Tx FIFO Underrun Statistic Register + 0x264 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with transmit FIFO underrun + 0 + 16 + read-only + + + + + IEEE_T_CSERR + Frames Transmitted with Carrier Sense Error Statistic Register + 0x268 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames transmitted with carrier sense error + 0 + 16 + read-only + + + + + IEEE_T_SQE + Reserved Statistic Register + 0x26C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + This read-only field is reserved and always has the value 0 + 0 + 16 + read-only + + + + + IEEE_T_FDXFC + Flow Control Pause Frames Transmitted Statistic Register + 0x270 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of flow-control pause frames transmitted + 0 + 16 + read-only + + + + + IEEE_T_OCTETS_OK + Octet Count for Frames Transmitted w/o Error Statistic Register + 0x274 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Octet count for frames transmitted without error Counts total octets (includes header and FCS fields). + 0 + 32 + read-only + + + + + RMON_R_PACKETS + Rx Packet Count Statistic Register + 0x284 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of packets received + 0 + 16 + read-only + + + + + RMON_R_BC_PKT + Rx Broadcast Packets Statistic Register + 0x288 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive broadcast packets + 0 + 16 + read-only + + + + + RMON_R_MC_PKT + Rx Multicast Packets Statistic Register + 0x28C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive multicast packets + 0 + 16 + read-only + + + + + RMON_R_CRC_ALIGN + Rx Packets with CRC/Align Error Statistic Register + 0x290 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets with CRC or align error + 0 + 16 + read-only + + + + + RMON_R_UNDERSIZE + Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register + 0x294 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets with less than 64 bytes and good CRC + 0 + 16 + read-only + + + + + RMON_R_OVERSIZE + Rx Packets Greater Than MAX_FL and Good CRC Statistic Register + 0x298 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets greater than MAX_FL and good CRC + 0 + 16 + read-only + + + + + RMON_R_FRAG + Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register + 0x29C + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets with less than 64 bytes and bad CRC + 0 + 16 + read-only + + + + + RMON_R_JAB + Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register + 0x2A0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive packets greater than MAX_FL and bad CRC + 0 + 16 + read-only + + + + + RMON_R_RESVD_0 + Reserved Statistic Register + 0x2A4 + 32 + read-only + 0 + 0xFFFFFFFF + + + RMON_R_P64 + Rx 64-Byte Packets Statistic Register + 0x2A8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 64-byte receive packets + 0 + 16 + read-only + + + + + RMON_R_P65TO127 + Rx 65- to 127-Byte Packets Statistic Register + 0x2AC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 65- to 127-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P128TO255 + Rx 128- to 255-Byte Packets Statistic Register + 0x2B0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 128- to 255-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P256TO511 + Rx 256- to 511-Byte Packets Statistic Register + 0x2B4 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 256- to 511-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P512TO1023 + Rx 512- to 1023-Byte Packets Statistic Register + 0x2B8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 512- to 1023-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P1024TO2047 + Rx 1024- to 2047-Byte Packets Statistic Register + 0x2BC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of 1024- to 2047-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_P_GTE2048 + Rx Packets Greater than 2048 Bytes Statistic Register + 0x2C0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of greater-than-2048-byte recieve packets + 0 + 16 + read-only + + + + + RMON_R_OCTETS + Rx Octets Statistic Register + 0x2C4 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of receive octets + 0 + 32 + read-only + + + + + IEEE_R_DROP + Frames not Counted Correctly Statistic Register + 0x2C8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Frame count + 0 + 16 + read-only + + + + + IEEE_R_FRAME_OK + Frames Received OK Statistic Register + 0x2CC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames received OK + 0 + 16 + read-only + + + + + IEEE_R_CRC + Frames Received with CRC Error Statistic Register + 0x2D0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames received with CRC error + 0 + 16 + read-only + + + + + IEEE_R_ALIGN + Frames Received with Alignment Error Statistic Register + 0x2D4 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of frames received with alignment error + 0 + 16 + read-only + + + + + IEEE_R_MACERR + Receive FIFO Overflow Count Statistic Register + 0x2D8 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Receive FIFO overflow count + 0 + 16 + read-only + + + + + IEEE_R_FDXFC + Flow Control Pause Frames Received Statistic Register + 0x2DC + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of flow-control pause frames received + 0 + 16 + read-only + + + + + IEEE_R_OCTETS_OK + Octet Count for Frames Received without Error Statistic Register + 0x2E0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Number of octets for frames received without error + 0 + 32 + read-only + + + + + ATCR + Adjustable Timer Control Register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + Enable Timer + 0 + 1 + read-write + + + EN_0 + The timer stops at the current value. + 0 + + + EN_1 + The timer starts incrementing. + 0x1 + + + + + OFFEN + Enable One-Shot Offset Event + 2 + 1 + read-write + + + OFFEN_0 + Disable. + 0 + + + OFFEN_1 + The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared when the offset event is reached, so no further event occurs until the field is set again. The timer offset value must be set before setting this field. + 0x1 + + + + + OFFRST + Reset Timer On Offset Event + 3 + 1 + read-write + + + OFFRST_0 + The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached. + 0 + + + OFFRST_1 + If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. + 0x1 + + + + + PEREN + Enable Periodical Event + 4 + 1 + read-write + + + PEREN_0 + Disable. + 0 + + + PEREN_1 + A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when the timer wraps around according to the periodic setting ATPER. The timer period value must be set before setting this bit. Not all devices contain the event signal output. See the chip configuration details. + 0x1 + + + + + PINPER + Enables event signal output assertion on period event + 7 + 1 + read-write + + + PINPER_0 + Disable. + 0 + + + PINPER_1 + Enable. + 0x1 + + + + + RESTART + Reset Timer + 9 + 1 + read-write + + + CAPTURE + Capture Timer Value + 11 + 1 + read-write + + + CAPTURE_0 + No effect. + 0 + + + CAPTURE_1 + The current time is captured and can be read from the ATVR register. + 0x1 + + + + + SLAVE + Enable Timer Slave Mode + 13 + 1 + read-write + + + SLAVE_0 + The timer is active and all configuration fields in this register are relevant. + 0 + + + SLAVE_1 + The internal timer is disabled and the externally provided timer value is used. All other fields, except CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value. + 0x1 + + + + + + + ATVR + Timer Value Register + 0x404 + 32 + read-write + 0 + 0xFFFFFFFF + + + ATIME + A write sets the timer + 0 + 32 + read-write + + + + + ATOFF + Timer Offset Register + 0x408 + 32 + read-write + 0 + 0xFFFFFFFF + + + OFFSET + Offset value for one-shot event generation + 0 + 32 + read-write + + + + + ATPER + Timer Period Register + 0x40C + 32 + read-write + 0x3B9ACA00 + 0xFFFFFFFF + + + PERIOD + Value for generating periodic events + 0 + 32 + read-write + + + + + ATCOR + Timer Correction Register + 0x410 + 32 + read-write + 0 + 0xFFFFFFFF + + + COR + Correction Counter Wrap-Around Value + 0 + 31 + read-write + + + + + ATINC + Time-Stamping Clock Period Register + 0x414 + 32 + read-write + 0 + 0xFFFFFFFF + + + INC + Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds + 0 + 7 + read-write + + + INC_CORR + Correction Increment Value + 8 + 7 + read-write + + + + + ATSTMP + Timestamp of Last Transmitted Frame + 0x418 + 32 + read-only + 0 + 0xFFFFFFFF + + + TIMESTAMP + Timestamp of the last frame transmitted by the core that had TxBD[TS] set + 0 + 32 + read-only + + + + + TGSR + Timer Global Status Register + 0x604 + 32 + read-write + 0 + 0xFFFFFFFF + + + TF0 + Copy Of Timer Flag For Channel 0 + 0 + 1 + read-write + oneToClear + + + TF0_0 + Timer Flag for Channel 0 is clear + 0 + + + TF0_1 + Timer Flag for Channel 0 is set + 0x1 + + + + + TF1 + Copy Of Timer Flag For Channel 1 + 1 + 1 + read-write + oneToClear + + + TF1_0 + Timer Flag for Channel 1 is clear + 0 + + + TF1_1 + Timer Flag for Channel 1 is set + 0x1 + + + + + TF2 + Copy Of Timer Flag For Channel 2 + 2 + 1 + read-write + oneToClear + + + TF2_0 + Timer Flag for Channel 2 is clear + 0 + + + TF2_1 + Timer Flag for Channel 2 is set + 0x1 + + + + + TF3 + Copy Of Timer Flag For Channel 3 + 3 + 1 + read-write + oneToClear + + + TF3_0 + Timer Flag for Channel 3 is clear + 0 + + + TF3_1 + Timer Flag for Channel 3 is set + 0x1 + + + + + + + 4 + 0x8 + 0,1,2,3 + TCSR%s + Timer Control Status Register + 0x608 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDRE + Timer DMA Request Enable + 0 + 1 + read-write + + + TDRE_0 + DMA request is disabled + 0 + + + TDRE_1 + DMA request is enabled + 0x1 + + + + + TMODE + Timer Mode + 2 + 4 + read-write + + + TMODE_0 + Timer Channel is disabled. + 0 + + + TMODE_1 + Timer Channel is configured for Input Capture on rising edge. + 0x1 + + + TMODE_2 + Timer Channel is configured for Input Capture on falling edge. + 0x2 + + + TMODE_3 + Timer Channel is configured for Input Capture on both edges. + 0x3 + + + TMODE_4 + Timer Channel is configured for Output Compare - software only. + 0x4 + + + TMODE_5 + Timer Channel is configured for Output Compare - toggle output on compare. + 0x5 + + + TMODE_6 + Timer Channel is configured for Output Compare - clear output on compare. + 0x6 + + + TMODE_7 + Timer Channel is configured for Output Compare - set output on compare. + 0x7 + + + TMODE_9 + Timer Channel is configured for Output Compare - set output on compare, clear output on overflow. + #10x1 + + + TMODE_10 + Timer Channel is configured for Output Compare - clear output on compare, set output on overflow. + 0xA + + + TMODE_14 + Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC. + 0xE + + + TMODE_15 + Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC. + 0xF + + + + + TIE + Timer Interrupt Enable + 6 + 1 + read-write + + + TIE_0 + Interrupt is disabled + 0 + + + TIE_1 + Interrupt is enabled + 0x1 + + + + + TF + Timer Flag + 7 + 1 + read-write + oneToClear + + + TF_0 + Input Capture or Output Compare has not occurred. + 0 + + + TF_1 + Input Capture or Output Compare has occurred. + 0x1 + + + + + TPWC + Timer PulseWidth Control + 11 + 5 + read-write + + + TPWC_0 + Pulse width is one 1588-clock cycle. + 0 + + + TPWC_1 + Pulse width is two 1588-clock cycles. + 0x1 + + + TPWC_2 + Pulse width is three 1588-clock cycles. + 0x2 + + + TPWC_3 + Pulse width is four 1588-clock cycles. + 0x3 + + + TPWC_31 + Pulse width is 32 1588-clock cycles. + 0x1F + + + + + + + 4 + 0x8 + 0,1,2,3 + TCCR%s + Timer Compare Capture Register + 0x60C + 32 + read-write + 0 + 0xFFFFFFFF + + + TCC + Timer Capture Compare + 0 + 32 + read-write + + + + + + + ENET2 + Ethernet MAC-NET Core + ENET + ENET2_ + 0x402D4000 + + 0 + 0x628 + registers + + + ENET2 + 152 + + + ENET2_1588_Timer + 153 + + + + USB1 + USB + USB + USB_ + USB + 0x402E0000 + + 0 + 0x1E0 + registers + + + USB_OTG1 + 113 + + + + ID + Identification register + 0 + 32 + read-only + 0xE4A1FA05 + 0xFFFFFFFF + + + ID + Configuration number + 0 + 6 + read-only + + + NID + Complement version of ID + 8 + 6 + read-only + + + REVISION + Revision number of the controller core. + 16 + 8 + read-only + + + + + HWGENERAL + Hardware General + 0x4 + 32 + read-only + 0x35 + 0xFFFFFFFF + + + PHYW + Data width of the transciever connected to the controller core. PHYW bit reset value is + 4 + 2 + read-only + + + PHYW_0 + 8 bit wide data bus Software non-programmable + 0 + + + PHYW_1 + 16 bit wide data bus Software non-programmable + 0x1 + + + PHYW_2 + Reset to 8 bit wide data bus Software programmable + 0x2 + + + PHYW_3 + Reset to 16 bit wide data bus Software programmable + 0x3 + + + + + PHYM + Transciever type + 6 + 3 + read-only + + + PHYM_0 + UTMI/UMTI+ + 0 + + + PHYM_1 + ULPI DDR + 0x1 + + + PHYM_2 + ULPI + 0x2 + + + PHYM_3 + Serial Only + 0x3 + + + PHYM_4 + Software programmable - reset to UTMI/UTMI+ + 0x4 + + + PHYM_5 + Software programmable - reset to ULPI DDR + 0x5 + + + PHYM_6 + Software programmable - reset to ULPI + 0x6 + + + PHYM_7 + Software programmable - reset to Serial + 0x7 + + + + + SM + Serial interface mode capability + 9 + 2 + read-only + + + SM_0 + No Serial Engine, always use parallel signalling. + 0 + + + SM_1 + Serial Engine present, always use serial signalling for FS/LS. + 0x1 + + + SM_2 + Software programmable - Reset to use parallel signalling for FS/LS + 0x2 + + + SM_3 + Software programmable - Reset to use serial signalling for FS/LS + 0x3 + + + + + + + HWHOST + Host Hardware Parameters + 0x8 + 32 + read-only + 0x10020001 + 0xFFFFFFFF + + + HC + Host Capable. Indicating whether host operation mode is supported or not. + 0 + 1 + read-only + + + HC_0 + Not supported + 0 + + + HC_1 + Supported + 0x1 + + + + + NPORT + The Nmber of downstream ports supported by the host controller is (NPORT+1) + 1 + 3 + read-only + + + + + HWDEVICE + Device Hardware Parameters + 0xC + 32 + read-only + 0x11 + 0xFFFFFFFF + + + DC + Device Capable. Indicating whether device operation mode is supported or not. + 0 + 1 + read-only + + + DC_0 + Not supported + 0 + + + DC_1 + Supported + 0x1 + + + + + DEVEP + Device Endpoint Number + 1 + 5 + read-only + + + + + HWTXBUF + TX Buffer Hardware Parameters + 0x10 + 32 + read-only + 0x80080B08 + 0xFFFFFFFF + + + TXBURST + Default burst size for memory to TX buffer transfer + 0 + 8 + read-only + + + TXCHANADD + TX FIFO Buffer size is: (2^TXCHANADD) * 4 Bytes + 16 + 8 + read-only + + + + + HWRXBUF + RX Buffer Hardware Parameters + 0x14 + 32 + read-only + 0x808 + 0xFFFFFFFF + + + RXBURST + Default burst size for memory to RX buffer transfer + 0 + 8 + read-only + + + RXADD + Buffer total size for all receive endpoints is (2^RXADD) + 8 + 8 + read-only + + + + + GPTIMER0LD + General Purpose Timer #0 Load + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTLD + General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b' + 0 + 24 + read-write + + + + + GPTIMER0CTRL + General Purpose Timer #0 Controller + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTCNT + General Purpose Timer Counter. This field is the count value of the countdown timer. + 0 + 24 + read-write + + + GPTMODE + General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software; In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the counter value from GPTLD bits to start again + 24 + 1 + read-write + + + GPTMODE_0 + One Shot Mode + 0 + + + GPTMODE_1 + Repeat Mode + 0x1 + + + + + GPTRST + General Purpose Timer Reset + 30 + 1 + read-write + + + GPTRST_0 + No action + 0 + + + GPTRST_1 + Load counter value from GPTLD bits in n_GPTIMER0LD + 0x1 + + + + + GPTRUN + General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. + 31 + 1 + read-write + + + GPTRUN_0 + Stop counting + 0 + + + GPTRUN_1 + Run + 0x1 + + + + + + + GPTIMER1LD + General Purpose Timer #1 Load + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTLD + General Purpose Timer Load Value These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b' + 0 + 24 + read-write + + + + + GPTIMER1CTRL + General Purpose Timer #1 Controller + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + GPTCNT + General Purpose Timer Counter. This field is the count value of the countdown timer. + 0 + 24 + read-write + + + GPTMODE + General Purpose Timer Mode In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is reset by software + 24 + 1 + read-write + + + GPTMODE_0 + One Shot Mode + 0 + + + GPTMODE_1 + Repeat Mode + 0x1 + + + + + GPTRST + General Purpose Timer Reset + 30 + 1 + read-write + + + GPTRST_0 + No action + 0 + + + GPTRST_1 + Load counter value from GPTLD bits in USB_n_GPTIMER0LD + 0x1 + + + + + GPTRUN + General Purpose Timer Run GPTCNT bits are not effected when setting or clearing this bit. + 31 + 1 + read-write + + + GPTRUN_0 + Stop counting + 0 + + + GPTRUN_1 + Run + 0x1 + + + + + + + SBUSCFG + System Bus Config + 0x90 + 32 + read-write + 0x2 + 0xFFFFFFFF + + + AHBBRST + AHB master interface Burst configuration These bits control AHB master transfer type sequence (or priority) + 0 + 3 + read-write + + + AHBBRST_0 + Incremental burst of unspecified length only + 0 + + + AHBBRST_1 + INCR4 burst, then single transfer + 0x1 + + + AHBBRST_2 + INCR8 burst, INCR4 burst, then single transfer + 0x2 + + + AHBBRST_3 + INCR16 burst, INCR8 burst, INCR4 burst, then single transfer + 0x3 + + + AHBBRST_5 + INCR4 burst, then incremental burst of unspecified length + 0x5 + + + AHBBRST_6 + INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0x6 + + + AHBBRST_7 + INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length + 0x7 + + + + + + + CAPLENGTH + Capability Registers Length + 0x100 + 8 + read-only + 0x40 + 0xFF + + + CAPLENGTH + These bits are used as an offset to add to register base to find the beginning of the Operational Register + 0 + 8 + read-only + + + + + HCIVERSION + Host Controller Interface Version + 0x102 + 16 + read-only + 0x100 + 0xFFFF + + + HCIVERSION + Host Controller Interface Version Number Default value is '10h', which means EHCI rev1.0. + 0 + 16 + read-only + + + + + HCSPARAMS + Host Controller Structural Parameters + 0x104 + 32 + read-only + 0x10011 + 0xFFFFFFFF + + + N_PORTS + Number of downstream ports + 0 + 4 + read-only + + + PPC + Port Power Control This field indicates whether the host controller implementation includes port power control + 4 + 1 + read-only + + + N_PCC + Number of Ports per Companion Controller This field indicates the number of ports supported per internal Companion Controller + 8 + 4 + read-only + + + N_CC + Number of Companion Controller (N_CC) + 12 + 4 + read-only + + + N_CC_0 + There is no internal Companion Controller and port-ownership hand-off is not supported. + 0 + + + N_CC_1 + There are internal companion controller(s) and port-ownership hand-offs is supported. + 0x1 + + + + + PI + Port Indicators (P INDICATOR) This bit indicates whether the ports support port indicator control + 16 + 1 + read-only + + + N_PTT + Number of Ports per Transaction Translator (N_PTT) + 20 + 4 + read-only + + + N_TT + Number of Transaction Translators (N_TT) + 24 + 4 + read-only + + + + + HCCPARAMS + Host Controller Capability Parameters + 0x108 + 32 + read-only + 0x6 + 0xFFFFFFFF + + + ADC + 64-bit Addressing Capability This bit is set '0b' in all controller core, no 64-bit addressing capability is supported + 0 + 1 + read-only + + + PFL + Programmable Frame List Flag If this bit is set to zero, then the system software must use a frame list length of 1024 elements with this host controller + 1 + 1 + read-only + + + ASP + Asynchronous Schedule Park Capability If this bit is set to a one, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule + 2 + 1 + read-only + + + IST + Isochronous Scheduling Threshold + 4 + 4 + read-only + + + EECP + EHCI Extended Capabilities Pointer + 8 + 8 + read-only + + + + + DCIVERSION + Device Controller Interface Version + 0x120 + 16 + read-only + 0x1 + 0xFFFF + + + DCIVERSION + Device Controller Interface Version Number Default value is '01h', which means rev0.1. + 0 + 16 + read-only + + + + + DCCPARAMS + Device Controller Capability Parameters + 0x124 + 32 + read-only + 0x188 + 0xFFFFFFFF + + + DEN + Device Endpoint Number This field indicates the number of endpoints built into the device controller + 0 + 5 + read-only + + + DC + Device Capable When this bit is 1, this controller is capable of operating as a USB 2.0 device. + 7 + 1 + read-only + + + HC + Host Capable When this bit is 1, this controller is capable of operating as an EHCI compatible USB 2 + 8 + 1 + read-only + + + + + USBCMD + USB Command Register + 0x140 + 32 + read-write + 0x80000 + 0xFFFFFFFF + + + RS + Run/Stop (RS) - Read/Write + 0 + 1 + read-write + + + RST + Controller Reset (RESET) - Read/Write + 1 + 1 + read-write + + + FS_1 + See description at bit 15 + 2 + 2 + read-write + + + PSE + Periodic Schedule Enable- Read/Write + 4 + 1 + read-write + + + PSE_0 + Do not process the Periodic Schedule + 0 + + + PSE_1 + Use the PERIODICLISTBASE register to access the Periodic Schedule. + 0x1 + + + + + ASE + Asynchronous Schedule Enable - Read/Write + 5 + 1 + read-write + + + ASE_0 + Do not process the Asynchronous Schedule. + 0 + + + ASE_1 + Use the ASYNCLISTADDR register to access the Asynchronous Schedule. + 0x1 + + + + + IAA + Interrupt on Async Advance Doorbell - Read/Write + 6 + 1 + read-write + + + ASP + Asynchronous Schedule Park Mode Count - Read/Write + 8 + 2 + read-write + + + ASPE + Asynchronous Schedule Park Mode Enable - Read/Write + 11 + 1 + read-write + + + ATDTW + Add dTD TripWire - Read/Write + 12 + 1 + read-write + + + SUTW + Setup TripWire - Read/Write + 13 + 1 + read-write + + + FS_2 + See also bits 3-2 Frame List Size - (Read/Write or Read Only) + 15 + 1 + read-write + + + FS_2_0 + 1024 elements (4096 bytes) Default value + 0 + + + FS_2_1 + 512 elements (2048 bytes) + 0x1 + + + + + ITC + Interrupt Threshold Control -Read/Write + 16 + 8 + read-write + + + ITC_0 + Immediate (no threshold) + 0 + + + ITC_1 + 1 micro-frame + 0x1 + + + ITC_2 + 2 micro-frames + 0x2 + + + ITC_4 + 4 micro-frames + 0x4 + + + ITC_8 + 8 micro-frames + 0x8 + + + ITC_16 + 16 micro-frames + 0x10 + + + ITC_32 + 32 micro-frames + 0x20 + + + ITC_64 + 64 micro-frames + 0x40 + + + + + + + USBSTS + USB Status Register + 0x144 + 32 + read-write + 0 + 0xFFFFFFFF + + + UI + USB Interrupt (USBINT) - R/WC + 0 + 1 + read-write + + + UEI + USB Error Interrupt (USBERRINT) - R/WC + 1 + 1 + read-write + + + PCI + Port Change Detect - R/WC + 2 + 1 + read-write + + + FRI + Frame List Rollover - R/WC + 3 + 1 + read-write + + + SEI + System Error- R/WC + 4 + 1 + read-write + + + AAI + Interrupt on Async Advance - R/WC + 5 + 1 + read-write + + + URI + USB Reset Received - R/WC + 6 + 1 + read-write + + + SRI + SOF Received - R/WC + 7 + 1 + read-write + + + SLI + DCSuspend - R/WC + 8 + 1 + read-write + + + ULPII + ULPI Interrupt - R/WC + 10 + 1 + read-write + + + HCH + HCHaIted - Read Only + 12 + 1 + read-write + + + RCL + Reclamation - Read Only + 13 + 1 + read-write + + + PS + Periodic Schedule Status - Read Only + 14 + 1 + read-write + + + AS + Asynchronous Schedule Status - Read Only + 15 + 1 + read-write + + + NAKI + NAK Interrupt Bit--RO + 16 + 1 + read-only + + + TI0 + General Purpose Timer Interrupt 0(GPTINT0)--R/WC + 24 + 1 + read-write + + + TI1 + General Purpose Timer Interrupt 1(GPTINT1)--R/WC + 25 + 1 + read-write + + + + + USBINTR + Interrupt Enable Register + 0x148 + 32 + read-write + 0 + 0xFFFFFFFF + + + UE + USB Interrupt Enable When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt + 0 + 1 + read-write + + + UEE + USB Error Interrupt Enable When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt + 1 + 1 + read-write + + + PCE + Port Change Detect Interrupt Enable When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt + 2 + 1 + read-write + + + FRE + Frame List Rollover Interrupt Enable When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt + 3 + 1 + read-write + + + SEE + System Error Interrupt Enable When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt + 4 + 1 + read-write + + + AAE + Async Advance Interrupt Enable When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt + 5 + 1 + read-write + + + URE + USB Reset Interrupt Enable When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt + 6 + 1 + read-write + + + SRE + SOF Received Interrupt Enable When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt + 7 + 1 + read-write + + + SLE + Sleep Interrupt Enable When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt + 8 + 1 + read-write + + + ULPIE + ULPI Interrupt Enable When this bit is one and the UPLII bit in n_USBSTS register is a one the controller will issue an interrupt + 10 + 1 + read-write + + + NAKE + NAK Interrupt Enable When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt + 16 + 1 + read-write + + + UAIE + USB Host Asynchronous Interrupt Enable When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold + 18 + 1 + read-write + + + UPIE + USB Host Periodic Interrupt Enable When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an interrupt at the next interrupt threshold + 19 + 1 + read-write + + + TIE0 + General Purpose Timer #0 Interrupt Enable When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt + 24 + 1 + read-write + + + TIE1 + General Purpose Timer #1 Interrupt Enable When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt + 25 + 1 + read-write + + + + + FRINDEX + USB Frame Index + 0x14C + 32 + read-write + 0 + 0xFFFFFFFF + + + FRINDEX + Frame Index + 0 + 14 + read-write + + + FRINDEX_0 + (1024) 12 + 0 + + + FRINDEX_1 + (512) 11 + 0x1 + + + FRINDEX_2 + (256) 10 + 0x2 + + + FRINDEX_3 + (128) 9 + 0x3 + + + FRINDEX_4 + (64) 8 + 0x4 + + + FRINDEX_5 + (32) 7 + 0x5 + + + FRINDEX_6 + (16) 6 + 0x6 + + + FRINDEX_7 + (8) 5 + 0x7 + + + + + + + DEVICEADDR + Device Address + DEVICEADDR_PERIODICLISTBASE + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + USBADRA + Device Address Advance + 24 + 1 + read-write + + + USBADR + Device Address. These bits correspond to the USB device address + 25 + 7 + read-write + + + + + PERIODICLISTBASE + Frame List Base Address + DEVICEADDR_PERIODICLISTBASE + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + BASEADR + Base Address (Low) + 12 + 20 + read-write + + + + + ASYNCLISTADDR + Next Asynch. Address + ASYNCLISTADDR_ENDPTLISTADDR + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + ASYBASE + Link Pointer Low (LPL) + 5 + 27 + read-write + + + + + ENDPTLISTADDR + Endpoint List Address + ASYNCLISTADDR_ENDPTLISTADDR + 0x158 + 32 + read-write + 0 + 0xFFFFFFFF + + + EPBASE + Endpoint List Pointer(Low) + 11 + 21 + read-write + + + + + BURSTSIZE + Programmable Burst Size + 0x160 + 32 + read-write + 0x808 + 0xFFFFFFFF + + + RXPBURST + Programmable RX Burst Size + 0 + 8 + read-write + + + TXPBURST + Programmable TX Burst Size + 8 + 9 + read-write + + + + + TXFILLTUNING + TX FIFO Fill Tuning + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXSCHOH + Scheduler Overhead + 0 + 8 + read-write + + + TXSCHHEALTH + Scheduler Health Counter + 8 + 5 + read-write + + + TXFIFOTHRES + FIFO Burst Threshold + 16 + 6 + read-write + + + + + ENDPTNAK + Endpoint NAK + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + EPRN + RX Endpoint NAK - R/WC + 0 + 8 + read-write + + + EPTN + TX Endpoint NAK - R/WC + 16 + 8 + read-write + + + + + ENDPTNAKEN + Endpoint NAK Enable + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + EPRNE + RX Endpoint NAK Enable - R/W + 0 + 8 + read-write + + + EPTNE + TX Endpoint NAK Enable - R/W + 16 + 8 + read-write + + + + + CONFIGFLAG + Configure Flag Register + 0x180 + 32 + read-only + 0x1 + 0xFFFFFFFF + + + CF + Configure Flag Host software sets this bit as the last action in its process of configuring the Host Controller + 0 + 1 + read-only + + + CF_0 + Port routing control logic default-routes each port to an implementation dependent classic host controller. + 0 + + + CF_1 + Port routing control logic default-routes all ports to this host controller. + 0x1 + + + + + + + PORTSC1 + Port Status & Control + 0x184 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + CCS + Current Connect Status-Read Only + 0 + 1 + read-only + + + CSC + Connect Status Change-R/WC + 1 + 1 + read-write + + + PE + Port Enabled/Disabled-Read/Write + 2 + 1 + read-write + + + PEC + Port Enable/Disable Change-R/WC + 3 + 1 + read-write + + + OCA + Over-current Active-Read Only + 4 + 1 + read-only + + + OCA_0 + This port does not have an over-current condition. + 0 + + + OCA_1 + This port currently has an over-current condition + 0x1 + + + + + OCC + Over-current Change-R/WC + 5 + 1 + read-write + + + FPR + Force Port Resume -Read/Write + 6 + 1 + read-write + + + SUSP + Suspend - Read/Write or Read Only + 7 + 1 + read-write + + + PR + Port Reset - Read/Write or Read Only + 8 + 1 + read-write + + + HSP + High-Speed Port - Read Only + 9 + 1 + read-only + + + LS + Line Status-Read Only + 10 + 2 + read-write + + + LS_0 + SE0 + 0 + + + LS_1 + K-state + 0x1 + + + LS_2 + J-state + 0x2 + + + LS_3 + Undefined + 0x3 + + + + + PP + Port Power (PP)-Read/Write or Read Only + 12 + 1 + read-write + + + PO + Port Owner-Read/Write + 13 + 1 + read-write + + + PIC + Port Indicator Control - Read/Write + 14 + 2 + read-write + + + PIC_0 + Port indicators are off + 0 + + + PIC_1 + Amber + 0x1 + + + PIC_2 + Green + 0x2 + + + PIC_3 + Undefined + 0x3 + + + + + PTC + Port Test Control - Read/Write + 16 + 4 + read-write + + + PTC_0 + TEST_MODE_DISABLE + 0 + + + PTC_1 + J_STATE + 0x1 + + + PTC_2 + K_STATE + 0x2 + + + PTC_3 + SE0 (host) / NAK (device) + 0x3 + + + PTC_4 + Packet + 0x4 + + + PTC_5 + FORCE_ENABLE_HS + 0x5 + + + PTC_6 + FORCE_ENABLE_FS + 0x6 + + + PTC_7 + FORCE_ENABLE_LS + 0x7 + + + + + WKCN + Wake on Connect Enable (WKCNNT_E) - Read/Write + 20 + 1 + read-write + + + WKDC + Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write + 21 + 1 + read-write + + + WKOC + Wake on Over-current Enable (WKOC_E) - Read/Write + 22 + 1 + read-write + + + PHCD + PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write + 23 + 1 + read-write + + + PHCD_0 + Enable PHY clock + 0 + + + PHCD_1 + Disable PHY clock + 0x1 + + + + + PFSC + Port Force Full Speed Connect - Read/Write + 24 + 1 + read-write + + + PFSC_0 + Normal operation + 0 + + + PFSC_1 + Forced to full speed + 0x1 + + + + + PTS_2 + See description at bits 31-30 + 25 + 1 + read-write + + + PSPD + Port Speed - Read Only. This register field indicates the speed at which the port is operating. + 26 + 2 + read-write + + + PSPD_0 + Full Speed + 0 + + + PSPD_1 + Low Speed + 0x1 + + + PSPD_2 + High Speed + 0x2 + + + PSPD_3 + Undefined + 0x3 + + + + + PTW + Parallel Transceiver Width This bit has no effect if serial interface engine is used + 28 + 1 + read-write + + + PTW_0 + Select the 8-bit UTMI interface [60MHz] + 0 + + + PTW_1 + Select the 16-bit UTMI interface [30MHz] + 0x1 + + + + + STS + Serial Transceiver Select 1 Serial Interface Engine is selected 0 Parallel Interface signals is selected Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals + 29 + 1 + read-write + + + PTS_1 + All USB port interface modes are listed in this field description, but not all are supported + 30 + 2 + read-write + + + + + OTGSC + On-The-Go Status & control + 0x1A4 + 32 + read-write + 0x1120 + 0xFFFFFFFF + + + VD + VBUS_Discharge - Read/Write. Setting this bit causes VBus to discharge through a resistor. + 0 + 1 + read-write + + + VC + VBUS Charge - Read/Write + 1 + 1 + read-write + + + OT + OTG Termination - Read/Write + 3 + 1 + read-write + + + DP + Data Pulsing - Read/Write + 4 + 1 + read-write + + + IDPU + ID Pullup - Read/Write This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default] + 5 + 1 + read-write + + + ID + USB ID - Read Only. 0 = A device, 1 = B device + 8 + 1 + read-only + + + AVV + A VBus Valid - Read Only. Indicates VBus is above the A VBus valid threshold. + 9 + 1 + read-only + + + ASV + A Session Valid - Read Only. Indicates VBus is above the A session valid threshold. + 10 + 1 + read-only + + + BSV + B Session Valid - Read Only. Indicates VBus is above the B session valid threshold. + 11 + 1 + read-only + + + BSE + B Session End - Read Only. Indicates VBus is below the B session end threshold. + 12 + 1 + read-only + + + TOG_1MS + 1 millisecond timer toggle - Read Only. This bit toggles once per millisecond. + 13 + 1 + read-only + + + DPS + Data Bus Pulsing Status - Read Only + 14 + 1 + read-only + + + IDIS + USB ID Interrupt Status - Read/Write + 16 + 1 + read-write + + + AVVIS + A VBus Valid Interrupt Status - Read/Write to Clear + 17 + 1 + read-write + + + ASVIS + A Session Valid Interrupt Status - Read/Write to Clear + 18 + 1 + read-write + + + BSVIS + B Session Valid Interrupt Status - Read/Write to Clear + 19 + 1 + read-write + + + BSEIS + B Session End Interrupt Status - Read/Write to Clear + 20 + 1 + read-write + + + STATUS_1MS + 1 millisecond timer Interrupt Status - Read/Write to Clear + 21 + 1 + read-write + + + DPIS + Data Pulse Interrupt Status - Read/Write to Clear + 22 + 1 + read-write + + + IDIE + USB ID Interrupt Enable - Read/Write. Setting this bit enables the USB ID interrupt. + 24 + 1 + read-write + + + AVVIE + A VBus Valid Interrupt Enable - Read/Write. Setting this bit enables the A VBus valid interrupt. + 25 + 1 + read-write + + + ASVIE + A Session Valid Interrupt Enable - Read/Write + 26 + 1 + read-write + + + BSVIE + B Session Valid Interrupt Enable - Read/Write + 27 + 1 + read-write + + + BSEIE + B Session End Interrupt Enable - Read/Write. Setting this bit enables the B session end interrupt. + 28 + 1 + read-write + + + EN_1MS + 1 millisecond timer Interrupt Enable - Read/Write + 29 + 1 + read-write + + + DPIE + Data Pulse Interrupt Enable + 30 + 1 + read-write + + + + + USBMODE + USB Device Mode + 0x1A8 + 32 + read-write + 0x5000 + 0xFFFFFFFF + + + CM + Controller Mode - R/WO + 0 + 2 + read-write + + + CM_0 + Idle [Default for combination host/device] + 0 + + + CM_2 + Device Controller [Default for device only controller] + 0x2 + + + CM_3 + Host Controller [Default for host only controller] + 0x3 + + + + + ES + Endian Select - Read/Write + 2 + 1 + read-write + + + ES_0 + Little Endian [Default] + 0 + + + ES_1 + Big Endian + 0x1 + + + + + SLOM + Setup Lockout Mode + 3 + 1 + read-write + + + SLOM_0 + Setup Lockouts On (default); + 0 + + + SLOM_1 + Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register . + 0x1 + + + + + SDIS + Stream Disable Mode + 4 + 1 + read-write + + + + + ENDPTSETUPSTAT + Endpoint Setup Status + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + ENDPTSETUPSTAT + Setup Endpoint Status + 0 + 16 + read-write + + + + + ENDPTPRIME + Endpoint Prime + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + PERB + Prime Endpoint Receive Buffer - R/WS + 0 + 8 + read-write + + + PETB + Prime Endpoint Transmit Buffer - R/WS + 16 + 8 + read-write + + + + + ENDPTFLUSH + Endpoint Flush + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + FERB + Flush Endpoint Receive Buffer - R/WS + 0 + 8 + read-write + + + FETB + Flush Endpoint Transmit Buffer - R/WS + 16 + 8 + read-write + + + + + ENDPTSTAT + Endpoint Status + 0x1B8 + 32 + read-only + 0 + 0xFFFFFFFF + + + ERBR + Endpoint Receive Buffer Ready -- Read Only + 0 + 8 + read-only + + + ETBR + Endpoint Transmit Buffer Ready -- Read Only + 16 + 8 + read-only + + + + + ENDPTCOMPLETE + Endpoint Complete + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + ERCE + Endpoint Receive Complete Event - RW/C + 0 + 8 + read-write + + + ETCE + Endpoint Transmit Complete Event - R/WC + 16 + 8 + read-write + + + + + ENDPTCTRL0 + Endpoint Control0 + 0x1C0 + 32 + read-write + 0x800080 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control Endpoint0 is fixed as a Control End Point. + 2 + 2 + read-write + + + RXE + RX Endpoint Enable 1 Enabled Endpoint0 is always enabled. + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK [Default] 1 End Point Stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host + 16 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 - Control Endpoint0 is fixed as a Control End Point. + 18 + 2 + read-write + + + TXE + TX Endpoint Enable 1 Enabled Endpoint0 is always enabled. + 23 + 1 + read-write + + + + + ENDPTCTRL1 + Endpoint Control 1 + 0x1C4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL2 + Endpoint Control 2 + 0x1C8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL3 + Endpoint Control 3 + 0x1CC + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL4 + Endpoint Control 4 + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL5 + Endpoint Control 5 + 0x1D4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL6 + Endpoint Control 6 + 0x1D8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + ENDPTCTRL7 + Endpoint Control 7 + 0x1DC + 32 + read-write + 0 + 0xFFFFFFFF + + + RXS + RX Endpoint Stall - Read/Write 0 End Point OK + 0 + 1 + read-write + + + RXD + RX Endpoint Data Sink - Read/Write 0 Dual Port Memory Buffer/DMA Engine [Default] Should always be written as zero + 1 + 1 + read-write + + + RXT + RX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 2 + 2 + read-write + + + RXI + RX Data Toggle Inhibit 0 Disabled [Default] 1 Enabled This bit is only used for test and should always be written as zero + 5 + 1 + read-write + + + RXR + RX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the host and device + 6 + 1 + read-write + + + RXE + RX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 7 + 1 + read-write + + + TXS + TX Endpoint Stall - Read/Write 0 End Point OK 1 End Point Stalled This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared + 16 + 1 + read-write + + + TXD + TX Endpoint Data Source - Read/Write 0 Dual Port Memory Buffer/DMA Engine [DEFAULT] Should always be written as 0 + 17 + 1 + read-write + + + TXT + TX Endpoint Type - Read/Write 00 Control 01 Isochronous 10 Bulk 11 Interrupt + 18 + 2 + read-write + + + TXI + TX Data Toggle Inhibit 0 PID Sequencing Enabled + 21 + 1 + read-write + + + TXR + TX Data Toggle Reset (WS) Write 1 - Reset PID Sequence Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order to synchronize the data PID's between the Host and device + 22 + 1 + read-write + + + TXE + TX Endpoint Enable 0 Disabled [Default] 1 Enabled An Endpoint should be enabled only after it has been configured + 23 + 1 + read-write + + + + + + + USB2 + USB + USB + USB_ + 0x402E0200 + + 0 + 0x1E0 + registers + + + USB_OTG2 + 112 + + + + USBNC1 + USB + USB1 + USBNC + USBNC_ + USBNC + 0x402E0000 + + 0 + 0x81C + registers + + + + USB_OTG1_CTRL + USB OTG1 Control Register + 0x800 + 32 + read-write + 0x30001000 + 0xFFFFFFFF + + + OVER_CUR_DIS + Disable OTG1 Overcurrent Detection + 7 + 1 + read-write + + + OVER_CUR_DIS_0 + Enables overcurrent detection + 0 + + + OVER_CUR_DIS_1 + Disables overcurrent detection + 0x1 + + + + + OVER_CUR_POL + OTG1 Polarity of Overcurrent The polarity of OTG1 port overcurrent event + 8 + 1 + read-write + + + OVER_CUR_POL_0 + High active (high on this signal represents an overcurrent condition) + 0 + + + OVER_CUR_POL_1 + Low active (low on this signal represents an overcurrent condition) + 0x1 + + + + + PWR_POL + OTG1 Power Polarity This bit should be set according to PMIC Power Pin polarity. + 9 + 1 + read-write + + + PWR_POL_0 + PMIC Power Pin is Low active. + 0 + + + PWR_POL_1 + PMIC Power Pin is High active. + 0x1 + + + + + WIE + OTG1 Wake-up Interrupt Enable This bit enables or disables the OTG1 wake-up interrupt + 10 + 1 + read-write + + + WIE_0 + Interrupt Disabled + 0 + + + WIE_1 + Interrupt Enabled + 0x1 + + + + + WKUP_SW_EN + OTG1 Software Wake-up Enable + 14 + 1 + read-write + + + WKUP_SW_EN_0 + Disable + 0 + + + WKUP_SW_EN_1 + Enable + 0x1 + + + + + WKUP_SW + OTG1 Software Wake-up + 15 + 1 + read-write + + + WKUP_SW_0 + Inactive + 0 + + + WKUP_SW_1 + Force wake-up + 0x1 + + + + + WKUP_ID_EN + OTG1 Wake-up on ID change enable + 16 + 1 + read-write + + + WKUP_ID_EN_0 + Disable + 0 + + + WKUP_ID_EN_1 + Enable + 0x1 + + + + + WKUP_VBUS_EN + OTG1 wake-up on VBUS change enable + 17 + 1 + read-write + + + WKUP_VBUS_EN_0 + Disable + 0 + + + WKUP_VBUS_EN_1 + Enable + 0x1 + + + + + WKUP_DPDM_EN + Wake-up on DPDM change enable + 29 + 1 + read-write + + + WKUP_DPDM_EN_0 + DPDM changes wake-up to be disabled only when VBUS is 0. + 0 + + + WKUP_DPDM_EN_1 + (Default) DPDM changes wake-up to be enabled, it is for device only. + 0x1 + + + + + WIR + OTG1 Wake-up Interrupt Request This bit indicates that a wake-up interrupt request is received on the OTG1 port + 31 + 1 + read-only + + + WIR_0 + No wake-up interrupt request received + 0 + + + WIR_1 + Wake-up Interrupt Request received + 0x1 + + + + + + + USB_OTG1_PHY_CTRL_0 + OTG1 UTMI PHY Control 0 Register + 0x818 + 32 + read-write + 0 + 0xFFFFFFFF + + + UTMI_CLK_VLD + Indicating whether OTG1 UTMI PHY clock is valid + 31 + 1 + read-write + + + UTMI_CLK_VLD_0 + Invalid + 0 + + + UTMI_CLK_VLD_1 + Valid + 0x1 + + + + + + + + + USBNC2 + USB + USBNC + USBNC_ + 0x402E0004 + + 0 + 0x81C + registers + + + + SEMC + SEMC + SEMC + 0x402F0000 + + 0 + 0x100 + registers + + + SEMC + 109 + + + + MCR + Module Control Register + 0 + 32 + read-write + 0x10000002 + 0xFFFFFFFF + + + SWRST + Software Reset + 0 + 1 + read-write + + + MDIS + Module Disable + 1 + 1 + read-write + + + MDIS_0 + Module enabled + 0 + + + MDIS_1 + Module disabled. + 0x1 + + + + + DQSMD + DQS (read strobe) mode + 2 + 1 + read-write + + + DQSMD_0 + Dummy read strobe loopbacked internally + 0 + + + DQSMD_1 + Dummy read strobe loopbacked from DQS pad or DLL delay chain. Details information at descriptions of DQSSEL bit. + 0x1 + + + + + WPOL0 + WAIT/RDY# polarity for NOR/PSRAM + 6 + 1 + read-write + + + WPOL0_0 + Low active + 0 + + + WPOL0_1 + High active + 0x1 + + + + + WPOL1 + WAIT/RDY# polarity for NAND + 7 + 1 + read-write + + + WPOL1_0 + Low active + 0 + + + WPOL1_1 + High active + 0x1 + + + + + DQSSEL + Select DQS source when DQSMD and DLLSEL both set. + 10 + 1 + read-write + + + DQSSEL_0 + SDRAM/NOR/SRAM read clock source is from DQS pad in synchronous mode. + 0 + + + DQSSEL_1 + SDRAM/NOR/SRAM read clock source is from DLL delay chain in synchronous mode. + 0x1 + + + + + DLLSEL + Select DLL delay chain clock input. + 11 + 1 + read-write + + + DLLSEL_0 + DLL delay chain clock input is from NAND device's DQS pad. For NAND synchronous mode only. + 0 + + + DLLSEL_1 + DLL delay chain clock input is from internal clock. For SDRAM, NOR and SRAM synchronous mode only. + 0x1 + + + + + CTO + Command Execution timeout cycles + 16 + 8 + read-write + + + BTO + Bus timeout cycles + 24 + 5 + read-write + + + BTO_0 + 255*1 + 0 + + + BTO_1 + 255*2 - 255*2^30 + 0x1 + + + BTO_2 + 255*2 - 255*2^30 + 0x2 + + + BTO_3 + 255*2 - 255*2^30 + 0x3 + + + BTO_4 + 255*2 - 255*2^30 + 0x4 + + + BTO_5 + 255*2 - 255*2^30 + 0x5 + + + BTO_6 + 255*2 - 255*2^30 + 0x6 + + + BTO_7 + 255*2 - 255*2^30 + 0x7 + + + BTO_8 + 255*2 - 255*2^30 + 0x8 + + + BTO_9 + 255*2 - 255*2^30 + 0x9 + + + BTO_31 + 255*2^31 + 0x1F + + + + + + + IOCR + IO Mux Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + MUX_A8 + SEMC_A8 output selection + 0 + 3 + read-write + + + MUX_A8_0 + SDRAM Address bit (A8) + 0 + + + MUX_A8_1 + NAND CE# + 0x1 + + + MUX_A8_2 + NOR CE# + 0x2 + + + MUX_A8_3 + PSRAM CE# + 0x3 + + + MUX_A8_4 + DBI CSX + 0x4 + + + MUX_A8_5 + SDRAM Address bit (A8) + 0x5 + + + MUX_A8_6 + SDRAM Address bit (A8) + 0x6 + + + MUX_A8_7 + SDRAM Address bit (A8) + 0x7 + + + + + MUX_CSX0 + SEMC_CSX0 output selection + 3 + 3 + read-write + + + MUX_CSX0_0 + NOR/PSRAM Address bit 24 (A24) + 0 + + + MUX_CSX0_1 + SDRAM CS1 + 0x1 + + + MUX_CSX0_2 + SDRAM CS2 + 0x2 + + + MUX_CSX0_3 + SDRAM CS3 + 0x3 + + + MUX_CSX0_4 + NAND CE# + 0x4 + + + MUX_CSX0_5 + NOR CE# + 0x5 + + + MUX_CSX0_6 + PSRAM CE# + 0x6 + + + MUX_CSX0_7 + DBI CSX + 0x7 + + + + + MUX_CSX1 + SEMC_CSX1 output selection + 6 + 3 + read-write + + + MUX_CSX1_0 + NOR/PSRAM Address bit 25 (A25) + 0 + + + MUX_CSX1_1 + SDRAM CS1 + 0x1 + + + MUX_CSX1_2 + SDRAM CS2 + 0x2 + + + MUX_CSX1_3 + SDRAM CS3 + 0x3 + + + MUX_CSX1_4 + NAND CE# + 0x4 + + + MUX_CSX1_5 + NOR CE# + 0x5 + + + MUX_CSX1_6 + PSRAM CE# + 0x6 + + + MUX_CSX1_7 + DBI CSX + 0x7 + + + + + MUX_CSX2 + SEMC_CSX2 output selection + 9 + 3 + read-write + + + MUX_CSX2_0 + NOR/PSRAM Address bit 26 (A26) + 0 + + + MUX_CSX2_1 + SDRAM CS1 + 0x1 + + + MUX_CSX2_2 + SDRAM CS2 + 0x2 + + + MUX_CSX2_3 + SDRAM CS3 + 0x3 + + + MUX_CSX2_4 + NAND CE# + 0x4 + + + MUX_CSX2_5 + NOR CE# + 0x5 + + + MUX_CSX2_6 + PSRAM CE# + 0x6 + + + MUX_CSX2_7 + DBI CSX + 0x7 + + + + + MUX_CSX3 + SEMC_CSX3 output selection + 12 + 3 + read-write + + + MUX_CSX3_0 + NOR/PSRAM Address bit 27 (A27) + 0 + + + MUX_CSX3_1 + SDRAM CS1 + 0x1 + + + MUX_CSX3_2 + SDRAM CS2 + 0x2 + + + MUX_CSX3_3 + SDRAM CS3 + 0x3 + + + MUX_CSX3_4 + NAND CE# + 0x4 + + + MUX_CSX3_5 + NOR CE# + 0x5 + + + MUX_CSX3_6 + PSRAM CE# + 0x6 + + + MUX_CSX3_7 + DBI CSX + 0x7 + + + + + MUX_RDY + SEMC_RDY function selection + 15 + 3 + read-write + + + MUX_RDY_0 + NAND Ready/Wait# input + 0 + + + MUX_RDY_1 + SDRAM CS1 + 0x1 + + + MUX_RDY_2 + SDRAM CS2 + 0x2 + + + MUX_RDY_3 + SDRAM CS3 + 0x3 + + + MUX_RDY_4 + NOR CE# + 0x4 + + + MUX_RDY_5 + PSRAM CE# + 0x5 + + + MUX_RDY_6 + DBI CSX + 0x6 + + + MUX_RDY_7 + NOR/PSRAM Address bit 27 + 0x7 + + + + + MUX_CLKX0 + SEMC_CLKX0 function selection + 24 + 1 + read-write + + + MUX_CLKX0_0 + NOR clock + 0 + + + MUX_CLKX0_1 + SRAM clock + 0x1 + + + + + MUX_CLKX1 + SEMC_CLKX1 function selection + 25 + 1 + read-write + + + MUX_CLKX1_0 + NOR clock + 0 + + + MUX_CLKX1_1 + SRAM clock + 0x1 + + + + + + + BMCR0 + Master Bus (AXI) Control Register 0 + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + WQOS + Weight of QoS + 0 + 4 + read-write + + + WAGE + Weight of Aging + 4 + 4 + read-write + + + WSH + Weight of Slave Hit (no read/write switch) + 8 + 8 + read-write + + + WRWS + Weight of Slave Hit (Read/Write switch) + 16 + 8 + read-write + + + + + BMCR1 + Master Bus (AXI) Control Register 1 + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + WQOS + Weight of QoS + 0 + 4 + read-write + + + WAGE + Weight of Aging + 4 + 4 + read-write + + + WPH + Weight of Page Hit + 8 + 8 + read-write + + + WRWS + Weight of Read/Write switch + 16 + 8 + read-write + + + WBR + Weight of Bank Rotation + 24 + 8 + read-write + + + + + BR0 + Base Register 0 (For SDRAM CS0 device) + 0x10 + 32 + read-write + 0x8000001D + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR1 + Base Register 1 (For SDRAM CS1 device) + 0x14 + 32 + read-write + 0x8400001C + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR2 + Base Register 2 (For SDRAM CS2 device) + 0x18 + 32 + read-write + 0x8800001C + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR3 + Base Register 3 (For SDRAM CS3 device) + 0x1C + 32 + read-write + 0x8C00001C + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR4 + Base Register 4 (For NAND device) + 0x20 + 32 + read-write + 0x9E00001A + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR5 + Base Register 5 (For NOR device) + 0x24 + 32 + read-write + 0x90000018 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR6 + Base Register 6 (For PSRAM device) + 0x28 + 32 + read-write + 0x98000018 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR7 + Base Register 7 (For DBI-B (MIPI Display Bus Interface Type B) device) + 0x2C + 32 + read-write + 0x9C00001A + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + BR8 + Base Register 8 (For NAND device) + 0x30 + 32 + read-write + 0x26 + 0xFFFFFFFF + + + VLD + Valid + 0 + 1 + read-write + + + MS + Memory size + 1 + 5 + read-write + + + MS_0 + 4KB + 0 + + + MS_1 + 8KB + 0x1 + + + MS_2 + 16KB + 0x2 + + + MS_3 + 32KB + 0x3 + + + MS_4 + 64KB + 0x4 + + + MS_5 + 128KB + 0x5 + + + MS_6 + 256KB + 0x6 + + + MS_7 + 512KB + 0x7 + + + MS_8 + 1MB + 0x8 + + + MS_9 + 2MB + 0x9 + + + MS_10 + 4MB + 0xA + + + MS_11 + 8MB + 0xB + + + MS_12 + 16MB + 0xC + + + MS_13 + 32MB + 0xD + + + MS_14 + 64MB + 0xE + + + MS_15 + 128MB + 0xF + + + MS_16 + 256MB + 0x10 + + + MS_17 + 512MB + 0x11 + + + MS_18 + 1GB + 0x12 + + + MS_19 + 2GB + 0x13 + + + MS_20 + 4GB + 0x14 + + + MS_21 + 4GB + 0x15 + + + MS_22 + 4GB + 0x16 + + + MS_23 + 4GB + 0x17 + + + MS_24 + 4GB + 0x18 + + + MS_25 + 4GB + 0x19 + + + MS_26 + 4GB + 0x1A + + + MS_27 + 4GB + 0x1B + + + MS_28 + 4GB + 0x1C + + + MS_29 + 4GB + 0x1D + + + MS_30 + 4GB + 0x1E + + + MS_31 + 4GB + 0x1F + + + + + BA + Base Address + 12 + 20 + read-write + + + + + DLLCR + DLL Control Register + 0x34 + 32 + read-write + 0x100 + 0xFFFFFFFF + + + DLLEN + DLL calibration enable. + 0 + 1 + read-write + + + DLLRESET + Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation). + 1 + 1 + read-write + + + SLVDLYTARGET + The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (ipgclock). + 3 + 4 + read-write + + + OVRDEN + Slave clock delay line delay cell number selection override enable. + 8 + 1 + read-write + + + OVRDVAL + Slave clock delay line delay cell number selection override value. + 9 + 6 + read-write + + + + + INTEN + Interrupt Enable Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + IPCMDDONEEN + IP command done interrupt enable + 0 + 1 + read-write + + + IPCMDERREN + IP command error interrupt enable + 1 + 1 + read-write + + + AXICMDERREN + AXI command error interrupt enable + 2 + 1 + read-write + + + AXIBUSERREN + AXI bus error interrupt enable + 3 + 1 + read-write + + + NDPAGEENDEN + This bit enable/disable the NDPAGEEND interrupt generation. + 4 + 1 + read-write + + + NDPAGEENDEN_0 + Disable + 0 + + + NDPAGEENDEN_1 + Enable + 0x1 + + + + + NDNOPENDEN + This bit enable/disable the NDNOPEND interrupt generation. + 5 + 1 + read-write + + + NDNOPENDEN_0 + Disable + 0 + + + NDNOPENDEN_1 + Enable + 0x1 + + + + + + + INTR + Interrupt Enable Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + IPCMDDONE + IP command normal done interrupt + 0 + 1 + read-write + oneToClear + + + IPCMDERR + IP command error done interrupt + 1 + 1 + read-write + oneToClear + + + AXICMDERR + AXI command error interrupt + 2 + 1 + read-write + oneToClear + + + AXIBUSERR + AXI bus error interrupt + 3 + 1 + read-write + oneToClear + + + NDPAGEEND + This interrupt is generated when the last address of one page in NAND device is written by AXI command + 4 + 1 + read-write + oneToClear + + + NDNOPEND + This interrupt is generated when all pending AXI write command to NAND is finished on NAND interface. + 5 + 1 + read-write + oneToClear + + + + + SDRAMCR0 + SDRAM control register 0 + 0x40 + 32 + read-write + 0xC26 + 0xFFFFFFFF + + + PS + Port Size + 0 + 1 + read-write + + + PS_0 + 8bit + 0 + + + PS_1 + 16bit + 0x1 + + + + + BL + Burst Length + 4 + 3 + read-write + + + BL_0 + 1 + 0 + + + BL_1 + 2 + 0x1 + + + BL_2 + 4 + 0x2 + + + BL_3 + 8 + 0x3 + + + BL_4 + 8 + 0x4 + + + BL_5 + 8 + 0x5 + + + BL_6 + 8 + 0x6 + + + BL_7 + 8 + 0x7 + + + + + COL8 + Column 8 selection bit + 7 + 1 + read-write + + + COL8_0 + Column address bit number is decided by COL field. + 0 + + + COL8_1 + Column address bit number is 8. COL field is ignored. + 0x1 + + + + + COL + Column address bit number + 8 + 2 + read-write + + + COL_0 + 12 bit + 0 + + + COL_1 + 11 bit + 0x1 + + + COL_2 + 10 bit + 0x2 + + + COL_3 + 9 bit + 0x3 + + + + + CL + CAS Latency + 10 + 2 + read-write + + + CL_0 + 1 + 0 + + + CL_1 + 1 + 0x1 + + + CL_2 + 2 + 0x2 + + + CL_3 + 3 + 0x3 + + + + + BANK2 + 2 Bank selection bit + 14 + 1 + read-write + + + BANK2_0 + SDRAM device has 4 banks. + 0 + + + BANK2_1 + SDRAM device has 2 banks. + 0x1 + + + + + + + SDRAMCR1 + SDRAM control register 1 + 0x44 + 32 + read-write + 0x994934 + 0xFFFFFFFF + + + PRE2ACT + PRECHARGE to ACT/Refresh wait time + 0 + 4 + read-write + + + ACT2RW + ACT to Read/Write wait time + 4 + 4 + read-write + + + RFRC + Refresh recovery time + 8 + 5 + read-write + + + WRC + Write recovery time + 13 + 3 + read-write + + + CKEOFF + CKE OFF minimum time + 16 + 4 + read-write + + + ACT2PRE + ACT to Precharge minimum time + 20 + 4 + read-write + + + + + SDRAMCR2 + SDRAM control register 2 + 0x48 + 32 + read-write + 0x80000EEE + 0xFFFFFFFF + + + SRRC + Self Refresh Recovery time + 0 + 8 + read-write + + + REF2REF + Refresh to Refresh wait time + 8 + 8 + read-write + + + ACT2ACT + ACT to ACT wait time + 16 + 8 + read-write + + + ITO + SDRAM Idle timeout + 24 + 8 + read-write + + + ITO_0 + IDLE timeout period is 256*Prescale period. + 0 + + + ITO_1 + IDLE timeout period is ITO*Prescale period. + 0x1 + + + ITO_2 + IDLE timeout period is ITO*Prescale period. + 0x2 + + + ITO_3 + IDLE timeout period is ITO*Prescale period. + 0x3 + + + ITO_4 + IDLE timeout period is ITO*Prescale period. + 0x4 + + + ITO_5 + IDLE timeout period is ITO*Prescale period. + 0x5 + + + ITO_6 + IDLE timeout period is ITO*Prescale period. + 0x6 + + + ITO_7 + IDLE timeout period is ITO*Prescale period. + 0x7 + + + ITO_8 + IDLE timeout period is ITO*Prescale period. + 0x8 + + + ITO_9 + IDLE timeout period is ITO*Prescale period. + 0x9 + + + + + + + SDRAMCR3 + SDRAM control register 3 + 0x4C + 32 + read-write + 0x40808000 + 0xFFFFFFFF + + + REN + Refresh enable + 0 + 1 + read-write + + + REBL + Refresh burst length + 1 + 3 + read-write + + + REBL_0 + 1 + 0 + + + REBL_1 + 2 + 0x1 + + + REBL_2 + 3 + 0x2 + + + REBL_3 + 4 + 0x3 + + + REBL_4 + 5 + 0x4 + + + REBL_5 + 6 + 0x5 + + + REBL_6 + 7 + 0x6 + + + REBL_7 + 8 + 0x7 + + + + + PRESCALE + Prescaler timer period + 8 + 8 + read-write + + + PRESCALE_0 + 256*16 cycle + 0 + + + PRESCALE_1 + PRESCALE*16 cycle + 0x1 + + + PRESCALE_2 + PRESCALE*16 cycle + 0x2 + + + PRESCALE_3 + PRESCALE*16 cycle + 0x3 + + + PRESCALE_4 + PRESCALE*16 cycle + 0x4 + + + PRESCALE_5 + PRESCALE*16 cycle + 0x5 + + + PRESCALE_6 + PRESCALE*16 cycle + 0x6 + + + PRESCALE_7 + PRESCALE*16 cycle + 0x7 + + + PRESCALE_8 + PRESCALE*16 cycle + 0x8 + + + PRESCALE_9 + PRESCALE*16 cycle + 0x9 + + + + + RT + Refresh timer period + 16 + 8 + read-write + + + RT_0 + 256*Prescaler period + 0 + + + RT_1 + RT*Prescaler period + 0x1 + + + RT_2 + RT*Prescaler period + 0x2 + + + RT_3 + RT*Prescaler period + 0x3 + + + RT_4 + RT*Prescaler period + 0x4 + + + RT_5 + RT*Prescaler period + 0x5 + + + RT_6 + RT*Prescaler period + 0x6 + + + RT_7 + RT*Prescaler period + 0x7 + + + RT_8 + RT*Prescaler period + 0x8 + + + RT_9 + RT*Prescaler period + 0x9 + + + + + UT + Refresh urgent threshold + 24 + 8 + read-write + + + UT_0 + 256*Prescaler period + 0 + + + UT_1 + UT*Prescaler period + 0x1 + + + UT_2 + UT*Prescaler period + 0x2 + + + UT_3 + UT*Prescaler period + 0x3 + + + UT_4 + UT*Prescaler period + 0x4 + + + UT_5 + UT*Prescaler period + 0x5 + + + UT_6 + UT*Prescaler period + 0x6 + + + UT_7 + UT*Prescaler period + 0x7 + + + UT_8 + UT*Prescaler period + 0x8 + + + UT_9 + UT*Prescaler period + 0x9 + + + + + + + NANDCR0 + NAND control register 0 + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Port Size + 0 + 1 + read-write + + + PS_0 + 8bit + 0 + + + PS_1 + 16bit + 0x1 + + + + + SYNCEN + Select NAND controller mode. + 1 + 1 + read-write + + + SYNCEN_0 + Asynchronous mode is enabled. + 0 + + + SYNCEN_1 + Synchronous mode is enabled. + 0x1 + + + + + BL + Burst Length + 4 + 3 + read-write + + + BL_0 + 1 + 0 + + + BL_1 + 2 + 0x1 + + + BL_2 + 4 + 0x2 + + + BL_3 + 8 + 0x3 + + + BL_4 + 16 + 0x4 + + + BL_5 + 32 + 0x5 + + + BL_6 + 64 + 0x6 + + + BL_7 + 64 + 0x7 + + + + + EDO + EDO mode enabled + 7 + 1 + read-write + + + EDO_0 + EDO mode disabled + 0 + + + EDO_1 + EDO mode enabled + 0x1 + + + + + COL + Column address bit number + 8 + 3 + read-write + + + COL_0 + 16 + 0 + + + COL_1 + 15 + 0x1 + + + COL_2 + 14 + 0x2 + + + COL_3 + 13 + 0x3 + + + COL_4 + 12 + 0x4 + + + COL_5 + 11 + 0x5 + + + COL_6 + 10 + 0x6 + + + COL_7 + 9 + 0x7 + + + + + + + NANDCR1 + NAND control register 1 + 0x54 + 32 + read-write + 0 + 0xFFFFFFFF + + + CES + CE setup time + 0 + 4 + read-write + + + CEH + CE hold time + 4 + 4 + read-write + + + WEL + WE# LOW time + 8 + 4 + read-write + + + WEH + WE# HIGH time + 12 + 4 + read-write + + + REL + RE# LOW time + 16 + 4 + read-write + + + REH + RE# HIGH time + 20 + 4 + read-write + + + TA + Turnaround time + 24 + 4 + read-write + + + CEITV + CE# interval time + 28 + 4 + read-write + + + + + NANDCR2 + NAND control register 2 + 0x58 + 32 + read-write + 0x10410 + 0xFFFFFFFF + + + TWHR + WE# HIGH to RE# LOW wait time + 0 + 6 + read-write + + + TRHW + RE# HIGH to WE# LOW wait time + 6 + 6 + read-write + + + TADL + ALE to WRITE Data start wait time + 12 + 6 + read-write + + + TRR + Ready to RE# LOW min wait time + 18 + 6 + read-write + + + TWB + WE# HIGH to busy wait time + 24 + 6 + read-write + + + + + NANDCR3 + NAND control register 3 + 0x5C + 32 + read-write + 0 + 0xFFFFFFFF + + + NDOPT1 + NAND option bit 1 + 0 + 1 + read-write + + + NDOPT2 + NAND option bit 2 + 1 + 1 + read-write + + + NDOPT3 + NAND option bit 3 + 2 + 1 + read-write + + + CLE + NAND CLE Option + 3 + 1 + read-write + + + RDS + Read Data Setup cycle time. + 16 + 4 + read-write + + + RDH + Read Data Hold cycle time. + 20 + 4 + read-write + + + WDS + Write Data Setup cycle time. + 24 + 4 + read-write + + + WDH + Write Data Hold cycle time. + 28 + 4 + read-write + + + + + NORCR0 + NOR control register 0 + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Port Size + 0 + 1 + read-write + + + PS_0 + 8bit + 0 + + + PS_1 + 16bit + 0x1 + + + + + SYNCEN + Select NOR controller mode. + 1 + 1 + read-write + + + SYNCEN_0 + Asynchronous mode is enabled. + 0 + + + SYNCEN_1 + Synchronous mode is enabled. + 0x1 + + + + + BL + Burst Length + 4 + 3 + read-write + + + BL_0 + 1 + 0 + + + BL_1 + 2 + 0x1 + + + BL_2 + 4 + 0x2 + + + BL_3 + 8 + 0x3 + + + BL_4 + 16 + 0x4 + + + BL_5 + 32 + 0x5 + + + BL_6 + 64 + 0x6 + + + BL_7 + 64 + 0x7 + + + + + AM + Address Mode + 8 + 2 + read-write + + + AM_0 + Address/Data MUX mode + 0 + + + AM_1 + Advanced Address/Data MUX mode + 0x1 + + + AM_2 + Address/Data non-MUX mode + 0x2 + + + AM_3 + Address/Data non-MUX mode + 0x3 + + + + + ADVP + ADV# polarity + 10 + 1 + read-write + + + ADVP_0 + ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. + 0 + + + ADVP_1 + ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH. + 0x1 + + + + + ADVH + ADV# level control during address hold state + 11 + 1 + read-write + + + ADVH_0 + ADV# is high during address hold state. + 0 + + + ADVH_1 + ADV# is low during address hold state. + 0x1 + + + + + COL + Column Address bit width + 12 + 4 + read-write + + + COL_0 + 12 Bits + 0 + + + COL_1 + 11 Bits + 0x1 + + + COL_2 + 10 Bits + 0x2 + + + COL_3 + 9 Bits + 0x3 + + + COL_4 + 8 Bits + 0x4 + + + COL_5 + 7 Bits + 0x5 + + + COL_6 + 6 Bits + 0x6 + + + COL_7 + 5 Bits + 0x7 + + + COL_8 + 4 Bits + 0x8 + + + COL_9 + 3 Bits + 0x9 + + + COL_10 + 2 Bits + 0xA + + + COL_11 + 12 Bits + 0xB + + + COL_12 + 12 Bits + 0xC + + + COL_13 + 12 Bits + 0xD + + + COL_14 + 12 Bits + 0xE + + + COL_15 + 12 Bits + 0xF + + + + + + + NORCR1 + NOR control register 1 + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + CES + CE setup time cycle + 0 + 4 + read-write + + + CEH + CE hold min time (CEH+1) cycle + 4 + 4 + read-write + + + AS + Address setup time + 8 + 4 + read-write + + + AH + Address hold time + 12 + 4 + read-write + + + WEL + WE LOW time (WEL+1) cycle + 16 + 4 + read-write + + + WEH + WE HIGH time (WEH+1) cycle + 20 + 4 + read-write + + + REL + RE LOW time (REL+1) cycle + 24 + 4 + read-write + + + REH + RE HIGH time (REH+1) cycle + 28 + 4 + read-write + + + + + NORCR2 + NOR control register 2 + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + TA + Turnaround time cycle + 8 + 4 + read-write + + + AWDH + Address to write data hold time cycle + 12 + 4 + read-write + + + LC + Latency count + 16 + 4 + read-write + + + RD + Read cycle time + 20 + 4 + read-write + + + CEITV + CE# interval min time + 24 + 4 + read-write + + + RDH + Read cycle hold time + 28 + 4 + read-write + + + + + NORCR3 + NOR control register 3 + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + ASSR + Address setup time for synchronous read + 0 + 4 + read-write + + + AHSR + Address hold time for synchronous read + 4 + 4 + read-write + + + + + SRAMCR0 + SRAM control register 0 + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Port Size + 0 + 1 + read-write + + + PS_0 + 8bit + 0 + + + PS_1 + 16bit + 0x1 + + + + + SYNCEN + Select SRAM controller mode. + 1 + 1 + read-write + + + SYNCEN_0 + Asynchronous mode is enabled. + 0 + + + SYNCEN_1 + Synchronous mode is enabled. + 0x1 + + + + + BL + Burst Length + 4 + 3 + read-write + + + BL_0 + 1 + 0 + + + BL_1 + 2 + 0x1 + + + BL_2 + 4 + 0x2 + + + BL_3 + 8 + 0x3 + + + BL_4 + 16 + 0x4 + + + BL_5 + 32 + 0x5 + + + BL_6 + 64 + 0x6 + + + BL_7 + 64 + 0x7 + + + + + AM + Address Mode + 8 + 2 + read-write + + + AM_0 + Address/Data MUX mode + 0 + + + AM_1 + Advanced Address/Data MUX mode + 0x1 + + + AM_2 + Address/Data non-MUX mode + 0x2 + + + AM_3 + Address/Data non-MUX mode + 0x3 + + + + + ADVP + ADV# polarity + 10 + 1 + read-write + + + ADVP_0 + ADV# is Low Active. In ASYNC mode, device sample address with ADV# rise edge; In SYNC mode, device sample address when ADV# is LOW. + 0 + + + ADVP_1 + ADV# is High Active. In ASYNC mode, device sample address with ADV# fall edge; In SYNC mode, device sample address when ADV# is HIGH. + 0x1 + + + + + ADVH + ADV# level control during address hold state + 11 + 1 + read-write + + + ADVH_0 + ADV# is high during address hold state. + 0 + + + ADVH_1 + ADV# is low during address hold state. + 0x1 + + + + + COL + Column Address bit width + 12 + 4 + read-write + + + COL_0 + 12 Bits + 0 + + + COL_1 + 11 Bits + 0x1 + + + COL_2 + 10 Bits + 0x2 + + + COL_3 + 9 Bits + 0x3 + + + COL_4 + 8 Bits + 0x4 + + + COL_5 + 7 Bits + 0x5 + + + COL_6 + 6 Bits + 0x6 + + + COL_7 + 5 Bits + 0x7 + + + COL_8 + 4 Bits + 0x8 + + + COL_9 + 3 Bits + 0x9 + + + COL_10 + 2 Bits + 0xA + + + COL_11 + 12 Bits + 0xB + + + COL_12 + 12 Bits + 0xC + + + COL_13 + 12 Bits + 0xD + + + COL_14 + 12 Bits + 0xE + + + COL_15 + 12 Bits + 0xF + + + + + + + SRAMCR1 + SRAM control register 1 + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + CES + CE setup time cycle + 0 + 4 + read-write + + + CEH + CE hold min time + 4 + 4 + read-write + + + AS + Address setup time + 8 + 4 + read-write + + + AH + Address hold time + 12 + 4 + read-write + + + WEL + WE LOW time (WEL+1) cycle + 16 + 4 + read-write + + + WEH + WE HIGH time (WEH+1) cycle + 20 + 4 + read-write + + + REL + RE LOW time (REL+1) cycle + 24 + 4 + read-write + + + REH + RE HIGH time (REH+1) cycle + 28 + 4 + read-write + + + + + SRAMCR2 + SRAM control register 2 + 0x78 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDS + Write Data setup time (WDS+1) cycle + 0 + 4 + read-write + + + WDH + Write Data hold time WDH cycle + 4 + 4 + read-write + + + TA + Turnaround time cycle + 8 + 4 + read-write + + + AWDH + Address to write data hold time cycle + 12 + 4 + read-write + + + LC + Latency count + 16 + 4 + read-write + + + RD + Read cycle time + 20 + 4 + read-write + + + CEITV + CE# interval min time + 24 + 4 + read-write + + + RDH + Read cycle hold time + 28 + 4 + read-write + + + + + SRAMCR3 + SRAM control register 3 + 0x7C + 32 + read-write + 0 + 0xFFFFFFFF + + + DBICR0 + DBI-B control register 0 + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + PS + Port Size + 0 + 1 + read-write + + + PS_0 + 8bit + 0 + + + PS_1 + 16bit + 0x1 + + + + + BL + Burst Length + 4 + 3 + read-write + + + BL_0 + 1 + 0 + + + BL_1 + 2 + 0x1 + + + BL_2 + 4 + 0x2 + + + BL_3 + 8 + 0x3 + + + BL_4 + 16 + 0x4 + + + BL_5 + 32 + 0x5 + + + BL_6 + 64 + 0x6 + + + BL_7 + 64 + 0x7 + + + + + COL + Column Address bit width + 12 + 4 + read-write + + + COL_0 + 12 Bits + 0 + + + COL_1 + 11 Bits + 0x1 + + + COL_2 + 10 Bits + 0x2 + + + COL_3 + 9 Bits + 0x3 + + + COL_4 + 8 Bits + 0x4 + + + COL_5 + 7 Bits + 0x5 + + + COL_6 + 6 Bits + 0x6 + + + COL_7 + 5 Bits + 0x7 + + + COL_8 + 4 Bits + 0x8 + + + COL_9 + 3 Bits + 0x9 + + + COL_10 + 2 Bits + 0xA + + + COL_11 + 12 Bits + 0xB + + + COL_12 + 12 Bits + 0xC + + + COL_13 + 12 Bits + 0xD + + + COL_14 + 12 Bits + 0xE + + + COL_15 + 12 Bits + 0xF + + + + + + + DBICR1 + DBI-B control register 1 + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + CES + CSX Setup Time + 0 + 4 + read-write + + + CEH + CSX Hold Time + 4 + 4 + read-write + + + WEL + WRX Low Time + 8 + 4 + read-write + + + WEH + WRX High Time + 12 + 4 + read-write + + + REL + RDX Low Time + 16 + 6 + read-write + + + REH + RDX High Time + 22 + 6 + read-write + + + CEITV + CSX interval min time + 28 + 4 + read-write + + + + + IPCR0 + IP Command control register 0 + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + SA + Slave address + 0 + 32 + read-write + + + + + IPCR1 + IP Command control register 1 + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATSZ + Data Size in Byte + 0 + 3 + read-write + + + DATSZ_0 + 4 + 0 + + + DATSZ_1 + 1 + 0x1 + + + DATSZ_2 + 2 + 0x2 + + + DATSZ_3 + 3 + 0x3 + + + DATSZ_4 + 4 + 0x4 + + + DATSZ_5 + 4 + 0x5 + + + DATSZ_6 + 4 + 0x6 + + + DATSZ_7 + 4 + 0x7 + + + + + NAND_EXT_ADDR + NAND Extended Address + 8 + 8 + read-write + + + + + IPCR2 + IP Command control register 2 + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + BM0 + Byte Mask for Byte 0 (IPTXD bit 7:0) + 0 + 1 + read-write + + + BM0_0 + Byte Unmasked + 0 + + + BM0_1 + Byte Masked + 0x1 + + + + + BM1 + Byte Mask for Byte 1 (IPTXD bit 15:8) + 1 + 1 + read-write + + + BM1_0 + Byte Unmasked + 0 + + + BM1_1 + Byte Masked + 0x1 + + + + + BM2 + Byte Mask for Byte 2 (IPTXD bit 23:16) + 2 + 1 + read-write + + + BM2_0 + Byte Unmasked + 0 + + + BM2_1 + Byte Masked + 0x1 + + + + + BM3 + Byte Mask for Byte 3 (IPTXD bit 31:24) + 3 + 1 + read-write + + + BM3_0 + Byte Unmasked + 0 + + + BM3_1 + Byte Masked + 0x1 + + + + + + + IPCMD + IP Command register + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + CMD + SDRAM Commands: 0x8: READ 0x9: WRITE 0xA: MODESET 0xB: ACTIVE 0xC: AUTO REFRESH 0xD: SELF REFRESH 0xE: PRECHARGE 0xF: PRECHARGE ALL Others: RSVD SELF REFRESH will be sent to all SDRAM devices because they shared same SEMC_CLK pin + 0 + 16 + read-write + + + KEY + This field should be written with 0xA55A when trigging an IP command for all device types + 16 + 16 + write-only + + + + + IPTXDAT + TX DATA register (for IP Command) + 0xA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + DAT + no description available + 0 + 32 + read-write + + + + + IPRXDAT + RX DATA register (for IP Command) + 0xB0 + 32 + read-only + 0 + 0xFFFFFFFF + + + DAT + no description available + 0 + 32 + read-only + + + + + STS0 + Status register 0 + 0xC0 + 32 + read-only + 0x1 + 0xFFFFFFFF + + + IDLE + Indicating whether SEMC is in IDLE state. + 0 + 1 + read-only + + + NARDY + Indicating NAND device Ready/WAIT# pin level. + 1 + 1 + read-only + + + NARDY_0 + NAND device is not ready + 0 + + + NARDY_1 + NAND device is ready + 0x1 + + + + + + + STS1 + Status register 1 + 0xC4 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS2 + Status register 2 + 0xC8 + 32 + read-only + 0 + 0xFFFFFFFF + + + NDWRPEND + This field indicating whether there is pending AXI command (write) to NAND device. + 3 + 1 + read-only + + + NDWRPEND_0 + No pending + 0 + + + NDWRPEND_1 + Pending + 0x1 + + + + + + + STS3 + Status register 3 + 0xCC + 32 + read-only + 0 + 0xFFFFFFFF + + + STS4 + Status register 4 + 0xD0 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS5 + Status register 5 + 0xD4 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS6 + Status register 6 + 0xD8 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS7 + Status register 7 + 0xDC + 32 + read-only + 0 + 0xFFFFFFFF + + + STS8 + Status register 8 + 0xE0 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS9 + Status register 9 + 0xE4 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS10 + Status register 10 + 0xE8 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS11 + Status register 11 + 0xEC + 32 + read-only + 0 + 0xFFFFFFFF + + + STS12 + Status register 12 + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + NDADDR + This field indicating the last write address (AXI command) to NAND device (without base address in SEMC_BR4). + 0 + 32 + read-only + + + + + STS13 + Status register 13 + 0xF4 + 32 + read-only + 0x100 + 0xFFFFFFFF + + + SLVLOCK + Sample clock slave delay line locked. + 0 + 1 + read-only + + + REFLOCK + Sample clock reference delay line locked. + 1 + 1 + read-only + + + SLVSEL + Sample clock slave delay line delay cell number selection . + 2 + 6 + read-only + + + REFSEL + Sample clock reference delay line delay cell number selection. + 8 + 6 + read-only + + + + + STS14 + Status register 14 + 0xF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + STS15 + Status register 15 + 0xFC + 32 + read-only + 0 + 0xFFFFFFFF + + + + + DCP + DCP register reference index + DCP + DCP_ + 0x402FC000 + + 0 + 0x434 + registers + + + DCP + 50 + + + DCP_VMI + 51 + + + + CTRL + DCP control register 0 + 0 + 32 + read-write + 0xF0800000 + 0xFFFFFFFF + + + CHANNEL_INTERRUPT_ENABLE + Per-channel interrupt enable bit + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + ENABLE_CONTEXT_SWITCHING + Enable automatic context switching for the channels + 21 + 1 + read-write + + + ENABLE_CONTEXT_CACHING + The software must set this bit to enable the caching of contexts between the operations + 22 + 1 + read-write + + + GATHER_RESIDUAL_WRITES + The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations + 23 + 1 + read-write + + + PRESENT_SHA + Indicates whether the SHA1/SHA2 functions are present. + 28 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + PRESENT_CRYPTO + Indicates whether the crypto (cipher/hash) functions are present. + 29 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + CLKGATE + This bit must be set to zero for a normal operation + 30 + 1 + read-write + + + SFTRST + Set this bit to zero to enable a normal DCP operation + 31 + 1 + read-write + + + + + CTRL_SET + DCP control register 0 + 0x4 + 32 + read-write + 0xF0800000 + 0xFFFFFFFF + + + CHANNEL_INTERRUPT_ENABLE + Per-channel interrupt enable bit + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + ENABLE_CONTEXT_SWITCHING + Enable automatic context switching for the channels + 21 + 1 + read-write + + + ENABLE_CONTEXT_CACHING + The software must set this bit to enable the caching of contexts between the operations + 22 + 1 + read-write + + + GATHER_RESIDUAL_WRITES + The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations + 23 + 1 + read-write + + + PRESENT_SHA + Indicates whether the SHA1/SHA2 functions are present. + 28 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + PRESENT_CRYPTO + Indicates whether the crypto (cipher/hash) functions are present. + 29 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + CLKGATE + This bit must be set to zero for a normal operation + 30 + 1 + read-write + + + SFTRST + Set this bit to zero to enable a normal DCP operation + 31 + 1 + read-write + + + + + CTRL_CLR + DCP control register 0 + 0x8 + 32 + read-write + 0xF0800000 + 0xFFFFFFFF + + + CHANNEL_INTERRUPT_ENABLE + Per-channel interrupt enable bit + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + ENABLE_CONTEXT_SWITCHING + Enable automatic context switching for the channels + 21 + 1 + read-write + + + ENABLE_CONTEXT_CACHING + The software must set this bit to enable the caching of contexts between the operations + 22 + 1 + read-write + + + GATHER_RESIDUAL_WRITES + The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations + 23 + 1 + read-write + + + PRESENT_SHA + Indicates whether the SHA1/SHA2 functions are present. + 28 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + PRESENT_CRYPTO + Indicates whether the crypto (cipher/hash) functions are present. + 29 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + CLKGATE + This bit must be set to zero for a normal operation + 30 + 1 + read-write + + + SFTRST + Set this bit to zero to enable a normal DCP operation + 31 + 1 + read-write + + + + + CTRL_TOG + DCP control register 0 + 0xC + 32 + read-write + 0xF0800000 + 0xFFFFFFFF + + + CHANNEL_INTERRUPT_ENABLE + Per-channel interrupt enable bit + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + ENABLE_CONTEXT_SWITCHING + Enable automatic context switching for the channels + 21 + 1 + read-write + + + ENABLE_CONTEXT_CACHING + The software must set this bit to enable the caching of contexts between the operations + 22 + 1 + read-write + + + GATHER_RESIDUAL_WRITES + The software must set this bit to enable the ragged writes to the unaligned buffers to be gathered between multiple write operations + 23 + 1 + read-write + + + PRESENT_SHA + Indicates whether the SHA1/SHA2 functions are present. + 28 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + PRESENT_CRYPTO + Indicates whether the crypto (cipher/hash) functions are present. + 29 + 1 + read-only + + + Absent + Absent + 0 + + + Present + Present + 0x1 + + + + + CLKGATE + This bit must be set to zero for a normal operation + 30 + 1 + read-write + + + SFTRST + Set this bit to zero to enable a normal DCP operation + 31 + 1 + read-write + + + + + STAT + DCP status register + 0x10 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + IRQ + Indicates which channels have pending interrupt requests + 0 + 4 + read-write + + + READY_CHANNELS + Indicates which channels are ready to proceed with a transfer (the active channel is also included) + 16 + 8 + read-only + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CUR_CHANNEL + Current (active) channel (encoded) + 24 + 4 + read-only + + + None + None + 0 + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x3 + + + CH3 + CH3 + 0x4 + + + + + OTP_KEY_READY + When set, it indicates that the OTP key is shifted from the fuse block and is ready for use. + 28 + 1 + read-only + + + + + STAT_SET + DCP status register + 0x14 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + IRQ + Indicates which channels have pending interrupt requests + 0 + 4 + read-write + + + READY_CHANNELS + Indicates which channels are ready to proceed with a transfer (the active channel is also included) + 16 + 8 + read-only + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CUR_CHANNEL + Current (active) channel (encoded) + 24 + 4 + read-only + + + None + None + 0 + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x3 + + + CH3 + CH3 + 0x4 + + + + + OTP_KEY_READY + When set, it indicates that the OTP key is shifted from the fuse block and is ready for use. + 28 + 1 + read-only + + + + + STAT_CLR + DCP status register + 0x18 + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + IRQ + Indicates which channels have pending interrupt requests + 0 + 4 + read-write + + + READY_CHANNELS + Indicates which channels are ready to proceed with a transfer (the active channel is also included) + 16 + 8 + read-only + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CUR_CHANNEL + Current (active) channel (encoded) + 24 + 4 + read-only + + + None + None + 0 + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x3 + + + CH3 + CH3 + 0x4 + + + + + OTP_KEY_READY + When set, it indicates that the OTP key is shifted from the fuse block and is ready for use. + 28 + 1 + read-only + + + + + STAT_TOG + DCP status register + 0x1C + 32 + read-write + 0x10000000 + 0xFFFFFFFF + + + IRQ + Indicates which channels have pending interrupt requests + 0 + 4 + read-write + + + READY_CHANNELS + Indicates which channels are ready to proceed with a transfer (the active channel is also included) + 16 + 8 + read-only + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CUR_CHANNEL + Current (active) channel (encoded) + 24 + 4 + read-only + + + None + None + 0 + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x3 + + + CH3 + CH3 + 0x4 + + + + + OTP_KEY_READY + When set, it indicates that the OTP key is shifted from the fuse block and is ready for use. + 28 + 1 + read-only + + + + + CHANNELCTRL + DCP channel control register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE_CHANNEL + Setting a bit in this field enables the DMA channel associated with it + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + HIGH_PRIORITY_CHANNEL + Setting a bit in this field causes the corresponding channel to have high-priority arbitration + 8 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CH0_IRQ_MERGED + Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt + 16 + 1 + read-write + + + + + CHANNELCTRL_SET + DCP channel control register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE_CHANNEL + Setting a bit in this field enables the DMA channel associated with it + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + HIGH_PRIORITY_CHANNEL + Setting a bit in this field causes the corresponding channel to have high-priority arbitration + 8 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CH0_IRQ_MERGED + Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt + 16 + 1 + read-write + + + + + CHANNELCTRL_CLR + DCP channel control register + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE_CHANNEL + Setting a bit in this field enables the DMA channel associated with it + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + HIGH_PRIORITY_CHANNEL + Setting a bit in this field causes the corresponding channel to have high-priority arbitration + 8 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CH0_IRQ_MERGED + Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt + 16 + 1 + read-write + + + + + CHANNELCTRL_TOG + DCP channel control register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE_CHANNEL + Setting a bit in this field enables the DMA channel associated with it + 0 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + HIGH_PRIORITY_CHANNEL + Setting a bit in this field causes the corresponding channel to have high-priority arbitration + 8 + 8 + read-write + + + CH0 + CH0 + 0x1 + + + CH1 + CH1 + 0x2 + + + CH2 + CH2 + 0x4 + + + CH3 + CH3 + 0x8 + + + + + CH0_IRQ_MERGED + Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt + 16 + 1 + read-write + + + + + CAPABILITY0 + DCP capability 0 register + 0x30 + 32 + read-write + 0x404 + 0xFFFFFFFF + + + NUM_KEYS + Encoded value indicating the number of key-storage locations implemented in the design + 0 + 8 + read-only + + + NUM_CHANNELS + Encoded value indicating the number of channels implemented in the design + 8 + 4 + read-only + + + DISABLE_UNIQUE_KEY + Write to a 1 to disable the per-device unique key + 29 + 1 + read-write + + + DISABLE_DECRYPT + Write to 1 to disable the decryption + 31 + 1 + read-write + + + + + CAPABILITY1 + DCP capability 1 register + 0x40 + 32 + read-only + 0x70001 + 0xFFFFFFFF + + + CIPHER_ALGORITHMS + One-hot field indicating which cipher algorithms are available + 0 + 16 + read-only + + + AES128 + AES128 + 0x1 + + + + + HASH_ALGORITHMS + One-hot field indicating which hashing features are implemented in the hardware + 16 + 16 + read-only + + + SHA1 + SHA1 + 0x1 + + + CRC32 + CRC32 + 0x2 + + + SHA256 + SHA256 + 0x4 + + + + + + + CONTEXT + DCP context buffer pointer + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Context pointer address + 0 + 32 + read-write + + + + + KEY + DCP key index + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + SUBWORD + Key subword pointer + 0 + 2 + read-write + + + INDEX + Key index pointer. The valid indices are 0-[number_keys]. + 4 + 2 + read-write + + + + + KEYDATA + DCP key data + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Word 0 data for the key. This is the least-significant word. + 0 + 32 + read-write + + + + + PACKET0 + DCP work packet 0 status register + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + Next pointer register + 0 + 32 + read-only + + + + + PACKET1 + DCP work packet 1 status register + 0x90 + 32 + read-only + 0 + 0xFFFFFFFF + + + INTERRUPT + Reflects whether the channel must issue an interrupt upon the completion of the packet. + 0 + 1 + read-only + + + DECR_SEMAPHORE + Reflects whether the channel's semaphore must be decremented at the end of the current operation + 1 + 1 + read-only + + + CHAIN + Reflects whether the next command pointer register must be loaded into the channel's current descriptor pointer + 2 + 1 + read-only + + + CHAIN_CONTIGUOUS + Reflects whether the next packet's address is located following this packet's payload. + 3 + 1 + read-only + + + ENABLE_MEMCOPY + Reflects whether the selected hashing function should be enabled for this operation. + 4 + 1 + read-only + + + ENABLE_CIPHER + Reflects whether the selected cipher function must be enabled for this operation. + 5 + 1 + read-only + + + ENABLE_HASH + Reflects whether the selected hashing function must be enabled for this operation. + 6 + 1 + read-only + + + ENABLE_BLIT + Reflects whether the DCP must perform a blit operation + 7 + 1 + read-only + + + CIPHER_ENCRYPT + When the cipher block is enabled, this bit indicates whether the operation is encryption or decryption + 8 + 1 + read-only + + + DECRYPT + DECRYPT + 0 + + + ENCRYPT + ENCRYPT + 0x1 + + + + + CIPHER_INIT + Reflects whether the cipher block must load the initialization vector from the payload for this operation + 9 + 1 + read-only + + + OTP_KEY + Reflects whether a hardware-based key must be used + 10 + 1 + read-only + + + PAYLOAD_KEY + When set, it indicates the payload contains the key + 11 + 1 + read-only + + + HASH_INIT + Reflects whether the current hashing block is the initial block in the hashing operation, so the hash registers must be initialized before the operation + 12 + 1 + read-only + + + HASH_TERM + Reflects whether the current hashing block is the final block in the hashing operation, so the hash padding must be applied by the hardware + 13 + 1 + read-only + + + CHECK_HASH + Reflects whether the calculated hash value must be compared to the hash provided in the payload. + 14 + 1 + read-only + + + HASH_OUTPUT + When the hashing is enabled, this bit controls whether the input or output data is hashed. + 15 + 1 + read-only + + + INPUT + INPUT + 0 + + + OUTPUT + OUTPUT + 0x1 + + + + + CONSTANT_FILL + When this bit is set (MEMCOPY and BLIT modes only), the DCP simply fills the destination buffer with the value found in the source address field + 16 + 1 + read-only + + + TEST_SEMA_IRQ + This bit is used to test the channel semaphore transition to 0. FOR TEST USE ONLY! + 17 + 1 + read-only + + + KEY_BYTESWAP + Reflects whether the DCP engine swaps the key bytes (big-endian key). + 18 + 1 + read-only + + + KEY_WORDSWAP + Reflects whether the DCP engine swaps the key words (big-endian key). + 19 + 1 + read-only + + + INPUT_BYTESWAP + Reflects whether the DCP engine byteswaps the input data (big-endian data). + 20 + 1 + read-only + + + INPUT_WORDSWAP + Reflects whether the DCP engine wordswaps the input data (big-endian data). + 21 + 1 + read-only + + + OUTPUT_BYTESWAP + Reflects whether the DCP engine byteswaps the output data (big-endian data). + 22 + 1 + read-only + + + OUTPUT_WORDSWAP + Reflects whether the DCP engine wordswaps the output data (big-endian data). + 23 + 1 + read-only + + + TAG + Packet Tag + 24 + 8 + read-only + + + + + PACKET2 + DCP work packet 2 status register + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + CIPHER_SELECT + Cipher selection field + 0 + 4 + read-only + + + AES128 + AES128 + 0 + + + + + CIPHER_MODE + Cipher mode selection field. Reflects the mode of operation for the cipher operations. + 4 + 4 + read-only + + + ECB + ECB + 0 + + + CBC + CBC + 0x1 + + + + + KEY_SELECT + Key selection field + 8 + 8 + read-only + + + KEY0 + KEY0 + 0 + + + KEY1 + KEY1 + 0x1 + + + KEY2 + KEY2 + 0x2 + + + KEY3 + KEY3 + 0x3 + + + UNIQUE_KEY + UNIQUE_KEY + 0xFE + + + OTP_KEY + OTP_KEY + 0xFF + + + + + HASH_SELECT + Hash Selection Field + 16 + 4 + read-only + + + SHA1 + SHA1 + 0 + + + CRC32 + CRC32 + 0x1 + + + SHA256 + SHA256 + 0x2 + + + + + CIPHER_CFG + Cipher configuration bits. Optional configuration bits are required for the ciphers. + 24 + 8 + read-only + + + + + PACKET3 + DCP work packet 3 status register + 0xB0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + Source buffer address pointer + 0 + 32 + read-only + + + + + PACKET4 + DCP work packet 4 status register + 0xC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + Destination buffer address pointer + 0 + 32 + read-only + + + + + PACKET5 + DCP work packet 5 status register + 0xD0 + 32 + read-only + 0 + 0xFFFFFFFF + + + COUNT + Byte count register. This value is the working value and updates as the operation proceeds. + 0 + 32 + read-only + + + + + PACKET6 + DCP work packet 6 status register + 0xE0 + 32 + read-only + 0 + 0xFFFFFFFF + + + ADDR + This regiser reflects the payload pointer for the current control packet. + 0 + 32 + read-only + + + + + CH0CMDPTR + DCP channel 0 command pointer address register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 0. + 0 + 32 + read-write + + + + + CH0SEMA + DCP channel 0 semaphore register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 16 + 8 + read-only + + + + + CH0STAT + DCP channel 0 status register + 0x120 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error signalled because the next pointer is 0x00000000 + 0x1 + + + NO_CHAIN + Error signalled because the semaphore is non-zero and neither chain bit is set + 0x2 + + + CONTEXT_ERROR + Error signalled because an error is reported reading/writing the context buffer + 0x3 + + + PAYLOAD_ERROR + Error signalled because an error is reported reading/writing the payload + 0x4 + + + INVALID_MODE + Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure + 24 + 8 + read-only + + + + + CH0STAT_SET + DCP channel 0 status register + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error signalled because the next pointer is 0x00000000 + 0x1 + + + NO_CHAIN + Error signalled because the semaphore is non-zero and neither chain bit is set + 0x2 + + + CONTEXT_ERROR + Error signalled because an error is reported reading/writing the context buffer + 0x3 + + + PAYLOAD_ERROR + Error signalled because an error is reported reading/writing the payload + 0x4 + + + INVALID_MODE + Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure + 24 + 8 + read-only + + + + + CH0STAT_CLR + DCP channel 0 status register + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error signalled because the next pointer is 0x00000000 + 0x1 + + + NO_CHAIN + Error signalled because the semaphore is non-zero and neither chain bit is set + 0x2 + + + CONTEXT_ERROR + Error signalled because an error is reported reading/writing the context buffer + 0x3 + + + PAYLOAD_ERROR + Error signalled because an error is reported reading/writing the payload + 0x4 + + + INVALID_MODE + Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure + 24 + 8 + read-only + + + + + CH0STAT_TOG + DCP channel 0 status register + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet payload + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error signalled because the next pointer is 0x00000000 + 0x1 + + + NO_CHAIN + Error signalled because the semaphore is non-zero and neither chain bit is set + 0x2 + + + CONTEXT_ERROR + Error signalled because an error is reported reading/writing the context buffer + 0x3 + + + PAYLOAD_ERROR + Error signalled because an error is reported reading/writing the payload + 0x4 + + + INVALID_MODE + Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash) + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure + 24 + 8 + read-only + + + + + CH0OPTS + DCP channel 0 options register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH0OPTS_SET + DCP channel 0 options register + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH0OPTS_CLR + DCP channel 0 options register + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH0OPTS_TOG + DCP channel 0 options register + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH1CMDPTR + DCP channel 1 command pointer address register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 1. + 0 + 32 + read-write + + + + + CH1SEMA + DCP channel 1 semaphore register + 0x150 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and the DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 16 + 8 + read-only + + + + + CH1STAT + DCP channel 1 status register + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported when reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported when reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH1STAT_SET + DCP channel 1 status register + 0x164 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported when reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported when reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH1STAT_CLR + DCP channel 1 status register + 0x168 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported when reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported when reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH1STAT_TOG + DCP channel 1 status register + 0x16C + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates the additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported when reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported when reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH1OPTS + DCP channel 1 options register + 0x170 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH1OPTS_SET + DCP channel 1 options register + 0x174 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH1OPTS_CLR + DCP channel 1 options register + 0x178 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH1OPTS_TOG + DCP channel 1 options register + 0x17C + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH2CMDPTR + DCP channel 2 command pointer address register + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 2. + 0 + 32 + read-write + + + + + CH2SEMA + DCP channel 2 semaphore register + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 16 + 8 + read-only + + + + + CH2STAT + DCP channel 2 status register + 0x1A0 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH2STAT_SET + DCP channel 2 status register + 0x1A4 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH2STAT_CLR + DCP channel 2 status register + 0x1A8 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH2STAT_TOG + DCP channel 2 status register + 0x1AC + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload, or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH2OPTS + DCP channel 2 options register + 0x1B0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH2OPTS_SET + DCP channel 2 options register + 0x1B4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH2OPTS_CLR + DCP channel 2 options register + 0x1B8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH2OPTS_TOG + DCP channel 2 options register + 0x1BC + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH3CMDPTR + DCP channel 3 command pointer address register + 0x1C0 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR + Pointer to the descriptor structure to be processed for channel 3. + 0 + 32 + read-write + + + + + CH3SEMA + DCP channel 3 semaphore register + 0x1D0 + 32 + read-write + 0 + 0xFFFFFFFF + + + INCREMENT + The value written to this field is added to the semaphore count in an atomic way, such that the simultaneous software adds and DCP hardware substracts happening on the same clock are protected + 0 + 8 + read-write + + + VALUE + This read-only field shows the current (instantaneous) value of the semaphore counter. + 16 + 8 + read-only + + + + + CH3STAT + DCP channel 3 status register + 0x1E0 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH3STAT_SET + DCP channel 3 status register + 0x1E4 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH3STAT_CLR + DCP channel 3 status register + 0x1E8 + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH3STAT_TOG + DCP channel 3 status register + 0x1EC + 32 + read-write + 0 + 0xFFFFFFFF + + + HASH_MISMATCH + This bit indicates that a hashing check operation is mismatched for the control packets that enable the HASH_CHECK bit + 1 + 1 + read-write + + + ERROR_SETUP + This bit indicates that the hardware detected an invalid programming configuration (such as a buffer length that is not a multiple of the natural data size for the operation) + 2 + 1 + read-write + + + ERROR_PACKET + This bit indicates that a bus error occurred when reading the packet or payload or when writing the status back to the packet paylaod + 3 + 1 + read-write + + + ERROR_SRC + This bit indicates that a bus error occurred when reading from the source buffer + 4 + 1 + read-write + + + ERROR_DST + This bit indicates that a bus error occurred when storing to the destination buffer + 5 + 1 + read-write + + + ERROR_PAGEFAULT + This bit indicates that a page fault occurred while converting a virtual address to a physical address + 6 + 1 + read-write + + + ERROR_CODE + Indicates additional error codes for some of the error conditions. + 16 + 8 + read-write + + + NEXT_CHAIN_IS_0 + Error is signalled because the next pointer is 0x00000000. + 0x1 + + + NO_CHAIN + Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set. + 0x2 + + + CONTEXT_ERROR + Error is signalled because an error was reported while reading/writing the context buffer. + 0x3 + + + PAYLOAD_ERROR + Error is signalled because an error was reported while reading/writing the payload. + 0x4 + + + INVALID_MODE + Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash). + 0x5 + + + + + TAG + Indicates the tag from the last completed packet in the command structure. + 24 + 8 + read-only + + + + + CH3OPTS + DCP channel 3 options register + 0x1F0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH3OPTS_SET + DCP channel 3 options register + 0x1F4 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH3OPTS_CLR + DCP channel 3 options register + 0x1F8 + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + CH3OPTS_TOG + DCP channel 3 options register + 0x1FC + 32 + read-write + 0 + 0xFFFFFFFF + + + RECOVERY_TIMER + This field indicates the recovery time for the channel + 0 + 16 + read-write + + + + + DBGSELECT + DCP debug select register + 0x400 + 32 + read-write + 0 + 0xFFFFFFFF + + + INDEX + Selects a value to read via the debug data register. + 0 + 8 + read-write + + + CONTROL + CONTROL + 0x1 + + + OTPKEY0 + OTPKEY0 + 0x10 + + + OTPKEY1 + OTPKEY1 + 0x11 + + + OTPKEY2 + OTPKEY2 + 0x12 + + + OTPKEY3 + OTPKEY3 + 0x13 + + + + + + + DBGDATA + DCP debug data register + 0x410 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA + Debug data + 0 + 32 + read-only + + + + + PAGETABLE + DCP page table register + 0x420 + 32 + read-write + 0 + 0xFFFFFFFF + + + ENABLE + Page table enable control + 0 + 1 + read-write + + + FLUSH + Page table flush control. To flush the TLB, write this bit to 1 and then back to 0. + 1 + 1 + read-write + + + BASE + Page table base address + 2 + 30 + read-write + + + + + VERSION + DCP version register + 0x430 + 32 + read-only + 0x2010000 + 0xFFFFFFFF + + + STEP + Fixed read-only value reflecting the stepping of the version of the design implementation. + 0 + 16 + read-only + + + MINOR + Fixed read-only value reflecting the MINOR version of the design implementation. + 16 + 8 + read-only + + + MAJOR + Fixed read-only value reflecting the MAJOR version of the design implementation. + 24 + 8 + read-only + + + + + + + SPDIF + SPDIF + SPDIF + SPDIF_ + 0x40380000 + + 0 + 0x54 + registers + + + SPDIF + 60 + + + + SCR + SPDIF Configuration Register + 0 + 32 + read-write + 0x400 + 0xFFFFFFFF + + + USrc_Sel + no description available + 0 + 2 + read-write + + + USrc_Sel_0 + No embedded U channel + 0 + + + USrc_Sel_1 + U channel from SPDIF receive block (CD mode) + 0x1 + + + USrc_Sel_3 + U channel from on chip transmitter + 0x3 + + + + + TxSel + no description available + 2 + 3 + read-write + + + TxSel_0 + Off and output 0 + 0 + + + TxSel_1 + Feed-through SPDIFIN + 0x1 + + + TxSel_5 + Tx Normal operation + 0x5 + + + + + ValCtrl + no description available + 5 + 1 + read-write + + + ValCtrl_0 + Outgoing Validity always set + 0 + + + ValCtrl_1 + Outgoing Validity always clear + 0x1 + + + + + DMA_TX_En + DMA Transmit Request Enable (Tx FIFO empty) + 8 + 1 + read-write + + + DMA_Rx_En + DMA Receive Request Enable (RX FIFO full) + 9 + 1 + read-write + + + TxFIFO_Ctrl + no description available + 10 + 2 + read-write + + + TxFIFO_Ctrl_0 + Send out digital zero on SPDIF Tx + 0 + + + TxFIFO_Ctrl_1 + Tx Normal operation + 0x1 + + + TxFIFO_Ctrl_2 + Reset to 1 sample remaining + 0x2 + + + + + soft_reset + When write 1 to this bit, it will cause SPDIF software reset + 12 + 1 + read-write + + + LOW_POWER + When write 1 to this bit, it will cause SPDIF enter low-power mode + 13 + 1 + read-write + + + TxFIFOEmpty_Sel + no description available + 15 + 2 + read-write + + + TxFIFOEmpty_Sel_0 + Empty interrupt if 0 sample in Tx left and right FIFOs + 0 + + + TxFIFOEmpty_Sel_1 + Empty interrupt if at most 4 sample in Tx left and right FIFOs + 0x1 + + + TxFIFOEmpty_Sel_2 + Empty interrupt if at most 8 sample in Tx left and right FIFOs + 0x2 + + + TxFIFOEmpty_Sel_3 + Empty interrupt if at most 12 sample in Tx left and right FIFOs + 0x3 + + + + + TxAutoSync + no description available + 17 + 1 + read-write + + + TxAutoSync_0 + Tx FIFO auto sync off + 0 + + + TxAutoSync_1 + Tx FIFO auto sync on + 0x1 + + + + + RxAutoSync + no description available + 18 + 1 + read-write + + + RxAutoSync_0 + Rx FIFO auto sync off + 0 + + + RxAutoSync_1 + RxFIFO auto sync on + 0x1 + + + + + RxFIFOFull_Sel + no description available + 19 + 2 + read-write + + + RxFIFOFull_Sel_0 + Full interrupt if at least 1 sample in Rx left and right FIFOs + 0 + + + RxFIFOFull_Sel_1 + Full interrupt if at least 4 sample in Rx left and right FIFOs + 0x1 + + + RxFIFOFull_Sel_2 + Full interrupt if at least 8 sample in Rx left and right FIFOs + 0x2 + + + RxFIFOFull_Sel_3 + Full interrupt if at least 16 sample in Rx left and right FIFO + 0x3 + + + + + RxFIFO_Rst + no description available + 21 + 1 + read-write + + + RxFIFO_Rst_0 + Normal operation + 0 + + + RxFIFO_Rst_1 + Reset register to 1 sample remaining + 0x1 + + + + + RxFIFO_Off_On + no description available + 22 + 1 + read-write + + + RxFIFO_Off_On_0 + SPDIF Rx FIFO is on + 0 + + + RxFIFO_Off_On_1 + SPDIF Rx FIFO is off. Does not accept data from interface + 0x1 + + + + + RxFIFO_Ctrl + no description available + 23 + 1 + read-write + + + RxFIFO_Ctrl_0 + Normal operation + 0 + + + RxFIFO_Ctrl_1 + Always read zero from Rx data register + 0x1 + + + + + + + SRCD + CDText Control Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + USyncMode + no description available + 1 + 1 + read-write + + + USyncMode_0 + Non-CD data + 0 + + + USyncMode_1 + CD user channel subcode + 0x1 + + + + + + + SRPC + PhaseConfig Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + GainSel + Gain selection: + 3 + 3 + read-write + + + GainSel_0 + 24*(2**10) + 0 + + + GainSel_1 + 16*(2**10) + 0x1 + + + GainSel_2 + 12*(2**10) + 0x2 + + + GainSel_3 + 8*(2**10) + 0x3 + + + GainSel_4 + 6*(2**10) + 0x4 + + + GainSel_5 + 4*(2**10) + 0x5 + + + GainSel_6 + 3*(2**10) + 0x6 + + + + + LOCK + LOCK bit to show that the internal DPLL is locked, read only + 6 + 1 + read-only + + + ClkSrc_Sel + Clock source selection, all other settings not shown are reserved: + 7 + 4 + read-write + + + ClkSrc_Sel_0 + if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) + 0 + + + ClkSrc_Sel_1 + if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) + 0x1 + + + ClkSrc_Sel_3 + if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK + 0x3 + + + ClkSrc_Sel_5 + REF_CLK_32K (XTALOSC) + 0x5 + + + ClkSrc_Sel_6 + tx_clk (SPDIF0_CLK_ROOT) + 0x6 + + + ClkSrc_Sel_8 + SPDIF_EXT_CLK + 0x8 + + + + + + + SIE + InterruptEn Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + RxFIFOFul + SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO. + 0 + 1 + read-write + + + TxEm + SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO. + 1 + 1 + read-write + + + LockLoss + SPDIF receiver loss of lock + 2 + 1 + read-write + + + RxFIFOResyn + Rx FIFO resync + 3 + 1 + read-write + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 4 + 1 + read-write + + + UQErr + U/Q Channel framing error + 5 + 1 + read-write + + + UQSync + U/Q Channel sync found + 6 + 1 + read-write + + + QRxOv + Q Channel receive register overrun + 7 + 1 + read-write + + + QRxFul + Q Channel receive register full, can't be cleared with reg + 8 + 1 + read-write + + + URxOv + U Channel receive register overrun + 9 + 1 + read-write + + + URxFul + U Channel receive register full, can't be cleared with reg + 10 + 1 + read-write + + + BitErr + SPDIF receiver found parity bit error + 14 + 1 + read-write + + + SymErr + SPDIF receiver found illegal symbol + 15 + 1 + read-write + + + ValNoGood + SPDIF validity flag no good + 16 + 1 + read-write + + + CNew + SPDIF receive change in value of control channel + 17 + 1 + read-write + + + TxResyn + SPDIF Tx FIFO resync + 18 + 1 + read-write + + + TxUnOv + SPDIF Tx FIFO under/overrun + 19 + 1 + read-write + + + Lock + SPDIF receiver's DPLL is locked + 20 + 1 + read-write + + + + + SIC + InterruptClear Register + SIC_SIS + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + LockLoss + SPDIF receiver loss of lock + 2 + 1 + write-only + + + RxFIFOResyn + Rx FIFO resync + 3 + 1 + write-only + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 4 + 1 + write-only + + + UQErr + U/Q Channel framing error + 5 + 1 + write-only + + + UQSync + U/Q Channel sync found + 6 + 1 + write-only + + + QRxOv + Q Channel receive register overrun + 7 + 1 + write-only + + + URxOv + U Channel receive register overrun + 9 + 1 + write-only + + + BitErr + SPDIF receiver found parity bit error + 14 + 1 + write-only + + + SymErr + SPDIF receiver found illegal symbol + 15 + 1 + write-only + + + ValNoGood + SPDIF validity flag no good + 16 + 1 + write-only + + + CNew + SPDIF receive change in value of control channel + 17 + 1 + write-only + + + TxResyn + SPDIF Tx FIFO resync + 18 + 1 + write-only + + + TxUnOv + SPDIF Tx FIFO under/overrun + 19 + 1 + write-only + + + Lock + SPDIF receiver's DPLL is locked + 20 + 1 + write-only + + + + + SIS + InterruptStat Register + SIC_SIS + 0x10 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + RxFIFOFul + SPDIF Rx FIFO full, can't be cleared with reg. IntClear. To clear it, read from Rx FIFO. + 0 + 1 + read-only + + + TxEm + SPDIF Tx FIFO empty, can't be cleared with reg. IntClear. To clear it, write toTx FIFO. + 1 + 1 + read-only + + + LockLoss + SPDIF receiver loss of lock + 2 + 1 + read-only + + + RxFIFOResyn + Rx FIFO resync + 3 + 1 + read-only + + + RxFIFOUnOv + Rx FIFO underrun/overrun + 4 + 1 + read-only + + + UQErr + U/Q Channel framing error + 5 + 1 + read-only + + + UQSync + U/Q Channel sync found + 6 + 1 + read-only + + + QRxOv + Q Channel receive register overrun + 7 + 1 + read-only + + + QRxFul + Q Channel receive register full, can't be cleared with reg + 8 + 1 + read-only + + + URxOv + U Channel receive register overrun + 9 + 1 + read-only + + + URxFul + U Channel receive register full, can't be cleared with reg + 10 + 1 + read-only + + + BitErr + SPDIF receiver found parity bit error + 14 + 1 + read-only + + + SymErr + SPDIF receiver found illegal symbol + 15 + 1 + read-only + + + ValNoGood + SPDIF validity flag no good + 16 + 1 + read-only + + + CNew + SPDIF receive change in value of control channel + 17 + 1 + read-only + + + TxResyn + SPDIF Tx FIFO resync + 18 + 1 + read-only + + + TxUnOv + SPDIF Tx FIFO under/overrun + 19 + 1 + read-only + + + Lock + SPDIF receiver's DPLL is locked + 20 + 1 + read-only + + + + + SRL + SPDIFRxLeft Register + 0x14 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxDataLeft + Processor receive SPDIF data left + 0 + 24 + read-only + + + + + SRR + SPDIFRxRight Register + 0x18 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxDataRight + Processor receive SPDIF data right + 0 + 24 + read-only + + + + + SRCSH + SPDIFRxCChannel_h Register + 0x1C + 32 + read-only + 0 + 0xFFFFFFFF + + + RxCChannel_h + SPDIF receive C channel register, contains first 24 bits of C channel without interpretation + 0 + 24 + read-only + + + + + SRCSL + SPDIFRxCChannel_l Register + 0x20 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxCChannel_l + SPDIF receive C channel register, contains next 24 bits of C channel without interpretation + 0 + 24 + read-only + + + + + SRU + UchannelRx Register + 0x24 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxUChannel + SPDIF receive U channel register, contains next 3 U channel bytes + 0 + 24 + read-only + + + + + SRQ + QchannelRx Register + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + RxQChannel + SPDIF receive Q channel register, contains next 3 Q channel bytes + 0 + 24 + read-only + + + + + STL + SPDIFTxLeft Register + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + TxDataLeft + SPDIF transmit left channel data. It is write-only, and always returns zeros when read + 0 + 24 + write-only + + + + + STR + SPDIFTxRight Register + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxDataRight + SPDIF transmit right channel data. It is write-only, and always returns zeros when read + 0 + 24 + write-only + + + + + STCSCH + SPDIFTxCChannelCons_h Register + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxCChannelCons_h + SPDIF transmit Cons + 0 + 24 + read-write + + + + + STCSCL + SPDIFTxCChannelCons_l Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + TxCChannelCons_l + SPDIF transmit Cons + 0 + 24 + read-write + + + + + SRFM + FreqMeas Register + 0x44 + 32 + read-only + 0 + 0xFFFFFFFF + + + FreqMeas + Frequency measurement data + 0 + 24 + read-only + + + + + STC + SPDIFTxClk Register + 0x50 + 32 + read-write + 0x20F00 + 0xFFFFFFFF + + + TxClk_DF + Divider factor (1-128) + 0 + 7 + read-write + + + TxClk_DF_0 + divider factor is 1 + 0 + + + TxClk_DF_1 + divider factor is 2 + 0x1 + + + TxClk_DF_127 + divider factor is 128 + 0x7F + + + + + tx_all_clk_en + Spdif transfer clock enable. When data is going to be transfered, this bit should be set to1. + 7 + 1 + read-write + + + tx_all_clk_en_0 + disable transfer clock. + 0 + + + tx_all_clk_en_1 + enable transfer clock. + 0x1 + + + + + TxClk_Source + no description available + 8 + 3 + read-write + + + TxClk_Source_0 + XTALOSC input (XTALOSC clock) + 0 + + + TxClk_Source_1 + tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) + 0x1 + + + TxClk_Source_2 + tx_clk1 (from SAI1) + 0x2 + + + TxClk_Source_3 + tx_clk2 SPDIF_EXT_CLK, from pads + 0x3 + + + TxClk_Source_4 + tx_clk3 (from SAI2) + 0x4 + + + TxClk_Source_5 + ipg_clk input (frequency divided) + 0x5 + + + TxClk_Source_6 + tx_clk4 (from SAI3) + 0x6 + + + + + SYSCLK_DF + system clock divider factor, 2~512. + 11 + 9 + read-write + + + SYSCLK_DF_0 + no clock signal + 0 + + + SYSCLK_DF_1 + divider factor is 2 + 0x1 + + + SYSCLK_DF_511 + divider factor is 512 + 0x1FF + + + + + + + + + SAI1 + I2S + I2S + I2S + 0x40384000 + + 0 + 0xE4 + registers + + + SAI1 + 56 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x3000000 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + FEATURE_0 + Standard feature set. + 0 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x50504 + 0xFFFFFFFF + + + DATALINE + Number of Datalines + 0 + 4 + read-only + + + FIFO + FIFO Size + 8 + 4 + read-only + + + FRAME + Frame Size + 16 + 4 + read-only + + + + + TCSR + SAI Transmit Control Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRDE + FIFO Request DMA Enable + 0 + 1 + read-write + + + FRDE_0 + Disables the DMA request. + 0 + + + FRDE_1 + Enables the DMA request. + 0x1 + + + + + FWDE + FIFO Warning DMA Enable + 1 + 1 + read-write + + + FWDE_0 + Disables the DMA request. + 0 + + + FWDE_1 + Enables the DMA request. + 0x1 + + + + + FRIE + FIFO Request Interrupt Enable + 8 + 1 + read-write + + + FRIE_0 + Disables the interrupt. + 0 + + + FRIE_1 + Enables the interrupt. + 0x1 + + + + + FWIE + FIFO Warning Interrupt Enable + 9 + 1 + read-write + + + FWIE_0 + Disables the interrupt. + 0 + + + FWIE_1 + Enables the interrupt. + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 10 + 1 + read-write + + + FEIE_0 + Disables the interrupt. + 0 + + + FEIE_1 + Enables the interrupt. + 0x1 + + + + + SEIE + Sync Error Interrupt Enable + 11 + 1 + read-write + + + SEIE_0 + Disables interrupt. + 0 + + + SEIE_1 + Enables interrupt. + 0x1 + + + + + WSIE + Word Start Interrupt Enable + 12 + 1 + read-write + + + WSIE_0 + Disables interrupt. + 0 + + + WSIE_1 + Enables interrupt. + 0x1 + + + + + FRF + FIFO Request Flag + 16 + 1 + read-only + + + FRF_0 + Transmit FIFO watermark has not been reached. + 0 + + + FRF_1 + Transmit FIFO watermark has been reached. + 0x1 + + + + + FWF + FIFO Warning Flag + 17 + 1 + read-only + + + FWF_0 + No enabled transmit FIFO is empty. + 0 + + + FWF_1 + Enabled transmit FIFO is empty. + 0x1 + + + + + FEF + FIFO Error Flag + 18 + 1 + read-write + oneToClear + + + FEF_0 + Transmit underrun not detected. + 0 + + + FEF_1 + Transmit underrun detected. + 0x1 + + + + + SEF + Sync Error Flag + 19 + 1 + read-write + oneToClear + + + SEF_0 + Sync error not detected. + 0 + + + SEF_1 + Frame sync error detected. + 0x1 + + + + + WSF + Word Start Flag + 20 + 1 + read-write + oneToClear + + + WSF_0 + Start of word not detected. + 0 + + + WSF_1 + Start of word detected. + 0x1 + + + + + SR + Software Reset + 24 + 1 + read-write + + + SR_0 + No effect. + 0 + + + SR_1 + Software reset. + 0x1 + + + + + FR + FIFO Reset + 25 + 1 + read-write + + + FR_0 + No effect. + 0 + + + FR_1 + FIFO reset. + 0x1 + + + + + BCE + Bit Clock Enable + 28 + 1 + read-write + + + BCE_0 + Transmit bit clock is disabled. + 0 + + + BCE_1 + Transmit bit clock is enabled. + 0x1 + + + + + DBGE + Debug Enable + 29 + 1 + read-write + + + DBGE_0 + Transmitter is disabled in Debug mode, after completing the current frame. + 0 + + + DBGE_1 + Transmitter is enabled in Debug mode. + 0x1 + + + + + STOPE + Stop Enable + 30 + 1 + read-write + + + STOPE_0 + Transmitter disabled in Stop mode. + 0 + + + STOPE_1 + Transmitter enabled in Stop mode. + 0x1 + + + + + TE + Transmitter Enable + 31 + 1 + read-write + + + TE_0 + Transmitter is disabled. + 0 + + + TE_1 + Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. + 0x1 + + + + + + + TCR1 + SAI Transmit Configuration 1 Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TFW + Transmit FIFO Watermark + 0 + 5 + read-write + + + + + TCR2 + SAI Transmit Configuration 2 Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIV + Bit Clock Divide + 0 + 8 + read-write + + + BCD + Bit Clock Direction + 24 + 1 + read-write + + + BCD_0 + Bit clock is generated externally in Slave mode. + 0 + + + BCD_1 + Bit clock is generated internally in Master mode. + 0x1 + + + + + BCP + Bit Clock Polarity + 25 + 1 + read-write + + + BCP_0 + Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. + 0 + + + BCP_1 + Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. + 0x1 + + + + + MSEL + MCLK Select + 26 + 2 + read-write + + + MSEL_0 + Bus Clock selected. + 0 + + + MSEL_1 + Master Clock (MCLK) 1 option selected. + 0x1 + + + MSEL_2 + Master Clock (MCLK) 2 option selected. + 0x2 + + + MSEL_3 + Master Clock (MCLK) 3 option selected. + 0x3 + + + + + BCI + Bit Clock Input + 28 + 1 + read-write + + + BCI_0 + No effect. + 0 + + + BCI_1 + Internal logic is clocked as if bit clock was externally generated. + 0x1 + + + + + BCS + Bit Clock Swap + 29 + 1 + read-write + + + BCS_0 + Use the normal bit clock source. + 0 + + + BCS_1 + Swap the bit clock source. + 0x1 + + + + + SYNC + Synchronous Mode + 30 + 2 + read-write + + + SYNC_0 + Asynchronous mode. + 0 + + + SYNC_1 + Synchronous with receiver. + 0x1 + + + + + + + TCR3 + SAI Transmit Configuration 3 Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDFL + Word Flag Configuration + 0 + 5 + read-write + + + TCE + Transmit Channel Enable + 16 + 4 + read-write + + + CFR + Channel FIFO Reset + 24 + 4 + read-write + + + + + TCR4 + SAI Transmit Configuration 4 Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + FSD + Frame Sync Direction + 0 + 1 + read-write + + + FSD_0 + Frame sync is generated externally in Slave mode. + 0 + + + FSD_1 + Frame sync is generated internally in Master mode. + 0x1 + + + + + FSP + Frame Sync Polarity + 1 + 1 + read-write + + + FSP_0 + Frame sync is active high. + 0 + + + FSP_1 + Frame sync is active low. + 0x1 + + + + + ONDEM + On Demand Mode + 2 + 1 + read-write + + + ONDEM_0 + Internal frame sync is generated continuously. + 0 + + + ONDEM_1 + Internal frame sync is generated when the FIFO warning flag is clear. + 0x1 + + + + + FSE + Frame Sync Early + 3 + 1 + read-write + + + FSE_0 + Frame sync asserts with the first bit of the frame. + 0 + + + FSE_1 + Frame sync asserts one bit before the first bit of the frame. + 0x1 + + + + + MF + MSB First + 4 + 1 + read-write + + + MF_0 + LSB is transmitted first. + 0 + + + MF_1 + MSB is transmitted first. + 0x1 + + + + + CHMOD + Channel Mode + 5 + 1 + read-write + + + CHMOD_0 + TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. + 0 + + + CHMOD_1 + Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. + 0x1 + + + + + SYWD + Sync Width + 8 + 5 + read-write + + + FRSZ + Frame size + 16 + 5 + read-write + + + FPACK + FIFO Packing Mode + 24 + 2 + read-write + + + FPACK_0 + FIFO packing is disabled + 0 + + + FPACK_2 + 8-bit FIFO packing is enabled + 0x2 + + + FPACK_3 + 16-bit FIFO packing is enabled + 0x3 + + + + + FCOMB + FIFO Combine Mode + 26 + 2 + read-write + + + FCOMB_0 + FIFO combine mode disabled. + 0 + + + FCOMB_1 + FIFO combine mode enabled on FIFO reads (from transmit shift registers). + 0x1 + + + FCOMB_2 + FIFO combine mode enabled on FIFO writes (by software). + 0x2 + + + FCOMB_3 + FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). + 0x3 + + + + + FCONT + FIFO Continue on Error + 28 + 1 + read-write + + + FCONT_0 + On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + 0 + + + FCONT_1 + On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + 0x1 + + + + + + + TCR5 + SAI Transmit Configuration 5 Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + FBT + First Bit Shifted + 8 + 5 + read-write + + + W0W + Word 0 Width + 16 + 5 + read-write + + + WNW + Word N Width + 24 + 5 + read-write + + + + + 4 + 0x4 + TDR[%s] + SAI Transmit Data Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDR + Transmit Data Register + 0 + 32 + read-write + + + + + 4 + 0x4 + TFR[%s] + SAI Transmit FIFO Register + 0x40 + 32 + read-only + 0 + 0xFFFFFFFF + + + RFP + Read FIFO Pointer + 0 + 6 + read-only + + + WFP + Write FIFO Pointer + 16 + 6 + read-only + + + WCP + Write Channel Pointer + 31 + 1 + read-only + + + WCP_0 + No effect. + 0 + + + WCP_1 + FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. + 0x1 + + + + + + + TMR + SAI Transmit Mask Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + TWM + Transmit Word Mask + 0 + 32 + read-write + + + TWM_0 + Word N is enabled. + 0 + + + TWM_1 + Word N is masked. The transmit data pins are tri-stated or drive zero when masked. + 0x1 + + + + + + + RCSR + SAI Receive Control Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + FRDE + FIFO Request DMA Enable + 0 + 1 + read-write + + + FRDE_0 + Disables the DMA request. + 0 + + + FRDE_1 + Enables the DMA request. + 0x1 + + + + + FWDE + FIFO Warning DMA Enable + 1 + 1 + read-write + + + FWDE_0 + Disables the DMA request. + 0 + + + FWDE_1 + Enables the DMA request. + 0x1 + + + + + FRIE + FIFO Request Interrupt Enable + 8 + 1 + read-write + + + FRIE_0 + Disables the interrupt. + 0 + + + FRIE_1 + Enables the interrupt. + 0x1 + + + + + FWIE + FIFO Warning Interrupt Enable + 9 + 1 + read-write + + + FWIE_0 + Disables the interrupt. + 0 + + + FWIE_1 + Enables the interrupt. + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 10 + 1 + read-write + + + FEIE_0 + Disables the interrupt. + 0 + + + FEIE_1 + Enables the interrupt. + 0x1 + + + + + SEIE + Sync Error Interrupt Enable + 11 + 1 + read-write + + + SEIE_0 + Disables interrupt. + 0 + + + SEIE_1 + Enables interrupt. + 0x1 + + + + + WSIE + Word Start Interrupt Enable + 12 + 1 + read-write + + + WSIE_0 + Disables interrupt. + 0 + + + WSIE_1 + Enables interrupt. + 0x1 + + + + + FRF + FIFO Request Flag + 16 + 1 + read-only + + + FRF_0 + Receive FIFO watermark not reached. + 0 + + + FRF_1 + Receive FIFO watermark has been reached. + 0x1 + + + + + FWF + FIFO Warning Flag + 17 + 1 + read-only + + + FWF_0 + No enabled receive FIFO is full. + 0 + + + FWF_1 + Enabled receive FIFO is full. + 0x1 + + + + + FEF + FIFO Error Flag + 18 + 1 + read-write + oneToClear + + + FEF_0 + Receive overflow not detected. + 0 + + + FEF_1 + Receive overflow detected. + 0x1 + + + + + SEF + Sync Error Flag + 19 + 1 + read-write + oneToClear + + + SEF_0 + Sync error not detected. + 0 + + + SEF_1 + Frame sync error detected. + 0x1 + + + + + WSF + Word Start Flag + 20 + 1 + read-write + oneToClear + + + WSF_0 + Start of word not detected. + 0 + + + WSF_1 + Start of word detected. + 0x1 + + + + + SR + Software Reset + 24 + 1 + read-write + + + SR_0 + No effect. + 0 + + + SR_1 + Software reset. + 0x1 + + + + + FR + FIFO Reset + 25 + 1 + read-write + + + FR_0 + No effect. + 0 + + + FR_1 + FIFO reset. + 0x1 + + + + + BCE + Bit Clock Enable + 28 + 1 + read-write + + + BCE_0 + Receive bit clock is disabled. + 0 + + + BCE_1 + Receive bit clock is enabled. + 0x1 + + + + + DBGE + Debug Enable + 29 + 1 + read-write + + + DBGE_0 + Receiver is disabled in Debug mode, after completing the current frame. + 0 + + + DBGE_1 + Receiver is enabled in Debug mode. + 0x1 + + + + + STOPE + Stop Enable + 30 + 1 + read-write + + + STOPE_0 + Receiver disabled in Stop mode. + 0 + + + STOPE_1 + Receiver enabled in Stop mode. + 0x1 + + + + + RE + Receiver Enable + 31 + 1 + read-write + + + RE_0 + Receiver is disabled. + 0 + + + RE_1 + Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. + 0x1 + + + + + + + RCR1 + SAI Receive Configuration 1 Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + RFW + Receive FIFO Watermark + 0 + 5 + read-write + + + + + RCR2 + SAI Receive Configuration 2 Register + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIV + Bit Clock Divide + 0 + 8 + read-write + + + BCD + Bit Clock Direction + 24 + 1 + read-write + + + BCD_0 + Bit clock is generated externally in Slave mode. + 0 + + + BCD_1 + Bit clock is generated internally in Master mode. + 0x1 + + + + + BCP + Bit Clock Polarity + 25 + 1 + read-write + + + BCP_0 + Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. + 0 + + + BCP_1 + Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. + 0x1 + + + + + MSEL + MCLK Select + 26 + 2 + read-write + + + MSEL_0 + Bus Clock selected. + 0 + + + MSEL_1 + Master Clock (MCLK) 1 option selected. + 0x1 + + + MSEL_2 + Master Clock (MCLK) 2 option selected. + 0x2 + + + MSEL_3 + Master Clock (MCLK) 3 option selected. + 0x3 + + + + + BCI + Bit Clock Input + 28 + 1 + read-write + + + BCI_0 + No effect. + 0 + + + BCI_1 + Internal logic is clocked as if bit clock was externally generated. + 0x1 + + + + + BCS + Bit Clock Swap + 29 + 1 + read-write + + + BCS_0 + Use the normal bit clock source. + 0 + + + BCS_1 + Swap the bit clock source. + 0x1 + + + + + SYNC + Synchronous Mode + 30 + 2 + read-write + + + SYNC_0 + Asynchronous mode. + 0 + + + SYNC_1 + Synchronous with transmitter. + 0x1 + + + + + + + RCR3 + SAI Receive Configuration 3 Register + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + WDFL + Word Flag Configuration + 0 + 5 + read-write + + + RCE + Receive Channel Enable + 16 + 4 + read-write + + + CFR + Channel FIFO Reset + 24 + 4 + read-write + + + + + RCR4 + SAI Receive Configuration 4 Register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + FSD + Frame Sync Direction + 0 + 1 + read-write + + + FSD_0 + Frame Sync is generated externally in Slave mode. + 0 + + + FSD_1 + Frame Sync is generated internally in Master mode. + 0x1 + + + + + FSP + Frame Sync Polarity + 1 + 1 + read-write + + + FSP_0 + Frame sync is active high. + 0 + + + FSP_1 + Frame sync is active low. + 0x1 + + + + + ONDEM + On Demand Mode + 2 + 1 + read-write + + + ONDEM_0 + Internal frame sync is generated continuously. + 0 + + + ONDEM_1 + Internal frame sync is generated when the FIFO warning flag is clear. + 0x1 + + + + + FSE + Frame Sync Early + 3 + 1 + read-write + + + FSE_0 + Frame sync asserts with the first bit of the frame. + 0 + + + FSE_1 + Frame sync asserts one bit before the first bit of the frame. + 0x1 + + + + + MF + MSB First + 4 + 1 + read-write + + + MF_0 + LSB is received first. + 0 + + + MF_1 + MSB is received first. + 0x1 + + + + + SYWD + Sync Width + 8 + 5 + read-write + + + FRSZ + Frame Size + 16 + 5 + read-write + + + FPACK + FIFO Packing Mode + 24 + 2 + read-write + + + FPACK_0 + FIFO packing is disabled + 0 + + + FPACK_2 + 8-bit FIFO packing is enabled + 0x2 + + + FPACK_3 + 16-bit FIFO packing is enabled + 0x3 + + + + + FCOMB + FIFO Combine Mode + 26 + 2 + read-write + + + FCOMB_0 + FIFO combine mode disabled. + 0 + + + FCOMB_1 + FIFO combine mode enabled on FIFO writes (from receive shift registers). + 0x1 + + + FCOMB_2 + FIFO combine mode enabled on FIFO reads (by software). + 0x2 + + + FCOMB_3 + FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). + 0x3 + + + + + FCONT + FIFO Continue on Error + 28 + 1 + read-write + + + FCONT_0 + On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. + 0 + + + FCONT_1 + On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. + 0x1 + + + + + + + RCR5 + SAI Receive Configuration 5 Register + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + FBT + First Bit Shifted + 8 + 5 + read-write + + + W0W + Word 0 Width + 16 + 5 + read-write + + + WNW + Word N Width + 24 + 5 + read-write + + + + + 4 + 0x4 + RDR[%s] + SAI Receive Data Register + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RDR + Receive Data Register + 0 + 32 + read-only + + + + + 4 + 0x4 + RFR[%s] + SAI Receive FIFO Register + 0xC0 + 32 + read-only + 0 + 0xFFFFFFFF + + + RFP + Read FIFO Pointer + 0 + 6 + read-only + + + RCP + Receive Channel Pointer + 15 + 1 + read-only + + + RCP_0 + No effect. + 0 + + + RCP_1 + FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. + 0x1 + + + + + WFP + Write FIFO Pointer + 16 + 6 + read-only + + + + + RMR + SAI Receive Mask Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + RWM + Receive Word Mask + 0 + 32 + read-write + + + RWM_0 + Word N is enabled. + 0 + + + RWM_1 + Word N is masked. + 0x1 + + + + + + + + + SAI2 + I2S + I2S + 0x40388000 + + 0 + 0xE4 + registers + + + SAI2 + 57 + + + + SAI3 + I2S + I2S + 0x4038C000 + + 0 + 0xE4 + registers + + + SAI3_RX + 58 + + + SAI3_TX + 59 + + + + LPSPI1 + LPSPI + LPSPI + LPSPI + 0x40394000 + + 0 + 0x78 + registers + + + LPSPI1 + 32 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x1020004 + 0xFFFFFFFF + + + FEATURE + Module Identification Number + 0 + 16 + read-only + + + FEATURE_4 + Standard feature set supporting a 32-bit shift register. + 0x4 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x40404 + 0xFFFFFFFF + + + TXFIFO + Transmit FIFO Size + 0 + 8 + read-only + + + RXFIFO + Receive FIFO Size + 8 + 8 + read-only + + + PCSNUM + PCS Number + 16 + 8 + read-only + + + + + CR + Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEN + Module Enable + 0 + 1 + read-write + + + MEN_0 + Module is disabled + 0 + + + MEN_1 + Module is enabled + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + RST_0 + Module is not reset + 0 + + + RST_1 + Module is reset + 0x1 + + + + + DOZEN + Doze mode enable + 2 + 1 + read-write + + + DOZEN_0 + Module is enabled in Doze mode + 0 + + + DOZEN_1 + Module is disabled in Doze mode + 0x1 + + + + + DBGEN + Debug Enable + 3 + 1 + read-write + + + DBGEN_0 + Module is disabled in debug mode + 0 + + + DBGEN_1 + Module is enabled in debug mode + 0x1 + + + + + RTF + Reset Transmit FIFO + 8 + 1 + write-only + + + RTF_0 + No effect + 0 + + + RTF_1 + Transmit FIFO is reset + 0x1 + + + + + RRF + Reset Receive FIFO + 9 + 1 + write-only + + + RRF_0 + No effect + 0 + + + RRF_1 + Receive FIFO is reset + 0x1 + + + + + + + SR + Status Register + 0x14 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + TDF + Transmit Data Flag + 0 + 1 + read-only + + + TDF_0 + Transmit data not requested + 0 + + + TDF_1 + Transmit data is requested + 0x1 + + + + + RDF + Receive Data Flag + 1 + 1 + read-only + + + RDF_0 + Receive Data is not ready + 0 + + + RDF_1 + Receive data is ready + 0x1 + + + + + WCF + Word Complete Flag + 8 + 1 + read-write + oneToClear + + + WCF_0 + Transfer of a received word has not yet completed + 0 + + + WCF_1 + Transfer of a received word has completed + 0x1 + + + + + FCF + Frame Complete Flag + 9 + 1 + read-write + oneToClear + + + FCF_0 + Frame transfer has not completed + 0 + + + FCF_1 + Frame transfer has completed + 0x1 + + + + + TCF + Transfer Complete Flag + 10 + 1 + read-write + oneToClear + + + TCF_0 + All transfers have not completed + 0 + + + TCF_1 + All transfers have completed + 0x1 + + + + + TEF + Transmit Error Flag + 11 + 1 + read-write + oneToClear + + + TEF_0 + Transmit FIFO underrun has not occurred + 0 + + + TEF_1 + Transmit FIFO underrun has occurred + 0x1 + + + + + REF + Receive Error Flag + 12 + 1 + read-write + oneToClear + + + REF_0 + Receive FIFO has not overflowed + 0 + + + REF_1 + Receive FIFO has overflowed + 0x1 + + + + + DMF + Data Match Flag + 13 + 1 + read-write + oneToClear + + + DMF_0 + Have not received matching data + 0 + + + DMF_1 + Have received matching data + 0x1 + + + + + MBF + Module Busy Flag + 24 + 1 + read-only + + + MBF_0 + LPSPI is idle + 0 + + + MBF_1 + LPSPI is busy + 0x1 + + + + + + + IER + Interrupt Enable Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDIE + Transmit Data Interrupt Enable + 0 + 1 + read-write + + + TDIE_0 + Disabled + 0 + + + TDIE_1 + Enabled + 0x1 + + + + + RDIE + Receive Data Interrupt Enable + 1 + 1 + read-write + + + RDIE_0 + Disabled + 0 + + + RDIE_1 + Enabled + 0x1 + + + + + WCIE + Word Complete Interrupt Enable + 8 + 1 + read-write + + + WCIE_0 + Disabled + 0 + + + WCIE_1 + Enabled + 0x1 + + + + + FCIE + Frame Complete Interrupt Enable + 9 + 1 + read-write + + + FCIE_0 + Disabled + 0 + + + FCIE_1 + Enabled + 0x1 + + + + + TCIE + Transfer Complete Interrupt Enable + 10 + 1 + read-write + + + TCIE_0 + Disabled + 0 + + + TCIE_1 + Enabled + 0x1 + + + + + TEIE + Transmit Error Interrupt Enable + 11 + 1 + read-write + + + TEIE_0 + Disabled + 0 + + + TEIE_1 + Enabled + 0x1 + + + + + REIE + Receive Error Interrupt Enable + 12 + 1 + read-write + + + REIE_0 + Disabled + 0 + + + REIE_1 + Enabled + 0x1 + + + + + DMIE + Data Match Interrupt Enable + 13 + 1 + read-write + + + DMIE_0 + Disabled + 0 + + + DMIE_1 + Enabled + 0x1 + + + + + + + DER + DMA Enable Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TDDE + Transmit Data DMA Enable + 0 + 1 + read-write + + + TDDE_0 + DMA request is disabled + 0 + + + TDDE_1 + DMA request is enabled + 0x1 + + + + + RDDE + Receive Data DMA Enable + 1 + 1 + read-write + + + RDDE_0 + DMA request is disabled + 0 + + + RDDE_1 + DMA request is enabled + 0x1 + + + + + + + CFGR0 + Configuration Register 0 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + HREN + Host Request Enable + 0 + 1 + read-write + + + HREN_0 + Host request is disabled + 0 + + + HREN_1 + Host request is enabled + 0x1 + + + + + HRPOL + Host Request Polarity + 1 + 1 + read-write + + + HRPOL_0 + Active low + 0 + + + HRPOL_1 + Active high + 0x1 + + + + + HRSEL + Host Request Select + 2 + 1 + read-write + + + HRSEL_0 + Host request input is the LPSPI_HREQ pin + 0 + + + HRSEL_1 + Host request input is the input trigger + 0x1 + + + + + CIRFIFO + Circular FIFO Enable + 8 + 1 + read-write + + + CIRFIFO_0 + Circular FIFO is disabled + 0 + + + CIRFIFO_1 + Circular FIFO is enabled + 0x1 + + + + + RDMO + Receive Data Match Only + 9 + 1 + read-write + + + RDMO_0 + Received data is stored in the receive FIFO as in normal operations + 0 + + + RDMO_1 + Received data is discarded unless the Data Match Flag (DMF) is set + 0x1 + + + + + + + CFGR1 + Configuration Register 1 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASTER + Master Mode + 0 + 1 + read-write + + + MASTER_0 + Slave mode + 0 + + + MASTER_1 + Master mode + 0x1 + + + + + SAMPLE + Sample Point + 1 + 1 + read-write + + + SAMPLE_0 + Input data is sampled on SCK edge + 0 + + + SAMPLE_1 + Input data is sampled on delayed SCK edge + 0x1 + + + + + AUTOPCS + Automatic PCS + 2 + 1 + read-write + + + AUTOPCS_0 + Automatic PCS generation is disabled + 0 + + + AUTOPCS_1 + Automatic PCS generation is enabled + 0x1 + + + + + NOSTALL + No Stall + 3 + 1 + read-write + + + NOSTALL_0 + Transfers will stall when the transmit FIFO is empty or the receive FIFO is full + 0 + + + NOSTALL_1 + Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur + 0x1 + + + + + PCSPOL + Peripheral Chip Select Polarity + 8 + 4 + read-write + + + PCSPOL_0 + The Peripheral Chip Select pin PCSx is active low + 0 + + + PCSPOL_1 + The Peripheral Chip Select pin PCSx is active high + 0x1 + + + + + MATCFG + Match Configuration + 16 + 3 + read-write + + + MATCFG_0 + Match is disabled + 0 + + + MATCFG_2 + 010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) + 0x2 + + + MATCFG_3 + 011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) + 0x3 + + + MATCFG_4 + 100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] + 0x4 + + + MATCFG_5 + 101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] + 0x5 + + + MATCFG_6 + 110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] + 0x6 + + + MATCFG_7 + 111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] + 0x7 + + + + + PINCFG + Pin Configuration + 24 + 2 + read-write + + + PINCFG_0 + SIN is used for input data and SOUT is used for output data + 0 + + + PINCFG_1 + SIN is used for both input and output data + 0x1 + + + PINCFG_2 + SOUT is used for both input and output data + 0x2 + + + PINCFG_3 + SOUT is used for input data and SIN is used for output data + 0x3 + + + + + OUTCFG + Output Config + 26 + 1 + read-write + + + OUTCFG_0 + Output data retains last value when chip select is negated + 0 + + + OUTCFG_1 + Output data is tristated when chip select is negated + 0x1 + + + + + PCSCFG + Peripheral Chip Select Configuration + 27 + 1 + read-write + + + PCSCFG_0 + PCS[3:2] are enabled + 0 + + + PCSCFG_1 + PCS[3:2] are disabled + 0x1 + + + + + + + DMR0 + Data Match Register 0 + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCH0 + Match 0 Value + 0 + 32 + read-write + + + + + DMR1 + Data Match Register 1 + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCH1 + Match 1 Value + 0 + 32 + read-write + + + + + CCR + Clock Configuration Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + SCKDIV + SCK Divider + 0 + 8 + read-write + + + DBT + Delay Between Transfers + 8 + 8 + read-write + + + PCSSCK + PCS-to-SCK Delay + 16 + 8 + read-write + + + SCKPCS + SCK-to-PCS Delay + 24 + 8 + read-write + + + + + FCR + FIFO Control Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXWATER + Transmit FIFO Watermark + 0 + 4 + read-write + + + RXWATER + Receive FIFO Watermark + 16 + 4 + read-write + + + + + FSR + FIFO Status Register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXCOUNT + Transmit FIFO Count + 0 + 5 + read-only + + + RXCOUNT + Receive FIFO Count + 16 + 5 + read-only + + + + + TCR + Transmit Command Register + 0x60 + 32 + read-write + 0x1F + 0xFFFFFFFF + + + FRAMESZ + Frame Size + 0 + 12 + read-write + + + WIDTH + Transfer Width + 16 + 2 + read-write + + + WIDTH_0 + 1 bit transfer + 0 + + + WIDTH_1 + 2 bit transfer + 0x1 + + + WIDTH_2 + 4 bit transfer + 0x2 + + + + + TXMSK + Transmit Data Mask + 18 + 1 + read-write + + + TXMSK_0 + Normal transfer + 0 + + + TXMSK_1 + Mask transmit data + 0x1 + + + + + RXMSK + Receive Data Mask + 19 + 1 + read-write + + + RXMSK_0 + Normal transfer + 0 + + + RXMSK_1 + Receive data is masked + 0x1 + + + + + CONTC + Continuing Command + 20 + 1 + read-write + + + CONTC_0 + Command word for start of new transfer + 0 + + + CONTC_1 + Command word for continuing transfer + 0x1 + + + + + CONT + Continuous Transfer + 21 + 1 + read-write + + + CONT_0 + Continuous transfer is disabled + 0 + + + CONT_1 + Continuous transfer is enabled + 0x1 + + + + + BYSW + Byte Swap + 22 + 1 + read-write + + + BYSW_0 + Byte swap is disabled + 0 + + + BYSW_1 + Byte swap is enabled + 0x1 + + + + + LSBF + LSB First + 23 + 1 + read-write + + + LSBF_0 + Data is transferred MSB first + 0 + + + LSBF_1 + Data is transferred LSB first + 0x1 + + + + + PCS + Peripheral Chip Select + 24 + 2 + read-write + + + PCS_0 + Transfer using LPSPI_PCS[0] + 0 + + + PCS_1 + Transfer using LPSPI_PCS[1] + 0x1 + + + PCS_2 + Transfer using LPSPI_PCS[2] + 0x2 + + + PCS_3 + Transfer using LPSPI_PCS[3] + 0x3 + + + + + PRESCALE + Prescaler Value + 27 + 3 + read-write + + + PRESCALE_0 + Divide by 1 + 0 + + + PRESCALE_1 + Divide by 2 + 0x1 + + + PRESCALE_2 + Divide by 4 + 0x2 + + + PRESCALE_3 + Divide by 8 + 0x3 + + + PRESCALE_4 + Divide by 16 + 0x4 + + + PRESCALE_5 + Divide by 32 + 0x5 + + + PRESCALE_6 + Divide by 64 + 0x6 + + + PRESCALE_7 + Divide by 128 + 0x7 + + + + + CPHA + Clock Phase + 30 + 1 + read-write + + + CPHA_0 + Data is captured on the leading edge of SCK and changed on the following edge of SCK + 0 + + + CPHA_1 + Data is changed on the leading edge of SCK and captured on the following edge of SCK + 0x1 + + + + + CPOL + Clock Polarity + 31 + 1 + read-write + + + CPOL_0 + The inactive state value of SCK is low + 0 + + + CPOL_1 + The inactive state value of SCK is high + 0x1 + + + + + + + TDR + Transmit Data Register + 0x64 + 32 + write-only + 0 + 0xFFFFFFFF + + + DATA + Transmit Data + 0 + 32 + write-only + + + + + RSR + Receive Status Register + 0x70 + 32 + read-only + 0x2 + 0xFFFFFFFF + + + SOF + Start Of Frame + 0 + 1 + read-only + + + SOF_0 + Subsequent data word received after LPSPI_PCS assertion + 0 + + + SOF_1 + First data word received after LPSPI_PCS assertion + 0x1 + + + + + RXEMPTY + RX FIFO Empty + 1 + 1 + read-only + + + RXEMPTY_0 + RX FIFO is not empty + 0 + + + RXEMPTY_1 + RX FIFO is empty + 0x1 + + + + + + + RDR + Receive Data Register + 0x74 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA + Receive Data + 0 + 32 + read-only + + + + + + + LPSPI2 + LPSPI + LPSPI + 0x40398000 + + 0 + 0x78 + registers + + + LPSPI2 + 33 + + + + LPSPI3 + LPSPI + LPSPI + 0x4039C000 + + 0 + 0x78 + registers + + + LPSPI3 + 34 + + + + LPSPI4 + LPSPI + LPSPI + 0x403A0000 + + 0 + 0x78 + registers + + + LPSPI4 + 35 + + + + ADC_ETC + ADC_ETC + ADC_ETC + 0x403B0000 + + 0 + 0x150 + registers + + + ADC_ETC_IRQ0 + 118 + + + ADC_ETC_IRQ1 + 119 + + + ADC_ETC_IRQ2 + 120 + + + ADC_ETC_ERROR_IRQ + 121 + + + + CTRL + ADC_ETC Global Control Register + 0 + 32 + read-write + 0xC0000000 + 0xFFFFFFFF + + + TRIG_ENABLE + TRIG enable register + 0 + 8 + read-write + + + EXT0_TRIG_ENABLE + TSC0 TRIG enable register. 1'b1: enable external TSC0 trigger. 1'b0: disable external TSC0 trigger. + 8 + 1 + read-write + + + EXT0_TRIG_PRIORITY + External TSC0 trigger priority, 7 is Highest, 0 is lowest . + 9 + 3 + read-write + + + EXT1_TRIG_ENABLE + TSC1 TRIG enable register. 1'b1: enable external TSC1 trigger. 1'b0: disable external TSC1 trigger. + 12 + 1 + read-write + + + EXT1_TRIG_PRIORITY + External TSC1 trigger priority, 7 is Highest, 0 is lowest . + 13 + 3 + read-write + + + PRE_DIVIDER + Pre-divider for trig delay and interval . + 16 + 8 + read-write + + + DMA_MODE_SEL + 1'b0: Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared + 29 + 1 + read-write + + + TSC_BYPASS + 1'b1: TSC is bypassed to ADC2. 1'b0: TSC not bypassed. To use ADC2, this bit should be cleared. + 30 + 1 + read-write + + + SOFTRST + Software reset, high active. When write 1 ,all logical will be reset. + 31 + 1 + read-write + + + + + DONE0_1_IRQ + ETC DONE0 and DONE1 IRQ State Register + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIG0_DONE0 + TRIG0 done0 interrupt detection + 0 + 1 + read-write + + + TRIG1_DONE0 + TRIG1 done0 interrupt detection + 1 + 1 + read-write + + + TRIG2_DONE0 + TRIG2 done0 interrupt detection + 2 + 1 + read-write + + + TRIG3_DONE0 + TRIG3 done0 interrupt detection + 3 + 1 + read-write + + + TRIG4_DONE0 + TRIG4 done0 interrupt detection + 4 + 1 + read-write + + + TRIG5_DONE0 + TRIG5 done0 interrupt detection + 5 + 1 + read-write + + + TRIG6_DONE0 + TRIG6 done0 interrupt detection + 6 + 1 + read-write + + + TRIG7_DONE0 + TRIG7 done0 interrupt detection + 7 + 1 + read-write + + + TRIG0_DONE1 + TRIG0 done1 interrupt detection + 16 + 1 + read-write + + + TRIG1_DONE1 + TRIG1 done1 interrupt detection + 17 + 1 + read-write + + + TRIG2_DONE1 + TRIG2 done1 interrupt detection + 18 + 1 + read-write + + + TRIG3_DONE1 + TRIG3 done1 interrupt detection + 19 + 1 + read-write + + + TRIG4_DONE1 + TRIG4 done1 interrupt detection + 20 + 1 + read-write + + + TRIG5_DONE1 + TRIG5 done1 interrupt detection + 21 + 1 + read-write + + + TRIG6_DONE1 + TRIG6 done1 interrupt detection + 22 + 1 + read-write + + + TRIG7_DONE1 + TRIG7 done1 interrupt detection + 23 + 1 + read-write + + + + + DONE2_ERR_IRQ + ETC DONE_2 and DONE_ERR IRQ State Register + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIG0_DONE2 + TRIG0 done2 interrupt detection + 0 + 1 + read-write + + + TRIG1_DONE2 + TRIG1 done2 interrupt detection + 1 + 1 + read-write + + + TRIG2_DONE2 + TRIG2 done2 interrupt detection + 2 + 1 + read-write + + + TRIG3_DONE2 + TRIG3 done2 interrupt detection + 3 + 1 + read-write + + + TRIG4_DONE2 + TRIG4 done2 interrupt detection + 4 + 1 + read-write + + + TRIG5_DONE2 + TRIG5 done2 interrupt detection + 5 + 1 + read-write + + + TRIG6_DONE2 + TRIG6 done2 interrupt detection + 6 + 1 + read-write + + + TRIG7_DONE2 + TRIG7 done2 interrupt detection + 7 + 1 + read-write + + + TRIG0_ERR + TRIG0 error interrupt detection + 16 + 1 + read-write + + + TRIG1_ERR + TRIG1 error interrupt detection + 17 + 1 + read-write + + + TRIG2_ERR + TRIG2 error interrupt detection + 18 + 1 + read-write + + + TRIG3_ERR + TRIG3 error interrupt detection + 19 + 1 + read-write + + + TRIG4_ERR + TRIG4 error interrupt detection + 20 + 1 + read-write + + + TRIG5_ERR + TRIG5 error interrupt detection + 21 + 1 + read-write + + + TRIG6_ERR + TRIG6 error interrupt detection + 22 + 1 + read-write + + + TRIG7_ERR + TRIG7 error interrupt detection + 23 + 1 + read-write + + + + + DMA_CTRL + ETC DMA control Register + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIG0_ENABLE + When TRIG0 done enable DMA request + 0 + 1 + read-write + + + TRIG1_ENABLE + When TRIG1 done enable DMA request + 1 + 1 + read-write + + + TRIG2_ENABLE + When TRIG2 done enable DMA request + 2 + 1 + read-write + + + TRIG3_ENABLE + When TRIG3 done enable DMA request + 3 + 1 + read-write + + + TRIG4_ENABLE + When TRIG4 done enable DMA request + 4 + 1 + read-write + + + TRIG5_ENABLE + When TRIG5 done enable DMA request + 5 + 1 + read-write + + + TRIG6_ENABLE + When TRIG6 done enable DMA request + 6 + 1 + read-write + + + TRIG7_ENABLE + When TRIG7 done enable DMA request + 7 + 1 + read-write + + + TRIG0_REQ + When TRIG0 done DMA request detection + 16 + 1 + read-write + + + TRIG1_REQ + When TRIG1 done DMA request detection + 17 + 1 + read-write + + + TRIG2_REQ + When TRIG2 done DMA request detection + 18 + 1 + read-write + + + TRIG3_REQ + When TRIG3 done DMA request detection + 19 + 1 + read-write + + + TRIG4_REQ + When TRIG4 done DMA request detection + 20 + 1 + read-write + + + TRIG5_REQ + When TRIG5 done DMA request detection + 21 + 1 + read-write + + + TRIG6_REQ + When TRIG6 done DMA request detection + 22 + 1 + read-write + + + TRIG7_REQ + When TRIG7 done DMA request detection + 23 + 1 + read-write + + + + + TRIG0_CTRL + ETC_TRIG0 Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER. This register is self-clearing. + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG0_COUNTER + ETC_TRIG0 Counter Register + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG0_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection. For more information, see the ADC chapter. + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection. For more information, see the ADC chapter. + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG0_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG0_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG0_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG0_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0x28 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG0_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0x2C + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG0_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0x30 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG0_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0x34 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + TRIG1_CTRL + ETC_TRIG1 Control Register + 0x38 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER. This register is self-clearing. + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG1_COUNTER + ETC_TRIG1 Counter Register + 0x3C + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG1_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG1_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG1_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG1_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x4C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG1_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0x50 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG1_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0x54 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG1_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0x58 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG1_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + TRIG2_CTRL + ETC_TRIG2 Control Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER. This register is self-clearing. + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG2_COUNTER + ETC_TRIG2 Counter Register + 0x64 + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG2_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x68 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG2_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x6C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG2_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x70 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG2_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x74 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG2_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0x78 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG2_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0x7C + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG2_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0x80 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG2_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0x84 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + TRIG3_CTRL + ETC_TRIG3 Control Register + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER. This register is self-clearing. + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG3_COUNTER + ETC_TRIG3 Counter Register + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG3_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG3_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x94 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG3_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x98 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG3_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x9C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG3_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0xA0 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG3_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0xA4 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG3_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0xA8 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG3_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0xAC + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + TRIG4_CTRL + ETC_TRIG4 Control Register + 0xB0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER. This register is self-clearing. + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG4_COUNTER + ETC_TRIG4 Counter Register + 0xB4 + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG4_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0xB8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG4_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0xBC + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG4_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0xC0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG4_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0xC4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG4_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0xC8 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG4_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0xCC + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG4_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0xD0 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG4_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0xD4 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + TRIG5_CTRL + ETC_TRIG5 Control Register + 0xD8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG5_COUNTER + ETC_TRIG5 Counter Register + 0xDC + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG5_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0xE0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG5_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0xE4 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG5_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0xE8 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG5_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0xEC + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG5_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0xF0 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG5_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0xF4 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG5_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0xF8 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG5_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0xFC + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + TRIG6_CTRL + ETC_TRIG6 Control Register + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER. This register is self-clearing. + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG6_COUNTER + ETC_TRIG6 Counter Register + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG6_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG6_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG6_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG6_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG6_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0x118 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG6_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0x11C + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG6_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0x120 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG6_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0x124 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + TRIG7_CTRL + ETC_TRIG7 Control Register + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + SW_TRIG + Software write 1 as the TRIGGER. This register is self-clearing. + 0 + 1 + read-write + + + TRIG_MODE + TRIG mode register. 1'b0: hardware trigger. 1'b1: software trigger. + 4 + 1 + read-write + + + TRIG_CHAIN + TRIG chain length to the ADC. 0: Trig length is 1; ... 7: Trig length is 8; + 8 + 3 + read-write + + + TRIG_PRIORITY + External trigger priority, 7 is highest, 0 is lowest . + 12 + 3 + read-write + + + SYNC_MODE + TRIG mode control . 1'b0: Disable sync mode; 1'b1: Enable sync mode + 16 + 1 + read-write + + + + + TRIG7_COUNTER + ETC_TRIG7 Counter Register + 0x12C + 32 + read-write + 0 + 0xFFFFFFFF + + + INIT_DELAY + TRIGGER initial delay counter + 0 + 16 + read-write + + + SAMPLE_INTERVAL + TRIGGER sampling interval counter + 16 + 16 + read-write + + + + + TRIG7_CHAIN_1_0 + ETC_TRIG Chain 0/1 Register + 0x130 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL0 + CHAIN0 CSEL ADC channel selection + 0 + 4 + read-write + + + HWTS0 + CHAIN0 HWTS ADC hardware trigger selection + 4 + 8 + read-write + + + B2B0 + CHAIN0 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 12 + 1 + read-write + + + IE0 + CHAIN0 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 13 + 2 + read-write + + + CSEL1 + CHAIN1 CSEL ADC channel selection + 16 + 4 + read-write + + + HWTS1 + CHAIN1 HWTS ADC hardware trigger selection + 20 + 8 + read-write + + + B2B1 + CHAIN1 B2B 1'b0: Disable B2B, wait until interval is reached 1'b1: Enable B2B, back to back ADC trigger + 28 + 1 + read-write + + + IE1 + CHAIN1 IE 2'b00: No interrupt when finished 2'b01: Finished Interrupt on Done0 2'b10: Finished Interrupt on Done1 2'b11: Finished Interrupt on Done2 + 29 + 2 + read-write + + + + + TRIG7_CHAIN_3_2 + ETC_TRIG Chain 2/3 Register + 0x134 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL2 + CHAIN2 CSEL + 0 + 4 + read-write + + + HWTS2 + CHAIN2 HWTS + 4 + 8 + read-write + + + B2B2 + CHAIN2 B2B + 12 + 1 + read-write + + + IE2 + CHAIN2 IE + 13 + 2 + read-write + + + CSEL3 + CHAIN3 CSEL + 16 + 4 + read-write + + + HWTS3 + CHAIN3 HWTS + 20 + 8 + read-write + + + B2B3 + CHAIN3 B2B + 28 + 1 + read-write + + + IE3 + CHAIN3 IE + 29 + 2 + read-write + + + + + TRIG7_CHAIN_5_4 + ETC_TRIG Chain 4/5 Register + 0x138 + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL4 + CHAIN4 CSEL + 0 + 4 + read-write + + + HWTS4 + CHAIN4 HWTS + 4 + 8 + read-write + + + B2B4 + CHAIN4 B2B + 12 + 1 + read-write + + + IE4 + CHAIN4 IE + 13 + 2 + read-write + + + CSEL5 + CHAIN5 CSEL + 16 + 4 + read-write + + + HWTS5 + CHAIN5 HWTS + 20 + 8 + read-write + + + B2B5 + CHAIN5 B2B + 28 + 1 + read-write + + + IE5 + CHAIN5 IE + 29 + 2 + read-write + + + + + TRIG7_CHAIN_7_6 + ETC_TRIG Chain 6/7 Register + 0x13C + 32 + read-write + 0 + 0xFFFFFFFF + + + CSEL6 + CHAIN6 CSEL + 0 + 4 + read-write + + + HWTS6 + CHAIN6 HWTS + 4 + 8 + read-write + + + B2B6 + CHAIN6 B2B + 12 + 1 + read-write + + + IE6 + CHAIN6 IE + 13 + 2 + read-write + + + CSEL7 + CHAIN7 CSEL + 16 + 4 + read-write + + + HWTS7 + CHAIN7 HWTS + 20 + 8 + read-write + + + B2B7 + CHAIN7 B2B + 28 + 1 + read-write + + + IE7 + CHAIN7 IE + 29 + 2 + read-write + + + + + TRIG7_RESULT_1_0 + ETC_TRIG Result Data 1/0 Register + 0x140 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA0 + Result DATA0 + 0 + 12 + read-only + + + DATA1 + Result DATA1 + 16 + 12 + read-only + + + + + TRIG7_RESULT_3_2 + ETC_TRIG Result Data 3/2 Register + 0x144 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA2 + Result DATA2 + 0 + 12 + read-only + + + DATA3 + Result DATA3 + 16 + 12 + read-only + + + + + TRIG7_RESULT_5_4 + ETC_TRIG Result Data 5/4 Register + 0x148 + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA4 + Result DATA4 + 0 + 12 + read-only + + + DATA5 + Result DATA5 + 16 + 12 + read-only + + + + + TRIG7_RESULT_7_6 + ETC_TRIG Result Data 7/6 Register + 0x14C + 32 + read-only + 0 + 0xFFFFFFFF + + + DATA6 + Result DATA6 + 0 + 12 + read-only + + + DATA7 + Result DATA7 + 16 + 12 + read-only + + + + + + + AOI1 + AND/OR/INVERT module + AOI + AOI1_ + AOI + 0x403B4000 + + 0 + 0x10 + registers + + + + 4 + 0x4 + 0,1,2,3 + BFCRT01%s + Boolean Function Term 0 and 1 Configuration Register for EVENTn + 0 + 16 + read-write + 0 + 0xFFFF + + + PT1_DC + Product term 1, D input configuration + 0 + 2 + read-write + + + PT1_DC_0 + Force the D input in this product term to a logical zero + 0 + + + PT1_DC_1 + Pass the D input in this product term + 0x1 + + + PT1_DC_2 + Complement the D input in this product term + 0x2 + + + PT1_DC_3 + Force the D input in this product term to a logical one + 0x3 + + + + + PT1_CC + Product term 1, C input configuration + 2 + 2 + read-write + + + PT1_CC_0 + Force the C input in this product term to a logical zero + 0 + + + PT1_CC_1 + Pass the C input in this product term + 0x1 + + + PT1_CC_2 + Complement the C input in this product term + 0x2 + + + PT1_CC_3 + Force the C input in this product term to a logical one + 0x3 + + + + + PT1_BC + Product term 1, B input configuration + 4 + 2 + read-write + + + PT1_BC_0 + Force the B input in this product term to a logical zero + 0 + + + PT1_BC_1 + Pass the B input in this product term + 0x1 + + + PT1_BC_2 + Complement the B input in this product term + 0x2 + + + PT1_BC_3 + Force the B input in this product term to a logical one + 0x3 + + + + + PT1_AC + Product term 1, A input configuration + 6 + 2 + read-write + + + PT1_AC_0 + Force the A input in this product term to a logical zero + 0 + + + PT1_AC_1 + Pass the A input in this product term + 0x1 + + + PT1_AC_2 + Complement the A input in this product term + 0x2 + + + PT1_AC_3 + Force the A input in this product term to a logical one + 0x3 + + + + + PT0_DC + Product term 0, D input configuration + 8 + 2 + read-write + + + PT0_DC_0 + Force the D input in this product term to a logical zero + 0 + + + PT0_DC_1 + Pass the D input in this product term + 0x1 + + + PT0_DC_2 + Complement the D input in this product term + 0x2 + + + PT0_DC_3 + Force the D input in this product term to a logical one + 0x3 + + + + + PT0_CC + Product term 0, C input configuration + 10 + 2 + read-write + + + PT0_CC_0 + Force the C input in this product term to a logical zero + 0 + + + PT0_CC_1 + Pass the C input in this product term + 0x1 + + + PT0_CC_2 + Complement the C input in this product term + 0x2 + + + PT0_CC_3 + Force the C input in this product term to a logical one + 0x3 + + + + + PT0_BC + Product term 0, B input configuration + 12 + 2 + read-write + + + PT0_BC_0 + Force the B input in this product term to a logical zero + 0 + + + PT0_BC_1 + Pass the B input in this product term + 0x1 + + + PT0_BC_2 + Complement the B input in this product term + 0x2 + + + PT0_BC_3 + Force the B input in this product term to a logical one + 0x3 + + + + + PT0_AC + Product term 0, A input configuration + 14 + 2 + read-write + + + PT0_AC_0 + Force the A input in this product term to a logical zero + 0 + + + PT0_AC_1 + Pass the A input in this product term + 0x1 + + + PT0_AC_2 + Complement the A input in this product term + 0x2 + + + PT0_AC_3 + Force the A input in this product term to a logical one + 0x3 + + + + + + + 4 + 0x4 + 0,1,2,3 + BFCRT23%s + Boolean Function Term 2 and 3 Configuration Register for EVENTn + 0x2 + 16 + read-write + 0 + 0xFFFF + + + PT3_DC + Product term 3, D input configuration + 0 + 2 + read-write + + + PT3_DC_0 + Force the D input in this product term to a logical zero + 0 + + + PT3_DC_1 + Pass the D input in this product term + 0x1 + + + PT3_DC_2 + Complement the D input in this product term + 0x2 + + + PT3_DC_3 + Force the D input in this product term to a logical one + 0x3 + + + + + PT3_CC + Product term 3, C input configuration + 2 + 2 + read-write + + + PT3_CC_0 + Force the C input in this product term to a logical zero + 0 + + + PT3_CC_1 + Pass the C input in this product term + 0x1 + + + PT3_CC_2 + Complement the C input in this product term + 0x2 + + + PT3_CC_3 + Force the C input in this product term to a logical one + 0x3 + + + + + PT3_BC + Product term 3, B input configuration + 4 + 2 + read-write + + + PT3_BC_0 + Force the B input in this product term to a logical zero + 0 + + + PT3_BC_1 + Pass the B input in this product term + 0x1 + + + PT3_BC_2 + Complement the B input in this product term + 0x2 + + + PT3_BC_3 + Force the B input in this product term to a logical one + 0x3 + + + + + PT3_AC + Product term 3, A input configuration + 6 + 2 + read-write + + + PT3_AC_0 + Force the A input in this product term to a logical zero + 0 + + + PT3_AC_1 + Pass the A input in this product term + 0x1 + + + PT3_AC_2 + Complement the A input in this product term + 0x2 + + + PT3_AC_3 + Force the A input in this product term to a logical one + 0x3 + + + + + PT2_DC + Product term 2, D input configuration + 8 + 2 + read-write + + + PT2_DC_0 + Force the D input in this product term to a logical zero + 0 + + + PT2_DC_1 + Pass the D input in this product term + 0x1 + + + PT2_DC_2 + Complement the D input in this product term + 0x2 + + + PT2_DC_3 + Force the D input in this product term to a logical one + 0x3 + + + + + PT2_CC + Product term 2, C input configuration + 10 + 2 + read-write + + + PT2_CC_0 + Force the C input in this product term to a logical zero + 0 + + + PT2_CC_1 + Pass the C input in this product term + 0x1 + + + PT2_CC_2 + Complement the C input in this product term + 0x2 + + + PT2_CC_3 + Force the C input in this product term to a logical one + 0x3 + + + + + PT2_BC + Product term 2, B input configuration + 12 + 2 + read-write + + + PT2_BC_0 + Force the B input in this product term to a logical zero + 0 + + + PT2_BC_1 + Pass the B input in this product term + 0x1 + + + PT2_BC_2 + Complement the B input in this product term + 0x2 + + + PT2_BC_3 + Force the B input in this product term to a logical one + 0x3 + + + + + PT2_AC + Product term 2, A input configuration + 14 + 2 + read-write + + + PT2_AC_0 + Force the A input in this product term to a logical zero + 0 + + + PT2_AC_1 + Pass the A input in this product term + 0x1 + + + PT2_AC_2 + Complement the A input in this product term + 0x2 + + + PT2_AC_3 + Force the A input in this product term to a logical one + 0x3 + + + + + + + + + AOI2 + AND/OR/INVERT module + AOI + AOI2_ + 0x403B8000 + + 0 + 0x10 + registers + + + + XBARA1 + Crossbar Switch + XBARA + XBARA1_ + 0x403BC000 + + 0 + 0x88 + registers + + + + SEL0 + Crossbar A Select Register 0 + 0 + 16 + read-write + 0 + 0xFFFF + + + SEL0 + Input (XBARA_INn) to be muxed to XBARA_OUT0 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL1 + Input (XBARA_INn) to be muxed to XBARA_OUT1 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL1 + Crossbar A Select Register 1 + 0x2 + 16 + read-write + 0 + 0xFFFF + + + SEL2 + Input (XBARA_INn) to be muxed to XBARA_OUT2 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL3 + Input (XBARA_INn) to be muxed to XBARA_OUT3 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL2 + Crossbar A Select Register 2 + 0x4 + 16 + read-write + 0 + 0xFFFF + + + SEL4 + Input (XBARA_INn) to be muxed to XBARA_OUT4 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL5 + Input (XBARA_INn) to be muxed to XBARA_OUT5 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL3 + Crossbar A Select Register 3 + 0x6 + 16 + read-write + 0 + 0xFFFF + + + SEL6 + Input (XBARA_INn) to be muxed to XBARA_OUT6 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL7 + Input (XBARA_INn) to be muxed to XBARA_OUT7 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL4 + Crossbar A Select Register 4 + 0x8 + 16 + read-write + 0 + 0xFFFF + + + SEL8 + Input (XBARA_INn) to be muxed to XBARA_OUT8 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL9 + Input (XBARA_INn) to be muxed to XBARA_OUT9 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL5 + Crossbar A Select Register 5 + 0xA + 16 + read-write + 0 + 0xFFFF + + + SEL10 + Input (XBARA_INn) to be muxed to XBARA_OUT10 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL11 + Input (XBARA_INn) to be muxed to XBARA_OUT11 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL6 + Crossbar A Select Register 6 + 0xC + 16 + read-write + 0 + 0xFFFF + + + SEL12 + Input (XBARA_INn) to be muxed to XBARA_OUT12 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL13 + Input (XBARA_INn) to be muxed to XBARA_OUT13 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL7 + Crossbar A Select Register 7 + 0xE + 16 + read-write + 0 + 0xFFFF + + + SEL14 + Input (XBARA_INn) to be muxed to XBARA_OUT14 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL15 + Input (XBARA_INn) to be muxed to XBARA_OUT15 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL8 + Crossbar A Select Register 8 + 0x10 + 16 + read-write + 0 + 0xFFFF + + + SEL16 + Input (XBARA_INn) to be muxed to XBARA_OUT16 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL17 + Input (XBARA_INn) to be muxed to XBARA_OUT17 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL9 + Crossbar A Select Register 9 + 0x12 + 16 + read-write + 0 + 0xFFFF + + + SEL18 + Input (XBARA_INn) to be muxed to XBARA_OUT18 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL19 + Input (XBARA_INn) to be muxed to XBARA_OUT19 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL10 + Crossbar A Select Register 10 + 0x14 + 16 + read-write + 0 + 0xFFFF + + + SEL20 + Input (XBARA_INn) to be muxed to XBARA_OUT20 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL21 + Input (XBARA_INn) to be muxed to XBARA_OUT21 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL11 + Crossbar A Select Register 11 + 0x16 + 16 + read-write + 0 + 0xFFFF + + + SEL22 + Input (XBARA_INn) to be muxed to XBARA_OUT22 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL23 + Input (XBARA_INn) to be muxed to XBARA_OUT23 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL12 + Crossbar A Select Register 12 + 0x18 + 16 + read-write + 0 + 0xFFFF + + + SEL24 + Input (XBARA_INn) to be muxed to XBARA_OUT24 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL25 + Input (XBARA_INn) to be muxed to XBARA_OUT25 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL13 + Crossbar A Select Register 13 + 0x1A + 16 + read-write + 0 + 0xFFFF + + + SEL26 + Input (XBARA_INn) to be muxed to XBARA_OUT26 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL27 + Input (XBARA_INn) to be muxed to XBARA_OUT27 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL14 + Crossbar A Select Register 14 + 0x1C + 16 + read-write + 0 + 0xFFFF + + + SEL28 + Input (XBARA_INn) to be muxed to XBARA_OUT28 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL29 + Input (XBARA_INn) to be muxed to XBARA_OUT29 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL15 + Crossbar A Select Register 15 + 0x1E + 16 + read-write + 0 + 0xFFFF + + + SEL30 + Input (XBARA_INn) to be muxed to XBARA_OUT30 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL31 + Input (XBARA_INn) to be muxed to XBARA_OUT31 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL16 + Crossbar A Select Register 16 + 0x20 + 16 + read-write + 0 + 0xFFFF + + + SEL32 + Input (XBARA_INn) to be muxed to XBARA_OUT32 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL33 + Input (XBARA_INn) to be muxed to XBARA_OUT33 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL17 + Crossbar A Select Register 17 + 0x22 + 16 + read-write + 0 + 0xFFFF + + + SEL34 + Input (XBARA_INn) to be muxed to XBARA_OUT34 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL35 + Input (XBARA_INn) to be muxed to XBARA_OUT35 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL18 + Crossbar A Select Register 18 + 0x24 + 16 + read-write + 0 + 0xFFFF + + + SEL36 + Input (XBARA_INn) to be muxed to XBARA_OUT36 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL37 + Input (XBARA_INn) to be muxed to XBARA_OUT37 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL19 + Crossbar A Select Register 19 + 0x26 + 16 + read-write + 0 + 0xFFFF + + + SEL38 + Input (XBARA_INn) to be muxed to XBARA_OUT38 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL39 + Input (XBARA_INn) to be muxed to XBARA_OUT39 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL20 + Crossbar A Select Register 20 + 0x28 + 16 + read-write + 0 + 0xFFFF + + + SEL40 + Input (XBARA_INn) to be muxed to XBARA_OUT40 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL41 + Input (XBARA_INn) to be muxed to XBARA_OUT41 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL21 + Crossbar A Select Register 21 + 0x2A + 16 + read-write + 0 + 0xFFFF + + + SEL42 + Input (XBARA_INn) to be muxed to XBARA_OUT42 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL43 + Input (XBARA_INn) to be muxed to XBARA_OUT43 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL22 + Crossbar A Select Register 22 + 0x2C + 16 + read-write + 0 + 0xFFFF + + + SEL44 + Input (XBARA_INn) to be muxed to XBARA_OUT44 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL45 + Input (XBARA_INn) to be muxed to XBARA_OUT45 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL23 + Crossbar A Select Register 23 + 0x2E + 16 + read-write + 0 + 0xFFFF + + + SEL46 + Input (XBARA_INn) to be muxed to XBARA_OUT46 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL47 + Input (XBARA_INn) to be muxed to XBARA_OUT47 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL24 + Crossbar A Select Register 24 + 0x30 + 16 + read-write + 0 + 0xFFFF + + + SEL48 + Input (XBARA_INn) to be muxed to XBARA_OUT48 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL49 + Input (XBARA_INn) to be muxed to XBARA_OUT49 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL25 + Crossbar A Select Register 25 + 0x32 + 16 + read-write + 0 + 0xFFFF + + + SEL50 + Input (XBARA_INn) to be muxed to XBARA_OUT50 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL51 + Input (XBARA_INn) to be muxed to XBARA_OUT51 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL26 + Crossbar A Select Register 26 + 0x34 + 16 + read-write + 0 + 0xFFFF + + + SEL52 + Input (XBARA_INn) to be muxed to XBARA_OUT52 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL53 + Input (XBARA_INn) to be muxed to XBARA_OUT53 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL27 + Crossbar A Select Register 27 + 0x36 + 16 + read-write + 0 + 0xFFFF + + + SEL54 + Input (XBARA_INn) to be muxed to XBARA_OUT54 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL55 + Input (XBARA_INn) to be muxed to XBARA_OUT55 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL28 + Crossbar A Select Register 28 + 0x38 + 16 + read-write + 0 + 0xFFFF + + + SEL56 + Input (XBARA_INn) to be muxed to XBARA_OUT56 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL57 + Input (XBARA_INn) to be muxed to XBARA_OUT57 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL29 + Crossbar A Select Register 29 + 0x3A + 16 + read-write + 0 + 0xFFFF + + + SEL58 + Input (XBARA_INn) to be muxed to XBARA_OUT58 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL59 + Input (XBARA_INn) to be muxed to XBARA_OUT59 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL30 + Crossbar A Select Register 30 + 0x3C + 16 + read-write + 0 + 0xFFFF + + + SEL60 + Input (XBARA_INn) to be muxed to XBARA_OUT60 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL61 + Input (XBARA_INn) to be muxed to XBARA_OUT61 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL31 + Crossbar A Select Register 31 + 0x3E + 16 + read-write + 0 + 0xFFFF + + + SEL62 + Input (XBARA_INn) to be muxed to XBARA_OUT62 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL63 + Input (XBARA_INn) to be muxed to XBARA_OUT63 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL32 + Crossbar A Select Register 32 + 0x40 + 16 + read-write + 0 + 0xFFFF + + + SEL64 + Input (XBARA_INn) to be muxed to XBARA_OUT64 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL65 + Input (XBARA_INn) to be muxed to XBARA_OUT65 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL33 + Crossbar A Select Register 33 + 0x42 + 16 + read-write + 0 + 0xFFFF + + + SEL66 + Input (XBARA_INn) to be muxed to XBARA_OUT66 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL67 + Input (XBARA_INn) to be muxed to XBARA_OUT67 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL34 + Crossbar A Select Register 34 + 0x44 + 16 + read-write + 0 + 0xFFFF + + + SEL68 + Input (XBARA_INn) to be muxed to XBARA_OUT68 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL69 + Input (XBARA_INn) to be muxed to XBARA_OUT69 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL35 + Crossbar A Select Register 35 + 0x46 + 16 + read-write + 0 + 0xFFFF + + + SEL70 + Input (XBARA_INn) to be muxed to XBARA_OUT70 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL71 + Input (XBARA_INn) to be muxed to XBARA_OUT71 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL36 + Crossbar A Select Register 36 + 0x48 + 16 + read-write + 0 + 0xFFFF + + + SEL72 + Input (XBARA_INn) to be muxed to XBARA_OUT72 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL73 + Input (XBARA_INn) to be muxed to XBARA_OUT73 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL37 + Crossbar A Select Register 37 + 0x4A + 16 + read-write + 0 + 0xFFFF + + + SEL74 + Input (XBARA_INn) to be muxed to XBARA_OUT74 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL75 + Input (XBARA_INn) to be muxed to XBARA_OUT75 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL38 + Crossbar A Select Register 38 + 0x4C + 16 + read-write + 0 + 0xFFFF + + + SEL76 + Input (XBARA_INn) to be muxed to XBARA_OUT76 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL77 + Input (XBARA_INn) to be muxed to XBARA_OUT77 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL39 + Crossbar A Select Register 39 + 0x4E + 16 + read-write + 0 + 0xFFFF + + + SEL78 + Input (XBARA_INn) to be muxed to XBARA_OUT78 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL79 + Input (XBARA_INn) to be muxed to XBARA_OUT79 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL40 + Crossbar A Select Register 40 + 0x50 + 16 + read-write + 0 + 0xFFFF + + + SEL80 + Input (XBARA_INn) to be muxed to XBARA_OUT80 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL81 + Input (XBARA_INn) to be muxed to XBARA_OUT81 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL41 + Crossbar A Select Register 41 + 0x52 + 16 + read-write + 0 + 0xFFFF + + + SEL82 + Input (XBARA_INn) to be muxed to XBARA_OUT82 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL83 + Input (XBARA_INn) to be muxed to XBARA_OUT83 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL42 + Crossbar A Select Register 42 + 0x54 + 16 + read-write + 0 + 0xFFFF + + + SEL84 + Input (XBARA_INn) to be muxed to XBARA_OUT84 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL85 + Input (XBARA_INn) to be muxed to XBARA_OUT85 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL43 + Crossbar A Select Register 43 + 0x56 + 16 + read-write + 0 + 0xFFFF + + + SEL86 + Input (XBARA_INn) to be muxed to XBARA_OUT86 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL87 + Input (XBARA_INn) to be muxed to XBARA_OUT87 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL44 + Crossbar A Select Register 44 + 0x58 + 16 + read-write + 0 + 0xFFFF + + + SEL88 + Input (XBARA_INn) to be muxed to XBARA_OUT88 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL89 + Input (XBARA_INn) to be muxed to XBARA_OUT89 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL45 + Crossbar A Select Register 45 + 0x5A + 16 + read-write + 0 + 0xFFFF + + + SEL90 + Input (XBARA_INn) to be muxed to XBARA_OUT90 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL91 + Input (XBARA_INn) to be muxed to XBARA_OUT91 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL46 + Crossbar A Select Register 46 + 0x5C + 16 + read-write + 0 + 0xFFFF + + + SEL92 + Input (XBARA_INn) to be muxed to XBARA_OUT92 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL93 + Input (XBARA_INn) to be muxed to XBARA_OUT93 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL47 + Crossbar A Select Register 47 + 0x5E + 16 + read-write + 0 + 0xFFFF + + + SEL94 + Input (XBARA_INn) to be muxed to XBARA_OUT94 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL95 + Input (XBARA_INn) to be muxed to XBARA_OUT95 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL48 + Crossbar A Select Register 48 + 0x60 + 16 + read-write + 0 + 0xFFFF + + + SEL96 + Input (XBARA_INn) to be muxed to XBARA_OUT96 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL97 + Input (XBARA_INn) to be muxed to XBARA_OUT97 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL49 + Crossbar A Select Register 49 + 0x62 + 16 + read-write + 0 + 0xFFFF + + + SEL98 + Input (XBARA_INn) to be muxed to XBARA_OUT98 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL99 + Input (XBARA_INn) to be muxed to XBARA_OUT99 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL50 + Crossbar A Select Register 50 + 0x64 + 16 + read-write + 0 + 0xFFFF + + + SEL100 + Input (XBARA_INn) to be muxed to XBARA_OUT100 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL101 + Input (XBARA_INn) to be muxed to XBARA_OUT101 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL51 + Crossbar A Select Register 51 + 0x66 + 16 + read-write + 0 + 0xFFFF + + + SEL102 + Input (XBARA_INn) to be muxed to XBARA_OUT102 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL103 + Input (XBARA_INn) to be muxed to XBARA_OUT103 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL52 + Crossbar A Select Register 52 + 0x68 + 16 + read-write + 0 + 0xFFFF + + + SEL104 + Input (XBARA_INn) to be muxed to XBARA_OUT104 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL105 + Input (XBARA_INn) to be muxed to XBARA_OUT105 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL53 + Crossbar A Select Register 53 + 0x6A + 16 + read-write + 0 + 0xFFFF + + + SEL106 + Input (XBARA_INn) to be muxed to XBARA_OUT106 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL107 + Input (XBARA_INn) to be muxed to XBARA_OUT107 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL54 + Crossbar A Select Register 54 + 0x6C + 16 + read-write + 0 + 0xFFFF + + + SEL108 + Input (XBARA_INn) to be muxed to XBARA_OUT108 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL109 + Input (XBARA_INn) to be muxed to XBARA_OUT109 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL55 + Crossbar A Select Register 55 + 0x6E + 16 + read-write + 0 + 0xFFFF + + + SEL110 + Input (XBARA_INn) to be muxed to XBARA_OUT110 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL111 + Input (XBARA_INn) to be muxed to XBARA_OUT111 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL56 + Crossbar A Select Register 56 + 0x70 + 16 + read-write + 0 + 0xFFFF + + + SEL112 + Input (XBARA_INn) to be muxed to XBARA_OUT112 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL113 + Input (XBARA_INn) to be muxed to XBARA_OUT113 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL57 + Crossbar A Select Register 57 + 0x72 + 16 + read-write + 0 + 0xFFFF + + + SEL114 + Input (XBARA_INn) to be muxed to XBARA_OUT114 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL115 + Input (XBARA_INn) to be muxed to XBARA_OUT115 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL58 + Crossbar A Select Register 58 + 0x74 + 16 + read-write + 0 + 0xFFFF + + + SEL116 + Input (XBARA_INn) to be muxed to XBARA_OUT116 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL117 + Input (XBARA_INn) to be muxed to XBARA_OUT117 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL59 + Crossbar A Select Register 59 + 0x76 + 16 + read-write + 0 + 0xFFFF + + + SEL118 + Input (XBARA_INn) to be muxed to XBARA_OUT118 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL119 + Input (XBARA_INn) to be muxed to XBARA_OUT119 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL60 + Crossbar A Select Register 60 + 0x78 + 16 + read-write + 0 + 0xFFFF + + + SEL120 + Input (XBARA_INn) to be muxed to XBARA_OUT120 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL121 + Input (XBARA_INn) to be muxed to XBARA_OUT121 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL61 + Crossbar A Select Register 61 + 0x7A + 16 + read-write + 0 + 0xFFFF + + + SEL122 + Input (XBARA_INn) to be muxed to XBARA_OUT122 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL123 + Input (XBARA_INn) to be muxed to XBARA_OUT123 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL62 + Crossbar A Select Register 62 + 0x7C + 16 + read-write + 0 + 0xFFFF + + + SEL124 + Input (XBARA_INn) to be muxed to XBARA_OUT124 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL125 + Input (XBARA_INn) to be muxed to XBARA_OUT125 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL63 + Crossbar A Select Register 63 + 0x7E + 16 + read-write + 0 + 0xFFFF + + + SEL126 + Input (XBARA_INn) to be muxed to XBARA_OUT126 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL127 + Input (XBARA_INn) to be muxed to XBARA_OUT127 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL64 + Crossbar A Select Register 64 + 0x80 + 16 + read-write + 0 + 0xFFFF + + + SEL128 + Input (XBARA_INn) to be muxed to XBARA_OUT128 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL129 + Input (XBARA_INn) to be muxed to XBARA_OUT129 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + SEL65 + Crossbar A Select Register 65 + 0x82 + 16 + read-write + 0 + 0xFFFF + + + SEL130 + Input (XBARA_INn) to be muxed to XBARA_OUT130 (refer to Functional Description section for input/output assignment) + 0 + 7 + read-write + + + SEL131 + Input (XBARA_INn) to be muxed to XBARA_OUT131 (refer to Functional Description section for input/output assignment) + 8 + 7 + read-write + + + + + CTRL0 + Crossbar A Control Register 0 + 0x84 + 16 + read-write + 0 + 0xFFFF + + + DEN0 + DMA Enable for XBAR_OUT0 + 0 + 1 + read-write + + + DEN0_0 + DMA disabled + 0 + + + DEN0_1 + DMA enabled + 0x1 + + + + + IEN0 + Interrupt Enable for XBAR_OUT0 + 1 + 1 + read-write + + + IEN0_0 + Interrupt disabled + 0 + + + IEN0_1 + Interrupt enabled + 0x1 + + + + + EDGE0 + Active edge for edge detection on XBAR_OUT0 + 2 + 2 + read-write + + + EDGE0_0 + STS0 never asserts + 0 + + + EDGE0_1 + STS0 asserts on rising edges of XBAR_OUT0 + 0x1 + + + EDGE0_2 + STS0 asserts on falling edges of XBAR_OUT0 + 0x2 + + + EDGE0_3 + STS0 asserts on rising and falling edges of XBAR_OUT0 + 0x3 + + + + + STS0 + Edge detection status for XBAR_OUT0 + 4 + 1 + read-write + oneToClear + + + STS0_0 + Active edge not yet detected on XBAR_OUT0 + 0 + + + STS0_1 + Active edge detected on XBAR_OUT0 + 0x1 + + + + + DEN1 + DMA Enable for XBAR_OUT1 + 8 + 1 + read-write + + + DEN1_0 + DMA disabled + 0 + + + DEN1_1 + DMA enabled + 0x1 + + + + + IEN1 + Interrupt Enable for XBAR_OUT1 + 9 + 1 + read-write + + + IEN1_0 + Interrupt disabled + 0 + + + IEN1_1 + Interrupt enabled + 0x1 + + + + + EDGE1 + Active edge for edge detection on XBAR_OUT1 + 10 + 2 + read-write + + + EDGE1_0 + STS1 never asserts + 0 + + + EDGE1_1 + STS1 asserts on rising edges of XBAR_OUT1 + 0x1 + + + EDGE1_2 + STS1 asserts on falling edges of XBAR_OUT1 + 0x2 + + + EDGE1_3 + STS1 asserts on rising and falling edges of XBAR_OUT1 + 0x3 + + + + + STS1 + Edge detection status for XBAR_OUT1 + 12 + 1 + read-write + oneToClear + + + STS1_0 + Active edge not yet detected on XBAR_OUT1 + 0 + + + STS1_1 + Active edge detected on XBAR_OUT1 + 0x1 + + + + + + + CTRL1 + Crossbar A Control Register 1 + 0x86 + 16 + read-write + 0 + 0xFFFF + + + DEN2 + DMA Enable for XBAR_OUT2 + 0 + 1 + read-write + + + DEN2_0 + DMA disabled + 0 + + + DEN2_1 + DMA enabled + 0x1 + + + + + IEN2 + Interrupt Enable for XBAR_OUT2 + 1 + 1 + read-write + + + IEN2_0 + Interrupt disabled + 0 + + + IEN2_1 + Interrupt enabled + 0x1 + + + + + EDGE2 + Active edge for edge detection on XBAR_OUT2 + 2 + 2 + read-write + + + EDGE2_0 + STS2 never asserts + 0 + + + EDGE2_1 + STS2 asserts on rising edges of XBAR_OUT2 + 0x1 + + + EDGE2_2 + STS2 asserts on falling edges of XBAR_OUT2 + 0x2 + + + EDGE2_3 + STS2 asserts on rising and falling edges of XBAR_OUT2 + 0x3 + + + + + STS2 + Edge detection status for XBAR_OUT2 + 4 + 1 + read-write + oneToClear + + + STS2_0 + Active edge not yet detected on XBAR_OUT2 + 0 + + + STS2_1 + Active edge detected on XBAR_OUT2 + 0x1 + + + + + DEN3 + DMA Enable for XBAR_OUT3 + 8 + 1 + read-write + + + DEN3_0 + DMA disabled + 0 + + + DEN3_1 + DMA enabled + 0x1 + + + + + IEN3 + Interrupt Enable for XBAR_OUT3 + 9 + 1 + read-write + + + IEN3_0 + Interrupt disabled + 0 + + + IEN3_1 + Interrupt enabled + 0x1 + + + + + EDGE3 + Active edge for edge detection on XBAR_OUT3 + 10 + 2 + read-write + + + EDGE3_0 + STS3 never asserts + 0 + + + EDGE3_1 + STS3 asserts on rising edges of XBAR_OUT3 + 0x1 + + + EDGE3_2 + STS3 asserts on falling edges of XBAR_OUT3 + 0x2 + + + EDGE3_3 + STS3 asserts on rising and falling edges of XBAR_OUT3 + 0x3 + + + + + STS3 + Edge detection status for XBAR_OUT3 + 12 + 1 + read-write + oneToClear + + + STS3_0 + Active edge not yet detected on XBAR_OUT3 + 0 + + + STS3_1 + Active edge detected on XBAR_OUT3 + 0x1 + + + + + + + + + XBARB2 + Crossbar Switch + XBARA + XBARB2_ + XBARA + 0x403C0000 + + 0 + 0x10 + registers + + + + SEL0 + Crossbar B Select Register 0 + 0 + 16 + read-write + 0 + 0xFFFF + + + SEL0 + Input (XBARB_INn) to be muxed to XBARB_OUT0 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL1 + Input (XBARB_INn) to be muxed to XBARB_OUT1 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL1 + Crossbar B Select Register 1 + 0x2 + 16 + read-write + 0 + 0xFFFF + + + SEL2 + Input (XBARB_INn) to be muxed to XBARB_OUT2 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL3 + Input (XBARB_INn) to be muxed to XBARB_OUT3 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL2 + Crossbar B Select Register 2 + 0x4 + 16 + read-write + 0 + 0xFFFF + + + SEL4 + Input (XBARB_INn) to be muxed to XBARB_OUT4 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL5 + Input (XBARB_INn) to be muxed to XBARB_OUT5 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL3 + Crossbar B Select Register 3 + 0x6 + 16 + read-write + 0 + 0xFFFF + + + SEL6 + Input (XBARB_INn) to be muxed to XBARB_OUT6 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL7 + Input (XBARB_INn) to be muxed to XBARB_OUT7 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL4 + Crossbar B Select Register 4 + 0x8 + 16 + read-write + 0 + 0xFFFF + + + SEL8 + Input (XBARB_INn) to be muxed to XBARB_OUT8 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL9 + Input (XBARB_INn) to be muxed to XBARB_OUT9 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL5 + Crossbar B Select Register 5 + 0xA + 16 + read-write + 0 + 0xFFFF + + + SEL10 + Input (XBARB_INn) to be muxed to XBARB_OUT10 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL11 + Input (XBARB_INn) to be muxed to XBARB_OUT11 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL6 + Crossbar B Select Register 6 + 0xC + 16 + read-write + 0 + 0xFFFF + + + SEL12 + Input (XBARB_INn) to be muxed to XBARB_OUT12 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL13 + Input (XBARB_INn) to be muxed to XBARB_OUT13 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + SEL7 + Crossbar B Select Register 7 + 0xE + 16 + read-write + 0 + 0xFFFF + + + SEL14 + Input (XBARB_INn) to be muxed to XBARB_OUT14 (refer to Functional Description section for input/output assignment) + 0 + 6 + read-write + + + SEL15 + Input (XBARB_INn) to be muxed to XBARB_OUT15 (refer to Functional Description section for input/output assignment) + 8 + 6 + read-write + + + + + + + XBARB3 + Crossbar Switch + XBARA + XBARB3_ + 0x403C4000 + + 0 + 0x10 + registers + + + + ENC1 + Quadrature Decoder + ENC + ENC1_ + ENC + 0x403C8000 + + 0 + 0x28 + registers + + + ENC1 + 129 + + + + CTRL + Control Register + 0 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enable + 0 + 1 + read-write + + + CMPIE_0 + Compare interrupt is disabled + 0 + + + CMPIE_1 + Compare interrupt is enabled + 0x1 + + + + + CMPIRQ + Compare Interrupt Request + 1 + 1 + read-write + oneToClear + + + CMPIRQ_0 + No match has occurred + 0 + + + CMPIRQ_1 + COMP match has occurred + 0x1 + + + + + WDE + Watchdog Enable + 2 + 1 + read-write + + + WDE_0 + Watchdog timer is disabled + 0 + + + WDE_1 + Watchdog timer is enabled + 0x1 + + + + + DIE + Watchdog Timeout Interrupt Enable + 3 + 1 + read-write + + + DIE_0 + Watchdog timer interrupt is disabled + 0 + + + DIE_1 + Watchdog timer interrupt is enabled + 0x1 + + + + + DIRQ + Watchdog Timeout Interrupt Request + 4 + 1 + read-write + oneToClear + + + DIRQ_0 + No interrupt has occurred + 0 + + + DIRQ_1 + Watchdog timeout interrupt has occurred + 0x1 + + + + + XNE + Use Negative Edge of INDEX Pulse + 5 + 1 + read-write + + + XNE_0 + Use positive transition edge of INDEX pulse + 0 + + + XNE_1 + Use negative transition edge of INDEX pulse + 0x1 + + + + + XIP + INDEX Triggered Initialization of Position Counters UPOS and LPOS + 6 + 1 + read-write + + + XIP_0 + No action + 0 + + + XIP_1 + INDEX pulse initializes the position counter + 0x1 + + + + + XIE + INDEX Pulse Interrupt Enable + 7 + 1 + read-write + + + XIE_0 + INDEX pulse interrupt is disabled + 0 + + + XIE_1 + INDEX pulse interrupt is enabled + 0x1 + + + + + XIRQ + INDEX Pulse Interrupt Request + 8 + 1 + read-write + oneToClear + + + XIRQ_0 + No interrupt has occurred + 0 + + + XIRQ_1 + INDEX pulse interrupt has occurred + 0x1 + + + + + PH1 + Enable Signal Phase Count Mode + 9 + 1 + read-write + + + PH1_0 + Use standard quadrature decoder where PHASEA and PHASEB represent a two phase quadrature signal. + 0 + + + PH1_1 + Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction. If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down If CTRL[REV] = 1, PHASEB = 1, then count up + 0x1 + + + + + REV + Enable Reverse Direction Counting + 10 + 1 + read-write + + + REV_0 + Count normally + 0 + + + REV_1 + Count in the reverse direction + 0x1 + + + + + SWIP + Software Triggered Initialization of Position Counters UPOS and LPOS + 11 + 1 + read-write + + + SWIP_0 + No action + 0 + + + SWIP_1 + Initialize position counter + 0x1 + + + + + HNE + Use Negative Edge of HOME Input + 12 + 1 + read-write + + + HNE_0 + Use positive going edge-to-trigger initialization of position counters UPOS and LPOS + 0 + + + HNE_1 + Use negative going edge-to-trigger initialization of position counters UPOS and LPOS + 0x1 + + + + + HIP + Enable HOME to Initialize Position Counters UPOS and LPOS + 13 + 1 + read-write + + + HIP_0 + No action + 0 + + + HIP_1 + HOME signal initializes the position counter + 0x1 + + + + + HIE + HOME Interrupt Enable + 14 + 1 + read-write + + + HIE_0 + Disable HOME interrupts + 0 + + + HIE_1 + Enable HOME interrupts + 0x1 + + + + + HIRQ + HOME Signal Transition Interrupt Request + 15 + 1 + read-write + oneToClear + + + HIRQ_0 + No interrupt + 0 + + + HIRQ_1 + HOME signal transition interrupt request + 0x1 + + + + + + + FILT + Input Filter Register + 0x2 + 16 + read-write + 0 + 0xFFFF + + + FILT_PER + Input Filter Sample Period + 0 + 8 + read-write + + + FILT_CNT + Input Filter Sample Count + 8 + 3 + read-write + + + + + WTR + Watchdog Timeout Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + WDOG + WDOG[15:0] is a binary representation of the number of clock cycles plus one that the watchdog timer counts before timing out and optionally generating an interrupt + 0 + 16 + read-write + + + + + POSD + Position Difference Counter Register + 0x6 + 16 + read-write + 0 + 0xFFFF + + + POSD + This read/write register contains the position change in value occurring between each read of the position register + 0 + 16 + read-write + + + + + POSDH + Position Difference Hold Register + 0x8 + 16 + read-only + 0 + 0xFFFF + + + POSDH + This read-only register contains a snapshot of the value of the POSD register + 0 + 16 + read-only + + + + + REV + Revolution Counter Register + 0xA + 16 + read-write + 0 + 0xFFFF + + + REV + This read/write register contains the current value of the revolution counter. + 0 + 16 + read-write + + + + + REVH + Revolution Hold Register + 0xC + 16 + read-only + 0 + 0xFFFF + + + REVH + This read-only register contains a snapshot of the value of the REV register. + 0 + 16 + read-only + + + + + UPOS + Upper Position Counter Register + 0xE + 16 + read-write + 0 + 0xFFFF + + + POS + This read/write register contains the upper (most significant) half of the position counter + 0 + 16 + read-write + + + + + LPOS + Lower Position Counter Register + 0x10 + 16 + read-write + 0 + 0xFFFF + + + POS + This read/write register contains the lower (least significant) half of the position counter + 0 + 16 + read-write + + + + + UPOSH + Upper Position Hold Register + 0x12 + 16 + read-only + 0 + 0xFFFF + + + POSH + This read-only register contains a snapshot of the UPOS register. + 0 + 16 + read-only + + + + + LPOSH + Lower Position Hold Register + 0x14 + 16 + read-only + 0 + 0xFFFF + + + POSH + This read-only register contains a snapshot of the LPOS register. + 0 + 16 + read-only + + + + + UINIT + Upper Initialization Register + 0x16 + 16 + read-write + 0 + 0xFFFF + + + INIT + This read/write register contains the value to be used to initialize the upper half of the position counter (UPOS) + 0 + 16 + read-write + + + + + LINIT + Lower Initialization Register + 0x18 + 16 + read-write + 0 + 0xFFFF + + + INIT + This read/write register contains the value to be used to initialize the lower half of the position counter (LPOS) + 0 + 16 + read-write + + + + + IMR + Input Monitor Register + 0x1A + 16 + read-only + 0 + 0xFFFF + + + HOME + This is the raw HOME input. + 0 + 1 + read-only + + + INDEX + This is the raw INDEX input. + 1 + 1 + read-only + + + PHB + This is the raw PHASEB input. + 2 + 1 + read-only + + + PHA + This is the raw PHASEA input. + 3 + 1 + read-only + + + FHOM + This is the filtered version of HOME input. + 4 + 1 + read-only + + + FIND + This is the filtered version of INDEX input. + 5 + 1 + read-only + + + FPHB + This is the filtered version of PHASEB input. + 6 + 1 + read-only + + + FPHA + This is the filtered version of PHASEA input. + 7 + 1 + read-only + + + + + TST + Test Register + 0x1C + 16 + read-write + 0 + 0xFFFF + + + TEST_COUNT + These bits hold the number of quadrature advances to generate. + 0 + 8 + read-write + + + TEST_PERIOD + These bits hold the period of quadrature phase in IPBus clock cycles. + 8 + 5 + read-write + + + QDN + Quadrature Decoder Negative Signal + 13 + 1 + read-write + + + QDN_0 + Leaves quadrature decoder signal in a positive direction + 0 + + + QDN_1 + Generates a negative quadrature decoder signal + 0x1 + + + + + TCE + Test Counter Enable + 14 + 1 + read-write + + + TCE_0 + Test count is not enabled + 0 + + + TCE_1 + Test count is enabled + 0x1 + + + + + TEN + Test Mode Enable + 15 + 1 + read-write + + + TEN_0 + Test module is not enabled + 0 + + + TEN_1 + Test module is enabled + 0x1 + + + + + + + CTRL2 + Control 2 Register + 0x1E + 16 + read-write + 0 + 0xFFFF + + + UPDHLD + Update Hold Registers + 0 + 1 + read-write + + + UPDHLD_0 + Disable updates of hold registers on rising edge of TRIGGER + 0 + + + UPDHLD_1 + Enable updates of hold registers on rising edge of TRIGGER + 0x1 + + + + + UPDPOS + Update Position Registers + 1 + 1 + read-write + + + UPDPOS_0 + No action for POSD, REV, UPOS and LPOS on rising edge of TRIGGER + 0 + + + UPDPOS_1 + Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER + 0x1 + + + + + MOD + Enable Modulo Counting + 2 + 1 + read-write + + + MOD_0 + Disable modulo counting + 0 + + + MOD_1 + Enable modulo counting + 0x1 + + + + + DIR + Count Direction Flag + 3 + 1 + read-only + + + DIR_0 + Last count was in the down direction + 0 + + + DIR_1 + Last count was in the up direction + 0x1 + + + + + RUIE + Roll-under Interrupt Enable + 4 + 1 + read-write + + + RUIE_0 + Roll-under interrupt is disabled + 0 + + + RUIE_1 + Roll-under interrupt is enabled + 0x1 + + + + + RUIRQ + Roll-under Interrupt Request + 5 + 1 + read-write + oneToClear + + + RUIRQ_0 + No roll-under has occurred + 0 + + + RUIRQ_1 + Roll-under has occurred + 0x1 + + + + + ROIE + Roll-over Interrupt Enable + 6 + 1 + read-write + + + ROIE_0 + Roll-over interrupt is disabled + 0 + + + ROIE_1 + Roll-over interrupt is enabled + 0x1 + + + + + ROIRQ + Roll-over Interrupt Request + 7 + 1 + read-write + oneToClear + + + ROIRQ_0 + No roll-over has occurred + 0 + + + ROIRQ_1 + Roll-over has occurred + 0x1 + + + + + REVMOD + Revolution Counter Modulus Enable + 8 + 1 + read-write + + + REVMOD_0 + Use INDEX pulse to increment/decrement revolution counter (REV). + 0 + + + REVMOD_1 + Use modulus counting roll-over/under to increment/decrement revolution counter (REV). + 0x1 + + + + + OUTCTL + Output Control + 9 + 1 + read-write + + + OUTCTL_0 + POSMATCH pulses when a match occurs between the position counters (POS) and the compare value (COMP). + 0 + + + OUTCTL_1 + POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read. + 0x1 + + + + + SABIE + Simultaneous PHASEA and PHASEB Change Interrupt Enable + 10 + 1 + read-write + + + SABIE_0 + Simultaneous PHASEA and PHASEB change interrupt disabled. + 0 + + + SABIE_1 + Simultaneous PHASEA and PHASEB change interrupt enabled. + 0x1 + + + + + SABIRQ + Simultaneous PHASEA and PHASEB Change Interrupt Request + 11 + 1 + read-write + oneToClear + + + SABIRQ_0 + No simultaneous change of PHASEA and PHASEB has occurred. + 0 + + + SABIRQ_1 + A simultaneous change of PHASEA and PHASEB has occurred. + 0x1 + + + + + + + UMOD + Upper Modulus Register + 0x20 + 16 + read-write + 0 + 0xFFFF + + + MOD + This read/write register contains the upper (most significant) half of the modulus register + 0 + 16 + read-write + + + + + LMOD + Lower Modulus Register + 0x22 + 16 + read-write + 0 + 0xFFFF + + + MOD + This read/write register contains the lower (least significant) half of the modulus register + 0 + 16 + read-write + + + + + UCOMP + Upper Position Compare Register + 0x24 + 16 + read-write + 0xFFFF + 0xFFFF + + + COMP + This read/write register contains the upper (most significant) half of the position compare register + 0 + 16 + read-write + + + + + LCOMP + Lower Position Compare Register + 0x26 + 16 + read-write + 0xFFFF + 0xFFFF + + + COMP + This read/write register contains the lower (least significant) half of the position compare register + 0 + 16 + read-write + + + + + + + ENC2 + Quadrature Decoder + ENC + ENC2_ + 0x403CC000 + + 0 + 0x28 + registers + + + ENC2 + 130 + + + + ENC3 + Quadrature Decoder + ENC + ENC3_ + 0x403D0000 + + 0 + 0x28 + registers + + + ENC3 + 131 + + + + ENC4 + Quadrature Decoder + ENC + ENC4_ + 0x403D4000 + + 0 + 0x28 + registers + + + ENC4 + 132 + + + + PWM1 + PWM + PWM + PWM + 0x403DC000 + + 0 + 0x196 + registers + + + PWM1_0 + 102 + + + PWM1_1 + 103 + + + PWM1_2 + 104 + + + PWM1_3 + 105 + + + PWM1_FAULT + 106 + + + + SM0CNT + Counter Register + 0 + 16 + read-only + 0 + 0xFFFF + + + CNT + Counter Register Bits + 0 + 16 + read-only + + + + + SM0INIT + Initial Count Register + 0x2 + 16 + read-write + 0 + 0xFFFF + + + INIT + Initial Count Register Bits + 0 + 16 + read-write + + + + + SM0CTRL2 + Control 2 Register + 0x4 + 16 + read-write + 0 + 0xFFFF + + + CLK_SEL + Clock Source Select + 0 + 2 + read-write + + + CLK_SEL_0 + The IPBus clock is used as the clock for the local prescaler and counter. + 0 + + + CLK_SEL_1 + EXT_CLK is used as the clock for the local prescaler and counter. + 0x1 + + + CLK_SEL_2 + Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. + 0x2 + + + + + RELOAD_SEL + Reload Source Select + 2 + 1 + read-write + + + RELOAD_SEL_0 + The local RELOAD signal is used to reload registers. + 0 + + + RELOAD_SEL_1 + The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. + 0x1 + + + + + FORCE_SEL + This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + 3 + 3 + read-write + + + FORCE_SEL_0 + The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + 0 + + + FORCE_SEL_1 + The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x1 + + + FORCE_SEL_2 + The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + 0x2 + + + FORCE_SEL_3 + The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x3 + + + FORCE_SEL_4 + The local sync signal from this submodule is used to force updates. + 0x4 + + + FORCE_SEL_5 + The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x5 + + + FORCE_SEL_6 + The external force signal, EXT_FORCE, from outside the PWM module causes updates. + 0x6 + + + FORCE_SEL_7 + The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + 0x7 + + + + + FORCE + Force Initialization + 6 + 1 + read-write + + + FRCEN + FRCEN + 7 + 1 + read-write + + + FRCEN_0 + Initialization from a FORCE_OUT is disabled. + 0 + + + FRCEN_1 + Initialization from a FORCE_OUT is enabled. + 0x1 + + + + + INIT_SEL + Initialization Control Select + 8 + 2 + read-write + + + INIT_SEL_0 + Local sync (PWM_X) causes initialization. + 0 + + + INIT_SEL_1 + Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. + 0x1 + + + INIT_SEL_2 + Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. + 0x2 + + + INIT_SEL_3 + EXT_SYNC causes initialization. + 0x3 + + + + + PWMX_INIT + PWM_X Initial Value + 10 + 1 + read-write + + + PWM45_INIT + PWM45 Initial Value + 11 + 1 + read-write + + + PWM23_INIT + PWM23 Initial Value + 12 + 1 + read-write + + + INDEP + Independent or Complementary Pair Operation + 13 + 1 + read-write + + + INDEP_0 + PWM_A and PWM_B form a complementary PWM pair. + 0 + + + INDEP_1 + PWM_A and PWM_B outputs are independent PWMs. + 0x1 + + + + + WAITEN + WAIT Enable + 14 + 1 + read-write + + + DBGEN + Debug Enable + 15 + 1 + read-write + + + + + SM0CTRL + Control Register + 0x6 + 16 + read-write + 0x400 + 0xFFFF + + + DBLEN + Double Switching Enable + 0 + 1 + read-write + + + DBLEN_0 + Double switching disabled. + 0 + + + DBLEN_1 + Double switching enabled. + 0x1 + + + + + DBLX + PWMX Double Switching Enable + 1 + 1 + read-write + + + DBLX_0 + PWMX double pulse disabled. + 0 + + + DBLX_1 + PWMX double pulse enabled. + 0x1 + + + + + LDMOD + Load Mode Select + 2 + 1 + read-write + + + LDMOD_0 + Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + 0 + + + LDMOD_1 + Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + 0x1 + + + + + SPLIT + Split the DBLPWM signal to PWMA and PWMB + 3 + 1 + read-write + + + SPLIT_0 + DBLPWM is not split. PWMA and PWMB each have double pulses. + 0 + + + SPLIT_1 + DBLPWM is split to PWMA and PWMB. + 0x1 + + + + + PRSC + Prescaler + 4 + 3 + read-write + + + PRSC_0 + PWM clock frequency = fclk + 0 + + + PRSC_1 + PWM clock frequency = fclk/2 + 0x1 + + + PRSC_2 + PWM clock frequency = fclk/4 + 0x2 + + + PRSC_3 + PWM clock frequency = fclk/8 + 0x3 + + + PRSC_4 + PWM clock frequency = fclk/16 + 0x4 + + + PRSC_5 + PWM clock frequency = fclk/32 + 0x5 + + + PRSC_6 + PWM clock frequency = fclk/64 + 0x6 + + + PRSC_7 + PWM clock frequency = fclk/128 + 0x7 + + + + + COMPMODE + Compare Mode + 7 + 1 + read-write + + + COMPMODE_0 + The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. + 0 + + + COMPMODE_1 + The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + 0x1 + + + + + DT + Deadtime + 8 + 2 + read-only + + + FULL + Full Cycle Reload + 10 + 1 + read-write + + + FULL_0 + Full-cycle reloads disabled. + 0 + + + FULL_1 + Full-cycle reloads enabled. + 0x1 + + + + + HALF + Half Cycle Reload + 11 + 1 + read-write + + + HALF_0 + Half-cycle reloads disabled. + 0 + + + HALF_1 + Half-cycle reloads enabled. + 0x1 + + + + + LDFQ + Load Frequency + 12 + 4 + read-write + + + LDFQ_0 + Every PWM opportunity + 0 + + + LDFQ_1 + Every 2 PWM opportunities + 0x1 + + + LDFQ_2 + Every 3 PWM opportunities + 0x2 + + + LDFQ_3 + Every 4 PWM opportunities + 0x3 + + + LDFQ_4 + Every 5 PWM opportunities + 0x4 + + + LDFQ_5 + Every 6 PWM opportunities + 0x5 + + + LDFQ_6 + Every 7 PWM opportunities + 0x6 + + + LDFQ_7 + Every 8 PWM opportunities + 0x7 + + + LDFQ_8 + Every 9 PWM opportunities + 0x8 + + + LDFQ_9 + Every 10 PWM opportunities + 0x9 + + + LDFQ_10 + Every 11 PWM opportunities + 0xA + + + LDFQ_11 + Every 12 PWM opportunities + 0xB + + + LDFQ_12 + Every 13 PWM opportunities + 0xC + + + LDFQ_13 + Every 14 PWM opportunities + 0xD + + + LDFQ_14 + Every 15 PWM opportunities + 0xE + + + LDFQ_15 + Every 16 PWM opportunities + 0xF + + + + + + + SM0VAL0 + Value Register 0 + 0xA + 16 + read-write + 0 + 0xFFFF + + + VAL0 + Value Register 0 + 0 + 16 + read-write + + + + + SM0FRACVAL1 + Fractional Value Register 1 + 0xC + 16 + read-write + 0 + 0xFFFF + + + FRACVAL1 + Fractional Value 1 Register + 11 + 5 + read-write + + + + + SM0VAL1 + Value Register 1 + 0xE + 16 + read-write + 0 + 0xFFFF + + + VAL1 + Value Register 1 + 0 + 16 + read-write + + + + + SM0FRACVAL2 + Fractional Value Register 2 + 0x10 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL2 + Fractional Value 2 + 11 + 5 + read-write + + + + + SM0VAL2 + Value Register 2 + 0x12 + 16 + read-write + 0 + 0xFFFF + + + VAL2 + Value Register 2 + 0 + 16 + read-write + + + + + SM0FRACVAL3 + Fractional Value Register 3 + 0x14 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL3 + Fractional Value 3 + 11 + 5 + read-write + + + + + SM0VAL3 + Value Register 3 + 0x16 + 16 + read-write + 0 + 0xFFFF + + + VAL3 + Value Register 3 + 0 + 16 + read-write + + + + + SM0FRACVAL4 + Fractional Value Register 4 + 0x18 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL4 + Fractional Value 4 + 11 + 5 + read-write + + + + + SM0VAL4 + Value Register 4 + 0x1A + 16 + read-write + 0 + 0xFFFF + + + VAL4 + Value Register 4 + 0 + 16 + read-write + + + + + SM0FRACVAL5 + Fractional Value Register 5 + 0x1C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL5 + Fractional Value 5 + 11 + 5 + read-write + + + + + SM0VAL5 + Value Register 5 + 0x1E + 16 + read-write + 0 + 0xFFFF + + + VAL5 + Value Register 5 + 0 + 16 + read-write + + + + + SM0FRCTRL + Fractional Control Register + 0x20 + 16 + read-write + 0 + 0xFFFF + + + FRAC1_EN + Fractional Cycle PWM Period Enable + 1 + 1 + read-write + + + FRAC1_EN_0 + Disable fractional cycle length for the PWM period. + 0 + + + FRAC1_EN_1 + Enable fractional cycle length for the PWM period. + 0x1 + + + + + FRAC23_EN + Fractional Cycle Placement Enable for PWM_A + 2 + 1 + read-write + + + FRAC23_EN_0 + Disable fractional cycle placement for PWM_A. + 0 + + + FRAC23_EN_1 + Enable fractional cycle placement for PWM_A. + 0x1 + + + + + FRAC45_EN + Fractional Cycle Placement Enable for PWM_B + 4 + 1 + read-write + + + FRAC45_EN_0 + Disable fractional cycle placement for PWM_B. + 0 + + + FRAC45_EN_1 + Enable fractional cycle placement for PWM_B. + 0x1 + + + + + FRAC_PU + Fractional Delay Circuit Power Up + 8 + 1 + read-write + + + FRAC_PU_0 + Turn off fractional delay logic. + 0 + + + FRAC_PU_1 + Power up fractional delay logic. + 0x1 + + + + + TEST + Test Status Bit + 15 + 1 + read-only + + + + + SM0OCTRL + Output Control Register + 0x22 + 16 + read-write + 0 + 0xFFFF + + + PWMXFS + PWM_X Fault State + 0 + 2 + read-write + + + PWMXFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMXFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMXFS_2 + Output is tristated. + 0x2 + + + PWMXFS_3 + Output is tristated. + 0x3 + + + + + PWMBFS + PWM_B Fault State + 2 + 2 + read-write + + + PWMBFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMBFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMBFS_2 + Output is tristated. + 0x2 + + + PWMBFS_3 + Output is tristated. + 0x3 + + + + + PWMAFS + PWM_A Fault State + 4 + 2 + read-write + + + PWMAFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMAFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMAFS_2 + Output is tristated. + 0x2 + + + PWMAFS_3 + Output is tristated. + 0x3 + + + + + POLX + PWM_X Output Polarity + 8 + 1 + read-write + + + POLX_0 + PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + 0 + + + POLX_1 + PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + 0x1 + + + + + POLB + PWM_B Output Polarity + 9 + 1 + read-write + + + POLB_0 + PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + 0 + + + POLB_1 + PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + 0x1 + + + + + POLA + PWM_A Output Polarity + 10 + 1 + read-write + + + POLA_0 + PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + 0 + + + POLA_1 + PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + 0x1 + + + + + PWMX_IN + PWM_X Input + 13 + 1 + read-only + + + PWMB_IN + PWM_B Input + 14 + 1 + read-only + + + PWMA_IN + PWM_A Input + 15 + 1 + read-only + + + + + SM0STS + Status Register + 0x24 + 16 + read-write + 0 + 0xFFFF + + + CMPF + Compare Flags + 0 + 6 + read-write + oneToClear + + + CMPF_0 + No compare event has occurred for a particular VALx value. + 0 + + + CMPF_1 + A compare event has occurred for a particular VALx value. + 0x1 + + + + + CFX0 + Capture Flag X0 + 6 + 1 + read-write + oneToClear + + + CFX1 + Capture Flag X1 + 7 + 1 + read-write + oneToClear + + + CFB0 + Capture Flag B0 + 8 + 1 + read-write + oneToClear + + + CFB1 + Capture Flag B1 + 9 + 1 + read-write + oneToClear + + + CFA0 + Capture Flag A0 + 10 + 1 + read-write + oneToClear + + + CFA1 + Capture Flag A1 + 11 + 1 + read-write + oneToClear + + + RF + Reload Flag + 12 + 1 + read-write + oneToClear + + + RF_0 + No new reload cycle since last STS[RF] clearing + 0 + + + RF_1 + New reload cycle since last STS[RF] clearing + 0x1 + + + + + REF + Reload Error Flag + 13 + 1 + read-write + oneToClear + + + REF_0 + No reload error occurred. + 0 + + + REF_1 + Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + 0x1 + + + + + RUF + Registers Updated Flag + 14 + 1 + read-only + + + RUF_0 + No register update has occurred since last reload. + 0 + + + RUF_1 + At least one of the double buffered registers has been updated since the last reload. + 0x1 + + + + + + + SM0INTEN + Interrupt Enable Register + 0x26 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enables + 0 + 6 + read-write + + + CMPIE_0 + The corresponding STS[CMPF] bit will not cause an interrupt request. + 0 + + + CMPIE_1 + The corresponding STS[CMPF] bit will cause an interrupt request. + 0x1 + + + + + CX0IE + Capture X 0 Interrupt Enable + 6 + 1 + read-write + + + CX0IE_0 + Interrupt request disabled for STS[CFX0]. + 0 + + + CX0IE_1 + Interrupt request enabled for STS[CFX0]. + 0x1 + + + + + CX1IE + Capture X 1 Interrupt Enable + 7 + 1 + read-write + + + CX1IE_0 + Interrupt request disabled for STS[CFX1]. + 0 + + + CX1IE_1 + Interrupt request enabled for STS[CFX1]. + 0x1 + + + + + CB0IE + Capture B 0 Interrupt Enable + 8 + 1 + read-write + + + CB0IE_0 + Interrupt request disabled for STS[CFB0]. + 0 + + + CB0IE_1 + Interrupt request enabled for STS[CFB0]. + 0x1 + + + + + CB1IE + Capture B 1 Interrupt Enable + 9 + 1 + read-write + + + CB1IE_0 + Interrupt request disabled for STS[CFB1]. + 0 + + + CB1IE_1 + Interrupt request enabled for STS[CFB1]. + 0x1 + + + + + CA0IE + Capture A 0 Interrupt Enable + 10 + 1 + read-write + + + CA0IE_0 + Interrupt request disabled for STS[CFA0]. + 0 + + + CA0IE_1 + Interrupt request enabled for STS[CFA0]. + 0x1 + + + + + CA1IE + Capture A 1 Interrupt Enable + 11 + 1 + read-write + + + CA1IE_0 + Interrupt request disabled for STS[CFA1]. + 0 + + + CA1IE_1 + Interrupt request enabled for STS[CFA1]. + 0x1 + + + + + RIE + Reload Interrupt Enable + 12 + 1 + read-write + + + RIE_0 + STS[RF] CPU interrupt requests disabled + 0 + + + RIE_1 + STS[RF] CPU interrupt requests enabled + 0x1 + + + + + REIE + Reload Error Interrupt Enable + 13 + 1 + read-write + + + REIE_0 + STS[REF] CPU interrupt requests disabled + 0 + + + REIE_1 + STS[REF] CPU interrupt requests enabled + 0x1 + + + + + + + SM0DMAEN + DMA Enable Register + 0x28 + 16 + read-write + 0 + 0xFFFF + + + CX0DE + Capture X0 FIFO DMA Enable + 0 + 1 + read-write + + + CX1DE + Capture X1 FIFO DMA Enable + 1 + 1 + read-write + + + CB0DE + Capture B0 FIFO DMA Enable + 2 + 1 + read-write + + + CB1DE + Capture B1 FIFO DMA Enable + 3 + 1 + read-write + + + CA0DE + Capture A0 FIFO DMA Enable + 4 + 1 + read-write + + + CA1DE + Capture A1 FIFO DMA Enable + 5 + 1 + read-write + + + CAPTDE + Capture DMA Enable Source Select + 6 + 2 + read-write + + + CAPTDE_0 + Read DMA requests disabled. + 0 + + + CAPTDE_1 + Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. + 0x1 + + + CAPTDE_2 + A local sync (VAL1 matches counter) sets the read DMA request. + 0x2 + + + CAPTDE_3 + A local reload (STS[RF] being set) sets the read DMA request. + 0x3 + + + + + FAND + FIFO Watermark AND Control + 8 + 1 + read-write + + + FAND_0 + Selected FIFO watermarks are OR'ed together. + 0 + + + FAND_1 + Selected FIFO watermarks are AND'ed together. + 0x1 + + + + + VALDE + Value Registers DMA Enable + 9 + 1 + read-write + + + VALDE_0 + DMA write requests disabled + 0 + + + VALDE_1 + DMA write requests for the VALx and FRACVALx registers enabled + 0x1 + + + + + + + SM0TCTRL + Output Trigger Control Register + 0x2A + 16 + read-write + 0 + 0xFFFF + + + OUT_TRIG_EN + Output Trigger Enables + 0 + 6 + read-write + + + OUT_TRIG_EN_0 + PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + 0 + + + OUT_TRIG_EN_1 + PWM_OUT_TRIGx will set when the counter value matches the VALx value. + 0x1 + + + + + TRGFRQ + Trigger frequency + 12 + 1 + read-write + + + TRGFRQ_0 + Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0 + + + TRGFRQ_1 + Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0x1 + + + + + PWBOT1 + Output Trigger 1 Source Select + 14 + 1 + read-write + + + PWBOT1_0 + Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + 0 + + + PWBOT1_1 + Route the PWMB output to the PWM_OUT_TRIG1 port. + 0x1 + + + + + PWAOT0 + Output Trigger 0 Source Select + 15 + 1 + read-write + + + PWAOT0_0 + Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + 0 + + + PWAOT0_1 + Route the PWMA output to the PWM_OUT_TRIG0 port. + 0x1 + + + + + + + SM0DISMAP0 + Fault Disable Mapping Register 0 + 0x2C + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS0A + PWM_A Fault Disable Mask 0 + 0 + 4 + read-write + + + DIS0B + PWM_B Fault Disable Mask 0 + 4 + 4 + read-write + + + DIS0X + PWM_X Fault Disable Mask 0 + 8 + 4 + read-write + + + + + SM0DISMAP1 + Fault Disable Mapping Register 1 + 0x2E + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS1A + PWM_A Fault Disable Mask 1 + 0 + 4 + read-write + + + DIS1B + PWM_B Fault Disable Mask 1 + 4 + 4 + read-write + + + DIS1X + PWM_X Fault Disable Mask 1 + 8 + 4 + read-write + + + + + SM0DTCNT0 + Deadtime Count Register 0 + 0x30 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT0 + DTCNT0 + 0 + 16 + read-write + + + + + SM0DTCNT1 + Deadtime Count Register 1 + 0x32 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT1 + DTCNT1 + 0 + 16 + read-write + + + + + SM0CAPTCTRLA + Capture Control A Register + 0x34 + 16 + read-write + 0 + 0xFFFF + + + ARMA + Arm A + 0 + 1 + read-write + + + ARMA_0 + Input capture operation is disabled. + 0 + + + ARMA_1 + Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + 0x1 + + + + + ONESHOTA + One Shot Mode A + 1 + 1 + read-write + + + ONESHOTA_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTA_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + 0x1 + + + + + EDGA0 + Edge A 0 + 2 + 2 + read-write + + + EDGA0_0 + Disabled + 0 + + + EDGA0_1 + Capture falling edges + 0x1 + + + EDGA0_2 + Capture rising edges + 0x2 + + + EDGA0_3 + Capture any edge + 0x3 + + + + + EDGA1 + Edge A 1 + 4 + 2 + read-write + + + EDGA1_0 + Disabled + 0 + + + EDGA1_1 + Capture falling edges + 0x1 + + + EDGA1_2 + Capture rising edges + 0x2 + + + EDGA1_3 + Capture any edge + 0x3 + + + + + INP_SELA + Input Select A + 6 + 1 + read-write + + + INP_SELA_0 + Raw PWM_A input signal selected as source. + 0 + + + INP_SELA_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTA_EN + Edge Counter A Enable + 7 + 1 + read-write + + + EDGCNTA_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTA_EN_1 + Edge counter enabled + 0x1 + + + + + CFAWM + Capture A FIFOs Water Mark + 8 + 2 + read-write + + + CA0CNT + Capture A0 FIFO Word Count + 10 + 3 + read-only + + + CA1CNT + Capture A1 FIFO Word Count + 13 + 3 + read-only + + + + + SM0CAPTCOMPA + Capture Compare A Register + 0x36 + 16 + read-write + 0 + 0xFFFF + + + EDGCMPA + Edge Compare A + 0 + 8 + read-write + + + EDGCNTA + Edge Counter A + 8 + 8 + read-only + + + + + SM0CAPTCTRLB + Capture Control B Register + 0x38 + 16 + read-write + 0 + 0xFFFF + + + ARMB + Arm B + 0 + 1 + read-write + + + ARMB_0 + Input capture operation is disabled. + 0 + + + ARMB_1 + Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + 0x1 + + + + + ONESHOTB + One Shot Mode B + 1 + 1 + read-write + + + ONESHOTB_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTB_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + 0x1 + + + + + EDGB0 + Edge B 0 + 2 + 2 + read-write + + + EDGB0_0 + Disabled + 0 + + + EDGB0_1 + Capture falling edges + 0x1 + + + EDGB0_2 + Capture rising edges + 0x2 + + + EDGB0_3 + Capture any edge + 0x3 + + + + + EDGB1 + Edge B 1 + 4 + 2 + read-write + + + EDGB1_0 + Disabled + 0 + + + EDGB1_1 + Capture falling edges + 0x1 + + + EDGB1_2 + Capture rising edges + 0x2 + + + EDGB1_3 + Capture any edge + 0x3 + + + + + INP_SELB + Input Select B + 6 + 1 + read-write + + + INP_SELB_0 + Raw PWM_B input signal selected as source. + 0 + + + INP_SELB_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTB_EN + Edge Counter B Enable + 7 + 1 + read-write + + + EDGCNTB_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTB_EN_1 + Edge counter enabled + 0x1 + + + + + CFBWM + Capture B FIFOs Water Mark + 8 + 2 + read-write + + + CB0CNT + Capture B0 FIFO Word Count + 10 + 3 + read-only + + + CB1CNT + Capture B1 FIFO Word Count + 13 + 3 + read-only + + + + + SM0CAPTCOMPB + Capture Compare B Register + 0x3A + 16 + read-write + 0 + 0xFFFF + + + EDGCMPB + Edge Compare B + 0 + 8 + read-write + + + EDGCNTB + Edge Counter B + 8 + 8 + read-only + + + + + SM0CAPTCTRLX + Capture Control X Register + 0x3C + 16 + read-write + 0 + 0xFFFF + + + ARMX + Arm X + 0 + 1 + read-write + + + ARMX_0 + Input capture operation is disabled. + 0 + + + ARMX_1 + Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + 0x1 + + + + + ONESHOTX + One Shot Mode Aux + 1 + 1 + read-write + + + ONESHOTX_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTX_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + 0x1 + + + + + EDGX0 + Edge X 0 + 2 + 2 + read-write + + + EDGX0_0 + Disabled + 0 + + + EDGX0_1 + Capture falling edges + 0x1 + + + EDGX0_2 + Capture rising edges + 0x2 + + + EDGX0_3 + Capture any edge + 0x3 + + + + + EDGX1 + Edge X 1 + 4 + 2 + read-write + + + EDGX1_0 + Disabled + 0 + + + EDGX1_1 + Capture falling edges + 0x1 + + + EDGX1_2 + Capture rising edges + 0x2 + + + EDGX1_3 + Capture any edge + 0x3 + + + + + INP_SELX + Input Select X + 6 + 1 + read-write + + + INP_SELX_0 + Raw PWM_X input signal selected as source. + 0 + + + INP_SELX_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTX_EN + Edge Counter X Enable + 7 + 1 + read-write + + + EDGCNTX_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTX_EN_1 + Edge counter enabled + 0x1 + + + + + CFXWM + Capture X FIFOs Water Mark + 8 + 2 + read-write + + + CX0CNT + Capture X0 FIFO Word Count + 10 + 3 + read-only + + + CX1CNT + Capture X1 FIFO Word Count + 13 + 3 + read-only + + + + + SM0CAPTCOMPX + Capture Compare X Register + 0x3E + 16 + read-write + 0 + 0xFFFF + + + EDGCMPX + Edge Compare X + 0 + 8 + read-write + + + EDGCNTX + Edge Counter X + 8 + 8 + read-only + + + + + SM0CVAL0 + Capture Value 0 Register + 0x40 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL0 + CAPTVAL0 + 0 + 16 + read-only + + + + + SM0CVAL0CYC + Capture Value 0 Cycle Register + 0x42 + 16 + read-only + 0 + 0xFFFF + + + CVAL0CYC + CVAL0CYC + 0 + 4 + read-only + + + + + SM0CVAL1 + Capture Value 1 Register + 0x44 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL1 + CAPTVAL1 + 0 + 16 + read-only + + + + + SM0CVAL1CYC + Capture Value 1 Cycle Register + 0x46 + 16 + read-only + 0 + 0xFFFF + + + CVAL1CYC + CVAL1CYC + 0 + 4 + read-only + + + + + SM0CVAL2 + Capture Value 2 Register + 0x48 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL2 + CAPTVAL2 + 0 + 16 + read-only + + + + + SM0CVAL2CYC + Capture Value 2 Cycle Register + 0x4A + 16 + read-only + 0 + 0xFFFF + + + CVAL2CYC + CVAL2CYC + 0 + 4 + read-only + + + + + SM0CVAL3 + Capture Value 3 Register + 0x4C + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL3 + CAPTVAL3 + 0 + 16 + read-only + + + + + SM0CVAL3CYC + Capture Value 3 Cycle Register + 0x4E + 16 + read-only + 0 + 0xFFFF + + + CVAL3CYC + CVAL3CYC + 0 + 4 + read-only + + + + + SM0CVAL4 + Capture Value 4 Register + 0x50 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL4 + CAPTVAL4 + 0 + 16 + read-only + + + + + SM0CVAL4CYC + Capture Value 4 Cycle Register + 0x52 + 16 + read-only + 0 + 0xFFFF + + + CVAL4CYC + CVAL4CYC + 0 + 4 + read-only + + + + + SM0CVAL5 + Capture Value 5 Register + 0x54 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL5 + CAPTVAL5 + 0 + 16 + read-only + + + + + SM0CVAL5CYC + Capture Value 5 Cycle Register + 0x56 + 16 + read-only + 0 + 0xFFFF + + + CVAL5CYC + CVAL5CYC + 0 + 4 + read-only + + + + + SM1CNT + Counter Register + 0x60 + 16 + read-only + 0 + 0xFFFF + + + CNT + Counter Register Bits + 0 + 16 + read-only + + + + + SM1INIT + Initial Count Register + 0x62 + 16 + read-write + 0 + 0xFFFF + + + INIT + Initial Count Register Bits + 0 + 16 + read-write + + + + + SM1CTRL2 + Control 2 Register + 0x64 + 16 + read-write + 0 + 0xFFFF + + + CLK_SEL + Clock Source Select + 0 + 2 + read-write + + + CLK_SEL_0 + The IPBus clock is used as the clock for the local prescaler and counter. + 0 + + + CLK_SEL_1 + EXT_CLK is used as the clock for the local prescaler and counter. + 0x1 + + + CLK_SEL_2 + Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. + 0x2 + + + + + RELOAD_SEL + Reload Source Select + 2 + 1 + read-write + + + RELOAD_SEL_0 + The local RELOAD signal is used to reload registers. + 0 + + + RELOAD_SEL_1 + The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. + 0x1 + + + + + FORCE_SEL + This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + 3 + 3 + read-write + + + FORCE_SEL_0 + The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + 0 + + + FORCE_SEL_1 + The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x1 + + + FORCE_SEL_2 + The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + 0x2 + + + FORCE_SEL_3 + The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x3 + + + FORCE_SEL_4 + The local sync signal from this submodule is used to force updates. + 0x4 + + + FORCE_SEL_5 + The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x5 + + + FORCE_SEL_6 + The external force signal, EXT_FORCE, from outside the PWM module causes updates. + 0x6 + + + FORCE_SEL_7 + The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + 0x7 + + + + + FORCE + Force Initialization + 6 + 1 + read-write + + + FRCEN + FRCEN + 7 + 1 + read-write + + + FRCEN_0 + Initialization from a FORCE_OUT is disabled. + 0 + + + FRCEN_1 + Initialization from a FORCE_OUT is enabled. + 0x1 + + + + + INIT_SEL + Initialization Control Select + 8 + 2 + read-write + + + INIT_SEL_0 + Local sync (PWM_X) causes initialization. + 0 + + + INIT_SEL_1 + Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. + 0x1 + + + INIT_SEL_2 + Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. + 0x2 + + + INIT_SEL_3 + EXT_SYNC causes initialization. + 0x3 + + + + + PWMX_INIT + PWM_X Initial Value + 10 + 1 + read-write + + + PWM45_INIT + PWM45 Initial Value + 11 + 1 + read-write + + + PWM23_INIT + PWM23 Initial Value + 12 + 1 + read-write + + + INDEP + Independent or Complementary Pair Operation + 13 + 1 + read-write + + + INDEP_0 + PWM_A and PWM_B form a complementary PWM pair. + 0 + + + INDEP_1 + PWM_A and PWM_B outputs are independent PWMs. + 0x1 + + + + + WAITEN + WAIT Enable + 14 + 1 + read-write + + + DBGEN + Debug Enable + 15 + 1 + read-write + + + + + SM1CTRL + Control Register + 0x66 + 16 + read-write + 0x400 + 0xFFFF + + + DBLEN + Double Switching Enable + 0 + 1 + read-write + + + DBLEN_0 + Double switching disabled. + 0 + + + DBLEN_1 + Double switching enabled. + 0x1 + + + + + DBLX + PWMX Double Switching Enable + 1 + 1 + read-write + + + DBLX_0 + PWMX double pulse disabled. + 0 + + + DBLX_1 + PWMX double pulse enabled. + 0x1 + + + + + LDMOD + Load Mode Select + 2 + 1 + read-write + + + LDMOD_0 + Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + 0 + + + LDMOD_1 + Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + 0x1 + + + + + SPLIT + Split the DBLPWM signal to PWMA and PWMB + 3 + 1 + read-write + + + SPLIT_0 + DBLPWM is not split. PWMA and PWMB each have double pulses. + 0 + + + SPLIT_1 + DBLPWM is split to PWMA and PWMB. + 0x1 + + + + + PRSC + Prescaler + 4 + 3 + read-write + + + PRSC_0 + PWM clock frequency = fclk + 0 + + + PRSC_1 + PWM clock frequency = fclk/2 + 0x1 + + + PRSC_2 + PWM clock frequency = fclk/4 + 0x2 + + + PRSC_3 + PWM clock frequency = fclk/8 + 0x3 + + + PRSC_4 + PWM clock frequency = fclk/16 + 0x4 + + + PRSC_5 + PWM clock frequency = fclk/32 + 0x5 + + + PRSC_6 + PWM clock frequency = fclk/64 + 0x6 + + + PRSC_7 + PWM clock frequency = fclk/128 + 0x7 + + + + + COMPMODE + Compare Mode + 7 + 1 + read-write + + + COMPMODE_0 + The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. + 0 + + + COMPMODE_1 + The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + 0x1 + + + + + DT + Deadtime + 8 + 2 + read-only + + + FULL + Full Cycle Reload + 10 + 1 + read-write + + + FULL_0 + Full-cycle reloads disabled. + 0 + + + FULL_1 + Full-cycle reloads enabled. + 0x1 + + + + + HALF + Half Cycle Reload + 11 + 1 + read-write + + + HALF_0 + Half-cycle reloads disabled. + 0 + + + HALF_1 + Half-cycle reloads enabled. + 0x1 + + + + + LDFQ + Load Frequency + 12 + 4 + read-write + + + LDFQ_0 + Every PWM opportunity + 0 + + + LDFQ_1 + Every 2 PWM opportunities + 0x1 + + + LDFQ_2 + Every 3 PWM opportunities + 0x2 + + + LDFQ_3 + Every 4 PWM opportunities + 0x3 + + + LDFQ_4 + Every 5 PWM opportunities + 0x4 + + + LDFQ_5 + Every 6 PWM opportunities + 0x5 + + + LDFQ_6 + Every 7 PWM opportunities + 0x6 + + + LDFQ_7 + Every 8 PWM opportunities + 0x7 + + + LDFQ_8 + Every 9 PWM opportunities + 0x8 + + + LDFQ_9 + Every 10 PWM opportunities + 0x9 + + + LDFQ_10 + Every 11 PWM opportunities + 0xA + + + LDFQ_11 + Every 12 PWM opportunities + 0xB + + + LDFQ_12 + Every 13 PWM opportunities + 0xC + + + LDFQ_13 + Every 14 PWM opportunities + 0xD + + + LDFQ_14 + Every 15 PWM opportunities + 0xE + + + LDFQ_15 + Every 16 PWM opportunities + 0xF + + + + + + + SM1VAL0 + Value Register 0 + 0x6A + 16 + read-write + 0 + 0xFFFF + + + VAL0 + Value Register 0 + 0 + 16 + read-write + + + + + SM1FRACVAL1 + Fractional Value Register 1 + 0x6C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL1 + Fractional Value 1 Register + 11 + 5 + read-write + + + + + SM1VAL1 + Value Register 1 + 0x6E + 16 + read-write + 0 + 0xFFFF + + + VAL1 + Value Register 1 + 0 + 16 + read-write + + + + + SM1FRACVAL2 + Fractional Value Register 2 + 0x70 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL2 + Fractional Value 2 + 11 + 5 + read-write + + + + + SM1VAL2 + Value Register 2 + 0x72 + 16 + read-write + 0 + 0xFFFF + + + VAL2 + Value Register 2 + 0 + 16 + read-write + + + + + SM1FRACVAL3 + Fractional Value Register 3 + 0x74 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL3 + Fractional Value 3 + 11 + 5 + read-write + + + + + SM1VAL3 + Value Register 3 + 0x76 + 16 + read-write + 0 + 0xFFFF + + + VAL3 + Value Register 3 + 0 + 16 + read-write + + + + + SM1FRACVAL4 + Fractional Value Register 4 + 0x78 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL4 + Fractional Value 4 + 11 + 5 + read-write + + + + + SM1VAL4 + Value Register 4 + 0x7A + 16 + read-write + 0 + 0xFFFF + + + VAL4 + Value Register 4 + 0 + 16 + read-write + + + + + SM1FRACVAL5 + Fractional Value Register 5 + 0x7C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL5 + Fractional Value 5 + 11 + 5 + read-write + + + + + SM1VAL5 + Value Register 5 + 0x7E + 16 + read-write + 0 + 0xFFFF + + + VAL5 + Value Register 5 + 0 + 16 + read-write + + + + + SM1FRCTRL + Fractional Control Register + 0x80 + 16 + read-write + 0 + 0xFFFF + + + FRAC1_EN + Fractional Cycle PWM Period Enable + 1 + 1 + read-write + + + FRAC1_EN_0 + Disable fractional cycle length for the PWM period. + 0 + + + FRAC1_EN_1 + Enable fractional cycle length for the PWM period. + 0x1 + + + + + FRAC23_EN + Fractional Cycle Placement Enable for PWM_A + 2 + 1 + read-write + + + FRAC23_EN_0 + Disable fractional cycle placement for PWM_A. + 0 + + + FRAC23_EN_1 + Enable fractional cycle placement for PWM_A. + 0x1 + + + + + FRAC45_EN + Fractional Cycle Placement Enable for PWM_B + 4 + 1 + read-write + + + FRAC45_EN_0 + Disable fractional cycle placement for PWM_B. + 0 + + + FRAC45_EN_1 + Enable fractional cycle placement for PWM_B. + 0x1 + + + + + FRAC_PU + Fractional Delay Circuit Power Up + 8 + 1 + read-write + + + FRAC_PU_0 + Turn off fractional delay logic. + 0 + + + FRAC_PU_1 + Power up fractional delay logic. + 0x1 + + + + + TEST + Test Status Bit + 15 + 1 + read-only + + + + + SM1OCTRL + Output Control Register + 0x82 + 16 + read-write + 0 + 0xFFFF + + + PWMXFS + PWM_X Fault State + 0 + 2 + read-write + + + PWMXFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMXFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMXFS_2 + Output is tristated. + 0x2 + + + PWMXFS_3 + Output is tristated. + 0x3 + + + + + PWMBFS + PWM_B Fault State + 2 + 2 + read-write + + + PWMBFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMBFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMBFS_2 + Output is tristated. + 0x2 + + + PWMBFS_3 + Output is tristated. + 0x3 + + + + + PWMAFS + PWM_A Fault State + 4 + 2 + read-write + + + PWMAFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMAFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMAFS_2 + Output is tristated. + 0x2 + + + PWMAFS_3 + Output is tristated. + 0x3 + + + + + POLX + PWM_X Output Polarity + 8 + 1 + read-write + + + POLX_0 + PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + 0 + + + POLX_1 + PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + 0x1 + + + + + POLB + PWM_B Output Polarity + 9 + 1 + read-write + + + POLB_0 + PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + 0 + + + POLB_1 + PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + 0x1 + + + + + POLA + PWM_A Output Polarity + 10 + 1 + read-write + + + POLA_0 + PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + 0 + + + POLA_1 + PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + 0x1 + + + + + PWMX_IN + PWM_X Input + 13 + 1 + read-only + + + PWMB_IN + PWM_B Input + 14 + 1 + read-only + + + PWMA_IN + PWM_A Input + 15 + 1 + read-only + + + + + SM1STS + Status Register + 0x84 + 16 + read-write + 0 + 0xFFFF + + + CMPF + Compare Flags + 0 + 6 + read-write + oneToClear + + + CMPF_0 + No compare event has occurred for a particular VALx value. + 0 + + + CMPF_1 + A compare event has occurred for a particular VALx value. + 0x1 + + + + + CFX0 + Capture Flag X0 + 6 + 1 + read-write + oneToClear + + + CFX1 + Capture Flag X1 + 7 + 1 + read-write + oneToClear + + + CFB0 + Capture Flag B0 + 8 + 1 + read-write + oneToClear + + + CFB1 + Capture Flag B1 + 9 + 1 + read-write + oneToClear + + + CFA0 + Capture Flag A0 + 10 + 1 + read-write + oneToClear + + + CFA1 + Capture Flag A1 + 11 + 1 + read-write + oneToClear + + + RF + Reload Flag + 12 + 1 + read-write + oneToClear + + + RF_0 + No new reload cycle since last STS[RF] clearing + 0 + + + RF_1 + New reload cycle since last STS[RF] clearing + 0x1 + + + + + REF + Reload Error Flag + 13 + 1 + read-write + oneToClear + + + REF_0 + No reload error occurred. + 0 + + + REF_1 + Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + 0x1 + + + + + RUF + Registers Updated Flag + 14 + 1 + read-only + + + RUF_0 + No register update has occurred since last reload. + 0 + + + RUF_1 + At least one of the double buffered registers has been updated since the last reload. + 0x1 + + + + + + + SM1INTEN + Interrupt Enable Register + 0x86 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enables + 0 + 6 + read-write + + + CMPIE_0 + The corresponding STS[CMPF] bit will not cause an interrupt request. + 0 + + + CMPIE_1 + The corresponding STS[CMPF] bit will cause an interrupt request. + 0x1 + + + + + CX0IE + Capture X 0 Interrupt Enable + 6 + 1 + read-write + + + CX0IE_0 + Interrupt request disabled for STS[CFX0]. + 0 + + + CX0IE_1 + Interrupt request enabled for STS[CFX0]. + 0x1 + + + + + CX1IE + Capture X 1 Interrupt Enable + 7 + 1 + read-write + + + CX1IE_0 + Interrupt request disabled for STS[CFX1]. + 0 + + + CX1IE_1 + Interrupt request enabled for STS[CFX1]. + 0x1 + + + + + CB0IE + Capture B 0 Interrupt Enable + 8 + 1 + read-write + + + CB0IE_0 + Interrupt request disabled for STS[CFB0]. + 0 + + + CB0IE_1 + Interrupt request enabled for STS[CFB0]. + 0x1 + + + + + CB1IE + Capture B 1 Interrupt Enable + 9 + 1 + read-write + + + CB1IE_0 + Interrupt request disabled for STS[CFB1]. + 0 + + + CB1IE_1 + Interrupt request enabled for STS[CFB1]. + 0x1 + + + + + CA0IE + Capture A 0 Interrupt Enable + 10 + 1 + read-write + + + CA0IE_0 + Interrupt request disabled for STS[CFA0]. + 0 + + + CA0IE_1 + Interrupt request enabled for STS[CFA0]. + 0x1 + + + + + CA1IE + Capture A 1 Interrupt Enable + 11 + 1 + read-write + + + CA1IE_0 + Interrupt request disabled for STS[CFA1]. + 0 + + + CA1IE_1 + Interrupt request enabled for STS[CFA1]. + 0x1 + + + + + RIE + Reload Interrupt Enable + 12 + 1 + read-write + + + RIE_0 + STS[RF] CPU interrupt requests disabled + 0 + + + RIE_1 + STS[RF] CPU interrupt requests enabled + 0x1 + + + + + REIE + Reload Error Interrupt Enable + 13 + 1 + read-write + + + REIE_0 + STS[REF] CPU interrupt requests disabled + 0 + + + REIE_1 + STS[REF] CPU interrupt requests enabled + 0x1 + + + + + + + SM1DMAEN + DMA Enable Register + 0x88 + 16 + read-write + 0 + 0xFFFF + + + CX0DE + Capture X0 FIFO DMA Enable + 0 + 1 + read-write + + + CX1DE + Capture X1 FIFO DMA Enable + 1 + 1 + read-write + + + CB0DE + Capture B0 FIFO DMA Enable + 2 + 1 + read-write + + + CB1DE + Capture B1 FIFO DMA Enable + 3 + 1 + read-write + + + CA0DE + Capture A0 FIFO DMA Enable + 4 + 1 + read-write + + + CA1DE + Capture A1 FIFO DMA Enable + 5 + 1 + read-write + + + CAPTDE + Capture DMA Enable Source Select + 6 + 2 + read-write + + + CAPTDE_0 + Read DMA requests disabled. + 0 + + + CAPTDE_1 + Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. + 0x1 + + + CAPTDE_2 + A local sync (VAL1 matches counter) sets the read DMA request. + 0x2 + + + CAPTDE_3 + A local reload (STS[RF] being set) sets the read DMA request. + 0x3 + + + + + FAND + FIFO Watermark AND Control + 8 + 1 + read-write + + + FAND_0 + Selected FIFO watermarks are OR'ed together. + 0 + + + FAND_1 + Selected FIFO watermarks are AND'ed together. + 0x1 + + + + + VALDE + Value Registers DMA Enable + 9 + 1 + read-write + + + VALDE_0 + DMA write requests disabled + 0 + + + VALDE_1 + DMA write requests for the VALx and FRACVALx registers enabled + 0x1 + + + + + + + SM1TCTRL + Output Trigger Control Register + 0x8A + 16 + read-write + 0 + 0xFFFF + + + OUT_TRIG_EN + Output Trigger Enables + 0 + 6 + read-write + + + OUT_TRIG_EN_0 + PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + 0 + + + OUT_TRIG_EN_1 + PWM_OUT_TRIGx will set when the counter value matches the VALx value. + 0x1 + + + + + TRGFRQ + Trigger frequency + 12 + 1 + read-write + + + TRGFRQ_0 + Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0 + + + TRGFRQ_1 + Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0x1 + + + + + PWBOT1 + Output Trigger 1 Source Select + 14 + 1 + read-write + + + PWBOT1_0 + Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + 0 + + + PWBOT1_1 + Route the PWMB output to the PWM_OUT_TRIG1 port. + 0x1 + + + + + PWAOT0 + Output Trigger 0 Source Select + 15 + 1 + read-write + + + PWAOT0_0 + Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + 0 + + + PWAOT0_1 + Route the PWMA output to the PWM_OUT_TRIG0 port. + 0x1 + + + + + + + SM1DISMAP0 + Fault Disable Mapping Register 0 + 0x8C + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS0A + PWM_A Fault Disable Mask 0 + 0 + 4 + read-write + + + DIS0B + PWM_B Fault Disable Mask 0 + 4 + 4 + read-write + + + DIS0X + PWM_X Fault Disable Mask 0 + 8 + 4 + read-write + + + + + SM1DISMAP1 + Fault Disable Mapping Register 1 + 0x8E + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS1A + PWM_A Fault Disable Mask 1 + 0 + 4 + read-write + + + DIS1B + PWM_B Fault Disable Mask 1 + 4 + 4 + read-write + + + DIS1X + PWM_X Fault Disable Mask 1 + 8 + 4 + read-write + + + + + SM1DTCNT0 + Deadtime Count Register 0 + 0x90 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT0 + DTCNT0 + 0 + 16 + read-write + + + + + SM1DTCNT1 + Deadtime Count Register 1 + 0x92 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT1 + DTCNT1 + 0 + 16 + read-write + + + + + SM1CAPTCTRLA + Capture Control A Register + 0x94 + 16 + read-write + 0 + 0xFFFF + + + ARMA + Arm A + 0 + 1 + read-write + + + ARMA_0 + Input capture operation is disabled. + 0 + + + ARMA_1 + Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + 0x1 + + + + + ONESHOTA + One Shot Mode A + 1 + 1 + read-write + + + ONESHOTA_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTA_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + 0x1 + + + + + EDGA0 + Edge A 0 + 2 + 2 + read-write + + + EDGA0_0 + Disabled + 0 + + + EDGA0_1 + Capture falling edges + 0x1 + + + EDGA0_2 + Capture rising edges + 0x2 + + + EDGA0_3 + Capture any edge + 0x3 + + + + + EDGA1 + Edge A 1 + 4 + 2 + read-write + + + EDGA1_0 + Disabled + 0 + + + EDGA1_1 + Capture falling edges + 0x1 + + + EDGA1_2 + Capture rising edges + 0x2 + + + EDGA1_3 + Capture any edge + 0x3 + + + + + INP_SELA + Input Select A + 6 + 1 + read-write + + + INP_SELA_0 + Raw PWM_A input signal selected as source. + 0 + + + INP_SELA_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTA_EN + Edge Counter A Enable + 7 + 1 + read-write + + + EDGCNTA_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTA_EN_1 + Edge counter enabled + 0x1 + + + + + CFAWM + Capture A FIFOs Water Mark + 8 + 2 + read-write + + + CA0CNT + Capture A0 FIFO Word Count + 10 + 3 + read-only + + + CA1CNT + Capture A1 FIFO Word Count + 13 + 3 + read-only + + + + + SM1CAPTCOMPA + Capture Compare A Register + 0x96 + 16 + read-write + 0 + 0xFFFF + + + EDGCMPA + Edge Compare A + 0 + 8 + read-write + + + EDGCNTA + Edge Counter A + 8 + 8 + read-only + + + + + SM1CAPTCTRLB + Capture Control B Register + 0x98 + 16 + read-write + 0 + 0xFFFF + + + ARMB + Arm B + 0 + 1 + read-write + + + ARMB_0 + Input capture operation is disabled. + 0 + + + ARMB_1 + Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + 0x1 + + + + + ONESHOTB + One Shot Mode B + 1 + 1 + read-write + + + ONESHOTB_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTB_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + 0x1 + + + + + EDGB0 + Edge B 0 + 2 + 2 + read-write + + + EDGB0_0 + Disabled + 0 + + + EDGB0_1 + Capture falling edges + 0x1 + + + EDGB0_2 + Capture rising edges + 0x2 + + + EDGB0_3 + Capture any edge + 0x3 + + + + + EDGB1 + Edge B 1 + 4 + 2 + read-write + + + EDGB1_0 + Disabled + 0 + + + EDGB1_1 + Capture falling edges + 0x1 + + + EDGB1_2 + Capture rising edges + 0x2 + + + EDGB1_3 + Capture any edge + 0x3 + + + + + INP_SELB + Input Select B + 6 + 1 + read-write + + + INP_SELB_0 + Raw PWM_B input signal selected as source. + 0 + + + INP_SELB_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTB_EN + Edge Counter B Enable + 7 + 1 + read-write + + + EDGCNTB_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTB_EN_1 + Edge counter enabled + 0x1 + + + + + CFBWM + Capture B FIFOs Water Mark + 8 + 2 + read-write + + + CB0CNT + Capture B0 FIFO Word Count + 10 + 3 + read-only + + + CB1CNT + Capture B1 FIFO Word Count + 13 + 3 + read-only + + + + + SM1CAPTCOMPB + Capture Compare B Register + 0x9A + 16 + read-write + 0 + 0xFFFF + + + EDGCMPB + Edge Compare B + 0 + 8 + read-write + + + EDGCNTB + Edge Counter B + 8 + 8 + read-only + + + + + SM1CAPTCTRLX + Capture Control X Register + 0x9C + 16 + read-write + 0 + 0xFFFF + + + ARMX + Arm X + 0 + 1 + read-write + + + ARMX_0 + Input capture operation is disabled. + 0 + + + ARMX_1 + Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + 0x1 + + + + + ONESHOTX + One Shot Mode Aux + 1 + 1 + read-write + + + ONESHOTX_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTX_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + 0x1 + + + + + EDGX0 + Edge X 0 + 2 + 2 + read-write + + + EDGX0_0 + Disabled + 0 + + + EDGX0_1 + Capture falling edges + 0x1 + + + EDGX0_2 + Capture rising edges + 0x2 + + + EDGX0_3 + Capture any edge + 0x3 + + + + + EDGX1 + Edge X 1 + 4 + 2 + read-write + + + EDGX1_0 + Disabled + 0 + + + EDGX1_1 + Capture falling edges + 0x1 + + + EDGX1_2 + Capture rising edges + 0x2 + + + EDGX1_3 + Capture any edge + 0x3 + + + + + INP_SELX + Input Select X + 6 + 1 + read-write + + + INP_SELX_0 + Raw PWM_X input signal selected as source. + 0 + + + INP_SELX_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTX_EN + Edge Counter X Enable + 7 + 1 + read-write + + + EDGCNTX_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTX_EN_1 + Edge counter enabled + 0x1 + + + + + CFXWM + Capture X FIFOs Water Mark + 8 + 2 + read-write + + + CX0CNT + Capture X0 FIFO Word Count + 10 + 3 + read-only + + + CX1CNT + Capture X1 FIFO Word Count + 13 + 3 + read-only + + + + + SM1CAPTCOMPX + Capture Compare X Register + 0x9E + 16 + read-write + 0 + 0xFFFF + + + EDGCMPX + Edge Compare X + 0 + 8 + read-write + + + EDGCNTX + Edge Counter X + 8 + 8 + read-only + + + + + SM1CVAL0 + Capture Value 0 Register + 0xA0 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL0 + CAPTVAL0 + 0 + 16 + read-only + + + + + SM1CVAL0CYC + Capture Value 0 Cycle Register + 0xA2 + 16 + read-only + 0 + 0xFFFF + + + CVAL0CYC + CVAL0CYC + 0 + 4 + read-only + + + + + SM1CVAL1 + Capture Value 1 Register + 0xA4 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL1 + CAPTVAL1 + 0 + 16 + read-only + + + + + SM1CVAL1CYC + Capture Value 1 Cycle Register + 0xA6 + 16 + read-only + 0 + 0xFFFF + + + CVAL1CYC + CVAL1CYC + 0 + 4 + read-only + + + + + SM1CVAL2 + Capture Value 2 Register + 0xA8 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL2 + CAPTVAL2 + 0 + 16 + read-only + + + + + SM1CVAL2CYC + Capture Value 2 Cycle Register + 0xAA + 16 + read-only + 0 + 0xFFFF + + + CVAL2CYC + CVAL2CYC + 0 + 4 + read-only + + + + + SM1CVAL3 + Capture Value 3 Register + 0xAC + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL3 + CAPTVAL3 + 0 + 16 + read-only + + + + + SM1CVAL3CYC + Capture Value 3 Cycle Register + 0xAE + 16 + read-only + 0 + 0xFFFF + + + CVAL3CYC + CVAL3CYC + 0 + 4 + read-only + + + + + SM1CVAL4 + Capture Value 4 Register + 0xB0 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL4 + CAPTVAL4 + 0 + 16 + read-only + + + + + SM1CVAL4CYC + Capture Value 4 Cycle Register + 0xB2 + 16 + read-only + 0 + 0xFFFF + + + CVAL4CYC + CVAL4CYC + 0 + 4 + read-only + + + + + SM1CVAL5 + Capture Value 5 Register + 0xB4 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL5 + CAPTVAL5 + 0 + 16 + read-only + + + + + SM1CVAL5CYC + Capture Value 5 Cycle Register + 0xB6 + 16 + read-only + 0 + 0xFFFF + + + CVAL5CYC + CVAL5CYC + 0 + 4 + read-only + + + + + SM2CNT + Counter Register + 0xC0 + 16 + read-only + 0 + 0xFFFF + + + CNT + Counter Register Bits + 0 + 16 + read-only + + + + + SM2INIT + Initial Count Register + 0xC2 + 16 + read-write + 0 + 0xFFFF + + + INIT + Initial Count Register Bits + 0 + 16 + read-write + + + + + SM2CTRL2 + Control 2 Register + 0xC4 + 16 + read-write + 0 + 0xFFFF + + + CLK_SEL + Clock Source Select + 0 + 2 + read-write + + + CLK_SEL_0 + The IPBus clock is used as the clock for the local prescaler and counter. + 0 + + + CLK_SEL_1 + EXT_CLK is used as the clock for the local prescaler and counter. + 0x1 + + + CLK_SEL_2 + Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. + 0x2 + + + + + RELOAD_SEL + Reload Source Select + 2 + 1 + read-write + + + RELOAD_SEL_0 + The local RELOAD signal is used to reload registers. + 0 + + + RELOAD_SEL_1 + The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. + 0x1 + + + + + FORCE_SEL + This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + 3 + 3 + read-write + + + FORCE_SEL_0 + The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + 0 + + + FORCE_SEL_1 + The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x1 + + + FORCE_SEL_2 + The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + 0x2 + + + FORCE_SEL_3 + The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x3 + + + FORCE_SEL_4 + The local sync signal from this submodule is used to force updates. + 0x4 + + + FORCE_SEL_5 + The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x5 + + + FORCE_SEL_6 + The external force signal, EXT_FORCE, from outside the PWM module causes updates. + 0x6 + + + FORCE_SEL_7 + The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + 0x7 + + + + + FORCE + Force Initialization + 6 + 1 + read-write + + + FRCEN + FRCEN + 7 + 1 + read-write + + + FRCEN_0 + Initialization from a FORCE_OUT is disabled. + 0 + + + FRCEN_1 + Initialization from a FORCE_OUT is enabled. + 0x1 + + + + + INIT_SEL + Initialization Control Select + 8 + 2 + read-write + + + INIT_SEL_0 + Local sync (PWM_X) causes initialization. + 0 + + + INIT_SEL_1 + Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. + 0x1 + + + INIT_SEL_2 + Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. + 0x2 + + + INIT_SEL_3 + EXT_SYNC causes initialization. + 0x3 + + + + + PWMX_INIT + PWM_X Initial Value + 10 + 1 + read-write + + + PWM45_INIT + PWM45 Initial Value + 11 + 1 + read-write + + + PWM23_INIT + PWM23 Initial Value + 12 + 1 + read-write + + + INDEP + Independent or Complementary Pair Operation + 13 + 1 + read-write + + + INDEP_0 + PWM_A and PWM_B form a complementary PWM pair. + 0 + + + INDEP_1 + PWM_A and PWM_B outputs are independent PWMs. + 0x1 + + + + + WAITEN + WAIT Enable + 14 + 1 + read-write + + + DBGEN + Debug Enable + 15 + 1 + read-write + + + + + SM2CTRL + Control Register + 0xC6 + 16 + read-write + 0x400 + 0xFFFF + + + DBLEN + Double Switching Enable + 0 + 1 + read-write + + + DBLEN_0 + Double switching disabled. + 0 + + + DBLEN_1 + Double switching enabled. + 0x1 + + + + + DBLX + PWMX Double Switching Enable + 1 + 1 + read-write + + + DBLX_0 + PWMX double pulse disabled. + 0 + + + DBLX_1 + PWMX double pulse enabled. + 0x1 + + + + + LDMOD + Load Mode Select + 2 + 1 + read-write + + + LDMOD_0 + Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + 0 + + + LDMOD_1 + Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + 0x1 + + + + + SPLIT + Split the DBLPWM signal to PWMA and PWMB + 3 + 1 + read-write + + + SPLIT_0 + DBLPWM is not split. PWMA and PWMB each have double pulses. + 0 + + + SPLIT_1 + DBLPWM is split to PWMA and PWMB. + 0x1 + + + + + PRSC + Prescaler + 4 + 3 + read-write + + + PRSC_0 + PWM clock frequency = fclk + 0 + + + PRSC_1 + PWM clock frequency = fclk/2 + 0x1 + + + PRSC_2 + PWM clock frequency = fclk/4 + 0x2 + + + PRSC_3 + PWM clock frequency = fclk/8 + 0x3 + + + PRSC_4 + PWM clock frequency = fclk/16 + 0x4 + + + PRSC_5 + PWM clock frequency = fclk/32 + 0x5 + + + PRSC_6 + PWM clock frequency = fclk/64 + 0x6 + + + PRSC_7 + PWM clock frequency = fclk/128 + 0x7 + + + + + COMPMODE + Compare Mode + 7 + 1 + read-write + + + COMPMODE_0 + The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. + 0 + + + COMPMODE_1 + The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + 0x1 + + + + + DT + Deadtime + 8 + 2 + read-only + + + FULL + Full Cycle Reload + 10 + 1 + read-write + + + FULL_0 + Full-cycle reloads disabled. + 0 + + + FULL_1 + Full-cycle reloads enabled. + 0x1 + + + + + HALF + Half Cycle Reload + 11 + 1 + read-write + + + HALF_0 + Half-cycle reloads disabled. + 0 + + + HALF_1 + Half-cycle reloads enabled. + 0x1 + + + + + LDFQ + Load Frequency + 12 + 4 + read-write + + + LDFQ_0 + Every PWM opportunity + 0 + + + LDFQ_1 + Every 2 PWM opportunities + 0x1 + + + LDFQ_2 + Every 3 PWM opportunities + 0x2 + + + LDFQ_3 + Every 4 PWM opportunities + 0x3 + + + LDFQ_4 + Every 5 PWM opportunities + 0x4 + + + LDFQ_5 + Every 6 PWM opportunities + 0x5 + + + LDFQ_6 + Every 7 PWM opportunities + 0x6 + + + LDFQ_7 + Every 8 PWM opportunities + 0x7 + + + LDFQ_8 + Every 9 PWM opportunities + 0x8 + + + LDFQ_9 + Every 10 PWM opportunities + 0x9 + + + LDFQ_10 + Every 11 PWM opportunities + 0xA + + + LDFQ_11 + Every 12 PWM opportunities + 0xB + + + LDFQ_12 + Every 13 PWM opportunities + 0xC + + + LDFQ_13 + Every 14 PWM opportunities + 0xD + + + LDFQ_14 + Every 15 PWM opportunities + 0xE + + + LDFQ_15 + Every 16 PWM opportunities + 0xF + + + + + + + SM2VAL0 + Value Register 0 + 0xCA + 16 + read-write + 0 + 0xFFFF + + + VAL0 + Value Register 0 + 0 + 16 + read-write + + + + + SM2FRACVAL1 + Fractional Value Register 1 + 0xCC + 16 + read-write + 0 + 0xFFFF + + + FRACVAL1 + Fractional Value 1 Register + 11 + 5 + read-write + + + + + SM2VAL1 + Value Register 1 + 0xCE + 16 + read-write + 0 + 0xFFFF + + + VAL1 + Value Register 1 + 0 + 16 + read-write + + + + + SM2FRACVAL2 + Fractional Value Register 2 + 0xD0 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL2 + Fractional Value 2 + 11 + 5 + read-write + + + + + SM2VAL2 + Value Register 2 + 0xD2 + 16 + read-write + 0 + 0xFFFF + + + VAL2 + Value Register 2 + 0 + 16 + read-write + + + + + SM2FRACVAL3 + Fractional Value Register 3 + 0xD4 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL3 + Fractional Value 3 + 11 + 5 + read-write + + + + + SM2VAL3 + Value Register 3 + 0xD6 + 16 + read-write + 0 + 0xFFFF + + + VAL3 + Value Register 3 + 0 + 16 + read-write + + + + + SM2FRACVAL4 + Fractional Value Register 4 + 0xD8 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL4 + Fractional Value 4 + 11 + 5 + read-write + + + + + SM2VAL4 + Value Register 4 + 0xDA + 16 + read-write + 0 + 0xFFFF + + + VAL4 + Value Register 4 + 0 + 16 + read-write + + + + + SM2FRACVAL5 + Fractional Value Register 5 + 0xDC + 16 + read-write + 0 + 0xFFFF + + + FRACVAL5 + Fractional Value 5 + 11 + 5 + read-write + + + + + SM2VAL5 + Value Register 5 + 0xDE + 16 + read-write + 0 + 0xFFFF + + + VAL5 + Value Register 5 + 0 + 16 + read-write + + + + + SM2FRCTRL + Fractional Control Register + 0xE0 + 16 + read-write + 0 + 0xFFFF + + + FRAC1_EN + Fractional Cycle PWM Period Enable + 1 + 1 + read-write + + + FRAC1_EN_0 + Disable fractional cycle length for the PWM period. + 0 + + + FRAC1_EN_1 + Enable fractional cycle length for the PWM period. + 0x1 + + + + + FRAC23_EN + Fractional Cycle Placement Enable for PWM_A + 2 + 1 + read-write + + + FRAC23_EN_0 + Disable fractional cycle placement for PWM_A. + 0 + + + FRAC23_EN_1 + Enable fractional cycle placement for PWM_A. + 0x1 + + + + + FRAC45_EN + Fractional Cycle Placement Enable for PWM_B + 4 + 1 + read-write + + + FRAC45_EN_0 + Disable fractional cycle placement for PWM_B. + 0 + + + FRAC45_EN_1 + Enable fractional cycle placement for PWM_B. + 0x1 + + + + + FRAC_PU + Fractional Delay Circuit Power Up + 8 + 1 + read-write + + + FRAC_PU_0 + Turn off fractional delay logic. + 0 + + + FRAC_PU_1 + Power up fractional delay logic. + 0x1 + + + + + TEST + Test Status Bit + 15 + 1 + read-only + + + + + SM2OCTRL + Output Control Register + 0xE2 + 16 + read-write + 0 + 0xFFFF + + + PWMXFS + PWM_X Fault State + 0 + 2 + read-write + + + PWMXFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMXFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMXFS_2 + Output is tristated. + 0x2 + + + PWMXFS_3 + Output is tristated. + 0x3 + + + + + PWMBFS + PWM_B Fault State + 2 + 2 + read-write + + + PWMBFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMBFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMBFS_2 + Output is tristated. + 0x2 + + + PWMBFS_3 + Output is tristated. + 0x3 + + + + + PWMAFS + PWM_A Fault State + 4 + 2 + read-write + + + PWMAFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMAFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMAFS_2 + Output is tristated. + 0x2 + + + PWMAFS_3 + Output is tristated. + 0x3 + + + + + POLX + PWM_X Output Polarity + 8 + 1 + read-write + + + POLX_0 + PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + 0 + + + POLX_1 + PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + 0x1 + + + + + POLB + PWM_B Output Polarity + 9 + 1 + read-write + + + POLB_0 + PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + 0 + + + POLB_1 + PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + 0x1 + + + + + POLA + PWM_A Output Polarity + 10 + 1 + read-write + + + POLA_0 + PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + 0 + + + POLA_1 + PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + 0x1 + + + + + PWMX_IN + PWM_X Input + 13 + 1 + read-only + + + PWMB_IN + PWM_B Input + 14 + 1 + read-only + + + PWMA_IN + PWM_A Input + 15 + 1 + read-only + + + + + SM2STS + Status Register + 0xE4 + 16 + read-write + 0 + 0xFFFF + + + CMPF + Compare Flags + 0 + 6 + read-write + oneToClear + + + CMPF_0 + No compare event has occurred for a particular VALx value. + 0 + + + CMPF_1 + A compare event has occurred for a particular VALx value. + 0x1 + + + + + CFX0 + Capture Flag X0 + 6 + 1 + read-write + oneToClear + + + CFX1 + Capture Flag X1 + 7 + 1 + read-write + oneToClear + + + CFB0 + Capture Flag B0 + 8 + 1 + read-write + oneToClear + + + CFB1 + Capture Flag B1 + 9 + 1 + read-write + oneToClear + + + CFA0 + Capture Flag A0 + 10 + 1 + read-write + oneToClear + + + CFA1 + Capture Flag A1 + 11 + 1 + read-write + oneToClear + + + RF + Reload Flag + 12 + 1 + read-write + oneToClear + + + RF_0 + No new reload cycle since last STS[RF] clearing + 0 + + + RF_1 + New reload cycle since last STS[RF] clearing + 0x1 + + + + + REF + Reload Error Flag + 13 + 1 + read-write + oneToClear + + + REF_0 + No reload error occurred. + 0 + + + REF_1 + Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + 0x1 + + + + + RUF + Registers Updated Flag + 14 + 1 + read-only + + + RUF_0 + No register update has occurred since last reload. + 0 + + + RUF_1 + At least one of the double buffered registers has been updated since the last reload. + 0x1 + + + + + + + SM2INTEN + Interrupt Enable Register + 0xE6 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enables + 0 + 6 + read-write + + + CMPIE_0 + The corresponding STS[CMPF] bit will not cause an interrupt request. + 0 + + + CMPIE_1 + The corresponding STS[CMPF] bit will cause an interrupt request. + 0x1 + + + + + CX0IE + Capture X 0 Interrupt Enable + 6 + 1 + read-write + + + CX0IE_0 + Interrupt request disabled for STS[CFX0]. + 0 + + + CX0IE_1 + Interrupt request enabled for STS[CFX0]. + 0x1 + + + + + CX1IE + Capture X 1 Interrupt Enable + 7 + 1 + read-write + + + CX1IE_0 + Interrupt request disabled for STS[CFX1]. + 0 + + + CX1IE_1 + Interrupt request enabled for STS[CFX1]. + 0x1 + + + + + CB0IE + Capture B 0 Interrupt Enable + 8 + 1 + read-write + + + CB0IE_0 + Interrupt request disabled for STS[CFB0]. + 0 + + + CB0IE_1 + Interrupt request enabled for STS[CFB0]. + 0x1 + + + + + CB1IE + Capture B 1 Interrupt Enable + 9 + 1 + read-write + + + CB1IE_0 + Interrupt request disabled for STS[CFB1]. + 0 + + + CB1IE_1 + Interrupt request enabled for STS[CFB1]. + 0x1 + + + + + CA0IE + Capture A 0 Interrupt Enable + 10 + 1 + read-write + + + CA0IE_0 + Interrupt request disabled for STS[CFA0]. + 0 + + + CA0IE_1 + Interrupt request enabled for STS[CFA0]. + 0x1 + + + + + CA1IE + Capture A 1 Interrupt Enable + 11 + 1 + read-write + + + CA1IE_0 + Interrupt request disabled for STS[CFA1]. + 0 + + + CA1IE_1 + Interrupt request enabled for STS[CFA1]. + 0x1 + + + + + RIE + Reload Interrupt Enable + 12 + 1 + read-write + + + RIE_0 + STS[RF] CPU interrupt requests disabled + 0 + + + RIE_1 + STS[RF] CPU interrupt requests enabled + 0x1 + + + + + REIE + Reload Error Interrupt Enable + 13 + 1 + read-write + + + REIE_0 + STS[REF] CPU interrupt requests disabled + 0 + + + REIE_1 + STS[REF] CPU interrupt requests enabled + 0x1 + + + + + + + SM2DMAEN + DMA Enable Register + 0xE8 + 16 + read-write + 0 + 0xFFFF + + + CX0DE + Capture X0 FIFO DMA Enable + 0 + 1 + read-write + + + CX1DE + Capture X1 FIFO DMA Enable + 1 + 1 + read-write + + + CB0DE + Capture B0 FIFO DMA Enable + 2 + 1 + read-write + + + CB1DE + Capture B1 FIFO DMA Enable + 3 + 1 + read-write + + + CA0DE + Capture A0 FIFO DMA Enable + 4 + 1 + read-write + + + CA1DE + Capture A1 FIFO DMA Enable + 5 + 1 + read-write + + + CAPTDE + Capture DMA Enable Source Select + 6 + 2 + read-write + + + CAPTDE_0 + Read DMA requests disabled. + 0 + + + CAPTDE_1 + Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. + 0x1 + + + CAPTDE_2 + A local sync (VAL1 matches counter) sets the read DMA request. + 0x2 + + + CAPTDE_3 + A local reload (STS[RF] being set) sets the read DMA request. + 0x3 + + + + + FAND + FIFO Watermark AND Control + 8 + 1 + read-write + + + FAND_0 + Selected FIFO watermarks are OR'ed together. + 0 + + + FAND_1 + Selected FIFO watermarks are AND'ed together. + 0x1 + + + + + VALDE + Value Registers DMA Enable + 9 + 1 + read-write + + + VALDE_0 + DMA write requests disabled + 0 + + + VALDE_1 + DMA write requests for the VALx and FRACVALx registers enabled + 0x1 + + + + + + + SM2TCTRL + Output Trigger Control Register + 0xEA + 16 + read-write + 0 + 0xFFFF + + + OUT_TRIG_EN + Output Trigger Enables + 0 + 6 + read-write + + + OUT_TRIG_EN_0 + PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + 0 + + + OUT_TRIG_EN_1 + PWM_OUT_TRIGx will set when the counter value matches the VALx value. + 0x1 + + + + + TRGFRQ + Trigger frequency + 12 + 1 + read-write + + + TRGFRQ_0 + Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0 + + + TRGFRQ_1 + Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0x1 + + + + + PWBOT1 + Output Trigger 1 Source Select + 14 + 1 + read-write + + + PWBOT1_0 + Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + 0 + + + PWBOT1_1 + Route the PWMB output to the PWM_OUT_TRIG1 port. + 0x1 + + + + + PWAOT0 + Output Trigger 0 Source Select + 15 + 1 + read-write + + + PWAOT0_0 + Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + 0 + + + PWAOT0_1 + Route the PWMA output to the PWM_OUT_TRIG0 port. + 0x1 + + + + + + + SM2DISMAP0 + Fault Disable Mapping Register 0 + 0xEC + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS0A + PWM_A Fault Disable Mask 0 + 0 + 4 + read-write + + + DIS0B + PWM_B Fault Disable Mask 0 + 4 + 4 + read-write + + + DIS0X + PWM_X Fault Disable Mask 0 + 8 + 4 + read-write + + + + + SM2DISMAP1 + Fault Disable Mapping Register 1 + 0xEE + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS1A + PWM_A Fault Disable Mask 1 + 0 + 4 + read-write + + + DIS1B + PWM_B Fault Disable Mask 1 + 4 + 4 + read-write + + + DIS1X + PWM_X Fault Disable Mask 1 + 8 + 4 + read-write + + + + + SM2DTCNT0 + Deadtime Count Register 0 + 0xF0 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT0 + DTCNT0 + 0 + 16 + read-write + + + + + SM2DTCNT1 + Deadtime Count Register 1 + 0xF2 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT1 + DTCNT1 + 0 + 16 + read-write + + + + + SM2CAPTCTRLA + Capture Control A Register + 0xF4 + 16 + read-write + 0 + 0xFFFF + + + ARMA + Arm A + 0 + 1 + read-write + + + ARMA_0 + Input capture operation is disabled. + 0 + + + ARMA_1 + Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + 0x1 + + + + + ONESHOTA + One Shot Mode A + 1 + 1 + read-write + + + ONESHOTA_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTA_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + 0x1 + + + + + EDGA0 + Edge A 0 + 2 + 2 + read-write + + + EDGA0_0 + Disabled + 0 + + + EDGA0_1 + Capture falling edges + 0x1 + + + EDGA0_2 + Capture rising edges + 0x2 + + + EDGA0_3 + Capture any edge + 0x3 + + + + + EDGA1 + Edge A 1 + 4 + 2 + read-write + + + EDGA1_0 + Disabled + 0 + + + EDGA1_1 + Capture falling edges + 0x1 + + + EDGA1_2 + Capture rising edges + 0x2 + + + EDGA1_3 + Capture any edge + 0x3 + + + + + INP_SELA + Input Select A + 6 + 1 + read-write + + + INP_SELA_0 + Raw PWM_A input signal selected as source. + 0 + + + INP_SELA_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTA_EN + Edge Counter A Enable + 7 + 1 + read-write + + + EDGCNTA_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTA_EN_1 + Edge counter enabled + 0x1 + + + + + CFAWM + Capture A FIFOs Water Mark + 8 + 2 + read-write + + + CA0CNT + Capture A0 FIFO Word Count + 10 + 3 + read-only + + + CA1CNT + Capture A1 FIFO Word Count + 13 + 3 + read-only + + + + + SM2CAPTCOMPA + Capture Compare A Register + 0xF6 + 16 + read-write + 0 + 0xFFFF + + + EDGCMPA + Edge Compare A + 0 + 8 + read-write + + + EDGCNTA + Edge Counter A + 8 + 8 + read-only + + + + + SM2CAPTCTRLB + Capture Control B Register + 0xF8 + 16 + read-write + 0 + 0xFFFF + + + ARMB + Arm B + 0 + 1 + read-write + + + ARMB_0 + Input capture operation is disabled. + 0 + + + ARMB_1 + Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + 0x1 + + + + + ONESHOTB + One Shot Mode B + 1 + 1 + read-write + + + ONESHOTB_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTB_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + 0x1 + + + + + EDGB0 + Edge B 0 + 2 + 2 + read-write + + + EDGB0_0 + Disabled + 0 + + + EDGB0_1 + Capture falling edges + 0x1 + + + EDGB0_2 + Capture rising edges + 0x2 + + + EDGB0_3 + Capture any edge + 0x3 + + + + + EDGB1 + Edge B 1 + 4 + 2 + read-write + + + EDGB1_0 + Disabled + 0 + + + EDGB1_1 + Capture falling edges + 0x1 + + + EDGB1_2 + Capture rising edges + 0x2 + + + EDGB1_3 + Capture any edge + 0x3 + + + + + INP_SELB + Input Select B + 6 + 1 + read-write + + + INP_SELB_0 + Raw PWM_B input signal selected as source. + 0 + + + INP_SELB_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTB_EN + Edge Counter B Enable + 7 + 1 + read-write + + + EDGCNTB_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTB_EN_1 + Edge counter enabled + 0x1 + + + + + CFBWM + Capture B FIFOs Water Mark + 8 + 2 + read-write + + + CB0CNT + Capture B0 FIFO Word Count + 10 + 3 + read-only + + + CB1CNT + Capture B1 FIFO Word Count + 13 + 3 + read-only + + + + + SM2CAPTCOMPB + Capture Compare B Register + 0xFA + 16 + read-write + 0 + 0xFFFF + + + EDGCMPB + Edge Compare B + 0 + 8 + read-write + + + EDGCNTB + Edge Counter B + 8 + 8 + read-only + + + + + SM2CAPTCTRLX + Capture Control X Register + 0xFC + 16 + read-write + 0 + 0xFFFF + + + ARMX + Arm X + 0 + 1 + read-write + + + ARMX_0 + Input capture operation is disabled. + 0 + + + ARMX_1 + Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + 0x1 + + + + + ONESHOTX + One Shot Mode Aux + 1 + 1 + read-write + + + ONESHOTX_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTX_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + 0x1 + + + + + EDGX0 + Edge X 0 + 2 + 2 + read-write + + + EDGX0_0 + Disabled + 0 + + + EDGX0_1 + Capture falling edges + 0x1 + + + EDGX0_2 + Capture rising edges + 0x2 + + + EDGX0_3 + Capture any edge + 0x3 + + + + + EDGX1 + Edge X 1 + 4 + 2 + read-write + + + EDGX1_0 + Disabled + 0 + + + EDGX1_1 + Capture falling edges + 0x1 + + + EDGX1_2 + Capture rising edges + 0x2 + + + EDGX1_3 + Capture any edge + 0x3 + + + + + INP_SELX + Input Select X + 6 + 1 + read-write + + + INP_SELX_0 + Raw PWM_X input signal selected as source. + 0 + + + INP_SELX_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTX_EN + Edge Counter X Enable + 7 + 1 + read-write + + + EDGCNTX_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTX_EN_1 + Edge counter enabled + 0x1 + + + + + CFXWM + Capture X FIFOs Water Mark + 8 + 2 + read-write + + + CX0CNT + Capture X0 FIFO Word Count + 10 + 3 + read-only + + + CX1CNT + Capture X1 FIFO Word Count + 13 + 3 + read-only + + + + + SM2CAPTCOMPX + Capture Compare X Register + 0xFE + 16 + read-write + 0 + 0xFFFF + + + EDGCMPX + Edge Compare X + 0 + 8 + read-write + + + EDGCNTX + Edge Counter X + 8 + 8 + read-only + + + + + SM2CVAL0 + Capture Value 0 Register + 0x100 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL0 + CAPTVAL0 + 0 + 16 + read-only + + + + + SM2CVAL0CYC + Capture Value 0 Cycle Register + 0x102 + 16 + read-only + 0 + 0xFFFF + + + CVAL0CYC + CVAL0CYC + 0 + 4 + read-only + + + + + SM2CVAL1 + Capture Value 1 Register + 0x104 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL1 + CAPTVAL1 + 0 + 16 + read-only + + + + + SM2CVAL1CYC + Capture Value 1 Cycle Register + 0x106 + 16 + read-only + 0 + 0xFFFF + + + CVAL1CYC + CVAL1CYC + 0 + 4 + read-only + + + + + SM2CVAL2 + Capture Value 2 Register + 0x108 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL2 + CAPTVAL2 + 0 + 16 + read-only + + + + + SM2CVAL2CYC + Capture Value 2 Cycle Register + 0x10A + 16 + read-only + 0 + 0xFFFF + + + CVAL2CYC + CVAL2CYC + 0 + 4 + read-only + + + + + SM2CVAL3 + Capture Value 3 Register + 0x10C + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL3 + CAPTVAL3 + 0 + 16 + read-only + + + + + SM2CVAL3CYC + Capture Value 3 Cycle Register + 0x10E + 16 + read-only + 0 + 0xFFFF + + + CVAL3CYC + CVAL3CYC + 0 + 4 + read-only + + + + + SM2CVAL4 + Capture Value 4 Register + 0x110 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL4 + CAPTVAL4 + 0 + 16 + read-only + + + + + SM2CVAL4CYC + Capture Value 4 Cycle Register + 0x112 + 16 + read-only + 0 + 0xFFFF + + + CVAL4CYC + CVAL4CYC + 0 + 4 + read-only + + + + + SM2CVAL5 + Capture Value 5 Register + 0x114 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL5 + CAPTVAL5 + 0 + 16 + read-only + + + + + SM2CVAL5CYC + Capture Value 5 Cycle Register + 0x116 + 16 + read-only + 0 + 0xFFFF + + + CVAL5CYC + CVAL5CYC + 0 + 4 + read-only + + + + + SM3CNT + Counter Register + 0x120 + 16 + read-only + 0 + 0xFFFF + + + CNT + Counter Register Bits + 0 + 16 + read-only + + + + + SM3INIT + Initial Count Register + 0x122 + 16 + read-write + 0 + 0xFFFF + + + INIT + Initial Count Register Bits + 0 + 16 + read-write + + + + + SM3CTRL2 + Control 2 Register + 0x124 + 16 + read-write + 0 + 0xFFFF + + + CLK_SEL + Clock Source Select + 0 + 2 + read-write + + + CLK_SEL_0 + The IPBus clock is used as the clock for the local prescaler and counter. + 0 + + + CLK_SEL_1 + EXT_CLK is used as the clock for the local prescaler and counter. + 0x1 + + + CLK_SEL_2 + Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. + 0x2 + + + + + RELOAD_SEL + Reload Source Select + 2 + 1 + read-write + + + RELOAD_SEL_0 + The local RELOAD signal is used to reload registers. + 0 + + + RELOAD_SEL_1 + The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0. + 0x1 + + + + + FORCE_SEL + This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. + 3 + 3 + read-write + + + FORCE_SEL_0 + The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + 0 + + + FORCE_SEL_1 + The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x1 + + + FORCE_SEL_2 + The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + 0x2 + + + FORCE_SEL_3 + The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x3 + + + FORCE_SEL_4 + The local sync signal from this submodule is used to force updates. + 0x4 + + + FORCE_SEL_5 + The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. + 0x5 + + + FORCE_SEL_6 + The external force signal, EXT_FORCE, from outside the PWM module causes updates. + 0x6 + + + FORCE_SEL_7 + The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + 0x7 + + + + + FORCE + Force Initialization + 6 + 1 + read-write + + + FRCEN + FRCEN + 7 + 1 + read-write + + + FRCEN_0 + Initialization from a FORCE_OUT is disabled. + 0 + + + FRCEN_1 + Initialization from a FORCE_OUT is enabled. + 0x1 + + + + + INIT_SEL + Initialization Control Select + 8 + 2 + read-write + + + INIT_SEL_0 + Local sync (PWM_X) causes initialization. + 0 + + + INIT_SEL_1 + Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. + 0x1 + + + INIT_SEL_2 + Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. + 0x2 + + + INIT_SEL_3 + EXT_SYNC causes initialization. + 0x3 + + + + + PWMX_INIT + PWM_X Initial Value + 10 + 1 + read-write + + + PWM45_INIT + PWM45 Initial Value + 11 + 1 + read-write + + + PWM23_INIT + PWM23 Initial Value + 12 + 1 + read-write + + + INDEP + Independent or Complementary Pair Operation + 13 + 1 + read-write + + + INDEP_0 + PWM_A and PWM_B form a complementary PWM pair. + 0 + + + INDEP_1 + PWM_A and PWM_B outputs are independent PWMs. + 0x1 + + + + + WAITEN + WAIT Enable + 14 + 1 + read-write + + + DBGEN + Debug Enable + 15 + 1 + read-write + + + + + SM3CTRL + Control Register + 0x126 + 16 + read-write + 0x400 + 0xFFFF + + + DBLEN + Double Switching Enable + 0 + 1 + read-write + + + DBLEN_0 + Double switching disabled. + 0 + + + DBLEN_1 + Double switching enabled. + 0x1 + + + + + DBLX + PWMX Double Switching Enable + 1 + 1 + read-write + + + DBLX_0 + PWMX double pulse disabled. + 0 + + + DBLX_1 + PWMX double pulse enabled. + 0x1 + + + + + LDMOD + Load Mode Select + 2 + 1 + read-write + + + LDMOD_0 + Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + 0 + + + LDMOD_1 + Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. + 0x1 + + + + + SPLIT + Split the DBLPWM signal to PWMA and PWMB + 3 + 1 + read-write + + + SPLIT_0 + DBLPWM is not split. PWMA and PWMB each have double pulses. + 0 + + + SPLIT_1 + DBLPWM is split to PWMA and PWMB. + 0x1 + + + + + PRSC + Prescaler + 4 + 3 + read-write + + + PRSC_0 + PWM clock frequency = fclk + 0 + + + PRSC_1 + PWM clock frequency = fclk/2 + 0x1 + + + PRSC_2 + PWM clock frequency = fclk/4 + 0x2 + + + PRSC_3 + PWM clock frequency = fclk/8 + 0x3 + + + PRSC_4 + PWM clock frequency = fclk/16 + 0x4 + + + PRSC_5 + PWM clock frequency = fclk/32 + 0x5 + + + PRSC_6 + PWM clock frequency = fclk/64 + 0x6 + + + PRSC_7 + PWM clock frequency = fclk/128 + 0x7 + + + + + COMPMODE + Compare Mode + 7 + 1 + read-write + + + COMPMODE_0 + The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. + 0 + + + COMPMODE_1 + The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + 0x1 + + + + + DT + Deadtime + 8 + 2 + read-only + + + FULL + Full Cycle Reload + 10 + 1 + read-write + + + FULL_0 + Full-cycle reloads disabled. + 0 + + + FULL_1 + Full-cycle reloads enabled. + 0x1 + + + + + HALF + Half Cycle Reload + 11 + 1 + read-write + + + HALF_0 + Half-cycle reloads disabled. + 0 + + + HALF_1 + Half-cycle reloads enabled. + 0x1 + + + + + LDFQ + Load Frequency + 12 + 4 + read-write + + + LDFQ_0 + Every PWM opportunity + 0 + + + LDFQ_1 + Every 2 PWM opportunities + 0x1 + + + LDFQ_2 + Every 3 PWM opportunities + 0x2 + + + LDFQ_3 + Every 4 PWM opportunities + 0x3 + + + LDFQ_4 + Every 5 PWM opportunities + 0x4 + + + LDFQ_5 + Every 6 PWM opportunities + 0x5 + + + LDFQ_6 + Every 7 PWM opportunities + 0x6 + + + LDFQ_7 + Every 8 PWM opportunities + 0x7 + + + LDFQ_8 + Every 9 PWM opportunities + 0x8 + + + LDFQ_9 + Every 10 PWM opportunities + 0x9 + + + LDFQ_10 + Every 11 PWM opportunities + 0xA + + + LDFQ_11 + Every 12 PWM opportunities + 0xB + + + LDFQ_12 + Every 13 PWM opportunities + 0xC + + + LDFQ_13 + Every 14 PWM opportunities + 0xD + + + LDFQ_14 + Every 15 PWM opportunities + 0xE + + + LDFQ_15 + Every 16 PWM opportunities + 0xF + + + + + + + SM3VAL0 + Value Register 0 + 0x12A + 16 + read-write + 0 + 0xFFFF + + + VAL0 + Value Register 0 + 0 + 16 + read-write + + + + + SM3FRACVAL1 + Fractional Value Register 1 + 0x12C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL1 + Fractional Value 1 Register + 11 + 5 + read-write + + + + + SM3VAL1 + Value Register 1 + 0x12E + 16 + read-write + 0 + 0xFFFF + + + VAL1 + Value Register 1 + 0 + 16 + read-write + + + + + SM3FRACVAL2 + Fractional Value Register 2 + 0x130 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL2 + Fractional Value 2 + 11 + 5 + read-write + + + + + SM3VAL2 + Value Register 2 + 0x132 + 16 + read-write + 0 + 0xFFFF + + + VAL2 + Value Register 2 + 0 + 16 + read-write + + + + + SM3FRACVAL3 + Fractional Value Register 3 + 0x134 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL3 + Fractional Value 3 + 11 + 5 + read-write + + + + + SM3VAL3 + Value Register 3 + 0x136 + 16 + read-write + 0 + 0xFFFF + + + VAL3 + Value Register 3 + 0 + 16 + read-write + + + + + SM3FRACVAL4 + Fractional Value Register 4 + 0x138 + 16 + read-write + 0 + 0xFFFF + + + FRACVAL4 + Fractional Value 4 + 11 + 5 + read-write + + + + + SM3VAL4 + Value Register 4 + 0x13A + 16 + read-write + 0 + 0xFFFF + + + VAL4 + Value Register 4 + 0 + 16 + read-write + + + + + SM3FRACVAL5 + Fractional Value Register 5 + 0x13C + 16 + read-write + 0 + 0xFFFF + + + FRACVAL5 + Fractional Value 5 + 11 + 5 + read-write + + + + + SM3VAL5 + Value Register 5 + 0x13E + 16 + read-write + 0 + 0xFFFF + + + VAL5 + Value Register 5 + 0 + 16 + read-write + + + + + SM3FRCTRL + Fractional Control Register + 0x140 + 16 + read-write + 0 + 0xFFFF + + + FRAC1_EN + Fractional Cycle PWM Period Enable + 1 + 1 + read-write + + + FRAC1_EN_0 + Disable fractional cycle length for the PWM period. + 0 + + + FRAC1_EN_1 + Enable fractional cycle length for the PWM period. + 0x1 + + + + + FRAC23_EN + Fractional Cycle Placement Enable for PWM_A + 2 + 1 + read-write + + + FRAC23_EN_0 + Disable fractional cycle placement for PWM_A. + 0 + + + FRAC23_EN_1 + Enable fractional cycle placement for PWM_A. + 0x1 + + + + + FRAC45_EN + Fractional Cycle Placement Enable for PWM_B + 4 + 1 + read-write + + + FRAC45_EN_0 + Disable fractional cycle placement for PWM_B. + 0 + + + FRAC45_EN_1 + Enable fractional cycle placement for PWM_B. + 0x1 + + + + + FRAC_PU + Fractional Delay Circuit Power Up + 8 + 1 + read-write + + + FRAC_PU_0 + Turn off fractional delay logic. + 0 + + + FRAC_PU_1 + Power up fractional delay logic. + 0x1 + + + + + TEST + Test Status Bit + 15 + 1 + read-only + + + + + SM3OCTRL + Output Control Register + 0x142 + 16 + read-write + 0 + 0xFFFF + + + PWMXFS + PWM_X Fault State + 0 + 2 + read-write + + + PWMXFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMXFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMXFS_2 + Output is tristated. + 0x2 + + + PWMXFS_3 + Output is tristated. + 0x3 + + + + + PWMBFS + PWM_B Fault State + 2 + 2 + read-write + + + PWMBFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMBFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMBFS_2 + Output is tristated. + 0x2 + + + PWMBFS_3 + Output is tristated. + 0x3 + + + + + PWMAFS + PWM_A Fault State + 4 + 2 + read-write + + + PWMAFS_0 + Output is forced to logic 0 state prior to consideration of output polarity control. + 0 + + + PWMAFS_1 + Output is forced to logic 1 state prior to consideration of output polarity control. + 0x1 + + + PWMAFS_2 + Output is tristated. + 0x2 + + + PWMAFS_3 + Output is tristated. + 0x3 + + + + + POLX + PWM_X Output Polarity + 8 + 1 + read-write + + + POLX_0 + PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + 0 + + + POLX_1 + PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + 0x1 + + + + + POLB + PWM_B Output Polarity + 9 + 1 + read-write + + + POLB_0 + PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + 0 + + + POLB_1 + PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + 0x1 + + + + + POLA + PWM_A Output Polarity + 10 + 1 + read-write + + + POLA_0 + PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + 0 + + + POLA_1 + PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + 0x1 + + + + + PWMX_IN + PWM_X Input + 13 + 1 + read-only + + + PWMB_IN + PWM_B Input + 14 + 1 + read-only + + + PWMA_IN + PWM_A Input + 15 + 1 + read-only + + + + + SM3STS + Status Register + 0x144 + 16 + read-write + 0 + 0xFFFF + + + CMPF + Compare Flags + 0 + 6 + read-write + oneToClear + + + CMPF_0 + No compare event has occurred for a particular VALx value. + 0 + + + CMPF_1 + A compare event has occurred for a particular VALx value. + 0x1 + + + + + CFX0 + Capture Flag X0 + 6 + 1 + read-write + oneToClear + + + CFX1 + Capture Flag X1 + 7 + 1 + read-write + oneToClear + + + CFB0 + Capture Flag B0 + 8 + 1 + read-write + oneToClear + + + CFB1 + Capture Flag B1 + 9 + 1 + read-write + oneToClear + + + CFA0 + Capture Flag A0 + 10 + 1 + read-write + oneToClear + + + CFA1 + Capture Flag A1 + 11 + 1 + read-write + oneToClear + + + RF + Reload Flag + 12 + 1 + read-write + oneToClear + + + RF_0 + No new reload cycle since last STS[RF] clearing + 0 + + + RF_1 + New reload cycle since last STS[RF] clearing + 0x1 + + + + + REF + Reload Error Flag + 13 + 1 + read-write + oneToClear + + + REF_0 + No reload error occurred. + 0 + + + REF_1 + Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + 0x1 + + + + + RUF + Registers Updated Flag + 14 + 1 + read-only + + + RUF_0 + No register update has occurred since last reload. + 0 + + + RUF_1 + At least one of the double buffered registers has been updated since the last reload. + 0x1 + + + + + + + SM3INTEN + Interrupt Enable Register + 0x146 + 16 + read-write + 0 + 0xFFFF + + + CMPIE + Compare Interrupt Enables + 0 + 6 + read-write + + + CMPIE_0 + The corresponding STS[CMPF] bit will not cause an interrupt request. + 0 + + + CMPIE_1 + The corresponding STS[CMPF] bit will cause an interrupt request. + 0x1 + + + + + CX0IE + Capture X 0 Interrupt Enable + 6 + 1 + read-write + + + CX0IE_0 + Interrupt request disabled for STS[CFX0]. + 0 + + + CX0IE_1 + Interrupt request enabled for STS[CFX0]. + 0x1 + + + + + CX1IE + Capture X 1 Interrupt Enable + 7 + 1 + read-write + + + CX1IE_0 + Interrupt request disabled for STS[CFX1]. + 0 + + + CX1IE_1 + Interrupt request enabled for STS[CFX1]. + 0x1 + + + + + CB0IE + Capture B 0 Interrupt Enable + 8 + 1 + read-write + + + CB0IE_0 + Interrupt request disabled for STS[CFB0]. + 0 + + + CB0IE_1 + Interrupt request enabled for STS[CFB0]. + 0x1 + + + + + CB1IE + Capture B 1 Interrupt Enable + 9 + 1 + read-write + + + CB1IE_0 + Interrupt request disabled for STS[CFB1]. + 0 + + + CB1IE_1 + Interrupt request enabled for STS[CFB1]. + 0x1 + + + + + CA0IE + Capture A 0 Interrupt Enable + 10 + 1 + read-write + + + CA0IE_0 + Interrupt request disabled for STS[CFA0]. + 0 + + + CA0IE_1 + Interrupt request enabled for STS[CFA0]. + 0x1 + + + + + CA1IE + Capture A 1 Interrupt Enable + 11 + 1 + read-write + + + CA1IE_0 + Interrupt request disabled for STS[CFA1]. + 0 + + + CA1IE_1 + Interrupt request enabled for STS[CFA1]. + 0x1 + + + + + RIE + Reload Interrupt Enable + 12 + 1 + read-write + + + RIE_0 + STS[RF] CPU interrupt requests disabled + 0 + + + RIE_1 + STS[RF] CPU interrupt requests enabled + 0x1 + + + + + REIE + Reload Error Interrupt Enable + 13 + 1 + read-write + + + REIE_0 + STS[REF] CPU interrupt requests disabled + 0 + + + REIE_1 + STS[REF] CPU interrupt requests enabled + 0x1 + + + + + + + SM3DMAEN + DMA Enable Register + 0x148 + 16 + read-write + 0 + 0xFFFF + + + CX0DE + Capture X0 FIFO DMA Enable + 0 + 1 + read-write + + + CX1DE + Capture X1 FIFO DMA Enable + 1 + 1 + read-write + + + CB0DE + Capture B0 FIFO DMA Enable + 2 + 1 + read-write + + + CB1DE + Capture B1 FIFO DMA Enable + 3 + 1 + read-write + + + CA0DE + Capture A0 FIFO DMA Enable + 4 + 1 + read-write + + + CA1DE + Capture A1 FIFO DMA Enable + 5 + 1 + read-write + + + CAPTDE + Capture DMA Enable Source Select + 6 + 2 + read-write + + + CAPTDE_0 + Read DMA requests disabled. + 0 + + + CAPTDE_1 + Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. + 0x1 + + + CAPTDE_2 + A local sync (VAL1 matches counter) sets the read DMA request. + 0x2 + + + CAPTDE_3 + A local reload (STS[RF] being set) sets the read DMA request. + 0x3 + + + + + FAND + FIFO Watermark AND Control + 8 + 1 + read-write + + + FAND_0 + Selected FIFO watermarks are OR'ed together. + 0 + + + FAND_1 + Selected FIFO watermarks are AND'ed together. + 0x1 + + + + + VALDE + Value Registers DMA Enable + 9 + 1 + read-write + + + VALDE_0 + DMA write requests disabled + 0 + + + VALDE_1 + DMA write requests for the VALx and FRACVALx registers enabled + 0x1 + + + + + + + SM3TCTRL + Output Trigger Control Register + 0x14A + 16 + read-write + 0 + 0xFFFF + + + OUT_TRIG_EN + Output Trigger Enables + 0 + 6 + read-write + + + OUT_TRIG_EN_0 + PWM_OUT_TRIGx will not set when the counter value matches the VALx value. + 0 + + + OUT_TRIG_EN_1 + PWM_OUT_TRIGx will set when the counter value matches the VALx value. + 0x1 + + + + + TRGFRQ + Trigger frequency + 12 + 1 + read-write + + + TRGFRQ_0 + Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0 + + + TRGFRQ_1 + Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + 0x1 + + + + + PWBOT1 + Output Trigger 1 Source Select + 14 + 1 + read-write + + + PWBOT1_0 + Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + 0 + + + PWBOT1_1 + Route the PWMB output to the PWM_OUT_TRIG1 port. + 0x1 + + + + + PWAOT0 + Output Trigger 0 Source Select + 15 + 1 + read-write + + + PWAOT0_0 + Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + 0 + + + PWAOT0_1 + Route the PWMA output to the PWM_OUT_TRIG0 port. + 0x1 + + + + + + + SM3DISMAP0 + Fault Disable Mapping Register 0 + 0x14C + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS0A + PWM_A Fault Disable Mask 0 + 0 + 4 + read-write + + + DIS0B + PWM_B Fault Disable Mask 0 + 4 + 4 + read-write + + + DIS0X + PWM_X Fault Disable Mask 0 + 8 + 4 + read-write + + + + + SM3DISMAP1 + Fault Disable Mapping Register 1 + 0x14E + 16 + read-write + 0xFFFF + 0xFFFF + + + DIS1A + PWM_A Fault Disable Mask 1 + 0 + 4 + read-write + + + DIS1B + PWM_B Fault Disable Mask 1 + 4 + 4 + read-write + + + DIS1X + PWM_X Fault Disable Mask 1 + 8 + 4 + read-write + + + + + SM3DTCNT0 + Deadtime Count Register 0 + 0x150 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT0 + DTCNT0 + 0 + 16 + read-write + + + + + SM3DTCNT1 + Deadtime Count Register 1 + 0x152 + 16 + read-write + 0x7FF + 0xFFFF + + + DTCNT1 + DTCNT1 + 0 + 16 + read-write + + + + + SM3CAPTCTRLA + Capture Control A Register + 0x154 + 16 + read-write + 0 + 0xFFFF + + + ARMA + Arm A + 0 + 1 + read-write + + + ARMA_0 + Input capture operation is disabled. + 0 + + + ARMA_1 + Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. + 0x1 + + + + + ONESHOTA + One Shot Mode A + 1 + 1 + read-write + + + ONESHOTA_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTA_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared. + 0x1 + + + + + EDGA0 + Edge A 0 + 2 + 2 + read-write + + + EDGA0_0 + Disabled + 0 + + + EDGA0_1 + Capture falling edges + 0x1 + + + EDGA0_2 + Capture rising edges + 0x2 + + + EDGA0_3 + Capture any edge + 0x3 + + + + + EDGA1 + Edge A 1 + 4 + 2 + read-write + + + EDGA1_0 + Disabled + 0 + + + EDGA1_1 + Capture falling edges + 0x1 + + + EDGA1_2 + Capture rising edges + 0x2 + + + EDGA1_3 + Capture any edge + 0x3 + + + + + INP_SELA + Input Select A + 6 + 1 + read-write + + + INP_SELA_0 + Raw PWM_A input signal selected as source. + 0 + + + INP_SELA_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTA_EN + Edge Counter A Enable + 7 + 1 + read-write + + + EDGCNTA_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTA_EN_1 + Edge counter enabled + 0x1 + + + + + CFAWM + Capture A FIFOs Water Mark + 8 + 2 + read-write + + + CA0CNT + Capture A0 FIFO Word Count + 10 + 3 + read-only + + + CA1CNT + Capture A1 FIFO Word Count + 13 + 3 + read-only + + + + + SM3CAPTCOMPA + Capture Compare A Register + 0x156 + 16 + read-write + 0 + 0xFFFF + + + EDGCMPA + Edge Compare A + 0 + 8 + read-write + + + EDGCNTA + Edge Counter A + 8 + 8 + read-only + + + + + SM3CAPTCTRLB + Capture Control B Register + 0x158 + 16 + read-write + 0 + 0xFFFF + + + ARMB + Arm B + 0 + 1 + read-write + + + ARMB_0 + Input capture operation is disabled. + 0 + + + ARMB_1 + Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. + 0x1 + + + + + ONESHOTB + One Shot Mode B + 1 + 1 + read-write + + + ONESHOTB_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTB_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared. + 0x1 + + + + + EDGB0 + Edge B 0 + 2 + 2 + read-write + + + EDGB0_0 + Disabled + 0 + + + EDGB0_1 + Capture falling edges + 0x1 + + + EDGB0_2 + Capture rising edges + 0x2 + + + EDGB0_3 + Capture any edge + 0x3 + + + + + EDGB1 + Edge B 1 + 4 + 2 + read-write + + + EDGB1_0 + Disabled + 0 + + + EDGB1_1 + Capture falling edges + 0x1 + + + EDGB1_2 + Capture rising edges + 0x2 + + + EDGB1_3 + Capture any edge + 0x3 + + + + + INP_SELB + Input Select B + 6 + 1 + read-write + + + INP_SELB_0 + Raw PWM_B input signal selected as source. + 0 + + + INP_SELB_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTB_EN + Edge Counter B Enable + 7 + 1 + read-write + + + EDGCNTB_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTB_EN_1 + Edge counter enabled + 0x1 + + + + + CFBWM + Capture B FIFOs Water Mark + 8 + 2 + read-write + + + CB0CNT + Capture B0 FIFO Word Count + 10 + 3 + read-only + + + CB1CNT + Capture B1 FIFO Word Count + 13 + 3 + read-only + + + + + SM3CAPTCOMPB + Capture Compare B Register + 0x15A + 16 + read-write + 0 + 0xFFFF + + + EDGCMPB + Edge Compare B + 0 + 8 + read-write + + + EDGCNTB + Edge Counter B + 8 + 8 + read-only + + + + + SM3CAPTCTRLX + Capture Control X Register + 0x15C + 16 + read-write + 0 + 0xFFFF + + + ARMX + Arm X + 0 + 1 + read-write + + + ARMX_0 + Input capture operation is disabled. + 0 + + + ARMX_1 + Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + 0x1 + + + + + ONESHOTX + One Shot Mode Aux + 1 + 1 + read-write + + + ONESHOTX_0 + Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. + 0 + + + ONESHOTX_1 + One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared. + 0x1 + + + + + EDGX0 + Edge X 0 + 2 + 2 + read-write + + + EDGX0_0 + Disabled + 0 + + + EDGX0_1 + Capture falling edges + 0x1 + + + EDGX0_2 + Capture rising edges + 0x2 + + + EDGX0_3 + Capture any edge + 0x3 + + + + + EDGX1 + Edge X 1 + 4 + 2 + read-write + + + EDGX1_0 + Disabled + 0 + + + EDGX1_1 + Capture falling edges + 0x1 + + + EDGX1_2 + Capture rising edges + 0x2 + + + EDGX1_3 + Capture any edge + 0x3 + + + + + INP_SELX + Input Select X + 6 + 1 + read-write + + + INP_SELX_0 + Raw PWM_X input signal selected as source. + 0 + + + INP_SELX_1 + Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers. + 0x1 + + + + + EDGCNTX_EN + Edge Counter X Enable + 7 + 1 + read-write + + + EDGCNTX_EN_0 + Edge counter disabled and held in reset + 0 + + + EDGCNTX_EN_1 + Edge counter enabled + 0x1 + + + + + CFXWM + Capture X FIFOs Water Mark + 8 + 2 + read-write + + + CX0CNT + Capture X0 FIFO Word Count + 10 + 3 + read-only + + + CX1CNT + Capture X1 FIFO Word Count + 13 + 3 + read-only + + + + + SM3CAPTCOMPX + Capture Compare X Register + 0x15E + 16 + read-write + 0 + 0xFFFF + + + EDGCMPX + Edge Compare X + 0 + 8 + read-write + + + EDGCNTX + Edge Counter X + 8 + 8 + read-only + + + + + SM3CVAL0 + Capture Value 0 Register + 0x160 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL0 + CAPTVAL0 + 0 + 16 + read-only + + + + + SM3CVAL0CYC + Capture Value 0 Cycle Register + 0x162 + 16 + read-only + 0 + 0xFFFF + + + CVAL0CYC + CVAL0CYC + 0 + 4 + read-only + + + + + SM3CVAL1 + Capture Value 1 Register + 0x164 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL1 + CAPTVAL1 + 0 + 16 + read-only + + + + + SM3CVAL1CYC + Capture Value 1 Cycle Register + 0x166 + 16 + read-only + 0 + 0xFFFF + + + CVAL1CYC + CVAL1CYC + 0 + 4 + read-only + + + + + SM3CVAL2 + Capture Value 2 Register + 0x168 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL2 + CAPTVAL2 + 0 + 16 + read-only + + + + + SM3CVAL2CYC + Capture Value 2 Cycle Register + 0x16A + 16 + read-only + 0 + 0xFFFF + + + CVAL2CYC + CVAL2CYC + 0 + 4 + read-only + + + + + SM3CVAL3 + Capture Value 3 Register + 0x16C + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL3 + CAPTVAL3 + 0 + 16 + read-only + + + + + SM3CVAL3CYC + Capture Value 3 Cycle Register + 0x16E + 16 + read-only + 0 + 0xFFFF + + + CVAL3CYC + CVAL3CYC + 0 + 4 + read-only + + + + + SM3CVAL4 + Capture Value 4 Register + 0x170 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL4 + CAPTVAL4 + 0 + 16 + read-only + + + + + SM3CVAL4CYC + Capture Value 4 Cycle Register + 0x172 + 16 + read-only + 0 + 0xFFFF + + + CVAL4CYC + CVAL4CYC + 0 + 4 + read-only + + + + + SM3CVAL5 + Capture Value 5 Register + 0x174 + 16 + read-only + 0 + 0xFFFF + + + CAPTVAL5 + CAPTVAL5 + 0 + 16 + read-only + + + + + SM3CVAL5CYC + Capture Value 5 Cycle Register + 0x176 + 16 + read-only + 0 + 0xFFFF + + + CVAL5CYC + CVAL5CYC + 0 + 4 + read-only + + + + + OUTEN + Output Enable Register + 0x180 + 16 + read-write + 0 + 0xFFFF + + + PWMX_EN + PWM_X Output Enables + 0 + 4 + read-write + + + PWMX_EN_0 + PWM_X output disabled. + 0 + + + PWMX_EN_1 + PWM_X output enabled. + 0x1 + + + + + PWMB_EN + PWM_B Output Enables + 4 + 4 + read-write + + + PWMB_EN_0 + PWM_B output disabled. + 0 + + + PWMB_EN_1 + PWM_B output enabled. + 0x1 + + + + + PWMA_EN + PWM_A Output Enables + 8 + 4 + read-write + + + PWMA_EN_0 + PWM_A output disabled. + 0 + + + PWMA_EN_1 + PWM_A output enabled. + 0x1 + + + + + + + MASK + Mask Register + 0x182 + 16 + read-write + 0 + 0xFFFF + + + MASKX + PWM_X Masks + 0 + 4 + read-write + + + MASKX_0 + PWM_X output normal. + 0 + + + MASKX_1 + PWM_X output masked. + 0x1 + + + + + MASKB + PWM_B Masks + 4 + 4 + read-write + + + MASKB_0 + PWM_B output normal. + 0 + + + MASKB_1 + PWM_B output masked. + 0x1 + + + + + MASKA + PWM_A Masks + 8 + 4 + read-write + + + MASKA_0 + PWM_A output normal. + 0 + + + MASKA_1 + PWM_A output masked. + 0x1 + + + + + UPDATE_MASK + Update Mask Bits Immediately + 12 + 4 + write-only + + + UPDATE_MASK_0 + Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule. + 0 + + + UPDATE_MASK_1 + Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit. + 0x1 + + + + + + + SWCOUT + Software Controlled Output Register + 0x184 + 16 + read-write + 0 + 0xFFFF + + + SM0OUT45 + Submodule 0 Software Controlled Output 45 + 0 + 1 + read-write + + + SM0OUT45_0 + A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. + 0 + + + SM0OUT45_1 + A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. + 0x1 + + + + + SM0OUT23 + Submodule 0 Software Controlled Output 23 + 1 + 1 + read-write + + + SM0OUT23_0 + A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. + 0 + + + SM0OUT23_1 + A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. + 0x1 + + + + + SM1OUT45 + Submodule 1 Software Controlled Output 45 + 2 + 1 + read-write + + + SM1OUT45_0 + A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. + 0 + + + SM1OUT45_1 + A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. + 0x1 + + + + + SM1OUT23 + Submodule 1 Software Controlled Output 23 + 3 + 1 + read-write + + + SM1OUT23_0 + A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. + 0 + + + SM1OUT23_1 + A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. + 0x1 + + + + + SM2OUT45 + Submodule 2 Software Controlled Output 45 + 4 + 1 + read-write + + + SM2OUT45_0 + A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. + 0 + + + SM2OUT45_1 + A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. + 0x1 + + + + + SM2OUT23 + Submodule 2 Software Controlled Output 23 + 5 + 1 + read-write + + + SM2OUT23_0 + A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. + 0 + + + SM2OUT23_1 + A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. + 0x1 + + + + + SM3OUT45 + Submodule 3 Software Controlled Output 45 + 6 + 1 + read-write + + + SM3OUT45_0 + A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. + 0 + + + SM3OUT45_1 + A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. + 0x1 + + + + + SM3OUT23 + Submodule 3 Software Controlled Output 23 + 7 + 1 + read-write + + + SM3OUT23_0 + A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. + 0 + + + SM3OUT23_1 + A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23. + 0x1 + + + + + + + DTSRCSEL + PWM Source Select Register + 0x186 + 16 + read-write + 0 + 0xFFFF + + + SM0SEL45 + Submodule 0 PWM45 Control Select + 0 + 2 + read-write + + + SM0SEL45_0 + Generated SM0PWM45 signal is used by the deadtime logic. + 0 + + + SM0SEL45_1 + Inverted generated SM0PWM45 signal is used by the deadtime logic. + 0x1 + + + SM0SEL45_2 + SWCOUT[SM0OUT45] is used by the deadtime logic. + 0x2 + + + SM0SEL45_3 + PWM0_EXTB signal is used by the deadtime logic. + 0x3 + + + + + SM0SEL23 + Submodule 0 PWM23 Control Select + 2 + 2 + read-write + + + SM0SEL23_0 + Generated SM0PWM23 signal is used by the deadtime logic. + 0 + + + SM0SEL23_1 + Inverted generated SM0PWM23 signal is used by the deadtime logic. + 0x1 + + + SM0SEL23_2 + SWCOUT[SM0OUT23] is used by the deadtime logic. + 0x2 + + + SM0SEL23_3 + PWM0_EXTA signal is used by the deadtime logic. + 0x3 + + + + + SM1SEL45 + Submodule 1 PWM45 Control Select + 4 + 2 + read-write + + + SM1SEL45_0 + Generated SM1PWM45 signal is used by the deadtime logic. + 0 + + + SM1SEL45_1 + Inverted generated SM1PWM45 signal is used by the deadtime logic. + 0x1 + + + SM1SEL45_2 + SWCOUT[SM1OUT45] is used by the deadtime logic. + 0x2 + + + SM1SEL45_3 + PWM1_EXTB signal is used by the deadtime logic. + 0x3 + + + + + SM1SEL23 + Submodule 1 PWM23 Control Select + 6 + 2 + read-write + + + SM1SEL23_0 + Generated SM1PWM23 signal is used by the deadtime logic. + 0 + + + SM1SEL23_1 + Inverted generated SM1PWM23 signal is used by the deadtime logic. + 0x1 + + + SM1SEL23_2 + SWCOUT[SM1OUT23] is used by the deadtime logic. + 0x2 + + + SM1SEL23_3 + PWM1_EXTA signal is used by the deadtime logic. + 0x3 + + + + + SM2SEL45 + Submodule 2 PWM45 Control Select + 8 + 2 + read-write + + + SM2SEL45_0 + Generated SM2PWM45 signal is used by the deadtime logic. + 0 + + + SM2SEL45_1 + Inverted generated SM2PWM45 signal is used by the deadtime logic. + 0x1 + + + SM2SEL45_2 + SWCOUT[SM2OUT45] is used by the deadtime logic. + 0x2 + + + SM2SEL45_3 + PWM2_EXTB signal is used by the deadtime logic. + 0x3 + + + + + SM2SEL23 + Submodule 2 PWM23 Control Select + 10 + 2 + read-write + + + SM2SEL23_0 + Generated SM2PWM23 signal is used by the deadtime logic. + 0 + + + SM2SEL23_1 + Inverted generated SM2PWM23 signal is used by the deadtime logic. + 0x1 + + + SM2SEL23_2 + SWCOUT[SM2OUT23] is used by the deadtime logic. + 0x2 + + + SM2SEL23_3 + PWM2_EXTA signal is used by the deadtime logic. + 0x3 + + + + + SM3SEL45 + Submodule 3 PWM45 Control Select + 12 + 2 + read-write + + + SM3SEL45_0 + Generated SM3PWM45 signal is used by the deadtime logic. + 0 + + + SM3SEL45_1 + Inverted generated SM3PWM45 signal is used by the deadtime logic. + 0x1 + + + SM3SEL45_2 + SWCOUT[SM3OUT45] is used by the deadtime logic. + 0x2 + + + SM3SEL45_3 + PWM3_EXTB signal is used by the deadtime logic. + 0x3 + + + + + SM3SEL23 + Submodule 3 PWM23 Control Select + 14 + 2 + read-write + + + SM3SEL23_0 + Generated SM3PWM23 signal is used by the deadtime logic. + 0 + + + SM3SEL23_1 + Inverted generated SM3PWM23 signal is used by the deadtime logic. + 0x1 + + + SM3SEL23_2 + SWCOUT[SM3OUT23] is used by the deadtime logic. + 0x2 + + + SM3SEL23_3 + PWM3_EXTA signal is used by the deadtime logic. + 0x3 + + + + + + + MCTRL + Master Control Register + 0x188 + 16 + read-write + 0 + 0xFFFF + + + LDOK + Load Okay + 0 + 4 + read-write + + + LDOK_0 + Do not load new values. + 0 + + + LDOK_1 + Load prescaler, modulus, and PWM values of the corresponding submodule. + 0x1 + + + + + CLDOK + Clear Load Okay + 4 + 4 + read-write + + + RUN + Run + 8 + 4 + read-write + + + RUN_0 + PWM generator is disabled in the corresponding submodule. + 0 + + + RUN_1 + PWM generator is enabled in the corresponding submodule. + 0x1 + + + + + IPOL + Current Polarity + 12 + 4 + read-write + + + IPOL_0 + PWM23 is used to generate complementary PWM pair in the corresponding submodule. + 0 + + + IPOL_1 + PWM45 is used to generate complementary PWM pair in the corresponding submodule. + 0x1 + + + + + + + MCTRL2 + Master Control 2 Register + 0x18A + 16 + read-write + 0 + 0xFFFF + + + MONPLL + Monitor PLL State + 0 + 2 + read-write + + + MONPLL_0 + Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. + 0 + + + MONPLL_1 + Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. + 0x1 + + + MONPLL_2 + Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. These bits are write protected until the next reset. + 0x2 + + + MONPLL_3 + Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. These bits are write protected until the next reset. + 0x3 + + + + + + + FCTRL0 + Fault Control Register + 0x18C + 16 + read-write + 0 + 0xFFFF + + + FIE + Fault Interrupt Enables + 0 + 4 + read-write + + + FIE_0 + FAULTx CPU interrupt requests disabled. + 0 + + + FIE_1 + FAULTx CPU interrupt requests enabled. + 0x1 + + + + + FSAFE + Fault Safety Mode + 4 + 4 + read-write + + + FSAFE_0 + Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFPINx]. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn). + 0 + + + FSAFE_1 + Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL]. + 0x1 + + + + + FAUTO + Automatic Fault Clearing + 8 + 4 + read-write + + + FAUTO_0 + Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending the state of FSTS[FFULL]. This is further controlled by FCTRL[FSAFE]. + 0 + + + FAUTO_1 + Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFLAGx]. + 0x1 + + + + + FLVL + Fault Level + 12 + 4 + read-write + + + FLVL_0 + A logic 0 on the fault input indicates a fault condition. + 0 + + + FLVL_1 + A logic 1 on the fault input indicates a fault condition. + 0x1 + + + + + + + FSTS0 + Fault Status Register + 0x18E + 16 + read-write + 0 + 0xFFFF + + + FFLAG + Fault Flags + 0 + 4 + read-write + + + FFLAG_0 + No fault on the FAULTx pin. + 0 + + + FFLAG_1 + Fault on the FAULTx pin. + 0x1 + + + + + FFULL + Full Cycle + 4 + 4 + read-write + + + FFULL_0 + PWM outputs are not re-enabled at the start of a full cycle + 0 + + + FFULL_1 + PWM outputs are re-enabled at the start of a full cycle + 0x1 + + + + + FFPIN + Filtered Fault Pins + 8 + 4 + read-only + + + FHALF + Half Cycle Fault Recovery + 12 + 4 + read-write + + + FHALF_0 + PWM outputs are not re-enabled at the start of a half cycle. + 0 + + + FHALF_1 + PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). + 0x1 + + + + + + + FFILT0 + Fault Filter Register + 0x190 + 16 + read-write + 0 + 0xFFFF + + + FILT_PER + Fault Filter Period + 0 + 8 + read-write + + + FILT_CNT + Fault Filter Count + 8 + 3 + read-write + + + GSTR + Fault Glitch Stretch Enable + 15 + 1 + read-write + + + GSTR_0 + Fault input glitch stretching is disabled. + 0 + + + GSTR_1 + Input fault signals will be stretched to at least 2 IPBus clock cycles. + 0x1 + + + + + + + FTST0 + Fault Test Register + 0x192 + 16 + read-write + 0 + 0xFFFF + + + FTEST + Fault Test + 0 + 1 + read-write + + + FTEST_0 + No fault + 0 + + + FTEST_1 + Cause a simulated fault + 0x1 + + + + + + + FCTRL20 + Fault Control 2 Register + 0x194 + 16 + read-write + 0 + 0xFFFF + + + NOCOMB + No Combinational Path From Fault Input To PWM Output + 0 + 4 + read-write + + + NOCOMB_0 + There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs. + 0 + + + NOCOMB_1 + The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs. + 0x1 + + + + + + + + + PWM2 + PWM + PWM + 0x403E0000 + + 0 + 0x196 + registers + + + PWM2_0 + 137 + + + PWM2_1 + 138 + + + PWM2_2 + 139 + + + PWM2_3 + 140 + + + PWM2_FAULT + 141 + + + + PWM3 + PWM + PWM + 0x403E4000 + + 0 + 0x196 + registers + + + PWM3_0 + 142 + + + PWM3_1 + 143 + + + PWM3_2 + 144 + + + PWM3_3 + 145 + + + PWM3_FAULT + 146 + + + + PWM4 + PWM + PWM + 0x403E8000 + + 0 + 0x196 + registers + + + PWM4_0 + 147 + + + PWM4_1 + 148 + + + PWM4_2 + 149 + + + PWM4_3 + 150 + + + PWM4_FAULT + 151 + + + + BEE + Bus Encryption Engine + BEE + BEE_ + 0x403EC000 + + 0 + 0x48 + registers + + + BEE + 55 + + + + CTRL + BEE Control Register + 0 + 32 + read-write + 0x7700 + 0xFFFFFFFF + + + BEE_ENABLE + BEE enable bit + 0 + 1 + read-write + + + BEE_ENABLE_0 + Disable BEE + 0 + + + BEE_ENABLE_1 + Enable BEE + 0x1 + + + + + CTRL_CLK_EN + Clock enable input, low inactive + 1 + 1 + read-write + + + CTRL_SFTRST_N + Soft reset input, low active + 2 + 1 + read-write + + + KEY_VALID + AES-128 key is ready + 4 + 1 + read-write + + + KEY_REGION_SEL + AES key region select + 5 + 1 + read-write + + + KEY_REGION_SEL_0 + Load AES key for region0 + 0 + + + KEY_REGION_SEL_1 + Load AES key for region1 + 0x1 + + + + + AC_PROT_EN + Enable access permission control When AC_PROT_EN is asserted, all encrypted regions are limited to be ARM core access only + 6 + 1 + read-write + + + LITTLE_ENDIAN + Endian swap control for the 16 bytes input and output data of AES core. + 7 + 1 + read-write + + + LITTLE_ENDIAN_0 + The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8, B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to Byte0 to Byte15. + 0 + + + LITTLE_ENDIAN_1 + The input and output data of AES core is not swapped. + 0x1 + + + + + SECURITY_LEVEL_R0 + Security level of the allowed access for memory region0 + 8 + 2 + read-write + + + CTRL_AES_MODE_R0 + AES mode of region0 + 10 + 1 + read-write + + + CTRL_AES_MODE_R0_0 + ECB + 0 + + + CTRL_AES_MODE_R0_1 + CTR + 0x1 + + + + + SECURITY_LEVEL_R1 + Security level of the allowed access for memory region1 + 12 + 2 + read-write + + + CTRL_AES_MODE_R1 + AES mode of region1 + 14 + 1 + read-write + + + CTRL_AES_MODE_R1_0 + ECB + 0 + + + CTRL_AES_MODE_R1_1 + CTR + 0x1 + + + + + BEE_ENABLE_LOCK + Lock bit for bee_enable + 16 + 1 + read-write + + + CTRL_CLK_EN_LOCK + Lock bit for ctrl_clk_en + 17 + 1 + read-write + + + CTRL_SFTRST_N_LOCK + Lock bit for ctrl_sftrst + 18 + 1 + read-write + + + REGION1_ADDR_LOCK + Lock bit for region1 address boundary + 19 + 1 + read-write + + + KEY_VALID_LOCK + Lock bit for key_valid + 20 + 1 + read-write + + + KEY_REGION_SEL_LOCK + Lock bit for key_region_sel + 21 + 1 + read-write + + + AC_PROT_EN_LOCK + Lock bit for ac_prot + 22 + 1 + read-write + + + LITTLE_ENDIAN_LOCK + Lock bit for little_endian + 23 + 1 + read-write + + + SECURITY_LEVEL_R0_LOCK + Lock bits for security_level_r0 + 24 + 2 + read-write + + + CTRL_AES_MODE_R0_LOCK + Lock bit for region0 ctrl_aes_mode + 26 + 1 + read-write + + + REGION0_KEY_LOCK + Lock bit for region0 AES key + 27 + 1 + read-write + + + SECURITY_LEVEL_R1_LOCK + Lock bits for security_level_r1 + 28 + 2 + read-write + + + CTRL_AES_MODE_R1_LOCK + Lock bit for region1 ctrl_aes_mode + 30 + 1 + read-write + + + REGION1_KEY_LOCK + Lock bit for region1 AES key + 31 + 1 + read-write + + + + + ADDR_OFFSET0 + no description available + 0x4 + 32 + read-write + 0xF000 + 0xFFFFFFFF + + + ADDR_OFFSET0 + Signed offset for BEE region 0 + 0 + 16 + read-write + + + ADDR_OFFSET0_LOCK + Lock bits for addr_offset0 + 16 + 16 + read-write + + + + + ADDR_OFFSET1 + no description available + 0x8 + 32 + read-write + 0xF000 + 0xFFFFFFFF + + + ADDR_OFFSET1 + Signed offset for BEE region 1 + 0 + 16 + read-write + + + ADDR_OFFSET1_LOCK + Lock bits for addr_offset1 + 16 + 16 + read-write + + + + + AES_KEY0_W0 + no description available + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY0 + AES 128 key from software + 0 + 32 + read-write + + + + + AES_KEY0_W1 + no description available + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY1 + AES 128 key from software + 0 + 32 + read-write + + + + + AES_KEY0_W2 + no description available + 0x14 + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY2 + AES 128 key from software + 0 + 32 + read-write + + + + + AES_KEY0_W3 + no description available + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + KEY3 + AES 128 key from software + 0 + 32 + read-write + + + + + STATUS + no description available + 0x1C + 32 + read-write + 0 + 0 + + + IRQ_VEC + bit 7: Protected region-3 access violation bit 6: Protected region-2 access violation bit 5: Protected region-1 access violation bit 4: Protected region-0 access violation bit 3: Region-1 read channel security violation bit 2: Read channel illegal access detected bit 1: Region-0 read channel security violation bit 0: Disable abort + 0 + 8 + read-write + oneToClear + + + BEE_IDLE + 1'b1: BEE is idle; 1'b0: BEE is active + 8 + 1 + read-only + + + + + CTR_NONCE0_W0 + no description available + 0x20 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE00 + Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00} + 0 + 32 + write-only + + + + + CTR_NONCE0_W1 + no description available + 0x24 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE01 + Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00} + 0 + 32 + write-only + + + + + CTR_NONCE0_W2 + no description available + 0x28 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE02 + Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00} + 0 + 32 + write-only + + + + + CTR_NONCE0_W3 + no description available + 0x2C + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE03 + Nonce0 from software for CTR, for region0. Nonce0={Nonce03,Nonce02,Nonce01,Nonce00} + 0 + 32 + write-only + + + + + CTR_NONCE1_W0 + no description available + 0x30 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE10 + Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10} + 0 + 32 + write-only + + + + + CTR_NONCE1_W1 + no description available + 0x34 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE11 + Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10} + 0 + 32 + write-only + + + + + CTR_NONCE1_W2 + no description available + 0x38 + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE12 + Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10} + 0 + 32 + write-only + + + + + CTR_NONCE1_W3 + no description available + 0x3C + 32 + write-only + 0 + 0xFFFFFFFF + + + NONCE13 + Nonce1 from software for CTR, for region1. Nonce1={Nonce13,Nonce12,Nonce11,Nonce10} + 0 + 32 + write-only + + + + + REGION1_TOP + no description available + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + REGION1_TOP + Address upper limit of region1 + 0 + 32 + read-write + + + + + REGION1_BOT + no description available + 0x44 + 32 + read-write + 0 + 0xFFFFFFFF + + + REGION1_BOT + Address lower limit of region1 + 0 + 32 + read-write + + + + + + + LPI2C1 + LPI2C + LPI2C + LPI2C + 0x403F0000 + + 0 + 0x174 + registers + + + LPI2C1 + 28 + + + + VERID + Version ID Register + 0 + 32 + read-only + 0x1000003 + 0xFFFFFFFF + + + FEATURE + Feature Specification Number + 0 + 16 + read-only + + + FEATURE_2 + Master only, with standard feature set + 0x2 + + + FEATURE_3 + Master and slave, with standard feature set + 0x3 + + + + + MINOR + Minor Version Number + 16 + 8 + read-only + + + MAJOR + Major Version Number + 24 + 8 + read-only + + + + + PARAM + Parameter Register + 0x4 + 32 + read-only + 0x202 + 0xFFFFFFFF + + + MTXFIFO + Master Transmit FIFO Size + 0 + 4 + read-only + + + MRXFIFO + Master Receive FIFO Size + 8 + 4 + read-only + + + + + MCR + Master Control Register + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEN + Master Enable + 0 + 1 + read-write + + + MEN_0 + Master logic is disabled + 0 + + + MEN_1 + Master logic is enabled + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + RST_0 + Master logic is not reset + 0 + + + RST_1 + Master logic is reset + 0x1 + + + + + DOZEN + Doze mode enable + 2 + 1 + read-write + + + DOZEN_0 + Master is enabled in Doze mode + 0 + + + DOZEN_1 + Master is disabled in Doze mode + 0x1 + + + + + DBGEN + Debug Enable + 3 + 1 + read-write + + + DBGEN_0 + Master is disabled in debug mode + 0 + + + DBGEN_1 + Master is enabled in debug mode + 0x1 + + + + + RTF + Reset Transmit FIFO + 8 + 1 + read-write + + + RTF_0 + No effect + 0 + + + RTF_1 + Transmit FIFO is reset + 0x1 + + + + + RRF + Reset Receive FIFO + 9 + 1 + read-write + + + RRF_0 + No effect + 0 + + + RRF_1 + Receive FIFO is reset + 0x1 + + + + + + + MSR + Master Status Register + 0x14 + 32 + read-write + 0x1 + 0xFFFFFFFF + + + TDF + Transmit Data Flag + 0 + 1 + read-only + + + TDF_0 + Transmit data is not requested + 0 + + + TDF_1 + Transmit data is requested + 0x1 + + + + + RDF + Receive Data Flag + 1 + 1 + read-only + + + RDF_0 + Receive Data is not ready + 0 + + + RDF_1 + Receive data is ready + 0x1 + + + + + EPF + End Packet Flag + 8 + 1 + read-write + oneToClear + + + EPF_0 + Master has not generated a STOP or Repeated START condition + 0 + + + EPF_1 + Master has generated a STOP or Repeated START condition + 0x1 + + + + + SDF + STOP Detect Flag + 9 + 1 + read-write + oneToClear + + + SDF_0 + Master has not generated a STOP condition + 0 + + + SDF_1 + Master has generated a STOP condition + 0x1 + + + + + NDF + NACK Detect Flag + 10 + 1 + read-write + oneToClear + + + NDF_0 + Unexpected NACK was not detected + 0 + + + NDF_1 + Unexpected NACK was detected + 0x1 + + + + + ALF + Arbitration Lost Flag + 11 + 1 + read-write + oneToClear + + + ALF_0 + Master has not lost arbitration + 0 + + + ALF_1 + Master has lost arbitration + 0x1 + + + + + FEF + FIFO Error Flag + 12 + 1 + read-write + oneToClear + + + FEF_0 + No error + 0 + + + FEF_1 + Master sending or receiving data without a START condition + 0x1 + + + + + PLTF + Pin Low Timeout Flag + 13 + 1 + read-write + oneToClear + + + PLTF_0 + Pin low timeout has not occurred or is disabled + 0 + + + PLTF_1 + Pin low timeout has occurred + 0x1 + + + + + DMF + Data Match Flag + 14 + 1 + read-write + oneToClear + + + DMF_0 + Have not received matching data + 0 + + + DMF_1 + Have received matching data + 0x1 + + + + + MBF + Master Busy Flag + 24 + 1 + read-only + + + MBF_0 + I2C Master is idle + 0 + + + MBF_1 + I2C Master is busy + 0x1 + + + + + BBF + Bus Busy Flag + 25 + 1 + read-only + + + BBF_0 + I2C Bus is idle + 0 + + + BBF_1 + I2C Bus is busy + 0x1 + + + + + + + MIER + Master Interrupt Enable Register + 0x18 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDIE + Transmit Data Interrupt Enable + 0 + 1 + read-write + + + TDIE_0 + Disabled + 0 + + + TDIE_1 + Enabled + 0x1 + + + + + RDIE + Receive Data Interrupt Enable + 1 + 1 + read-write + + + RDIE_0 + Disabled + 0 + + + RDIE_1 + Enabled + 0x1 + + + + + EPIE + End Packet Interrupt Enable + 8 + 1 + read-write + + + EPIE_0 + Disabled + 0 + + + EPIE_1 + Enabled + 0x1 + + + + + SDIE + STOP Detect Interrupt Enable + 9 + 1 + read-write + + + SDIE_0 + Disabled + 0 + + + SDIE_1 + Enabled + 0x1 + + + + + NDIE + NACK Detect Interrupt Enable + 10 + 1 + read-write + + + NDIE_0 + Disabled + 0 + + + NDIE_1 + Enabled + 0x1 + + + + + ALIE + Arbitration Lost Interrupt Enable + 11 + 1 + read-write + + + ALIE_0 + Disabled + 0 + + + ALIE_1 + Enabled + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 12 + 1 + read-write + + + FEIE_0 + Enabled + 0 + + + FEIE_1 + Disabled + 0x1 + + + + + PLTIE + Pin Low Timeout Interrupt Enable + 13 + 1 + read-write + + + PLTIE_0 + Disabled + 0 + + + PLTIE_1 + Enabled + 0x1 + + + + + DMIE + Data Match Interrupt Enable + 14 + 1 + read-write + + + DMIE_0 + Disabled + 0 + + + DMIE_1 + Enabled + 0x1 + + + + + + + MDER + Master DMA Enable Register + 0x1C + 32 + read-write + 0 + 0xFFFFFFFF + + + TDDE + Transmit Data DMA Enable + 0 + 1 + read-write + + + TDDE_0 + DMA request is disabled + 0 + + + TDDE_1 + DMA request is enabled + 0x1 + + + + + RDDE + Receive Data DMA Enable + 1 + 1 + read-write + + + RDDE_0 + DMA request is disabled + 0 + + + RDDE_1 + DMA request is enabled + 0x1 + + + + + + + MCFGR0 + Master Configuration Register 0 + 0x20 + 32 + read-write + 0 + 0xFFFFFFFF + + + HREN + Host Request Enable + 0 + 1 + read-write + + + HREN_0 + Host request input is disabled + 0 + + + HREN_1 + Host request input is enabled + 0x1 + + + + + HRPOL + Host Request Polarity + 1 + 1 + read-write + + + HRPOL_0 + Active low + 0 + + + HRPOL_1 + Active high + 0x1 + + + + + HRSEL + Host Request Select + 2 + 1 + read-write + + + HRSEL_0 + Host request input is pin HREQ + 0 + + + HRSEL_1 + Host request input is input trigger + 0x1 + + + + + CIRFIFO + Circular FIFO Enable + 8 + 1 + read-write + + + CIRFIFO_0 + Circular FIFO is disabled + 0 + + + CIRFIFO_1 + Circular FIFO is enabled + 0x1 + + + + + RDMO + Receive Data Match Only + 9 + 1 + read-write + + + RDMO_0 + Received data is stored in the receive FIFO + 0 + + + RDMO_1 + Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set + 0x1 + + + + + + + MCFGR1 + Master Configuration Register 1 + 0x24 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRESCALE + Prescaler + 0 + 3 + read-write + + + PRESCALE_0 + Divide by 1 + 0 + + + PRESCALE_1 + Divide by 2 + 0x1 + + + PRESCALE_2 + Divide by 4 + 0x2 + + + PRESCALE_3 + Divide by 8 + 0x3 + + + PRESCALE_4 + Divide by 16 + 0x4 + + + PRESCALE_5 + Divide by 32 + 0x5 + + + PRESCALE_6 + Divide by 64 + 0x6 + + + PRESCALE_7 + Divide by 128 + 0x7 + + + + + AUTOSTOP + Automatic STOP Generation + 8 + 1 + read-write + + + AUTOSTOP_0 + No effect + 0 + + + AUTOSTOP_1 + STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy + 0x1 + + + + + IGNACK + IGNACK + 9 + 1 + read-write + + + IGNACK_0 + LPI2C Master will receive ACK and NACK normally + 0 + + + IGNACK_1 + LPI2C Master will treat a received NACK as if it (NACK) was an ACK + 0x1 + + + + + TIMECFG + Timeout Configuration + 10 + 1 + read-write + + + TIMECFG_0 + Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout + 0 + + + TIMECFG_1 + Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout + 0x1 + + + + + MATCFG + Match Configuration + 16 + 3 + read-write + + + MATCFG_0 + Match is disabled + 0 + + + MATCFG_2 + Match is enabled (1st data word equals MATCH0 OR MATCH1) + 0x2 + + + MATCFG_3 + Match is enabled (any data word equals MATCH0 OR MATCH1) + 0x3 + + + MATCFG_4 + Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) + 0x4 + + + MATCFG_5 + Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) + 0x5 + + + MATCFG_6 + Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) + 0x6 + + + MATCFG_7 + Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) + 0x7 + + + + + PINCFG + Pin Configuration + 24 + 3 + read-write + + + PINCFG_0 + 2-pin open drain mode + 0 + + + PINCFG_1 + 2-pin output only mode (ultra-fast mode) + 0x1 + + + PINCFG_2 + 2-pin push-pull mode + 0x2 + + + PINCFG_3 + 4-pin push-pull mode + 0x3 + + + PINCFG_4 + 2-pin open drain mode with separate LPI2C slave + 0x4 + + + PINCFG_5 + 2-pin output only mode (ultra-fast mode) with separate LPI2C slave + 0x5 + + + PINCFG_6 + 2-pin push-pull mode with separate LPI2C slave + 0x6 + + + PINCFG_7 + 4-pin push-pull mode (inverted outputs) + 0x7 + + + + + + + MCFGR2 + Master Configuration Register 2 + 0x28 + 32 + read-write + 0 + 0xFFFFFFFF + + + BUSIDLE + Bus Idle Timeout + 0 + 12 + read-write + + + FILTSCL + Glitch Filter SCL + 16 + 4 + read-write + + + FILTSDA + Glitch Filter SDA + 24 + 4 + read-write + + + + + MCFGR3 + Master Configuration Register 3 + 0x2C + 32 + read-write + 0 + 0xFFFFFFFF + + + PINLOW + Pin Low Timeout + 8 + 12 + read-write + + + + + MDMR + Master Data Match Register + 0x40 + 32 + read-write + 0 + 0xFFFFFFFF + + + MATCH0 + Match 0 Value + 0 + 8 + read-write + + + MATCH1 + Match 1 Value + 16 + 8 + read-write + + + + + MCCR0 + Master Clock Configuration Register 0 + 0x48 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLKLO + Clock Low Period + 0 + 6 + read-write + + + CLKHI + Clock High Period + 8 + 6 + read-write + + + SETHOLD + Setup Hold Delay + 16 + 6 + read-write + + + DATAVD + Data Valid Delay + 24 + 6 + read-write + + + + + MCCR1 + Master Clock Configuration Register 1 + 0x50 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLKLO + Clock Low Period + 0 + 6 + read-write + + + CLKHI + Clock High Period + 8 + 6 + read-write + + + SETHOLD + Setup Hold Delay + 16 + 6 + read-write + + + DATAVD + Data Valid Delay + 24 + 6 + read-write + + + + + MFCR + Master FIFO Control Register + 0x58 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXWATER + Transmit FIFO Watermark + 0 + 2 + read-write + + + RXWATER + Receive FIFO Watermark + 16 + 2 + read-write + + + + + MFSR + Master FIFO Status Register + 0x5C + 32 + read-only + 0 + 0xFFFFFFFF + + + TXCOUNT + Transmit FIFO Count + 0 + 3 + read-only + + + RXCOUNT + Receive FIFO Count + 16 + 3 + read-only + + + + + MTDR + Master Transmit Data Register + 0x60 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Transmit Data + 0 + 8 + write-only + + + CMD + Command Data + 8 + 3 + write-only + + + CMD_0 + Transmit DATA[7:0] + 0 + + + CMD_1 + Receive (DATA[7:0] + 1) bytes + 0x1 + + + CMD_2 + Generate STOP condition + 0x2 + + + CMD_3 + Receive and discard (DATA[7:0] + 1) bytes + 0x3 + + + CMD_4 + Generate (repeated) START and transmit address in DATA[7:0] + 0x4 + + + CMD_5 + Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. + 0x5 + + + CMD_6 + Generate (repeated) START and transmit address in DATA[7:0] using high speed mode + 0x6 + + + CMD_7 + Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. + 0x7 + + + + + + + MRDR + Master Receive Data Register + 0x70 + 32 + read-only + 0x4000 + 0xFFFFFFFF + + + DATA + Receive Data + 0 + 8 + read-only + + + RXEMPTY + RX Empty + 14 + 1 + read-only + + + RXEMPTY_0 + Receive FIFO is not empty + 0 + + + RXEMPTY_1 + Receive FIFO is empty + 0x1 + + + + + + + SCR + Slave Control Register + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + SEN + Slave Enable + 0 + 1 + read-write + + + SEN_0 + I2C Slave mode is disabled + 0 + + + SEN_1 + I2C Slave mode is enabled + 0x1 + + + + + RST + Software Reset + 1 + 1 + read-write + + + RST_0 + Slave mode logic is not reset + 0 + + + RST_1 + Slave mode logic is reset + 0x1 + + + + + FILTEN + Filter Enable + 4 + 1 + read-write + + + FILTEN_0 + Disable digital filter and output delay counter for slave mode + 0 + + + FILTEN_1 + Enable digital filter and output delay counter for slave mode + 0x1 + + + + + FILTDZ + Filter Doze Enable + 5 + 1 + read-write + + + FILTDZ_0 + Filter remains enabled in Doze mode + 0 + + + FILTDZ_1 + Filter is disabled in Doze mode + 0x1 + + + + + RTF + Reset Transmit FIFO + 8 + 1 + read-write + + + RTF_0 + No effect + 0 + + + RTF_1 + Transmit Data Register is now empty + 0x1 + + + + + RRF + Reset Receive FIFO + 9 + 1 + read-write + + + RRF_0 + No effect + 0 + + + RRF_1 + Receive Data Register is now empty + 0x1 + + + + + + + SSR + Slave Status Register + 0x114 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDF + Transmit Data Flag + 0 + 1 + read-only + + + TDF_0 + Transmit data not requested + 0 + + + TDF_1 + Transmit data is requested + 0x1 + + + + + RDF + Receive Data Flag + 1 + 1 + read-only + + + RDF_0 + Receive data is not ready + 0 + + + RDF_1 + Receive data is ready + 0x1 + + + + + AVF + Address Valid Flag + 2 + 1 + read-only + + + AVF_0 + Address Status Register is not valid + 0 + + + AVF_1 + Address Status Register is valid + 0x1 + + + + + TAF + Transmit ACK Flag + 3 + 1 + read-only + + + TAF_0 + Transmit ACK/NACK is not required + 0 + + + TAF_1 + Transmit ACK/NACK is required + 0x1 + + + + + RSF + Repeated Start Flag + 8 + 1 + read-write + oneToClear + + + RSF_0 + Slave has not detected a Repeated START condition + 0 + + + RSF_1 + Slave has detected a Repeated START condition + 0x1 + + + + + SDF + STOP Detect Flag + 9 + 1 + read-write + oneToClear + + + SDF_0 + Slave has not detected a STOP condition + 0 + + + SDF_1 + Slave has detected a STOP condition + 0x1 + + + + + BEF + Bit Error Flag + 10 + 1 + read-write + oneToClear + + + BEF_0 + Slave has not detected a bit error + 0 + + + BEF_1 + Slave has detected a bit error + 0x1 + + + + + FEF + FIFO Error Flag + 11 + 1 + read-write + oneToClear + + + FEF_0 + FIFO underflow or overflow was not detected + 0 + + + FEF_1 + FIFO underflow or overflow was detected + 0x1 + + + + + AM0F + Address Match 0 Flag + 12 + 1 + read-only + + + AM0F_0 + Have not received an ADDR0 matching address + 0 + + + AM0F_1 + Have received an ADDR0 matching address + 0x1 + + + + + AM1F + Address Match 1 Flag + 13 + 1 + read-only + + + AM1F_0 + Have not received an ADDR1 or ADDR0/ADDR1 range matching address + 0 + + + AM1F_1 + Have received an ADDR1 or ADDR0/ADDR1 range matching address + 0x1 + + + + + GCF + General Call Flag + 14 + 1 + read-only + + + GCF_0 + Slave has not detected the General Call Address or the General Call Address is disabled + 0 + + + GCF_1 + Slave has detected the General Call Address + 0x1 + + + + + SARF + SMBus Alert Response Flag + 15 + 1 + read-only + + + SARF_0 + SMBus Alert Response is disabled or not detected + 0 + + + SARF_1 + SMBus Alert Response is enabled and detected + 0x1 + + + + + SBF + Slave Busy Flag + 24 + 1 + read-only + + + SBF_0 + I2C Slave is idle + 0 + + + SBF_1 + I2C Slave is busy + 0x1 + + + + + BBF + Bus Busy Flag + 25 + 1 + read-only + + + BBF_0 + I2C Bus is idle + 0 + + + BBF_1 + I2C Bus is busy + 0x1 + + + + + + + SIER + Slave Interrupt Enable Register + 0x118 + 32 + read-write + 0 + 0xFFFFFFFF + + + TDIE + Transmit Data Interrupt Enable + 0 + 1 + read-write + + + TDIE_0 + Disabled + 0 + + + TDIE_1 + Enabled + 0x1 + + + + + RDIE + Receive Data Interrupt Enable + 1 + 1 + read-write + + + RDIE_0 + Disabled + 0 + + + RDIE_1 + Enabled + 0x1 + + + + + AVIE + Address Valid Interrupt Enable + 2 + 1 + read-write + + + AVIE_0 + Disabled + 0 + + + AVIE_1 + Enabled + 0x1 + + + + + TAIE + Transmit ACK Interrupt Enable + 3 + 1 + read-write + + + TAIE_0 + Disabled + 0 + + + TAIE_1 + Enabled + 0x1 + + + + + RSIE + Repeated Start Interrupt Enable + 8 + 1 + read-write + + + RSIE_0 + Disabled + 0 + + + RSIE_1 + Enabled + 0x1 + + + + + SDIE + STOP Detect Interrupt Enable + 9 + 1 + read-write + + + SDIE_0 + Disabled + 0 + + + SDIE_1 + Enabled + 0x1 + + + + + BEIE + Bit Error Interrupt Enable + 10 + 1 + read-write + + + BEIE_0 + Disabled + 0 + + + BEIE_1 + Enabled + 0x1 + + + + + FEIE + FIFO Error Interrupt Enable + 11 + 1 + read-write + + + FEIE_0 + Disabled + 0 + + + FEIE_1 + Enabled + 0x1 + + + + + AM0IE + Address Match 0 Interrupt Enable + 12 + 1 + read-write + + + AM0IE_0 + Enabled + 0 + + + AM0IE_1 + Disabled + 0x1 + + + + + AM1F + Address Match 1 Interrupt Enable + 13 + 1 + read-write + + + AM1F_0 + Disabled + 0 + + + AM1F_1 + Enabled + 0x1 + + + + + GCIE + General Call Interrupt Enable + 14 + 1 + read-write + + + GCIE_0 + Disabled + 0 + + + GCIE_1 + Enabled + 0x1 + + + + + SARIE + SMBus Alert Response Interrupt Enable + 15 + 1 + read-write + + + SARIE_0 + Disabled + 0 + + + SARIE_1 + Enabled + 0x1 + + + + + + + SDER + Slave DMA Enable Register + 0x11C + 32 + read-write + 0 + 0xFFFFFFFF + + + TDDE + Transmit Data DMA Enable + 0 + 1 + read-write + + + TDDE_0 + DMA request is disabled + 0 + + + TDDE_1 + DMA request is enabled + 0x1 + + + + + RDDE + Receive Data DMA Enable + 1 + 1 + read-write + + + RDDE_0 + DMA request is disabled + 0 + + + RDDE_1 + DMA request is enabled + 0x1 + + + + + AVDE + Address Valid DMA Enable + 2 + 1 + read-write + + + AVDE_0 + DMA request is disabled + 0 + + + AVDE_1 + DMA request is enabled + 0x1 + + + + + + + SCFGR1 + Slave Configuration Register 1 + 0x124 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADRSTALL + Address SCL Stall + 0 + 1 + read-write + + + ADRSTALL_0 + Clock stretching is disabled + 0 + + + ADRSTALL_1 + Clock stretching is enabled + 0x1 + + + + + RXSTALL + RX SCL Stall + 1 + 1 + read-write + + + RXSTALL_0 + Clock stretching is disabled + 0 + + + RXSTALL_1 + Clock stretching is enabled + 0x1 + + + + + TXDSTALL + TX Data SCL Stall + 2 + 1 + read-write + + + TXDSTALL_0 + Clock stretching is disabled + 0 + + + TXDSTALL_1 + Clock stretching is enabled + 0x1 + + + + + ACKSTALL + ACK SCL Stall + 3 + 1 + read-write + + + ACKSTALL_0 + Clock stretching is disabled + 0 + + + ACKSTALL_1 + Clock stretching is enabled + 0x1 + + + + + GCEN + General Call Enable + 8 + 1 + read-write + + + GCEN_0 + General Call address is disabled + 0 + + + GCEN_1 + General Call address is enabled + 0x1 + + + + + SAEN + SMBus Alert Enable + 9 + 1 + read-write + + + SAEN_0 + Disables match on SMBus Alert + 0 + + + SAEN_1 + Enables match on SMBus Alert + 0x1 + + + + + TXCFG + Transmit Flag Configuration + 10 + 1 + read-write + + + TXCFG_0 + Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty + 0 + + + TXCFG_1 + Transmit Data Flag will assert whenever the Transmit Data register is empty + 0x1 + + + + + RXCFG + Receive Data Configuration + 11 + 1 + read-write + + + RXCFG_0 + Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). + 0 + + + RXCFG_1 + Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). + 0x1 + + + + + IGNACK + Ignore NACK + 12 + 1 + read-write + + + IGNACK_0 + Slave will end transfer when NACK is detected + 0 + + + IGNACK_1 + Slave will not end transfer when NACK detected + 0x1 + + + + + HSMEN + High Speed Mode Enable + 13 + 1 + read-write + + + HSMEN_0 + Disables detection of HS-mode master code + 0 + + + HSMEN_1 + Enables detection of HS-mode master code + 0x1 + + + + + ADDRCFG + Address Configuration + 16 + 3 + read-write + + + ADDRCFG_0 + Address match 0 (7-bit) + 0 + + + ADDRCFG_1 + Address match 0 (10-bit) + 0x1 + + + ADDRCFG_2 + Address match 0 (7-bit) or Address match 1 (7-bit) + 0x2 + + + ADDRCFG_3 + Address match 0 (10-bit) or Address match 1 (10-bit) + 0x3 + + + ADDRCFG_4 + Address match 0 (7-bit) or Address match 1 (10-bit) + 0x4 + + + ADDRCFG_5 + Address match 0 (10-bit) or Address match 1 (7-bit) + 0x5 + + + ADDRCFG_6 + From Address match 0 (7-bit) to Address match 1 (7-bit) + 0x6 + + + ADDRCFG_7 + From Address match 0 (10-bit) to Address match 1 (10-bit) + 0x7 + + + + + + + SCFGR2 + Slave Configuration Register 2 + 0x128 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLKHOLD + Clock Hold Time + 0 + 4 + read-write + + + DATAVD + Data Valid Delay + 8 + 6 + read-write + + + FILTSCL + Glitch Filter SCL + 16 + 4 + read-write + + + FILTSDA + Glitch Filter SDA + 24 + 4 + read-write + + + + + SAMR + Slave Address Match Register + 0x140 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDR0 + Address 0 Value + 1 + 10 + read-write + + + ADDR1 + Address 1 Value + 17 + 10 + read-write + + + + + SASR + Slave Address Status Register + 0x150 + 32 + read-only + 0x4000 + 0xFFFFFFFF + + + RADDR + Received Address + 0 + 11 + read-only + + + ANV + Address Not Valid + 14 + 1 + read-only + + + ANV_0 + Received Address (RADDR) is valid + 0 + + + ANV_1 + Received Address (RADDR) is not valid + 0x1 + + + + + + + STAR + Slave Transmit ACK Register + 0x154 + 32 + read-write + 0 + 0xFFFFFFFF + + + TXNACK + Transmit NACK + 0 + 1 + read-write + + + TXNACK_0 + Write a Transmit ACK for each received word + 0 + + + TXNACK_1 + Write a Transmit NACK for each received word + 0x1 + + + + + + + STDR + Slave Transmit Data Register + 0x160 + 32 + read-write + 0 + 0xFFFFFFFF + + + DATA + Transmit Data + 0 + 8 + write-only + + + + + SRDR + Slave Receive Data Register + 0x170 + 32 + read-only + 0x4000 + 0xFFFFFFFF + + + DATA + Receive Data + 0 + 8 + read-only + + + RXEMPTY + RX Empty + 14 + 1 + read-only + + + RXEMPTY_0 + The Receive Data Register is not empty + 0 + + + RXEMPTY_1 + The Receive Data Register is empty + 0x1 + + + + + SOF + Start Of Frame + 15 + 1 + read-only + + + SOF_0 + Indicates this is not the first data word since a (repeated) START or STOP condition + 0 + + + SOF_1 + Indicates this is the first data word since a (repeated) START or STOP condition + 0x1 + + + + + + + + + LPI2C2 + LPI2C + LPI2C + 0x403F4000 + + 0 + 0x174 + registers + + + LPI2C2 + 29 + + + + LPI2C3 + LPI2C + LPI2C + 0x403F8000 + + 0 + 0x174 + registers + + + LPI2C3 + 30 + + + + LPI2C4 + LPI2C + LPI2C + 0x403FC000 + + 0 + 0x174 + registers + + + LPI2C4 + 31 + + + + SystemControl + System Control Block + SCB + SCB_ + 0xE000E000 + + 0 + 0xFAC + registers + + + + ACTLR + Auxiliary Control Register, + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + DISFOLD + Disables folding of IT instructions. + 2 + 1 + read-write + + + DISFOLD_0 + Normal operation. + 0 + + + + + FPEXCODIS + Disables FPU exception outputs. + 10 + 1 + read-write + + + FPEXCODIS_0 + Normal operation. + 0 + + + FPEXCODIS_1 + FPU exception outputs are disabled. + 0x1 + + + + + DISRAMODE + Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions. + 11 + 1 + read-write + + + DISRAMODE_0 + Normal operation. + 0 + + + DISRAMODE_1 + Dynamic disabled. + 0x1 + + + + + DISITMATBFLUSH + Disables ITM and DWT ATB flush. + 12 + 1 + read-write + + + DISITMATBFLUSH_1 + ITM and DWT ATB flush disabled, this bit is always 1. + 0x1 + + + + + DISBTACREAD + Disables BTAC read. + 13 + 1 + read-write + + + DISBTACREAD_0 + Normal operation. + 0 + + + DISBTACREAD_1 + BTAC is not used and only static branch prediction can occur. + 0x1 + + + + + DISBTACALLOC + Disables BTAC allocate. + 14 + 1 + read-write + + + DISBTACALLOC_0 + Normal operation. + 0 + + + DISBTACALLOC_1 + No new entries are allocated in Branch Target Address Cache (BTAC), but existing entries can be updated. + 0x1 + + + + + DISCRITAXIRUR + Disables critical AXI Read-Under-Read. + 15 + 1 + read-write + + + DISCRITAXIRUR_0 + Normal operation. + 0 + + + DISCRITAXIRUR_1 + An AXI read to Strongly-Ordered or Device memory, or an LDREX to Shareable memory, is not put on AXI if there are any outstanding reads on AXI. Transactions on AXI cannot be interrupted. This bit might reduce the time that these transactions are in progress and might improve worst case interrupt latency. Performance is decreased when this bit is set. + 0x1 + + + + + DISDI + Disables dual-issued. + 16 + 5 + read-write + + + DISDI_0 + Normal operation. + 0 + + + DISDI_1 + Nothing can be dual-issued when this instruction type is in channel 0. + 0x1 + + + + + DISISSCH1 + Disables dual-issued. + 21 + 5 + read-write + + + DISISSCH1_0 + Normal operation. + 0 + + + DISISSCH1_1 + Nothing can be dual-issued when this instruction type is in channel 1. + 0x1 + + + + + DISDYNADD + Disables dynamic allocation of ADD and SUB instructions + 26 + 1 + read-write + + + DISDYNADD_0 + Normal operation. Some ADD and SUB instrctions are resolved in EX1. + 0 + + + DISDYNADD_1 + All ADD and SUB instructions are resolved in EX2. + 0x1 + + + + + DISCRITAXIRUW + Disables critical AXI read-under-write + 27 + 1 + read-write + + + DISCRITAXIRUW_0 + Normal operation. This is backwards compatible with r0. + 0 + + + DISCRITAXIRUW_1 + AXI reads to DEV/SO memory. Exclusive reads to Shareable memory are not initiated on the AXIM AR channel until all outstanding stores on AXI are complete. + 0x1 + + + + + DISFPUISSOPT + Disables critical AXI read-under-write + 28 + 1 + read-write + + + DISFPUISSOPT_0 + Normal operation. + 0 + + + + + + + CPUID + CPUID Base Register + 0xD00 + 32 + read-only + 0x410FC240 + 0xFFFFFFFF + + + REVISION + Indicates patch release: 0x0 = Patch 0 + 0 + 4 + read-only + + + PARTNO + Indicates part number + 4 + 12 + read-only + + + ARCHITECTURE + ARCHITECTURE + 16 + 4 + read-only + + + VARIANT + Indicates processor revision: 0x2 = Revision 2 + 20 + 4 + read-only + + + IMPLEMENTER + Implementer code + 24 + 8 + read-only + + + + + ICSR + Interrupt Control and State Register + 0xD04 + 32 + read-write + 0 + 0xFFFFFFFF + + + VECTACTIVE + Active exception number + 0 + 9 + read-only + + + RETTOBASE + Indicates whether there are preempted active exceptions + 11 + 1 + read-only + + + RETTOBASE_0 + there are preempted active exceptions to execute + 0 + + + RETTOBASE_1 + there are no active exceptions, or the currently-executing exception is the only active exception + 0x1 + + + + + VECTPENDING + Exception number of the highest priority pending enabled exception + 12 + 9 + read-only + + + ISRPENDING + Interrupt pending flag, excluding NMI and Faults + 22 + 1 + read-only + + + ISRPENDING_0 + No external interrupt pending. + 0 + + + ISRPENDING_1 + External interrupt pending. + 0x1 + + + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + write-only + + + PENDSTCLR_0 + no effect + 0 + + + PENDSTCLR_1 + removes the pending state from the SysTick exception + 0x1 + + + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + read-write + + + PENDSTSET_0 + write: no effect; read: SysTick exception is not pending + 0 + + + PENDSTSET_1 + write: changes SysTick exception state to pending; read: SysTick exception is pending + 0x1 + + + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + write-only + + + PENDSVCLR_0 + no effect + 0 + + + PENDSVCLR_1 + removes the pending state from the PendSV exception + 0x1 + + + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + read-write + + + PENDSVSET_0 + write: no effect; read: PendSV exception is not pending + 0 + + + PENDSVSET_1 + write: changes PendSV exception state to pending; read: PendSV exception is pending + 0x1 + + + + + NMIPENDSET + NMI set-pending bit + 31 + 1 + read-write + + + NMIPENDSET_0 + write: no effect; read: NMI exception is not pending + 0 + + + NMIPENDSET_1 + write: changes NMI exception state to pending; read: NMI exception is pending + 0x1 + + + + + + + VTOR + Vector Table Offset Register + 0xD08 + 32 + read-write + 0 + 0xFFFFFFFF + + + TBLOFF + Vector table base offset + 7 + 25 + read-write + + + + + AIRCR + Application Interrupt and Reset Control Register + 0xD0C + 32 + read-write + 0xFA050000 + 0xFFFFFFFF + + + VECTRESET + Writing 1 to this bit causes a local system reset + 0 + 1 + write-only + + + VECTRESET_0 + No change + 0 + + + VECTRESET_1 + Causes a local system reset + 0x1 + + + + + VECTCLRACTIVE + Writing 1 to this bit clears all active state information for fixed and configurable exceptions. + 1 + 1 + write-only + + + VECTCLRACTIVE_0 + No change + 0 + + + VECTCLRACTIVE_1 + Clears all active state information for fixed and configurable exceptions + 0x1 + + + + + SYSRESETREQ + System reset request + 2 + 1 + write-only + + + SYSRESETREQ_0 + no system reset request + 0 + + + SYSRESETREQ_1 + asserts a signal to the outer system that requests a reset + 0x1 + + + + + PRIGROUP + Interrupt priority grouping field. This field determines the split of group priority from subpriority. + 8 + 3 + read-write + + + ENDIANNESS + Data endianness + 15 + 1 + read-only + + + ENDIANNESS_0 + Little-endian + 0 + + + ENDIANNESS_1 + Big-endian + 0x1 + + + + + VECTKEY + Register key + 16 + 16 + read-write + + + + + SCR + System Control Register + 0xD10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SLEEPONEXIT + Indicates sleep-on-exit when returning from Handler mode to Thread mode + 1 + 1 + read-write + + + SLEEPONEXIT_0 + o not sleep when returning to Thread mode + 0 + + + SLEEPONEXIT_1 + enter sleep, or deep sleep, on return from an ISR + 0x1 + + + + + SLEEPDEEP + Controls whether the processor uses sleep or deep sleep as its low power mode + 2 + 1 + read-write + + + SLEEPDEEP_0 + sleep + 0 + + + SLEEPDEEP_1 + deep sleep + 0x1 + + + + + SEVONPEND + Send Event on Pending bit + 4 + 1 + read-write + + + SEVONPEND_0 + only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded + 0 + + + SEVONPEND_1 + enabled events and all interrupts, including disabled interrupts, can wakeup the processor + 0x1 + + + + + + + CCR + Configuration and Control Register + 0xD14 + 32 + read-write + 0x40000 + 0xFFFFFFFF + + + NONBASETHRDENA + Indicates how the processor enters Thread mode + 0 + 1 + read-write + + + NONBASETHRDENA_0 + processor can enter Thread mode only when no exception is active + 0 + + + NONBASETHRDENA_1 + processor can enter Thread mode from any level under the control of an EXC_RETURN value + 0x1 + + + + + USERSETMPEND + Enables unprivileged software access to the STIR + 1 + 1 + read-write + + + USERSETMPEND_0 + disable + 0 + + + USERSETMPEND_1 + enable + 0x1 + + + + + UNALIGN_TRP + Enables unaligned access traps + 3 + 1 + read-write + + + UNALIGN_TRP_0 + do not trap unaligned halfword and word accesses + 0 + + + UNALIGN_TRP_1 + trap unaligned halfword and word accesses + 0x1 + + + + + DIV_0_TRP + Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0 + 4 + 1 + read-write + + + DIV_0_TRP_0 + do not trap divide by 0 + 0 + + + DIV_0_TRP_1 + trap divide by 0 + 0x1 + + + + + BFHFNMIGN + Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. + 8 + 1 + read-write + + + BFHFNMIGN_0 + data bus faults caused by load and store instructions cause a lock-up + 0 + + + BFHFNMIGN_1 + handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions + 0x1 + + + + + STKALIGN + Indicates stack alignment on exception entry + 9 + 1 + read-write + + + STKALIGN_0 + 4-byte aligned + 0 + + + STKALIGN_1 + 8-byte aligned + 0x1 + + + + + DC + Enables L1 data cache. + 16 + 1 + read-write + + + DC_0 + L1 data cache disabled + 0 + + + DC_1 + L1 data cache enabled + 0x1 + + + + + IC + Enables L1 instruction cache. + 17 + 1 + read-write + + + IC_0 + L1 instruction cache disabled + 0 + + + IC_1 + L1 instruction cache enabled + 0x1 + + + + + BP + Always reads-as-one. It indicates branch prediction is enabled. + 18 + 1 + read-only + + + + + SHPR1 + System Handler Priority Register 1 + 0xD18 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_4 + Priority of system handler 4, MemManage + 0 + 8 + read-write + + + PRI_5 + Priority of system handler 5, BusFault + 8 + 8 + read-write + + + PRI_6 + Priority of system handler 6, UsageFault + 16 + 8 + read-write + + + + + SHPR2 + System Handler Priority Register 2 + 0xD1C + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_11 + Priority of system handler 11, SVCall + 24 + 8 + read-write + + + + + SHPR3 + System Handler Priority Register 3 + 0xD20 + 32 + read-write + 0 + 0xFFFFFFFF + + + PRI_14 + Priority of system handler 14, PendSV + 16 + 8 + read-write + + + PRI_15 + Priority of system handler 15, SysTick exception + 24 + 8 + read-write + + + + + SHCSR + System Handler Control and State Register + 0xD24 + 32 + read-write + 0 + 0xFFFFFFFF + + + MEMFAULTACT + MemManage exception active bit + 0 + 1 + read-write + + + MEMFAULTACT_0 + exception is not active + 0 + + + MEMFAULTACT_1 + exception is active + 0x1 + + + + + BUSFAULTACT + BusFault exception active bit + 1 + 1 + read-write + + + BUSFAULTACT_0 + exception is not active + 0 + + + BUSFAULTACT_1 + exception is active + 0x1 + + + + + USGFAULTACT + UsageFault exception active bit + 3 + 1 + read-write + + + USGFAULTACT_0 + exception is not active + 0 + + + USGFAULTACT_1 + exception is active + 0x1 + + + + + SVCALLACT + SVCall active bit + 7 + 1 + read-write + + + SVCALLACT_0 + exception is not active + 0 + + + SVCALLACT_1 + exception is active + 0x1 + + + + + MONITORACT + Debug monitor active bit + 8 + 1 + read-write + + + MONITORACT_0 + exception is not active + 0 + + + MONITORACT_1 + exception is active + 0x1 + + + + + PENDSVACT + PendSV exception active bit + 10 + 1 + read-write + + + PENDSVACT_0 + exception is not active + 0 + + + PENDSVACT_1 + exception is active + 0x1 + + + + + SYSTICKACT + SysTick exception active bit + 11 + 1 + read-write + + + SYSTICKACT_0 + exception is not active + 0 + + + SYSTICKACT_1 + exception is active + 0x1 + + + + + USGFAULTPENDED + UsageFault exception pending bit + 12 + 1 + read-write + + + USGFAULTPENDED_0 + exception is not pending + 0 + + + USGFAULTPENDED_1 + exception is pending + 0x1 + + + + + MEMFAULTPENDED + MemManage exception pending bit + 13 + 1 + read-write + + + MEMFAULTPENDED_0 + exception is not pending + 0 + + + MEMFAULTPENDED_1 + exception is pending + 0x1 + + + + + BUSFAULTPENDED + BusFault exception pending bit + 14 + 1 + read-write + + + BUSFAULTPENDED_0 + exception is not pending + 0 + + + BUSFAULTPENDED_1 + exception is pending + 0x1 + + + + + SVCALLPENDED + SVCall pending bit + 15 + 1 + read-write + + + SVCALLPENDED_0 + exception is not pending + 0 + + + SVCALLPENDED_1 + exception is pending + 0x1 + + + + + MEMFAULTENA + MemManage enable bit + 16 + 1 + read-write + + + MEMFAULTENA_0 + disable the exception + 0 + + + MEMFAULTENA_1 + enable the exception + 0x1 + + + + + BUSFAULTENA + BusFault enable bit + 17 + 1 + read-write + + + BUSFAULTENA_0 + disable the exception + 0 + + + BUSFAULTENA_1 + enable the exception + 0x1 + + + + + USGFAULTENA + UsageFault enable bit + 18 + 1 + read-write + + + USGFAULTENA_0 + disable the exception + 0 + + + USGFAULTENA_1 + enable the exception + 0x1 + + + + + + + CFSR + Configurable Fault Status Register + 0xD28 + 32 + read-write + 0 + 0xFFFFFFFF + + + IACCVIOL + Instruction access violation flag + 0 + 1 + read-write + + + IACCVIOL_0 + no instruction access violation fault + 0 + + + IACCVIOL_1 + the processor attempted an instruction fetch from a location that does not permit execution + 0x1 + + + + + DACCVIOL + Data access violation flag + 1 + 1 + read-write + + + DACCVIOL_0 + no data access violation fault + 0 + + + DACCVIOL_1 + the processor attempted a load or store at a location that does not permit the operation + 0x1 + + + + + MUNSTKERR + MemManage fault on unstacking for a return from exception + 3 + 1 + read-write + + + MUNSTKERR_0 + no unstacking fault + 0 + + + MUNSTKERR_1 + unstack for an exception return has caused one or more access violations + 0x1 + + + + + MSTKERR + MemManage fault on stacking for exception entry + 4 + 1 + read-write + + + MSTKERR_0 + no stacking fault + 0 + + + MSTKERR_1 + stacking for an exception entry has caused one or more access violations + 0x1 + + + + + MLSPERR + MemManage fault occurred during floating-point lazy state preservation + 5 + 1 + read-write + + + MLSPERR_0 + No MemManage fault occurred during floating-point lazy state preservation + 0 + + + MLSPERR_1 + A MemManage fault occurred during floating-point lazy state preservation + 0x1 + + + + + MMARVALID + MemManage Fault Address Register (MMFAR) valid flag + 7 + 1 + read-write + + + MMARVALID_0 + value in MMAR is not a valid fault address + 0 + + + MMARVALID_1 + MMAR holds a valid fault address + 0x1 + + + + + IBUSERR + Instruction bus error + 8 + 1 + read-write + + + IBUSERR_0 + no instruction bus error + 0 + + + IBUSERR_1 + instruction bus error + 0x1 + + + + + PRECISERR + Precise data bus error + 9 + 1 + read-write + + + PRECISERR_0 + no precise data bus error + 0 + + + PRECISERR_1 + a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault + 0x1 + + + + + IMPRECISERR + Imprecise data bus error + 10 + 1 + read-write + + + IMPRECISERR_0 + no imprecise data bus error + 0 + + + IMPRECISERR_1 + a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error + 0x1 + + + + + UNSTKERR + BusFault on unstacking for a return from exception + 11 + 1 + read-write + + + UNSTKERR_0 + no unstacking fault + 0 + + + UNSTKERR_1 + unstack for an exception return has caused one or more BusFaults + 0x1 + + + + + STKERR + BusFault on stacking for exception entry + 12 + 1 + read-write + + + STKERR_0 + no stacking fault + 0 + + + STKERR_1 + stacking for an exception entry has caused one or more BusFaults + 0x1 + + + + + LSPERR + Bus fault occurred during floating-point lazy state preservation + 13 + 1 + read-write + + + LSPERR_0 + No bus fault occurred during floating-point lazy state preservation + 0 + + + LSPERR_1 + A bus fault occurred during floating-point lazy state preservation + 0x1 + + + + + BFARVALID + BusFault Address Register (BFAR) valid flag + 15 + 1 + read-write + + + BFARVALID_0 + value in BFAR is not a valid fault address + 0 + + + BFARVALID_1 + BFAR holds a valid fault address + 0x1 + + + + + UNDEFINSTR + Undefined instruction UsageFault + 16 + 1 + read-write + + + UNDEFINSTR_0 + no undefined instruction UsageFault + 0 + + + UNDEFINSTR_1 + the processor has attempted to execute an undefined instruction + 0x1 + + + + + INVSTATE + Invalid state UsageFault + 17 + 1 + read-write + + + INVSTATE_0 + no invalid state UsageFault + 0 + + + INVSTATE_1 + the processor has attempted to execute an instruction that makes illegal use of the EPSR + 0x1 + + + + + INVPC + Invalid PC load UsageFault, caused by an invalid PC load by EXC_RETURN + 18 + 1 + read-write + + + INVPC_0 + no invalid PC load UsageFault + 0 + + + INVPC_1 + the processor has attempted an illegal load of EXC_RETURN to the PC + 0x1 + + + + + NOCP + No coprocessor UsageFault + 19 + 1 + read-write + + + NOCP_0 + no UsageFault caused by attempting to access a coprocessor + 0 + + + NOCP_1 + the processor has attempted to access a coprocessor + 0x1 + + + + + UNALIGNED + Unaligned access UsageFault + 24 + 1 + read-write + + + UNALIGNED_0 + no unaligned access fault, or unaligned access trapping not enabled + 0 + + + UNALIGNED_1 + the processor has made an unaligned memory access + 0x1 + + + + + DIVBYZERO + Divide by zero UsageFault + 25 + 1 + read-write + + + DIVBYZERO_0 + no divide by zero fault, or divide by zero trapping not enabled + 0 + + + DIVBYZERO_1 + the processor has executed an SDIV or UDIV instruction with a divisor of 0 + 0x1 + + + + + + + HFSR + HardFault Status register + 0xD2C + 32 + read-write + 0 + 0xFFFFFFFF + + + VECTTBL + Indicates a BusFault on a vector table read during exception processing. + 1 + 1 + read-write + + + VECTTBL_0 + no BusFault on vector table read + 0 + + + VECTTBL_1 + BusFault on vector table read + 0x1 + + + + + FORCED + Indicates a forced hard fault, generated by escalation of a fault with configurable priority that cannot be handles, either because of priority or because it is disabled. + 30 + 1 + read-write + + + FORCED_0 + no forced HardFault + 0 + + + FORCED_1 + forced HardFault + 0x1 + + + + + DEBUGEVT + Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable. + 31 + 1 + read-write + + + DEBUGEVT_0 + No Debug event has occurred. + 0 + + + DEBUGEVT_1 + Debug event has occurred. The Debug Fault Status Register has been updated. + 0x1 + + + + + + + DFSR + Debug Fault Status Register + 0xD30 + 32 + read-write + 0 + 0xFFFFFFFF + + + HALTED + Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1. + 0 + 1 + read-write + + + HALTED_0 + No active halt request debug event + 0 + + + HALTED_1 + Halt request debug event active + 0x1 + + + + + BKPT + Debug event generated by BKPT instruction execution or a breakpoint match in FPB + 1 + 1 + read-write + + + BKPT_0 + No current breakpoint debug event + 0 + + + BKPT_1 + At least one current breakpoint debug event + 0x1 + + + + + DWTTRAP + Debug event generated by the DWT + 2 + 1 + read-write + + + DWTTRAP_0 + No current debug events generated by the DWT + 0 + + + DWTTRAP_1 + At least one current debug event generated by the DWT + 0x1 + + + + + VCATCH + Indicates triggering of a Vector catch + 3 + 1 + read-write + + + VCATCH_0 + No Vector catch triggered + 0 + + + VCATCH_1 + Vector catch triggered + 0x1 + + + + + EXTERNAL + Debug event generated because of the assertion of an external debug request + 4 + 1 + read-write + + + EXTERNAL_0 + No external debug request debug event + 0 + + + EXTERNAL_1 + External debug request debug event + 0x1 + + + + + + + MMFAR + MemManage Fault Address Register + 0xD34 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDRESS + Address of MemManage fault location + 0 + 32 + read-write + + + + + BFAR + BusFault Address Register + 0xD38 + 32 + read-write + 0 + 0xFFFFFFFF + + + ADDRESS + Address of the BusFault location + 0 + 32 + read-write + + + + + ID_PFR0 + Processor Feature Register 0 + 0xD40 + 32 + read-only + 0 + 0xFFFFFFFF + + + STATE0 + ARM instruction set support + 0 + 4 + read-only + + + STATE0_0 + ARMv7-M unused + 0 + + + STATE0_1 + ARMv7-M unused + 0x1 + + + STATE0_2 + ARMv7-M unused + 0x2 + + + STATE0_3 + Support for Thumb encoding including Thumb-2 technology, with all basic 16-bit and 32-bit instructions. + 0x3 + + + + + STATE1 + Thumb instruction set support + 4 + 4 + read-only + + + STATE1_0 + The processor does not support the ARM instruction set. + 0 + + + STATE1_1 + ARMv7-M unused + 0x1 + + + + + STATE2 + ARMv7-M unused + 8 + 4 + read-only + + + STATE3 + ARMv7-M unused + 12 + 4 + read-only + + + + + ID_PFR1 + Processor Feature Register 1 + 0xD44 + 32 + read-only + 0 + 0xFFFFFFFF + + + PROGMODEL + M profile programmers' model + 8 + 4 + read-only + + + PROGMODEL_0 + ARMv7-M unused + 0 + + + PROGMODEL_2 + Two-stack programmers' model supported + 0x2 + + + + + + + ID_DFR0 + Debug Feature Register + 0xD48 + 32 + read-only + 0 + 0xFFFFFFFF + + + DEBUGMODEL + Support for memory-mapped debug model for M profile processors + 20 + 4 + read-only + + + DEBUGMODEL_0 + Not supported + 0 + + + DEBUGMODEL_1 + Support for M profile Debug architecture, with memory-mapped access. + 0x1 + + + + + + + ID_AFR0 + Auxiliary Feature Register + 0xD4C + 32 + read-only + 0 + 0xFFFFFFFF + + + IMPLEMENTATION_DEFINED0 + Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. + 0 + 4 + read-only + + + IMPLEMENTATION_DEFINED1 + Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. + 4 + 4 + read-only + + + IMPLEMENTATION_DEFINED2 + Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. + 8 + 4 + read-only + + + IMPLEMENTATION_DEFINED3 + Gives information about the IMPLEMENTATION DEFINED features of a processor implementation. + 12 + 4 + read-only + + + + + ID_MMFR0 + Memory Model Feature Register 0 + 0xD50 + 32 + read-only + 0 + 0xFFFFFFFF + + + PMSASUPPORT + Indicates support for a PMSA + 4 + 4 + read-only + + + PMSASUPPORT_0 + Not supported + 0 + + + PMSASUPPORT_1 + ARMv7-M unused + 0x1 + + + PMSASUPPORT_2 + ARMv7-M unused + 0x2 + + + PMSASUPPORT_3 + PMSAv7, providing support for a base region and subregions. + 0x3 + + + + + OUTERMOST_SHAREABILITY + Indicates the outermost shareability domain implemented + 8 + 4 + read-only + + + OUTERMOST_SHAREABILITY_0 + Implemented as Non-cacheable + 0 + + + OUTERMOST_SHAREABILITY_1 + ARMv7-M unused + 0x1 + + + OUTERMOST_SHAREABILITY_2 + ARMv7-M unused + 0x2 + + + OUTERMOST_SHAREABILITY_3 + ARMv7-M unused + 0x3 + + + OUTERMOST_SHAREABILITY_4 + ARMv7-M unused + 0x4 + + + OUTERMOST_SHAREABILITY_5 + ARMv7-M unused + 0x5 + + + OUTERMOST_SHAREABILITY_6 + ARMv7-M unused + 0x6 + + + OUTERMOST_SHAREABILITY_7 + ARMv7-M unused + 0x7 + + + OUTERMOST_SHAREABILITY_8 + ARMv7-M unused + 0x8 + + + OUTERMOST_SHAREABILITY_9 + ARMv7-M unused + 0x9 + + + OUTERMOST_SHAREABILITY_10 + ARMv7-M unused + 0xA + + + OUTERMOST_SHAREABILITY_11 + ARMv7-M unused + 0xB + + + OUTERMOST_SHAREABILITY_12 + ARMv7-M unused + 0xC + + + OUTERMOST_SHAREABILITY_13 + ARMv7-M unused + 0xD + + + OUTERMOST_SHAREABILITY_14 + ARMv7-M unused + 0xE + + + OUTERMOST_SHAREABILITY_15 + Shareability ignored. + 0xF + + + + + SHAREABILITY_LEVELS + Indicates the number of shareability levels implemented + 12 + 4 + read-only + + + SHAREABILITY_LEVELS_0 + One level of shareability implemented + 0 + + + SHAREABILITY_LEVELS_1 + ARMv7-M unused + 0x1 + + + + + TCM_SUPPORT + Indicates the support for Tightly Coupled Memory + 16 + 4 + read-only + + + TCM_SUPPORT_0 + No tightly coupled memories implemented. + 0 + + + TCM_SUPPORT_1 + Tightly coupled memories implemented with IMPLEMENTATION DEFINED control. + 0x1 + + + TCM_SUPPORT_2 + ARMv7-M unused + 0x2 + + + + + AUXILIARY_REGISTERS + Indicates the support for Auxiliary registers + 20 + 4 + read-only + + + AUXILIARY_REGISTERS_0 + Not supported + 0 + + + AUXILIARY_REGISTERS_1 + Support for Auxiliary Control Register only. + 0x1 + + + AUXILIARY_REGISTERS_2 + ARMv7-M unused + 0x2 + + + + + + + ID_MMFR1 + Memory Model Feature Register 1 + 0xD54 + 32 + read-only + 0 + 0xFFFFFFFF + + + ID_MMFR1 + Gives information about the implemented memory model and memory management support. + 0 + 32 + read-only + + + + + ID_MMFR2 + Memory Model Feature Register 2 + 0xD58 + 32 + read-only + 0 + 0xFFFFFFFF + + + WFI_STALL + Indicates the support for Wait For Interrupt (WFI) stalling + 24 + 4 + read-only + + + WFI_STALL_0 + Not supported + 0 + + + WFI_STALL_1 + Support for WFI stalling + 0x1 + + + + + + + ID_MMFR3 + Memory Model Feature Register 3 + 0xD5C + 32 + read-only + 0 + 0xFFFFFFFF + + + ID_MMFR3 + Gives information about the implemented memory model and memory management support. + 0 + 32 + read-only + + + + + ID_ISAR0 + Instruction Set Attributes Register 0 + 0xD60 + 32 + read-only + 0 + 0xFFFFFFFF + + + BITCOUNT_INSTRS + Indicates the supported Bit Counting instructions + 4 + 4 + read-only + + + BITCOUNT_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + BITCOUNT_INSTRS_1 + Adds support for the CLZ instruction + 0x1 + + + + + BITFIELD_INSTRS + Indicates the supported BitField instructions + 8 + 4 + read-only + + + BITFIELD_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + BITFIELD_INSTRS_1 + Adds support for the BFC, BFI, SBFX, and UBFX instructions + 0x1 + + + + + CMPBRANCH_INSTRS + Indicates the supported combined Compare and Branch instructions + 12 + 4 + read-only + + + CMPBRANCH_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + CMPBRANCH_INSTRS_1 + Adds support for the CBNZ and CBZ instructions + 0x1 + + + + + COPROC_INSTRS + Indicates the supported Coprocessor instructions + 16 + 4 + read-only + + + COPROC_INSTRS_0 + None supported, except for separately attributed architectures, for example the Floating-point extension + 0 + + + COPROC_INSTRS_1 + Adds support for generic CDP, LDC, MCR, MRC, and STC instructions + 0x1 + + + COPROC_INSTRS_2 + As for 1, and adds support for generic CDP2, LDC2, MCR2, MRC2, and STC2 instructions + 0x2 + + + COPROC_INSTRS_3 + As for 2, and adds support for generic MCRR and MRRC instructions + 0x3 + + + COPROC_INSTRS_4 + As for 3, and adds support for generic MCRR2 and MRRC2 instructions + 0x4 + + + + + DEBUG_INSTRS + Indicates the supported Debug instructions + 20 + 4 + read-only + + + DEBUG_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + DEBUG_INSTRS_1 + Adds support for the BKPT instruction + 0x1 + + + + + DIVIDE_INSTRS + Indicates the supported Divide instructions + 24 + 4 + read-only + + + DIVIDE_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + DIVIDE_INSTRS_1 + Adds support for the SDIV and UDIV instructions + 0x1 + + + + + + + ID_ISAR1 + Instruction Set Attributes Register 1 + 0xD64 + 32 + read-only + 0 + 0xFFFFFFFF + + + EXTEND_INSTRS + Indicates the supported Extend instructions + 12 + 4 + read-only + + + EXTEND_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + EXTEND_INSTRS_1 + Adds support for the SXTB, SXTH, UXTB, and UXTH instructions + 0x1 + + + EXTEND_INSTRS_2 + As for 1, and adds support for the SXTAB, SXTAB16, SXTAH, SXTB16, UXTAB, UXTAB16, UXTAH, and UXTB16 instructions + 0x2 + + + + + IFTHEN_INSTRS + Indicates the supported IfThen instructions + 16 + 4 + read-only + + + IFTHEN_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + IFTHEN_INSTRS_1 + Adds support for the IT instructions, and for the IT bits in the PSRs + 0x1 + + + + + IMMEDIATE_INSTRS + Indicates the support for data-processing instructions with long immediate + 20 + 4 + read-only + + + IMMEDIATE_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + IMMEDIATE_INSTRS_1 + Adds support for the ADDW, MOVW, MOVT, and SUBW instructions + 0x1 + + + + + INTERWORK_INSTRS + Indicates the supported Interworking instructions + 24 + 4 + read-only + + + INTERWORK_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + INTERWORK_INSTRS_1 + Adds support for the BX instruction, and the T bit in the PSR + 0x1 + + + INTERWORK_INSTRS_2 + As for 1, and adds support for the BLX instruction, and PC loads have BX-like behavior + 0x2 + + + INTERWORK_INSTRS_3 + ARMv7-M unused + 0x3 + + + + + + + ID_ISAR2 + Instruction Set Attributes Register 2 + 0xD68 + 32 + read-only + 0 + 0xFFFFFFFF + + + LOADSTORE_INSTRS + Indicates the supported additional load and store instructions + 0 + 4 + read-only + + + LOADSTORE_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + LOADSTORE_INSTRS_1 + Adds support for the LDRD and STRD instructions + 0x1 + + + + + MEMHINT_INSTRS + Indicates the supported Memory Hint instructions + 4 + 4 + read-only + + + MEMHINT_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + MEMHINT_INSTRS_1 + Adds support for the PLD instruction, ARMv7-M unused. + 0x1 + + + MEMHINT_INSTRS_2 + As for 1, ARMv7-M unused. + 0x2 + + + MEMHINT_INSTRS_3 + As for 1 or 2, and adds support for the PLI instruction. + 0x3 + + + + + MULTIACCESSINT_INSTRS + Indicates the support for multi-access interruptible instructions + 8 + 4 + read-only + + + MULTIACCESSINT_INSTRS_0 + None supported. This means the LDM and STM instructions are not interruptible. ARMv7-M unused. + 0 + + + MULTIACCESSINT_INSTRS_1 + LDM and STM instructions are restartable. + 0x1 + + + MULTIACCESSINT_INSTRS_2 + LDM and STM instructions are continuable. + 0x2 + + + + + MULT_INSTRS + Indicates the supported additional Multiply instructions + 12 + 4 + read-only + + + MULT_INSTRS_0 + None supported. This means only MUL is supported. ARMv7-M unused. + 0 + + + MULT_INSTRS_1 + Adds support for the MLA instruction, ARMv7-M unused. + 0x1 + + + MULT_INSTRS_2 + As for 1, and adds support for the MLS instruction. + 0x2 + + + + + MULTS_INSTRS + Indicates the supported advanced signed Multiply instructions + 16 + 4 + read-only + + + MULTS_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + MULTS_INSTRS_1 + Adds support for the SMULL and SMLAL instructions + 0x1 + + + MULTS_INSTRS_2 + As for 1, and adds support for the SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, and SMULWT instructions. + 0x2 + + + MULTS_INSTRS_3 + As for 2, and adds support for the SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX instructions. + 0x3 + + + + + MULTU_INSTRS + Indicates the supported advanced unsigned Multiply instructions + 20 + 4 + read-only + + + MULTU_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + MULTU_INSTRS_1 + Adds support for the UMULL and UMLAL instructions. + 0x1 + + + MULTU_INSTRS_2 + As for 1, and adds support for the UMAAL instruction. + 0x2 + + + + + REVERSAL_INSTRS + Indicates the supported Reversal instructions + 28 + 4 + read-only + + + REVERSAL_INSTRS_0 + None supported, ARMv7-M unused + 0 + + + REVERSAL_INSTRS_1 + Adds support for the REV, REV16, and REVSH instructions, ARMv7-M unused. + 0x1 + + + REVERSAL_INSTRS_2 + As for 1, and adds support for the RBIT instruction. + 0x2 + + + + + + + ID_ISAR3 + Instruction Set Attributes Register 3 + 0xD6C + 32 + read-only + 0 + 0xFFFFFFFF + + + SATURATE_INSTRS + Indicates the supported Saturate instructions + 0 + 4 + read-only + + + SATURATE_INSTRS_0 + None supported + 0 + + + SATURATE_INSTRS_1 + Adds support for the QADD, QDADD, QDSUB, and QSUB instructions, and for the Q bit in the PSRs. + 0x1 + + + + + SIMD_INSTRS + Indicates the supported SIMD instructions + 4 + 4 + read-only + + + SIMD_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + SIMD_INSTRS_1 + Adds support for the SSAT and USAT instructions, and for the Q bit in the PSRs. + 0x1 + + + SIMD_INSTRS_3 + As for 1, and adds support for the PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16, UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX, UXTAB16, and UXTB16 instructions. Also adds support for the GE[3:0] bits in the PSRs. + 0x3 + + + + + SVC_INSTRS + Indicates the supported SVC instructions + 8 + 4 + read-only + + + SVC_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + SVC_INSTRS_1 + Adds support for the SVC instruction. + 0x1 + + + + + SYNCHPRIM_INSTRS + Together with the ID_ISAR4[SYNCHPRIM_INSTRS_FRAC] indicates the supported Synchronization Primitives + 12 + 4 + read-only + + + TABBRANCH_INSTRS + Indicates the supported Table Branch instructions + 16 + 4 + read-only + + + TABBRANCH_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + TABBRANCH_INSTRS_1 + Adds support for the TBB and TBH instructions. + 0x1 + + + + + THUMBCOPY_INSTRS + Indicates the supported non flag-setting MOV instructions + 20 + 4 + read-only + + + THUMBCOPY_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + THUMBCOPY_INSTRS_1 + Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register. + 0x1 + + + + + TRUENOP_INSTRS + Indicates the supported non flag-setting MOV instructions + 24 + 4 + read-only + + + TRUENOP_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + TRUENOP_INSTRS_1 + Adds support for encoding T1 of the MOV (register) instruction copying from a low register to a low register. + 0x1 + + + + + + + ID_ISAR4 + Instruction Set Attributes Register 4 + 0xD70 + 32 + read-only + 0 + 0xFFFFFFFF + + + UNPRIV_INSTRS + Indicates the supported unprivileged instructions. These are the instruction variants indicated by a T suffix. + 0 + 4 + read-only + + + UNPRIV_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + UNPRIV_INSTRS_1 + Adds support for the LDRBT, LDRT, STRBT, and STRT instructions. + 0x1 + + + UNPRIV_INSTRS_2 + As for 1, and adds support for the LDRHT, LDRSBT, LDRSHT, and STRHT instructions. + 0x2 + + + + + WITHSHIFTS_INSTRS + Indicates the support for instructions with shifts + 4 + 4 + read-only + + + WITHSHIFTS_INSTRS_0 + Nonzero shifts supported only in MOV and shift instructions. + 0 + + + WITHSHIFTS_INSTRS_1 + Adds support for shifts of loads and stores over the range LSL 0-3. + 0x1 + + + WITHSHIFTS_INSTRS_3 + As for 1, and adds support for other constant shift options, on loads, stores, and other instructions. + 0x3 + + + WITHSHIFTS_INSTRS_4 + ARMv7-M unused. + 0x4 + + + + + WRITEBACK_INSTRS + Indicates the support for Writeback addressing modes + 8 + 4 + read-only + + + WRITEBACK_INSTRS_0 + Basic support. Only the LDM, STM, PUSH, and POP instructions support writeback addressing modes. ARMv7-M unused. + 0 + + + WRITEBACK_INSTRS_1 + Adds support for all of the writeback addressing modes defined in the ARMv7-M architecture. + 0x1 + + + + + BARRIER_INSTRS + Indicates the supported Barrier instructions + 16 + 4 + read-only + + + BARRIER_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + BARRIER_INSTRS_1 + Adds support for the DMB, DSB, and ISB barrier instructions. + 0x1 + + + + + SYNCHPRIM_INSTRS_FRAC + Together with the ID_ISAR3[SYNCHPRIM_INSTRS] indicates the supported Synchronization Primitives + 20 + 4 + read-only + + + PSR_M_INSTRS + Indicates the supported M profile instructions to modify the PSRs + 24 + 4 + read-only + + + PSR_M_INSTRS_0 + None supported, ARMv7-M unused. + 0 + + + PSR_M_INSTRS_1 + Adds support for the M-profile forms of the CPS, MRS, and MSR instructions, to access the PSRs. + 0x1 + + + + + + + CLIDR + Cache Level ID register + 0xD78 + 32 + read-only + 0 + 0xFFFFFFFF + + + CL1 + Indicate the type of cache implemented at level 1. + 0 + 3 + read-only + + + CL1_0 + No cache + 0 + + + CL1_1 + Instruction cache only + 0x1 + + + CL1_2 + Data cache only + 0x2 + + + CL1_3 + Separate instruction and data caches + 0x3 + + + CL1_4 + Unified cache + 0x4 + + + + + CL2 + Indicate the type of cache implemented at level 2. + 3 + 3 + read-only + + + CL2_0 + No cache + 0 + + + CL2_1 + Instruction cache only + 0x1 + + + CL2_2 + Data cache only + 0x2 + + + CL2_3 + Separate instruction and data caches + 0x3 + + + CL2_4 + Unified cache + 0x4 + + + + + CL3 + Indicate the type of cache implemented at level 3. + 6 + 3 + read-only + + + CL3_0 + No cache + 0 + + + CL3_1 + Instruction cache only + 0x1 + + + CL3_2 + Data cache only + 0x2 + + + CL3_3 + Separate instruction and data caches + 0x3 + + + CL3_4 + Unified cache + 0x4 + + + + + CL4 + Indicate the type of cache implemented at level 4. + 9 + 3 + read-only + + + CL4_0 + No cache + 0 + + + CL4_1 + Instruction cache only + 0x1 + + + CL4_2 + Data cache only + 0x2 + + + CL4_3 + Separate instruction and data caches + 0x3 + + + CL4_4 + Unified cache + 0x4 + + + + + CL5 + Indicate the type of cache implemented at level 5. + 12 + 3 + read-only + + + CL5_0 + No cache + 0 + + + CL5_1 + Instruction cache only + 0x1 + + + CL5_2 + Data cache only + 0x2 + + + CL5_3 + Separate instruction and data caches + 0x3 + + + CL5_4 + Unified cache + 0x4 + + + + + CL6 + Indicate the type of cache implemented at level 6. + 15 + 3 + read-only + + + CL6_0 + No cache + 0 + + + CL6_1 + Instruction cache only + 0x1 + + + CL6_2 + Data cache only + 0x2 + + + CL6_3 + Separate instruction and data caches + 0x3 + + + CL6_4 + Unified cache + 0x4 + + + + + CL7 + Indicate the type of cache implemented at level 7. + 18 + 3 + read-only + + + CL7_0 + No cache + 0 + + + CL7_1 + Instruction cache only + 0x1 + + + CL7_2 + Data cache only + 0x2 + + + CL7_3 + Separate instruction and data caches + 0x3 + + + CL7_4 + Unified cache + 0x4 + + + + + LOUIS + Level of Unification Inner Shareable for the cache hierarchy. This field is RAZ. + 21 + 3 + read-only + + + LOUIS_0 + 0 + 0 + + + LOUIS_1 + 1 + 0x1 + + + LOUIS_2 + 2 + 0x2 + + + LOUIS_3 + 3 + 0x3 + + + LOUIS_4 + 4 + 0x4 + + + LOUIS_5 + 5 + 0x5 + + + LOUIS_6 + 6 + 0x6 + + + LOUIS_7 + 7 + 0x7 + + + + + LOC + Level of Coherency for the cache hierarchy + 24 + 3 + read-only + + + LOC_0 + 0 + 0 + + + LOC_1 + 1 + 0x1 + + + LOC_2 + 2 + 0x2 + + + LOC_3 + 3 + 0x3 + + + LOC_4 + 4 + 0x4 + + + LOC_5 + 5 + 0x5 + + + LOC_6 + 6 + 0x6 + + + LOC_7 + 7 + 0x7 + + + + + LOU + Level of Unification for the cache hierarchy + 27 + 3 + read-only + + + LOU_0 + 0 + 0 + + + LOU_1 + 1 + 0x1 + + + LOU_2 + 2 + 0x2 + + + LOU_3 + 3 + 0x3 + + + LOU_4 + 4 + 0x4 + + + LOU_5 + 5 + 0x5 + + + LOU_6 + 6 + 0x6 + + + LOU_7 + 7 + 0x7 + + + + + + + CTR + Cache Type register + 0xD7C + 32 + read-only + 0x8000C000 + 0xFFFFFFFF + + + IMINLINE + Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor. + 0 + 4 + read-only + + + DMINLINE + Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor. + 16 + 4 + read-only + + + ERG + Exclusives Reservation Granule. The maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions, encoded as Log2 of the number of words. + 20 + 4 + read-only + + + CWG + Cache Write-back Granule. The maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified, encoded as Log2 of the number of words. + 24 + 4 + read-only + + + FORMAT + Indicates the implemented CTR format. + 29 + 3 + read-only + + + FORMAT_4 + ARMv7 format. + 0x4 + + + + + + + CCSIDR + Cache Size ID Register + 0xD80 + 32 + read-only + 0 + 0xFFFFFFFF + + + LINESIZE + (Log2(Number of words in cache line)) - 2. + 0 + 3 + read-only + + + LINESIZE_0 + The line length of 4 words. + 0 + + + LINESIZE_1 + The line length of 8 words. + 0x1 + + + LINESIZE_2 + The line length of 16 words. + 0x2 + + + LINESIZE_3 + The line length of 32 words. + 0x3 + + + LINESIZE_4 + The line length of 64 words. + 0x4 + + + LINESIZE_5 + The line length of 128 words. + 0x5 + + + LINESIZE_6 + The line length of 256 words. + 0x6 + + + LINESIZE_7 + The line length of 512 words. + 0x7 + + + + + ASSOCIATIVITY + (Associativity of cache) - 1, therefore a value of 0 indicates an associativity of 1. The associativity does not have to be a power of 2. + 3 + 10 + read-only + + + NUMSETS + (Number of sets in cache) - 1, therefore a value of 0 indicates 1 set in the cache. The number of sets does not have to be a power of 2. + 13 + 15 + read-only + + + WA + Indicates whether the cache level supports write-allocation + 28 + 1 + read-only + + + WA_0 + Feature not supported + 0 + + + WA_1 + Feature supported + 0x1 + + + + + RA + Indicates whether the cache level supports read-allocation + 29 + 1 + read-only + + + RA_0 + Feature not supported + 0 + + + RA_1 + Feature supported + 0x1 + + + + + WB + Indicates whether the cache level supports write-back + 30 + 1 + read-only + + + WB_0 + Feature not supported + 0 + + + WB_1 + Feature supported + 0x1 + + + + + WT + Indicates whether the cache level supports write-through + 31 + 1 + read-only + + + WT_0 + Feature not supported + 0 + + + WT_1 + Feature supported + 0x1 + + + + + + + CSSELR + Cache Size Selection Register + 0xD84 + 32 + read-write + 0 + 0xFFFFFFFF + + + IND + Instruction not data bit + 0 + 1 + read-write + + + IND_0 + Data or unified cache. + 0 + + + IND_1 + Instruction cache. + 0x1 + + + + + LEVEL + Cache level of required cache + 1 + 3 + read-write + + + LEVEL_0 + Level 1 cache. + 0 + + + LEVEL_1 + Level 2 cache. + 0x1 + + + LEVEL_2 + Level 3 cache. + 0x2 + + + LEVEL_3 + Level 4 cache. + 0x3 + + + LEVEL_4 + Level 5 cache. + 0x4 + + + LEVEL_5 + Level 6 cache. + 0x5 + + + LEVEL_6 + Level 7 cache. + 0x6 + + + + + + + CPACR + Coprocessor Access Control Register + 0xD88 + 32 + read-write + 0 + 0xFFFFFFFF + + + CP0 + Access privileges for coprocessor 0. + 0 + 2 + read-write + + + CP0_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP0_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP0_3 + Full access. + 0x3 + + + + + CP1 + Access privileges for coprocessor 1. + 2 + 2 + read-write + + + CP1_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP1_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP1_3 + Full access. + 0x3 + + + + + CP2 + Access privileges for coprocessor 2. + 4 + 2 + read-write + + + CP2_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP2_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP2_3 + Full access. + 0x3 + + + + + CP3 + Access privileges for coprocessor 3. + 6 + 2 + read-write + + + CP3_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP3_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP3_3 + Full access. + 0x3 + + + + + CP4 + Access privileges for coprocessor 4. + 8 + 2 + read-write + + + CP4_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP4_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP4_3 + Full access. + 0x3 + + + + + CP5 + Access privileges for coprocessor 5. + 10 + 2 + read-write + + + CP5_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP5_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP5_3 + Full access. + 0x3 + + + + + CP6 + Access privileges for coprocessor 6. + 12 + 2 + read-write + + + CP6_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP6_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP6_3 + Full access. + 0x3 + + + + + CP7 + Access privileges for coprocessor 7. + 14 + 2 + read-write + + + CP7_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP7_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP7_3 + Full access. + 0x3 + + + + + CP10 + Access privileges for coprocessor 10. + 20 + 2 + read-write + + + CP10_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP10_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP10_3 + Full access. + 0x3 + + + + + CP11 + Access privileges for coprocessor 11. + 22 + 2 + read-write + + + CP11_0 + Access denied. Any attempted access generates a NOCP UsageFault. + 0 + + + CP11_1 + Privileged access only. An unprivileged access generates a NOCP UsageFault. + 0x1 + + + CP11_3 + Full access. + 0x3 + + + + + + + STIR + Instruction cache invalidate all to Point of Unification (PoU) + 0xF00 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTID + Indicates the interrupt to be triggered + 0 + 9 + write-only + + + + + ICIALLU + Instruction cache invalidate all to Point of Unification (PoU) + 0xF50 + 32 + write-only + 0 + 0xFFFFFFFF + + + ICIALLU + I-cache invalidate all to PoU + 0 + 32 + write-only + + + + + ICIMVAU + Instruction cache invalidate by address to PoU + 0xF58 + 32 + write-only + 0 + 0xFFFFFFFF + + + ICIMVAU + I-cache invalidate by MVA to PoU + 0 + 32 + write-only + + + + + DCIMVAC + Data cache invalidate by address to Point of Coherency (PoC) + 0xF5C + 32 + write-only + 0 + 0xFFFFFFFF + + + DCIMVAC + D-cache invalidate by MVA to PoC + 0 + 32 + write-only + + + + + DCISW + Data cache invalidate by set/way + 0xF60 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCISW + D-cache invalidate by set-way + 0 + 32 + write-only + + + + + DCCMVAU + Data cache by address to PoU + 0xF64 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCMVAU + D-cache clean by MVA to PoU + 0 + 32 + write-only + + + + + DCCMVAC + Data cache clean by address to PoC + 0xF68 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCMVAC + D-cache clean by MVA to PoC + 0 + 32 + write-only + + + + + DCCSW + Data cache clean by set/way + 0xF6C + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCSW + D-cache clean by set-way + 0 + 32 + write-only + + + + + DCCIMVAC + Data cache clean and invalidate by address to PoC + 0xF70 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCIMVAC + D-cache clean and invalidate by MVA to PoC + 0 + 32 + write-only + + + + + DCCISW + Data cache clean and invalidate by set/way + 0xF74 + 32 + write-only + 0 + 0xFFFFFFFF + + + DCCISW + D-cache clean and invalidate by set-way + 0 + 32 + write-only + + + + + CM7_ITCMCR + Instruction Tightly-Coupled Memory Control Register + 0xF90 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + TCM enable. When a TCM is disabled all accesses are made to the AXIM interface. + 0 + 1 + read-write + + + EN_0 + TCM disabled. + 0 + + + EN_1 + TCM enabled. + 0x1 + + + + + RMW + Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence. + 1 + 1 + read-write + + + RMW_0 + RMW disabled. + 0 + + + RMW_1 + RMW enabled. + 0x1 + + + + + RETEN + Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access. + 2 + 1 + read-write + + + RETEN_0 + Retry phase disabled. + 0 + + + RETEN_1 + Retry phase enabled. + 0x1 + + + + + SZ + TCM size. Indicates the size of the relevant TCM. + 3 + 4 + read-only + + + SZ_0 + No TCM implemented. + 0 + + + SZ_3 + 4KB. + 0x3 + + + SZ_4 + 8KB. + 0x4 + + + SZ_5 + 16KB. + 0x5 + + + SZ_6 + 32KB. + 0x6 + + + SZ_7 + 64KB. + 0x7 + + + SZ_8 + 128KB. + 0x8 + + + SZ_9 + 256KB. + 0x9 + + + SZ_10 + 512KB. + 0xA + + + SZ_11 + 1MB. + 0xB + + + SZ_12 + 2MB. + 0xC + + + SZ_13 + 4MB. + 0xD + + + SZ_14 + 8MB. + 0xE + + + SZ_15 + 16MB. + 0xF + + + + + + + CM7_DTCMCR + Data Tightly-Coupled Memory Control Register + 0xF94 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + TCM enable. When a TCM is disabled all accesses are made to the AXIM interface. + 0 + 1 + read-write + + + EN_0 + TCM disabled. + 0 + + + EN_1 + TCM enabled. + 0x1 + + + + + RMW + Read-Modify-Write (RMW) enable. Indicates that all writes to TCM, that are not the full width of the TCM RAM, use a RMW sequence. + 1 + 1 + read-write + + + RMW_0 + RMW disabled. + 0 + + + RMW_1 + RMW enabled. + 0x1 + + + + + RETEN + Retry phase enable. When enabled the processor guarantees to honor the retry output on the corresponding TCM interface, re-executing the instruction which carried out the TCM access. + 2 + 1 + read-write + + + RETEN_0 + Retry phase disabled. + 0 + + + RETEN_1 + Retry phase enabled. + 0x1 + + + + + SZ + TCM size. Indicates the size of the relevant TCM. + 3 + 4 + read-only + + + SZ_0 + No TCM implemented. + 0 + + + SZ_3 + 4KB. + 0x3 + + + SZ_4 + 8KB. + 0x4 + + + SZ_5 + 16KB. + 0x5 + + + SZ_6 + 32KB. + 0x6 + + + SZ_7 + 64KB. + 0x7 + + + SZ_8 + 128KB. + 0x8 + + + SZ_9 + 256KB. + 0x9 + + + SZ_10 + 512KB. + 0xA + + + SZ_11 + 1MB. + 0xB + + + SZ_12 + 2MB. + 0xC + + + SZ_13 + 4MB. + 0xD + + + SZ_14 + 8MB. + 0xE + + + SZ_15 + 16MB. + 0xF + + + + + + + CM7_AHBPCR + AHBP Control Register + 0xF98 + 32 + read-write + 0 + 0xFFFFFFFF + + + EN + AHBP enable. + 0 + 1 + read-write + + + EN_0 + AHBP disabled. When disabled all accesses are made to the AXIM interface. + 0 + + + EN_1 + AHBP enabled. + 0x1 + + + + + SZ + AHBP size. + 1 + 3 + read-only + + + SZ_0 + 0MB. AHBP disabled. + 0 + + + SZ_1 + 64MB. + 0x1 + + + SZ_2 + 128MB. + 0x2 + + + SZ_3 + 256MB. + 0x3 + + + SZ_4 + 512MB. + 0x4 + + + + + + + CM7_CACR + L1 Cache Control Register + 0xF9C + 32 + read-write + 0 + 0xFFFFFFFF + + + SIWT + Shared cacheable-is-WT for data cache. Enables limited cache coherency usage. + 0 + 1 + read-write + + + SIWT_0 + Normal Cacheable Shared locations are treated as being Non-cacheable. Default mode of operation for Shared memory. + 0 + + + SIWT_1 + Normal Cacheable shared locations are treated as Write-Through. + 0x1 + + + + + ECCDIS + Enables ECC in the instruction and data cache. + 1 + 1 + read-write + + + ECCDIS_0 + Enables ECC in the instruction and data cache. + 0 + + + ECCDIS_1 + Disables ECC in the instruction and data cache. + 0x1 + + + + + FORCEWT + Enables Force Write-Through in the data cache. + 2 + 1 + read-write + + + FORCEWT_0 + Disables Force Write-Through. + 0 + + + FORCEWT_1 + Enables Force Write-Through. All Cacheable memory regions are treated as Write-Through. + 0x1 + + + + + + + CM7_AHBSCR + AHB Slave Control Register + 0xFA0 + 32 + read-write + 0 + 0xFFFFFFFF + + + CTL + AHBS prioritization control. + 0 + 2 + read-write + + + CTL_0 + AHBS access priority demoted. This is the reset value. + 0 + + + CTL_1 + Software access priority demoted. + 0x1 + + + CTL_2 + AHBS access priority demoted by initializing the fairness counter to the CM7_AHBSCR[INITCOUNT] value when the software execution priority is higher than or equal to the threshold level programed in CM7_AHBSCR[TPRI]. + 0x2 + + + CTL_3 + AHBSPRI signal has control of access priority. + 0x3 + + + + + TPRI + Threshold execution priority for AHBS traffic demotion. + 2 + 9 + read-write + + + INITCOUNT + Fairness counter initialization value. + 11 + 5 + read-write + + + + + CM7_ABFSR + Auxiliary Bus Fault Status Register + 0xFA8 + 32 + read-write + 0 + 0xFFFFFFFF + + + ITCM + Asynchronous fault on ITCM interface. + 0 + 1 + read-write + + + DTCM + Asynchronous fault on DTCM interface. + 1 + 1 + read-write + + + AHBP + Asynchronous fault on AHBP interface. + 2 + 1 + read-write + + + AXIM + Asynchronous fault on AXIM interface. + 3 + 1 + read-write + + + EPPB + Asynchronous fault on EPPB interface. + 4 + 1 + read-write + + + AXIMTYPE + Indicates the type of fault on the AXIM interface. Only valid when AXIM is 1. + 8 + 2 + read-write + + + AXIMTYPE_0 + OKAY. + 0 + + + AXIMTYPE_1 + EXOKAY. + 0x1 + + + AXIMTYPE_2 + SLVERR. + 0x2 + + + AXIMTYPE_3 + DECERR. + 0x3 + + + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + 0xE000E100 + + 0 + 0xE04 + registers + + + DMA0_DMA16 + 0 + + + DMA1_DMA17 + 1 + + + DMA2_DMA18 + 2 + + + DMA3_DMA19 + 3 + + + DMA4_DMA20 + 4 + + + DMA5_DMA21 + 5 + + + DMA6_DMA22 + 6 + + + DMA7_DMA23 + 7 + + + DMA8_DMA24 + 8 + + + DMA9_DMA25 + 9 + + + DMA10_DMA26 + 10 + + + DMA11_DMA27 + 11 + + + DMA12_DMA28 + 12 + + + DMA13_DMA29 + 13 + + + DMA14_DMA30 + 14 + + + DMA15_DMA31 + 15 + + + DMA_ERROR + 16 + + + CTI0_ERROR + 17 + + + CTI1_ERROR + 18 + + + CORE + 19 + + + LPUART1 + 20 + + + LPUART2 + 21 + + + LPUART3 + 22 + + + LPUART4 + 23 + + + LPUART5 + 24 + + + LPUART6 + 25 + + + LPUART7 + 26 + + + LPUART8 + 27 + + + LPI2C1 + 28 + + + LPI2C2 + 29 + + + LPI2C3 + 30 + + + LPI2C4 + 31 + + + LPSPI1 + 32 + + + LPSPI2 + 33 + + + LPSPI3 + 34 + + + LPSPI4 + 35 + + + CAN1 + 36 + + + CAN2 + 37 + + + FLEXRAM + 38 + + + KPP + 39 + + + TSC_DIG + 40 + + + GPR_IRQ + 41 + + + WDOG2 + 45 + + + SNVS_HP_WRAPPER + 46 + + + SNVS_HP_WRAPPER_TZ + 47 + + + SNVS_LP_WRAPPER + 48 + + + CSU + 49 + + + DCP + 50 + + + DCP_VMI + 51 + + + Reserved68 + 52 + + + TRNG + 53 + + + SJC + 54 + + + BEE + 55 + + + SAI1 + 56 + + + SAI2 + 57 + + + SAI3_RX + 58 + + + SAI3_TX + 59 + + + SPDIF + 60 + + + PMU_EVENT + 61 + + + Reserved78 + 62 + + + TEMP_LOW_HIGH + 63 + + + TEMP_PANIC + 64 + + + USB_PHY1 + 65 + + + USB_PHY2 + 66 + + + ADC1 + 67 + + + ADC2 + 68 + + + DCDC + 69 + + + Reserved86 + 70 + + + Reserved87 + 71 + + + GPIO1_INT0 + 72 + + + GPIO1_INT1 + 73 + + + GPIO1_INT2 + 74 + + + GPIO1_INT3 + 75 + + + GPIO1_INT4 + 76 + + + GPIO1_INT5 + 77 + + + GPIO1_INT6 + 78 + + + GPIO1_INT7 + 79 + + + GPIO1_Combined_0_15 + 80 + + + GPIO1_Combined_16_31 + 81 + + + GPIO2_Combined_0_15 + 82 + + + GPIO2_Combined_16_31 + 83 + + + GPIO3_Combined_0_15 + 84 + + + GPIO3_Combined_16_31 + 85 + + + GPIO4_Combined_0_15 + 86 + + + GPIO4_Combined_16_31 + 87 + + + GPIO5_Combined_0_15 + 88 + + + GPIO5_Combined_16_31 + 89 + + + FLEXIO1 + 90 + + + FLEXIO2 + 91 + + + WDOG1 + 92 + + + RTWDOG + 93 + + + EWM + 94 + + + CCM_1 + 95 + + + CCM_2 + 96 + + + GPC + 97 + + + SRC + 98 + + + Reserved115 + 99 + + + GPT1 + 100 + + + GPT2 + 101 + + + PWM1_0 + 102 + + + PWM1_1 + 103 + + + PWM1_2 + 104 + + + PWM1_3 + 105 + + + PWM1_FAULT + 106 + + + FLEXSPI2 + 107 + + + SEMC + 109 + + + USDHC1 + 110 + + + USDHC2 + 111 + + + USB_OTG2 + 112 + + + USB_OTG1 + 113 + + + ENET + 114 + + + ENET_1588_Timer + 115 + + + XBAR1_IRQ_0_1 + 116 + + + XBAR1_IRQ_2_3 + 117 + + + ADC_ETC_IRQ0 + 118 + + + ADC_ETC_IRQ1 + 119 + + + ADC_ETC_IRQ2 + 120 + + + ADC_ETC_ERROR_IRQ + 121 + + + PIT + 122 + + + ACMP1 + 123 + + + ACMP2 + 124 + + + ACMP3 + 125 + + + ACMP4 + 126 + + + Reserved143 + 127 + + + Reserved144 + 128 + + + ENC1 + 129 + + + ENC2 + 130 + + + ENC3 + 131 + + + ENC4 + 132 + + + TMR1 + 133 + + + TMR2 + 134 + + + TMR3 + 135 + + + TMR4 + 136 + + + PWM2_0 + 137 + + + PWM2_1 + 138 + + + PWM2_2 + 139 + + + PWM2_3 + 140 + + + PWM2_FAULT + 141 + + + PWM3_0 + 142 + + + PWM3_1 + 143 + + + PWM3_2 + 144 + + + PWM3_3 + 145 + + + PWM3_FAULT + 146 + + + PWM4_0 + 147 + + + PWM4_1 + 148 + + + PWM4_2 + 149 + + + PWM4_3 + 150 + + + PWM4_FAULT + 151 + + + ENET2 + 152 + + + ENET2_1588_Timer + 153 + + + CAN3 + 154 + + + Reserved171 + 155 + + + FLEXIO3 + 156 + + + GPIO6_7_8_9 + 157 + + + + NVICISER0 + Interrupt Set Enable Register n + 0 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISER1 + Interrupt Set Enable Register n + 0x4 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISER2 + Interrupt Set Enable Register n + 0x8 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISER3 + Interrupt Set Enable Register n + 0xC + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISER4 + Interrupt Set Enable Register n + 0x10 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETENA + Interrupt set enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER0 + Interrupt Clear Enable Register n + 0x80 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER1 + Interrupt Clear Enable Register n + 0x84 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER2 + Interrupt Clear Enable Register n + 0x88 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER3 + Interrupt Clear Enable Register n + 0x8C + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICICER4 + Interrupt Clear Enable Register n + 0x90 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRENA + Interrupt clear-enable bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR0 + Interrupt Set Pending Register n + 0x100 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR1 + Interrupt Set Pending Register n + 0x104 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR2 + Interrupt Set Pending Register n + 0x108 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR3 + Interrupt Set Pending Register n + 0x10C + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICISPR4 + Interrupt Set Pending Register n + 0x110 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETPEND + Interrupt set-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR0 + Interrupt Clear Pending Register n + 0x180 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR1 + Interrupt Clear Pending Register n + 0x184 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR2 + Interrupt Clear Pending Register n + 0x188 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR3 + Interrupt Clear Pending Register n + 0x18C + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICICPR4 + Interrupt Clear Pending Register n + 0x190 + 32 + read-write + 0 + 0xFFFFFFFF + + + CLRPEND + Interrupt clear-pending bits + 0 + 32 + read-write + oneToClear + + + + + NVICIABR0 + Interrupt Active bit Register n + 0x200 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR1 + Interrupt Active bit Register n + 0x204 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR2 + Interrupt Active bit Register n + 0x208 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR3 + Interrupt Active bit Register n + 0x20C + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIABR4 + Interrupt Active bit Register n + 0x210 + 32 + read-write + 0 + 0xFFFFFFFF + + + ACTIVE + Interrupt active flags + 0 + 32 + read-write + + + + + NVICIP0 + Interrupt Priority Register 0 + 0x300 + 8 + read-write + 0 + 0xFF + + + PRI0 + Priority of the INT_DMA0_DMA16 interrupt 0 + 4 + 4 + read-write + + + + + NVICIP1 + Interrupt Priority Register 1 + 0x301 + 8 + read-write + 0 + 0xFF + + + PRI1 + Priority of the INT_DMA1_DMA17 interrupt 1 + 4 + 4 + read-write + + + + + NVICIP2 + Interrupt Priority Register 2 + 0x302 + 8 + read-write + 0 + 0xFF + + + PRI2 + Priority of the INT_DMA2_DMA18 interrupt 2 + 4 + 4 + read-write + + + + + NVICIP3 + Interrupt Priority Register 3 + 0x303 + 8 + read-write + 0 + 0xFF + + + PRI3 + Priority of the INT_DMA3_DMA19 interrupt 3 + 4 + 4 + read-write + + + + + NVICIP4 + Interrupt Priority Register 4 + 0x304 + 8 + read-write + 0 + 0xFF + + + PRI4 + Priority of the INT_DMA4_DMA20 interrupt 4 + 4 + 4 + read-write + + + + + NVICIP5 + Interrupt Priority Register 5 + 0x305 + 8 + read-write + 0 + 0xFF + + + PRI5 + Priority of the INT_DMA5_DMA21 interrupt 5 + 4 + 4 + read-write + + + + + NVICIP6 + Interrupt Priority Register 6 + 0x306 + 8 + read-write + 0 + 0xFF + + + PRI6 + Priority of the INT_DMA6_DMA22 interrupt 6 + 4 + 4 + read-write + + + + + NVICIP7 + Interrupt Priority Register 7 + 0x307 + 8 + read-write + 0 + 0xFF + + + PRI7 + Priority of the INT_DMA7_DMA23 interrupt 7 + 4 + 4 + read-write + + + + + NVICIP8 + Interrupt Priority Register 8 + 0x308 + 8 + read-write + 0 + 0xFF + + + PRI8 + Priority of the INT_DMA8_DMA24 interrupt 8 + 4 + 4 + read-write + + + + + NVICIP9 + Interrupt Priority Register 9 + 0x309 + 8 + read-write + 0 + 0xFF + + + PRI9 + Priority of the INT_DMA9_DMA25 interrupt 9 + 4 + 4 + read-write + + + + + NVICIP10 + Interrupt Priority Register 10 + 0x30A + 8 + read-write + 0 + 0xFF + + + PRI10 + Priority of the INT_DMA10_DMA26 interrupt 10 + 4 + 4 + read-write + + + + + NVICIP11 + Interrupt Priority Register 11 + 0x30B + 8 + read-write + 0 + 0xFF + + + PRI11 + Priority of the INT_DMA11_DMA27 interrupt 11 + 4 + 4 + read-write + + + + + NVICIP12 + Interrupt Priority Register 12 + 0x30C + 8 + read-write + 0 + 0xFF + + + PRI12 + Priority of the INT_DMA12_DMA28 interrupt 12 + 4 + 4 + read-write + + + + + NVICIP13 + Interrupt Priority Register 13 + 0x30D + 8 + read-write + 0 + 0xFF + + + PRI13 + Priority of the INT_DMA13_DMA29 interrupt 13 + 4 + 4 + read-write + + + + + NVICIP14 + Interrupt Priority Register 14 + 0x30E + 8 + read-write + 0 + 0xFF + + + PRI14 + Priority of the INT_DMA14_DMA30 interrupt 14 + 4 + 4 + read-write + + + + + NVICIP15 + Interrupt Priority Register 15 + 0x30F + 8 + read-write + 0 + 0xFF + + + PRI15 + Priority of the INT_DMA15_DMA31 interrupt 15 + 4 + 4 + read-write + + + + + NVICIP16 + Interrupt Priority Register 16 + 0x310 + 8 + read-write + 0 + 0xFF + + + PRI16 + Priority of the INT_DMA_ERROR interrupt 16 + 4 + 4 + read-write + + + + + NVICIP17 + Interrupt Priority Register 17 + 0x311 + 8 + read-write + 0 + 0xFF + + + PRI17 + Priority of the INT_CTI0_ERROR interrupt 17 + 4 + 4 + read-write + + + + + NVICIP18 + Interrupt Priority Register 18 + 0x312 + 8 + read-write + 0 + 0xFF + + + PRI18 + Priority of the INT_CTI1_ERROR interrupt 18 + 4 + 4 + read-write + + + + + NVICIP19 + Interrupt Priority Register 19 + 0x313 + 8 + read-write + 0 + 0xFF + + + PRI19 + Priority of the INT_CORE interrupt 19 + 4 + 4 + read-write + + + + + NVICIP20 + Interrupt Priority Register 20 + 0x314 + 8 + read-write + 0 + 0xFF + + + PRI20 + Priority of the INT_LPUART1 interrupt 20 + 4 + 4 + read-write + + + + + NVICIP21 + Interrupt Priority Register 21 + 0x315 + 8 + read-write + 0 + 0xFF + + + PRI21 + Priority of the INT_LPUART2 interrupt 21 + 4 + 4 + read-write + + + + + NVICIP22 + Interrupt Priority Register 22 + 0x316 + 8 + read-write + 0 + 0xFF + + + PRI22 + Priority of the INT_LPUART3 interrupt 22 + 4 + 4 + read-write + + + + + NVICIP23 + Interrupt Priority Register 23 + 0x317 + 8 + read-write + 0 + 0xFF + + + PRI23 + Priority of the INT_LPUART4 interrupt 23 + 4 + 4 + read-write + + + + + NVICIP24 + Interrupt Priority Register 24 + 0x318 + 8 + read-write + 0 + 0xFF + + + PRI24 + Priority of the INT_LPUART5 interrupt 24 + 4 + 4 + read-write + + + + + NVICIP25 + Interrupt Priority Register 25 + 0x319 + 8 + read-write + 0 + 0xFF + + + PRI25 + Priority of the INT_LPUART6 interrupt 25 + 4 + 4 + read-write + + + + + NVICIP26 + Interrupt Priority Register 26 + 0x31A + 8 + read-write + 0 + 0xFF + + + PRI26 + Priority of the INT_LPUART7 interrupt 26 + 4 + 4 + read-write + + + + + NVICIP27 + Interrupt Priority Register 27 + 0x31B + 8 + read-write + 0 + 0xFF + + + PRI27 + Priority of the INT_LPUART8 interrupt 27 + 4 + 4 + read-write + + + + + NVICIP28 + Interrupt Priority Register 28 + 0x31C + 8 + read-write + 0 + 0xFF + + + PRI28 + Priority of the INT_LPI2C1 interrupt 28 + 4 + 4 + read-write + + + + + NVICIP29 + Interrupt Priority Register 29 + 0x31D + 8 + read-write + 0 + 0xFF + + + PRI29 + Priority of the INT_LPI2C2 interrupt 29 + 4 + 4 + read-write + + + + + NVICIP30 + Interrupt Priority Register 30 + 0x31E + 8 + read-write + 0 + 0xFF + + + PRI30 + Priority of the INT_LPI2C3 interrupt 30 + 4 + 4 + read-write + + + + + NVICIP31 + Interrupt Priority Register 31 + 0x31F + 8 + read-write + 0 + 0xFF + + + PRI31 + Priority of the INT_LPI2C4 interrupt 31 + 4 + 4 + read-write + + + + + NVICIP32 + Interrupt Priority Register 32 + 0x320 + 8 + read-write + 0 + 0xFF + + + PRI32 + Priority of the INT_LPSPI1 interrupt 32 + 4 + 4 + read-write + + + + + NVICIP33 + Interrupt Priority Register 33 + 0x321 + 8 + read-write + 0 + 0xFF + + + PRI33 + Priority of the INT_LPSPI2 interrupt 33 + 4 + 4 + read-write + + + + + NVICIP34 + Interrupt Priority Register 34 + 0x322 + 8 + read-write + 0 + 0xFF + + + PRI34 + Priority of the INT_LPSPI3 interrupt 34 + 4 + 4 + read-write + + + + + NVICIP35 + Interrupt Priority Register 35 + 0x323 + 8 + read-write + 0 + 0xFF + + + PRI35 + Priority of the INT_LPSPI4 interrupt 35 + 4 + 4 + read-write + + + + + NVICIP36 + Interrupt Priority Register 36 + 0x324 + 8 + read-write + 0 + 0xFF + + + PRI36 + Priority of the INT_CAN1 interrupt 36 + 4 + 4 + read-write + + + + + NVICIP37 + Interrupt Priority Register 37 + 0x325 + 8 + read-write + 0 + 0xFF + + + PRI37 + Priority of the INT_CAN2 interrupt 37 + 4 + 4 + read-write + + + + + NVICIP38 + Interrupt Priority Register 38 + 0x326 + 8 + read-write + 0 + 0xFF + + + PRI38 + Priority of the INT_FLEXRAM interrupt 38 + 4 + 4 + read-write + + + + + NVICIP39 + Interrupt Priority Register 39 + 0x327 + 8 + read-write + 0 + 0xFF + + + PRI39 + Priority of the INT_KPP interrupt 39 + 4 + 4 + read-write + + + + + NVICIP40 + Interrupt Priority Register 40 + 0x328 + 8 + read-write + 0 + 0xFF + + + PRI40 + Priority of the INT_TSC_DIG interrupt 40 + 4 + 4 + read-write + + + + + NVICIP41 + Interrupt Priority Register 41 + 0x329 + 8 + read-write + 0 + 0xFF + + + PRI41 + Priority of the INT_GPR_IRQ interrupt 41 + 4 + 4 + read-write + + + + + NVICIP42 + Interrupt Priority Register 42 + 0x32A + 8 + read-write + 0 + 0xFF + + + PRI42 + Priority of interrupt 42 + 4 + 4 + read-write + + + + + NVICIP43 + Interrupt Priority Register 43 + 0x32B + 8 + read-write + 0 + 0xFF + + + PRI43 + Priority of interrupt 43 + 4 + 4 + read-write + + + + + NVICIP44 + Interrupt Priority Register 44 + 0x32C + 8 + read-write + 0 + 0xFF + + + PRI44 + Priority of interrupt 44 + 4 + 4 + read-write + + + + + NVICIP45 + Interrupt Priority Register 45 + 0x32D + 8 + read-write + 0 + 0xFF + + + PRI45 + Priority of the INT_WDOG2 interrupt 45 + 4 + 4 + read-write + + + + + NVICIP46 + Interrupt Priority Register 46 + 0x32E + 8 + read-write + 0 + 0xFF + + + PRI46 + Priority of the INT_SNVS_HP_WRAPPER interrupt 46 + 4 + 4 + read-write + + + + + NVICIP47 + Interrupt Priority Register 47 + 0x32F + 8 + read-write + 0 + 0xFF + + + PRI47 + Priority of the INT_SNVS_HP_WRAPPER_TZ interrupt 47 + 4 + 4 + read-write + + + + + NVICIP48 + Interrupt Priority Register 48 + 0x330 + 8 + read-write + 0 + 0xFF + + + PRI48 + Priority of the INT_SNVS_LP_WRAPPER interrupt 48 + 4 + 4 + read-write + + + + + NVICIP49 + Interrupt Priority Register 49 + 0x331 + 8 + read-write + 0 + 0xFF + + + PRI49 + Priority of the INT_CSU interrupt 49 + 4 + 4 + read-write + + + + + NVICIP50 + Interrupt Priority Register 50 + 0x332 + 8 + read-write + 0 + 0xFF + + + PRI50 + Priority of the INT_DCP interrupt 50 + 4 + 4 + read-write + + + + + NVICIP51 + Interrupt Priority Register 51 + 0x333 + 8 + read-write + 0 + 0xFF + + + PRI51 + Priority of the INT_DCP_VMI interrupt 51 + 4 + 4 + read-write + + + + + NVICIP52 + Interrupt Priority Register 52 + 0x334 + 8 + read-write + 0 + 0xFF + + + PRI52 + Priority of the INT_Reserved68 interrupt 52 + 4 + 4 + read-write + + + + + NVICIP53 + Interrupt Priority Register 53 + 0x335 + 8 + read-write + 0 + 0xFF + + + PRI53 + Priority of the INT_TRNG interrupt 53 + 4 + 4 + read-write + + + + + NVICIP54 + Interrupt Priority Register 54 + 0x336 + 8 + read-write + 0 + 0xFF + + + PRI54 + Priority of the INT_SJC interrupt 54 + 4 + 4 + read-write + + + + + NVICIP55 + Interrupt Priority Register 55 + 0x337 + 8 + read-write + 0 + 0xFF + + + PRI55 + Priority of the INT_BEE interrupt 55 + 4 + 4 + read-write + + + + + NVICIP56 + Interrupt Priority Register 56 + 0x338 + 8 + read-write + 0 + 0xFF + + + PRI56 + Priority of the INT_SAI1 interrupt 56 + 4 + 4 + read-write + + + + + NVICIP57 + Interrupt Priority Register 57 + 0x339 + 8 + read-write + 0 + 0xFF + + + PRI57 + Priority of the INT_SAI2 interrupt 57 + 4 + 4 + read-write + + + + + NVICIP58 + Interrupt Priority Register 58 + 0x33A + 8 + read-write + 0 + 0xFF + + + PRI58 + Priority of the INT_SAI3_RX interrupt 58 + 4 + 4 + read-write + + + + + NVICIP59 + Interrupt Priority Register 59 + 0x33B + 8 + read-write + 0 + 0xFF + + + PRI59 + Priority of the INT_SAI3_TX interrupt 59 + 4 + 4 + read-write + + + + + NVICIP60 + Interrupt Priority Register 60 + 0x33C + 8 + read-write + 0 + 0xFF + + + PRI60 + Priority of the INT_SPDIF interrupt 60 + 4 + 4 + read-write + + + + + NVICIP61 + Interrupt Priority Register 61 + 0x33D + 8 + read-write + 0 + 0xFF + + + PRI61 + Priority of the INT_PMU_EVENT interrupt 61 + 4 + 4 + read-write + + + + + NVICIP62 + Interrupt Priority Register 62 + 0x33E + 8 + read-write + 0 + 0xFF + + + PRI62 + Priority of the INT_Reserved78 interrupt 62 + 4 + 4 + read-write + + + + + NVICIP63 + Interrupt Priority Register 63 + 0x33F + 8 + read-write + 0 + 0xFF + + + PRI63 + Priority of the INT_TEMP_LOW_HIGH interrupt 63 + 4 + 4 + read-write + + + + + NVICIP64 + Interrupt Priority Register 64 + 0x340 + 8 + read-write + 0 + 0xFF + + + PRI64 + Priority of the INT_TEMP_PANIC interrupt 64 + 4 + 4 + read-write + + + + + NVICIP65 + Interrupt Priority Register 65 + 0x341 + 8 + read-write + 0 + 0xFF + + + PRI65 + Priority of the INT_USB_PHY1 interrupt 65 + 4 + 4 + read-write + + + + + NVICIP66 + Interrupt Priority Register 66 + 0x342 + 8 + read-write + 0 + 0xFF + + + PRI66 + Priority of the INT_USB_PHY2 interrupt 66 + 4 + 4 + read-write + + + + + NVICIP67 + Interrupt Priority Register 67 + 0x343 + 8 + read-write + 0 + 0xFF + + + PRI67 + Priority of the INT_ADC1 interrupt 67 + 4 + 4 + read-write + + + + + NVICIP68 + Interrupt Priority Register 68 + 0x344 + 8 + read-write + 0 + 0xFF + + + PRI68 + Priority of the INT_ADC2 interrupt 68 + 4 + 4 + read-write + + + + + NVICIP69 + Interrupt Priority Register 69 + 0x345 + 8 + read-write + 0 + 0xFF + + + PRI69 + Priority of the INT_DCDC interrupt 69 + 4 + 4 + read-write + + + + + NVICIP70 + Interrupt Priority Register 70 + 0x346 + 8 + read-write + 0 + 0xFF + + + PRI70 + Priority of the INT_Reserved86 interrupt 70 + 4 + 4 + read-write + + + + + NVICIP71 + Interrupt Priority Register 71 + 0x347 + 8 + read-write + 0 + 0xFF + + + PRI71 + Priority of the INT_Reserved87 interrupt 71 + 4 + 4 + read-write + + + + + NVICIP72 + Interrupt Priority Register 72 + 0x348 + 8 + read-write + 0 + 0xFF + + + PRI72 + Priority of the INT_GPIO1_INT0 interrupt 72 + 4 + 4 + read-write + + + + + NVICIP73 + Interrupt Priority Register 73 + 0x349 + 8 + read-write + 0 + 0xFF + + + PRI73 + Priority of the INT_GPIO1_INT1 interrupt 73 + 4 + 4 + read-write + + + + + NVICIP74 + Interrupt Priority Register 74 + 0x34A + 8 + read-write + 0 + 0xFF + + + PRI74 + Priority of the INT_GPIO1_INT2 interrupt 74 + 4 + 4 + read-write + + + + + NVICIP75 + Interrupt Priority Register 75 + 0x34B + 8 + read-write + 0 + 0xFF + + + PRI75 + Priority of the INT_GPIO1_INT3 interrupt 75 + 4 + 4 + read-write + + + + + NVICIP76 + Interrupt Priority Register 76 + 0x34C + 8 + read-write + 0 + 0xFF + + + PRI76 + Priority of the INT_GPIO1_INT4 interrupt 76 + 4 + 4 + read-write + + + + + NVICIP77 + Interrupt Priority Register 77 + 0x34D + 8 + read-write + 0 + 0xFF + + + PRI77 + Priority of the INT_GPIO1_INT5 interrupt 77 + 4 + 4 + read-write + + + + + NVICIP78 + Interrupt Priority Register 78 + 0x34E + 8 + read-write + 0 + 0xFF + + + PRI78 + Priority of the INT_GPIO1_INT6 interrupt 78 + 4 + 4 + read-write + + + + + NVICIP79 + Interrupt Priority Register 79 + 0x34F + 8 + read-write + 0 + 0xFF + + + PRI79 + Priority of the INT_GPIO1_INT7 interrupt 79 + 4 + 4 + read-write + + + + + NVICIP80 + Interrupt Priority Register 80 + 0x350 + 8 + read-write + 0 + 0xFF + + + PRI80 + Priority of the INT_GPIO1_Combined_0_15 interrupt 80 + 4 + 4 + read-write + + + + + NVICIP81 + Interrupt Priority Register 81 + 0x351 + 8 + read-write + 0 + 0xFF + + + PRI81 + Priority of the INT_GPIO1_Combined_16_31 interrupt 81 + 4 + 4 + read-write + + + + + NVICIP82 + Interrupt Priority Register 82 + 0x352 + 8 + read-write + 0 + 0xFF + + + PRI82 + Priority of the INT_GPIO2_Combined_0_15 interrupt 82 + 4 + 4 + read-write + + + + + NVICIP83 + Interrupt Priority Register 83 + 0x353 + 8 + read-write + 0 + 0xFF + + + PRI83 + Priority of the INT_GPIO2_Combined_16_31 interrupt 83 + 4 + 4 + read-write + + + + + NVICIP84 + Interrupt Priority Register 84 + 0x354 + 8 + read-write + 0 + 0xFF + + + PRI84 + Priority of the INT_GPIO3_Combined_0_15 interrupt 84 + 4 + 4 + read-write + + + + + NVICIP85 + Interrupt Priority Register 85 + 0x355 + 8 + read-write + 0 + 0xFF + + + PRI85 + Priority of the INT_GPIO3_Combined_16_31 interrupt 85 + 4 + 4 + read-write + + + + + NVICIP86 + Interrupt Priority Register 86 + 0x356 + 8 + read-write + 0 + 0xFF + + + PRI86 + Priority of the INT_GPIO4_Combined_0_15 interrupt 86 + 4 + 4 + read-write + + + + + NVICIP87 + Interrupt Priority Register 87 + 0x357 + 8 + read-write + 0 + 0xFF + + + PRI87 + Priority of the INT_GPIO4_Combined_16_31 interrupt 87 + 4 + 4 + read-write + + + + + NVICIP88 + Interrupt Priority Register 88 + 0x358 + 8 + read-write + 0 + 0xFF + + + PRI88 + Priority of the INT_GPIO5_Combined_0_15 interrupt 88 + 4 + 4 + read-write + + + + + NVICIP89 + Interrupt Priority Register 89 + 0x359 + 8 + read-write + 0 + 0xFF + + + PRI89 + Priority of the INT_GPIO5_Combined_16_31 interrupt 89 + 4 + 4 + read-write + + + + + NVICIP90 + Interrupt Priority Register 90 + 0x35A + 8 + read-write + 0 + 0xFF + + + PRI90 + Priority of the INT_FLEXIO1 interrupt 90 + 4 + 4 + read-write + + + + + NVICIP91 + Interrupt Priority Register 91 + 0x35B + 8 + read-write + 0 + 0xFF + + + PRI91 + Priority of the INT_FLEXIO2 interrupt 91 + 4 + 4 + read-write + + + + + NVICIP92 + Interrupt Priority Register 92 + 0x35C + 8 + read-write + 0 + 0xFF + + + PRI92 + Priority of the INT_WDOG1 interrupt 92 + 4 + 4 + read-write + + + + + NVICIP93 + Interrupt Priority Register 93 + 0x35D + 8 + read-write + 0 + 0xFF + + + PRI93 + Priority of the INT_RTWDOG interrupt 93 + 4 + 4 + read-write + + + + + NVICIP94 + Interrupt Priority Register 94 + 0x35E + 8 + read-write + 0 + 0xFF + + + PRI94 + Priority of the INT_EWM interrupt 94 + 4 + 4 + read-write + + + + + NVICIP95 + Interrupt Priority Register 95 + 0x35F + 8 + read-write + 0 + 0xFF + + + PRI95 + Priority of the INT_CCM_1 interrupt 95 + 4 + 4 + read-write + + + + + NVICIP96 + Interrupt Priority Register 96 + 0x360 + 8 + read-write + 0 + 0xFF + + + PRI96 + Priority of the INT_CCM_2 interrupt 96 + 4 + 4 + read-write + + + + + NVICIP97 + Interrupt Priority Register 97 + 0x361 + 8 + read-write + 0 + 0xFF + + + PRI97 + Priority of the INT_GPC interrupt 97 + 4 + 4 + read-write + + + + + NVICIP98 + Interrupt Priority Register 98 + 0x362 + 8 + read-write + 0 + 0xFF + + + PRI98 + Priority of the INT_SRC interrupt 98 + 4 + 4 + read-write + + + + + NVICIP99 + Interrupt Priority Register 99 + 0x363 + 8 + read-write + 0 + 0xFF + + + PRI99 + Priority of the INT_Reserved115 interrupt 99 + 4 + 4 + read-write + + + + + NVICIP100 + Interrupt Priority Register 100 + 0x364 + 8 + read-write + 0 + 0xFF + + + PRI100 + Priority of the INT_GPT1 interrupt 100 + 4 + 4 + read-write + + + + + NVICIP101 + Interrupt Priority Register 101 + 0x365 + 8 + read-write + 0 + 0xFF + + + PRI101 + Priority of the INT_GPT2 interrupt 101 + 4 + 4 + read-write + + + + + NVICIP102 + Interrupt Priority Register 102 + 0x366 + 8 + read-write + 0 + 0xFF + + + PRI102 + Priority of the INT_PWM1_0 interrupt 102 + 4 + 4 + read-write + + + + + NVICIP103 + Interrupt Priority Register 103 + 0x367 + 8 + read-write + 0 + 0xFF + + + PRI103 + Priority of the INT_PWM1_1 interrupt 103 + 4 + 4 + read-write + + + + + NVICIP104 + Interrupt Priority Register 104 + 0x368 + 8 + read-write + 0 + 0xFF + + + PRI104 + Priority of the INT_PWM1_2 interrupt 104 + 4 + 4 + read-write + + + + + NVICIP105 + Interrupt Priority Register 105 + 0x369 + 8 + read-write + 0 + 0xFF + + + PRI105 + Priority of the INT_PWM1_3 interrupt 105 + 4 + 4 + read-write + + + + + NVICIP106 + Interrupt Priority Register 106 + 0x36A + 8 + read-write + 0 + 0xFF + + + PRI106 + Priority of the INT_PWM1_FAULT interrupt 106 + 4 + 4 + read-write + + + + + NVICIP107 + Interrupt Priority Register 107 + 0x36B + 8 + read-write + 0 + 0xFF + + + PRI107 + Priority of the INT_FLEXSPI2 interrupt 107 + 4 + 4 + read-write + + + + + NVICIP108 + Interrupt Priority Register 108 + 0x36C + 8 + read-write + 0 + 0xFF + + + PRI108 + Priority of interrupt 108 + 4 + 4 + read-write + + + + + NVICIP109 + Interrupt Priority Register 109 + 0x36D + 8 + read-write + 0 + 0xFF + + + PRI109 + Priority of the INT_SEMC interrupt 109 + 4 + 4 + read-write + + + + + NVICIP110 + Interrupt Priority Register 110 + 0x36E + 8 + read-write + 0 + 0xFF + + + PRI110 + Priority of the INT_USDHC1 interrupt 110 + 4 + 4 + read-write + + + + + NVICIP111 + Interrupt Priority Register 111 + 0x36F + 8 + read-write + 0 + 0xFF + + + PRI111 + Priority of the INT_USDHC2 interrupt 111 + 4 + 4 + read-write + + + + + NVICIP112 + Interrupt Priority Register 112 + 0x370 + 8 + read-write + 0 + 0xFF + + + PRI112 + Priority of the INT_USB_OTG2 interrupt 112 + 4 + 4 + read-write + + + + + NVICIP113 + Interrupt Priority Register 113 + 0x371 + 8 + read-write + 0 + 0xFF + + + PRI113 + Priority of the INT_USB_OTG1 interrupt 113 + 4 + 4 + read-write + + + + + NVICIP114 + Interrupt Priority Register 114 + 0x372 + 8 + read-write + 0 + 0xFF + + + PRI114 + Priority of the INT_ENET interrupt 114 + 4 + 4 + read-write + + + + + NVICIP115 + Interrupt Priority Register 115 + 0x373 + 8 + read-write + 0 + 0xFF + + + PRI115 + Priority of the INT_ENET_1588_Timer interrupt 115 + 4 + 4 + read-write + + + + + NVICIP116 + Interrupt Priority Register 116 + 0x374 + 8 + read-write + 0 + 0xFF + + + PRI116 + Priority of the INT_XBAR1_IRQ_0_1 interrupt 116 + 4 + 4 + read-write + + + + + NVICIP117 + Interrupt Priority Register 117 + 0x375 + 8 + read-write + 0 + 0xFF + + + PRI117 + Priority of the INT_XBAR1_IRQ_2_3 interrupt 117 + 4 + 4 + read-write + + + + + NVICIP118 + Interrupt Priority Register 118 + 0x376 + 8 + read-write + 0 + 0xFF + + + PRI118 + Priority of the INT_ADC_ETC_IRQ0 interrupt 118 + 4 + 4 + read-write + + + + + NVICIP119 + Interrupt Priority Register 119 + 0x377 + 8 + read-write + 0 + 0xFF + + + PRI119 + Priority of the INT_ADC_ETC_IRQ1 interrupt 119 + 4 + 4 + read-write + + + + + NVICIP120 + Interrupt Priority Register 120 + 0x378 + 8 + read-write + 0 + 0xFF + + + PRI120 + Priority of the INT_ADC_ETC_IRQ2 interrupt 120 + 4 + 4 + read-write + + + + + NVICIP121 + Interrupt Priority Register 121 + 0x379 + 8 + read-write + 0 + 0xFF + + + PRI121 + Priority of the INT_ADC_ETC_ERROR_IRQ interrupt 121 + 4 + 4 + read-write + + + + + NVICIP122 + Interrupt Priority Register 122 + 0x37A + 8 + read-write + 0 + 0xFF + + + PRI122 + Priority of the INT_PIT interrupt 122 + 4 + 4 + read-write + + + + + NVICIP123 + Interrupt Priority Register 123 + 0x37B + 8 + read-write + 0 + 0xFF + + + PRI123 + Priority of the INT_ACMP1 interrupt 123 + 4 + 4 + read-write + + + + + NVICIP124 + Interrupt Priority Register 124 + 0x37C + 8 + read-write + 0 + 0xFF + + + PRI124 + Priority of the INT_ACMP2 interrupt 124 + 4 + 4 + read-write + + + + + NVICIP125 + Interrupt Priority Register 125 + 0x37D + 8 + read-write + 0 + 0xFF + + + PRI125 + Priority of the INT_ACMP3 interrupt 125 + 4 + 4 + read-write + + + + + NVICIP126 + Interrupt Priority Register 126 + 0x37E + 8 + read-write + 0 + 0xFF + + + PRI126 + Priority of the INT_ACMP4 interrupt 126 + 4 + 4 + read-write + + + + + NVICIP127 + Interrupt Priority Register 127 + 0x37F + 8 + read-write + 0 + 0xFF + + + PRI127 + Priority of the INT_Reserved143 interrupt 127 + 4 + 4 + read-write + + + + + NVICIP128 + Interrupt Priority Register 128 + 0x380 + 8 + read-write + 0 + 0xFF + + + PRI128 + Priority of the INT_Reserved144 interrupt 128 + 4 + 4 + read-write + + + + + NVICIP129 + Interrupt Priority Register 129 + 0x381 + 8 + read-write + 0 + 0xFF + + + PRI129 + Priority of the INT_ENC1 interrupt 129 + 4 + 4 + read-write + + + + + NVICIP130 + Interrupt Priority Register 130 + 0x382 + 8 + read-write + 0 + 0xFF + + + PRI130 + Priority of the INT_ENC2 interrupt 130 + 4 + 4 + read-write + + + + + NVICIP131 + Interrupt Priority Register 131 + 0x383 + 8 + read-write + 0 + 0xFF + + + PRI131 + Priority of the INT_ENC3 interrupt 131 + 4 + 4 + read-write + + + + + NVICIP132 + Interrupt Priority Register 132 + 0x384 + 8 + read-write + 0 + 0xFF + + + PRI132 + Priority of the INT_ENC4 interrupt 132 + 4 + 4 + read-write + + + + + NVICIP133 + Interrupt Priority Register 133 + 0x385 + 8 + read-write + 0 + 0xFF + + + PRI133 + Priority of the INT_TMR1 interrupt 133 + 4 + 4 + read-write + + + + + NVICIP134 + Interrupt Priority Register 134 + 0x386 + 8 + read-write + 0 + 0xFF + + + PRI134 + Priority of the INT_TMR2 interrupt 134 + 4 + 4 + read-write + + + + + NVICIP135 + Interrupt Priority Register 135 + 0x387 + 8 + read-write + 0 + 0xFF + + + PRI135 + Priority of the INT_TMR3 interrupt 135 + 4 + 4 + read-write + + + + + NVICIP136 + Interrupt Priority Register 136 + 0x388 + 8 + read-write + 0 + 0xFF + + + PRI136 + Priority of the INT_TMR4 interrupt 136 + 4 + 4 + read-write + + + + + NVICIP137 + Interrupt Priority Register 137 + 0x389 + 8 + read-write + 0 + 0xFF + + + PRI137 + Priority of the INT_PWM2_0 interrupt 137 + 4 + 4 + read-write + + + + + NVICIP138 + Interrupt Priority Register 138 + 0x38A + 8 + read-write + 0 + 0xFF + + + PRI138 + Priority of the INT_PWM2_1 interrupt 138 + 4 + 4 + read-write + + + + + NVICIP139 + Interrupt Priority Register 139 + 0x38B + 8 + read-write + 0 + 0xFF + + + PRI139 + Priority of the INT_PWM2_2 interrupt 139 + 4 + 4 + read-write + + + + + NVICIP140 + Interrupt Priority Register 140 + 0x38C + 8 + read-write + 0 + 0xFF + + + PRI140 + Priority of the INT_PWM2_3 interrupt 140 + 4 + 4 + read-write + + + + + NVICIP141 + Interrupt Priority Register 141 + 0x38D + 8 + read-write + 0 + 0xFF + + + PRI141 + Priority of the INT_PWM2_FAULT interrupt 141 + 4 + 4 + read-write + + + + + NVICIP142 + Interrupt Priority Register 142 + 0x38E + 8 + read-write + 0 + 0xFF + + + PRI142 + Priority of the INT_PWM3_0 interrupt 142 + 4 + 4 + read-write + + + + + NVICIP143 + Interrupt Priority Register 143 + 0x38F + 8 + read-write + 0 + 0xFF + + + PRI143 + Priority of the INT_PWM3_1 interrupt 143 + 4 + 4 + read-write + + + + + NVICIP144 + Interrupt Priority Register 144 + 0x390 + 8 + read-write + 0 + 0xFF + + + PRI144 + Priority of the INT_PWM3_2 interrupt 144 + 4 + 4 + read-write + + + + + NVICIP145 + Interrupt Priority Register 145 + 0x391 + 8 + read-write + 0 + 0xFF + + + PRI145 + Priority of the INT_PWM3_3 interrupt 145 + 4 + 4 + read-write + + + + + NVICIP146 + Interrupt Priority Register 146 + 0x392 + 8 + read-write + 0 + 0xFF + + + PRI146 + Priority of the INT_PWM3_FAULT interrupt 146 + 4 + 4 + read-write + + + + + NVICIP147 + Interrupt Priority Register 147 + 0x393 + 8 + read-write + 0 + 0xFF + + + PRI147 + Priority of the INT_PWM4_0 interrupt 147 + 4 + 4 + read-write + + + + + NVICIP148 + Interrupt Priority Register 148 + 0x394 + 8 + read-write + 0 + 0xFF + + + PRI148 + Priority of the INT_PWM4_1 interrupt 148 + 4 + 4 + read-write + + + + + NVICIP149 + Interrupt Priority Register 149 + 0x395 + 8 + read-write + 0 + 0xFF + + + PRI149 + Priority of the INT_PWM4_2 interrupt 149 + 4 + 4 + read-write + + + + + NVICIP150 + Interrupt Priority Register 150 + 0x396 + 8 + read-write + 0 + 0xFF + + + PRI150 + Priority of the INT_PWM4_3 interrupt 150 + 4 + 4 + read-write + + + + + NVICIP151 + Interrupt Priority Register 151 + 0x397 + 8 + read-write + 0 + 0xFF + + + PRI151 + Priority of the INT_PWM4_FAULT interrupt 151 + 4 + 4 + read-write + + + + + NVICIP152 + Interrupt Priority Register 152 + 0x398 + 8 + read-write + 0 + 0xFF + + + PRI152 + Priority of the INT_ENET2 interrupt 152 + 4 + 4 + read-write + + + + + NVICIP153 + Interrupt Priority Register 153 + 0x399 + 8 + read-write + 0 + 0xFF + + + PRI153 + Priority of the INT_ENET2_1588_Timer interrupt 153 + 4 + 4 + read-write + + + + + NVICIP154 + Interrupt Priority Register 154 + 0x39A + 8 + read-write + 0 + 0xFF + + + PRI154 + Priority of the INT_CAN3 interrupt 154 + 4 + 4 + read-write + + + + + NVICIP155 + Interrupt Priority Register 155 + 0x39B + 8 + read-write + 0 + 0xFF + + + PRI155 + Priority of the INT_Reserved171 interrupt 155 + 4 + 4 + read-write + + + + + NVICIP156 + Interrupt Priority Register 156 + 0x39C + 8 + read-write + 0 + 0xFF + + + PRI156 + Priority of the INT_FLEXIO3 interrupt 156 + 4 + 4 + read-write + + + + + NVICIP157 + Interrupt Priority Register 157 + 0x39D + 8 + read-write + 0 + 0xFF + + + PRI157 + Priority of the INT_GPIO6_7_8_9 interrupt 157 + 4 + 4 + read-write + + + + + NVICSTIR + Software Trigger Interrupt Register + 0xE00 + 32 + read-write + 0 + 0xFFFFFFFF + + + INTID + Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3. + 0 + 9 + read-write + + + + + + + \ No newline at end of file diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/MIMXRT1061_features.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/MIMXRT1061_features.h new file mode 100644 index 0000000000..e0691d34f2 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/MIMXRT1061_features.h @@ -0,0 +1,621 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2018-11-16 +** Build: b190319 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 0.1 (2017-01-10) +** Initial version. +** - rev. 1.0 (2018-11-16) +** Update feature files to align with IMXRT1060RM Rev.0. +** +** ################################################################### +*/ + +#ifndef _MIMXRT1061_FEATURES_H_ +#define _MIMXRT1061_FEATURES_H_ + +/* SOC module features */ + +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (2) +/* @brief AIPSTZ availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPSTZ_COUNT (4) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (2) +/* @brief CCM availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_COUNT (1) +/* @brief CCM_ANALOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (4) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (1) +/* @brief DCP availability on the SoC. */ +#define FSL_FEATURE_SOC_DCP_COUNT (1) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (1) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (4) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_ENET_COUNT (2) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (1) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (3) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (3) +/* @brief FLEXRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXRAM_COUNT (1) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (2) +/* @brief GPC availability on the SoC. */ +#define FSL_FEATURE_SOC_GPC_COUNT (1) +/* @brief GPT availability on the SoC. */ +#define FSL_FEATURE_SOC_GPT_COUNT (2) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (3) +/* @brief IGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_IGPIO_COUNT (9) +/* @brief IOMUXC availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_COUNT (1) +/* @brief IOMUXC_GPR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1) +/* @brief IOMUXC_SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1) +/* @brief KPP availability on the SoC. */ +#define FSL_FEATURE_SOC_KPP_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (4) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (4) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (8) +/* @brief OCOTP availability on the SoC. */ +#define FSL_FEATURE_SOC_OCOTP_COUNT (1) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (1) +/* @brief PMU availability on the SoC. */ +#define FSL_FEATURE_SOC_PMU_COUNT (1) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (4) +/* @brief ROMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ROMC_COUNT (1) +/* @brief SEMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMC_COUNT (1) +/* @brief SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_SNVS_COUNT (1) +/* @brief SPDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SPDIF_COUNT (1) +/* @brief SRC availability on the SoC. */ +#define FSL_FEATURE_SOC_SRC_COUNT (1) +/* @brief TEMPMON availability on the SoC. */ +#define FSL_FEATURE_SOC_TEMPMON_COUNT (1) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (4) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (1) +/* @brief TSC availability on the SoC. */ +#define FSL_FEATURE_SOC_TSC_COUNT (1) +/* @brief USBHS availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHS_COUNT (2) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (2) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (2) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (2) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (2) +/* @brief XBARA availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARA_COUNT (1) +/* @brief XBARB availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARB_COUNT (2) +/* @brief XTALOSC24M availability on the SoC. */ +#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1) + +/* ADC module features */ + +/* @brief Remove Hardware Trigger feature. */ +#define FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE (0) +/* @brief Remove ALT Clock selection feature. */ +#define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1) +/* @brief Conversion control count (related to number of registers HCn and Rn). */ +#define FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT (8) + +/* ADC_ETC module features */ + +/* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */ +#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1) + +/* AOI module features */ + +/* @brief Maximum value of input mux. */ +#define FSL_FEATURE_AOI_MODULE_INPUTS (4) +/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ +#define FSL_FEATURE_AOI_EVENT_COUNT (4) + +/* FLEXCAN module features */ + +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (64) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) \ + (((x) == CAN1) ? (0) : \ + (((x) == CAN2) ? (0) : \ + (((x) == CAN3) ? (1) : (-1)))) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (1) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) \ + (((x) == CAN1) ? (0) : \ + (((x) == CAN2) ? (0) : \ + (((x) == CAN3) ? (1) : (-1)))) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) \ + (((x) == CAN1) ? (0) : \ + (((x) == CAN2) ? (0) : \ + (((x) == CAN3) ? (1) : (-1)))) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) \ + (((x) == CAN1) ? (1) : \ + (((x) == CAN2) ? (1) : \ + (((x) == CAN3) ? (0) : (-1)))) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (1) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (1) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (1) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) \ + (((x) == CAN1) ? (0) : \ + (((x) == CAN2) ? (0) : \ + (((x) == CAN3) ? (1) : (-1)))) +/* @brief Has extra MB interrupt or common one. */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1) + +/* CMP module features */ + +/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ +#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0) +/* @brief Has Window mode in CMP (register bit field CR1[WE]). */ +#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) +/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ +#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) +/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ +#define FSL_FEATURE_CMP_HAS_DMA (1) +/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ +#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) +/* @brief Has DAC Test function in CMP (register DACTEST). */ +#define FSL_FEATURE_CMP_HAS_DAC_TEST (0) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) +/* @brief Channel IRQ entry shared offset. */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (16) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (0) + +/* DMAMUX module features */ + +/* @brief Number of DMA channels (related to number of register CHCFGn). */ +#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32) +/* @brief Total number of DMA channels on all modules. */ +#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 32) +/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ +#define FSL_FEATURE_DMAMUX_HAS_TRIG (1) +/* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */ +#define FSL_FEATURE_DMAMUX_HAS_A_ON (1) + +/* ENET module features */ + +/* @brief Support Interrupt Coalesce */ +#define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (1) +/* @brief Queue Size. */ +#define FSL_FEATURE_ENET_QUEUE (1) +/* @brief Has AVB Support. */ +#define FSL_FEATURE_ENET_HAS_AVB (0) +/* @brief Has Timer Pulse Width control. */ +#define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (1) +/* @brief Has Extend MDIO Support. */ +#define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1) +/* @brief Has Additional 1588 Timer Channel Interrupt. */ +#define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0) + +/* EWM module features */ + +/* @brief Has clock select (register CLKCTRL). */ +#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) +/* @brief Has clock prescaler (register CLKPRESCALER). */ +#define FSL_FEATURE_EWM_HAS_PRESCALER (1) + +/* FLEXIO module features */ + +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200404) +/* @brief Flexio DMA request base channel */ +#define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) + +/* FLEXRAM module features */ + +/* @brief Bank size */ +#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768) +/* @brief Total Bank numbers */ +#define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16) + +/* FLEXSPI module features */ + +/* @brief FlexSPI AHB buffer count */ +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (4) +/* @brief FlexSPI has no data learn. */ +#define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1) + +/* GPC module features */ + +/* @brief Has DVFS0 Change Request. */ +#define FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR (0) +/* @brief Has GPC interrupt/event masking. */ +#define FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM (0) +/* @brief Has L2 cache power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_L2PGE (0) +/* @brief Has FLEXRAM PDRAM0(bank1-7) power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE (1) +/* @brief Has VADC power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_VADC (0) +/* @brief Has Display power control. */ +#define FSL_FEATURE_GPC_HAS_CNTR_DISPLAY (0) +/* @brief Supports IRQ 0-31. */ +#define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1) + +/* IGPIO module features */ + +/* @brief Has data register set DR_SET. */ +#define FSL_FEATURE_IGPIO_HAS_DR_SET (1) +/* @brief Has data register clear DR_CLEAR. */ +#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1) +/* @brief Has data register toggle DR_TOGGLE. */ +#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (16) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief Maximal data width without parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10) +/* @brief Maximal data width with parity bit. */ +#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (157) + +/* OCOTP module features */ + +/* No feature definitions */ + +/* PIT module features */ + +/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ +#define FSL_FEATURE_PIT_TIMER_COUNT (4) +/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ +#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) +/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ +#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) +/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ +#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) +/* @brief Has timer enable control. */ +#define FSL_FEATURE_PIT_HAS_MDIS (1) + +/* PMU module features */ + +/* @brief PMU supports lower power control. */ +#define FSL_FEATURE_PMU_HAS_LOWPWR_CTRL (0) + +/* PWM module features */ + +/* @brief Number of each EflexPWM module channels (outputs). */ +#define FSL_FEATURE_PWM_CHANNEL_COUNT (12U) +/* @brief Number of EflexPWM module A channels (outputs). */ +#define FSL_FEATURE_PWM_CHANNELA_COUNT (4U) +/* @brief Number of EflexPWM module B channels (outputs). */ +#define FSL_FEATURE_PWM_CHANNELB_COUNT (4U) +/* @brief Number of EflexPWM module X channels (outputs). */ +#define FSL_FEATURE_PWM_CHANNELX_COUNT (4U) +/* @brief Number of each EflexPWM module compare channels interrupts. */ +#define FSL_FEATURE_PWM_CMP_INT_HANDLER_COUNT (4U) +/* @brief Number of each EflexPWM module reload channels interrupts. */ +#define FSL_FEATURE_PWM_RELOAD_INT_HANDLER_COUNT (4U) +/* @brief Number of each EflexPWM module capture channels interrupts. */ +#define FSL_FEATURE_PWM_CAP_INT_HANDLER_COUNT (1U) +/* @brief Number of each EflexPWM module reload error channels interrupts. */ +#define FSL_FEATURE_PWM_RERR_INT_HANDLER_COUNT (1U) +/* @brief Number of each EflexPWM module fault channels interrupts. */ +#define FSL_FEATURE_PWM_FAULT_INT_HANDLER_COUNT (1U) +/* @brief Number of submodules in each EflexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U) + +/* RTWDOG module features */ + +/* @brief Watchdog is available. */ +#define FSL_FEATURE_RTWDOG_HAS_WATCHDOG (1) +/* @brief RTWDOG_CNT can be 32-bit written. */ +#define FSL_FEATURE_RTWDOG_HAS_32BIT_ACCESS (1) + +/* SAI module features */ + +/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ +#define FSL_FEATURE_SAI_FIFO_COUNT (32) +/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ +#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) \ + (((x) == SAI1) ? (4) : \ + (((x) == SAI2) ? (1) : \ + (((x) == SAI3) ? (1) : (-1)))) +/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ +#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) +/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) +/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) +/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ +#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) +/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ +#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) +/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ +#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) +/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ +#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0) +/* @brief Interrupt source number */ +#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) +/* @brief Has register of MCR. */ +#define FSL_FEATURE_SAI_HAS_MCR (0) +/* @brief Has bit field MICS of the MCR register. */ +#define FSL_FEATURE_SAI_HAS_NO_MCR_MICS (1) +/* @brief Has register of MDR */ +#define FSL_FEATURE_SAI_HAS_MDR (0) +/* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) +/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ +#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) +/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ +#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1) + +/* SEMC module features */ + +/* @brief Has WDH time in NOR controller (register bit field NORCR2[WDH]). */ +#define FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME (0) +/* @brief Has WDS time in NOR controller (register bit field NORCR2[WDS]).) */ +#define FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME (0) + +/* SNVS module features */ + +/* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */ +#define FSL_FEATURE_SNVS_HAS_SRTC (1) + +/* SRC module features */ + +/* @brief There is MASK_WDOG3_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST (1) +/* @brief There is MIX_RST_STRCH bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH (0) +/* @brief There is DBG_RST_MSK_PG bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG (1) +/* @brief There is WDOG3_RST_OPTN bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN (0) +/* @brief There is CORES_DBG_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST (0) +/* @brief There is MTSR bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_MTSR (0) +/* @brief There is CORE0_DBG_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORE0_DBG_RST (1) +/* @brief There is CORE0_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1) +/* @brief There is LOCKUP_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (0) +/* @brief There is SWRC bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_SWRC (0) +/* @brief There is EIM_RST bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_EIM_RST (0) +/* @brief There is LUEN bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_SCR_LUEN (0) +/* @brief There is no WRBC bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_NO_SCR_WRBC (1) +/* @brief There is no WRE bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_NO_SCR_WRE (1) +/* @brief There is SISR register. */ +#define FSL_FEATURE_SRC_HAS_SISR (0) +/* @brief There is RESET_OUT bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT (0) +/* @brief There is WDOG3_RST_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B (1) +/* @brief There is SW bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_SW (0) +/* @brief There is IPP_USER_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B (1) +/* @brief There is SNVS bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_SNVS (0) +/* @brief There is CSU_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B (1) +/* @brief There is LOCKUP bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP (0) +/* @brief There is LOCKUP_SYSRESETREQ bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ (1) +/* @brief There is POR bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_POR (0) +/* @brief There is IPP_RESET_B bit in SRSR register. */ +#define FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B (1) +/* @brief There is no WBI bit in SCR register. */ +#define FSL_FEATURE_SRC_HAS_NO_SRSR_WBI (1) + +/* SCB module features */ + +/* @brief L1 ICACHE line size in byte. */ +#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (32) +/* @brief L1 DCACHE line size in byte. */ +#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32) + +/* TRNG module features */ + +/* @brief TRNG has no TRNG_ACC bitfield. */ +#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1) + +/* USBHS module features */ + +/* @brief EHCI module instance count */ +#define FSL_FEATURE_USBHS_EHCI_COUNT (2) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USBHS_ENDPT_COUNT (8) + +/* USDHC module features */ + +/* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ +#define FSL_FEATURE_USDHC_HAS_EXT_DMA (0) +/* @brief Has HS400 mode (MIX_CTRL[HS400_MODE]) */ +#define FSL_FEATURE_USDHC_HAS_HS400_MODE (0) +/* @brief Has SDR50 support (HOST_CTRL_CAP[SDR50_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR50_MODE (1) +/* @brief Has SDR104 support (HOST_CTRL_CAP[SDR104_SUPPORT]) */ +#define FSL_FEATURE_USDHC_HAS_SDR104_MODE (1) + +/* XBARA module features */ + +/* @brief Number of interrupt requests. */ +#define FSL_FEATURE_XBARA_INTERRUPT_COUNT (4) + +#endif /* _MIMXRT1061_FEATURES_H_ */ + diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/MIMXRT1061xxxxx_flexspi_nor.scf b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/MIMXRT1061xxxxx_flexspi_nor.scf new file mode 100644 index 0000000000..e566fa3841 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/MIMXRT1061xxxxx_flexspi_nor.scf @@ -0,0 +1,90 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MIMXRT1061CVJ5A +** MIMXRT1061CVL5A +** MIMXRT1061DVJ6A +** MIMXRT1061DVL6A +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1060RM Rev.1, 12/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b190312 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_flash_config_start 0x60000000 +#define m_flash_config_size 0x00001000 + +#define m_ivt_start 0x60001000 +#define m_ivt_size 0x00001000 + +#define m_interrupts_start 0x60002000 +#define m_interrupts_size 0x00000400 + +#define m_text_start 0x60002400 +#define m_text_size 0x007FDC00 + +#define m_data_start 0x20000000 +#define m_data_size 0x00020000 + +#define m_data2_start 0x20200000 +#define m_data2_size 0x000C0000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region + RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address + * (.boot_hdr.conf, +FIRST) + } + + RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address + * (.boot_hdr.ivt, +FIRST) + * (.boot_hdr.boot_data) + * (.boot_hdr.dcd_data) + } +#else +LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region +#endif + VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + * (NonCacheable.init) + * (NonCacheable) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/MIMXRT1061xxxxx_flexspi_nor_sdram.scf b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/MIMXRT1061xxxxx_flexspi_nor_sdram.scf new file mode 100644 index 0000000000..267e4be1d2 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/MIMXRT1061xxxxx_flexspi_nor_sdram.scf @@ -0,0 +1,100 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MIMXRT1061CVJ5A +** MIMXRT1061CVL5A +** MIMXRT1061DVJ6A +** MIMXRT1061DVL6A +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1060RM Rev.1, 12/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b190312 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_flash_config_start 0x60000000 +#define m_flash_config_size 0x00001000 + +#define m_ivt_start 0x60001000 +#define m_ivt_size 0x00001000 + +#define m_interrupts_start 0x60002000 +#define m_interrupts_size 0x00000400 + +#define m_text_start 0x60002400 +#define m_text_size 0x007FDC00 + +#define m_data_start 0x80000000 +#define m_data_size 0x01E00000 + +#define m_ncache_start 0x81E00000 +#define m_ncache_size 0x00200000 + +#define m_data2_start 0x20000000 +#define m_data2_size 0x00020000 + +#define m_data3_start 0x20200000 +#define m_data3_size 0x000C0000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region + RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address + * (.boot_hdr.conf, +FIRST) + } + + RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address + * (.boot_hdr.ivt, +FIRST) + * (.boot_hdr.boot_data) + * (.boot_hdr.dcd_data) + } +#else +LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region +#endif + VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + *(m_usb_dma_init_data) + *(m_usb_dma_noninit_data) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data + * (NonCacheable.init) + * (NonCacheable) + } +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/MIMXRT1061xxxxx_ram.scf b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/MIMXRT1061xxxxx_ram.scf new file mode 100644 index 0000000000..58f84b2251 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/MIMXRT1061xxxxx_ram.scf @@ -0,0 +1,71 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MIMXRT1061CVJ5A +** MIMXRT1061CVL5A +** MIMXRT1061DVJ6A +** MIMXRT1061DVL6A +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1060RM Rev.1, 12/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b190312 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000400 + +#define m_text_start 0x00000400 +#define m_text_size 0x0001FC00 + +#define m_data_start 0x20000000 +#define m_data_size 0x00020000 + +#define m_data2_start 0x20200000 +#define m_data2_size 0x000C0000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region + VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + * (NonCacheable.init) + * (NonCacheable) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/MIMXRT1061xxxxx_sdram.scf b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/MIMXRT1061xxxxx_sdram.scf new file mode 100644 index 0000000000..5accb0c271 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/MIMXRT1061xxxxx_sdram.scf @@ -0,0 +1,81 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MIMXRT1061CVJ5A +** MIMXRT1061CVL5A +** MIMXRT1061DVJ6A +** MIMXRT1061DVL6A +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1060RM Rev.1, 12/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b190312 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000400 + +#define m_text_start 0x00000400 +#define m_text_size 0x0001FC00 + +#define m_data_start 0x80000000 +#define m_data_size 0x01E00000 + +#define m_ncache_start 0x81E00000 +#define m_ncache_size 0x00200000 + +#define m_data2_start 0x20000000 +#define m_data2_size 0x00020000 + +#define m_data3_start 0x20200000 +#define m_data3_size 0x000C0000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region + VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + *(m_usb_dma_init_data) + *(m_usb_dma_noninit_data) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data + * (NonCacheable.init) + * (NonCacheable) + } +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/MIMXRT1061xxxxx_sdram_txt.scf b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/MIMXRT1061xxxxx_sdram_txt.scf new file mode 100644 index 0000000000..bcbf41ac50 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/MIMXRT1061xxxxx_sdram_txt.scf @@ -0,0 +1,81 @@ +#! armcc -E +/* +** ################################################################### +** Processors: MIMXRT1061CVJ5A +** MIMXRT1061CVL5A +** MIMXRT1061DVJ6A +** MIMXRT1061DVL6A +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: IMXRT1060RM Rev.1, 12/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b190312 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +#define m_interrupts_start 0x80000000 +#define m_interrupts_size 0x00000400 + +#define m_text_start 0x80000400 +#define m_text_size 0x001FFC00 + +#define m_data_start 0x20200000 +#define m_data_size 0x000C0000 + +#define m_data2_start 0x20000000 +#define m_data2_size 0x00020000 + +#define m_data3_start 0x80200000 +#define m_data3_size 0x01C00000 + +#define m_ncache_start 0x81E00000 +#define m_ncache_size 0x00200000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region + VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + *(m_usb_dma_init_data) + *(m_usb_dma_noninit_data) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data + * (NonCacheable.init) + * (NonCacheable) + } +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/MIMXRT106x_QSPI_4KB_SEC.FLM b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/MIMXRT106x_QSPI_4KB_SEC.FLM new file mode 100644 index 0000000000000000000000000000000000000000..be10fdfb859d6141e64daf7591af9535c16a6b69 GIT binary patch literal 2847664 zcmeFadwf*Y)i-|5>;wV?iGg4Q9HT*{5p8Zjyi_xpOEQwnI5PoM?0^I%%B@@!pZc^> zK|xT_;vHMsQfq6qRPj=)E#9xKC|EDmO0BKdTE&VjT9w~-?aMj)oY^One%{~v&->Bm zp*d@<@7jCqwXbLGefE4i-kz{++fx69tO=H)o?LvSRq~A^Eh}UdH(FKrGr`*5DzlpJ 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z4dUPq2G*;`w$wc-^Jj7@9NhANX9qMl#Sw4bz<<=A!Kr)9DzCb)qckX-;&1*8PTgx( zIP>@8|D#g574G+#KU4P?aKOA)b&vjsO63qEiq$E79Jlh9mCCc~hAI7-y1#<5d9AAc z>P2{nhY2=yy$Rg2@4_=6>V`V~8Jv3V#JpBj%f5m~hZfEtR8+SrfxC15)|EE8AEm(N zJ$8oI5o;*)ZCyDTJXERwEBsUbDLelW{;6|e{!ZRu>&lzz1ks;)zrCQ$(p2^t+Pczc nK=5C4J`RA_CPr1C4Y=LZ%~$#}bw@y%=bf<@_!$uV*Wms?jG1$2 literal 0 HcmV?d00001 diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/startup_MIMXRT1061.s b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/startup_MIMXRT1061.s new file mode 100644 index 0000000000..21d9644381 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/arm/startup_MIMXRT1061.s @@ -0,0 +1,1063 @@ +; * ------------------------------------------------------------------------- +; * @file: startup_MIMXRT1061.s +; * @purpose: CMSIS Cortex-M7 Core Device Startup File +; * MIMXRT1061 +; * @version: 1.1 +; * @date: 2018-11-27 +; * @build: b190124 +; * ------------------------------------------------------------------------- +; * +; * Copyright 1997-2016 Freescale Semiconductor, Inc. +; * Copyright 2016-2019 NXP +; * All rights reserved. +; * +; * SPDX-License-Identifier: BSD-3-Clause +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_DMA16_IRQHandler ;DMA channel 0/16 transfer complete + DCD DMA1_DMA17_IRQHandler ;DMA channel 1/17 transfer complete + DCD DMA2_DMA18_IRQHandler ;DMA channel 2/18 transfer complete + DCD DMA3_DMA19_IRQHandler ;DMA channel 3/19 transfer complete + DCD DMA4_DMA20_IRQHandler ;DMA channel 4/20 transfer complete + DCD DMA5_DMA21_IRQHandler ;DMA channel 5/21 transfer complete + DCD DMA6_DMA22_IRQHandler ;DMA channel 6/22 transfer complete + DCD DMA7_DMA23_IRQHandler ;DMA channel 7/23 transfer complete + DCD DMA8_DMA24_IRQHandler ;DMA channel 8/24 transfer complete + DCD DMA9_DMA25_IRQHandler ;DMA channel 9/25 transfer complete + DCD DMA10_DMA26_IRQHandler ;DMA channel 10/26 transfer complete + DCD DMA11_DMA27_IRQHandler ;DMA channel 11/27 transfer complete + DCD DMA12_DMA28_IRQHandler ;DMA channel 12/28 transfer complete + DCD DMA13_DMA29_IRQHandler ;DMA channel 13/29 transfer complete + DCD DMA14_DMA30_IRQHandler ;DMA channel 14/30 transfer complete + DCD DMA15_DMA31_IRQHandler ;DMA channel 15/31 transfer complete + DCD DMA_ERROR_IRQHandler ;DMA error interrupt channels 0-15 / 16-31 + DCD CTI0_ERROR_IRQHandler ;CTI0_Error + DCD CTI1_ERROR_IRQHandler ;CTI1_Error + DCD CORE_IRQHandler ;CorePlatform exception IRQ + DCD LPUART1_IRQHandler ;LPUART1 TX interrupt and RX interrupt + DCD LPUART2_IRQHandler ;LPUART2 TX interrupt and RX interrupt + DCD LPUART3_IRQHandler ;LPUART3 TX interrupt and RX interrupt + DCD LPUART4_IRQHandler ;LPUART4 TX interrupt and RX interrupt + DCD LPUART5_IRQHandler ;LPUART5 TX interrupt and RX interrupt + DCD LPUART6_IRQHandler ;LPUART6 TX interrupt and RX interrupt + DCD LPUART7_IRQHandler ;LPUART7 TX interrupt and RX interrupt + DCD LPUART8_IRQHandler ;LPUART8 TX interrupt and RX interrupt + DCD LPI2C1_IRQHandler ;LPI2C1 interrupt + DCD LPI2C2_IRQHandler ;LPI2C2 interrupt + DCD LPI2C3_IRQHandler ;LPI2C3 interrupt + DCD LPI2C4_IRQHandler ;LPI2C4 interrupt + DCD LPSPI1_IRQHandler ;LPSPI1 single interrupt vector for all sources + DCD LPSPI2_IRQHandler ;LPSPI2 single interrupt vector for all sources + DCD LPSPI3_IRQHandler ;LPSPI3 single interrupt vector for all sources + DCD LPSPI4_IRQHandler ;LPSPI4 single interrupt vector for all sources + DCD CAN1_IRQHandler ;CAN1 interrupt + DCD CAN2_IRQHandler ;CAN2 interrupt + DCD FLEXRAM_IRQHandler ;FlexRAM address out of range Or access hit IRQ + DCD KPP_IRQHandler ;Keypad nterrupt + DCD TSC_DIG_IRQHandler ;TSC interrupt + DCD GPR_IRQ_IRQHandler ;GPR interrupt + DCD Reserved58_IRQHandler ;Reserved interrupt + DCD Reserved59_IRQHandler ;Reserved interrupt + DCD Reserved60_IRQHandler ;Reserved interrupt + DCD WDOG2_IRQHandler ;WDOG2 interrupt + DCD SNVS_HP_WRAPPER_IRQHandler ;SRTC Consolidated Interrupt. Non TZ + DCD SNVS_HP_WRAPPER_TZ_IRQHandler ;SRTC Security Interrupt. TZ + DCD SNVS_LP_WRAPPER_IRQHandler ;ON-OFF button press shorter than 5 secs (pulse event) + DCD CSU_IRQHandler ;CSU interrupt + DCD DCP_IRQHandler ;DCP_IRQ interrupt + DCD DCP_VMI_IRQHandler ;DCP_VMI_IRQ interrupt + DCD Reserved68_IRQHandler ;Reserved interrupt + DCD TRNG_IRQHandler ;TRNG interrupt + DCD SJC_IRQHandler ;SJC interrupt + DCD BEE_IRQHandler ;BEE interrupt + DCD SAI1_IRQHandler ;SAI1 interrupt + DCD SAI2_IRQHandler ;SAI1 interrupt + DCD SAI3_RX_IRQHandler ;SAI3 interrupt + DCD SAI3_TX_IRQHandler ;SAI3 interrupt + DCD SPDIF_IRQHandler ;SPDIF interrupt + DCD PMU_EVENT_IRQHandler ;Brown-out event interrupt + DCD Reserved78_IRQHandler ;Reserved interrupt + DCD TEMP_LOW_HIGH_IRQHandler ;TempSensor low/high interrupt + DCD TEMP_PANIC_IRQHandler ;TempSensor panic interrupt + DCD USB_PHY1_IRQHandler ;USBPHY (UTMI0), Interrupt + DCD USB_PHY2_IRQHandler ;USBPHY (UTMI1), Interrupt + DCD ADC1_IRQHandler ;ADC1 interrupt + DCD ADC2_IRQHandler ;ADC2 interrupt + DCD DCDC_IRQHandler ;DCDC interrupt + DCD Reserved86_IRQHandler ;Reserved interrupt + DCD Reserved87_IRQHandler ;Reserved interrupt + DCD GPIO1_INT0_IRQHandler ;Active HIGH Interrupt from INT0 from GPIO + DCD GPIO1_INT1_IRQHandler ;Active HIGH Interrupt from INT1 from GPIO + DCD GPIO1_INT2_IRQHandler ;Active HIGH Interrupt from INT2 from GPIO + DCD GPIO1_INT3_IRQHandler ;Active HIGH Interrupt from INT3 from GPIO + DCD GPIO1_INT4_IRQHandler ;Active HIGH Interrupt from INT4 from GPIO + DCD GPIO1_INT5_IRQHandler ;Active HIGH Interrupt from INT5 from GPIO + DCD GPIO1_INT6_IRQHandler ;Active HIGH Interrupt from INT6 from GPIO + DCD GPIO1_INT7_IRQHandler ;Active HIGH Interrupt from INT7 from GPIO + DCD GPIO1_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO1 signal 0 throughout 15 + DCD GPIO1_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO1 signal 16 throughout 31 + DCD GPIO2_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO2 signal 0 throughout 15 + DCD GPIO2_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO2 signal 16 throughout 31 + DCD GPIO3_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO3 signal 0 throughout 15 + DCD GPIO3_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO3 signal 16 throughout 31 + DCD GPIO4_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO4 signal 0 throughout 15 + DCD GPIO4_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO4 signal 16 throughout 31 + DCD GPIO5_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO5 signal 0 throughout 15 + DCD GPIO5_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO5 signal 16 throughout 31 + DCD FLEXIO1_IRQHandler ;FLEXIO1 interrupt + DCD FLEXIO2_IRQHandler ;FLEXIO2 interrupt + DCD WDOG1_IRQHandler ;WDOG1 interrupt + DCD RTWDOG_IRQHandler ;RTWDOG interrupt + DCD EWM_IRQHandler ;EWM interrupt + DCD CCM_1_IRQHandler ;CCM IRQ1 interrupt + DCD CCM_2_IRQHandler ;CCM IRQ2 interrupt + DCD GPC_IRQHandler ;GPC interrupt + DCD SRC_IRQHandler ;SRC interrupt + DCD Reserved115_IRQHandler ;Reserved interrupt + DCD GPT1_IRQHandler ;GPT1 interrupt + DCD GPT2_IRQHandler ;GPT2 interrupt + DCD PWM1_0_IRQHandler ;PWM1 capture 0, compare 0, or reload 0 interrupt + DCD PWM1_1_IRQHandler ;PWM1 capture 1, compare 1, or reload 0 interrupt + DCD PWM1_2_IRQHandler ;PWM1 capture 2, compare 2, or reload 0 interrupt + DCD PWM1_3_IRQHandler ;PWM1 capture 3, compare 3, or reload 0 interrupt + DCD PWM1_FAULT_IRQHandler ;PWM1 fault or reload error interrupt + DCD FLEXSPI2_IRQHandler ;FlexSPI2 interrupt + DCD FLEXSPI_IRQHandler ;FlexSPI0 interrupt + DCD SEMC_IRQHandler ;Reserved interrupt + DCD USDHC1_IRQHandler ;USDHC1 interrupt + DCD USDHC2_IRQHandler ;USDHC2 interrupt + DCD USB_OTG2_IRQHandler ;USBO2 USB OTG2 + DCD USB_OTG1_IRQHandler ;USBO2 USB OTG1 + DCD ENET_IRQHandler ;ENET interrupt + DCD ENET_1588_Timer_IRQHandler ;ENET_1588_Timer interrupt + DCD XBAR1_IRQ_0_1_IRQHandler ;XBAR1 interrupt + DCD XBAR1_IRQ_2_3_IRQHandler ;XBAR1 interrupt + DCD ADC_ETC_IRQ0_IRQHandler ;ADCETC IRQ0 interrupt + DCD ADC_ETC_IRQ1_IRQHandler ;ADCETC IRQ1 interrupt + DCD ADC_ETC_IRQ2_IRQHandler ;ADCETC IRQ2 interrupt + DCD ADC_ETC_ERROR_IRQ_IRQHandler ;ADCETC Error IRQ interrupt + DCD PIT_IRQHandler ;PIT interrupt + DCD ACMP1_IRQHandler ;ACMP interrupt + DCD ACMP2_IRQHandler ;ACMP interrupt + DCD ACMP3_IRQHandler ;ACMP interrupt + DCD ACMP4_IRQHandler ;ACMP interrupt + DCD Reserved143_IRQHandler ;Reserved interrupt + DCD Reserved144_IRQHandler ;Reserved interrupt + DCD ENC1_IRQHandler ;ENC1 interrupt + DCD ENC2_IRQHandler ;ENC2 interrupt + DCD ENC3_IRQHandler ;ENC3 interrupt + DCD ENC4_IRQHandler ;ENC4 interrupt + DCD TMR1_IRQHandler ;TMR1 interrupt + DCD TMR2_IRQHandler ;TMR2 interrupt + DCD TMR3_IRQHandler ;TMR3 interrupt + DCD TMR4_IRQHandler ;TMR4 interrupt + DCD PWM2_0_IRQHandler ;PWM2 capture 0, compare 0, or reload 0 interrupt + DCD PWM2_1_IRQHandler ;PWM2 capture 1, compare 1, or reload 0 interrupt + DCD PWM2_2_IRQHandler ;PWM2 capture 2, compare 2, or reload 0 interrupt + DCD PWM2_3_IRQHandler ;PWM2 capture 3, compare 3, or reload 0 interrupt + DCD PWM2_FAULT_IRQHandler ;PWM2 fault or reload error interrupt + DCD PWM3_0_IRQHandler ;PWM3 capture 0, compare 0, or reload 0 interrupt + DCD PWM3_1_IRQHandler ;PWM3 capture 1, compare 1, or reload 0 interrupt + DCD PWM3_2_IRQHandler ;PWM3 capture 2, compare 2, or reload 0 interrupt + DCD PWM3_3_IRQHandler ;PWM3 capture 3, compare 3, or reload 0 interrupt + DCD PWM3_FAULT_IRQHandler ;PWM3 fault or reload error interrupt + DCD PWM4_0_IRQHandler ;PWM4 capture 0, compare 0, or reload 0 interrupt + DCD PWM4_1_IRQHandler ;PWM4 capture 1, compare 1, or reload 0 interrupt + DCD PWM4_2_IRQHandler ;PWM4 capture 2, compare 2, or reload 0 interrupt + DCD PWM4_3_IRQHandler ;PWM4 capture 3, compare 3, or reload 0 interrupt + DCD PWM4_FAULT_IRQHandler ;PWM4 fault or reload error interrupt + DCD ENET2_IRQHandler ;ENET2 interrupt + DCD ENET2_1588_Timer_IRQHandler ;ENET2_1588_Timer interrupt + DCD CAN3_IRQHandler ;CAN3 interrupt + DCD Reserved171_IRQHandler ;Reserved interrupt + DCD FLEXIO3_IRQHandler ;FLEXIO3 interrupt + DCD GPIO6_7_8_9_IRQHandler ;GPIO6, GPIO7, GPIO8, GPIO9 interrupt + DCD DefaultISR ;174 + DCD DefaultISR ;175 + DCD DefaultISR ;176 + DCD DefaultISR ;177 + DCD DefaultISR ;178 + DCD DefaultISR ;179 + DCD DefaultISR ;180 + DCD DefaultISR ;181 + DCD DefaultISR ;182 + DCD DefaultISR ;183 + DCD DefaultISR ;184 + DCD DefaultISR ;185 + DCD DefaultISR ;186 + DCD DefaultISR ;187 + DCD DefaultISR ;188 + DCD DefaultISR ;189 + DCD DefaultISR ;190 + DCD DefaultISR ;191 + DCD DefaultISR ;192 + DCD DefaultISR ;193 + DCD DefaultISR ;194 + DCD DefaultISR ;195 + DCD DefaultISR ;196 + DCD DefaultISR ;197 + DCD DefaultISR ;198 + DCD DefaultISR ;199 + DCD DefaultISR ;200 + DCD DefaultISR ;201 + DCD DefaultISR ;202 + DCD DefaultISR ;203 + DCD DefaultISR ;204 + DCD DefaultISR ;205 + DCD DefaultISR ;206 + DCD DefaultISR ;207 + DCD DefaultISR ;208 + DCD DefaultISR ;209 + DCD DefaultISR ;210 + DCD DefaultISR ;211 + DCD DefaultISR ;212 + DCD DefaultISR ;213 + DCD DefaultISR ;214 + DCD DefaultISR ;215 + DCD DefaultISR ;216 + DCD DefaultISR ;217 + DCD DefaultISR ;218 + DCD DefaultISR ;219 + DCD DefaultISR ;220 + DCD DefaultISR ;221 + DCD DefaultISR ;222 + DCD DefaultISR ;223 + DCD DefaultISR ;224 + DCD DefaultISR ;225 + DCD DefaultISR ;226 + DCD DefaultISR ;227 + DCD DefaultISR ;228 + DCD DefaultISR ;229 + DCD DefaultISR ;230 + DCD DefaultISR ;231 + DCD DefaultISR ;232 + DCD DefaultISR ;233 + DCD DefaultISR ;234 + DCD DefaultISR ;235 + DCD DefaultISR ;236 + DCD DefaultISR ;237 + DCD DefaultISR ;238 + DCD DefaultISR ;239 + DCD DefaultISR ;240 + DCD DefaultISR ;241 + DCD DefaultISR ;242 + DCD DefaultISR ;243 + DCD DefaultISR ;244 + DCD DefaultISR ;245 + DCD DefaultISR ;246 + DCD DefaultISR ;247 + DCD DefaultISR ;248 + DCD DefaultISR ;249 + DCD DefaultISR ;250 + DCD DefaultISR ;251 + DCD DefaultISR ;252 + DCD DefaultISR ;253 + DCD DefaultISR ;254 + DCD 0xFFFFFFFF ; Reserved for user TRIM value +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__Vectors + STR R1, [R0] + LDR R2, [R1] + MSR MSP, R2 + + LDR R0, =0x400AC044 ; IOMUXC_GPR_GPR17 + LDR R1, =0x55555555 ; 1MB OCRAM + STR R1, [R0] + + LDR R0, =0x400AC040 ; IOMUXC_GPR_GPR16 + LDR R1, =0x00000007 ; + STR R1, [R0] + + LDR R0, =SystemInit + BLX R0 + CPSIE i ; Unmask interrupts + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +DMA0_DMA16_IRQHandler\ + PROC + EXPORT DMA0_DMA16_IRQHandler [WEAK] + LDR R0, =DMA0_DMA16_DriverIRQHandler + BX R0 + ENDP + +DMA1_DMA17_IRQHandler\ + PROC + EXPORT DMA1_DMA17_IRQHandler [WEAK] + LDR R0, =DMA1_DMA17_DriverIRQHandler + BX R0 + ENDP + +DMA2_DMA18_IRQHandler\ + PROC + EXPORT DMA2_DMA18_IRQHandler [WEAK] + LDR R0, =DMA2_DMA18_DriverIRQHandler + BX R0 + ENDP + +DMA3_DMA19_IRQHandler\ + PROC + EXPORT DMA3_DMA19_IRQHandler [WEAK] + LDR R0, =DMA3_DMA19_DriverIRQHandler + BX R0 + ENDP + +DMA4_DMA20_IRQHandler\ + PROC + EXPORT DMA4_DMA20_IRQHandler [WEAK] + LDR R0, =DMA4_DMA20_DriverIRQHandler + BX R0 + ENDP + +DMA5_DMA21_IRQHandler\ + PROC + EXPORT DMA5_DMA21_IRQHandler [WEAK] + LDR R0, =DMA5_DMA21_DriverIRQHandler + BX R0 + ENDP + +DMA6_DMA22_IRQHandler\ + PROC + EXPORT DMA6_DMA22_IRQHandler [WEAK] + LDR R0, =DMA6_DMA22_DriverIRQHandler + BX R0 + ENDP + +DMA7_DMA23_IRQHandler\ + PROC + EXPORT DMA7_DMA23_IRQHandler [WEAK] + LDR R0, =DMA7_DMA23_DriverIRQHandler + BX R0 + ENDP + +DMA8_DMA24_IRQHandler\ + PROC + EXPORT DMA8_DMA24_IRQHandler [WEAK] + LDR R0, =DMA8_DMA24_DriverIRQHandler + BX R0 + ENDP + +DMA9_DMA25_IRQHandler\ + PROC + EXPORT DMA9_DMA25_IRQHandler [WEAK] + LDR R0, =DMA9_DMA25_DriverIRQHandler + BX R0 + ENDP + +DMA10_DMA26_IRQHandler\ + PROC + EXPORT DMA10_DMA26_IRQHandler [WEAK] + LDR R0, =DMA10_DMA26_DriverIRQHandler + BX R0 + ENDP + +DMA11_DMA27_IRQHandler\ + PROC + EXPORT DMA11_DMA27_IRQHandler [WEAK] + LDR R0, =DMA11_DMA27_DriverIRQHandler + BX R0 + ENDP + +DMA12_DMA28_IRQHandler\ + PROC + EXPORT DMA12_DMA28_IRQHandler [WEAK] + LDR R0, =DMA12_DMA28_DriverIRQHandler + BX R0 + ENDP + +DMA13_DMA29_IRQHandler\ + PROC + EXPORT DMA13_DMA29_IRQHandler [WEAK] + LDR R0, =DMA13_DMA29_DriverIRQHandler + BX R0 + ENDP + +DMA14_DMA30_IRQHandler\ + PROC + EXPORT DMA14_DMA30_IRQHandler [WEAK] + LDR R0, =DMA14_DMA30_DriverIRQHandler + BX R0 + ENDP + +DMA15_DMA31_IRQHandler\ + PROC + EXPORT DMA15_DMA31_IRQHandler [WEAK] + LDR R0, =DMA15_DMA31_DriverIRQHandler + BX R0 + ENDP + +DMA_ERROR_IRQHandler\ + PROC + EXPORT DMA_ERROR_IRQHandler [WEAK] + LDR R0, =DMA_ERROR_DriverIRQHandler + BX R0 + ENDP + +LPUART1_IRQHandler\ + PROC + EXPORT LPUART1_IRQHandler [WEAK] + LDR R0, =LPUART1_DriverIRQHandler + BX R0 + ENDP + +LPUART2_IRQHandler\ + PROC + EXPORT LPUART2_IRQHandler [WEAK] + LDR R0, =LPUART2_DriverIRQHandler + BX R0 + ENDP + +LPUART3_IRQHandler\ + PROC + EXPORT LPUART3_IRQHandler [WEAK] + LDR R0, =LPUART3_DriverIRQHandler + BX R0 + ENDP + +LPUART4_IRQHandler\ + PROC + EXPORT LPUART4_IRQHandler [WEAK] + LDR R0, =LPUART4_DriverIRQHandler + BX R0 + ENDP + +LPUART5_IRQHandler\ + PROC + EXPORT LPUART5_IRQHandler [WEAK] + LDR R0, =LPUART5_DriverIRQHandler + BX R0 + ENDP + +LPUART6_IRQHandler\ + PROC + EXPORT LPUART6_IRQHandler [WEAK] + LDR R0, =LPUART6_DriverIRQHandler + BX R0 + ENDP + +LPUART7_IRQHandler\ + PROC + EXPORT LPUART7_IRQHandler [WEAK] + LDR R0, =LPUART7_DriverIRQHandler + BX R0 + ENDP + +LPUART8_IRQHandler\ + PROC + EXPORT LPUART8_IRQHandler [WEAK] + LDR R0, =LPUART8_DriverIRQHandler + BX R0 + ENDP + +LPI2C1_IRQHandler\ + PROC + EXPORT LPI2C1_IRQHandler [WEAK] + LDR R0, =LPI2C1_DriverIRQHandler + BX R0 + ENDP + +LPI2C2_IRQHandler\ + PROC + EXPORT LPI2C2_IRQHandler [WEAK] + LDR R0, =LPI2C2_DriverIRQHandler + BX R0 + ENDP + +LPI2C3_IRQHandler\ + PROC + EXPORT LPI2C3_IRQHandler [WEAK] + LDR R0, =LPI2C3_DriverIRQHandler + BX R0 + ENDP + +LPI2C4_IRQHandler\ + PROC + EXPORT LPI2C4_IRQHandler [WEAK] + LDR R0, =LPI2C4_DriverIRQHandler + BX R0 + ENDP + +LPSPI1_IRQHandler\ + PROC + EXPORT LPSPI1_IRQHandler [WEAK] + LDR R0, =LPSPI1_DriverIRQHandler + BX R0 + ENDP + +LPSPI2_IRQHandler\ + PROC + EXPORT LPSPI2_IRQHandler [WEAK] + LDR R0, =LPSPI2_DriverIRQHandler + BX R0 + ENDP + +LPSPI3_IRQHandler\ + PROC + EXPORT LPSPI3_IRQHandler [WEAK] + LDR R0, =LPSPI3_DriverIRQHandler + BX R0 + ENDP + +LPSPI4_IRQHandler\ + PROC + EXPORT LPSPI4_IRQHandler [WEAK] + LDR R0, =LPSPI4_DriverIRQHandler + BX R0 + ENDP + +CAN1_IRQHandler\ + PROC + EXPORT CAN1_IRQHandler [WEAK] + LDR R0, =CAN1_DriverIRQHandler + BX R0 + ENDP + +CAN2_IRQHandler\ + PROC + EXPORT CAN2_IRQHandler [WEAK] + LDR R0, =CAN2_DriverIRQHandler + BX R0 + ENDP + +SAI1_IRQHandler\ + PROC + EXPORT SAI1_IRQHandler [WEAK] + LDR R0, =SAI1_DriverIRQHandler + BX R0 + ENDP + +SAI2_IRQHandler\ + PROC + EXPORT SAI2_IRQHandler [WEAK] + LDR R0, =SAI2_DriverIRQHandler + BX R0 + ENDP + +SAI3_RX_IRQHandler\ + PROC + EXPORT SAI3_RX_IRQHandler [WEAK] + LDR R0, =SAI3_RX_DriverIRQHandler + BX R0 + ENDP + +SAI3_TX_IRQHandler\ + PROC + EXPORT SAI3_TX_IRQHandler [WEAK] + LDR R0, =SAI3_TX_DriverIRQHandler + BX R0 + ENDP + +SPDIF_IRQHandler\ + PROC + EXPORT SPDIF_IRQHandler [WEAK] + LDR R0, =SPDIF_DriverIRQHandler + BX R0 + ENDP + +FLEXIO1_IRQHandler\ + PROC + EXPORT FLEXIO1_IRQHandler [WEAK] + LDR R0, =FLEXIO1_DriverIRQHandler + BX R0 + ENDP + +FLEXIO2_IRQHandler\ + PROC + EXPORT FLEXIO2_IRQHandler [WEAK] + LDR R0, =FLEXIO2_DriverIRQHandler + BX R0 + ENDP + +FLEXSPI2_IRQHandler\ + PROC + EXPORT FLEXSPI2_IRQHandler [WEAK] + LDR R0, =FLEXSPI2_DriverIRQHandler + BX R0 + ENDP + +FLEXSPI_IRQHandler\ + PROC + EXPORT FLEXSPI_IRQHandler [WEAK] + LDR R0, =FLEXSPI_DriverIRQHandler + BX R0 + ENDP + +USDHC1_IRQHandler\ + PROC + EXPORT USDHC1_IRQHandler [WEAK] + LDR R0, =USDHC1_DriverIRQHandler + BX R0 + ENDP + +USDHC2_IRQHandler\ + PROC + EXPORT USDHC2_IRQHandler [WEAK] + LDR R0, =USDHC2_DriverIRQHandler + BX R0 + ENDP + +ENET_IRQHandler\ + PROC + EXPORT ENET_IRQHandler [WEAK] + LDR R0, =ENET_DriverIRQHandler + BX R0 + ENDP + +ENET_1588_Timer_IRQHandler\ + PROC + EXPORT ENET_1588_Timer_IRQHandler [WEAK] + LDR R0, =ENET_1588_Timer_DriverIRQHandler + BX R0 + ENDP + +ENET2_IRQHandler\ + PROC + EXPORT ENET2_IRQHandler [WEAK] + LDR R0, =ENET2_DriverIRQHandler + BX R0 + ENDP + +ENET2_1588_Timer_IRQHandler\ + PROC + EXPORT ENET2_1588_Timer_IRQHandler [WEAK] + LDR R0, =ENET2_1588_Timer_DriverIRQHandler + BX R0 + ENDP + +CAN3_IRQHandler\ + PROC + EXPORT CAN3_IRQHandler [WEAK] + LDR R0, =CAN3_DriverIRQHandler + BX R0 + ENDP + +FLEXIO3_IRQHandler\ + PROC + EXPORT FLEXIO3_IRQHandler [WEAK] + LDR R0, =FLEXIO3_DriverIRQHandler + BX R0 + ENDP + +Default_Handler\ + PROC + EXPORT DMA0_DMA16_DriverIRQHandler [WEAK] + EXPORT DMA1_DMA17_DriverIRQHandler [WEAK] + EXPORT DMA2_DMA18_DriverIRQHandler [WEAK] + EXPORT DMA3_DMA19_DriverIRQHandler [WEAK] + EXPORT DMA4_DMA20_DriverIRQHandler [WEAK] + EXPORT DMA5_DMA21_DriverIRQHandler [WEAK] + EXPORT DMA6_DMA22_DriverIRQHandler [WEAK] + EXPORT DMA7_DMA23_DriverIRQHandler [WEAK] + EXPORT DMA8_DMA24_DriverIRQHandler [WEAK] + EXPORT DMA9_DMA25_DriverIRQHandler [WEAK] + EXPORT DMA10_DMA26_DriverIRQHandler [WEAK] + EXPORT DMA11_DMA27_DriverIRQHandler [WEAK] + EXPORT DMA12_DMA28_DriverIRQHandler [WEAK] + EXPORT DMA13_DMA29_DriverIRQHandler [WEAK] + EXPORT DMA14_DMA30_DriverIRQHandler [WEAK] + EXPORT DMA15_DMA31_DriverIRQHandler [WEAK] + EXPORT DMA_ERROR_DriverIRQHandler [WEAK] + EXPORT CTI0_ERROR_IRQHandler [WEAK] + EXPORT CTI1_ERROR_IRQHandler [WEAK] + EXPORT CORE_IRQHandler [WEAK] + EXPORT LPUART1_DriverIRQHandler [WEAK] + EXPORT LPUART2_DriverIRQHandler [WEAK] + EXPORT LPUART3_DriverIRQHandler [WEAK] + EXPORT LPUART4_DriverIRQHandler [WEAK] + EXPORT LPUART5_DriverIRQHandler [WEAK] + EXPORT LPUART6_DriverIRQHandler [WEAK] + EXPORT LPUART7_DriverIRQHandler [WEAK] + EXPORT LPUART8_DriverIRQHandler [WEAK] + EXPORT LPI2C1_DriverIRQHandler [WEAK] + EXPORT LPI2C2_DriverIRQHandler [WEAK] + EXPORT LPI2C3_DriverIRQHandler [WEAK] + EXPORT LPI2C4_DriverIRQHandler [WEAK] + EXPORT LPSPI1_DriverIRQHandler [WEAK] + EXPORT LPSPI2_DriverIRQHandler [WEAK] + EXPORT LPSPI3_DriverIRQHandler [WEAK] + EXPORT LPSPI4_DriverIRQHandler [WEAK] + EXPORT CAN1_DriverIRQHandler [WEAK] + EXPORT CAN2_DriverIRQHandler [WEAK] + EXPORT FLEXRAM_IRQHandler [WEAK] + EXPORT KPP_IRQHandler [WEAK] + EXPORT TSC_DIG_IRQHandler [WEAK] + EXPORT GPR_IRQ_IRQHandler [WEAK] + EXPORT Reserved58_IRQHandler [WEAK] + EXPORT Reserved59_IRQHandler [WEAK] + EXPORT Reserved60_IRQHandler [WEAK] + EXPORT WDOG2_IRQHandler [WEAK] + EXPORT SNVS_HP_WRAPPER_IRQHandler [WEAK] + EXPORT SNVS_HP_WRAPPER_TZ_IRQHandler [WEAK] + EXPORT SNVS_LP_WRAPPER_IRQHandler [WEAK] + EXPORT CSU_IRQHandler [WEAK] + EXPORT DCP_IRQHandler [WEAK] + EXPORT DCP_VMI_IRQHandler [WEAK] + EXPORT Reserved68_IRQHandler [WEAK] + EXPORT TRNG_IRQHandler [WEAK] + EXPORT SJC_IRQHandler [WEAK] + EXPORT BEE_IRQHandler [WEAK] + EXPORT SAI1_DriverIRQHandler [WEAK] + EXPORT SAI2_DriverIRQHandler [WEAK] + EXPORT SAI3_RX_DriverIRQHandler [WEAK] + EXPORT SAI3_TX_DriverIRQHandler [WEAK] + EXPORT SPDIF_DriverIRQHandler [WEAK] + EXPORT PMU_EVENT_IRQHandler [WEAK] + EXPORT Reserved78_IRQHandler [WEAK] + EXPORT TEMP_LOW_HIGH_IRQHandler [WEAK] + EXPORT TEMP_PANIC_IRQHandler [WEAK] + EXPORT USB_PHY1_IRQHandler [WEAK] + EXPORT USB_PHY2_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT ADC2_IRQHandler [WEAK] + EXPORT DCDC_IRQHandler [WEAK] + EXPORT Reserved86_IRQHandler [WEAK] + EXPORT Reserved87_IRQHandler [WEAK] + EXPORT GPIO1_INT0_IRQHandler [WEAK] + EXPORT GPIO1_INT1_IRQHandler [WEAK] + EXPORT GPIO1_INT2_IRQHandler [WEAK] + EXPORT GPIO1_INT3_IRQHandler [WEAK] + EXPORT GPIO1_INT4_IRQHandler [WEAK] + EXPORT GPIO1_INT5_IRQHandler [WEAK] + EXPORT GPIO1_INT6_IRQHandler [WEAK] + EXPORT GPIO1_INT7_IRQHandler [WEAK] + EXPORT GPIO1_Combined_0_15_IRQHandler [WEAK] + EXPORT GPIO1_Combined_16_31_IRQHandler [WEAK] + EXPORT GPIO2_Combined_0_15_IRQHandler [WEAK] + EXPORT GPIO2_Combined_16_31_IRQHandler [WEAK] + EXPORT GPIO3_Combined_0_15_IRQHandler [WEAK] + EXPORT GPIO3_Combined_16_31_IRQHandler [WEAK] + EXPORT GPIO4_Combined_0_15_IRQHandler [WEAK] + EXPORT GPIO4_Combined_16_31_IRQHandler [WEAK] + EXPORT GPIO5_Combined_0_15_IRQHandler [WEAK] + EXPORT GPIO5_Combined_16_31_IRQHandler [WEAK] + EXPORT FLEXIO1_DriverIRQHandler [WEAK] + EXPORT FLEXIO2_DriverIRQHandler [WEAK] + EXPORT WDOG1_IRQHandler [WEAK] + EXPORT RTWDOG_IRQHandler [WEAK] + EXPORT EWM_IRQHandler [WEAK] + EXPORT CCM_1_IRQHandler [WEAK] + EXPORT CCM_2_IRQHandler [WEAK] + EXPORT GPC_IRQHandler [WEAK] + EXPORT SRC_IRQHandler [WEAK] + EXPORT Reserved115_IRQHandler [WEAK] + EXPORT GPT1_IRQHandler [WEAK] + EXPORT GPT2_IRQHandler [WEAK] + EXPORT PWM1_0_IRQHandler [WEAK] + EXPORT PWM1_1_IRQHandler [WEAK] + EXPORT PWM1_2_IRQHandler [WEAK] + EXPORT PWM1_3_IRQHandler [WEAK] + EXPORT PWM1_FAULT_IRQHandler [WEAK] + EXPORT FLEXSPI2_DriverIRQHandler [WEAK] + EXPORT FLEXSPI_DriverIRQHandler [WEAK] + EXPORT SEMC_IRQHandler [WEAK] + EXPORT USDHC1_DriverIRQHandler [WEAK] + EXPORT USDHC2_DriverIRQHandler [WEAK] + EXPORT USB_OTG2_IRQHandler [WEAK] + EXPORT USB_OTG1_IRQHandler [WEAK] + EXPORT ENET_DriverIRQHandler [WEAK] + EXPORT ENET_1588_Timer_DriverIRQHandler [WEAK] + EXPORT XBAR1_IRQ_0_1_IRQHandler [WEAK] + EXPORT XBAR1_IRQ_2_3_IRQHandler [WEAK] + EXPORT ADC_ETC_IRQ0_IRQHandler [WEAK] + EXPORT ADC_ETC_IRQ1_IRQHandler [WEAK] + EXPORT ADC_ETC_IRQ2_IRQHandler [WEAK] + EXPORT ADC_ETC_ERROR_IRQ_IRQHandler [WEAK] + EXPORT PIT_IRQHandler [WEAK] + EXPORT ACMP1_IRQHandler [WEAK] + EXPORT ACMP2_IRQHandler [WEAK] + EXPORT ACMP3_IRQHandler [WEAK] + EXPORT ACMP4_IRQHandler [WEAK] + EXPORT Reserved143_IRQHandler [WEAK] + EXPORT Reserved144_IRQHandler [WEAK] + EXPORT ENC1_IRQHandler [WEAK] + EXPORT ENC2_IRQHandler [WEAK] + EXPORT ENC3_IRQHandler [WEAK] + EXPORT ENC4_IRQHandler [WEAK] + EXPORT TMR1_IRQHandler [WEAK] + EXPORT TMR2_IRQHandler [WEAK] + EXPORT TMR3_IRQHandler [WEAK] + EXPORT TMR4_IRQHandler [WEAK] + EXPORT PWM2_0_IRQHandler [WEAK] + EXPORT PWM2_1_IRQHandler [WEAK] + EXPORT PWM2_2_IRQHandler [WEAK] + EXPORT PWM2_3_IRQHandler [WEAK] + EXPORT PWM2_FAULT_IRQHandler [WEAK] + EXPORT PWM3_0_IRQHandler [WEAK] + EXPORT PWM3_1_IRQHandler [WEAK] + EXPORT PWM3_2_IRQHandler [WEAK] + EXPORT PWM3_3_IRQHandler [WEAK] + EXPORT PWM3_FAULT_IRQHandler [WEAK] + EXPORT PWM4_0_IRQHandler [WEAK] + EXPORT PWM4_1_IRQHandler [WEAK] + EXPORT PWM4_2_IRQHandler [WEAK] + EXPORT PWM4_3_IRQHandler [WEAK] + EXPORT PWM4_FAULT_IRQHandler [WEAK] + EXPORT ENET2_DriverIRQHandler [WEAK] + EXPORT ENET2_1588_Timer_DriverIRQHandler [WEAK] + EXPORT CAN3_DriverIRQHandler [WEAK] + EXPORT Reserved171_IRQHandler [WEAK] + EXPORT FLEXIO3_DriverIRQHandler [WEAK] + EXPORT GPIO6_7_8_9_IRQHandler [WEAK] + EXPORT DefaultISR [WEAK] +DMA0_DMA16_DriverIRQHandler +DMA1_DMA17_DriverIRQHandler +DMA2_DMA18_DriverIRQHandler +DMA3_DMA19_DriverIRQHandler +DMA4_DMA20_DriverIRQHandler +DMA5_DMA21_DriverIRQHandler +DMA6_DMA22_DriverIRQHandler +DMA7_DMA23_DriverIRQHandler +DMA8_DMA24_DriverIRQHandler +DMA9_DMA25_DriverIRQHandler +DMA10_DMA26_DriverIRQHandler +DMA11_DMA27_DriverIRQHandler +DMA12_DMA28_DriverIRQHandler +DMA13_DMA29_DriverIRQHandler +DMA14_DMA30_DriverIRQHandler +DMA15_DMA31_DriverIRQHandler +DMA_ERROR_DriverIRQHandler +CTI0_ERROR_IRQHandler +CTI1_ERROR_IRQHandler +CORE_IRQHandler +LPUART1_DriverIRQHandler +LPUART2_DriverIRQHandler +LPUART3_DriverIRQHandler +LPUART4_DriverIRQHandler +LPUART5_DriverIRQHandler +LPUART6_DriverIRQHandler +LPUART7_DriverIRQHandler +LPUART8_DriverIRQHandler +LPI2C1_DriverIRQHandler +LPI2C2_DriverIRQHandler +LPI2C3_DriverIRQHandler +LPI2C4_DriverIRQHandler +LPSPI1_DriverIRQHandler +LPSPI2_DriverIRQHandler +LPSPI3_DriverIRQHandler +LPSPI4_DriverIRQHandler +CAN1_DriverIRQHandler +CAN2_DriverIRQHandler +FLEXRAM_IRQHandler +KPP_IRQHandler +TSC_DIG_IRQHandler +GPR_IRQ_IRQHandler +Reserved58_IRQHandler +Reserved59_IRQHandler +Reserved60_IRQHandler +WDOG2_IRQHandler +SNVS_HP_WRAPPER_IRQHandler +SNVS_HP_WRAPPER_TZ_IRQHandler +SNVS_LP_WRAPPER_IRQHandler +CSU_IRQHandler +DCP_IRQHandler +DCP_VMI_IRQHandler +Reserved68_IRQHandler +TRNG_IRQHandler +SJC_IRQHandler +BEE_IRQHandler +SAI1_DriverIRQHandler +SAI2_DriverIRQHandler +SAI3_RX_DriverIRQHandler +SAI3_TX_DriverIRQHandler +SPDIF_DriverIRQHandler +PMU_EVENT_IRQHandler +Reserved78_IRQHandler +TEMP_LOW_HIGH_IRQHandler +TEMP_PANIC_IRQHandler +USB_PHY1_IRQHandler +USB_PHY2_IRQHandler +ADC1_IRQHandler +ADC2_IRQHandler +DCDC_IRQHandler +Reserved86_IRQHandler +Reserved87_IRQHandler +GPIO1_INT0_IRQHandler +GPIO1_INT1_IRQHandler +GPIO1_INT2_IRQHandler +GPIO1_INT3_IRQHandler +GPIO1_INT4_IRQHandler +GPIO1_INT5_IRQHandler +GPIO1_INT6_IRQHandler +GPIO1_INT7_IRQHandler +GPIO1_Combined_0_15_IRQHandler +GPIO1_Combined_16_31_IRQHandler +GPIO2_Combined_0_15_IRQHandler +GPIO2_Combined_16_31_IRQHandler +GPIO3_Combined_0_15_IRQHandler +GPIO3_Combined_16_31_IRQHandler +GPIO4_Combined_0_15_IRQHandler +GPIO4_Combined_16_31_IRQHandler +GPIO5_Combined_0_15_IRQHandler +GPIO5_Combined_16_31_IRQHandler +FLEXIO1_DriverIRQHandler +FLEXIO2_DriverIRQHandler +WDOG1_IRQHandler +RTWDOG_IRQHandler +EWM_IRQHandler +CCM_1_IRQHandler +CCM_2_IRQHandler +GPC_IRQHandler +SRC_IRQHandler +Reserved115_IRQHandler +GPT1_IRQHandler +GPT2_IRQHandler +PWM1_0_IRQHandler +PWM1_1_IRQHandler +PWM1_2_IRQHandler +PWM1_3_IRQHandler +PWM1_FAULT_IRQHandler +FLEXSPI2_DriverIRQHandler +FLEXSPI_DriverIRQHandler +SEMC_IRQHandler +USDHC1_DriverIRQHandler +USDHC2_DriverIRQHandler +USB_OTG2_IRQHandler +USB_OTG1_IRQHandler +ENET_DriverIRQHandler +ENET_1588_Timer_DriverIRQHandler +XBAR1_IRQ_0_1_IRQHandler +XBAR1_IRQ_2_3_IRQHandler +ADC_ETC_IRQ0_IRQHandler +ADC_ETC_IRQ1_IRQHandler +ADC_ETC_IRQ2_IRQHandler +ADC_ETC_ERROR_IRQ_IRQHandler +PIT_IRQHandler +ACMP1_IRQHandler +ACMP2_IRQHandler +ACMP3_IRQHandler +ACMP4_IRQHandler +Reserved143_IRQHandler +Reserved144_IRQHandler +ENC1_IRQHandler +ENC2_IRQHandler +ENC3_IRQHandler +ENC4_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +TMR4_IRQHandler +PWM2_0_IRQHandler +PWM2_1_IRQHandler +PWM2_2_IRQHandler +PWM2_3_IRQHandler +PWM2_FAULT_IRQHandler +PWM3_0_IRQHandler +PWM3_1_IRQHandler +PWM3_2_IRQHandler +PWM3_3_IRQHandler +PWM3_FAULT_IRQHandler +PWM4_0_IRQHandler +PWM4_1_IRQHandler +PWM4_2_IRQHandler +PWM4_3_IRQHandler +PWM4_FAULT_IRQHandler +ENET2_DriverIRQHandler +ENET2_1588_Timer_DriverIRQHandler +CAN3_DriverIRQHandler +Reserved171_IRQHandler +FLEXIO3_DriverIRQHandler +GPIO6_7_8_9_IRQHandler +DefaultISR + LDR R0, =DefaultISR + BX R0 + ENDP + ALIGN + + + END diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_adc.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_adc.c new file mode 100644 index 0000000000..b2fa29b718 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_adc.c @@ -0,0 +1,394 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_adc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.adc_12b1msps_sar" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for ADC module. + * + * @param base ADC peripheral base address + */ +static uint32_t ADC_GetInstance(ADC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to ADC bases for each instance. */ +static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to ADC clocks for each instance. */ +static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t ADC_GetInstance(ADC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_adcBases); instance++) + { + if (s_adcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_adcBases)); + + return instance; +} + +/*! + * brief Initialize the ADC module. + * + * param base ADC peripheral base address. + * param config Pointer to "adc_config_t" structure. + */ +void ADC_Init(ADC_Type *base, const adc_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* ADCx_CFG */ + tmp32 = base->CFG & (ADC_CFG_AVGS_MASK | ADC_CFG_ADTRG_MASK); /* Reserve AVGS and ADTRG bits. */ + tmp32 |= ADC_CFG_REFSEL(config->referenceVoltageSource) | ADC_CFG_ADSTS(config->samplePeriodMode) | + ADC_CFG_ADICLK(config->clockSource) | ADC_CFG_ADIV(config->clockDriver) | ADC_CFG_MODE(config->resolution); + if (config->enableOverWrite) + { + tmp32 |= ADC_CFG_OVWREN_MASK; + } + if (config->enableLongSample) + { + tmp32 |= ADC_CFG_ADLSMP_MASK; + } + if (config->enableLowPower) + { + tmp32 |= ADC_CFG_ADLPC_MASK; + } + if (config->enableHighSpeed) + { + tmp32 |= ADC_CFG_ADHSC_MASK; + } + base->CFG = tmp32; + + /* ADCx_GC */ + tmp32 = base->GC & ~(ADC_GC_ADCO_MASK | ADC_GC_ADACKEN_MASK); + if (config->enableContinuousConversion) + { + tmp32 |= ADC_GC_ADCO_MASK; + } + if (config->enableAsynchronousClockOutput) + { + tmp32 |= ADC_GC_ADACKEN_MASK; + } + base->GC = tmp32; +} + +/*! + * brief De-initializes the ADC module. + * + * param base ADC peripheral base address. + */ +void ADC_Deinit(ADC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets an available pre-defined settings for the converter's configuration. + * + * This function initializes the converter configuration structure with available settings. The default values are: + * code + * config->enableAsynchronousClockOutput = true; + * config->enableOverWrite = false; + * config->enableContinuousConversion = false; + * config->enableHighSpeed = false; + * config->enableLowPower = false; + * config->enableLongSample = false; + * config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0; + * config->samplePeriodMode = kADC_SamplePeriod2or12Clocks; + * config->clockSource = kADC_ClockSourceAD; + * config->clockDriver = kADC_ClockDriver1; + * config->resolution = kADC_Resolution12Bit; + * endcode + * param base ADC peripheral base address. + * param config Pointer to the configuration structure. + */ +void ADC_GetDefaultConfig(adc_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->enableAsynchronousClockOutput = true; + config->enableOverWrite = false; + config->enableContinuousConversion = false; + config->enableHighSpeed = false; + config->enableLowPower = false; + config->enableLongSample = false; + config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0; + config->samplePeriodMode = kADC_SamplePeriod2or12Clocks; + config->clockSource = kADC_ClockSourceAD; + config->clockDriver = kADC_ClockDriver1; + config->resolution = kADC_Resolution12Bit; +} + +/*! + * brief Configures the conversion channel. + * + * This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API + * configures the channel while the external trigger source helps to trigger the conversion. + * + * Note that the "Channel Group" has a detailed description. + * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one + * group of status and control registers, one for each conversion. The channel group parameter indicates which group of + * registers are used, for example channel group 0 is for Group A registers and channel group 1 is for Group B + * registers. The + * channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of + * the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and + * hardware + * trigger modes. Channel groups 1 and greater indicate potentially multiple channel group registers for + * use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual + * about the + * number of SC1n registers (channel groups) specific to this device. None of the channel groups 1 or greater are used + * for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion. + * Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and + * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a + * conversion aborts the current conversion. + * + * param base ADC peripheral base address. + * param channelGroup Channel group index. + * param config Pointer to the "adc_channel_config_t" structure for the conversion channel. + */ +void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config) +{ + assert(NULL != config); + assert(channelGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT); + + uint32_t tmp32; + + tmp32 = ADC_HC_ADCH(config->channelNumber); + if (config->enableInterruptOnConversionCompleted) + { + tmp32 |= ADC_HC_AIEN_MASK; + } + base->HC[channelGroup] = tmp32; +} + +/* + *To complete calibration, the user must follow the below procedure: + * 1. Configure ADC_CFG with actual operating values for maximum accuracy. + * 2. Configure the ADC_GC values along with CAL bit. + * 3. Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC. + * 4. When CAL bit becomes '0' then check the CALF status and COCO[0] bit status. + */ +/*! + * brief Automates the hardware calibration. + * + * This auto calibration helps to adjust the plus/minus side gain automatically. + * Execute the calibration before using the converter. Note that the software trigger should be used + * during calibration. + * + * param base ADC peripheral base address. + * + * return Execution status. + * retval kStatus_Success Calibration is done successfully. + * retval kStatus_Fail Calibration has failed. + */ +status_t ADC_DoAutoCalibration(ADC_Type *base) +{ + status_t status = kStatus_Success; +#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) + bool bHWTrigger = false; + + /* The calibration would be failed when in hardwar mode. + * Remember the hardware trigger state here and restore it later if the hardware trigger is enabled.*/ + if (0U != (ADC_CFG_ADTRG_MASK & base->CFG)) + { + bHWTrigger = true; + ADC_EnableHardwareTrigger(base, false); + } +#endif + + /* Clear the CALF and launch the calibration. */ + base->GS = ADC_GS_CALF_MASK; /* Clear the CALF. */ + base->GC |= ADC_GC_CAL_MASK; /* Launch the calibration. */ + + /* Check the status of CALF bit in ADC_GS and the CAL bit in ADC_GC. */ + while (0U != (base->GC & ADC_GC_CAL_MASK)) + { + /* Check the CALF when the calibration is active. */ + if (0U != (ADC_GetStatusFlags(base) & kADC_CalibrationFailedFlag)) + { + status = kStatus_Fail; + break; + } + } + + /* When CAL bit becomes '0' then check the CALF status and COCO[0] bit status. */ + if (0U == ADC_GetChannelStatusFlags(base, 0U)) /* Check the COCO[0] bit status. */ + { + status = kStatus_Fail; + } + if (0U != (ADC_GetStatusFlags(base) & kADC_CalibrationFailedFlag)) /* Check the CALF status. */ + { + status = kStatus_Fail; + } + + /* Clear conversion done flag. */ + ADC_GetChannelConversionValue(base, 0U); + +#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) + /* Restore original trigger mode. */ + if (true == bHWTrigger) + { + ADC_EnableHardwareTrigger(base, true); + } +#endif + + return status; +} + +/*! + * brief Set user defined offset. + * + * param base ADC peripheral base address. + * param config Pointer to "adc_offest_config_t" structure. + */ +void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + + tmp32 = ADC_OFS_OFS(config->offsetValue); + if (config->enableSigned) + { + tmp32 |= ADC_OFS_SIGN_MASK; + } + base->OFS = tmp32; +} + +/*! + * brief Configures the hardware compare mode. + * + * The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the + * result + * in the compare range is available. To compare the range, see "adc_hardware_compare_mode_t" or the appopriate + * reference + * manual for more information. + * + * param base ADC peripheral base address. + * param Pointer to "adc_hardware_compare_config_t" structure. + * + */ +void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config) +{ + uint32_t tmp32; + + tmp32 = base->GC & ~(ADC_GC_ACFE_MASK | ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK); + if (NULL == config) /* Pass "NULL" to disable the feature. */ + { + base->GC = tmp32; + return; + } + /* Enable the feature. */ + tmp32 |= ADC_GC_ACFE_MASK; + + /* Select the hardware compare working mode. */ + switch (config->hardwareCompareMode) + { + case kADC_HardwareCompareMode0: + break; + case kADC_HardwareCompareMode1: + tmp32 |= ADC_GC_ACFGT_MASK; + break; + case kADC_HardwareCompareMode2: + tmp32 |= ADC_GC_ACREN_MASK; + break; + case kADC_HardwareCompareMode3: + tmp32 |= ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK; + break; + default: + break; + } + base->GC = tmp32; + + /* Load the compare values. */ + tmp32 = ADC_CV_CV1(config->value1) | ADC_CV_CV2(config->value2); + base->CV = tmp32; +} + +/*! + * brief Configures the hardware average mode. + * + * The hardware average mode provides a way to process the conversion result automatically by using hardware. The + * multiple + * conversion results are accumulated and averaged internally making them easier to read. + * + * param base ADC peripheral base address. + * param mode Setting the hardware average mode. See "adc_hardware_average_mode_t". + */ +void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode) +{ + uint32_t tmp32; + + if (mode == kADC_HardwareAverageDiasable) + { + base->GC &= ~ADC_GC_AVGE_MASK; + } + else + { + tmp32 = base->CFG & ~ADC_CFG_AVGS_MASK; + tmp32 |= ADC_CFG_AVGS(mode); + base->CFG = tmp32; + base->GC |= ADC_GC_AVGE_MASK; /* Enable the hardware compare. */ + } +} + +/*! + * brief Clears the converter's status falgs. + * + * param base ADC peripheral base address. + * param mask Mask value for the cleared flags. See "adc_status_flags_t". + */ +void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) +{ + uint32_t tmp32 = 0; + + if (0U != (mask & kADC_CalibrationFailedFlag)) + { + tmp32 |= ADC_GS_CALF_MASK; + } + if (0U != (mask & kADC_ConversionActiveFlag)) + { + tmp32 |= ADC_GS_ADACT_MASK; + } + base->GS = tmp32; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_adc.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_adc.h new file mode 100644 index 0000000000..645e22e3f6 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_adc.h @@ -0,0 +1,420 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_ADC_H_ +#define _FSL_ADC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup adc_12b1msps_sar + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief ADC driver version */ +#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2. */ + +/*! + * @brief Converter's status flags. + */ +typedef enum _adc_status_flags +{ + kADC_ConversionActiveFlag = ADC_GS_ADACT_MASK, /*!< Conversion is active,not support w1c. */ + kADC_CalibrationFailedFlag = ADC_GS_CALF_MASK, /*!< Calibration is failed,support w1c. */ + kADC_AsynchronousWakeupInterruptFlag = + ADC_GS_AWKST_MASK, /*!< Asynchronous wakeup interrupt occurred, support w1c. */ +} adc_status_flags_t; + +/*! + * @brief Reference voltage source. + */ +typedef enum _adc_reference_voltage_source +{ + kADC_ReferenceVoltageSourceAlt0 = 0U, /*!< For external pins pair of VrefH and VrefL. */ +} adc_reference_voltage_source_t; + +/*! + * @brief Sample time duration. + */ +typedef enum _adc_sample_period_mode +{ + /* This group of enumeration is for internal use which is related to register setting. */ + kADC_SamplePeriod2or12Clocks = 0U, /*!< Long sample 12 clocks or short sample 2 clocks. */ + kADC_SamplePeriod4or16Clocks = 1U, /*!< Long sample 16 clocks or short sample 4 clocks. */ + kADC_SamplePeriod6or20Clocks = 2U, /*!< Long sample 20 clocks or short sample 6 clocks. */ + kADC_SamplePeriod8or24Clocks = 3U, /*!< Long sample 24 clocks or short sample 8 clocks. */ + /* This group of enumeration is for a public user. */ + /* For long sample mode. */ + kADC_SamplePeriodLong12Clcoks = kADC_SamplePeriod2or12Clocks, /*!< Long sample 12 clocks. */ + kADC_SamplePeriodLong16Clcoks = kADC_SamplePeriod4or16Clocks, /*!< Long sample 16 clocks. */ + kADC_SamplePeriodLong20Clcoks = kADC_SamplePeriod6or20Clocks, /*!< Long sample 20 clocks. */ + kADC_SamplePeriodLong24Clcoks = kADC_SamplePeriod8or24Clocks, /*!< Long sample 24 clocks. */ + /* For short sample mode. */ + kADC_SamplePeriodShort2Clocks = kADC_SamplePeriod2or12Clocks, /*!< Short sample 2 clocks. */ + kADC_SamplePeriodShort4Clocks = kADC_SamplePeriod4or16Clocks, /*!< Short sample 4 clocks. */ + kADC_SamplePeriodShort6Clocks = kADC_SamplePeriod6or20Clocks, /*!< Short sample 6 clocks. */ + kADC_SamplePeriodShort8Clocks = kADC_SamplePeriod8or24Clocks, /*!< Short sample 8 clocks. */ +} adc_sample_period_mode_t; + +/*! + * @brief Clock source. + */ +typedef enum _adc_clock_source +{ + kADC_ClockSourceIPG = 0U, /*!< Select IPG clock to generate ADCK. */ + kADC_ClockSourceIPGDiv2 = 1U, /*!< Select IPG clock divided by 2 to generate ADCK. */ +#if !(defined(FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE) && FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE) + kADC_ClockSourceALT = 2U, /*!< Select alternate clock to generate ADCK. */ +#endif + kADC_ClockSourceAD = 3U, /*!< Select Asynchronous clock to generate ADCK. */ +} adc_clock_source_t; + +/*! + * @brief Clock divider for the converter. + */ +typedef enum _adc_clock_drvier +{ + kADC_ClockDriver1 = 0U, /*!< For divider 1 from the input clock to the module. */ + kADC_ClockDriver2 = 1U, /*!< For divider 2 from the input clock to the module. */ + kADC_ClockDriver4 = 2U, /*!< For divider 4 from the input clock to the module. */ + kADC_ClockDriver8 = 3U, /*!< For divider 8 from the input clock to the module. */ +} adc_clock_driver_t; + +/*! + * @brief Converter's resolution. + */ +typedef enum _adc_resolution +{ + kADC_Resolution8Bit = 0U, /*!< Single End 8-bit resolution. */ + kADC_Resolution10Bit = 1U, /*!< Single End 10-bit resolution. */ + kADC_Resolution12Bit = 2U, /*!< Single End 12-bit resolution. */ +} adc_resolution_t; + +/*! + * @brief Converter hardware compare mode. + */ +typedef enum _adc_hardware_compare_mode +{ + kADC_HardwareCompareMode0 = 0U, /*!< Compare true if the result is less than the value1. */ + kADC_HardwareCompareMode1 = 1U, /*!< Compare true if the result is greater than or equal to value1. */ + kADC_HardwareCompareMode2 = 2U, /*!< Value1 <= Value2, compare true if the result is less than value1 Or + the result is Greater than value2. + Value1 > Value2, compare true if the result is less than value1 And the + result is greater than value2*/ + kADC_HardwareCompareMode3 = 3U, /*!< Value1 <= Value2, compare true if the result is greater than or equal + to value1 And the result is less than or equal to value2. + Value1 > Value2, compare true if the result is greater than or equal to + value1 Or the result is less than or equal to value2. */ +} adc_hardware_compare_mode_t; + +/*! + * @brief Converter hardware average mode. + */ +typedef enum _adc_hardware_average_mode +{ + kADC_HardwareAverageCount4 = 0U, /*!< For hardware average with 4 samples. */ + kADC_HardwareAverageCount8 = 1U, /*!< For hardware average with 8 samples. */ + kADC_HardwareAverageCount16 = 2U, /*!< For hardware average with 16 samples. */ + kADC_HardwareAverageCount32 = 3U, /*!< For hardware average with 32 samples. */ + kADC_HardwareAverageDiasable = 4U, /*!< Disable the hardware average function. */ +} adc_hardware_average_mode_t; + +/*! + * @brief Converter configuration. + */ +typedef struct _adc_config +{ + bool enableOverWrite; /*!< Enable the overwriting. */ + bool enableContinuousConversion; /*!< Enable the continuous conversion mode. */ + bool enableHighSpeed; /*!< Enable the high-speed mode. */ + bool enableLowPower; /*!< Enable the low power mode. */ + bool enableLongSample; /*!< Enable the long sample mode. */ + bool enableAsynchronousClockOutput; /*!< Enable the asynchronous clock output. */ + adc_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */ + adc_sample_period_mode_t samplePeriodMode; /*!< Select the sample period in long sample mode or short mode. */ + adc_clock_source_t clockSource; /*!< Select the input clock source to generate the internal clock ADCK. */ + adc_clock_driver_t clockDriver; /*!< Select the divide ratio used by the ADC to generate the internal clock ADCK. */ + adc_resolution_t resolution; /*!< Select the ADC resolution mode. */ +} adc_config_t; + +/*! + * @brief Converter Offset configuration. + */ +typedef struct _adc_offest_config +{ + bool enableSigned; /*!< if false,The offset value is added with the raw result. + if true,The offset value is subtracted from the raw converted value. */ + uint32_t offsetValue; /*!< User configurable offset value(0-4095). */ +} adc_offest_config_t; + +/*! + * @brief ADC hardware compare configuration. + * + * In kADC_HardwareCompareMode0, compare true if the result is less than the value1. + * In kADC_HardwareCompareMode1, compare true if the result is greater than or equal to value1. + * In kADC_HardwareCompareMode2, Value1 <= Value2, compare true if the result is less than value1 Or the result is + * Greater than value2. + * Value1 > Value2, compare true if the result is less than value1 And the result is + * Greater than value2. + * In kADC_HardwareCompareMode3, Value1 <= Value2, compare true if the result is greater than or equal to value1 And the + * result is less than or equal to value2. + * Value1 > Value2, compare true if the result is greater than or equal to value1 Or the + * result is less than or equal to value2. + */ +typedef struct _adc_hardware_compare_config +{ + adc_hardware_compare_mode_t hardwareCompareMode; /*!< Select the hardware compare mode. + See "adc_hardware_compare_mode_t". */ + uint16_t value1; /*!< Setting value1(0-4095) for hardware compare mode. */ + uint16_t value2; /*!< Setting value2(0-4095) for hardware compare mode. */ +} adc_hardware_compare_config_t; + +/*! + * @brief ADC channel conversion configuration. + */ +typedef struct _adc_channel_config +{ + uint32_t channelNumber; /*!< Setting the conversion channel number. The available range is 0-31. + See channel connection information for each chip in Reference + Manual document. */ + bool enableInterruptOnConversionCompleted; /*!< Generate an interrupt request once the conversion is completed. */ +} adc_channel_config_t; +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initialize the ADC module. + * + * @param base ADC peripheral base address. + * @param config Pointer to "adc_config_t" structure. + */ +void ADC_Init(ADC_Type *base, const adc_config_t *config); + +/*! + * @brief De-initializes the ADC module. + * + * @param base ADC peripheral base address. + */ +void ADC_Deinit(ADC_Type *base); + +/*! + * @brief Gets an available pre-defined settings for the converter's configuration. + * + * This function initializes the converter configuration structure with available settings. The default values are: + * @code + * config->enableAsynchronousClockOutput = true; + * config->enableOverWrite = false; + * config->enableContinuousConversion = false; + * config->enableHighSpeed = false; + * config->enableLowPower = false; + * config->enableLongSample = false; + * config->referenceVoltageSource = kADC_ReferenceVoltageSourceAlt0; + * config->samplePeriodMode = kADC_SamplePeriod2or12Clocks; + * config->clockSource = kADC_ClockSourceAD; + * config->clockDriver = kADC_ClockDriver1; + * config->resolution = kADC_Resolution12Bit; + * @endcode + * @param base ADC peripheral base address. + * @param config Pointer to the configuration structure. + */ +void ADC_GetDefaultConfig(adc_config_t *config); + +/*! + * @brief Configures the conversion channel. + * + * This operation triggers the conversion when in software trigger mode. When in hardware trigger mode, this API + * configures the channel while the external trigger source helps to trigger the conversion. + * + * Note that the "Channel Group" has a detailed description. + * To allow sequential conversions of the ADC to be triggered by internal peripherals, the ADC has more than one + * group of status and control registers, one for each conversion. The channel group parameter indicates which group of + * registers are used, for example channel group 0 is for Group A registers and channel group 1 is for Group B + * registers. The + * channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of + * the channel groups is actively controlling ADC conversions. The channel group 0 is used for both software and + * hardware + * trigger modes. Channel groups 1 and greater indicate potentially multiple channel group registers for + * use only in hardware trigger mode. See the chip configuration information in the appropriate MCU reference manual + * about the + * number of SC1n registers (channel groups) specific to this device. None of the channel groups 1 or greater are used + * for software trigger operation. Therefore, writing to these channel groups does not initiate a new conversion. + * Updating the channel group 0 while a different channel group is actively controlling a conversion is allowed and + * vice versa. Writing any of the channel group registers while that specific channel group is actively controlling a + * conversion aborts the current conversion. + * + * @param base ADC peripheral base address. + * @param channelGroup Channel group index. + * @param config Pointer to the "adc_channel_config_t" structure for the conversion channel. + */ +void ADC_SetChannelConfig(ADC_Type *base, uint32_t channelGroup, const adc_channel_config_t *config); + +/*! + * @brief Gets the conversion value. + * + * @param base ADC peripheral base address. + * @param channelGroup Channel group index. + * + * @return Conversion value. + */ +static inline uint32_t ADC_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup) +{ + assert(channelGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT); + + return base->R[channelGroup]; +} + +/*! + * @brief Gets the status flags of channel. + * + * A conversion is completed when the result of the conversion is transferred into the data + * result registers. (provided the compare function & hardware averaging is disabled), this is + * indicated by the setting of COCOn. If hardware averaging is enabled, COCOn sets only, + * if the last of the selected number of conversions is complete. If the compare function is + * enabled, COCOn sets and conversion result data is transferred only if the compare + * condition is true. If both hardware averaging and compare functions are enabled, then + * COCOn sets only if the last of the selected number of conversions is complete and the + * compare condition is true. + * + * @param base ADC peripheral base address. + * @param channelGroup Channel group index. + * + * @return Status flags of channel.return 0 means COCO flag is 0,return 1 means COCOflag is 1. + */ +static inline uint32_t ADC_GetChannelStatusFlags(ADC_Type *base, uint32_t channelGroup) +{ + assert(channelGroup < FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT); + + /* If flag is set,return 1,otherwise, return 0. */ + return (((base->HS) & (1U << channelGroup)) >> channelGroup); +} + +/*! + * @brief Automates the hardware calibration. + * + * This auto calibration helps to adjust the plus/minus side gain automatically. + * Execute the calibration before using the converter. Note that the software trigger should be used + * during calibration. + * + * @param base ADC peripheral base address. + * + * @return Execution status. + * @retval kStatus_Success Calibration is done successfully. + * @retval kStatus_Fail Calibration has failed. + */ +status_t ADC_DoAutoCalibration(ADC_Type *base); + +/*! + * @brief Set user defined offset. + * + * @param base ADC peripheral base address. + * @param config Pointer to "adc_offest_config_t" structure. + */ +void ADC_SetOffsetConfig(ADC_Type *base, const adc_offest_config_t *config); + +/*! + * @brief Enables generating the DMA trigger when the conversion is complete. + * + * @param base ADC peripheral base address. + * @param enable Switcher of the DMA feature. "true" means enabled, "false" means not enabled. + */ +static inline void ADC_EnableDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->GC |= ADC_GC_DMAEN_MASK; + } + else + { + base->GC &= ~ADC_GC_DMAEN_MASK; + } +} + +/*! + * @brief Enables the hardware trigger mode. + * + * @param base ADC peripheral base address. + * @param enable Switcher of the trigger mode. "true" means hardware tirgger mode,"false" means software mode. + */ +#if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) +static inline void ADC_EnableHardwareTrigger(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= ADC_CFG_ADTRG_MASK; + } + else + { + base->CFG &= ~ADC_CFG_ADTRG_MASK; + } +} +#endif + +/*! + * @brief Configures the hardware compare mode. + * + * The hardware compare mode provides a way to process the conversion result automatically by using hardware. Only the + * result + * in the compare range is available. To compare the range, see "adc_hardware_compare_mode_t" or the appopriate + * reference + * manual for more information. + * + * @param base ADC peripheral base address. + * @param Pointer to "adc_hardware_compare_config_t" structure. + * + */ +void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_config_t *config); + +/*! + * @brief Configures the hardware average mode. + * + * The hardware average mode provides a way to process the conversion result automatically by using hardware. The + * multiple + * conversion results are accumulated and averaged internally making them easier to read. + * + * @param base ADC peripheral base address. + * @param mode Setting the hardware average mode. See "adc_hardware_average_mode_t". + */ +void ADC_SetHardwareAverageConfig(ADC_Type *base, adc_hardware_average_mode_t mode); + +/*! + * @brief Gets the converter's status flags. + * + * @param base ADC peripheral base address. + * + * @return Flags' mask if indicated flags are asserted. See "adc_status_flags_t". + */ +static inline uint32_t ADC_GetStatusFlags(ADC_Type *base) +{ + return base->GS; +} + +/*! + * @brief Clears the converter's status falgs. + * + * @param base ADC peripheral base address. + * @param mask Mask value for the cleared flags. See "adc_status_flags_t". + */ +void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask); + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_ADC_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_adc_etc.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_adc_etc.c new file mode 100644 index 0000000000..cdd5db1f9d --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_adc_etc.c @@ -0,0 +1,411 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_adc_etc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.adc_etc" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(ADC_ETC_CLOCKS) +/*! + * @brief Get instance number for ADC_ETC module. + * + * @param base ADC_ETC peripheral base address + */ +static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to ADC_ETC bases for each instance. */ +static ADC_ETC_Type *const s_adcetcBases[] = ADC_ETC_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to ADC_ETC clocks for each instance. */ +static const clock_ip_name_t s_adcetcClocks[] = ADC_ETC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t ADC_ETC_GetInstance(ADC_ETC_Type *base) +{ + uint32_t instance = 0U; + uint32_t adcetcArrayCount = (sizeof(s_adcetcBases) / sizeof(s_adcetcBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < adcetcArrayCount; instance++) + { + if (s_adcetcBases[instance] == base) + { + break; + } + } + + return instance; +} +#endif /* ADC_ETC_CLOCKS */ + +/*! + * brief Initialize the ADC_ETC module. + * + * param base ADC_ETC peripheral base address. + * param config Pointer to "adc_etc_config_t" structure. + */ +void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(ADC_ETC_CLOCKS) + /* Open clock gate. */ + CLOCK_EnableClock(s_adcetcClocks[ADC_ETC_GetInstance(base)]); +#endif /* ADC_ETC_CLOCKS */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable software reset. */ + ADC_ETC_DoSoftwareReset(base, false); + + /* Set ADC_ETC_CTRL register. */ + tmp32 = ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(config->TSC0triggerPriority) | + ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(config->TSC1triggerPriority) | + ADC_ETC_CTRL_PRE_DIVIDER(config->clockPreDivider) | ADC_ETC_CTRL_TRIG_ENABLE(config->XBARtriggerMask) +#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL + | ADC_ETC_CTRL_DMA_MODE_SEL(config->dmaMode) +#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/ + ; + if (config->enableTSCBypass) + { + tmp32 |= ADC_ETC_CTRL_TSC_BYPASS_MASK; + } + if (config->enableTSC0Trigger) + { + tmp32 |= ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK; + } + if (config->enableTSC1Trigger) + { + tmp32 |= ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK; + } + base->CTRL = tmp32; +} + +/*! + * brief De-Initialize the ADC_ETC module. + * + * param base ADC_ETC peripheral base address. + */ +void ADC_ETC_Deinit(ADC_ETC_Type *base) +{ + /* Do software reset to clear all logical. */ + ADC_ETC_DoSoftwareReset(base, true); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(ADC_ETC_CLOCKS) + /* Close clock gate. */ + CLOCK_DisableClock(s_adcetcClocks[ADC_ETC_GetInstance(base)]); +#endif /* ADC_ETC_CLOCKS */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets an available pre-defined settings for the ADC_ETC's configuration. + * This function initializes the ADC_ETC's configuration structure with available settings. The default values are: + * code + * config->enableTSCBypass = true; + * config->enableTSC0Trigger = false; + * config->enableTSC1Trigger = false; + * config->TSC0triggerPriority = 0U; + * config->TSC1triggerPriority = 0U; + * config->clockPreDivider = 0U; + * config->XBARtriggerMask = 0U; + * endCode + * + * param config Pointer to "adc_etc_config_t" structure. + */ +void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config) +{ + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->enableTSCBypass = true; + config->enableTSC0Trigger = false; + config->enableTSC1Trigger = false; +#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL + config->dmaMode = kADC_ETC_TrigDMAWithLatchedSignal; +#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/ + config->TSC0triggerPriority = 0U; + config->TSC1triggerPriority = 0U; + config->clockPreDivider = 0U; + config->XBARtriggerMask = 0U; +} + +/*! + * brief Set the external XBAR trigger configuration. + * + * param base ADC_ETC peripheral base address. + * param triggerGroup Trigger group index. + * param config Pointer to "adc_etc_trigger_config_t" structure. + */ +void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config) +{ + assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT); + assert(ADC_ETC_TRIGn_COUNTER_COUNT > triggerGroup); + + uint32_t tmp32; + + /* Set ADC_ETC_TRGn_CTRL register. */ + tmp32 = ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(config->triggerChainLength) | + ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(config->triggerPriority); + if (config->enableSyncMode) + { + tmp32 |= ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK; + } + if (config->enableSWTriggerMode) + { + tmp32 |= ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK; + } + base->TRIG[triggerGroup].TRIGn_CTRL = tmp32; + + /* Set ADC_ETC_TRGn_COUNTER register. */ + tmp32 = ADC_ETC_TRIGn_COUNTER_INIT_DELAY(config->initialDelay) | + ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(config->sampleIntervalDelay); + base->TRIG[triggerGroup].TRIGn_COUNTER = tmp32; +} + +/*! + * brief Set the external XBAR trigger chain configuration. + * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be + * configurated. + * + * param base ADC_ETC peripheral base address. + * param triggerGroup Trigger group index. Available number is 0~7. + * param chainGroup Trigger chain group index. Available number is 0~7. + * param config Pointer to "adc_etc_trigger_chain_config_t" structure. + */ +void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base, + uint32_t triggerGroup, + uint32_t chainGroup, + const adc_etc_trigger_chain_config_t *config) +{ + assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT); + + uint32_t tmp; + uint32_t tmp32; + uint8_t mRemainder = chainGroup % 2U; + + /* Set ADC_ETC_TRIGn_CHAINm register. */ + tmp = ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(config->ADCHCRegisterSelect) | + ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(config->ADCChannelSelect) | + ADC_ETC_TRIGn_CHAIN_1_0_IE0(config->InterruptEnable); + if (config->enableB2BMode) + { + tmp |= ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK; + } + switch (chainGroup / 2U) + { + case 0U: /* Configurate trigger chain0 and chain 1. */ + tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_1_0; + if (mRemainder == 0U) /* Chain 0. */ + { + tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK | ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK | + ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK | ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK); + tmp32 |= tmp; + } + else /* Chain 1. */ + { + tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK | ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK | + ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK | ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK); + tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT); + } + base->TRIG[triggerGroup].TRIGn_CHAIN_1_0 = tmp32; + break; + case 1U: /* Configurate trigger chain2 and chain 3. */ + tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_3_2; + if (mRemainder == 0U) /* Chain 2. */ + { + tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK | ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK | + ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK | ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK); + tmp32 |= tmp; + } + else /* Chain 3. */ + { + tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK | ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK | + ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK | ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK); + tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT); + } + base->TRIG[triggerGroup].TRIGn_CHAIN_3_2 = tmp32; + break; + case 2U: /* Configurate trigger chain4 and chain 5. */ + tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_5_4; + if (mRemainder == 0U) /* Chain 4. */ + { + tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK | ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK | + ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK | ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK); + tmp32 |= tmp; + } + else /* Chain 5. */ + { + tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK | ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK | + ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK | ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK); + tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT); + } + base->TRIG[triggerGroup].TRIGn_CHAIN_5_4 = tmp32; + break; + case 3U: /* Configurate trigger chain6 and chain 7. */ + tmp32 = base->TRIG[triggerGroup].TRIGn_CHAIN_7_6; + if (mRemainder == 0U) /* Chain 6. */ + { + tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK | ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK | + ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK | ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK); + tmp32 |= tmp; + } + else /* Chain 7. */ + { + tmp32 &= ~(ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK | ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK | + ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK | ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK); + tmp32 |= (tmp << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT); + } + base->TRIG[triggerGroup].TRIGn_CHAIN_7_6 = tmp32; + break; + default: + break; + } +} + +/*! + * brief Gets the interrupt status flags of external XBAR and TSC triggers. + * + * param base ADC_ETC peripheral base address. + * param sourceIndex trigger source index. + * + * return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask". + */ +uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex) +{ + uint32_t tmp32 = 0U; + + if (((base->DONE0_1_IRQ) & (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK << sourceIndex)) != 0U) + { + tmp32 |= kADC_ETC_Done0StatusFlagMask; /* Customized DONE0 status flags mask, which is defined in fsl_adc_etc.h + file. */ + } + if (((base->DONE0_1_IRQ) & (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK << sourceIndex)) != 0U) + { + tmp32 |= kADC_ETC_Done1StatusFlagMask; /* Customized DONE1 status flags mask, which is defined in fsl_adc_etc.h + file. */ + } + if (((base->DONE2_ERR_IRQ) & (ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK << sourceIndex)) != 0U) + { + tmp32 |= kADC_ETC_Done2StatusFlagMask; /* Customized DONE2 status flags mask, which is defined in fsl_adc_etc.h + file. */ + } + if (((base->DONE2_ERR_IRQ) & (ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK << sourceIndex)) != 0U) + { + tmp32 |= kADC_ETC_ErrorStatusFlagMask; /* Customized ERROR status flags mask, which is defined in fsl_adc_etc.h + file. */ + } + return tmp32; +} + +/*! + * brief Clears the ADC_ETC's interrupt status falgs. + * + * param base ADC_ETC peripheral base address. + * param sourceIndex trigger source index. + * param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask". + */ +void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex, uint32_t mask) +{ + if (0U != (mask & kADC_ETC_Done0StatusFlagMask)) /* Write 1 to clear DONE0 status flags. */ + { + base->DONE0_1_IRQ = (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK << sourceIndex); + } + if (0U != (mask & kADC_ETC_Done1StatusFlagMask)) /* Write 1 to clear DONE1 status flags. */ + { + base->DONE0_1_IRQ = (ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK << sourceIndex); + } + if (0U != (mask & kADC_ETC_Done2StatusFlagMask)) /* Write 1 to clear DONE2 status flags. */ + { + base->DONE2_ERR_IRQ = (ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK << sourceIndex); + } + if (0U != (mask & kADC_ETC_ErrorStatusFlagMask)) /* Write 1 to clear ERROR status flags. */ + { + base->DONE2_ERR_IRQ = (ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK << sourceIndex); + } +} + +/*! + * brief Get ADC conversion result from external XBAR sources. + * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would + * return Trigger0 source's chain1 conversion result. + * + * param base ADC_ETC peripheral base address. + * param triggerGroup Trigger group index. Available number is 0~7. + * param chainGroup Trigger chain group index. Available number is 0~7. + * return ADC conversion result value. + */ +uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup) +{ + assert(triggerGroup < ADC_ETC_TRIGn_RESULT_1_0_COUNT); + + uint32_t mADCResult; + uint8_t mRemainder = chainGroup % 2U; + + switch (chainGroup / 2U) + { + case 0U: + if (0U == mRemainder) + { + mADCResult = ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_1_0); + } + else + { + mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_1_0) >> ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT; + } + break; + case 1U: + if (0U == mRemainder) + { + mADCResult = ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_3_2); + } + else + { + mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_3_2) >> ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT; + } + break; + case 2U: + if (0U == mRemainder) + { + mADCResult = ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_5_4); + } + else + { + mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_5_4) >> ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT; + } + break; + case 3U: + if (0U == mRemainder) + { + mADCResult = ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK & (base->TRIG[triggerGroup].TRIGn_RESULT_7_6); + } + else + { + mADCResult = (base->TRIG[triggerGroup].TRIGn_RESULT_7_6) >> ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT; + } + break; + default: + return 0U; + } + return mADCResult; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_adc_etc.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_adc_etc.h new file mode 100644 index 0000000000..4b43f1aa15 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_adc_etc.h @@ -0,0 +1,317 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_ADC_ETC_H_ +#define _FSL_ADC_ETC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup adc_etc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief ADC_ETC driver version */ +#define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ +/*! @brief The mask of status flags cleared by writing 1. */ +#define ADC_ETC_DMA_CTRL_TRGn_REQ_MASK 0xFF0000U + +/*! + * @brief ADC_ETC customized status flags mask. + */ +enum _adc_etc_status_flag_mask +{ + kADC_ETC_Done0StatusFlagMask = 1U, + kADC_ETC_Done1StatusFlagMask = 2U, + kADC_ETC_Done2StatusFlagMask = 4U, + kADC_ETC_ErrorStatusFlagMask = 8U, +}; + +/*! + * @brief External triggers sources. + */ +typedef enum _adc_etc_external_trigger_source +{ + /* External XBAR sources. Support HW or SW mode. */ + kADC_ETC_Trg0TriggerSource = 0U, /* External XBAR trigger0 source. */ + kADC_ETC_Trg1TriggerSource = 1U, /* External XBAR trigger1 source. */ + kADC_ETC_Trg2TriggerSource = 2U, /* External XBAR trigger2 source. */ + kADC_ETC_Trg3TriggerSource = 3U, /* External XBAR trigger3 source. */ + kADC_ETC_Trg4TriggerSource = 4U, /* External XBAR trigger4 source. */ + kADC_ETC_Trg5TriggerSource = 5U, /* External XBAR trigger5 source. */ + kADC_ETC_Trg6TriggerSource = 6U, /* External XBAR trigger6 source. */ + kADC_ETC_Trg7TriggerSource = 7U, /* External XBAR trigger7 source. */ + /* External TSC sources. Only support HW mode. */ + kADC_ETC_TSC0TriggerSource = 8U, /* External TSC trigger0 source. */ + kADC_ETC_TSC1TriggerSource = 9U, /* External TSC trigger1 source. */ +} adc_etc_external_trigger_source_t; + +/*! + * @brief Interrupt enable/disable mask. + */ +typedef enum _adc_etc_interrupt_enable +{ + kADC_ETC_InterruptDisable = 0U, /* Disable the ADC_ETC interrupt. */ + kADC_ETC_Done0InterruptEnable = 1U, /* Enable the DONE0 interrupt when ADC conversions complete. */ + kADC_ETC_Done1InterruptEnable = 2U, /* Enable the DONE1 interrupt when ADC conversions complete. */ + kADC_ETC_Done2InterruptEnable = 3U, /* Enable the DONE2 interrupt when ADC conversions complete. */ +} adc_etc_interrupt_enable_t; + +#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL +/*! + * @brief DMA mode selection. + */ +typedef enum _adc_etc_dma_mode_selection +{ + kADC_ETC_TrigDMAWithLatchedSignal = + 0U, /* Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. */ + kADC_ETC_TrigDMAWithPulsedSignal = 1U, /* Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. */ +} adc_etc_dma_mode_selection_t; +#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/ + +/*! + * @brief ADC_ETC configuration. + */ +typedef struct _adc_etc_config +{ + bool enableTSCBypass; /* If bypass TSC, TSC would trigger ADC directly. + Otherwise TSC would trigger ADC through ADC_ETC. */ + bool enableTSC0Trigger; /* Enable external TSC0 trigger. It is valid when enableTSCBypass = false. */ + bool enableTSC1Trigger; /* Enable external TSC1 trigger. It is valid when enableTSCBypass = false.*/ +#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL + adc_etc_dma_mode_selection_t dmaMode; /* Select the ADC_ETC DMA mode. */ +#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/ + uint32_t TSC0triggerPriority; /* External TSC0 trigger priority, 7 is highest, 0 is lowest. */ + uint32_t TSC1triggerPriority; /* External TSC1 trigger priority, 7 is highest, 0 is lowest. */ + uint32_t clockPreDivider; /* Pre-divider for trig delay and interval. Available range is 0-255. + Clock would be divided by (clockPreDivider+1). */ + uint32_t XBARtriggerMask; /* Enable the corresponding trigger source. Available range is trigger0:0x01 to + trigger7:0x80 + For example, XBARtriggerMask = 0x7U, which means trigger0, trigger1 and trigger2 is + enabled. */ +} adc_etc_config_t; + +/*! + * @brief ADC_ETC trigger chain configuration. + */ +typedef struct _adc_etc_trigger_chain_config +{ + bool enableB2BMode; /* Enable ADC_ETC BackToBack mode. when not enabled B2B mode, + wait until interval delay is reached. */ + uint32_t ADCHCRegisterSelect; /* Select relevant ADC_HCx register to trigger. 1U : HC0, 2U: HC1, 4U: HC2 ... */ + uint32_t ADCChannelSelect; /* Select ADC sample channel. */ + adc_etc_interrupt_enable_t InterruptEnable; /* Enable/disable Interrupt. */ +} adc_etc_trigger_chain_config_t; + +/*! + * @brief ADC_ETC trigger configuration. + */ +typedef struct _adc_etc_trigger_config +{ + bool enableSyncMode; /* Enable the sync Mode, In SyncMode ADC1 and ADC2 are controlled by the same trigger source. + In AsyncMode ADC1 and ADC2 are controlled by separate trigger source. */ + bool enableSWTriggerMode; /* Enable the sofware trigger mode. */ + uint32_t triggerChainLength; /* TRIG chain length to the ADC. 0: Trig length is 1. ... 7: Trig length is 8. */ + uint32_t triggerPriority; /* External trigger priority, 7 is highest, 0 is lowest. */ + uint32_t sampleIntervalDelay; /* Set sampling interval delay. */ + uint32_t initialDelay; /* Set trigger initial delay. */ +} adc_etc_trigger_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initialize the ADC_ETC module. + * + * @param base ADC_ETC peripheral base address. + * @param config Pointer to "adc_etc_config_t" structure. + */ +void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config); + +/*! + * @brief De-Initialize the ADC_ETC module. + * + * @param base ADC_ETC peripheral base address. + */ +void ADC_ETC_Deinit(ADC_ETC_Type *base); + +/*! + * @brief Gets an available pre-defined settings for the ADC_ETC's configuration. + * This function initializes the ADC_ETC's configuration structure with available settings. The default values are: + * @code + * config->enableTSCBypass = true; + * config->enableTSC0Trigger = false; + * config->enableTSC1Trigger = false; + * config->TSC0triggerPriority = 0U; + * config->TSC1triggerPriority = 0U; + * config->clockPreDivider = 0U; + * config->XBARtriggerMask = 0U; + * @endCode + * + * @param config Pointer to "adc_etc_config_t" structure. + */ +void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config); + +/*! + * @brief Set the external XBAR trigger configuration. + * + * @param base ADC_ETC peripheral base address. + * @param triggerGroup Trigger group index. + * @param config Pointer to "adc_etc_trigger_config_t" structure. + */ +void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config); + +/*! + * @brief Set the external XBAR trigger chain configuration. + * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be + * configurated. + * + * @param base ADC_ETC peripheral base address. + * @param triggerGroup Trigger group index. Available number is 0~7. + * @param chainGroup Trigger chain group index. Available number is 0~7. + * @param config Pointer to "adc_etc_trigger_chain_config_t" structure. + */ +void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base, + uint32_t triggerGroup, + uint32_t chainGroup, + const adc_etc_trigger_chain_config_t *config); + +/*! + * @brief Gets the interrupt status flags of external XBAR and TSC triggers. + * + * @param base ADC_ETC peripheral base address. + * @param sourceIndex trigger source index. + * + * @return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask". + */ +uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex); + +/*! + * @brief Clears the ADC_ETC's interrupt status falgs. + * + * @param base ADC_ETC peripheral base address. + * @param sourceIndex trigger source index. + * @param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask". + */ +void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base, + adc_etc_external_trigger_source_t sourceIndex, + uint32_t mask); + +/*! + * @brief Enable the DMA corresponding to each trigger source. + * + * @param base ADC_ETC peripheral base address. + * @param triggerGroup Trigger group index. Available number is 0~7. + */ +static inline void ADC_ETC_EnableDMA(ADC_ETC_Type *base, uint32_t triggerGroup) +{ + /* Avoid clearing status flags at the same time. */ + base->DMA_CTRL = + (base->DMA_CTRL | (ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK << triggerGroup)) & ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK; +} + +/*! + * @brief Disable the DMA corresponding to each trigger sources. + * + * @param base ADC_ETC peripheral base address. + * @param triggerGroup Trigger group index. Available number is 0~7. + */ +static inline void ADC_ETC_DisableDMA(ADC_ETC_Type *base, uint32_t triggerGroup) +{ + /* Avoid clearing status flags at the same time. */ + base->DMA_CTRL = + (base->DMA_CTRL & ~(ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK << triggerGroup)) & ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK; +} + +/*! + * @brief Get the DMA request status falgs. Only external XBAR sources support DMA request. + * + * @param base ADC_ETC peripheral base address. + * @return Mask of external XBAR tirgger's DMA request asserted flags. Available range is trigger0:0x01 to + * trigger7:0x80. + */ +static inline uint32_t ADC_ETC_GetDMAStatusFlags(ADC_ETC_Type *base) +{ + return (((base->DMA_CTRL) & ADC_ETC_DMA_CTRL_TRGn_REQ_MASK) >> ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT); +} + +/*! + * @brief Clear the DMA request status falgs. Only external XBAR sources support DMA request. + * + * @param base ADC_ETC peripheral base address. + * @param mask Mask of external XBAR tirgger's DMA request asserted flags. Available range is trigger0:0x01 to + * trigger7:0x80. + */ +static inline void ADC_ETC_ClearDMAStatusFlags(ADC_ETC_Type *base, uint32_t mask) +{ + base->DMA_CTRL = ((base->DMA_CTRL) & ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK) | (mask << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT); +} + +/*! + * @brief When enable ,all logical will be reset. + * + * @param base ADC_ETC peripheral base address. + * @param enable Enable/Disable the software reset. + */ +static inline void ADC_ETC_DoSoftwareReset(ADC_ETC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= ADC_ETC_CTRL_SOFTRST_MASK; + } + else + { + base->CTRL &= ~ADC_ETC_CTRL_SOFTRST_MASK; + } +} + +/*! + * @brief Do software trigger corresponding to each XBAR trigger sources. + * Each XBAR trigger sources can be configured as HW or SW trigger mode. In hardware trigger mode, + * trigger source is from XBAR. In software mode, trigger source is from software tigger. TSC trigger sources + * can only work in hardware trigger mode. + * + * @param base ADC_ETC peripheral base address. + * @param triggerGroup Trigger group index. Available number is 0~7. + */ +static inline void ADC_ETC_DoSoftwareTrigger(ADC_ETC_Type *base, uint32_t triggerGroup) +{ + assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT); + + base->TRIG[triggerGroup].TRIGn_CTRL |= ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK; +} + +/*! + * @brief Get ADC conversion result from external XBAR sources. + * For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would + * return Trigger0 source's chain1 conversion result. + * + * @param base ADC_ETC peripheral base address. + * @param triggerGroup Trigger group index. Available number is 0~7. + * @param chainGroup Trigger chain group index. Available number is 0~7. + * @return ADC conversion result value. + */ +uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup); + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_ADC_ETC_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_aipstz.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_aipstz.c new file mode 100644 index 0000000000..cef6997595 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_aipstz.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_aipstz.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.aipstz" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * brief Configure the privilege level for master. + * + * param base AIPSTZ peripheral base pointer + * param master Masters for AIPSTZ. + * param privilegeConfig Configuration is ORed from aipstz_master_privilege_level_t. + */ +void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig) +{ + uint32_t mask = ((uint32_t)master >> 8) - 1; + uint32_t shift = (uint32_t)master & 0xFF; + base->MPR = (base->MPR & (~(mask << shift))) | (privilegeConfig << shift); +} + +/*! + * brief Configure the access for peripheral. + * + * param base AIPSTZ peripheral base pointer + * param master Peripheral for AIPSTZ. + * param accessControl Configuration is ORed from aipstz_peripheral_access_control_t. + */ +void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl) +{ + volatile uint32_t *reg = (uint32_t *)((uint32_t)base + ((uint32_t)peripheral >> 16)); + uint32_t mask = (((uint32_t)peripheral & 0xFF00U) >> 8) - 1; + uint32_t shift = (uint32_t)peripheral & 0xFF; + + *reg = (*reg & (~(mask << shift))) | ((accessControl & mask) << shift); +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_aipstz.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_aipstz.h new file mode 100644 index 0000000000..432e0d52ef --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_aipstz.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_AIPSTZ_H_ +#define _FSL_AIPSTZ_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup aipstz + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_AIPSTZ_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief List of AIPSTZ privilege configuration.*/ +typedef enum _aipstz_master_privilege_level +{ + kAIPSTZ_MasterBufferedWriteEnable = (1U << 3), /*!< Write accesses from this master are allowed to be buffered. */ + kAIPSTZ_MasterTrustedForReadEnable = (1U << 2), /*!< This master is trusted for read accesses. */ + kAIPSTZ_MasterTrustedForWriteEnable = (1U << 1), /*!< This master is trusted for write accesses. */ + kAIPSTZ_MasterForceUserModeEnable = 1U /*!< Accesses from this master are forced to user-mode. */ +} aipstz_master_privilege_level_t; + +/*! @brief List of AIPSTZ masters. Organized by width for the 8-15 bits and shift for lower 8 bits.*/ +typedef enum _aipstz_master +{ + kAIPSTZ_Master0 = (0x400U | 28U), + kAIPSTZ_Master1 = (0x400U | 24U), + kAIPSTZ_Master2 = (0x400U | 20U), + kAIPSTZ_Master3 = (0x400U | 16U), + kAIPSTZ_Master5 = (0x400U | 8U) +} aipstz_master_t; + +/*! @brief List of AIPSTZ peripheral access control configuration.*/ +typedef enum _aipstz_peripheral_access_control +{ + kAIPSTZ_PeripheralAllowUntrustedMaster = 1U, + kAIPSTZ_PeripheralWriteProtected = (1U << 1), + kAIPSTZ_PeripheralRequireSupervisor = (1U << 2), + kAIPSTZ_PeripheralAllowBufferedWrite = (1U << 3) +} aipstz_peripheral_access_control_t; + +/*! @brief List of AIPSTZ peripherals. Organized by register offset for higher 32 bits, width for the 8-15 bits and + * shift for lower 8 bits.*/ +typedef enum _aipstz_peripheral +{ + kAIPSTZ_Peripheral0 = ((0x40 << 16) | (4 << 8) | 28), + kAIPSTZ_Peripheral1 = ((0x40 << 16) | (4 << 8) | 24), + kAIPSTZ_Peripheral2 = ((0x40 << 16) | (4 << 8) | 20), + kAIPSTZ_Peripheral3 = ((0x40 << 16) | (4 << 8) | 16), + kAIPSTZ_Peripheral4 = ((0x40 << 16) | (4 << 8) | 12), + kAIPSTZ_Peripheral5 = ((0x40 << 16) | (4 << 8) | 8), + kAIPSTZ_Peripheral6 = ((0x40 << 16) | (4 << 8) | 4), + kAIPSTZ_Peripheral7 = ((0x40 << 16) | (4 << 8) | 0), + kAIPSTZ_Peripheral8 = ((0x44 << 16) | (4 << 8) | 28), + kAIPSTZ_Peripheral9 = ((0x44 << 16) | (4 << 8) | 24), + kAIPSTZ_Peripheral10 = ((0x44 << 16) | (4 << 8) | 20), + kAIPSTZ_Peripheral11 = ((0x44 << 16) | (4 << 8) | 16), + kAIPSTZ_Peripheral12 = ((0x44 << 16) | (4 << 8) | 12), + kAIPSTZ_Peripheral13 = ((0x44 << 16) | (4 << 8) | 8), + kAIPSTZ_Peripheral14 = ((0x44 << 16) | (4 << 8) | 4), + kAIPSTZ_Peripheral15 = ((0x44 << 16) | (4 << 8) | 0), + kAIPSTZ_Peripheral16 = ((0x48 << 16) | (4 << 8) | 28), + kAIPSTZ_Peripheral17 = ((0x48 << 16) | (4 << 8) | 24), + kAIPSTZ_Peripheral18 = ((0x48 << 16) | (4 << 8) | 20), + kAIPSTZ_Peripheral19 = ((0x48 << 16) | (4 << 8) | 16), + kAIPSTZ_Peripheral20 = ((0x48 << 16) | (4 << 8) | 12), + kAIPSTZ_Peripheral21 = ((0x48 << 16) | (4 << 8) | 8), + kAIPSTZ_Peripheral22 = ((0x48 << 16) | (4 << 8) | 4), + kAIPSTZ_Peripheral23 = ((0x48 << 16) | (4 << 8) | 0), + kAIPSTZ_Peripheral24 = ((0x4C << 16) | (4 << 8) | 28), + kAIPSTZ_Peripheral25 = ((0x4C << 16) | (4 << 8) | 24), + kAIPSTZ_Peripheral26 = ((0x4C << 16) | (4 << 8) | 20), + kAIPSTZ_Peripheral27 = ((0x4C << 16) | (4 << 8) | 16), + kAIPSTZ_Peripheral28 = ((0x4C << 16) | (4 << 8) | 12), + kAIPSTZ_Peripheral29 = ((0x4C << 16) | (4 << 8) | 8), + kAIPSTZ_Peripheral30 = ((0x4C << 16) | (4 << 8) | 4), + kAIPSTZ_Peripheral31 = ((0x4C << 16) | (4 << 8) | 0), + kAIPSTZ_Peripheral32 = ((0x50 << 16) | (4 << 8) | 28), + kAIPSTZ_Peripheral33 = ((0x50 << 16) | (4 << 8) | 24) +} aipstz_peripheral_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Configure the privilege level for master. + * + * @param base AIPSTZ peripheral base pointer + * @param master Masters for AIPSTZ. + * @param privilegeConfig Configuration is ORed from @aipstz_master_privilege_level_t. + */ +void AIPSTZ_SetMasterPriviledgeLevel(AIPSTZ_Type *base, aipstz_master_t master, uint32_t privilegeConfig); + +/*! + * @brief Configure the access for peripheral. + * + * @param base AIPSTZ peripheral base pointer + * @param master Peripheral for AIPSTZ. + * @param accessControl Configuration is ORed from @aipstz_peripheral_access_control_t. + */ +void AIPSTZ_SetPeripheralAccessControl(AIPSTZ_Type *base, aipstz_peripheral_t peripheral, uint32_t accessControl); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_AIPSTZ_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_aoi.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_aoi.c new file mode 100644 index 0000000000..85d8b1fe97 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_aoi.c @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_aoi.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.aoi" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to aoi bases for each instance. */ +static AOI_Type *const s_aoiBases[] = AOI_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to aoi clocks for each instance. */ +static const clock_ip_name_t s_aoiClocks[] = AOI_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for AOI module. + * + * @param base AOI peripheral base address + * + * @return The AOI instance + */ +static uint32_t AOI_GetInstance(AOI_Type *base); +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t AOI_GetInstance(AOI_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_aoiBases); instance++) + { + if (s_aoiBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_aoiBases)); + + return instance; +} + +/*! + * brief Initializes an AOI instance for operation. + * + * This function un-gates the AOI clock. + * + * param base AOI peripheral address. + */ +void AOI_Init(AOI_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock gate from clock manager. */ + CLOCK_EnableClock(s_aoiClocks[AOI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Deinitializes an AOI instance for operation. + * + * This function shutdowns AOI module. + * + * param base AOI peripheral address. + */ +void AOI_Deinit(AOI_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock gate from clock manager */ + CLOCK_DisableClock(s_aoiClocks[AOI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets the Boolean evaluation associated. + * + * This function returns the Boolean evaluation associated. + * + * Example: + code + aoi_event_config_t demoEventLogicStruct; + + AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct); + endcode + * + * param base AOI peripheral address. + * param event Index of the event which will be set of type aoi_event_t. + * param config Selected input configuration . + */ +void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config) +{ + assert(event < FSL_FEATURE_AOI_EVENT_COUNT); + assert(config != NULL); + + uint16_t value = 0; + /* Read BFCRT01 register at event index. */ + value = base->BFCRT[event].BFCRT01; + + config->PT0AC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_AC_MASK) >> AOI_BFCRT01_PT0_AC_SHIFT); + config->PT0BC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_BC_MASK) >> AOI_BFCRT01_PT0_BC_SHIFT); + config->PT0CC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_CC_MASK) >> AOI_BFCRT01_PT0_CC_SHIFT); + config->PT0DC = (aoi_input_config_t)((value & AOI_BFCRT01_PT0_DC_MASK) >> AOI_BFCRT01_PT0_DC_SHIFT); + + config->PT1AC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_AC_MASK) >> AOI_BFCRT01_PT1_AC_SHIFT); + config->PT1BC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_BC_MASK) >> AOI_BFCRT01_PT1_BC_SHIFT); + config->PT1CC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_CC_MASK) >> AOI_BFCRT01_PT1_CC_SHIFT); + config->PT1DC = (aoi_input_config_t)((value & AOI_BFCRT01_PT1_DC_MASK) >> AOI_BFCRT01_PT1_DC_SHIFT); + + /* Read BFCRT23 register at event index. */ + value = 0; + value = base->BFCRT[event].BFCRT23; + + config->PT2AC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_AC_MASK) >> AOI_BFCRT23_PT2_AC_SHIFT); + config->PT2BC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_BC_MASK) >> AOI_BFCRT23_PT2_BC_SHIFT); + config->PT2CC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_CC_MASK) >> AOI_BFCRT23_PT2_CC_SHIFT); + config->PT2DC = (aoi_input_config_t)((value & AOI_BFCRT23_PT2_DC_MASK) >> AOI_BFCRT23_PT2_DC_SHIFT); + + config->PT3AC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_AC_MASK) >> AOI_BFCRT23_PT3_AC_SHIFT); + config->PT3BC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_BC_MASK) >> AOI_BFCRT23_PT3_BC_SHIFT); + config->PT3CC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_CC_MASK) >> AOI_BFCRT23_PT3_CC_SHIFT); + config->PT3DC = (aoi_input_config_t)((value & AOI_BFCRT23_PT3_DC_MASK) >> AOI_BFCRT23_PT3_DC_SHIFT); +} + +/*! + * brief Configures an AOI event. + * + * This function configures an AOI event according + * to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D) + * of all product terms (0, 1, 2, and 3) of a desired event. + * + * Example: + code + aoi_event_config_t demoEventLogicStruct; + + demoEventLogicStruct.PT0AC = kAOI_InvInputSignal; + demoEventLogicStruct.PT0BC = kAOI_InputSignal; + demoEventLogicStruct.PT0CC = kAOI_LogicOne; + demoEventLogicStruct.PT0DC = kAOI_LogicOne; + + demoEventLogicStruct.PT1AC = kAOI_LogicZero; + demoEventLogicStruct.PT1BC = kAOI_LogicOne; + demoEventLogicStruct.PT1CC = kAOI_LogicOne; + demoEventLogicStruct.PT1DC = kAOI_LogicOne; + + demoEventLogicStruct.PT2AC = kAOI_LogicZero; + demoEventLogicStruct.PT2BC = kAOI_LogicOne; + demoEventLogicStruct.PT2CC = kAOI_LogicOne; + demoEventLogicStruct.PT2DC = kAOI_LogicOne; + + demoEventLogicStruct.PT3AC = kAOI_LogicZero; + demoEventLogicStruct.PT3BC = kAOI_LogicOne; + demoEventLogicStruct.PT3CC = kAOI_LogicOne; + demoEventLogicStruct.PT3DC = kAOI_LogicOne; + + AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct); + endcode + * + * param base AOI peripheral address. + * param event Event which will be configured of type aoi_event_t. + * param eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for + * filling out the members of this structure and passing the pointer to this function. + */ +void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig) +{ + assert(eventConfig != NULL); + assert(event < FSL_FEATURE_AOI_EVENT_COUNT); + + uint16_t value = 0; + /* Calculate value to configure product term 0, 1 */ + value = AOI_BFCRT01_PT0_AC(eventConfig->PT0AC) | AOI_BFCRT01_PT0_BC(eventConfig->PT0BC) | + AOI_BFCRT01_PT0_CC(eventConfig->PT0CC) | AOI_BFCRT01_PT0_DC(eventConfig->PT0DC) | + AOI_BFCRT01_PT1_AC(eventConfig->PT1AC) | AOI_BFCRT01_PT1_BC(eventConfig->PT1BC) | + AOI_BFCRT01_PT1_CC(eventConfig->PT1CC) | AOI_BFCRT01_PT1_DC(eventConfig->PT1DC); + /* Write value to register */ + base->BFCRT[event].BFCRT01 = value; + + /* Reset and calculate value to configure product term 2, 3 */ + value = 0; + value = AOI_BFCRT23_PT2_AC(eventConfig->PT2AC) | AOI_BFCRT23_PT2_BC(eventConfig->PT2BC) | + AOI_BFCRT23_PT2_CC(eventConfig->PT2CC) | AOI_BFCRT23_PT2_DC(eventConfig->PT2DC) | + AOI_BFCRT23_PT3_AC(eventConfig->PT3AC) | AOI_BFCRT23_PT3_BC(eventConfig->PT3BC) | + AOI_BFCRT23_PT3_CC(eventConfig->PT3CC) | AOI_BFCRT23_PT3_DC(eventConfig->PT3DC); + /* Write value to register */ + base->BFCRT[event].BFCRT23 = value; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_aoi.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_aoi.h new file mode 100644 index 0000000000..ca6cd73b79 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_aoi.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_AOI_H_ +#define _FSL_AOI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup aoi + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef AOI +#define AOI AOI0 /*!< AOI peripheral address */ +#endif + +/*! @name Driver version */ +/*@{*/ +#define FSL_AOI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +/*@}*/ + +/*! + * @brief AOI input configurations. + * + * The selection item represents the Boolean evaluations. + */ +typedef enum _aoi_input_config +{ + kAOI_LogicZero = 0x0U, /*!< Forces the input to logical zero. */ + kAOI_InputSignal = 0x1U, /*!< Passes the input signal. */ + kAOI_InvInputSignal = 0x2U, /*!< Inverts the input signal. */ + kAOI_LogicOne = 0x3U /*!< Forces the input to logical one. */ +} aoi_input_config_t; + +/*! + * @brief AOI event indexes, where an event is the collection of the four product + * terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D). + */ +typedef enum _aoi_event +{ + kAOI_Event0 = 0x0U, /*!< Event 0 index */ + kAOI_Event1 = 0x1U, /*!< Event 1 index */ + kAOI_Event2 = 0x2U, /*!< Event 2 index */ + kAOI_Event3 = 0x3U /*!< Event 3 index */ +} aoi_event_t; + +/*! + * @brief AOI event configuration structure + * + * Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make + * whole event configuration. + */ +typedef struct _aoi_event_config +{ + aoi_input_config_t PT0AC; /*!< Product term 0 input A */ + aoi_input_config_t PT0BC; /*!< Product term 0 input B */ + aoi_input_config_t PT0CC; /*!< Product term 0 input C */ + aoi_input_config_t PT0DC; /*!< Product term 0 input D */ + aoi_input_config_t PT1AC; /*!< Product term 1 input A */ + aoi_input_config_t PT1BC; /*!< Product term 1 input B */ + aoi_input_config_t PT1CC; /*!< Product term 1 input C */ + aoi_input_config_t PT1DC; /*!< Product term 1 input D */ + aoi_input_config_t PT2AC; /*!< Product term 2 input A */ + aoi_input_config_t PT2BC; /*!< Product term 2 input B */ + aoi_input_config_t PT2CC; /*!< Product term 2 input C */ + aoi_input_config_t PT2DC; /*!< Product term 2 input D */ + aoi_input_config_t PT3AC; /*!< Product term 3 input A */ + aoi_input_config_t PT3BC; /*!< Product term 3 input B */ + aoi_input_config_t PT3CC; /*!< Product term 3 input C */ + aoi_input_config_t PT3DC; /*!< Product term 3 input D */ +} aoi_event_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @name AOI Initialization + * @{ + */ + +/*! + * @brief Initializes an AOI instance for operation. + * + * This function un-gates the AOI clock. + * + * @param base AOI peripheral address. + */ +void AOI_Init(AOI_Type *base); + +/*! + * @brief Deinitializes an AOI instance for operation. + * + * This function shutdowns AOI module. + * + * @param base AOI peripheral address. + */ +void AOI_Deinit(AOI_Type *base); + +/*@}*/ + +/*! + * @name AOI Get Set Operation + * @{ + */ + +/*! + * @brief Gets the Boolean evaluation associated. + * + * This function returns the Boolean evaluation associated. + * + * Example: + @code + aoi_event_config_t demoEventLogicStruct; + + AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct); + @endcode + * + * @param base AOI peripheral address. + * @param event Index of the event which will be set of type aoi_event_t. + * @param config Selected input configuration . + */ +void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config); + +/*! + * @brief Configures an AOI event. + * + * This function configures an AOI event according + * to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D) + * of all product terms (0, 1, 2, and 3) of a desired event. + * + * Example: + @code + aoi_event_config_t demoEventLogicStruct; + + demoEventLogicStruct.PT0AC = kAOI_InvInputSignal; + demoEventLogicStruct.PT0BC = kAOI_InputSignal; + demoEventLogicStruct.PT0CC = kAOI_LogicOne; + demoEventLogicStruct.PT0DC = kAOI_LogicOne; + + demoEventLogicStruct.PT1AC = kAOI_LogicZero; + demoEventLogicStruct.PT1BC = kAOI_LogicOne; + demoEventLogicStruct.PT1CC = kAOI_LogicOne; + demoEventLogicStruct.PT1DC = kAOI_LogicOne; + + demoEventLogicStruct.PT2AC = kAOI_LogicZero; + demoEventLogicStruct.PT2BC = kAOI_LogicOne; + demoEventLogicStruct.PT2CC = kAOI_LogicOne; + demoEventLogicStruct.PT2DC = kAOI_LogicOne; + + demoEventLogicStruct.PT3AC = kAOI_LogicZero; + demoEventLogicStruct.PT3BC = kAOI_LogicOne; + demoEventLogicStruct.PT3CC = kAOI_LogicOne; + demoEventLogicStruct.PT3DC = kAOI_LogicOne; + + AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct); + @endcode + * + * @param base AOI peripheral address. + * @param event Event which will be configured of type aoi_event_t. + * @param eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for + * filling out the members of this structure and passing the pointer to this function. + */ +void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*@}*/ + +/*!* @} */ + +#endif /* _FSL_AOI_H_*/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_bee.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_bee.c new file mode 100644 index 0000000000..3632743903 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_bee.c @@ -0,0 +1,303 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_bee.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.bee" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void aligned_memcpy(void *dst, const void *src, size_t size) +{ + register uint32_t *to32 = (uint32_t *)(uintptr_t)dst; + register const uint32_t *from32 = (const uint32_t *)(uintptr_t)src; + + while (size >= sizeof(uint32_t)) + { + *to32 = *from32; + size -= sizeof(uint32_t); + to32++; + from32++; + } +} + +/*! + * brief Resets BEE module to factory default values. + * + * This function performs hardware reset of BEE module. Attributes and keys from software for both regions are cleared. + * + * param base BEE peripheral address. + */ +void BEE_Init(BEE_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Bee); +#endif + + base->CTRL = BEE_CTRL_CTRL_SFTRST_N_MASK | BEE_CTRL_CTRL_CLK_EN_MASK; +} + +/*! + * brief Resets BEE module, clears keys for both regions and disables clock to the BEE. + * + * This function performs hardware reset of BEE module and disables clocks. Attributes and keys from software for both + * regions are cleared. + * + * param base BEE peripheral address. + */ +void BEE_Deinit(BEE_Type *base) +{ + base->CTRL &= + ~(BEE_CTRL_BEE_ENABLE_MASK | BEE_CTRL_CTRL_SFTRST_N_MASK | BEE_CTRL_CTRL_CLK_EN_MASK | BEE_CTRL_KEY_VALID_MASK); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_Bee); +#endif +} + +/*! + * brief Loads default values to the BEE region configuration structure. + * + * Loads default values to the BEE region configuration structure. The default values are as follows: + * code + * config->region0Mode = kBEE_AesCtrMode; + * config->region1Mode = kBEE_AesCtrMode; + * config->region0AddrOffset = 0U; + * config->region1AddrOffset = 0U; + * config->region0SecLevel = kBEE_SecurityLevel3; + * config->region1SecLevel = kBEE_SecurityLevel3; + * config->region1Bot = 0U; + * config->region1Top = 0U; + * config->accessPermission = kBEE_AccessProtDisabled; + * config->endianSwapEn = kBEE_EndianSwapEnabled; + * endcode + * + * param config Configuration structure for BEE peripheral. + */ +void BEE_GetDefaultConfig(bee_region_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->region0Mode = kBEE_AesCtrMode; + config->region1Mode = kBEE_AesCtrMode; + config->region0AddrOffset = 0U; + config->region1AddrOffset = 0U; + config->region0SecLevel = kBEE_SecurityLevel3; + config->region1SecLevel = kBEE_SecurityLevel3; + config->region1Bot = 0U; + config->region1Top = 0U; + config->accessPermission = kBEE_AccessProtDisabled; + config->endianSwapEn = kBEE_EndianSwapEnabled; +} + +/*! + * brief Sets BEE configuration. + * + * This function sets BEE peripheral and BEE region settings accorging to given configuration structure. + * + * param base BEE peripheral address. + * param config Configuration structure for BEE. + */ +void BEE_SetConfig(BEE_Type *base, const bee_region_config_t *config) +{ + uint32_t beeCtrlVal; + bool reenable = false; + + /* Wait until BEE is in idle state */ + while (!(BEE_GetStatusFlags(base) & kBEE_IdleFlag)) + { + } + + /* Disable BEE before region configuration in case it is enabled. */ + if (base->CTRL & BEE_CTRL_BEE_ENABLE_MASK) + { + BEE_Disable(base); + reenable = true; + } + + /* Preserve CTRL bit values that are not set by this function */ + beeCtrlVal = base->CTRL & 0xFFFF0037; + + /* Set variable according to configuration */ + beeCtrlVal |= BEE_CTRL_AC_PROT_EN(config->accessPermission) | BEE_CTRL_LITTLE_ENDIAN(config->endianSwapEn) | + BEE_CTRL_SECURITY_LEVEL_R0(config->region0SecLevel) | BEE_CTRL_CTRL_AES_MODE_R0(config->region0Mode) | + BEE_CTRL_SECURITY_LEVEL_R1(config->region1SecLevel) | BEE_CTRL_CTRL_AES_MODE_R1(config->region1Mode); + + /* Load values to registers */ + base->CTRL = beeCtrlVal; + base->ADDR_OFFSET0 = config->region0AddrOffset; + base->ADDR_OFFSET1 = config->region1AddrOffset; + base->REGION1_BOT = config->region1Bot; + base->REGION1_TOP = config->region1Top; + + /* Reenable BEE if it was enabled before. */ + if (reenable) + { + BEE_Enable(base); + } +} + +/*! + * brief Loads the AES key for selected region into BEE key registers. + * + * This function loads given AES key to BEE register for the given region. + * The key must be 32-bit aligned and stored in little-endian format. + * + * Please note, that eFuse BEE_KEYx_SEL must be set accordingly to be able to load and use key loaded in BEE registers. + * Otherwise, key cannot loaded and BEE will use key from OTPMK or SW_GP2. + * + * param base BEE peripheral address. + * param region Selection of the BEE region to be configured. + * param key AES key (in little-endian format). + * param keySize Size of AES key. + */ +status_t BEE_SetRegionKey(BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize) +{ + bool redisable = false; + + /* Key must be 32-bit aligned */ + if (((uintptr_t)key & 0x3u) || (keySize != 16)) + { + return kStatus_InvalidArgument; + } + + /* Wait until BEE is in idle state */ + while (!(BEE_GetStatusFlags(base) & kBEE_IdleFlag)) + { + } + + /* Clear KEY_VALID bit before new key is loaded */ + base->CTRL &= ~BEE_CTRL_KEY_VALID_MASK; + + /* Write key registers, key is stored in little-endian format in memory */ + aligned_memcpy((uint32_t *)&base->AES_KEY0_W0, key, keySize); + + /* Enable BEE before key configuration. */ + if (!(base->CTRL & BEE_CTRL_BEE_ENABLE_MASK)) + { + BEE_Enable(base); + redisable = true; + } + + if (region == kBEE_Region0) + { + base->CTRL &= ~BEE_CTRL_KEY_REGION_SEL_MASK; + } + + else if (region == kBEE_Region1) + { + base->CTRL |= BEE_CTRL_KEY_REGION_SEL_MASK; + } + + else + { + return kStatus_InvalidArgument; + } + + /* Set KEY_VALID bit to trigger key loading */ + base->CTRL |= BEE_CTRL_KEY_VALID_MASK; + /* Wait until key is ready */ + while (!(base->CTRL & BEE_CTRL_KEY_VALID_MASK)) + { + } + + /* Redisable BEE if it was disabled before this function call. */ + if (redisable) + { + BEE_Disable(base); + } + + return kStatus_Success; +} + +/*! + * brief Loads the nonce for selected region into BEE nonce registers. + * + * This function loads given nonce(only AES CTR mode) to BEE register for the given region. + * The nonce must be 32-bit aligned and stored in little-endian format. + * + * param base BEE peripheral address. + * param region Selection of the BEE region to be configured. + * param nonce AES nonce (in little-endian format). + * param nonceSize Size of AES nonce. + */ +status_t BEE_SetRegionNonce(BEE_Type *base, bee_region_t region, const uint8_t *nonce, size_t nonceSize) +{ + /* Nonce must be 32-bit aligned */ + if (((uintptr_t)nonce & 0x3u) || (nonceSize != 16)) + { + return kStatus_InvalidArgument; + } + + /* Wait until BEE is in idle state */ + while (!(BEE_GetStatusFlags(base) & kBEE_IdleFlag)) + { + } + + /* Write nonce registers, nonce is stored in little-endian format in memory */ + if (region == kBEE_Region0) + { + aligned_memcpy((uint32_t *)&base->CTR_NONCE0_W0, nonce, nonceSize); + } + + else if (region == kBEE_Region1) + { + aligned_memcpy((uint32_t *)&base->CTR_NONCE1_W0, nonce, nonceSize); + } + + else + { + return kStatus_InvalidArgument; + } + + return kStatus_Success; +} + +/*! + * brief Gets the BEE status flags. + * + * This function returns status of BEE peripheral. + * + * param base BEE peripheral address. + * + * return The status flags. This is the logical OR of members of the + * enumeration ::bee_status_flags_t + */ +uint32_t BEE_GetStatusFlags(BEE_Type *base) +{ + return base->STATUS; +} + +/*! + * brief Clears the BEE status flags. + * + * param base BEE peripheral base address. + * param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::bee_status_flags_t + */ +void BEE_ClearStatusFlags(BEE_Type *base, uint32_t mask) +{ + /* w1c */ + base->STATUS |= mask; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_bee.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_bee.h new file mode 100644 index 0000000000..77068a7ab6 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_bee.h @@ -0,0 +1,229 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_BEE_H_ +#define _FSL_BEE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup bee + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief BEE driver version. Version 2.0.1. + * + * Current version: 2.0.1 + * + * Change log: + * - Version 2.0.1 + * - Initial version + */ +#define FSL_BEE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +typedef enum _bee_aes_mode +{ + kBEE_AesEcbMode = 0U, /*!< AES ECB Mode */ + kBEE_AesCtrMode = 1U /*!< AES CTR Mode */ +} bee_aes_mode_t; + +typedef enum _bee_region +{ + kBEE_Region0 = 0U, /*!< BEE region 0 */ + kBEE_Region1 = 1U /*!< BEE region 1 */ +} bee_region_t; + +typedef enum _bee_ac_prot_enable +{ + kBEE_AccessProtDisabled = 0U, /*!< BEE access permission control disabled */ + kBEE_AccessProtEnabled = 1U /*!< BEE access permission control enabled */ +} bee_ac_prot_enable; + +typedef enum _bee_endian_swap_enable +{ + kBEE_EndianSwapDisabled = 1U, /*!< BEE endian swap disabled */ + kBEE_EndianSwapEnabled = 0U /*!< BEE endian swap enabled */ +} bee_endian_swap_enable; + +typedef enum _bee_security_level +{ + kBEE_SecurityLevel0 = 0U, /*!< BEE security level 0 */ + kBEE_SecurityLevel1 = 1U, /*!< BEE security level 1 */ + kBEE_SecurityLevel2 = 2U, /*!< BEE security level 2 */ + kBEE_SecurityLevel3 = 3U /*!< BEE security level 3 */ +} bee_security_level; + +typedef enum _bee_status_flags +{ + kBEE_DisableAbortFlag = 1U, /*!< Disable abort flag. */ + kBEE_Reg0ReadSecViolation = 2U, /*!< Region-0 read channel security violation */ + kBEE_ReadIllegalAccess = 4U, /*!< Read channel illegal access detected */ + kBEE_Reg1ReadSecViolation = 8U, /*!< Region-1 read channel security violation */ + kBEE_Reg0AccessViolation = 16U, /*!< Protected region-0 access violation */ + kBEE_Reg1AccessViolation = 32U, /*!< Protected region-1 access violation */ + kBEE_IdleFlag = BEE_STATUS_BEE_IDLE_MASK /*!< Idle flag */ +} bee_status_flags_t; + +/*! @brief BEE region configuration structure. */ +typedef struct _bee_region_config +{ + bee_aes_mode_t region0Mode; /*!< AES mode used for encryption/decryption for region 0 */ + bee_aes_mode_t region1Mode; /*!< AES mode used for encryption/decryption for region 1 */ + uint32_t region0AddrOffset; /*!< Region 0 address offset */ + uint32_t region1AddrOffset; /*!< Region 1 address offset */ + bee_security_level region0SecLevel; /*!< Region 0 security level */ + bee_security_level region1SecLevel; /*!< Region 1 security level */ + uint32_t region1Bot; /*!< Region 1 bottom address */ + uint32_t region1Top; /*!< Region 1 top address */ + bee_ac_prot_enable accessPermission; /*!< Access permission control enable/disable */ + bee_endian_swap_enable endianSwapEn; /*!< Endian swap enable/disable */ +} bee_region_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Resets BEE module to factory default values. + * + * This function performs hardware reset of BEE module. Attributes and keys from software for both regions are cleared. + * + * @param base BEE peripheral address. + */ +void BEE_Init(BEE_Type *base); + +/*! + * @brief Resets BEE module, clears keys for both regions and disables clock to the BEE. + * + * This function performs hardware reset of BEE module and disables clocks. Attributes and keys from software for both + * regions are cleared. + * + * @param base BEE peripheral address. + */ +void BEE_Deinit(BEE_Type *base); + +/*! + * @brief Enables BEE decryption. + * + * This function enables decryption using BEE. + * + * @param base BEE peripheral address. + */ +static inline void BEE_Enable(BEE_Type *base) +{ + base->CTRL |= BEE_CTRL_BEE_ENABLE_MASK; +} + +/*! + * @brief Disables BEE decryption. + * + * This function disables decryption using BEE. + * + * @param base BEE peripheral address. + */ +static inline void BEE_Disable(BEE_Type *base) +{ + base->CTRL &= ~BEE_CTRL_BEE_ENABLE_MASK; +} + +/*! + * @brief Loads default values to the BEE region configuration structure. + * + * Loads default values to the BEE region configuration structure. The default values are as follows: + * @code + * config->region0Mode = kBEE_AesCtrMode; + * config->region1Mode = kBEE_AesCtrMode; + * config->region0AddrOffset = 0U; + * config->region1AddrOffset = 0U; + * config->region0SecLevel = kBEE_SecurityLevel3; + * config->region1SecLevel = kBEE_SecurityLevel3; + * config->region1Bot = 0U; + * config->region1Top = 0U; + * config->accessPermission = kBEE_AccessProtDisabled; + * config->endianSwapEn = kBEE_EndianSwapEnabled; + * @endcode + * + * @param config Configuration structure for BEE peripheral. + */ +void BEE_GetDefaultConfig(bee_region_config_t *config); + +/*! + * @brief Sets BEE configuration. + * + * This function sets BEE peripheral and BEE region settings accorging to given configuration structure. + * + * @param base BEE peripheral address. + * @param config Configuration structure for BEE. + */ +void BEE_SetConfig(BEE_Type *base, const bee_region_config_t *config); + +/*! + * @brief Loads the AES key for selected region into BEE key registers. + * + * This function loads given AES key to BEE register for the given region. + * The key must be 32-bit aligned and stored in little-endian format. + * + * Please note, that eFuse BEE_KEYx_SEL must be set accordingly to be able to load and use key loaded in BEE registers. + * Otherwise, key cannot loaded and BEE will use key from OTPMK or SW_GP2. + * + * @param base BEE peripheral address. + * @param region Selection of the BEE region to be configured. + * @param key AES key (in little-endian format). + * @param keySize Size of AES key. + */ +status_t BEE_SetRegionKey(BEE_Type *base, bee_region_t region, const uint8_t *key, size_t keySize); + +/*! + * @brief Loads the nonce for selected region into BEE nonce registers. + * + * This function loads given nonce(only AES CTR mode) to BEE register for the given region. + * The nonce must be 32-bit aligned and stored in little-endian format. + * + * @param base BEE peripheral address. + * @param region Selection of the BEE region to be configured. + * @param nonce AES nonce (in little-endian format). + * @param nonceSize Size of AES nonce. + */ +status_t BEE_SetRegionNonce(BEE_Type *base, bee_region_t region, const uint8_t *nonce, size_t nonceSize); + +/*! + * @brief Gets the BEE status flags. + * + * This function returns status of BEE peripheral. + * + * @param base BEE peripheral address. + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::bee_status_flags_t + */ +uint32_t BEE_GetStatusFlags(BEE_Type *base); + +/*! + * @brief Clears the BEE status flags. + * + * @param base BEE peripheral base address. + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::bee_status_flags_t + */ +void BEE_ClearStatusFlags(BEE_Type *base, uint32_t mask); + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_BEE_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_cache.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_cache.c new file mode 100644 index 0000000000..259f299466 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_cache.c @@ -0,0 +1,603 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cache_armv7_m7" +#endif + +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +#define L2CACHE_OPERATION_TIMEOUT 0xFFFFFU +#define L2CACHE_8WAYS_MASK 0xFFU +#define L2CACHE_16WAYS_MASK 0xFFFFU +#define L2CACHE_SMALLWAYS_NUM 8U +#define L2CACHE_1KBCOVERTOB 1024U +#define L2CACHE_SAMLLWAYS_SIZE 16U +#define L2CACHE_LOCKDOWN_REGNUM 8 /*!< Lock down register numbers.*/ + /******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Set for all ways and waiting for the operation finished. + * This is provided for all the background operations. + * + * @param auxCtlReg The auxiliary control register. + * @param regAddr The register address to be operated. + */ +static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr); + +/*! + * @brief Invalidates the Level 2 cache line by physical address. + * This function invalidates a cache line by physcial address. + * + * @param address The physical addderss of the cache. + * The format of the address shall be : + * bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0 + * Tag | index | 0 + * Note: the physical address shall be aligned to the line size - 32B (256 bit). + * so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero. + * If the input address is not aligned, it will be changed to 32-byte aligned address. + * The n is varies according to the index width. + * @return The actual 32-byte aligned physical address be operated. + */ +static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address); + +/*! + * @brief Cleans the Level 2 cache line based on the physical address. + * This function cleans a cache line based on a physcial address. + * + * @param address The physical addderss of the cache. + * The format of the address shall be : + * bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0 + * Tag | index | 0 + * Note: the physical address shall be aligned to the line size - 32B (256 bit). + * so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero. + * If the input address is not aligned, it will be changed to 32-byte aligned address. + * The n is varies according to the index width. + * @return The actual 32-byte aligned physical address be operated. + */ +static uint32_t L2CACHE_CleanLineByAddr(uint32_t address); + +/*! + * @brief Cleans and invalidates the Level 2 cache line based on the physical address. + * This function cleans and invalidates a cache line based on a physcial address. + * + * @param address The physical addderss of the cache. + * The format of the address shall be : + * bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0 + * Tag | index | 0 + * Note: the physical address shall be aligned to the line size - 32B (256 bit). + * so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero. + * If the input address is not aligned, it will be changed to 32-byte aligned address. + * The n is varies according to the index width. + * @return The actual 32-byte aligned physical address be operated. + */ +static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address); + +/*! + * @brief Gets the number of the Level 2 cache and the way size. + * This function cleans and invalidates a cache line based on a physcial address. + * + * @param num_ways The number of the cache way. + * @param size_way The way size. + */ +static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way); +/******************************************************************************* + * Code + ******************************************************************************/ +static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr) +{ + uint16_t mask = L2CACHE_8WAYS_MASK; + uint32_t timeout = L2CACHE_OPERATION_TIMEOUT; + + /* Check the ways used at first. */ + if (auxCtlReg & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) + { + mask = L2CACHE_16WAYS_MASK; + } + + /* Set the opeartion for all ways/entries of the cache. */ + *(uint32_t *)regAddr = mask; + /* Waiting for until the operation is complete. */ + while ((*(volatile uint32_t *)regAddr & mask) && timeout) + { + __ASM("nop"); + timeout--; + } +} + +static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address) +{ + /* Align the address first. */ + address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1); + /* Invalidate the cache line by physical address. */ + L2CACHEC->REG7_INV_PA = address; + + return address; +} + +static uint32_t L2CACHE_CleanLineByAddr(uint32_t address) +{ + /* Align the address first. */ + address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1); + /* Invalidate the cache line by physical address. */ + L2CACHEC->REG7_CLEAN_PA = address; + + return address; +} + +static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address) +{ + /* Align the address first. */ + address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1); + /* Clean and invalidate the cache line by physical address. */ + L2CACHEC->REG7_CLEAN_INV_PA = address; + + return address; +} + +static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way) +{ + assert(num_ways); + assert(size_way); + + uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >> + L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT; + uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >> + L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT; + + *num_ways = (number + 1) * L2CACHE_SMALLWAYS_NUM; + if (!size) + { + /* 0 internally mapped to the same size as 1 - 16KB.*/ + size += 1; + } + *size_way = (1 << (size - 1)) * L2CACHE_SAMLLWAYS_SIZE * L2CACHE_1KBCOVERTOB; +} + +/*! + * brief Initializes the level 2 cache controller module. + * + * param config Pointer to configuration structure. See "l2cache_config_t". + */ +void L2CACHE_Init(l2cache_config_t *config) +{ + assert(config); + + uint16_t waysNum = 0xFFU; /* Default use the 8-way mask. */ + uint8_t count; + uint32_t auxReg = 0; + + /*The aux register must be configured when the cachec is disabled + * So disable first if the cache controller is enabled. + */ + if (L2CACHEC->REG1_CONTROL & L2CACHEC_REG1_CONTROL_CE_MASK) + { + L2CACHE_Disable(); + } + + /* Unlock all entries. */ + if (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) + { + waysNum = 0xFFFFU; + } + + for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count++) + { + L2CACHE_LockdownByWayEnable(count, waysNum, false); + } + + /* Set the ways and way-size etc. */ + auxReg = L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY(config->wayNum) | + L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) | + L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) | + L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) | + L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) | + L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) | L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc); + L2CACHEC->REG1_AUX_CONTROL = auxReg; + + /* Set the tag/data ram latency. */ + if (config->lateConfig) + { + uint32_t data = 0; + /* Tag latency. */ + data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | + L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | + L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) | + L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); + L2CACHEC->REG1_TAG_RAM_CONTROL = data; + /* Data latency. */ + data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | + L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | + L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) | + L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); + L2CACHEC->REG1_DATA_RAM_CONTROL = data; + } +} + +/*! + * brief Gets an available default settings for the cache controller. + * + * This function initializes the cache controller configuration structure with default settings. + * The default values are: + * code + * config->waysNum = kL2CACHE_8ways; + * config->waySize = kL2CACHE_32KbSize; + * config->repacePolicy = kL2CACHE_Roundrobin; + * config->lateConfig = NULL; + * config->istrPrefetchEnable = false; + * config->dataPrefetchEnable = false; + * config->nsLockdownEnable = false; + * config->writeAlloc = kL2CACHE_UseAwcache; + * endcode + * param config Pointer to the configuration structure. + */ +void L2CACHE_GetDefaultConfig(l2cache_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >> + L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT; + uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >> + L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT; + + /* Get the default value */ + config->wayNum = (l2cache_way_num_t)number; + config->waySize = (l2cache_way_size)size; + config->repacePolicy = kL2CACHE_Roundrobin; + config->lateConfig = NULL; + config->istrPrefetchEnable = false; + config->dataPrefetchEnable = false; + config->nsLockdownEnable = false; + config->writeAlloc = kL2CACHE_UseAwcache; +} + +/*! + * brief Enables the level 2 cache controller. + * This function enables the cache controller. Must be written using a secure access. + * If write with a Non-secure access will cause a DECERR response. + * + */ +void L2CACHE_Enable(void) +{ + /* Invalidate first. */ + L2CACHE_Invalidate(); + /* Enable the level 2 cache controller. */ + L2CACHEC->REG1_CONTROL = L2CACHEC_REG1_CONTROL_CE_MASK; +} + +/*! + * brief Disables the level 2 cache controller. + * This function disables the cache controller. Must be written using a secure access. + * If write with a Non-secure access will cause a DECERR response. + * + */ +void L2CACHE_Disable(void) +{ + /* First CleanInvalidate all enties in the cache. */ + L2CACHE_CleanInvalidate(); + /* Disable the level 2 cache controller. */ + L2CACHEC->REG1_CONTROL &= ~L2CACHEC_REG1_CONTROL_CE_MASK; + /* DSB - data sync barrier.*/ + __DSB(); +} + +/*! + * brief Invalidates the Level 2 cache. + * This function invalidates all entries in cache. + * + */ +void L2CACHE_Invalidate(void) +{ + /* Invalidate all entries in cache. */ + L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_INV_WAY); + /* Cache sync. */ + L2CACHEC->REG7_CACHE_SYNC = 0; +} + +/*! + * brief Cleans the level 2 cache controller. + * This function cleans all entries in the level 2 cache controller. + * + */ +void L2CACHE_Clean(void) +{ + /* Clean all entries of the cache. */ + L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_WAY); + /* Cache sync. */ + L2CACHEC->REG7_CACHE_SYNC = 0; +} + +/*! + * brief Cleans and invalidates the level 2 cache controller. + * This function cleans and invalidates all entries in the level 2 cache controller. + * + */ +void L2CACHE_CleanInvalidate(void) +{ + /* Clean all entries of the cache. */ + L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_INV_WAY); + /* Cache sync. */ + L2CACHEC->REG7_CACHE_SYNC = 0; +} + +/*! + * brief Invalidates the Level 2 cache lines in the range of two physical addresses. + * This function invalidates all cache lines between two physical addresses. + * + * param address The start address of the memory to be invalidated. + * param size_byte The memory size. + * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t endAddr = address + size_byte; + + /* Invalidate addresses in the range. */ + while (address < endAddr) + { + address = L2CACHE_InvalidateLineByAddr(address); + /* Update the size. */ + address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE; + } + + /* Cache sync. */ + L2CACHEC->REG7_CACHE_SYNC = 0; +} + +/*! + * brief Cleans the Level 2 cache lines in the range of two physical addresses. + * This function cleans all cache lines between two physical addresses. + * + * param address The start address of the memory to be cleaned. + * param size_byte The memory size. + * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t num_ways = 0; + uint32_t size_way = 0; + uint32_t endAddr = address + size_byte; + + /* Get the number and size of the cache way. */ + L2CACHE_GetWayNumSize(&num_ways, &size_way); + + /* Check if the clean size is over the cache size. */ + if ((endAddr - address) > num_ways * size_way) + { + L2CACHE_Clean(); + return; + } + + /* Clean addresses in the range. */ + while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr) + { + /* Clean the address in the range. */ + address = L2CACHE_CleanLineByAddr(address); + address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE; + } + + L2CACHEC->REG7_CACHE_SYNC = 0; +} + +/*! + * brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses. + * This function cleans and invalidates all cache lines between two physical addresses. + * + * param address The start address of the memory to be cleaned and invalidated. + * param size_byte The memory size. + * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t num_ways = 0; + uint32_t size_way = 0; + uint32_t endAddr = address + size_byte; + + /* Get the number and size of the cache way. */ + L2CACHE_GetWayNumSize(&num_ways, &size_way); + + /* Check if the clean size is over the cache size. */ + if ((endAddr - address) > num_ways * size_way) + { + L2CACHE_CleanInvalidate(); + return; + } + + /* Clean addresses in the range. */ + while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr) + { + /* Clean the address in the range. */ + address = L2CACHE_CleanInvalidateLineByAddr(address); + address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE; + } + + L2CACHEC->REG7_CACHE_SYNC = 0; +} + +/*! + * brief Enables or disables to lock down the data and instruction by way. + * This function locks down the cached instruction/data by way and prevent the adresses from + * being allocated and prevent dara from being evicted out of the level 2 cache. + * But the normal cache maintenance operations that invalidate, clean or clean + * and validate cache contents affect the locked-down cache lines as normal. + * + * param masterId The master id, range from 0 ~ 7. + * param mask The ways to be enabled or disabled to lockdown. + * each bit in value is related to each way of the cache. for example: + * value: bit 0 ------ way 0. + * value: bit 1 ------ way 1. + * -------------------------- + * value: bit 15 ------ way 15. + * Note: please make sure the value setting is align with your supported ways. + * param enable True enable the lockdown, false to disable the lockdown. + */ +void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) +{ + uint8_t num_ways = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >> + L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT; + num_ways = (num_ways + 1) * L2CACHE_SMALLWAYS_NUM; + + assert(mask < (1U << num_ways)); + assert(masterId < L2CACHE_LOCKDOWN_REGNUM); + + uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN; + uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN; + + if (enable) + { + /* Data lockdown. */ + L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask; + /* Instruction lockdown. */ + L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask; + } + else + { + /* Data lockdown. */ + L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask; + /* Instruction lockdown. */ + L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask; + } +} +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ + +/*! + * brief Invalidate cortex-m7 L1 instruction cache by range. + * + * param address The start address of the memory to be invalidated. + * param size_byte The memory size. + * note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L1 I-cache line size if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte) +{ +#if (__DCACHE_PRESENT == 1U) + uint32_t addr = address & (uint32_t) ~(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1); + int32_t size = size_byte + address - addr; + uint32_t linesize = 32U; + + __DSB(); + while (size > 0) + { + SCB->ICIMVAU = addr; + addr += linesize; + size -= linesize; + } + __DSB(); + __ISB(); +#endif +} + +/*! + * brief Invalidates all instruction caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * param address The physical address. + * param size_byte size of the memory to be invalidated. + * note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) +{ +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT + L2CACHE_InvalidateByRange(address, size_byte); +#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ + + L1CACHE_InvalidateICacheByRange(address, size_byte); +} + +/*! + * brief Invalidates all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * param address The physical address. + * param size_byte size of the memory to be invalidated. + * note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) +{ +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT + L2CACHE_InvalidateByRange(address, size_byte); +#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ + L1CACHE_InvalidateDCacheByRange(address, size_byte); +} + +/*! + * brief Cleans all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * param address The physical address. + * param size_byte size of the memory to be cleaned. + * note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_CleanDCacheByRange(address, size_byte); +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT + L2CACHE_CleanByRange(address, size_byte); +#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ +} + +/*! + * brief Cleans and Invalidates all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * param address The physical address. + * param size_byte size of the memory to be cleaned and invalidated. + * note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_CleanInvalidateDCacheByRange(address, size_byte); +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT + L2CACHE_CleanInvalidateByRange(address, size_byte); +#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_cache.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_cache.h new file mode 100644 index 0000000000..17e30a61d2 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_cache.h @@ -0,0 +1,467 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_CACHE_H_ +#define _FSL_CACHE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cache + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief cache driver version 2.0.1. */ +#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +#ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT +#define FSL_SDK_DISBLE_L2CACHE_PRESENT 0 +#endif +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT + +/*! @brief Number of level 2 cache controller ways. */ +typedef enum _l2cache_way_num +{ + kL2CACHE_8ways = 0, /*!< 8 ways. */ +#if defined(FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY) && FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY + kL2CACHE_16ways /*!< 16 ways. */ +#endif /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */ +} l2cache_way_num_t; + +/*! @brief Level 2 cache controller way size. */ +typedef enum _l2cache_way_size +{ + kL2CACHE_16KBSize = 1, /*!< 16 KB way size. */ + kL2CACHE_32KBSize = 2, /*!< 32 KB way size. */ + kL2CACHE_64KBSize = 3, /*!< 64 KB way size. */ + kL2CACHE_128KBSize = 4, /*!< 128 KB way size. */ + kL2CACHE_256KBSize = 5, /*!< 256 KB way size. */ + kL2CACHE_512KBSize = 6 /*!< 512 KB way size. */ +} l2cache_way_size; + +/*! @brief Level 2 cache controller replacement policy. */ +typedef enum _l2cache_replacement +{ + kL2CACHE_Pseudorandom = 0U, /*!< Peseudo-random replacement policy using an lfsr. */ + kL2CACHE_Roundrobin /*!< Round-robin replacemnt policy. */ +} l2cache_replacement_t; + +/*! @brief Level 2 cache controller force write allocate options. */ +typedef enum _l2cache_writealloc +{ + kL2CACHE_UseAwcache = 0, /*!< Use AWCAHE attribute for the write allocate. */ + kL2CACHE_NoWriteallocate, /*!< Force no write allocate. */ + kL2CACHE_forceWriteallocate /*!< Force write allocate when write misses. */ +} l2cache_writealloc_t; + +/*! @brief Level 2 cache controller tag/data ram latency. */ +typedef enum _l2cache_latency +{ + kL2CACHE_1CycleLate = 0, /*!< 1 cycle of latency. */ + kL2CACHE_2CycleLate, /*!< 2 cycle of latency. */ + kL2CACHE_3CycleLate, /*!< 3 cycle of latency. */ + kL2CACHE_4CycleLate, /*!< 4 cycle of latency. */ + kL2CACHE_5CycleLate, /*!< 5 cycle of latency. */ + kL2CACHE_6CycleLate, /*!< 6 cycle of latency. */ + kL2CACHE_7CycleLate, /*!< 7 cycle of latency. */ + kL2CACHE_8CycleLate /*!< 8 cycle of latency. */ +} l2cache_latency_t; + +/*! @brief Level 2 cache controller tag/data ram latency configure structure. */ +typedef struct _l2cache_latency_config +{ + l2cache_latency_t tagWriteLate; /*!< Tag write latency. */ + l2cache_latency_t tagReadLate; /*!< Tag Read latency. */ + l2cache_latency_t tagSetupLate; /*!< Tag setup latency. */ + l2cache_latency_t dataWriteLate; /*!< Data write latency. */ + l2cache_latency_t dataReadLate; /*!< Data Read latency. */ + l2cache_latency_t dataSetupLate; /*!< Data setup latency. */ +} L2cache_latency_config_t; + +/*! @brief Level 2 cache controller configure structure. */ +typedef struct _l2cache_config +{ + /* ------------------------ l2 cachec basic settings ---------------------------- */ + l2cache_way_num_t wayNum; /*!< The number of ways. */ + l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */ + l2cache_replacement_t repacePolicy; /*!< Replacemnet policy. */ + /* ------------------------ tag/data ram latency settings ----------------------- */ + L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ + /* ------------------------ Prefetch enable settings ---------------------------- */ + bool istrPrefetchEnable; /*!< Instruction prefetch enable. */ + bool dataPrefetchEnable; /*!< Data prefetch enable. */ + /* ------------------------ Non-secure access settings -------------------------- */ + bool nsLockdownEnable; /*!< None-secure lockdown enable. */ + /* ------------------------ other settings -------------------------------------- */ + l2cache_writealloc_t writeAlloc; /*!< Write allcoate force option. */ +} l2cache_config_t; +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Control for cortex-m7 L1 cache + *@{ + */ + +/*! + * @brief Enables cortex-m7 L1 instruction cache. + * + */ +static inline void L1CACHE_EnableICache(void) +{ + SCB_EnableICache(); +} + +/*! + * @brief Disables cortex-m7 L1 instruction cache. + * + */ +static inline void L1CACHE_DisableICache(void) +{ + SCB_DisableICache(); +} + +/*! + * @brief Invalidate cortex-m7 L1 instruction cache. + * + */ +static inline void L1CACHE_InvalidateICache(void) +{ + SCB_InvalidateICache(); +} + +/*! + * @brief Invalidate cortex-m7 L1 instruction cache by range. + * + * @param address The start address of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L1 I-cache line size if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Enables cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_EnableDCache(void) +{ + SCB_EnableDCache(); +} + +/*! + * @brief Disables cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_DisableDCache(void) +{ + SCB_DisableDCache(); +} + +/*! + * @brief Invalidates cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_InvalidateDCache(void) +{ + SCB_InvalidateDCache(); +} + +/*! + * @brief Cleans cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_CleanDCache(void) +{ + SCB_CleanDCache(); +} + +/*! + * @brief Cleans and Invalidates cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_CleanInvalidateDCache(void) +{ + SCB_CleanInvalidateDCache(); +} + +/*! + * @brief Invalidates cortex-m7 L1 data cache by range. + * + * @param address The start address of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L1 D-cache line size if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t startAddr = address & (uint32_t) ~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); + uint32_t size = size_byte + address - startAddr; + + SCB_InvalidateDCache_by_Addr((uint32_t *)startAddr, size); +} + +/*! + * @brief Cleans cortex-m7 L1 data cache by range. + * + * @param address The start address of the memory to be cleaned. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L1 D-cache line size if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t startAddr = address & (uint32_t) ~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); + uint32_t size = size_byte + address - startAddr; + + SCB_CleanDCache_by_Addr((uint32_t *)startAddr, size); +} + +/*! + * @brief Cleans and Invalidates cortex-m7 L1 data cache by range. + * + * @param address The start address of the memory to be clean and invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L1 D-cache line size if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t startAddr = address & (uint32_t) ~(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE - 1); + uint32_t size = size_byte + address - startAddr; + + SCB_CleanInvalidateDCache_by_Addr((uint32_t *)startAddr, size); +} +/*@}*/ + +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +/*! + * @name Control for L2 pl310 cache + *@{ + */ + +/*! + * @brief Initializes the level 2 cache controller module. + * + * @param config Pointer to configuration structure. See "l2cache_config_t". + */ +void L2CACHE_Init(l2cache_config_t *config); + +/*! + * @brief Gets an available default settings for the cache controller. + * + * This function initializes the cache controller configuration structure with default settings. + * The default values are: + * @code + * config->waysNum = kL2CACHE_8ways; + * config->waySize = kL2CACHE_32KbSize; + * config->repacePolicy = kL2CACHE_Roundrobin; + * config->lateConfig = NULL; + * config->istrPrefetchEnable = false; + * config->dataPrefetchEnable = false; + * config->nsLockdownEnable = false; + * config->writeAlloc = kL2CACHE_UseAwcache; + * @endcode + * @param config Pointer to the configuration structure. + */ +void L2CACHE_GetDefaultConfig(l2cache_config_t *config); + +/*! + * @brief Enables the level 2 cache controller. + * This function enables the cache controller. Must be written using a secure access. + * If write with a Non-secure access will cause a DECERR response. + * + */ +void L2CACHE_Enable(void); + +/*! + * @brief Disables the level 2 cache controller. + * This function disables the cache controller. Must be written using a secure access. + * If write with a Non-secure access will cause a DECERR response. + * + */ +void L2CACHE_Disable(void); + +/*! + * @brief Invalidates the Level 2 cache. + * This function invalidates all entries in cache. + * + */ +void L2CACHE_Invalidate(void); + +/*! + * @brief Invalidates the Level 2 cache lines in the range of two physical addresses. + * This function invalidates all cache lines between two physical addresses. + * + * @param address The start address of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans the level 2 cache controller. + * This function cleans all entries in the level 2 cache controller. + * + */ +void L2CACHE_Clean(void); + +/*! + * @brief Cleans the Level 2 cache lines in the range of two physical addresses. + * This function cleans all cache lines between two physical addresses. + * + * @param address The start address of the memory to be cleaned. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans and invalidates the level 2 cache controller. + * This function cleans and invalidates all entries in the level 2 cache controller. + * + */ +void L2CACHE_CleanInvalidate(void); + +/*! + * @brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses. + * This function cleans and invalidates all cache lines between two physical addresses. + * + * @param address The start address of the memory to be cleaned and invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Enables or disables to lock down the data and instruction by way. + * This function locks down the cached instruction/data by way and prevent the adresses from + * being allocated and prevent dara from being evicted out of the level 2 cache. + * But the normal cache maintenance operations that invalidate, clean or clean + * and validate cache contents affect the locked-down cache lines as normal. + * + * @param masterId The master id, range from 0 ~ 7. + * @param mask The ways to be enabled or disabled to lockdown. + * each bit in value is related to each way of the cache. for example: + * value: bit 0 ------ way 0. + * value: bit 1 ------ way 1. + * -------------------------- + * value: bit 15 ------ way 15. + * Note: please make sure the value setting is align with your supported ways. + * @param enable True enable the lockdown, false to disable the lockdown. + */ +void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable); + +/*@}*/ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ + +/*! + * @name Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310) + * Mainly used for many drivers for easy cache operation. + *@{ + */ + +/*! + * @brief Invalidates all instruction caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be invalidated. + * @note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Invalidates all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be invalidated. + * @note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be cleaned. + * @note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans and Invalidates all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be cleaned and invalidated. + * @note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CACHE_H_*/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_clock.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_clock.c new file mode 100644 index 0000000000..e7ab392f0c --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_clock.c @@ -0,0 +1,1276 @@ +/* + * Copyright 2018 - 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_clock.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to +achieve better performance, it is depend on the IDE Floating point settings, if double precision is selected +in IDE, clock_64b_t will switch to double type automatically. only support IAR and MDK here */ +#if __FPU_USED + +#if ((defined(__ICCARM__)) || (defined(__GNUC__))) + +#if (__ARMVFP__ >= __ARMFPV5__) && \ + (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/ +typedef double clock_64b_t; +#else +typedef uint64_t clock_64b_t; +#endif + +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) + +#if defined __TARGET_FPU_FPV5_D16 +typedef double clock_64b_t; +#else +typedef uint64_t clock_64b_t; +#endif + +#else +typedef uint64_t clock_64b_t; +#endif + +#else +typedef uint64_t clock_64b_t; +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* External XTAL (OSC) clock frequency. */ +volatile uint32_t g_xtalFreq; +/* External RTC XTAL clock frequency. */ +volatile uint32_t g_rtcXtalFreq; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the periph clock frequency. + * + * @return Periph clock frequency in Hz. + */ +static uint32_t CLOCK_GetPeriphClkFreq(void); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t CLOCK_GetPeriphClkFreq(void) +{ + uint32_t freq; + + /* Periph_clk2_clk ---> Periph_clk */ + if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) + { + switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) + { + /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(0U): + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + break; + + /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(1U): + freq = CLOCK_GetOscFreq(); + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(2U): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(3U): + default: + freq = 0U; + break; + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U); + } + /* Pre_Periph_clk ---> Periph_clk */ + else + { + switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) + { + /* PLL2 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + + /* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + break; + + /* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0); + break; + + /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): + freq = CLOCK_GetPllFreq(kCLOCK_PllArm) / + (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U); + break; + + default: + freq = 0U; + break; + } + } + + return freq; +} + +/*! + * brief Initialize the external 24MHz clock. + * + * This function supports two modes: + * 1. Use external crystal oscillator. + * 2. Bypass the external crystal oscillator, using input source clock directly. + * + * After this function, please call ref CLOCK_SetXtal0Freq to inform clock driver + * the external clock frequency. + * + * param bypassXtalOsc Pass in true to bypass the external crystal oscillator. + * note This device does not support bypass external crystal oscillator, so + * the input parameter should always be false. + */ +void CLOCK_InitExternalClk(bool bypassXtalOsc) +{ + /* This device does not support bypass XTAL OSC. */ + assert(!bypassXtalOsc); + + CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power up */ + while ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_XTALOSC_PWRUP_STAT_MASK) == 0) + { + } + CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; /* detect freq */ + while ((CCM_ANALOG->MISC0 & CCM_ANALOG_MISC0_OSC_XTALOK_MASK) == 0) + { + } + CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK; +} + +/*! + * brief Deinitialize the external 24MHz clock. + * + * This function disables the external 24MHz clock. + * + * After this function, please call ref CLOCK_SetXtal0Freq to set external clock + * frequency to 0. + */ +void CLOCK_DeinitExternalClk(void) +{ + CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power down */ +} + +/*! + * brief Switch the OSC. + * + * This function switches the OSC source for SoC. + * + * param osc OSC source to switch to. + */ +void CLOCK_SwitchOsc(clock_osc_t osc) +{ + if (osc == kCLOCK_RcOsc) + XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_SET_OSC_SEL_MASK; + else + XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK; +} + +/*! + * brief Initialize the RC oscillator 24MHz clock. + */ +void CLOCK_InitRcOsc24M(void) +{ + XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; +} + +/*! + * brief Power down the RCOSC 24M clock. + */ +void CLOCK_DeinitRcOsc24M(void) +{ + XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK; +} + +/*! + * brief Gets the AHB clock frequency. + * + * return The AHB clock frequency value in hertz. + */ +uint32_t CLOCK_GetAhbFreq(void) +{ + return CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U); +} + +/*! + * brief Gets the SEMC clock frequency. + * + * return The SEMC clock frequency value in hertz. + */ +uint32_t CLOCK_GetSemcFreq(void) +{ + uint32_t freq; + + /* SEMC alternative clock ---> SEMC Clock */ + if (CCM->CBCDR & CCM_CBCDR_SEMC_CLK_SEL_MASK) + { + /* PLL3 PFD1 ---> SEMC alternative clock ---> SEMC Clock */ + if (CCM->CBCDR & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK) + { + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); + } + /* PLL2 PFD2 ---> SEMC alternative clock ---> SEMC Clock */ + else + { + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + } + } + /* Periph_clk ---> SEMC Clock */ + else + { + freq = CLOCK_GetPeriphClkFreq(); + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_SEMC_PODF_MASK) >> CCM_CBCDR_SEMC_PODF_SHIFT) + 1U); + + return freq; +} + +/*! + * brief Gets the IPG clock frequency. + * + * return The IPG clock frequency value in hertz. + */ +uint32_t CLOCK_GetIpgFreq(void) +{ + return CLOCK_GetAhbFreq() / (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U); +} + +/*! + * brief Gets the PER clock frequency. + * + * return The PER clock frequency value in hertz. + */ +uint32_t CLOCK_GetPerClkFreq(void) +{ + uint32_t freq; + + /* Osc_clk ---> PER Clock*/ + if (CCM->CSCMR1 & CCM_CSCMR1_PERCLK_CLK_SEL_MASK) + { + freq = CLOCK_GetOscFreq(); + } + /* Periph_clk ---> AHB Clock ---> IPG Clock ---> PER Clock */ + else + { + freq = CLOCK_GetFreq(kCLOCK_IpgClk); + } + + freq /= (((CCM->CSCMR1 & CCM_CSCMR1_PERCLK_PODF_MASK) >> CCM_CSCMR1_PERCLK_PODF_SHIFT) + 1U); + + return freq; +} + +/*! + * brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * param clockName Clock names defined in clock_name_t + * return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t name) +{ + uint32_t freq; + + switch (name) + { + case kCLOCK_CpuClk: + case kCLOCK_AhbClk: + freq = CLOCK_GetAhbFreq(); + break; + + case kCLOCK_SemcClk: + freq = CLOCK_GetSemcFreq(); + break; + + case kCLOCK_IpgClk: + freq = CLOCK_GetIpgFreq(); + break; + + case kCLOCK_PerClk: + freq = CLOCK_GetPerClkFreq(); + break; + + case kCLOCK_OscClk: + freq = CLOCK_GetOscFreq(); + break; + case kCLOCK_RtcClk: + freq = CLOCK_GetRtcFreq(); + break; + case kCLOCK_ArmPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllArm); + break; + case kCLOCK_Usb1PllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + break; + case kCLOCK_Usb1PllPfd0Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd0); + break; + case kCLOCK_Usb1PllPfd1Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1); + break; + case kCLOCK_Usb1PllPfd2Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd2); + break; + case kCLOCK_Usb1PllPfd3Clk: + freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd3); + break; + case kCLOCK_Usb2PllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllUsb2); + break; + case kCLOCK_SysPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + break; + case kCLOCK_SysPllPfd0Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0); + break; + case kCLOCK_SysPllPfd1Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd1); + break; + case kCLOCK_SysPllPfd2Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2); + break; + case kCLOCK_SysPllPfd3Clk: + freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd3); + break; + case kCLOCK_EnetPll0Clk: + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet); + break; + case kCLOCK_EnetPll1Clk: + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet2); + break; + case kCLOCK_EnetPll2Clk: + freq = CLOCK_GetPllFreq(kCLOCK_PllEnet25M); + break; + case kCLOCK_AudioPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllAudio); + break; + case kCLOCK_VideoPllClk: + freq = CLOCK_GetPllFreq(kCLOCK_PllVideo); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/*! brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. + * param freq USB HS does not care about the clock source, so this parameter is ignored. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq) +{ + CCM->CCGR6 |= CCM_CCGR6_CG0_MASK; + USB1->USBCMD |= USBHS_USBCMD_RST_MASK; + for (volatile uint32_t i = 0; i < 400000; + i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ + { + __ASM("nop"); + } + PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | + (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); + return true; +} + +/*! brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. + * param freq USB HS does not care about the clock source, so this parameter is ignored. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq) +{ + CCM->CCGR6 |= CCM_CCGR6_CG0_MASK; + USB2->USBCMD |= USBHS_USBCMD_RST_MASK; + for (volatile uint32_t i = 0; i < 400000; + i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/ + { + __ASM("nop"); + } + PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | + (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK); + return true; +} + +/*! brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * param src USB HS PHY PLL clock source. + * param freq The frequency specified by src. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + if (CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK) + { + CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + } + else + { + CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll); + } + USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ + USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; + + USBPHY1->PWD = 0; + USBPHY1->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | + USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK; + return true; +} + +/*! brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs0PhyPllClock(void) +{ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; + USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} + +/*! + * brief Initialize the ARM PLL. + * + * This function initialize the ARM PLL with specific settings + * + * param config configuration to set to PLL. + */ +void CLOCK_InitArmPll(const clock_arm_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_ARM = (CCM_ANALOG->PLL_ARM & (~CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_ARM_BYPASS_MASK | CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_ARM = + (CCM_ANALOG->PLL_ARM & (~(CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK | CCM_ANALOG_PLL_ARM_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_ARM_ENABLE_MASK | CCM_ANALOG_PLL_ARM_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_ARM &= ~CCM_ANALOG_PLL_ARM_BYPASS_MASK; +} + +/*! + * brief De-initialize the ARM PLL. + */ +void CLOCK_DeinitArmPll(void) +{ + CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_POWERDOWN_MASK; +} + +/*! + * brief Initialize the System PLL. + * + * This function initializes the System PLL with specific settings + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitSysPll(const clock_sys_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_SYS = (CCM_ANALOG->PLL_SYS & (~CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_SYS_BYPASS_MASK | CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_SYS = + (CCM_ANALOG->PLL_SYS & (~(CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider); + + /* Initialize the fractional mode */ + CCM_ANALOG->PLL_SYS_NUM = CCM_ANALOG_PLL_SYS_NUM_A(config->numerator); + CCM_ANALOG->PLL_SYS_DENOM = CCM_ANALOG_PLL_SYS_DENOM_B(config->denominator); + + /* Initialize the spread spectrum mode */ + CCM_ANALOG->PLL_SYS_SS = CCM_ANALOG_PLL_SYS_SS_STEP(config->ss_step) | + CCM_ANALOG_PLL_SYS_SS_ENABLE(config->ss_enable) | + CCM_ANALOG_PLL_SYS_SS_STOP(config->ss_stop); + + while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_BYPASS_MASK; +} + +/*! + * brief De-initialize the System PLL. + */ +void CLOCK_DeinitSysPll(void) +{ + CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_POWERDOWN_MASK; +} + +/*! + * brief Initialize the USB1 PLL. + * + * This function initializes the USB1 PLL with specific settings + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_USB1_BYPASS_MASK | CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)) | + CCM_ANALOG_PLL_USB1_ENABLE_MASK | CCM_ANALOG_PLL_USB1_POWER_MASK | + CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK; +} + +/*! + * brief Deinitialize the USB1 PLL. + */ +void CLOCK_DeinitUsb1Pll(void) +{ + CCM_ANALOG->PLL_USB1 = 0U; +} + +/*! + * brief Initialize the USB2 PLL. + * + * This function initializes the USB2 PLL with specific settings + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config) +{ + /* Bypass PLL first */ + CCM_ANALOG->PLL_USB2 = (CCM_ANALOG->PLL_USB2 & (~CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_USB2_BYPASS_MASK | CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_USB2 = (CCM_ANALOG->PLL_USB2 & (~CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)) | + CCM_ANALOG_PLL_USB2_ENABLE_MASK | CCM_ANALOG_PLL_USB2_POWER_MASK | + CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB2_DIV_SELECT(config->loopDivider); + + while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_BYPASS_MASK; +} + +/*! + * brief Deinitialize the USB2 PLL. + */ +void CLOCK_DeinitUsb2Pll(void) +{ + CCM_ANALOG->PLL_USB2 = 0U; +} + +/*! + * brief Initializes the Audio PLL. + * + * This function initializes the Audio PLL with specific settings + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config) +{ + uint32_t pllAudio; + uint32_t misc2 = 0; + + /* Bypass PLL first */ + CCM_ANALOG->PLL_AUDIO = (CCM_ANALOG->PLL_AUDIO & (~CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_AUDIO_BYPASS_MASK | CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_AUDIO_NUM = CCM_ANALOG_PLL_AUDIO_NUM_A(config->numerator); + CCM_ANALOG->PLL_AUDIO_DENOM = CCM_ANALOG_PLL_AUDIO_DENOM_B(config->denominator); + + /* + * Set post divider: + * + * ------------------------------------------------------------------------ + * | config->postDivider | PLL_AUDIO[POST_DIV_SELECT] | MISC2[AUDIO_DIV] | + * ------------------------------------------------------------------------ + * | 1 | 2 | 0 | + * ------------------------------------------------------------------------ + * | 2 | 1 | 0 | + * ------------------------------------------------------------------------ + * | 4 | 2 | 3 | + * ------------------------------------------------------------------------ + * | 8 | 1 | 3 | + * ------------------------------------------------------------------------ + * | 16 | 0 | 3 | + * ------------------------------------------------------------------------ + */ + pllAudio = + (CCM_ANALOG->PLL_AUDIO & (~(CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK | CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_AUDIO_ENABLE_MASK | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(config->loopDivider); + + switch (config->postDivider) + { + case 16: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 8: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 4: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2); + misc2 = CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + break; + + case 2: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1); + break; + + default: + pllAudio |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(2); + break; + } + + CCM_ANALOG->MISC2 = + (CCM_ANALOG->MISC2 & ~(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)) | misc2; + + CCM_ANALOG->PLL_AUDIO = pllAudio; + + while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_AUDIO &= ~CCM_ANALOG_PLL_AUDIO_BYPASS_MASK; +} + +/*! + * brief De-initialize the Audio PLL. + */ +void CLOCK_DeinitAudioPll(void) +{ + CCM_ANALOG->PLL_AUDIO = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK; +} + +/*! + * brief Initialize the video PLL. + * + * This function configures the Video PLL with specific settings + * + * param config configuration to set to PLL. + */ +void CLOCK_InitVideoPll(const clock_video_pll_config_t *config) +{ + uint32_t pllVideo; + uint32_t misc2 = 0; + + /* Bypass PLL first */ + CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(config->src); + + CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(config->numerator); + CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(config->denominator); + + /* + * Set post divider: + * + * ------------------------------------------------------------------------ + * | config->postDivider | PLL_VIDEO[POST_DIV_SELECT] | MISC2[VIDEO_DIV] | + * ------------------------------------------------------------------------ + * | 1 | 2 | 0 | + * ------------------------------------------------------------------------ + * | 2 | 1 | 0 | + * ------------------------------------------------------------------------ + * | 4 | 2 | 3 | + * ------------------------------------------------------------------------ + * | 8 | 1 | 3 | + * ------------------------------------------------------------------------ + * | 16 | 0 | 3 | + * ------------------------------------------------------------------------ + */ + pllVideo = + (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) | + CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(config->loopDivider); + + switch (config->postDivider) + { + case 16: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(0); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 8: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 4: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2); + misc2 = CCM_ANALOG_MISC2_VIDEO_DIV(3); + break; + + case 2: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1); + break; + + default: + pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(2); + break; + } + + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & ~CCM_ANALOG_MISC2_VIDEO_DIV_MASK) | misc2; + + CCM_ANALOG->PLL_VIDEO = pllVideo; + + while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; +} + +/*! + * brief De-initialize the Video PLL. + */ +void CLOCK_DeinitVideoPll(void) +{ + CCM_ANALOG->PLL_VIDEO = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK; +} + +/*! + * brief Initialize the ENET PLL. + * + * This function initializes the ENET PLL with specific settings. + * + * param config Configuration to set to PLL. + */ +void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config) +{ + uint32_t enet_pll = CCM_ANALOG_PLL_ENET_DIV_SELECT(config->loopDivider) | + CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(config->loopDivider1); + + CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)) | + CCM_ANALOG_PLL_ENET_BYPASS_MASK | CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(config->src); + + if (config->enableClkOutput) + { + enet_pll |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + } + + if (config->enableClkOutput1) + { + enet_pll |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; + } + + if (config->enableClkOutput25M) + { + enet_pll |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + } + + CCM_ANALOG->PLL_ENET = + (CCM_ANALOG->PLL_ENET & (~(CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK | + CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) | + enet_pll; + + /* Wait for stable */ + while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0) + { + } + + /* Disable Bypass */ + CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_BYPASS_MASK; +} + +/*! + * brief Deinitialize the ENET PLL. + * + * This function disables the ENET PLL. + */ +void CLOCK_DeinitEnetPll(void) +{ + CCM_ANALOG->PLL_ENET = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK; +} + +/*! + * brief Get current PLL output frequency. + * + * This function get current output frequency of specific PLL + * + * param pll pll name to get frequency. + * return The PLL output frequency in hertz. + */ +uint32_t CLOCK_GetPllFreq(clock_pll_t pll) +{ + uint32_t freq; + uint32_t divSelect; + clock_64b_t freqTmp; + + const uint32_t enetRefClkFreq[] = { + 25000000U, /* 25M */ + 50000000U, /* 50M */ + 100000000U, /* 100M */ + 125000000U /* 125M */ + }; + + /* check if PLL is enabled */ + if (!CLOCK_IsPllEnabled(CCM_ANALOG, pll)) + { + return 0U; + } + + /* get pll reference clock */ + freq = CLOCK_GetPllBypassRefClk(CCM_ANALOG, pll); + + /* check if pll is bypassed */ + if (CLOCK_IsPllBypassed(CCM_ANALOG, pll)) + { + return freq; + } + + switch (pll) + { + case kCLOCK_PllArm: + freq = ((freq * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> + 1U); + break; + case kCLOCK_PllSys: + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_SYS_NUM))) / + ((clock_64b_t)(CCM_ANALOG->PLL_SYS_DENOM)); + + if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) + { + freq *= 22U; + } + else + { + freq *= 20U; + } + + freq += (uint32_t)freqTmp; + break; + + case kCLOCK_PllUsb1: + freq = (freq * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); + break; + + case kCLOCK_PllAudio: + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + divSelect = + (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT; + + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / + ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_DENOM)); + + freq = freq * divSelect + (uint32_t)freqTmp; + + /* AUDIO PLL output = PLL output frequency / POSTDIV. */ + + /* + * Post divider: + * + * PLL_AUDIO[POST_DIV_SELECT]: + * 0x00: 4 + * 0x01: 2 + * 0x02: 1 + * + * MISC2[AUDO_DIV]: + * 0x00: 1 + * 0x01: 2 + * 0x02: 1 + * 0x03: 4 + */ + switch (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK) + { + case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(0U): + freq = freq >> 2U; + break; + + case CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(1U): + freq = freq >> 1U; + break; + + default: + break; + } + + switch (CCM_ANALOG->MISC2 & (CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)) + { + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(1) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1): + freq >>= 2U; + break; + + case CCM_ANALOG_MISC2_AUDIO_DIV_MSB(0) | CCM_ANALOG_MISC2_AUDIO_DIV_LSB(1): + freq >>= 1U; + break; + + default: + break; + } + break; + + case kCLOCK_PllVideo: + /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ + divSelect = + (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT; + + freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / + ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_DENOM)); + + freq = freq * divSelect + (uint32_t)freqTmp; + + /* VIDEO PLL output = PLL output frequency / POSTDIV. */ + + /* + * Post divider: + * + * PLL_VIDEO[POST_DIV_SELECT]: + * 0x00: 4 + * 0x01: 2 + * 0x02: 1 + * + * MISC2[VIDEO_DIV]: + * 0x00: 1 + * 0x01: 2 + * 0x02: 1 + * 0x03: 4 + */ + switch (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK) + { + case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(0U): + freq = freq >> 2U; + break; + + case CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1U): + freq = freq >> 1U; + break; + + default: + break; + } + + switch (CCM_ANALOG->MISC2 & CCM_ANALOG_MISC2_VIDEO_DIV_MASK) + { + case CCM_ANALOG_MISC2_VIDEO_DIV(3): + freq >>= 2U; + break; + + case CCM_ANALOG_MISC2_VIDEO_DIV(1): + freq >>= 1U; + break; + + default: + break; + } + break; + case kCLOCK_PllEnet: + divSelect = + (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT; + freq = enetRefClkFreq[divSelect]; + break; + + case kCLOCK_PllEnet2: + divSelect = (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_SHIFT; + freq = enetRefClkFreq[divSelect]; + break; + + case kCLOCK_PllEnet25M: + /* ref_enetpll1 if fixed at 25MHz. */ + freq = 25000000UL; + break; + + case kCLOCK_PllUsb2: + freq = (freq * ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) ? 22U : 20U)); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/*! + * brief Initialize the System PLL PFD. + * + * This function initializes the System PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * param pfd Which PFD clock to enable. + * param pfdFrac The PFD FRAC value. + * note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac) +{ + uint32_t pfdIndex = (uint32_t)pfd; + uint32_t pfd528; + + pfd528 = CCM_ANALOG->PFD_528 & + ~((CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) << (8 * pfdIndex)); + + /* Disable the clock output first. */ + CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfdIndex)); + + /* Set the new value and enable output. */ + CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_FRAC(pfdFrac) << (8 * pfdIndex)); +} + +/*! + * brief De-initialize the System PLL PFD. + * + * This function disables the System PLL PFD. + * + * param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitSysPfd(clock_pfd_t pfd) +{ + CCM_ANALOG->PFD_528 |= CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfd); +} + +/*! + * brief Initialize the USB1 PLL PFD. + * + * This function initializes the USB1 PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * param pfd Which PFD clock to enable. + * param pfdFrac The PFD FRAC value. + * note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac) +{ + uint32_t pfdIndex = (uint32_t)pfd; + uint32_t pfd480; + + pfd480 = CCM_ANALOG->PFD_480 & + ~((CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) << (8 * pfdIndex)); + + /* Disable the clock output first. */ + CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfdIndex)); + + /* Set the new value and enable output. */ + CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_FRAC(pfdFrac) << (8 * pfdIndex)); +} + +/*! + * brief De-initialize the USB1 PLL PFD. + * + * This function disables the USB1 PLL PFD. + * + * param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd) +{ + CCM_ANALOG->PFD_480 |= CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfd); +} + +/*! + * brief Get current System PLL PFD output frequency. + * + * This function get current output frequency of specific System PLL PFD + * + * param pfd pfd name to get frequency. + * return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd) +{ + uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllSys); + + switch (pfd) + { + case kCLOCK_Pfd0: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT); + break; + + case kCLOCK_Pfd1: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT); + break; + + case kCLOCK_Pfd2: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT); + break; + + case kCLOCK_Pfd3: + freq /= ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT); + break; + + default: + freq = 0U; + break; + } + freq *= 18U; + + return freq; +} + +/*! + * brief Get current USB1 PLL PFD output frequency. + * + * This function get current output frequency of specific USB1 PLL PFD + * + * param pfd pfd name to get frequency. + * return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd) +{ + uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1); + + switch (pfd) + { + case kCLOCK_Pfd0: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT); + break; + + case kCLOCK_Pfd1: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT); + break; + + case kCLOCK_Pfd2: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT); + break; + + case kCLOCK_Pfd3: + freq /= ((CCM_ANALOG->PFD_480 & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK) >> CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT); + break; + + default: + freq = 0U; + break; + } + freq *= 18U; + + return freq; +} + +/*! brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * param src USB HS PHY PLL clock source. + * param freq The frequency specified by src. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U}; + CLOCK_InitUsb2Pll(&g_ccmConfigUsbPll); + USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ + USBPHY2->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; + + USBPHY2->PWD = 0; + USBPHY2->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | + USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK; + + return true; +} + +/*! brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void) +{ + CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK; + USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} + +/*! + * brief Use DWT to delay at least for some time. + * Please note that, this API will calculate the microsecond period with the maximum devices + * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise + * delay count was needed, please implement a new timer count to achieve this function. + * + * param delay_us Delay time in unit of microsecond. + */ +__attribute__((weak)) void SDK_DelayAtLeastUs(uint32_t delay_us) +{ + assert(0U != delay_us); + uint64_t count = 0U; + uint32_t period = SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY / 1000000; + + /* Make sure the DWT trace fucntion is enabled. */ + if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) + { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } + + /* CYCCNT not supported on this device. */ + assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); + + /* If CYCCENT has already been enabled, read directly, otherwise, need enable it. */ + if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) + { + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; + } + + /* Calculate the count ticks. */ + count = DWT->CYCCNT; + count += (uint64_t)period * delay_us; + + if (count > 0xFFFFFFFFUL) + { + count -= 0xFFFFFFFFUL; + /* wait for cyccnt overflow. */ + while (count < DWT->CYCCNT) + { + } + } + + /* Wait for cyccnt reach count value. */ + while (count > DWT->CYCCNT) + { + } +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_clock.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_clock.h new file mode 100644 index 0000000000..e0ca44ce54 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_clock.h @@ -0,0 +1,1580 @@ +/* + * Copyright 2018 - 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Configurations + ******************************************************************************/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.2.0. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL) +#endif + +/* analog pll definition */ +#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U) +#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U) + +/*@}*/ + +/*! + * @brief CCM registers offset. + */ +#define CCSR_OFFSET 0x0C +#define CBCDR_OFFSET 0x14 +#define CBCMR_OFFSET 0x18 +#define CSCMR1_OFFSET 0x1C +#define CSCMR2_OFFSET 0x20 +#define CSCDR1_OFFSET 0x24 +#define CDCDR_OFFSET 0x30 +#define CSCDR2_OFFSET 0x38 +#define CSCDR3_OFFSET 0x3C +#define CACRR_OFFSET 0x10 +#define CS1CDR_OFFSET 0x28 +#define CS2CDR_OFFSET 0x2C + +/*! + * @brief CCM Analog registers offset. + */ +#define PLL_ARM_OFFSET 0x00 +#define PLL_SYS_OFFSET 0x30 +#define PLL_USB1_OFFSET 0x10 +#define PLL_AUDIO_OFFSET 0x70 +#define PLL_VIDEO_OFFSET 0xA0 +#define PLL_ENET_OFFSET 0xE0 +#define PLL_USB2_OFFSET 0x20 + +#define CCM_TUPLE(reg, shift, mask, busyShift) \ + (int)((reg & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U)) +#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU)))) +#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU) +#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU)))) +#define CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU) + +#define CCM_NO_BUSY_WAIT (0x20U) + +/*! + * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields. + */ +#define CCM_ANALOG_TUPLE(reg, shift) (((reg & 0xFFFU) << 16U) | (shift)) +#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU) +#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \ + (*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off))) +#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U) + +/*! + * @brief clock1PN frequency. + */ +#define CLKPN_FREQ 0U + +/*! @brief External XTAL (24M OSC/SYSOSC) clock frequency. + * + * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetXtalFreq to set the value in to clock driver. For example, + * if XTAL is 24MHz, + * @code + * CLOCK_InitExternalClk(false); // Setup the 24M OSC/SYSOSC + * CLOCK_SetXtalFreq(240000000); // Set the XTAL value to clock driver. + * @endcode + */ +extern volatile uint32_t g_xtalFreq; + +/*! @brief External RTC XTAL (32K OSC) clock frequency. + * + * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the + * function CLOCK_SetRtcXtalFreq to set the value in to clock driver. + */ +extern volatile uint32_t g_rtcXtalFreq; + +/* For compatible with other platforms */ +#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq +#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq + +/*! @brief Clock ip name array for ADC. */ +#define ADC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \ + } + +/*! @brief Clock ip name array for AOI. */ +#define AOI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \ + } + +/*! @brief Clock ip name array for BEE. */ +#define BEE_CLOCKS \ + { \ + kCLOCK_Bee \ + } + +/*! @brief Clock ip name array for CMP. */ +#define CMP_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \ + } + +/*! @brief Clock ip name array for CSI. */ +#define CSI_CLOCKS \ + { \ + kCLOCK_Csi \ + } + +/*! @brief Clock ip name array for DCDC. */ +#define DCDC_CLOCKS \ + { \ + kCLOCK_Dcdc \ + } + +/*! @brief Clock ip name array for DCP. */ +#define DCP_CLOCKS \ + { \ + kCLOCK_Dcp \ + } + +/*! @brief Clock ip name array for DMAMUX_CLOCKS. */ +#define DMAMUX_CLOCKS \ + { \ + kCLOCK_Dma \ + } + +/*! @brief Clock ip name array for DMA. */ +#define EDMA_CLOCKS \ + { \ + kCLOCK_Dma \ + } + +/*! @brief Clock ip name array for ENC. */ +#define ENC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \ + } + +/*! @brief Clock ip name array for ENET. */ +#define ENET_CLOCKS \ + { \ + kCLOCK_Enet, kCLOCK_IpInvalid, kCLOCK_Enet2 \ + } + +/*! @brief Clock ip name array for EWM. */ +#define EWM_CLOCKS \ + { \ + kCLOCK_Ewm0 \ + } + +/*! @brief Clock ip name array for FLEXCAN. */ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, kCLOCK_Can3 \ + } + +/*! @brief Clock ip name array for FLEXCAN Peripheral clock. */ +#define FLEXCAN_PERIPH_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S, kCLOCK_Can3S \ + } + +/*! @brief Clock ip name array for FLEXIO. */ +#define FLEXIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2, kCLOCK_Flexio3 \ + } + +/*! @brief Clock ip name array for FLEXRAM. */ +#define FLEXRAM_CLOCKS \ + { \ + kCLOCK_FlexRam \ + } + +/*! @brief Clock ip name array for FLEXSPI. */ +#define FLEXSPI_CLOCKS \ + { \ + kCLOCK_FlexSpi, kCLOCK_IpInvalid, kCLOCK_FlexSpi2 \ + } + +/*! @brief Clock ip name array for FLEXSPI EXSC. */ +#define FLEXSPI_EXSC_CLOCKS \ + { \ + kCLOCK_FlexSpiExsc \ + } + +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ + } + +/*! @brief Clock ip name array for GPT. */ +#define GPT_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \ + } + +/*! @brief Clock ip name array for KPP. */ +#define KPP_CLOCKS \ + { \ + kCLOCK_Kpp \ + } + +/*! @brief Clock ip name array for LCDIF. */ +#define LCDIF_CLOCKS \ + { \ + kCLOCK_Lcd \ + } + +/*! @brief Clock ip name array for LCDIF PIXEL. */ +#define LCDIF_PERIPH_CLOCKS \ + { \ + kCLOCK_LcdPixel \ + } + +/*! @brief Clock ip name array for LPI2C. */ +#define LPI2C_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \ + } + +/*! @brief Clock ip name array for LPSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \ + } + +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \ + kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \ + } + +/*! @brief Clock ip name array for MQS. */ +#define MQS_CLOCKS \ + { \ + kCLOCK_Mqs \ + } + +/*! @brief Clock ip name array for OCRAM EXSC. */ +#define OCRAM_EXSC_CLOCKS \ + { \ + kCLOCK_OcramExsc \ + } + +/*! @brief Clock ip name array for PIT. */ +#define PIT_CLOCKS \ + { \ + kCLOCK_Pit \ + } + +/*! @brief Clock ip name array for PWM. */ +#define PWM_CLOCKS \ + { \ + {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \ + {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, \ + {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \ + {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \ + { \ + kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \ + } \ + } + +/*! @brief Clock ip name array for PXP. */ +#define PXP_CLOCKS \ + { \ + kCLOCK_Pxp \ + } + +/*! @brief Clock ip name array for RTWDOG. */ +#define RTWDOG_CLOCKS \ + { \ + kCLOCK_Wdog3 \ + } + +/*! @brief Clock ip name array for SAI. */ +#define SAI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \ + } + +/*! @brief Clock ip name array for SEMC. */ +#define SEMC_CLOCKS \ + { \ + kCLOCK_Semc \ + } + +/*! @brief Clock ip name array for SEMC EXSC. */ +#define SEMC_EXSC_CLOCKS \ + { \ + kCLOCK_SemcExsc \ + } + +/*! @brief Clock ip name array for QTIMER. */ +#define TMR_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ + } + +/*! @brief Clock ip name array for TRNG. */ +#define TRNG_CLOCKS \ + { \ + kCLOCK_Trng \ + } + +/*! @brief Clock ip name array for TSC. */ +#define TSC_CLOCKS \ + { \ + kCLOCK_Tsc \ + } + +/*! @brief Clock ip name array for WDOG. */ +#define WDOG_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \ + } + +/*! @brief Clock ip name array for USDHC. */ +#define USDHC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \ + } + +/*! @brief Clock ip name array for SPDIF. */ +#define SPDIF_CLOCKS \ + { \ + kCLOCK_Spdif \ + } + +/*! @brief Clock ip name array for XBARA. */ +#define XBARA_CLOCKS \ + { \ + kCLOCK_Xbar1 \ + } + +/*! @brief Clock ip name array for XBARB. */ +#define XBARB_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \ + } + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CpuClk = 0x0U, /*!< CPU clock */ + kCLOCK_AhbClk = 0x1U, /*!< AHB clock */ + kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */ + kCLOCK_IpgClk = 0x3U, /*!< IPG clock */ + kCLOCK_PerClk = 0x4U, /*!< PER clock */ + + kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */ + kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */ + + kCLOCK_ArmPllClk = 0x7U, /*!< ARMPLLCLK. */ + + kCLOCK_Usb1PllClk = 0x8U, /*!< USB1PLLCLK. */ + kCLOCK_Usb1PllPfd0Clk = 0x9U, /*!< USB1PLLPDF0CLK. */ + kCLOCK_Usb1PllPfd1Clk = 0xAU, /*!< USB1PLLPFD1CLK. */ + kCLOCK_Usb1PllPfd2Clk = 0xBU, /*!< USB1PLLPFD2CLK. */ + kCLOCK_Usb1PllPfd3Clk = 0xCU, /*!< USB1PLLPFD3CLK. */ + + kCLOCK_Usb2PllClk = 0xDU, /*!< USB2PLLCLK. */ + + kCLOCK_SysPllClk = 0xEU, /*!< SYSPLLCLK. */ + kCLOCK_SysPllPfd0Clk = 0xFU, /*!< SYSPLLPDF0CLK. */ + kCLOCK_SysPllPfd1Clk = 0x10U, /*!< SYSPLLPFD1CLK. */ + kCLOCK_SysPllPfd2Clk = 0x11U, /*!< SYSPLLPFD2CLK. */ + kCLOCK_SysPllPfd3Clk = 0x12U, /*!< SYSPLLPFD3CLK. */ + + kCLOCK_EnetPll0Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll0. */ + kCLOCK_EnetPll1Clk = 0x14U, /*!< Enet PLLCLK ref_enetpll1. */ + kCLOCK_EnetPll2Clk = 0x15U, /*!< Enet PLLCLK ref_enetpll2. */ + + kCLOCK_AudioPllClk = 0x16U, /*!< Audio PLLCLK. */ + kCLOCK_VideoPllClk = 0x17U, /*!< Video PLLCLK. */ +} clock_name_t; + +#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */ +#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */ + +/*! + * @brief CCM CCGR gate control for each module independently. + */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = -1, + + /* CCM CCGR0 */ + kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */ + kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */ + kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2 */ + kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3 */ + kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */ + kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */ + kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */ + kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*!< CCGR0, CG7 */ + kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*!< CCGR0, CG8 */ + kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*!< CCGR0, CG9 */ + kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10 */ + kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */ + kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */ + kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */ + kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */ + kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */ + + /* CCM CCGR1 */ + kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */ + kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */ + kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT, /*!< CCGR1, CG2 */ + kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*!< CCGR1, CG3 */ + kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*!< CCGR1, CG4 */ + kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*!< CCGR1, CG5 */ + kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */ + kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT, /*!< CCGR1, CG7 */ + kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */ + kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, /*!< CCGR1, CG9 */ + kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */ + kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */ + kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */ + kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */ + kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */ + kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */ + + /* CCM CCGR2 */ + kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */ + kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT, /*!< CCGR2, CG1 */ + kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */ + kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */ + kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */ + kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*!< CCGR2, CG5 */ + kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */ + kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT, /*!< CCGR2, CG7 */ + kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT, /*!< CCGR2, CG8 */ + kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT, /*!< CCGR2, CG9 */ + kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, /*!< CCGR2, CG10 */ + kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */ + kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */ + kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */ + kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, /*!< CCGR2, CG14 */ + kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, /*!< CCGR2, CG15 */ + + /* CCM CCGR3 */ + kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT, /*!< CCGR3, CG0 */ + kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*!< CCGR3, CG1 */ + kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*!< CCGR3, CG2 */ + kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*!< CCGR3, CG3 */ + kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */ + kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT, /*!< CCGR3, CG5 */ + kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT, /*!< CCGR3, CG6 */ + kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */ + kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */ + kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */ + kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10 */ + kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11 */ + kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12 */ + kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13 */ + kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, /*!< CCGR3, CG14 */ + kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */ + + /* CCM CCGR4 */ + kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */ + kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */ + kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */ + kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */ + kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*!< CCGR4, CG5 */ + kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */ + kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */ + kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */ + kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*!< CCGR4, CG9 */ + kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, /*!< CCGR4, CG10 */ + kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, /*!< CCGR4, CG11 */ + kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */ + kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13 */ + kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, /*!< CCGR4, CG14 */ + kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15 */ + + /* CCM CCGR5 */ + kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */ + kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */ + kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */ + kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */ + kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */ + kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */ + kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */ + kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */ + kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT, /*!< CCGR5, CG8 */ + kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */ + kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */ + kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */ + kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */ + kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13 */ + kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */ + kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */ + + /* CCM CCGR6 */ + kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */ + kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*!< CCGR6, CG1 */ + kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*!< CCGR6, CG2 */ + kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */ + kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*!< CCGR6, CG4 */ + kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */ + kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */ + kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*!< CCGR6, CG7 */ + kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*!< CCGR6, CG8 */ + kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */ + kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */ + kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */ + kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12 */ + kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */ + kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14 */ + kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15 */ + + /* CCM CCGR7 */ + kCLOCK_Enet2 = (7U << 8U) | CCM_CCGR7_CG0_SHIFT, /*!< CCGR7, CG0 */ + kCLOCK_FlexSpi2 = (7U << 8U) | CCM_CCGR7_CG1_SHIFT, /*!< CCGR7, CG1 */ + kCLOCK_Axbs_l = (7U << 8U) | CCM_CCGR7_CG2_SHIFT, /*!< CCGR7, CG2 */ + kCLOCK_Can3 = (7U << 8U) | CCM_CCGR7_CG3_SHIFT, /*!< CCGR7, CG3 */ + kCLOCK_Can3S = (7U << 8U) | CCM_CCGR7_CG4_SHIFT, /*!< CCGR7, CG4 */ + kCLOCK_Aips_lite = (7U << 8U) | CCM_CCGR7_CG5_SHIFT, /*!< CCGR7, CG5 */ + kCLOCK_Flexio3 = (7U << 8U) | CCM_CCGR7_CG6_SHIFT, /*!< CCGR7, CG6 */ + +} clock_ip_name_t; + +/*! @brief OSC 24M sorce select */ +typedef enum _clock_osc +{ + kCLOCK_RcOsc = 0U, /*!< On chip OSC. */ + kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */ +} clock_osc_t; + +/*! @brief Clock gate value */ +typedef enum _clock_gate_value +{ + kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */ + kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */ + kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */ +} clock_gate_value_t; + +/*! @brief System clock mode */ +typedef enum _clock_mode_t +{ + kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */ + kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */ + kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */ +} clock_mode_t; + +/*! + * @brief MUX control names for clock mux setting. + * + * These constants define the mux control names for clock mux setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +typedef enum _clock_mux +{ + kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET, + CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT, + CCM_CCSR_PLL3_SW_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */ + + kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_PERIPH_CLK_SEL_SHIFT, + CCM_CBCDR_PERIPH_CLK_SEL_MASK, + CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */ + kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT, + CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< semc mux name */ + kCLOCK_SemcMux = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_SEMC_CLK_SEL_SHIFT, + CCM_CBCDR_SEMC_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< semc mux name */ + + kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT, + CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */ + kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_TRACE_CLK_SEL_SHIFT, + CCM_CBCMR_TRACE_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< trace mux name */ + kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT, + CCM_CBCMR_PERIPH_CLK2_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */ + kCLOCK_Flexspi2Mux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT, + CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexspi2 mux name */ + kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_LPSPI_CLK_SEL_SHIFT, + CCM_CBCMR_LPSPI_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< lpspi mux name */ + + kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT, + CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexspi mux name */ + kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT, + CCM_CSCMR1_USDHC2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */ + kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT, + CCM_CSCMR1_USDHC1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */ + kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_SAI3_CLK_SEL_SHIFT, + CCM_CSCMR1_SAI3_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 mux name */ + kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_SAI2_CLK_SEL_SHIFT, + CCM_CSCMR1_SAI2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< sai2 mux name */ + kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_SAI1_CLK_SEL_SHIFT, + CCM_CSCMR1_SAI1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< sai1 mux name */ + kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT, + CCM_CSCMR1_PERCLK_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< perclk mux name */ + + kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2_OFFSET, + CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT, + CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio2 mux name */ + kCLOCK_CanMux = CCM_TUPLE(CSCMR2_OFFSET, + CCM_CSCMR2_CAN_CLK_SEL_SHIFT, + CCM_CSCMR2_CAN_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< can mux name */ + + kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_UART_CLK_SEL_SHIFT, + CCM_CSCDR1_UART_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< uart mux name */ + + kCLOCK_SpdifMux = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT, + CCM_CDCDR_SPDIF0_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif mux name */ + kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */ + + kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2_OFFSET, + CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT, + CCM_CSCDR2_LPI2C_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */ + kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2_OFFSET, + CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT, + CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< lcdif pre mux name */ + + kCLOCK_CsiMux = CCM_TUPLE(CSCDR3_OFFSET, + CCM_CSCDR3_CSI_CLK_SEL_SHIFT, + CCM_CSCDR3_CSI_CLK_SEL_MASK, + CCM_NO_BUSY_WAIT), /*!< csi mux name */ +} clock_mux_t; + +/*! + * @brief DIV control names for clock div setting. + * + * These constants define div control names for clock div setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +typedef enum _clock_div +{ + kCLOCK_ArmDiv = CCM_TUPLE(CACRR_OFFSET, + CCM_CACRR_ARM_PODF_SHIFT, + CCM_CACRR_ARM_PODF_MASK, + CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */ + + kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT, + CCM_CBCDR_PERIPH_CLK2_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */ + kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_SEMC_PODF_SHIFT, + CCM_CBCDR_SEMC_PODF_MASK, + CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */ + kCLOCK_AhbDiv = CCM_TUPLE(CBCDR_OFFSET, + CCM_CBCDR_AHB_PODF_SHIFT, + CCM_CBCDR_AHB_PODF_MASK, + CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */ + kCLOCK_IpgDiv = CCM_TUPLE( + CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */ + + kCLOCK_Flexspi2Div = CCM_TUPLE(CBCMR_OFFSET, + CCM_CBCMR_FLEXSPI2_PODF_SHIFT, + CCM_CBCMR_FLEXSPI2_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexspi2 div name */ + kCLOCK_LpspiDiv = CCM_TUPLE( + CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */ + kCLOCK_LcdifDiv = CCM_TUPLE( + CBCMR_OFFSET, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif div name */ + + kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_FLEXSPI_PODF_SHIFT, + CCM_CSCMR1_FLEXSPI_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexspi div name */ + kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1_OFFSET, + CCM_CSCMR1_PERCLK_PODF_SHIFT, + CCM_CSCMR1_PERCLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< perclk div name */ + + kCLOCK_CanDiv = CCM_TUPLE(CSCMR2_OFFSET, + CCM_CSCMR2_CAN_CLK_PODF_SHIFT, + CCM_CSCMR2_CAN_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< can div name */ + + kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_TRACE_PODF_SHIFT, + CCM_CSCDR1_TRACE_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< trace div name */ + kCLOCK_Usdhc2Div = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_USDHC2_PODF_SHIFT, + CCM_CSCDR1_USDHC2_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */ + kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_USDHC1_PODF_SHIFT, + CCM_CSCDR1_USDHC1_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */ + kCLOCK_UartDiv = CCM_TUPLE(CSCDR1_OFFSET, + CCM_CSCDR1_UART_CLK_PODF_SHIFT, + CCM_CSCDR1_UART_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< uart div name */ + + kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT, + CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio2 pre div name */ + kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI3_CLK_PRED_SHIFT, + CCM_CS1CDR_SAI3_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI3_CLK_PODF_SHIFT, + CCM_CS1CDR_SAI3_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 div name */ + kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT, + CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */ + kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI1_CLK_PRED_SHIFT, + CCM_CS1CDR_SAI1_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */ + kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR_OFFSET, + CCM_CS1CDR_SAI1_CLK_PODF_SHIFT, + CCM_CS1CDR_SAI1_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< sai1 div name */ + + kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET, + CCM_CS2CDR_SAI2_CLK_PRED_SHIFT, + CCM_CS2CDR_SAI2_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */ + kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR_OFFSET, + CCM_CS2CDR_SAI2_CLK_PODF_SHIFT, + CCM_CS2CDR_SAI2_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< sai2 div name */ + + kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT, + CCM_CDCDR_SPDIF0_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif pre div name */ + kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT, + CCM_CDCDR_SPDIF0_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< spdif div name */ + kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */ + kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR_OFFSET, + CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT, + CCM_CDCDR_FLEXIO1_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< flexio1 div name */ + + kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET, + CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT, + CCM_CSCDR2_LPI2C_CLK_PODF_MASK, + CCM_NO_BUSY_WAIT), /*!< lpi2c div name */ + kCLOCK_LcdifPreDiv = CCM_TUPLE(CSCDR2_OFFSET, + CCM_CSCDR2_LCDIF_PRED_SHIFT, + CCM_CSCDR2_LCDIF_PRED_MASK, + CCM_NO_BUSY_WAIT), /*!< lcdif pre div name */ + + kCLOCK_CsiDiv = CCM_TUPLE( + CSCDR3_OFFSET, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */ +} clock_div_t; + +/*! @brief USB clock source definition. */ +typedef enum _clock_usb_src +{ + kCLOCK_Usb480M = 0, /*!< Use 480M. */ + kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not + care the clock source. */ +} clock_usb_src_t; + +/*! @brief Source of the USB HS PHY. */ +typedef enum _clock_usb_phy_src +{ + kCLOCK_Usbphy480M = 0, /*!< Use 480M. */ +} clock_usb_phy_src_t; + +/*!@brief PLL clock source, bypass cloco source also */ +enum _clock_pll_clk_src +{ + kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */ + kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */ +}; + +/*! @brief PLL configuration for ARM */ +typedef struct _clock_arm_pll_config +{ + uint32_t loopDivider; /*!< PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2. */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ +} clock_arm_pll_config_t; + +/*! @brief PLL configuration for USB */ +typedef struct _clock_usb_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_usb_pll_config_t; + +/*! @brief PLL configuration for System */ +typedef struct _clock_sys_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M). + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + uint16_t ss_stop; /*!< Stop value to get frequency change. */ + uint8_t ss_enable; /*!< Enable spread spectrum modulation */ + uint16_t ss_step; /*!< Step value to get frequency change step. */ +} clock_sys_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_audio_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ +} clock_audio_pll_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_video_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_video_pll_config_t; + +/*! @brief PLL configuration for ENET */ +typedef struct _clock_enet_pll_config +{ + bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */ + bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET2 (ref_enetpll2). */ + uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock. + b00 25MHz + b01 50MHz + b10 100MHz (not 50% duty cycle) + b11 125MHz */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + bool enableClkOutput1; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */ + uint8_t loopDivider1; /*!< Controls the frequency of the ENET1 reference clock. + b00 25MHz + b01 50MHz + b10 100MHz (not 50% duty cycle) + b11 125MHz */ +} clock_enet_pll_config_t; + +/*! @brief PLL name */ +typedef enum _clock_pll +{ + kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< PLL ARM */ + kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */ + kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */ + kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */ + kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< PLL Video */ + + kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), /*!< PLL Enet0 */ + kCLOCK_PllEnet2 = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET2_REF_EN_SHIFT), /*!< PLL Enet1 */ + kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< PLL Enet2 */ + + kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2_OFFSET, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), /*!< PLL USB2 */ + +} clock_pll_t; + +/*! @brief PLL PFD name */ +typedef enum _clock_pfd +{ + kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */ + kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */ + kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */ + kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */ +} clock_pfd_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Set CCM MUX node to certain value. + * + * @param mux Which mux node to set, see \ref clock_mux_t. + * @param value Clock mux value to set, different mux has different value range. + */ +static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value) +{ + uint32_t busyShift; + + busyShift = CCM_TUPLE_BUSY_SHIFT(mux); + CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux)); + + assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while (CCM->CDHIPR & (1U << busyShift)) + { + } + } +} + +/*! + * @brief Get CCM MUX value. + * + * @param mux Which mux node to get, see \ref clock_mux_t. + * @return Clock mux value. + */ +static inline uint32_t CLOCK_GetMux(clock_mux_t mux) +{ + return (CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux)) >> CCM_TUPLE_SHIFT(mux); +} + +/*! + * @brief Set CCM DIV node to certain value. + * + * @param divider Which div node to set, see \ref clock_div_t. + * @param value Clock div value to set, different divider has different value range. + */ +static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value) +{ + uint32_t busyShift; + + busyShift = CCM_TUPLE_BUSY_SHIFT(divider); + CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) | + (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider)); + + assert(busyShift <= CCM_NO_BUSY_WAIT); + + /* Clock switch need Handshake? */ + if (CCM_NO_BUSY_WAIT != busyShift) + { + /* Wait until CCM internal handshake finish. */ + while (CCM->CDHIPR & (1U << busyShift)) + { + } + } +} + +/*! + * @brief Get CCM DIV node value. + * + * @param divider Which div node to get, see \ref clock_div_t. + */ +static inline uint32_t CLOCK_GetDiv(clock_div_t divider) +{ + return ((CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider)); +} + +/*! + * @brief Control the clock gate for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + * @param value Clock gate value to set, see \ref clock_gate_value_t. + */ +static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value) +{ + uint32_t index = ((uint32_t)name) >> 8U; + uint32_t shift = ((uint32_t)name) & 0x1FU; + volatile uint32_t *reg; + + assert(index <= 7); + + reg = ((volatile uint32_t *)&CCM->CCGR0) + index; + *reg = ((*reg) & ~(3U << shift)) | (((uint32_t)value) << shift); +} + +/*! + * @brief Enable the clock for specific IP. + * + * @param name Which clock to enable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_EnableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait); +} + +/*! + * @brief Disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_ip_name_t. + */ +static inline void CLOCK_DisableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded); +} + +/*! + * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal. + * + * @param mode Which mode to enter, see \ref clock_mode_t. + */ +static inline void CLOCK_SetMode(clock_mode_t mode) +{ + CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode); +} + +/*! + * @brief Gets the OSC clock frequency. + * + * This function will return the external XTAL OSC frequency if it is selected as the source of OSC, + * otherwise internal 24MHz RC OSC frequency will be returned. + * + * @param osc OSC type to get frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetOscFreq(void) +{ + return (XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) ? 24000000UL : g_xtalFreq; +} + +/*! + * @brief Gets the AHB clock frequency. + * + * @return The AHB clock frequency value in hertz. + */ +uint32_t CLOCK_GetAhbFreq(void); + +/*! + * @brief Gets the SEMC clock frequency. + * + * @return The SEMC clock frequency value in hertz. + */ +uint32_t CLOCK_GetSemcFreq(void); + +/*! + * @brief Gets the IPG clock frequency. + * + * @return The IPG clock frequency value in hertz. + */ +uint32_t CLOCK_GetIpgFreq(void); + +/*! + * @brief Gets the PER clock frequency. + * + * @return The PER clock frequency value in hertz. + */ +uint32_t CLOCK_GetPerClkFreq(void); + +/*! + * @brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * @param clockName Clock names defined in clock_name_t + * @return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t name); + +/*! + * @brief Get the CCM CPU/core/system frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetCpuClkFreq(void) +{ + return CLOCK_GetFreq(kCLOCK_CpuClk); +} + +/*! + * @name OSC operations + * @{ + */ + +/*! + * @brief Initialize the external 24MHz clock. + * + * This function supports two modes: + * 1. Use external crystal oscillator. + * 2. Bypass the external crystal oscillator, using input source clock directly. + * + * After this function, please call @ref CLOCK_SetXtal0Freq to inform clock driver + * the external clock frequency. + * + * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator. + * @note This device does not support bypass external crystal oscillator, so + * the input parameter should always be false. + */ +void CLOCK_InitExternalClk(bool bypassXtalOsc); + +/*! + * @brief Deinitialize the external 24MHz clock. + * + * This function disables the external 24MHz clock. + * + * After this function, please call @ref CLOCK_SetXtal0Freq to set external clock + * frequency to 0. + */ +void CLOCK_DeinitExternalClk(void); + +/*! + * @brief Switch the OSC. + * + * This function switches the OSC source for SoC. + * + * @param osc OSC source to switch to. + */ +void CLOCK_SwitchOsc(clock_osc_t osc); + +/*! + * @brief Gets the RTC clock frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetRtcFreq(void) +{ + return 32768U; +} + +/*! + * @brief Set the XTAL (24M OSC) frequency based on board setting. + * + * @param freq The XTAL input clock frequency in Hz. + */ +static inline void CLOCK_SetXtalFreq(uint32_t freq) +{ + g_xtalFreq = freq; +} + +/*! + * @brief Set the RTC XTAL (32K OSC) frequency based on board setting. + * + * @param freq The RTC XTAL input clock frequency in Hz. + */ +static inline void CLOCK_SetRtcXtalFreq(uint32_t freq) +{ + g_rtcXtalFreq = freq; +} + +/*! + * @brief Initialize the RC oscillator 24MHz clock. + */ +void CLOCK_InitRcOsc24M(void); + +/*! + * @brief Power down the RCOSC 24M clock. + */ +void CLOCK_DeinitRcOsc24M(void); +/* @} */ + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void); + +/* @} */ + +/*! + * @name PLL/PFD operations + * @{ + */ +/*! + * @brief PLL bypass setting + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @param bypass Bypass the PLL. + * - true: Bypass the PLL. + * - false:Not bypass the PLL. + */ +static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass) +{ + if (bypass) + { + CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT; + } + else + { + CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1U << CCM_ANALOG_PLL_BYPASS_SHIFT; + } +} + +/*! + * @brief Check if PLL is bypassed + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @return PLL bypass status. + * - true: The PLL is bypassed. + * - false: The PLL is not bypassed. + */ +static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_PLL_BYPASS_SHIFT)); +} + +/*! + * @brief Check if PLL is enabled + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @return PLL bypass status. + * - true: The PLL is enabled. + * - false: The PLL is not enabled. + */ +static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1U << CCM_ANALOG_TUPLE_SHIFT(pll))); +} + +/*! + * @brief PLL bypass clock source setting. + * Note: change the bypass clock source also change the pll reference clock source. + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @param src Bypass clock source, reference _clock_pll_bypass_clk_src. + */ +static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src) +{ + CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src; +} + +/*! + * @brief Get PLL bypass clock value, it is PLL reference clock actually. + * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 + * will be returned. + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration) + * @retval bypass reference clock frequency value. + */ +static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll) +{ + return (((CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK) >> + CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == kCLOCK_PllClkSrc24M) ? + CLOCK_GetOscFreq() : + CLKPN_FREQ; +} + +/*! + * @brief Initialize the ARM PLL. + * + * This function initialize the ARM PLL with specific settings + * + * @param config configuration to set to PLL. + */ +void CLOCK_InitArmPll(const clock_arm_pll_config_t *config); + +/*! + * @brief De-initialize the ARM PLL. + */ +void CLOCK_DeinitArmPll(void); + +/*! + * @brief Initialize the System PLL. + * + * This function initializes the System PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitSysPll(const clock_sys_pll_config_t *config); + +/*! + * @brief De-initialize the System PLL. + */ +void CLOCK_DeinitSysPll(void); + +/*! + * @brief Initialize the USB1 PLL. + * + * This function initializes the USB1 PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config); + +/*! + * @brief Deinitialize the USB1 PLL. + */ +void CLOCK_DeinitUsb1Pll(void); + +/*! + * @brief Initialize the USB2 PLL. + * + * This function initializes the USB2 PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config); + +/*! + * @brief Deinitialize the USB2 PLL. + */ +void CLOCK_DeinitUsb2Pll(void); + +/*! + * @brief Initializes the Audio PLL. + * + * This function initializes the Audio PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config); + +/*! + * @brief De-initialize the Audio PLL. + */ +void CLOCK_DeinitAudioPll(void); + +/*! + * @brief Initialize the video PLL. + * + * This function configures the Video PLL with specific settings + * + * @param config configuration to set to PLL. + */ +void CLOCK_InitVideoPll(const clock_video_pll_config_t *config); + +/*! + * @brief De-initialize the Video PLL. + */ +void CLOCK_DeinitVideoPll(void); +/*! + * @brief Initialize the ENET PLL. + * + * This function initializes the ENET PLL with specific settings. + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config); + +/*! + * @brief Deinitialize the ENET PLL. + * + * This function disables the ENET PLL. + */ +void CLOCK_DeinitEnetPll(void); + +/*! + * @brief Get current PLL output frequency. + * + * This function get current output frequency of specific PLL + * + * @param pll pll name to get frequency. + * @return The PLL output frequency in hertz. + */ +uint32_t CLOCK_GetPllFreq(clock_pll_t pll); + +/*! + * @brief Initialize the System PLL PFD. + * + * This function initializes the System PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * @param pfd Which PFD clock to enable. + * @param pfdFrac The PFD FRAC value. + * @note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac); + +/*! + * @brief De-initialize the System PLL PFD. + * + * This function disables the System PLL PFD. + * + * @param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitSysPfd(clock_pfd_t pfd); + +/*! + * @brief Initialize the USB1 PLL PFD. + * + * This function initializes the USB1 PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * @param pfd Which PFD clock to enable. + * @param pfdFrac The PFD FRAC value. + * @note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac); + +/*! + * @brief De-initialize the USB1 PLL PFD. + * + * This function disables the USB1 PLL PFD. + * + * @param pfd Which PFD clock to disable. + */ +void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd); + +/*! + * @brief Get current System PLL PFD output frequency. + * + * This function get current output frequency of specific System PLL PFD + * + * @param pfd pfd name to get frequency. + * @return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd); + +/*! + * @brief Get current USB1 PLL PFD output frequency. + * + * This function get current output frequency of specific USB1 PLL PFD + * + * @param pfd pfd name to get frequency. + * @return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd); + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs0PhyPllClock(void); + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void); + +/*! + * @brief Use DWT to delay at least for some time. + * Please note that, this API will calculate the microsecond period with the maximum + * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise + * delay count was needed, please implement a new timer count to achieve this function. + * + * @param delay_us Delay time in unit of microsecond. + */ +void SDK_DelayAtLeastUs(uint32_t delay_us); +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_cmp.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_cmp.c new file mode 100644 index 0000000000..806703bac8 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_cmp.c @@ -0,0 +1,371 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_cmp.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cmp" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for CMP module. + * + * @param base CMP peripheral base address + */ +static uint32_t CMP_GetInstance(CMP_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to CMP bases for each instance. */ +static CMP_Type *const s_cmpBases[] = CMP_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to CMP clocks for each instance. */ +static const clock_ip_name_t s_cmpClocks[] = CMP_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Codes + ******************************************************************************/ +static uint32_t CMP_GetInstance(CMP_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_cmpBases); instance++) + { + if (s_cmpBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_cmpBases)); + + return instance; +} + +/*! + * brief Initializes the CMP. + * + * This function initializes the CMP module. The operations included are as follows. + * - Enabling the clock for CMP module. + * - Configuring the comparator. + * - Enabling the CMP module. + * Note that for some devices, multiple CMP instances share the same clock gate. In this case, to enable the clock for + * any instance enables all CMPs. See the appropriate MCU reference manual for the clock assignment of the CMP. + * + * param base CMP peripheral base address. + * param config Pointer to the configuration structure. + */ +void CMP_Init(CMP_Type *base, const cmp_config_t *config) +{ + assert(NULL != config); + + uint8_t tmp8; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_cmpClocks[CMP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Configure. */ + CMP_Enable(base, false); /* Disable the CMP module during configuring. */ + /* CMPx_CR1. */ + tmp8 = (uint8_t)(base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK)); + if (true == config->enableHighSpeed) + { + tmp8 |= CMP_CR1_PMODE_MASK; + } + if (true == config->enableInvertOutput) + { + tmp8 |= CMP_CR1_INV_MASK; + } + if (true == config->useUnfilteredOutput) + { + tmp8 |= CMP_CR1_COS_MASK; + } + if (true == config->enablePinOut) + { + tmp8 |= CMP_CR1_OPE_MASK; + } +#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE + if (true == config->enableTriggerMode) + { + tmp8 |= CMP_CR1_TRIGM_MASK; + } + else + { + tmp8 &= ~(uint8_t)CMP_CR1_TRIGM_MASK; + } +#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ + base->CR1 = tmp8; + + /* CMPx_CR0. */ + tmp8 = base->CR0 & ~(uint8_t)CMP_CR0_HYSTCTR_MASK; + tmp8 |= CMP_CR0_HYSTCTR(config->hysteresisMode); + base->CR0 = tmp8; + + CMP_Enable(base, config->enableCmp); /* Enable the CMP module after configured or not. */ +} + +/*! + * brief De-initializes the CMP module. + * + * This function de-initializes the CMP module. The operations included are as follows. + * - Disabling the CMP module. + * - Disabling the clock for CMP module. + * + * This function disables the clock for the CMP. + * Note that for some devices, multiple CMP instances share the same clock gate. In this case, before disabling the + * clock for the CMP, ensure that all the CMP instances are not used. + * + * param base CMP peripheral base address. + */ +void CMP_Deinit(CMP_Type *base) +{ + /* Disable the CMP module. */ + CMP_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_cmpClocks[CMP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Initializes the CMP user configuration structure. + * + * This function initializes the user configuration structure to these default values. + * code + * config->enableCmp = true; + * config->hysteresisMode = kCMP_HysteresisLevel0; + * config->enableHighSpeed = false; + * config->enableInvertOutput = false; + * config->useUnfilteredOutput = false; + * config->enablePinOut = false; + * config->enableTriggerMode = false; + * endcode + * param config Pointer to the configuration structure. + */ +void CMP_GetDefaultConfig(cmp_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableCmp = true; /* Enable the CMP module after initialization. */ + config->hysteresisMode = kCMP_HysteresisLevel0; + config->enableHighSpeed = false; + config->enableInvertOutput = false; + config->useUnfilteredOutput = false; + config->enablePinOut = false; +#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE + config->enableTriggerMode = false; +#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ +} + +/*! + * brief Sets the input channels for the comparator. + * + * This function sets the input channels for the comparator. + * Note that two input channels cannot be set the same way in the application. When the user selects the same input + * from the analog mux to the positive and negative port, the comparator is disabled automatically. + * + * param base CMP peripheral base address. + * param positiveChannel Positive side input channel number. Available range is 0-7. + * param negativeChannel Negative side input channel number. Available range is 0-7. + */ +void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel) +{ + uint8_t tmp8 = base->MUXCR; + + tmp8 &= ~(uint8_t)(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK); + tmp8 |= CMP_MUXCR_PSEL(positiveChannel) | CMP_MUXCR_MSEL(negativeChannel); + base->MUXCR = tmp8; +} + +#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA +/*! + * brief Enables/disables the DMA request for rising/falling events. + * + * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of + * the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from + * the CMP + * if the DMA is disabled. + * + * param base CMP peripheral base address. + * param enable Enables or disables the feature. + */ +void CMP_EnableDMA(CMP_Type *base, bool enable) +{ + uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */ + + if (enable) + { + tmp8 |= CMP_SCR_DMAEN_MASK; + } + else + { + tmp8 &= ~(uint8_t)CMP_SCR_DMAEN_MASK; + } + base->SCR = tmp8; +} +#endif /* FSL_FEATURE_CMP_HAS_DMA */ + +/*! + * brief Configures the filter. + * + * param base CMP peripheral base address. + * param config Pointer to the configuration structure. + */ +void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config) +{ + assert(NULL != config); + + uint8_t tmp8; + +#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT + /* Choose the clock source for sampling. */ + if (config->enableSample) + { + base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */ + } + else + { + base->CR1 &= ~CMP_CR1_SE_MASK; /* Choose the internal divided bus clock. */ + } +#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ + /* Set the filter count. */ + tmp8 = (uint8_t)(base->CR0 & ~CMP_CR0_FILTER_CNT_MASK); + tmp8 |= CMP_CR0_FILTER_CNT(config->filterCount); + base->CR0 = tmp8; + /* Set the filter period. It is used as the divider to bus clock. */ + base->FPR = CMP_FPR_FILT_PER(config->filterPeriod); +} + +/*! + * brief Configures the internal DAC. + * + * param base CMP peripheral base address. + * param config Pointer to the configuration structure. "NULL" disables the feature. + */ +void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config) +{ + uint8_t tmp8 = 0U; + + if (NULL == config) + { + /* Passing "NULL" as input parameter means no available configuration. So the DAC feature is disabled.*/ + base->DACCR = 0U; + return; + } + /* CMPx_DACCR. */ + tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */ + if (kCMP_VrefSourceVin2 == config->referenceVoltageSource) + { + tmp8 |= CMP_DACCR_VRSEL_MASK; + } + tmp8 |= CMP_DACCR_VOSEL(config->DACValue); + + base->DACCR = tmp8; +} + +/*! + * brief Enables the interrupts. + * + * param base CMP peripheral base address. + * param mask Mask value for interrupts. See "_cmp_interrupt_enable". + */ +void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask) +{ + uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */ + + if (0U != ((uint32_t)kCMP_OutputRisingInterruptEnable & mask)) + { + tmp8 |= CMP_SCR_IER_MASK; + } + if (0U != ((uint32_t)kCMP_OutputFallingInterruptEnable & mask)) + { + tmp8 |= CMP_SCR_IEF_MASK; + } + base->SCR = tmp8; +} + +/*! + * brief Disables the interrupts. + * + * param base CMP peripheral base address. + * param mask Mask value for interrupts. See "_cmp_interrupt_enable". + */ +void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask) +{ + uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */ + + if (0U != ((uint32_t)kCMP_OutputRisingInterruptEnable & mask)) + { + tmp8 &= ~(uint8_t)CMP_SCR_IER_MASK; + } + if (0U != ((uint32_t)kCMP_OutputFallingInterruptEnable & mask)) + { + tmp8 &= ~(uint8_t)CMP_SCR_IEF_MASK; + } + base->SCR = tmp8; +} + +/*! + * brief Gets the status flags. + * + * param base CMP peripheral base address. + * + * return Mask value for the asserted flags. See "_cmp_status_flags". + */ +uint32_t CMP_GetStatusFlags(CMP_Type *base) +{ + uint32_t ret32 = 0U; + + if (0U != (CMP_SCR_CFR_MASK & base->SCR)) + { + ret32 |= (uint32_t)kCMP_OutputRisingEventFlag; + } + if (0U != (CMP_SCR_CFF_MASK & base->SCR)) + { + ret32 |= (uint32_t)kCMP_OutputFallingEventFlag; + } + if (0U != (CMP_SCR_COUT_MASK & base->SCR)) + { + ret32 |= (uint32_t)kCMP_OutputAssertEventFlag; + } + return ret32; +} + +/*! + * brief Clears the status flags. + * + * param base CMP peripheral base address. + * param mask Mask value for the flags. See "_cmp_status_flags". + */ +void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask) +{ + uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change the w1c bits. */ + + if (0U != ((uint32_t)kCMP_OutputRisingEventFlag & mask)) + { + tmp8 |= CMP_SCR_CFR_MASK; + } + if (0U != ((uint32_t)kCMP_OutputFallingEventFlag & mask)) + { + tmp8 |= CMP_SCR_CFF_MASK; + } + base->SCR = tmp8; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_cmp.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_cmp.h new file mode 100644 index 0000000000..c62c710842 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_cmp.h @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CMP_H_ +#define _FSL_CMP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cmp + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CMP driver version 2.0.1. */ +#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @brief Interrupt enable/disable mask. + */ +enum _cmp_interrupt_enable +{ + kCMP_OutputRisingInterruptEnable = CMP_SCR_IER_MASK, /*!< Comparator interrupt enable rising. */ + kCMP_OutputFallingInterruptEnable = CMP_SCR_IEF_MASK, /*!< Comparator interrupt enable falling. */ +}; + +/*! + * @brief Status flags' mask. + */ +enum _cmp_status_flags +{ + kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK, /*!< Rising-edge on the comparison output has occurred. */ + kCMP_OutputFallingEventFlag = CMP_SCR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */ + kCMP_OutputAssertEventFlag = CMP_SCR_COUT_MASK, /*!< Return the current value of the analog comparator output. */ +}; + +/*! + * @brief CMP Hysteresis mode. + */ +typedef enum _cmp_hysteresis_mode +{ + kCMP_HysteresisLevel0 = 0U, /*!< Hysteresis level 0. */ + kCMP_HysteresisLevel1 = 1U, /*!< Hysteresis level 1. */ + kCMP_HysteresisLevel2 = 2U, /*!< Hysteresis level 2. */ + kCMP_HysteresisLevel3 = 3U, /*!< Hysteresis level 3. */ +} cmp_hysteresis_mode_t; + +/*! + * @brief CMP Voltage Reference source. + */ +typedef enum _cmp_reference_voltage_source +{ + kCMP_VrefSourceVin1 = 0U, /*!< Vin1 is selected as a resistor ladder network supply reference Vin. */ + kCMP_VrefSourceVin2 = 1U, /*!< Vin2 is selected as a resistor ladder network supply reference Vin. */ +} cmp_reference_voltage_source_t; + +/*! + * @brief Configures the comparator. + */ +typedef struct _cmp_config +{ + bool enableCmp; /*!< Enable the CMP module. */ + cmp_hysteresis_mode_t hysteresisMode; /*!< CMP Hysteresis mode. */ + bool enableHighSpeed; /*!< Enable High-speed (HS) comparison mode. */ + bool enableInvertOutput; /*!< Enable the inverted comparator output. */ + bool useUnfilteredOutput; /*!< Set the compare output(COUT) to equal COUTA(true) or COUT(false). */ + bool enablePinOut; /*!< The comparator output is available on the associated pin. */ +#if defined(FSL_FEATURE_CMP_HAS_TRIGGER_MODE) && FSL_FEATURE_CMP_HAS_TRIGGER_MODE + bool enableTriggerMode; /*!< Enable the trigger mode. */ +#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ +} cmp_config_t; + +/*! + * @brief Configures the filter. + */ +typedef struct _cmp_filter_config +{ +#if defined(FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT) && FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT + bool enableSample; /*!< Using the external SAMPLE as a sampling clock input or using a divided bus clock. */ +#endif /* FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT */ + uint8_t filterCount; /*!< Filter Sample Count. Available range is 1-7; 0 disables the filter.*/ + uint8_t filterPeriod; /*!< Filter Sample Period. The divider to the bus clock. Available range is 0-255. */ +} cmp_filter_config_t; + +/*! + * @brief Configures the internal DAC. + */ +typedef struct _cmp_dac_config +{ + cmp_reference_voltage_source_t referenceVoltageSource; /*!< Supply voltage reference source. */ + uint8_t DACValue; /*!< Value for the DAC Output Voltage. Available range is 0-63.*/ +} cmp_dac_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initializes the CMP. + * + * This function initializes the CMP module. The operations included are as follows. + * - Enabling the clock for CMP module. + * - Configuring the comparator. + * - Enabling the CMP module. + * Note that for some devices, multiple CMP instances share the same clock gate. In this case, to enable the clock for + * any instance enables all CMPs. See the appropriate MCU reference manual for the clock assignment of the CMP. + * + * @param base CMP peripheral base address. + * @param config Pointer to the configuration structure. + */ +void CMP_Init(CMP_Type *base, const cmp_config_t *config); + +/*! + * @brief De-initializes the CMP module. + * + * This function de-initializes the CMP module. The operations included are as follows. + * - Disabling the CMP module. + * - Disabling the clock for CMP module. + * + * This function disables the clock for the CMP. + * Note that for some devices, multiple CMP instances share the same clock gate. In this case, before disabling the + * clock for the CMP, ensure that all the CMP instances are not used. + * + * @param base CMP peripheral base address. + */ +void CMP_Deinit(CMP_Type *base); + +/*! + * @brief Enables/disables the CMP module. + * + * @param base CMP peripheral base address. + * @param enable Enables or disables the module. + */ +static inline void CMP_Enable(CMP_Type *base, bool enable) +{ + if (enable) + { + base->CR1 |= CMP_CR1_EN_MASK; + } + else + { + base->CR1 &= ~(uint8_t)CMP_CR1_EN_MASK; + } +} + +/*! + * @brief Initializes the CMP user configuration structure. + * + * This function initializes the user configuration structure to these default values. + * @code + * config->enableCmp = true; + * config->hysteresisMode = kCMP_HysteresisLevel0; + * config->enableHighSpeed = false; + * config->enableInvertOutput = false; + * config->useUnfilteredOutput = false; + * config->enablePinOut = false; + * config->enableTriggerMode = false; + * @endcode + * @param config Pointer to the configuration structure. + */ +void CMP_GetDefaultConfig(cmp_config_t *config); + +/*! + * @brief Sets the input channels for the comparator. + * + * This function sets the input channels for the comparator. + * Note that two input channels cannot be set the same way in the application. When the user selects the same input + * from the analog mux to the positive and negative port, the comparator is disabled automatically. + * + * @param base CMP peripheral base address. + * @param positiveChannel Positive side input channel number. Available range is 0-7. + * @param negativeChannel Negative side input channel number. Available range is 0-7. + */ +void CMP_SetInputChannels(CMP_Type *base, uint8_t positiveChannel, uint8_t negativeChannel); + +/* @} */ + +/*! + * @name Advanced Features + * @{ + */ + +#if defined(FSL_FEATURE_CMP_HAS_DMA) && FSL_FEATURE_CMP_HAS_DMA +/*! + * @brief Enables/disables the DMA request for rising/falling events. + * + * This function enables/disables the DMA request for rising/falling events. Either event triggers the generation of + * the DMA request from CMP if the DMA feature is enabled. Both events are ignored for generating the DMA request from + * the CMP + * if the DMA is disabled. + * + * @param base CMP peripheral base address. + * @param enable Enables or disables the feature. + */ +void CMP_EnableDMA(CMP_Type *base, bool enable); +#endif /* FSL_FEATURE_CMP_HAS_DMA */ + +#if defined(FSL_FEATURE_CMP_HAS_WINDOW_MODE) && FSL_FEATURE_CMP_HAS_WINDOW_MODE +/*! + * @brief Enables/disables the window mode. + * + * @param base CMP peripheral base address. + * @param enable Enables or disables the feature. + */ +static inline void CMP_EnableWindowMode(CMP_Type *base, bool enable) +{ + if (enable) + { + base->CR1 |= CMP_CR1_WE_MASK; + } + else + { + base->CR1 &= ~CMP_CR1_WE_MASK; + } +} +#endif /* FSL_FEATURE_CMP_HAS_WINDOW_MODE */ + +#if defined(FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE) && FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE +/*! + * @brief Enables/disables the pass through mode. + * + * @param base CMP peripheral base address. + * @param enable Enables or disables the feature. + */ +static inline void CMP_EnablePassThroughMode(CMP_Type *base, bool enable) +{ + if (enable) + { + base->MUXCR |= CMP_MUXCR_PSTM_MASK; + } + else + { + base->MUXCR &= ~CMP_MUXCR_PSTM_MASK; + } +} +#endif /* FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE */ + +/*! + * @brief Configures the filter. + * + * @param base CMP peripheral base address. + * @param config Pointer to the configuration structure. + */ +void CMP_SetFilterConfig(CMP_Type *base, const cmp_filter_config_t *config); + +/*! + * @brief Configures the internal DAC. + * + * @param base CMP peripheral base address. + * @param config Pointer to the configuration structure. "NULL" disables the feature. + */ +void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config); + +/*! + * @brief Enables the interrupts. + * + * @param base CMP peripheral base address. + * @param mask Mask value for interrupts. See "_cmp_interrupt_enable". + */ +void CMP_EnableInterrupts(CMP_Type *base, uint32_t mask); + +/*! + * @brief Disables the interrupts. + * + * @param base CMP peripheral base address. + * @param mask Mask value for interrupts. See "_cmp_interrupt_enable". + */ +void CMP_DisableInterrupts(CMP_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Results + * @{ + */ + +/*! + * @brief Gets the status flags. + * + * @param base CMP peripheral base address. + * + * @return Mask value for the asserted flags. See "_cmp_status_flags". + */ +uint32_t CMP_GetStatusFlags(CMP_Type *base); + +/*! + * @brief Clears the status flags. + * + * @param base CMP peripheral base address. + * @param mask Mask value for the flags. See "_cmp_status_flags". + */ +void CMP_ClearStatusFlags(CMP_Type *base, uint32_t mask); + +/* @} */ +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_CMP_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_common.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_common.c new file mode 100644 index 0000000000..deca9c626e --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_common.c @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#define SDK_MEM_MAGIC_NUMBER 12345U + +typedef struct _mem_align_control_block +{ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned address to real address */ +} mem_align_cb_t; + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common" +#endif + +#ifndef __GIC_PRIO_BITS +#if defined(ENABLE_RAM_VECTOR_TABLE) +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$RW_m_data$$Base[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ + uint32_t n; + uint32_t ret; + uint32_t irqMaskValue; + + irqMaskValue = DisableGlobalIRQ(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif + + return ret; +} +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#endif /* __GIC_PRIO_BITS. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) +#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1u << intNumber; + EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERCLR[index] = 1u << intNumber; +} +#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +void *SDK_Malloc(size_t size, size_t alignbytes) +{ + mem_align_cb_t *p_cb = NULL; + uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t); + void *p_align_addr, *p_addr = malloc(alignedsize); + + if (!p_addr) + { + return NULL; + } + + p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4U); + p_cb->identifier = SDK_MEM_MAGIC_NUMBER; + p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr; + + return (void *)p_align_addr; +} + +void SDK_Free(void *ptr) +{ + mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4U); + + if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) + { + return; + } + + free((void *)((uint32_t)ptr - p_cb->offset)); +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_common.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_common.h new file mode 100644 index 0000000000..65bc0acce1 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_common.h @@ -0,0 +1,597 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/*! @name Driver version */ +/*@{*/ +/*! @brief common driver version 2.0.1. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ + kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ + kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ + kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ +}; + +/*! @brief Generic status return codes. */ +enum _generic_status +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/* + * Macro guard for whether to use default weak IRQ implementation in drivers + */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + +/*! @name Min/max macros */ +/* @{ */ +#if !defined(MIN) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) +/* @} */ + +/*! @name Alignment variable definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +/** + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http://supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#endif +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var +#endif +#elif defined(__GNUC__) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) +#endif +#else +#error Toolchain not supported +#define SDK_ALIGN(var, alignbytes) var +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var +#endif +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var +#endif +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) +/* @} */ + +/*! @name Non-cacheable region definition macros */ +/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, + * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables + * will be initialized to zero in system startup. + */ +/* @{ */ +#if (defined(__ICCARM__)) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#endif +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var +#endif +#elif(defined(__GNUC__)) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes))) +#endif +#else +#error Toolchain not supported. +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var +#endif +/* @} */ + +/*! @name Time sensitive region */ +/* @{ */ +#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +#else +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#else +#error Toolchain not supported. +#endif +#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ +/* @} */ + +/*! @name Ram Function */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif(defined(__GNUC__)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/* @} */ + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) + extern "C" +{ +#endif + + /*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ + static inline status_t EnableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ + static inline status_t DisableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ + static inline uint32_t DisableGlobalIRQ(void) + { +#if defined (__XCC__) + return 0; +#else +#if defined(CPSR_I_Msk) + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + + __disable_irq(); + + return cpsr; +#else + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +#endif +#endif + } + + /*! + * @brief Enable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ + static inline void EnableGlobalIRQ(uint32_t primask) + { +#if defined (__XCC__) +#else +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#else + __set_PRIMASK(primask); +#endif +#endif + } + +#if defined(ENABLE_RAM_VECTOR_TABLE) + /*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ + uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + /*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ + void EnableDeepSleepIRQ(IRQn_Type interrupt); + + /*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ + void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + + /*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ + void *SDK_Malloc(size_t size, size_t alignbytes); + + /*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ + void SDK_Free(void *ptr); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_COMMON_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_common_arm.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_common_arm.c new file mode 100644 index 0000000000..e77a265ce4 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_common_arm.c @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common_arm" +#endif + +#ifndef __GIC_PRIO_BITS +#if defined(ENABLE_RAM_VECTOR_TABLE) +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +#ifdef __VECTOR_TABLE +#undef __VECTOR_TABLE +#endif + +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$RW_m_data$$Base[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ + uint32_t n; + uint32_t ret; + uint32_t irqMaskValue; + + irqMaskValue = DisableGlobalIRQ(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[(int32_t)irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[(int32_t)irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + + return ret; +} +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#endif /* __GIC_PRIO_BITS. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) + +/* + * When the SYSCON STARTER registers are discontinuous, these functions are + * implemented in fsl_power.c. + */ +#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1UL << intNumber; + (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERCLR[index] = 1UL << intNumber; +} +#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(SDK_DELAY_USE_DWT) && defined(DWT) +/* Use WDT. */ +static void enableCpuCycleCounter(void) +{ + /* Make sure the DWT trace fucntion is enabled. */ + if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) + { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } + + /* CYCCNT not supported on this device. */ + assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); + + /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */ + if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) + { + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; + } +} + +static uint32_t getCpuCycleCount(void) +{ + return DWT->CYCCNT; +} +#else /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ +/* Use software loop. */ +#if defined(__CC_ARM) /* This macro is arm v5 specific */ +/* clang-format off */ +__ASM static void DelayLoop(uint32_t count) +{ +loop + SUBS R0, R0, #1 + CMP R0, #0 + BNE loop + BX LR +} +/* clang-format on */ +#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__) +/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler, + * use SUB and CMP here for compatibility */ +static void DelayLoop(uint32_t count) +{ + __ASM volatile(" MOV R0, %0" : : "r"(count)); + __ASM volatile( + "loop: \n" +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + " SUB R0, R0, #1 \n" +#else + " SUBS R0, R0, #1 \n" +#endif + " CMP R0, #0 \n" + + " BNE loop \n" + : + : + : "r0"); +} +#endif /* defined(__CC_ARM) */ +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ + +/*! + * @brief Delay at least for some time. + * Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have + * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and + * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports + * up to 4294967 in current code. If long time delay is needed, please implement a new delay function. + * + * @param delayTime_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) +{ + uint64_t count; + + if (delayTime_us > 0U) + { + count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); + + assert(count <= UINT32_MAX); + +#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */ + + enableCpuCycleCounter(); + /* Calculate the count ticks. */ + count += getCpuCycleCount(); + + if (count > UINT32_MAX) + { + count -= UINT32_MAX; + /* Wait for cyccnt overflow. */ + while (count < getCpuCycleCount()) + { + } + } + + /* Wait for cyccnt reach count value. */ + while (count > getCpuCycleCount()) + { + } +#else + /* Divide value may be different in various environment to ensure delay is precise. + * Every loop count includes three instructions, due to Cortex-M7 sometimes executes + * two instructions in one period, through test here set divide 1.5. Other M cores use + * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does + * not matter because other instructions outside while loop is enough to fill the time. + */ +#if (__CORTEX_M == 7) + count = count / 3U * 2U; +#else + count = count / 4U; +#endif + DelayLoop((uint32_t)count); +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ + } +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_common_arm.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_common_arm.h new file mode 100644 index 0000000000..2678ff625c --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_common_arm.h @@ -0,0 +1,671 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_COMMON_ARM_H_ +#define _FSL_COMMON_ARM_H_ + +/* + * For CMSIS pack RTE. + * CMSIS pack RTE generates "RTC_Components.h" which contains the statements + * of the related element for all selected software components. + */ +#ifdef _RTE_ +#include "RTE_Components.h" +#endif + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/*! @name Atomic modification + * + * These macros are used for atomic access, such as read-modify-write + * to the peripheral registers. + * + * - SDK_ATOMIC_LOCAL_ADD + * - SDK_ATOMIC_LOCAL_SET + * - SDK_ATOMIC_LOCAL_CLEAR + * - SDK_ATOMIC_LOCAL_TOGGLE + * - SDK_ATOMIC_LOCAL_CLEAR_AND_SET + * + * Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr + * means the address of the peripheral register or variable you want to modify + * atomically, the parameter @c clearBits is the bits to clear, the parameter + * @c setBits it the bits to set. + * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this: + * + * @code + volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR; + + SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02); + @endcode + * + * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result, + * register bit1:bit0 = 0b10. + * + * @note For the platforms don't support exclusive load and store, these macros + * disable the global interrupt to pretect the modification. + * + * @note These macros only guarantee the local processor atomic operations. For + * the multi-processor devices, use hardware semaphore such as SEMA42 to + * guarantee exclusive access if necessary. + * + * @{ + */ + +/* clang-format off */ +#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) +/* clang-format on */ + +/* If the LDREX and STREX are supported, use them. */ +#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXB(addr); \ + (ops); \ + } while (0UL != __STREXB((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXH(addr); \ + (ops); \ + } while (0UL != __STREXH((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXW(addr); \ + (ops); \ + } while (0UL != __STREXW((val), (addr))) + +static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ + _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \ + _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits)))) +#else + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) += (val); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) |= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) &= ~(bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) ^= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) = (*(addr) & ~(clearBits)) | (setBits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz)) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz)) +/* @} */ + +/*! @name ISR exit barrier + * @{ + * + * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + * exception return operation might vector to incorrect interrupt. + * For Cortex-M7, if core speed much faster than peripheral register write speed, + * the peripheral interrupt flags may be still set after exiting ISR, this results to + * the same error similar with errata 83869. + */ +#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U)) +#define SDK_ISR_EXIT_BARRIER __DSB() +#else +#define SDK_ISR_EXIT_BARRIER +#endif + +/* @} */ + +/*! @name Alignment variable definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +/* + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http:/ /supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +#elif defined(__GNUC__) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported +#endif + +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) +/* @} */ + +/*! @name Non-cacheable region definition macros */ +/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable + * variables, please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, + * these zero-inited variables will be initialized to zero in system startup. + */ +/* @{ */ + +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \ + defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) + +#if (defined(__ICCARM__)) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" + +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var +#if (defined(__CC_ARM)) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var +#else +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var +#endif + +#elif (defined(__GNUC__)) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif + +#else + +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes) + +#endif + +/* @} */ + +/*! + * @name Time sensitive region + * @{ + */ +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(var) var @"DataQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess" +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var +#elif (defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + __attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ + +/*! @name Ram Function */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif (defined(__GNUC__)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/* @} */ + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + void DefaultISR(void); +#endif + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ +static inline status_t EnableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ +static inline status_t DisableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ +static inline uint32_t DisableGlobalIRQ(void) +{ +#if defined(CPSR_I_Msk) + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + + __disable_irq(); + + return cpsr; +#else + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +#endif +} + +/*! + * @brief Enable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ +static inline void EnableGlobalIRQ(uint32_t primask) +{ +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#else + __set_PRIMASK(primask); +#endif +} + +#if defined(ENABLE_RAM_VECTOR_TABLE) +/*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) +/*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void EnableDeepSleepIRQ(IRQn_Type interrupt); + +/*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @} */ + +#endif /* _FSL_COMMON_ARM_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_dcdc.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_dcdc.c new file mode 100644 index 0000000000..248628763c --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_dcdc.c @@ -0,0 +1,469 @@ +/* + * Copyright 2017, NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_dcdc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dcdc_1" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for DCDC module. + * + * @param base DCDC peripheral base address + */ +static uint32_t DCDC_GetInstance(DCDC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to DCDC bases for each instance. */ +static DCDC_Type *const s_dcdcBases[] = DCDC_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to DCDC clocks for each instance. */ +static const clock_ip_name_t s_dcdcClocks[] = DCDC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t DCDC_GetInstance(DCDC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dcdcBases); instance++) + { + if (s_dcdcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_dcdcBases)); + + return instance; +} + +/*! + * brief Enable the access to DCDC registers. + * + * param base DCDC peripheral base address. + */ +void DCDC_Init(DCDC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_dcdcClocks[DCDC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Disable the access to DCDC registers. + * + * param base DCDC peripheral base address. + */ +void DCDC_Deinit(DCDC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_dcdcClocks[DCDC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Configure the DCDC clock source. + * + * param base DCDC peripheral base address. + * param clockSource Clock source for DCDC. See to "dcdc_clock_source_t". + */ +void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource) +{ + uint32_t tmp32; + + /* Configure the DCDC_REG0 register. */ + tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | + DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK); + switch (clockSource) + { + case kDCDC_ClockInternalOsc: + tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; + break; + case kDCDC_ClockExternalOsc: + /* Choose the external clock and disable the internal clock. */ + tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK; + break; + case kDCDC_ClockAutoSwitch: + /* Set to switch from internal ring osc to xtal 24M if auto mode is enabled. */ + tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK; + break; + default: + break; + } + base->REG0 = tmp32; +} + +/*! + * brief Get the default setting for detection configuration. + * + * The default configuration are set according to responding registers' setting when powered on. + * They are: + * code + * config->enableXtalokDetection = false; + * config->powerDownOverVoltageDetection = true; + * config->powerDownLowVlotageDetection = false; + * config->powerDownOverCurrentDetection = true; + * config->powerDownPeakCurrentDetection = true; + * config->powerDownZeroCrossDetection = true; + * config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0; + * config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0; + * endcode + * + * param config Pointer to configuration structure. See to "dcdc_detection_config_t" + */ +void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->enableXtalokDetection = false; + config->powerDownOverVoltageDetection = true; + config->powerDownLowVlotageDetection = false; + config->powerDownOverCurrentDetection = true; + config->powerDownPeakCurrentDetection = true; + config->powerDownZeroCrossDetection = true; + config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0; + config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0; +} + +/*! + * breif Configure the DCDC detection. + * + * param base DCDC peripheral base address. + * param config Pointer to configuration structure. See to "dcdc_detection_config_t" + */ +void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + /* Configure the DCDC_REG0 register. */ + tmp32 = base->REG0 & + ~(DCDC_REG0_XTALOK_DISABLE_MASK | DCDC_REG0_PWD_HIGH_VOLT_DET_MASK | DCDC_REG0_PWD_CMP_BATT_DET_MASK | + DCDC_REG0_PWD_OVERCUR_DET_MASK | DCDC_REG0_PWD_CUR_SNS_CMP_MASK | DCDC_REG0_PWD_ZCD_MASK | + DCDC_REG0_CUR_SNS_THRSH_MASK | DCDC_REG0_OVERCUR_TRIG_ADJ_MASK); + + tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold) | + DCDC_REG0_OVERCUR_TRIG_ADJ(config->OverCurrentThreshold); + if (false == config->enableXtalokDetection) + { + tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK; + } + if (config->powerDownOverVoltageDetection) + { + tmp32 |= DCDC_REG0_PWD_HIGH_VOLT_DET_MASK; + } + if (config->powerDownLowVlotageDetection) + { + tmp32 |= DCDC_REG0_PWD_CMP_BATT_DET_MASK; + } + if (config->powerDownOverCurrentDetection) + { + tmp32 |= DCDC_REG0_PWD_OVERCUR_DET_MASK; + } + if (config->powerDownPeakCurrentDetection) + { + tmp32 |= DCDC_REG0_PWD_CUR_SNS_CMP_MASK; + } + if (config->powerDownZeroCrossDetection) + { + tmp32 |= DCDC_REG0_PWD_ZCD_MASK; + } + base->REG0 = tmp32; +} + +/*! + * brief Get the default setting for low power configuration. + * + * The default configuration are set according to responding registers' setting when powered on. + * They are: + * code + * config->enableOverloadDetection = true; + * config->enableAdjustHystereticValue = false; + * config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle; + * config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32; + * endcode + * + * param config Pointer to configuration structure. See to "dcdc_low_power_config_t" + */ +void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->enableOverloadDetection = true; + config->enableAdjustHystereticValue = false; + config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle; + config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32; +} + +/*! + * brief Configure the DCDC low power. + * + * param base DCDC peripheral base address. + * param config Pointer to configuration structure. See to "dcdc_low_power_config_t". + */ +void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + /* Configure the DCDC_REG0 register. */ + tmp32 = base->REG0 & ~(DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK | DCDC_REG0_LP_HIGH_HYS_MASK | + DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK | DCDC_REG0_LP_OVERLOAD_THRSH_MASK); + tmp32 |= DCDC_REG0_LP_OVERLOAD_FREQ_SEL(config->countChargingTimePeriod) | + DCDC_REG0_LP_OVERLOAD_THRSH(config->countChargingTimeThreshold); + if (config->enableOverloadDetection) + { + tmp32 |= DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK; + } + if (config->enableAdjustHystereticValue) + { + tmp32 |= DCDC_REG0_LP_HIGH_HYS_MASK; + } + base->REG0 = tmp32; +} + +/*! + * brief Get DCDC status flags. + * + * param base peripheral base address. + * return Mask of asserted status flags. See to "_dcdc_status_flags_t". + */ +uint32_t DCDC_GetstatusFlags(DCDC_Type *base) +{ + uint32_t tmp32 = 0U; + + if (DCDC_REG0_STS_DC_OK_MASK == (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) + { + tmp32 |= kDCDC_LockedOKStatus; + } + + return tmp32; +} + +/*! + * brief Reset current alert signal. Alert signal is generate by peak current detection. + * + * param base DCDC peripheral base address. + * param enable Switcher to reset signal. True means reset signal. False means don't reset signal. + */ +void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable) +{ + if (enable) + { + base->REG0 |= DCDC_REG0_CURRENT_ALERT_RESET_MASK; + } + else + { + base->REG0 &= ~DCDC_REG0_CURRENT_ALERT_RESET_MASK; + } +} + +/*! + * brief Get the default setting for loop control configuration. + * + * The default configuration are set according to responding registers' setting when powered on. + * They are: + * code + * config->enableCommonHysteresis = false; + * config->enableCommonThresholdDetection = false; + * config->enableInvertHysteresisSign = false; + * config->enableRCThresholdDetection = false; + * config->enableRCScaleCircuit = 0U; + * config->complementFeedForwardStep = 0U; + * config->controlParameterMagnitude = 2U; + * config->integralProportionalRatio = 2U; + * endcode + * + * param config Pointer to configuration structure. See to "dcdc_loop_control_config_t" + */ +void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->enableCommonHysteresis = false; + config->enableCommonThresholdDetection = false; + config->enableInvertHysteresisSign = false; + config->enableRCThresholdDetection = false; + config->enableRCScaleCircuit = 0U; + config->complementFeedForwardStep = 0U; + config->controlParameterMagnitude = 2U; + config->integralProportionalRatio = 2U; +} + +/*! + * brief Configure the DCDC loop control. + * + * param base DCDC peripheral base address. + * param config Pointer to configuration structure. See to "dcdc_loop_control_config_t". + */ +void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + + /* Configure the DCDC_REG1 register. */ + tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_HYST_MASK | DCDC_REG1_LOOPCTRL_HST_THRESH_MASK); + if (config->enableCommonHysteresis) + { + tmp32 |= DCDC_REG1_LOOPCTRL_EN_HYST_MASK; + } + if (config->enableCommonThresholdDetection) + { + tmp32 |= DCDC_REG1_LOOPCTRL_HST_THRESH_MASK; + } + base->REG1 = tmp32; + + /* configure the DCDC_REG2 register. */ + tmp32 = base->REG2 & ~(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK | + DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK | DCDC_REG2_LOOPCTRL_DC_FF_MASK | + DCDC_REG2_LOOPCTRL_DC_R_MASK | DCDC_REG2_LOOPCTRL_DC_C_MASK); + tmp32 |= DCDC_REG2_LOOPCTRL_DC_FF(config->complementFeedForwardStep) | + DCDC_REG2_LOOPCTRL_DC_R(config->controlParameterMagnitude) | + DCDC_REG2_LOOPCTRL_DC_C(config->integralProportionalRatio) | + DCDC_REG2_LOOPCTRL_EN_RCSCALE(config->enableRCScaleCircuit); + if (config->enableInvertHysteresisSign) + { + tmp32 |= DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK; + } + if (config->enableRCThresholdDetection) + { + tmp32 |= DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK; + } + base->REG2 = tmp32; +} + +/*! + * brief Configure for the min power. + * + * param base DCDC peripheral base address. + * param config Pointer to configuration structure. See to "dcdc_min_power_config_t". + */ +void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + + tmp32 = base->REG3 & ~DCDC_REG3_MINPWR_DC_HALFCLK_MASK; + if (config->enableUseHalfFreqForContinuous) + { + tmp32 |= DCDC_REG3_MINPWR_DC_HALFCLK_MASK; + } + base->REG3 = tmp32; +} + +/*! + * brief Adjust the target voltage of VDD_SOC in run mode and low power mode. + * + * This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is + * stabled. + * Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch + * back to run mode if it detects the current loading is larger than about 50 mA(typical value). + * + * param base DCDC peripheral base address. + * param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V. + * param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V. + */ +void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby) +{ + uint32_t tmp32; + + /* Unlock the step for the output. */ + base->REG3 &= ~DCDC_REG3_DISABLE_STEP_MASK; + + /* Configure the DCDC_REG3 register. */ + tmp32 = base->REG3 & ~(DCDC_REG3_TARGET_LP_MASK | DCDC_REG3_TRG_MASK); + + tmp32 |= DCDC_REG3_TARGET_LP(VDDStandby) | DCDC_REG3_TRG(VDDRun); + base->REG3 = tmp32; + + /* DCDC_STS_DC_OK bit will be de-asserted after target register changes. After output voltage settling to new + * target value, DCDC_STS_DC_OK will be asserted. */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) + { + } +} + +/*! + * brief Configure the DCDC internal regulator. + * + * param base DCDC peripheral base address. + * param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t". + */ +void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + + /* Configure the DCDC_REG1 register. */ + tmp32 = base->REG1 & ~(DCDC_REG1_REG_FBK_SEL_MASK | DCDC_REG1_REG_RLOAD_SW_MASK); + tmp32 |= DCDC_REG1_REG_FBK_SEL(config->feedbackPoint); + if (config->enableLoadResistor) + { + tmp32 |= DCDC_REG1_REG_RLOAD_SW_MASK; + } + base->REG1 = tmp32; +} + +/*! + * brief Boot DCDC into DCM(discontinous conduction mode). + * + * pwd_zcd=0x0; + * pwd_cmp_offset=0x0; + * dcdc_loopctrl_en_rcscale=0x3 or 0x5; + * DCM_set_ctrl=1'b1; + * + * param base DCDC peripheral base address. + */ +void DCDC_BootIntoDCM(DCDC_Type *base) +{ + base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK); + base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x4U) | + DCDC_REG2_DCM_SET_CTRL_MASK; +} + +/*! + * brief Boot DCDC into CCM(continous conduction mode). + * + * pwd_zcd=0x1; + * pwd_cmp_offset=0x0; + * dcdc_loopctrl_en_rcscale=0x3; + * + * param base DCDC peripheral base address. + */ +void DCDC_BootIntoCCM(DCDC_Type *base) +{ + base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK; + base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x3U); +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_dcdc.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_dcdc.h new file mode 100644 index 0000000000..62636f4186 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_dcdc.h @@ -0,0 +1,464 @@ +/* + * Copyright 2017, NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FSL_DCDC_H__ +#define __FSL_DCDC_H__ + +#include "fsl_common.h" + +/*! + * @addtogroup dcdc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief DCDC driver version. */ +#define FSL_DCDC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + /*! + * @brief DCDC status flags. + */ +enum _dcdc_status_flags_t +{ + kDCDC_LockedOKStatus = (1U << 0U), /*!< Indicate DCDC status. 1'b1: DCDC already settled 1'b0: DCDC is settling. */ +}; + +/*! + * @brief The current bias of low power comparator. + */ +typedef enum _dcdc_comparator_current_bias +{ + kDCDC_ComparatorCurrentBias50nA = 0U, /*!< The current bias of low power comparator is 50nA. */ + kDCDC_ComparatorCurrentBias100nA = 1U, /*!< The current bias of low power comparator is 100nA. */ + kDCDC_ComparatorCurrentBias200nA = 2U, /*!< The current bias of low power comparator is 200nA. */ + kDCDC_ComparatorCurrentBias400nA = 3U, /*!< The current bias of low power comparator is 400nA. */ +} dcdc_comparator_current_bias_t; + +/*! + * @brief The threshold of over current detection. + */ +typedef enum _dcdc_over_current_threshold +{ + kDCDC_OverCurrentThresholdAlt0 = 0U, /*!< 1A in the run mode, 0.25A in the power save mode. */ + kDCDC_OverCurrentThresholdAlt1 = 1U, /*!< 2A in the run mode, 0.25A in the power save mode. */ + kDCDC_OverCurrentThresholdAlt2 = 2U, /*!< 1A in the run mode, 0.2A in the power save mode. */ + kDCDC_OverCurrentThresholdAlt3 = 3U, /*!< 2A in the run mode, 0.2A in the power save mode. */ +} dcdc_over_current_threshold_t; + +/*! + * @brief The threshold if peak current detection. + */ +typedef enum _dcdc_peak_current_threshold +{ + kDCDC_PeakCurrentThresholdAlt0 = 0U, /*!< 150mA peak current threshold. */ + kDCDC_PeakCurrentThresholdAlt1 = 1U, /*!< 250mA peak current threshold. */ + kDCDC_PeakCurrentThresholdAlt2 = 2U, /*!< 350mA peak current threshold. */ + kDCDC_PeakCurrentThresholdAlt3 = 3U, /*!< 450mA peak current threshold. */ + kDCDC_PeakCurrentThresholdAlt4 = 4U, /*!< 550mA peak current threshold. */ + kDCDC_PeakCurrentThresholdAlt5 = 5U, /*!< 650mA peak current threshold. */ +} dcdc_peak_current_threshold_t; + +/*! + * @brief The period of counting the charging times in power save mode. + */ +typedef enum _dcdc_count_charging_time_period +{ + kDCDC_CountChargingTimePeriod8Cycle = 0U, /*!< Eight 32k cycle. */ + kDCDC_CountChargingTimePeriod16Cycle = 1U, /*!< Sixteen 32k cycle. */ +} dcdc_count_charging_time_period_t; + +/*! + * @brief The threshold of the counting number of charging times + */ +typedef enum _dcdc_count_charging_time_threshold +{ + kDCDC_CountChargingTimeThreshold32 = 0U, /*!< 0x0: 32. */ + kDCDC_CountChargingTimeThreshold64 = 1U, /*!< 0x1: 64. */ + kDCDC_CountChargingTimeThreshold16 = 2U, /*!< 0x2: 16. */ + kDCDC_CountChargingTimeThreshold8 = 3U, /*!< 0x3: 8. */ +} dcdc_count_charging_time_threshold_t; + +/*! + * @brief Oscillator clock option. + */ +typedef enum _dcdc_clock_source +{ + kDCDC_ClockAutoSwitch = 0U, /*!< Automatic clock switch from internal oscillator to external clock. */ + kDCDC_ClockInternalOsc = 1U, /*!< Use internal oscillator. */ + kDCDC_ClockExternalOsc = 2U, /*!< Use external 24M crystal oscillator. */ +} dcdc_clock_source_t; + +/*! + * @brief Configuration for DCDC detection. + */ +typedef struct _dcdc_detection_config +{ + bool enableXtalokDetection; /*!< Enable xtalok detection circuit. */ + bool powerDownOverVoltageDetection; /*!< Power down over-voltage detection comparator. */ + bool powerDownLowVlotageDetection; /*!< Power down low-voltage detection comparator. */ + bool powerDownOverCurrentDetection; /*!< Power down over-current detection. */ + bool powerDownPeakCurrentDetection; /*!< Power down peak-current detection. */ + bool powerDownZeroCrossDetection; /*!< Power down the zero cross detection function for discontinuous conductor + mode. */ + dcdc_over_current_threshold_t OverCurrentThreshold; /*!< The threshold of over current detection. */ + dcdc_peak_current_threshold_t PeakCurrentThreshold; /*!< The threshold of peak current detection. */ +} dcdc_detection_config_t; + +/*! + * @brief Configuration for the loop control. + */ +typedef struct _dcdc_loop_control_config +{ + bool enableCommonHysteresis; /*!< Enable hysteresis in switching converter common mode analog comparators. + This feature will improve transient supply ripple and efficiency. */ + bool enableCommonThresholdDetection; /*!< Increase the threshold detection for common mode analog comparator. */ + bool enableInvertHysteresisSign; /*!< Invert the sign of the hysteresis in DC-DC analog comparators. */ + bool enableRCThresholdDetection; /*!< Increase the threshold detection for RC scale circuit. */ + uint32_t enableRCScaleCircuit; /*!< Available range is 0~7. Enable analog circuit of DC-DC converter to respond + faster under transient load conditions. */ + uint32_t complementFeedForwardStep; /*!< Available range is 0~7. Two's complement feed forward step in duty cycle in + the switching DC-DC converter. Each time this field makes a transition from + 0x0, the loop filter of the DC-DC converter is stepped once by a value + proportional to the change. This can be used to force a certain control loop + behavior, such as improving response under known heavy load transients. */ + uint32_t controlParameterMagnitude; /*!< Available range is 0~15. Magnitude of proportional control parameter in the + switching DC-DC converter control loop. */ + uint32_t integralProportionalRatio; /*!< Available range is 0~3.Ratio of integral control parameter to proportional + control parameter in the switching DC-DC converter, and can be used to + optimize efficiency and loop response. */ +} dcdc_loop_control_config_t; +/*! + * @brief Configuration for DCDC low power. + */ +typedef struct _dcdc_low_power_config +{ + bool enableOverloadDetection; /*!< Enable the overload detection in power save mode, if current is larger than the + overloading threshold (typical value is 50 mA), DCDC will switch to the run mode + automatically. */ + bool enableAdjustHystereticValue; /*!< Adjust hysteretic value in low power from 12.5mV to 25mV. */ + dcdc_count_charging_time_period_t + countChargingTimePeriod; /*!< The period of counting the charging times in power save mode. */ + dcdc_count_charging_time_threshold_t + countChargingTimeThreshold; /*!< the threshold of the counting number of charging times during + the period that lp_overload_freq_sel sets in power save mode. */ +} dcdc_low_power_config_t; + +/*! + * @brief Configuration for DCDC internal regulator. + */ +typedef struct _dcdc_internal_regulator_config +{ + bool enableLoadResistor; /*!< control the load resistor of the internal regulator of DCDC, the load resistor is + connected as default "true", and need set to "false" to disconnect the load + resistor. */ + uint32_t feedbackPoint; /*!< Available range is 0~3. Select the feedback point of the internal regulator. */ +} dcdc_internal_regulator_config_t; + +/*! + * @brief Configuration for min power setting. + */ +typedef struct _dcdc_min_power_config +{ + bool enableUseHalfFreqForContinuous; /*!< Set DCDC clock to half frequency for the continuous mode. */ +} dcdc_min_power_config_t; +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Enable the access to DCDC registers. + * + * @param base DCDC peripheral base address. + */ +void DCDC_Init(DCDC_Type *base); + +/*! + * @brief Disable the access to DCDC registers. + * + * @param base DCDC peripheral base address. + */ +void DCDC_Deinit(DCDC_Type *base); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get DCDC status flags. + * + * @param base peripheral base address. + * @return Mask of asserted status flags. See to "_dcdc_status_flags_t". + */ +uint32_t DCDC_GetstatusFlags(DCDC_Type *base); + +/* @} */ + +/*! + * @name Misc control. + * @{ + */ + +/*! + * @brief Enable the output range comparator. + * + * The output range comparator is disabled by default. + * + * @param base DCDC peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void DCDC_EnableOutputRangeComparator(DCDC_Type *base, bool enable) +{ + if (enable) + { + base->REG0 &= ~DCDC_REG0_PWD_CMP_OFFSET_MASK; + } + else + { + base->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; + } +} + +/*! + * @brief Configure the DCDC clock source. + * + * @param base DCDC peripheral base address. + * @param clockSource Clock source for DCDC. See to "dcdc_clock_source_t". + */ +void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource); + +/*! + * @brief Get the default setting for detection configuration. + * + * The default configuration are set according to responding registers' setting when powered on. + * They are: + * @code + * config->enableXtalokDetection = false; + * config->powerDownOverVoltageDetection = true; + * config->powerDownLowVlotageDetection = false; + * config->powerDownOverCurrentDetection = true; + * config->powerDownPeakCurrentDetection = true; + * config->powerDownZeroCrossDetection = true; + * config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0; + * config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0; + * @endcode + * + * @param config Pointer to configuration structure. See to "dcdc_detection_config_t" + */ +void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config); + +/*! + * @breif Configure the DCDC detection. + * + * @param base DCDC peripheral base address. + * @param config Pointer to configuration structure. See to "dcdc_detection_config_t" + */ +void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config); + +/*! + * @brief Get the default setting for low power configuration. + * + * The default configuration are set according to responding registers' setting when powered on. + * They are: + * @code + * config->enableOverloadDetection = true; + * config->enableAdjustHystereticValue = false; + * config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle; + * config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32; + * @endcode + * + * @param config Pointer to configuration structure. See to "dcdc_low_power_config_t" + */ +void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config); + +/*! + * @brief Configure the DCDC low power. + * + * @param base DCDC peripheral base address. + * @param config Pointer to configuration structure. See to "dcdc_low_power_config_t". + */ +void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config); + +/*! + * @brief Reset current alert signal. Alert signal is generate by peak current detection. + * + * @param base DCDC peripheral base address. + * @param enable Switcher to reset signal. True means reset signal. False means don't reset signal. + */ +void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable); + +/*! + * @brief Set the bangap trim value to trim bandgap voltage. + * + * @param base DCDC peripheral base address. + * @param TrimValue The bangap trim value. Available range is 0U-31U. + */ +static inline void DCDC_SetBandgapVoltageTrimValue(DCDC_Type *base, uint32_t trimValue) +{ + base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK; + base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue); +} + +/*! + * @brief Get the default setting for loop control configuration. + * + * The default configuration are set according to responding registers' setting when powered on. + * They are: + * @code + * config->enableCommonHysteresis = false; + * config->enableCommonThresholdDetection = false; + * config->enableInvertHysteresisSign = false; + * config->enableRCThresholdDetection = false; + * config->enableRCScaleCircuit = 0U; + * config->complementFeedForwardStep = 0U; + * config->controlParameterMagnitude = 2U; + * config->integralProportionalRatio = 2U; + * @endcode + * + * @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t" + */ +void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config); + +/*! + * @brief Configure the DCDC loop control. + * + * @param base DCDC peripheral base address. + * @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t". + */ +void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config); + +/*! + * @brief Configure for the min power. + * + * @param base DCDC peripheral base address. + * @param config Pointer to configuration structure. See to "dcdc_min_power_config_t". + */ +void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config); + +/*! + * @brief Set the current bias of low power comparator. + * + * @param base DCDC peripheral base address. + * @param biasVaule The current bias of low power comparator. Refer to "dcdc_comparator_current_bias_t". + */ +static inline void DCDC_SetLPComparatorBiasValue(DCDC_Type *base, dcdc_comparator_current_bias_t biasVaule) +{ + base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK; + base->REG1 |= DCDC_REG1_LP_CMP_ISRC_SEL(biasVaule); +} + +static inline void DCDC_LockTargetVoltage(DCDC_Type *base) +{ + base->REG3 |= DCDC_REG3_DISABLE_STEP_MASK; +} + +/*! + * @brief Adjust the target voltage of VDD_SOC in run mode and low power mode. + * + * This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is + * stabled. + * Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch + * back to run mode if it detects the current loading is larger than about 50 mA(typical value). + * + * @param base DCDC peripheral base address. + * @param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V. + * @param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V. + */ +void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby); + +/*! + * @brief Configure the DCDC internal regulator. + * + * @param base DCDC peripheral base address. + * @param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t". + */ +void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config); + +/*! + * @brief Ajust delay to reduce ground noise. + * + * @param base DCDC peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void DCDC_EnableAdjustDelay(DCDC_Type *base, bool enable) +{ + if (enable) + { + base->REG3 |= DCDC_REG3_MISC_DELAY_TIMING_MASK; + } + else + { + base->REG3 &= ~DCDC_REG3_MISC_DELAY_TIMING_MASK; + } +} + +/*! + * @brief Enable/Disable to improve the transition from heavy load to light load. It is valid while zero + * cross detection is enabled. If ouput exceeds the threshold, DCDC would return CCM from DCM. + * + * @param base DCDC peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void DCDC_EnableImproveTransition(DCDC_Type *base, bool enable) +{ + if (enable) + { + base->REG2 |= DCDC_REG2_DCM_SET_CTRL_MASK; + } + else + { + base->REG2 &= ~DCDC_REG2_DCM_SET_CTRL_MASK; + } +} + +/* @} */ + +/*! + * @name Application guideline. + * @{ + */ + +/*! + * @brief Boot DCDC into DCM(discontinous conduction mode). + * + * pwd_zcd=0x0; + * pwd_cmp_offset=0x0; + * dcdc_loopctrl_en_rcscale=0x3 or 0x5; + * DCM_set_ctrl=1'b1; + * + * @param base DCDC peripheral base address. + */ +void DCDC_BootIntoDCM(DCDC_Type *base); + +/*! + * @brief Boot DCDC into CCM(continous conduction mode). + * + * pwd_zcd=0x1; + * pwd_cmp_offset=0x0; + * dcdc_loopctrl_en_rcscale=0x3; + * + * @param base DCDC peripheral base address. + */ +void DCDC_BootIntoCCM(DCDC_Type *base); + +#if defined(__cplusplus) +} +#endif + +#endif /* __FSL_DCDC_H__ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_dcp.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_dcp.c new file mode 100644 index 0000000000..b5d2dee619 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_dcp.c @@ -0,0 +1,1345 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_dcp.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dcp" +#endif + +/*! Compile time sizeof() check */ +#define BUILD_ASSURE(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused)) + +#define dcp_memcpy memcpy + +/*! Internal states of the HASH creation process */ +typedef enum _dcp_hash_algo_state +{ + kDCP_StateHashInit = 1u, /*!< Init state. */ + kDCP_StateHashUpdate, /*!< Update state. */ +} dcp_hash_algo_state_t; + +/*! multiple of 64-byte block represented as byte array of 32-bit words */ +typedef union _dcp_hash_block +{ + uint32_t w[DCP_HASH_BLOCK_SIZE / 4]; /*!< array of 32-bit words */ + uint8_t b[DCP_HASH_BLOCK_SIZE]; /*!< byte array */ +} dcp_hash_block_t; + +/*! internal dcp_hash context structure */ +typedef struct _dcp_hash_ctx_internal +{ + dcp_hash_block_t blk; /*!< memory buffer. only full blocks are written to DCP during hash updates */ + size_t blksz; /*!< number of valid bytes in memory buffer */ + dcp_hash_algo_t algo; /*!< selected algorithm from the set of supported algorithms */ + dcp_hash_algo_state_t state; /*!< finite machine state of the hash software process */ + uint32_t fullMessageSize; /*!< track message size */ + uint32_t ctrl0; /*!< HASH_INIT and HASH_TERM flags */ + uint32_t runningHash[9]; /*!< running hash. up to SHA-256 plus size, that is 36 bytes. */ + dcp_handle_t *handle; +} dcp_hash_ctx_internal_t; + +/*!< SHA-1/SHA-2 digest length in bytes */ +enum _dcp_hash_digest_len +{ + kDCP_OutLenSha1 = 20u, + kDCP_OutLenSha256 = 32u, + kDCP_OutLenCrc32 = 4u, +}; + +enum _dcp_work_packet_bit_definitions +{ + kDCP_CONTROL0_DECR_SEMAPHOR = 1u << 1, /* DECR_SEMAPHOR */ + kDCP_CONTROL0_ENABLE_HASH = 1u << 6, /* ENABLE_HASH */ + kDCP_CONTROL0_HASH_INIT = 1u << 12, /* HASH_INIT */ + kDCP_CONTROL0_HASH_TERM = 1u << 13, /* HASH_TERM */ + kDCP_CONTROL1_HASH_SELECT_SHA256 = 2u << 16, + kDCP_CONTROL1_HASH_SELECT_SHA1 = 0u << 16, + kDCP_CONTROL1_HASH_SELECT_CRC32 = 1u << 16, +}; + +/*! 64-byte block represented as byte array of 16 32-bit words */ +typedef union _dcp_sha_block +{ + uint32_t w[64 / 4]; /*!< array of 32-bit words */ + uint8_t b[64]; /*!< byte array */ +} dcp_sha_block_t; + +#if defined(DCP_HASH_CAVP_COMPATIBLE) +/* result of sha1 hash for message with zero size */ +static uint8_t s_nullSha1[] = {0xda, 0x39, 0xa3, 0xee, 0x5e, 0x6b, 0x4b, 0x0d, 0x32, 0x55, + 0xbf, 0xef, 0x95, 0x60, 0x18, 0x90, 0xaf, 0xd8, 0x07, 0x09}; +/* result of sha256 hash for message with zero size */ +static uint8_t s_nullSha256[] = {0xe3, 0xb0, 0xc4, 0x42, 0x98, 0xfc, 0x1c, 0x14, 0x9a, 0xfb, 0xf4, + 0xc8, 0x99, 0x6f, 0xb9, 0x24, 0x27, 0xae, 0x41, 0xe4, 0x64, 0x9b, + 0x93, 0x4c, 0xa4, 0x95, 0x99, 0x1b, 0x78, 0x52, 0xb8, 0x55}; +#endif /* DCP_HASH_CAVP_COMPATIBLE */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +static dcp_context_t s_dcpContextSwitchingBuffer; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void dcp_reverse_and_copy(uint8_t *src, uint8_t *dest, size_t src_len) +{ + for (int i = 0; i < src_len; i++) + { + dest[i] = src[src_len - 1 - i]; + } +} + +static status_t dcp_get_channel_status(DCP_Type *base, dcp_channel_t channel) +{ + uint32_t statReg = 0; + uint32_t semaReg = 0; + status_t status = kStatus_Fail; + + switch (channel) + { + case kDCP_Channel0: + statReg = base->CH0STAT; + semaReg = base->CH0SEMA; + break; + + case kDCP_Channel1: + statReg = base->CH1STAT; + semaReg = base->CH1SEMA; + break; + + case kDCP_Channel2: + statReg = base->CH2STAT; + semaReg = base->CH2SEMA; + break; + + case kDCP_Channel3: + statReg = base->CH3STAT; + semaReg = base->CH3SEMA; + break; + + default: + break; + } + + if (!((semaReg & DCP_CH0SEMA_VALUE_MASK) || (statReg & DCP_CH0STAT_ERROR_CODE_MASK))) + { + status = kStatus_Success; + } + + return status; +} + +static void dcp_clear_status(DCP_Type *base) +{ + volatile uint32_t *dcpStatClrPtr = &base->STAT + 2u; + *dcpStatClrPtr = 0xFFu; + + while(base->STAT & 0xffu) + { + } +} + +static void dcp_clear_channel_status(DCP_Type *base, uint32_t mask) +{ + volatile uint32_t *chStatClrPtr; + + if (mask & kDCP_Channel0) + { + chStatClrPtr = &base->CH0STAT + 2u; + *chStatClrPtr = 0xFFu; + } + if (mask & kDCP_Channel1) + { + chStatClrPtr = &base->CH1STAT + 2u; + *chStatClrPtr = 0xFFu; + } + if (mask & kDCP_Channel2) + { + chStatClrPtr = &base->CH2STAT + 2u; + *chStatClrPtr = 0xFFu; + } + if (mask & kDCP_Channel3) + { + chStatClrPtr = &base->CH3STAT + 2u; + *chStatClrPtr = 0xFFu; + } +} + +static status_t dcp_aes_set_sram_based_key(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key) +{ + base->KEY = DCP_KEY_INDEX(handle->keySlot) | DCP_KEY_SUBWORD(0); + /* move the key by 32-bit words */ + int i = 0; + size_t keySize = 16u; + while (keySize) + { + keySize -= sizeof(uint32_t); + base->KEYDATA = ((uint32_t *)(uintptr_t)key)[i]; + i++; + } + return kStatus_Success; +} + +/* Disable optimizations for GCC to prevent instruction reordering */ +#if defined(__GNUC__) +#pragma GCC push_options +#pragma GCC optimize ("O0") +#endif +static status_t dcp_schedule_work(DCP_Type *base, dcp_handle_t *handle, dcp_work_packet_t *dcpPacket) +{ + status_t status; + + /* check if our channel is active */ + if ((base->STAT & (uint32_t)handle->channel) != handle->channel) + { + /* disable global interrupt */ + uint32_t currPriMask = DisableGlobalIRQ(); + + /* re-check if our channel is still available */ + if ((base->STAT & (uint32_t)handle->channel) == 0) + { + volatile uint32_t *cmdptr = NULL; + volatile uint32_t *chsema = NULL; + + switch (handle->channel) + { + case kDCP_Channel0: + cmdptr = &base->CH0CMDPTR; + chsema = &base->CH0SEMA; + break; + + case kDCP_Channel1: + cmdptr = &base->CH1CMDPTR; + chsema = &base->CH1SEMA; + break; + + case kDCP_Channel2: + cmdptr = &base->CH2CMDPTR; + chsema = &base->CH2SEMA; + break; + + case kDCP_Channel3: + cmdptr = &base->CH3CMDPTR; + chsema = &base->CH3SEMA; + break; + + default: + break; + } + + if (cmdptr && chsema) + { + /* set out packet to DCP CMDPTR */ + *cmdptr = (uint32_t)dcpPacket; + + /* Make sure that all data memory accesses are completed before starting of the job */ + __DSB(); + __ISB(); + + /* set the channel semaphore to start the job */ + *chsema = 1u; + } + + status = kStatus_Success; + } + + else + { + status = kStatus_DCP_Again; + } + /* global interrupt enable */ + EnableGlobalIRQ(currPriMask); + } + + else + { + return kStatus_DCP_Again; + } + + return status; +} +#if defined(__GNUC__) +#pragma GCC pop_options +#endif + +/*! + * brief Set AES key to dcp_handle_t struct and optionally to DCP. + * + * Sets the AES key for encryption/decryption with the dcp_handle_t structure. + * The dcp_handle_t input argument specifies keySlot. + * If the keySlot is kDCP_OtpKey, the function will check the OTP_KEY_READY bit and will return it's ready to use + * status. + * For other keySlot selections, the function will copy and hold the key in dcp_handle_t struct. + * If the keySlot is one of the four DCP SRAM-based keys (one of kDCP_KeySlot0, kDCP_KeySlot1, kDCP_KeySlot2, + * kDCP_KeySlot3), + * this function will also load the supplied key to the specified keySlot in DCP. + * + * param base DCP peripheral base address. + * param handle Handle used for the request. + * param key 0-mod-4 aligned pointer to AES key. + * param keySize AES key size in bytes. Shall equal 16. + * return status from set key operation + */ +status_t DCP_AES_SetKey(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key, size_t keySize) +{ + status_t status = kStatus_Fail; + + if ((kDCP_OtpKey == handle->keySlot) || (kDCP_OtpUniqueKey == handle->keySlot)) + { + /* for AES OTP and unique key, check and return read from fuses status */ + if ((base->STAT & DCP_STAT_OTP_KEY_READY_MASK) == DCP_STAT_OTP_KEY_READY_MASK) + { + status = kStatus_Success; + } + } + else + { + /* only work with aligned key[] */ + if (0x3U & (uintptr_t)key) + { + return kStatus_InvalidArgument; + } + + /* keySize must be 16. */ + if (keySize != 16U) + { + return kStatus_InvalidArgument; + } + + /* move the key by 32-bit words */ + int i = 0; + while (keySize) + { + keySize -= sizeof(uint32_t); + handle->keyWord[i] = ((uint32_t *)(uintptr_t)key)[i]; + i++; + } + + if (kDCP_PayloadKey != handle->keySlot) + { + /* move the key by 32-bit words to DCP SRAM-based key storage */ + status = dcp_aes_set_sram_based_key(base, handle, key); + } + else + { + /* for PAYLOAD_KEY, just return Ok status now */ + status = kStatus_Success; + } + } + + return status; +} + +/*! + * brief Encrypts AES on one or multiple 128-bit block(s). + * + * Encrypts AES. + * The source plaintext and destination ciphertext can overlap in system memory. + * + * param base DCP peripheral base address + * param handle Handle used for this request. + * param plaintext Input plain text to encrypt + * param[out] ciphertext Output cipher text + * param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * return Status from encrypt operation + */ +status_t DCP_AES_EncryptEcb( + DCP_Type *base, dcp_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size) +{ + status_t completionStatus = kStatus_Fail; + dcp_work_packet_t dcpWork = {0}; + + do + { + completionStatus = DCP_AES_EncryptEcbNonBlocking(base, handle, &dcpWork, plaintext, ciphertext, size); + } while (completionStatus == kStatus_DCP_Again); + + if (completionStatus != kStatus_Success) + { + return completionStatus; + } + + return DCP_WaitForChannelComplete(base, handle); +} + +/*! + * brief Encrypts AES using the ECB block mode. + * + * Puts AES ECB encrypt work packet to DCP channel. + * + * param base DCP peripheral base address + * param handle Handle used for this request. + * param[out] dcpPacket Memory for the DCP work packet. + * param plaintext Input plain text to encrypt. + * param[out] ciphertext Output cipher text + * param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * return kStatus_Success The work packet has been scheduled at DCP channel. + * return kStatus_DCP_Again The DCP channel is busy processing previous request. + */ +status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base, + dcp_handle_t *handle, + dcp_work_packet_t *dcpPacket, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size) +{ + /* Size must be 16-byte multiple */ + if ((size < 16u) || (size % 16u)) + { + return kStatus_InvalidArgument; + } + + dcpPacket->control0 = + 0x122u | (handle->swapConfig & 0xFC0000u); /* CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */ + dcpPacket->sourceBufferAddress = (uint32_t)plaintext; + dcpPacket->destinationBufferAddress = (uint32_t)ciphertext; + dcpPacket->bufferSize = (uint32_t)size; + + if (handle->keySlot == kDCP_OtpKey) + { + dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ + dcpPacket->control1 = (0xFFu << 8); /* KEY_SELECT = OTP_KEY */ + } + else if (handle->keySlot == kDCP_OtpUniqueKey) + { + dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ + dcpPacket->control1 = (0xFEu << 8); /* KEY_SELECT = UNIQUE_KEY */ + } + else if (handle->keySlot == kDCP_PayloadKey) + { + /* ECB does not have IV, so we can point payload directly to keyWord[] stored in handle. */ + dcpPacket->payloadPointer = (uint32_t)&handle->keyWord[0]; + dcpPacket->control0 |= (1u << 11); /* PAYLOAD_KEY */ + } + else + { + dcpPacket->control1 = (handle->keySlot << 8); /* KEY_SELECT = keySlot */ + } + + return dcp_schedule_work(base, handle, dcpPacket); +} + +/*! + * brief Decrypts AES on one or multiple 128-bit block(s). + * + * Decrypts AES. + * The source ciphertext and destination plaintext can overlap in system memory. + * + * param base DCP peripheral base address + * param handle Handle used for this request. + * param ciphertext Input plain text to encrypt + * param[out] plaintext Output cipher text + * param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * return Status from decrypt operation + */ +status_t DCP_AES_DecryptEcb( + DCP_Type *base, dcp_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size) +{ + status_t completionStatus = kStatus_Fail; + dcp_work_packet_t dcpWork = {0}; + + do + { + completionStatus = DCP_AES_DecryptEcbNonBlocking(base, handle, &dcpWork, ciphertext, plaintext, size); + } while (completionStatus == kStatus_DCP_Again); + + if (completionStatus != kStatus_Success) + { + return completionStatus; + } + + return DCP_WaitForChannelComplete(base, handle); +} + +/*! + * brief Decrypts AES using ECB block mode. + * + * Puts AES ECB decrypt dcpPacket to DCP input job ring. + * + * param base DCP peripheral base address + * param handle Handle used for this request. + * param[out] dcpPacket Memory for the DCP work packet. + * param ciphertext Input cipher text to decrypt + * param[out] plaintext Output plain text + * param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * return kStatus_Success The work packet has been scheduled at DCP channel. + * return kStatus_DCP_Again The DCP channel is busy processing previous request. + */ +status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base, + dcp_handle_t *handle, + dcp_work_packet_t *dcpPacket, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size) +{ + /* Size must be 16-byte multiple */ + if ((size < 16u) || (size % 16u)) + { + return kStatus_InvalidArgument; + } + + dcpPacket->control0 = 0x22u | (handle->swapConfig & 0xFC0000u); /* ENABLE_CIPHER | DECR_SEMAPHORE */ + dcpPacket->sourceBufferAddress = (uint32_t)ciphertext; + dcpPacket->destinationBufferAddress = (uint32_t)plaintext; + dcpPacket->bufferSize = (uint32_t)size; + + if (handle->keySlot == kDCP_OtpKey) + { + dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ + dcpPacket->control1 = (0xFFu << 8); /* KEY_SELECT = OTP_KEY */ + } + else if (handle->keySlot == kDCP_OtpUniqueKey) + { + dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ + dcpPacket->control1 = (0xFEu << 8); /* KEY_SELECT = UNIQUE_KEY */ + } + else if (handle->keySlot == kDCP_PayloadKey) + { + /* ECB does not have IV, so we can point payload directly to keyWord[] stored in handle. */ + dcpPacket->payloadPointer = (uint32_t)&handle->keyWord[0]; + dcpPacket->control0 |= (1u << 11); /* PAYLOAD_KEY */ + } + else + { + dcpPacket->control1 = (handle->keySlot << 8); /* KEY_SELECT = keySlot */ + } + + return dcp_schedule_work(base, handle, dcpPacket); +} + +/*! + * brief Encrypts AES using CBC block mode. + * + * Encrypts AES using CBC block mode. + * The source plaintext and destination ciphertext can overlap in system memory. + * + * param base DCP peripheral base address + * param handle Handle used for this request. + * param plaintext Input plain text to encrypt + * param[out] ciphertext Output cipher text + * param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * param iv Input initial vector to combine with the first input block. + * return Status from encrypt operation + */ +status_t DCP_AES_EncryptCbc(DCP_Type *base, + dcp_handle_t *handle, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size, + const uint8_t iv[16]) +{ + status_t completionStatus = kStatus_Fail; + dcp_work_packet_t dcpWork = {0}; + + do + { + completionStatus = DCP_AES_EncryptCbcNonBlocking(base, handle, &dcpWork, plaintext, ciphertext, size, iv); + } while (completionStatus == kStatus_DCP_Again); + + if (completionStatus != kStatus_Success) + { + return completionStatus; + } + + return DCP_WaitForChannelComplete(base, handle); +} + +/*! + * brief Encrypts AES using CBC block mode. + * + * Puts AES CBC encrypt dcpPacket to DCP input job ring. + * + * param base DCP peripheral base address + * param handle Handle used for this request. Specifies jobRing. + * param[out] dcpPacket Memory for the DCP work packet. + * param plaintext Input plain text to encrypt + * param[out] ciphertext Output cipher text + * param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * param iv Input initial vector to combine with the first input block. + * return kStatus_Success The work packet has been scheduled at DCP channel. + * return kStatus_DCP_Again The DCP channel is busy processing previous request. + */ +status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base, + dcp_handle_t *handle, + dcp_work_packet_t *dcpPacket, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size, + const uint8_t *iv) +{ + /* Size must be 16-byte multiple */ + if ((size < 16u) || (size % 16u)) + { + return kStatus_InvalidArgument; + } + + dcpPacket->control0 = + 0x322u | (handle->swapConfig & 0xFC0000u); /* CIPHER_INIT | CIPHER_ENCRYPT | ENABLE_CIPHER | DECR_SEMAPHORE */ + dcpPacket->control1 = 0x10u; /* CBC */ + dcpPacket->sourceBufferAddress = (uint32_t)plaintext; + dcpPacket->destinationBufferAddress = (uint32_t)ciphertext; + dcpPacket->bufferSize = (uint32_t)size; + + if (handle->keySlot == kDCP_OtpKey) + { + dcpPacket->payloadPointer = (uint32_t)iv; + dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ + dcpPacket->control1 |= (0xFFu << 8); /* KEY_SELECT = OTP_KEY */ + } + else if (handle->keySlot == kDCP_OtpUniqueKey) + { + dcpPacket->payloadPointer = (uint32_t)iv; + dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ + dcpPacket->control1 |= (0xFEu << 8); /* KEY_SELECT = UNIQUE_KEY */ + } + else if (handle->keySlot == kDCP_PayloadKey) + { + /* In this case payload must contain key & iv in one array. */ + /* Copy iv into handle right behind the keyWord[] so we can point payload to keyWord[]. */ + dcp_memcpy(handle->iv, iv, 16); + dcpPacket->payloadPointer = (uint32_t)&handle->keyWord[0]; + dcpPacket->control0 |= (1u << 11); /* PAYLOAD_KEY */ + } + else + { + dcpPacket->payloadPointer = (uint32_t)iv; + dcpPacket->control1 |= ((uint32_t)handle->keySlot << 8); /* KEY_SELECT = keySlot */ + } + + return dcp_schedule_work(base, handle, dcpPacket); +} + +/*! + * brief Decrypts AES using CBC block mode. + * + * Decrypts AES using CBC block mode. + * The source ciphertext and destination plaintext can overlap in system memory. + * + * param base DCP peripheral base address + * param handle Handle used for this request. + * param ciphertext Input cipher text to decrypt + * param[out] plaintext Output plain text + * param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * param iv Input initial vector to combine with the first input block. + * return Status from decrypt operation + */ +status_t DCP_AES_DecryptCbc(DCP_Type *base, + dcp_handle_t *handle, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size, + const uint8_t iv[16]) +{ + status_t completionStatus = kStatus_Fail; + dcp_work_packet_t dcpWork = {0}; + + do + { + completionStatus = DCP_AES_DecryptCbcNonBlocking(base, handle, &dcpWork, ciphertext, plaintext, size, iv); + } while (completionStatus == kStatus_DCP_Again); + + if (completionStatus != kStatus_Success) + { + return completionStatus; + } + + return DCP_WaitForChannelComplete(base, handle); +} + +/*! + * brief Decrypts AES using CBC block mode. + * + * Puts AES CBC decrypt dcpPacket to DCP input job ring. + * + * param base DCP peripheral base address + * param handle Handle used for this request. Specifies jobRing. + * param[out] dcpPacket Memory for the DCP work packet. + * param ciphertext Input cipher text to decrypt + * param[out] plaintext Output plain text + * param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * param iv Input initial vector to combine with the first input block. + * return kStatus_Success The work packet has been scheduled at DCP channel. + * return kStatus_DCP_Again The DCP channel is busy processing previous request. + */ +status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base, + dcp_handle_t *handle, + dcp_work_packet_t *dcpPacket, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size, + const uint8_t *iv) +{ + /* Size must be 16-byte multiple */ + if ((size < 16u) || (size % 16u)) + { + return kStatus_InvalidArgument; + } + + dcpPacket->control0 = 0x222u | (handle->swapConfig & 0xFC0000u); /* CIPHER_INIT | ENABLE_CIPHER | DECR_SEMAPHORE */ + dcpPacket->control1 = 0x10u; /* CBC */ + dcpPacket->sourceBufferAddress = (uint32_t)ciphertext; + dcpPacket->destinationBufferAddress = (uint32_t)plaintext; + dcpPacket->bufferSize = (uint32_t)size; + + if (handle->keySlot == kDCP_OtpKey) + { + dcpPacket->payloadPointer = (uint32_t)iv; + dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ + dcpPacket->control1 |= (0xFFu << 8); /* OTP_KEY */ + } + else if (handle->keySlot == kDCP_OtpUniqueKey) + { + dcpPacket->payloadPointer = (uint32_t)iv; + dcpPacket->control0 |= (1u << 10); /* OTP_KEY */ + dcpPacket->control1 |= (0xFEu << 8); /* UNIQUE_KEY */ + } + else if (handle->keySlot == kDCP_PayloadKey) + { + /* in this case payload must contain KEY + IV together */ + /* copy iv into handle struct so we can point payload directly to keyWord[]. */ + dcp_memcpy(handle->iv, iv, 16); + dcpPacket->payloadPointer = (uint32_t)&handle->keyWord[0]; + dcpPacket->control0 |= (1u << 11); /* PAYLOAD_KEY */ + } + else + { + dcpPacket->payloadPointer = (uint32_t)iv; + dcpPacket->control1 |= ((uint32_t)handle->keySlot << 8); /* KEY_SELECT */ + } + + return dcp_schedule_work(base, handle, dcpPacket); +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the DCP configuration structure to a default value. The default + * values are as follows. + * dcpConfig->gatherResidualWrites = true; + * dcpConfig->enableContextCaching = true; + * dcpConfig->enableContextSwitching = true; + * dcpConfig->enableChannnel = kDCP_chEnableAll; + * dcpConfig->enableChannelInterrupt = kDCP_chIntDisable; + * + * param[out] config Pointer to configuration structure. + */ +void DCP_GetDefaultConfig(dcp_config_t *config) +{ + /* ENABLE_CONTEXT_CACHING is disabled by default as the DCP Hash driver uses + * dcp_hash_save_running_hash() and dcp_hash_restore_running_hash() to support + * Hash context switch (different messages interleaved) on the same channel. + */ + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + dcp_config_t userConfig = { + true, false, true, kDCP_chEnableAll, kDCP_chIntDisable, + }; + + *config = userConfig; +} + +/*! + * brief Enables clock to and enables DCP + * + * Enable DCP clock and configure DCP. + * + * param base DCP base address + * param config Pointer to configuration structure. + */ +void DCP_Init(DCP_Type *base, const dcp_config_t *config) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Dcp); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + base->CTRL = 0xF0800000u; /* reset value */ + base->CTRL = 0x30800000u; /* default value */ + + dcp_clear_status(base); + dcp_clear_channel_status(base, kDCP_Channel0 | kDCP_Channel1 | kDCP_Channel2 | kDCP_Channel3); + + base->CTRL = DCP_CTRL_GATHER_RESIDUAL_WRITES(config->gatherResidualWrites) | + DCP_CTRL_ENABLE_CONTEXT_CACHING(config->enableContextCaching) | + DCP_CTRL_ENABLE_CONTEXT_SWITCHING(config->enableContextSwitching) | + DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(config->enableChannelInterrupt); + + /* enable DCP channels */ + base->CHANNELCTRL = DCP_CHANNELCTRL_ENABLE_CHANNEL(config->enableChannel); + + /* use context switching buffer */ + base->CONTEXT = (uint32_t)&s_dcpContextSwitchingBuffer; +} + +/*! + * brief Disable DCP clock + * + * Reset DCP and Disable DCP clock. + * + * param base DCP base address + */ +void DCP_Deinit(DCP_Type *base) +{ + base->CTRL = 0xF0800000u; /* reset value */ + memset(&s_dcpContextSwitchingBuffer, 0, sizeof(s_dcpContextSwitchingBuffer)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_Dcp); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Poll and wait on DCP channel. + * + * Polls the specified DCP channel until current it completes activity. + * + * param base DCP peripheral base address. + * param handle Specifies DCP channel. + * return kStatus_Success When data processing completes without error. + * return kStatus_Fail When error occurs. + */ +status_t DCP_WaitForChannelComplete(DCP_Type *base, dcp_handle_t *handle) +{ + /* wait if our channel is still active */ + while ((base->STAT & (uint32_t)handle->channel) == handle->channel) + { + } + + if (dcp_get_channel_status(base, handle->channel) != kStatus_Success) + { + dcp_clear_status(base); + dcp_clear_channel_status(base, handle->channel); + return kStatus_Fail; + } + + dcp_clear_status(base); + return kStatus_Success; +} + +/*! + * @brief Check validity of algoritm. + * + * This function checks the validity of input argument. + * + * @param algo Tested algorithm value. + * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. + */ +static status_t dcp_hash_check_input_alg(dcp_hash_algo_t algo) +{ + if ((algo != kDCP_Sha256) && (algo != kDCP_Sha1) && (algo != kDCP_Crc32)) + { + return kStatus_InvalidArgument; + } + return kStatus_Success; +} + +/*! + * @brief Check validity of input arguments. + * + * This function checks the validity of input arguments. + * + * @param base DCP peripheral base address. + * @param ctx Memory buffer given by user application where the DCP_HASH_Init/DCP_HASH_Update/DCP_HASH_Finish store + * context. + * @param algo Tested algorithm value. + * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. + */ +static status_t dcp_hash_check_input_args(DCP_Type *base, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo) +{ + /* Check validity of input algorithm */ + if (kStatus_Success != dcp_hash_check_input_alg(algo)) + { + return kStatus_InvalidArgument; + } + + if ((NULL == ctx) || (NULL == base)) + { + return kStatus_InvalidArgument; + } + + return kStatus_Success; +} + +/*! + * @brief Check validity of internal software context. + * + * This function checks if the internal context structure looks correct. + * + * @param ctxInternal Internal context. + * @param message Input message address. + * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise. + */ +static status_t dcp_hash_check_context(dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *message) +{ + if ((NULL == message) || (NULL == ctxInternal) || (kStatus_Success != dcp_hash_check_input_alg(ctxInternal->algo))) + { + return kStatus_InvalidArgument; + } + return kStatus_Success; +} + +/*! + * @brief Initialize the SHA engine for new hash. + * + * This function sets kDCP_CONTROL0_HASH_INIT for control0 in work packet to start a new hash. + * + * @param base SHA peripheral base address. + * @param ctxInternal Internal context. + */ +static status_t dcp_hash_engine_init(DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal) +{ + status_t status; + + status = kStatus_InvalidArgument; + + if ((kDCP_Sha256 == ctxInternal->algo) || (kDCP_Sha1 == ctxInternal->algo) || (kDCP_Crc32 == ctxInternal->algo)) + { + ctxInternal->ctrl0 = kDCP_CONTROL0_HASH_INIT; + status = kStatus_Success; + } + + return status; +} + +static status_t dcp_hash_update_non_blocking( + DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal, dcp_work_packet_t *dcpPacket, const uint8_t *msg, size_t size) +{ + dcpPacket->control0 = ctxInternal->ctrl0 | (ctxInternal->handle->swapConfig & 0xFC0000u) | + kDCP_CONTROL0_ENABLE_HASH | kDCP_CONTROL0_DECR_SEMAPHOR; + if (ctxInternal->algo == kDCP_Sha256) + { + dcpPacket->control1 = kDCP_CONTROL1_HASH_SELECT_SHA256; + } + else if (ctxInternal->algo == kDCP_Sha1) + { + dcpPacket->control1 = kDCP_CONTROL1_HASH_SELECT_SHA1; + } + else if (ctxInternal->algo == kDCP_Crc32) + { + dcpPacket->control1 = kDCP_CONTROL1_HASH_SELECT_CRC32; + } + else + { + return kStatus_Fail; + } + dcpPacket->sourceBufferAddress = (uint32_t)msg; + dcpPacket->destinationBufferAddress = 0; + dcpPacket->bufferSize = size; + dcpPacket->payloadPointer = (uint32_t)ctxInternal->runningHash; + + return dcp_schedule_work(base, ctxInternal->handle, dcpPacket); +} + +static status_t dcp_hash_update(DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal, const uint8_t *msg, size_t size) +{ + status_t completionStatus = kStatus_Fail; + dcp_work_packet_t dcpWork = {0}; + + do + { + completionStatus = dcp_hash_update_non_blocking(base, ctxInternal, &dcpWork, msg, size); + } while (completionStatus == kStatus_DCP_Again); + + completionStatus = DCP_WaitForChannelComplete(base, ctxInternal->handle); + + ctxInternal->ctrl0 = 0; /* clear kDCP_CONTROL0_HASH_INIT and kDCP_CONTROL0_HASH_TERM flags */ + return (completionStatus); +} + +/*! + * @brief Adds message to current hash. + * + * This function merges the message to fill the internal buffer, empties the internal buffer if + * it becomes full, then process all remaining message data. + * + * + * @param base DCP peripheral base address. + * @param ctxInternal Internal context. + * @param message Input message. + * @param messageSize Size of input message in bytes. + * @return kStatus_Success. + */ +static status_t dcp_hash_process_message_data(DCP_Type *base, + dcp_hash_ctx_internal_t *ctxInternal, + const uint8_t *message, + size_t messageSize) +{ + status_t status = kStatus_Fail; + + /* if there is partially filled internal buffer, fill it to full block */ + if (ctxInternal->blksz > 0) + { + size_t toCopy = DCP_HASH_BLOCK_SIZE - ctxInternal->blksz; + dcp_memcpy(&ctxInternal->blk.b[ctxInternal->blksz], message, toCopy); + message += toCopy; + messageSize -= toCopy; + + /* process full internal block */ + status = dcp_hash_update(base, ctxInternal, &ctxInternal->blk.b[0], DCP_HASH_BLOCK_SIZE); + if (kStatus_Success != status) + { + return status; + } + } + + /* process all full blocks in message[] */ + uint32_t fullBlocksSize = ((messageSize >> 6) << 6); /* (X / 64) * 64 */ + if (fullBlocksSize > 0) + { + status = dcp_hash_update(base, ctxInternal, message, fullBlocksSize); + if (kStatus_Success != status) + { + return status; + } + message += fullBlocksSize; + messageSize -= fullBlocksSize; + } + + /* copy last incomplete message bytes into internal block */ + dcp_memcpy(&ctxInternal->blk.b[0], message, messageSize); + ctxInternal->blksz = messageSize; + + return status; +} + +/*! + * @brief Finalize the running hash to make digest. + * + * This function empties the internal buffer, adds padding bits, and generates final digest. + * + * @param base SHA peripheral base address. + * @param ctxInternal Internal context. + * @return kStatus_Success. + */ +static status_t dcp_hash_finalize(DCP_Type *base, dcp_hash_ctx_internal_t *ctxInternal) +{ + status_t status; + + ctxInternal->ctrl0 |= kDCP_CONTROL0_HASH_TERM; + status = dcp_hash_update(base, ctxInternal, &ctxInternal->blk.b[0], ctxInternal->blksz); + + return status; +} + +static void dcp_hash_save_running_hash(dcp_hash_ctx_internal_t *ctxInternal) +{ + uint32_t *srcAddr = NULL; + + switch (ctxInternal->handle->channel) + { + case kDCP_Channel0: + srcAddr = &s_dcpContextSwitchingBuffer.x[43]; + break; + + case kDCP_Channel1: + srcAddr = &s_dcpContextSwitchingBuffer.x[30]; + break; + + case kDCP_Channel2: + srcAddr = &s_dcpContextSwitchingBuffer.x[17]; + break; + + case kDCP_Channel3: + srcAddr = &s_dcpContextSwitchingBuffer.x[4]; + break; + + default: + break; + } + if (srcAddr) + { + dcp_memcpy(ctxInternal->runningHash, srcAddr, sizeof(ctxInternal->runningHash)); + } +} + +static void dcp_hash_restore_running_hash(dcp_hash_ctx_internal_t *ctxInternal) +{ + uint32_t *destAddr = NULL; + + switch (ctxInternal->handle->channel) + { + case kDCP_Channel0: + destAddr = &s_dcpContextSwitchingBuffer.x[43]; + break; + + case kDCP_Channel1: + destAddr = &s_dcpContextSwitchingBuffer.x[30]; + break; + + case kDCP_Channel2: + destAddr = &s_dcpContextSwitchingBuffer.x[17]; + break; + + case kDCP_Channel3: + destAddr = &s_dcpContextSwitchingBuffer.x[4]; + break; + + default: + break; + } + if (destAddr) + { + dcp_memcpy(destAddr, ctxInternal->runningHash, sizeof(ctxInternal->runningHash)); + } +} + +/*! + * brief Initialize HASH context + * + * This function initializes the HASH. + * + * param base DCP peripheral base address + * param handle Specifies the DCP channel used for hashing. + * param[out] ctx Output hash context + * param algo Underlaying algorithm to use for hash computation. + * return Status of initialization + */ +status_t DCP_HASH_Init(DCP_Type *base, dcp_handle_t *handle, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo) +{ + status_t status; + + dcp_hash_ctx_internal_t *ctxInternal; + /* compile time check for the correct structure size */ + BUILD_ASSURE(sizeof(dcp_hash_ctx_t) >= sizeof(dcp_hash_ctx_internal_t), dcp_hash_ctx_t_size); + uint32_t i; + + status = dcp_hash_check_input_args(base, ctx, algo); + if (status != kStatus_Success) + { + return status; + } + + /* set algorithm in context struct for later use */ + ctxInternal = (dcp_hash_ctx_internal_t *)ctx; + ctxInternal->algo = algo; + ctxInternal->blksz = 0u; + for (i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++) + { + ctxInternal->blk.w[0] = 0u; + } + ctxInternal->state = kDCP_StateHashInit; + ctxInternal->fullMessageSize = 0; + ctxInternal->handle = handle; + return status; +} + +/*! + * brief Add data to current HASH + * + * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be + * hashed. The functions blocks. If it returns kStatus_Success, the running hash + * has been updated (DCP has processed the input data), so the memory at ref input pointer + * can be released back to system. The DCP context buffer is updated with the running hash + * and with all necessary information to support possible context switch. + * + * param base DCP peripheral base address + * param[in,out] ctx HASH context + * param input Input data + * param inputSize Size of input data in bytes + * return Status of the hash update operation + */ +status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize) +{ + bool isUpdateState; + status_t status; + dcp_hash_ctx_internal_t *ctxInternal; + size_t blockSize; + + if (inputSize == 0) + { + return kStatus_Success; + } + + ctxInternal = (dcp_hash_ctx_internal_t *)ctx; + status = dcp_hash_check_context(ctxInternal, input); + if (kStatus_Success != status) + { + return status; + } + + ctxInternal->fullMessageSize += inputSize; + blockSize = DCP_HASH_BLOCK_SIZE; + /* if we are still less than DCP_HASH_BLOCK_SIZE bytes, keep only in context */ + if ((ctxInternal->blksz + inputSize) <= blockSize) + { + dcp_memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, input, inputSize); + ctxInternal->blksz += inputSize; + return status; + } + else + { + isUpdateState = ctxInternal->state == kDCP_StateHashUpdate; + if (!isUpdateState) + { + /* start NEW hash */ + status = dcp_hash_engine_init(base, ctxInternal); + if (status != kStatus_Success) + { + return status; + } + ctxInternal->state = kDCP_StateHashUpdate; + } + else + { + dcp_hash_restore_running_hash(ctxInternal); + } + } + + /* process input data */ + status = dcp_hash_process_message_data(base, ctxInternal, input, inputSize); + dcp_hash_save_running_hash(ctxInternal); + return status; +} + +/*! + * brief Finalize hashing + * + * Outputs the final hash (computed by DCP_HASH_Update()) and erases the context. + * + * param[in,out] ctx Input hash context + * param[out] output Output hash data + * param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of + * output[] buffer. On function return, it stores the number of updated output bytes. + * return Status of the hash finish operation + */ +status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize) +{ + size_t algOutSize = 0; + status_t status; + dcp_hash_ctx_internal_t *ctxInternal; + + ctxInternal = (dcp_hash_ctx_internal_t *)ctx; + status = dcp_hash_check_context(ctxInternal, output); + if (kStatus_Success != status) + { + return status; + } + + if (ctxInternal->state == kDCP_StateHashInit) + { + status = dcp_hash_engine_init(base, ctxInternal); + if (status != kStatus_Success) + { + return status; + } + } + else + { + dcp_hash_restore_running_hash(ctxInternal); + } + + size_t outSize = 0u; + + /* compute algorithm output length */ + switch (ctxInternal->algo) + { + case kDCP_Sha256: + outSize = kDCP_OutLenSha256; + break; + case kDCP_Sha1: + outSize = kDCP_OutLenSha1; + break; + case kDCP_Crc32: + outSize = kDCP_OutLenCrc32; + break; + default: + break; + } + algOutSize = outSize; + +#if defined(DCP_HASH_CAVP_COMPATIBLE) + if (ctxInternal->fullMessageSize == 0) + { + switch (ctxInternal->algo) + { + case kDCP_Sha256: + dcp_memcpy(&output[0], &s_nullSha256, 32); + break; + case kDCP_Sha1: + dcp_memcpy(&output[0], &s_nullSha1, 20); + break; + default: + break; + } + + return kStatus_Success; + } +#endif /* DCP_HASH_CAVP_COMPATIBLE */ + + /* flush message last incomplete block, if there is any, and add padding bits */ + status = dcp_hash_finalize(base, ctxInternal); + + if (outputSize) + { + if (algOutSize < *outputSize) + { + *outputSize = algOutSize; + } + else + { + algOutSize = *outputSize; + } + } + + /* Reverse and copy result to output[] */ + dcp_reverse_and_copy((uint8_t *)ctxInternal->runningHash, &output[0], algOutSize); + + memset(ctx, 0, sizeof(dcp_hash_ctx_t)); + return status; +} + +/*! + * brief Create HASH on given data + * + * Perform the full SHA or CRC32 in one function call. The function is blocking. + * + * param base DCP peripheral base address + * param handle Handle used for the request. + * param algo Underlaying algorithm to use for hash computation. + * param input Input data + * param inputSize Size of input data in bytes + * param[out] output Output hash data + * param[out] outputSize Output parameter storing the size of the output hash in bytes + * return Status of the one call hash operation. + */ +status_t DCP_HASH(DCP_Type *base, + dcp_handle_t *handle, + dcp_hash_algo_t algo, + const uint8_t *input, + size_t inputSize, + uint8_t *output, + size_t *outputSize) +{ + dcp_hash_ctx_t hashCtx; + status_t status; + + status = DCP_HASH_Init(base, handle, &hashCtx, algo); + if (status != kStatus_Success) + { + return status; + } + + status = DCP_HASH_Update(base, &hashCtx, input, inputSize); + if (status != kStatus_Success) + { + return status; + } + + status = DCP_HASH_Finish(base, &hashCtx, output, outputSize); + + return status; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_dcp.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_dcp.h new file mode 100644 index 0000000000..ce6625597c --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_dcp.h @@ -0,0 +1,552 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_DCP_H_ +#define _FSL_DCP_H_ + +#include "fsl_common.h" + +/*! @brief DCP status return codes. */ +enum _dcp_status +{ + kStatus_DCP_Again = MAKE_STATUS(kStatusGroup_DCP, 0), /*!< Non-blocking function shall be called again. */ +}; + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! + * @addtogroup dcp_driver + * @{ + */ +/*! @name Driver version */ +/*@{*/ +/*! @brief DCP driver version. Version 2.1.1. + * + * Current version: 2.1.1 + * + * Change log: + * - Version 2.1.1 + * - Add DCP status clearing when channel operation is complete + * + * - 2.1.0 + * - Add byte/word swap feature for key, input and output data + * + * - Version 2.0.0 + * - Initial version + */ +#define FSL_DCP_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ + +/*! @brief DCP channel enable. + * + */ +typedef enum _dcp_ch_enable +{ + kDCP_chDisable = 0U, /*!< DCP channel disable */ + kDCP_ch0Enable = 1U, /*!< DCP channel 0 enable */ + kDCP_ch1Enable = 2U, /*!< DCP channel 1 enable */ + kDCP_ch2Enable = 4U, /*!< DCP channel 2 enable */ + kDCP_ch3Enable = 8U, /*!< DCP channel 3 enable */ + kDCP_chEnableAll = 15U, /*!< DCP channel enable all */ +} _dcp_ch_enable_t; + +/*! @brief DCP interrupt enable. + * + */ +typedef enum _dcp_ch_int_enable +{ + kDCP_chIntDisable = 0U, /*!< DCP interrupts disable */ + kDCP_ch0IntEnable = 1U, /*!< DCP channel 0 interrupt enable */ + kDCP_ch1IntEnable = 2U, /*!< DCP channel 1 interrupt enable */ + kDCP_ch2IntEnable = 4U, /*!< DCP channel 2 interrupt enable */ + kDCP_ch3IntEnable = 8U, /*!< DCP channel 3 interrupt enable */ +} _dcp_ch_int_enable_t; + +/*! @brief DCP channel selection. + * + */ +typedef enum _dcp_channel +{ + kDCP_Channel0 = (1u << 16), /*!< DCP channel 0. */ + kDCP_Channel1 = (1u << 17), /*!< DCP channel 1. */ + kDCP_Channel2 = (1u << 18), /*!< DCP channel 2. */ + kDCP_Channel3 = (1u << 19), /*!< DCP channel 3. */ +} dcp_channel_t; + +/*! @brief DCP key slot selection. + * + */ +typedef enum _dcp_key_slot +{ + kDCP_KeySlot0 = 0U, /*!< DCP key slot 0. */ + kDCP_KeySlot1 = 1U, /*!< DCP key slot 1. */ + kDCP_KeySlot2 = 2U, /*!< DCP key slot 2.*/ + kDCP_KeySlot3 = 3U, /*!< DCP key slot 3. */ + kDCP_OtpKey = 4U, /*!< DCP OTP key. */ + kDCP_OtpUniqueKey = 5U, /*!< DCP unique OTP key. */ + kDCP_PayloadKey = 6U, /*!< DCP payload key. */ +} dcp_key_slot_t; + +/*! @brief DCP key, input & output swap options + * + */ +typedef enum _dcp_swap +{ + kDCP_NoSwap = 0x0U, + kDCP_KeyByteSwap = 0x40000U, + kDCP_KeyWordSwap = 0x80000U, + kDCP_InputByteSwap = 0x100000U, + kDCP_InputWordSwap = 0x200000U, + kDCP_OutputByteSwap = 0x400000U, + kDCP_OutputWordSwap = 0x800000U, +} dcp_swap_t; + +/*! @brief DCP's work packet. */ +typedef struct _dcp_work_packet +{ + uint32_t nextCmdAddress; + uint32_t control0; + uint32_t control1; + uint32_t sourceBufferAddress; + uint32_t destinationBufferAddress; + uint32_t bufferSize; + uint32_t payloadPointer; + uint32_t status; +} dcp_work_packet_t; + +/*! @brief Specify DCP's key resource and DCP channel. */ +typedef struct _dcp_handle +{ + dcp_channel_t channel; /*!< Specify DCP channel. */ + dcp_key_slot_t keySlot; /*!< For operations with key (such as AES encryption/decryption), specify DCP key slot. */ + uint32_t swapConfig; /*!< For configuration of key, input, output byte/word swap options */ + uint32_t keyWord[4]; + uint32_t iv[4]; +} dcp_handle_t; + +/*! @brief DCP's context buffer, used by DCP for context switching between channels. */ +typedef struct _dcp_context +{ + uint32_t x[208 / sizeof(uint32_t)]; +} dcp_context_t; + +/*! @brief DCP's configuration structure. */ +typedef struct _dcp_config +{ + bool gatherResidualWrites; /*!< Enable the ragged writes to the unaligned buffers. */ + bool enableContextCaching; /*!< Enable the caching of contexts between the operations. */ + bool enableContextSwitching; /*!< Enable automatic context switching for the channels. */ + uint8_t enableChannel; /*!< DCP channel enable. */ + uint8_t enableChannelInterrupt; /*!< Per-channel interrupt enable. */ +} dcp_config_t; + +/*! @} */ + +/******************************************************************************* + * AES Definitions + *******************************************************************************/ + +/*! + * @addtogroup dcp_driver_aes + * @{ + */ + +/*! AES block size in bytes */ +#define DCP_AES_BLOCK_SIZE 16 + +/*! + *@} + */ /* end of dcp_driver_aes */ + +/******************************************************************************* + * HASH Definitions + ******************************************************************************/ +/*! + * @addtogroup dcp_driver_hash + * @{ + */ + +/* DCP cannot correctly compute hash for message with zero size. When enabled, driver bypases DCP and returns correct + * hash value. If you are sure, that the driver will never be called with zero sized message, you can disable this + * feature to reduce code size */ +#define DCP_HASH_CAVP_COMPATIBLE + +/*! @brief Supported cryptographic block cipher functions for HASH creation */ +typedef enum _dcp_hash_algo_t +{ + kDCP_Sha1, /*!< SHA_1 */ + kDCP_Sha256, /*!< SHA_256 */ + kDCP_Crc32, /*!< CRC_32 */ +} dcp_hash_algo_t; + +/*! @brief DCP HASH Context size. */ +#define DCP_SHA_BLOCK_SIZE 128 /*!< internal buffer block size */ +#define DCP_HASH_BLOCK_SIZE DCP_SHA_BLOCK_SIZE /*!< DCP hash block size */ + +/*! @brief DCP HASH Context size. */ +#define DCP_HASH_CTX_SIZE 58 + +/*! @brief Storage type used to save hash context. */ +typedef struct _dcp_hash_ctx_t +{ + uint32_t x[DCP_HASH_CTX_SIZE]; +} dcp_hash_ctx_t; + +/*! + *@} + */ /* end of dcp_driver_hash */ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup dcp_driver + * @{ + */ + +/*! + * @brief Enables clock to and enables DCP + * + * Enable DCP clock and configure DCP. + * + * @param base DCP base address + * @param config Pointer to configuration structure. + */ +void DCP_Init(DCP_Type *base, const dcp_config_t *config); + +/*! + * @brief Disable DCP clock + * + * Reset DCP and Disable DCP clock. + * + * @param base DCP base address + */ +void DCP_Deinit(DCP_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the DCP configuration structure to a default value. The default + * values are as follows. + * dcpConfig->gatherResidualWrites = true; + * dcpConfig->enableContextCaching = true; + * dcpConfig->enableContextSwitching = true; + * dcpConfig->enableChannnel = kDCP_chEnableAll; + * dcpConfig->enableChannelInterrupt = kDCP_chIntDisable; + * + * @param[out] config Pointer to configuration structure. + */ +void DCP_GetDefaultConfig(dcp_config_t *config); + +/*! + * @brief Poll and wait on DCP channel. + * + * Polls the specified DCP channel until current it completes activity. + * + * @param base DCP peripheral base address. + * @param handle Specifies DCP channel. + * @return kStatus_Success When data processing completes without error. + * @return kStatus_Fail When error occurs. + */ +status_t DCP_WaitForChannelComplete(DCP_Type *base, dcp_handle_t *handle); + +/*! + *@} + */ /* end of dcp_driver */ + +/******************************************************************************* + * AES API + ******************************************************************************/ + +/*! + * @addtogroup dcp_driver_aes + * @{ + */ + +/*! + * @brief Set AES key to dcp_handle_t struct and optionally to DCP. + * + * Sets the AES key for encryption/decryption with the dcp_handle_t structure. + * The dcp_handle_t input argument specifies keySlot. + * If the keySlot is kDCP_OtpKey, the function will check the OTP_KEY_READY bit and will return it's ready to use + * status. + * For other keySlot selections, the function will copy and hold the key in dcp_handle_t struct. + * If the keySlot is one of the four DCP SRAM-based keys (one of kDCP_KeySlot0, kDCP_KeySlot1, kDCP_KeySlot2, + * kDCP_KeySlot3), + * this function will also load the supplied key to the specified keySlot in DCP. + * + * @param base DCP peripheral base address. + * @param handle Handle used for the request. + * @param key 0-mod-4 aligned pointer to AES key. + * @param keySize AES key size in bytes. Shall equal 16. + * @return status from set key operation + */ +status_t DCP_AES_SetKey(DCP_Type *base, dcp_handle_t *handle, const uint8_t *key, size_t keySize); + +/*! + * @brief Encrypts AES on one or multiple 128-bit block(s). + * + * Encrypts AES. + * The source plaintext and destination ciphertext can overlap in system memory. + * + * @param base DCP peripheral base address + * @param handle Handle used for this request. + * @param plaintext Input plain text to encrypt + * @param[out] ciphertext Output cipher text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @return Status from encrypt operation + */ +status_t DCP_AES_EncryptEcb( + DCP_Type *base, dcp_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size); + +/*! + * @brief Decrypts AES on one or multiple 128-bit block(s). + * + * Decrypts AES. + * The source ciphertext and destination plaintext can overlap in system memory. + * + * @param base DCP peripheral base address + * @param handle Handle used for this request. + * @param ciphertext Input plain text to encrypt + * @param[out] plaintext Output cipher text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @return Status from decrypt operation + */ +status_t DCP_AES_DecryptEcb( + DCP_Type *base, dcp_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size); + +/*! + * @brief Encrypts AES using CBC block mode. + * + * Encrypts AES using CBC block mode. + * The source plaintext and destination ciphertext can overlap in system memory. + * + * @param base DCP peripheral base address + * @param handle Handle used for this request. + * @param plaintext Input plain text to encrypt + * @param[out] ciphertext Output cipher text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @param iv Input initial vector to combine with the first input block. + * @return Status from encrypt operation + */ +status_t DCP_AES_EncryptCbc(DCP_Type *base, + dcp_handle_t *handle, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size, + const uint8_t iv[16]); + +/*! + * @brief Decrypts AES using CBC block mode. + * + * Decrypts AES using CBC block mode. + * The source ciphertext and destination plaintext can overlap in system memory. + * + * @param base DCP peripheral base address + * @param handle Handle used for this request. + * @param ciphertext Input cipher text to decrypt + * @param[out] plaintext Output plain text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @param iv Input initial vector to combine with the first input block. + * @return Status from decrypt operation + */ +status_t DCP_AES_DecryptCbc(DCP_Type *base, + dcp_handle_t *handle, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size, + const uint8_t iv[16]); + +/*! + *@} + */ /* end of dcp_driver_aes */ + +/*! + * @addtogroup dcp_nonblocking_driver_aes + * @{ + */ +/*! + * @brief Encrypts AES using the ECB block mode. + * + * Puts AES ECB encrypt work packet to DCP channel. + * + * @param base DCP peripheral base address + * @param handle Handle used for this request. + * @param[out] dcpPacket Memory for the DCP work packet. + * @param plaintext Input plain text to encrypt. + * @param[out] ciphertext Output cipher text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @return kStatus_Success The work packet has been scheduled at DCP channel. + * @return kStatus_DCP_Again The DCP channel is busy processing previous request. + */ +status_t DCP_AES_EncryptEcbNonBlocking(DCP_Type *base, + dcp_handle_t *handle, + dcp_work_packet_t *dcpPacket, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size); + +/*! + * @brief Decrypts AES using ECB block mode. + * + * Puts AES ECB decrypt dcpPacket to DCP input job ring. + * + * @param base DCP peripheral base address + * @param handle Handle used for this request. + * @param[out] dcpPacket Memory for the DCP work packet. + * @param ciphertext Input cipher text to decrypt + * @param[out] plaintext Output plain text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @return kStatus_Success The work packet has been scheduled at DCP channel. + * @return kStatus_DCP_Again The DCP channel is busy processing previous request. + */ +status_t DCP_AES_DecryptEcbNonBlocking(DCP_Type *base, + dcp_handle_t *handle, + dcp_work_packet_t *dcpPacket, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size); + +/*! + * @brief Encrypts AES using CBC block mode. + * + * Puts AES CBC encrypt dcpPacket to DCP input job ring. + * + * @param base DCP peripheral base address + * @param handle Handle used for this request. Specifies jobRing. + * @param[out] dcpPacket Memory for the DCP work packet. + * @param plaintext Input plain text to encrypt + * @param[out] ciphertext Output cipher text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @param iv Input initial vector to combine with the first input block. + * @return kStatus_Success The work packet has been scheduled at DCP channel. + * @return kStatus_DCP_Again The DCP channel is busy processing previous request. + */ +status_t DCP_AES_EncryptCbcNonBlocking(DCP_Type *base, + dcp_handle_t *handle, + dcp_work_packet_t *dcpPacket, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size, + const uint8_t *iv); + +/*! + * @brief Decrypts AES using CBC block mode. + * + * Puts AES CBC decrypt dcpPacket to DCP input job ring. + * + * @param base DCP peripheral base address + * @param handle Handle used for this request. Specifies jobRing. + * @param[out] dcpPacket Memory for the DCP work packet. + * @param ciphertext Input cipher text to decrypt + * @param[out] plaintext Output plain text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @param iv Input initial vector to combine with the first input block. + * @return kStatus_Success The work packet has been scheduled at DCP channel. + * @return kStatus_DCP_Again The DCP channel is busy processing previous request. + */ +status_t DCP_AES_DecryptCbcNonBlocking(DCP_Type *base, + dcp_handle_t *handle, + dcp_work_packet_t *dcpPacket, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size, + const uint8_t *iv); + +/*! + *@} + */ /* end of dcp_nonblocking_driver_aes */ + +/******************************************************************************* + * HASH API + ******************************************************************************/ + +/*! + * @addtogroup dcp_driver_hash + * @{ + */ +/*! + * @brief Initialize HASH context + * + * This function initializes the HASH. + * + * @param base DCP peripheral base address + * @param handle Specifies the DCP channel used for hashing. + * @param[out] ctx Output hash context + * @param algo Underlaying algorithm to use for hash computation. + * @return Status of initialization + */ +status_t DCP_HASH_Init(DCP_Type *base, dcp_handle_t *handle, dcp_hash_ctx_t *ctx, dcp_hash_algo_t algo); + +/*! + * @brief Add data to current HASH + * + * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be + * hashed. The functions blocks. If it returns kStatus_Success, the running hash + * has been updated (DCP has processed the input data), so the memory at @ref input pointer + * can be released back to system. The DCP context buffer is updated with the running hash + * and with all necessary information to support possible context switch. + * + * @param base DCP peripheral base address + * @param[in,out] ctx HASH context + * @param input Input data + * @param inputSize Size of input data in bytes + * @return Status of the hash update operation + */ +status_t DCP_HASH_Update(DCP_Type *base, dcp_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize); + +/*! + * @brief Finalize hashing + * + * Outputs the final hash (computed by DCP_HASH_Update()) and erases the context. + * + * @param[in,out] ctx Input hash context + * @param[out] output Output hash data + * @param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of + * output[] buffer. On function return, it stores the number of updated output bytes. + * @return Status of the hash finish operation + */ +status_t DCP_HASH_Finish(DCP_Type *base, dcp_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize); + +/*! + * @brief Create HASH on given data + * + * Perform the full SHA or CRC32 in one function call. The function is blocking. + * + * @param base DCP peripheral base address + * @param handle Handle used for the request. + * @param algo Underlaying algorithm to use for hash computation. + * @param input Input data + * @param inputSize Size of input data in bytes + * @param[out] output Output hash data + * @param[out] outputSize Output parameter storing the size of the output hash in bytes + * @return Status of the one call hash operation. + */ +status_t DCP_HASH(DCP_Type *base, + dcp_handle_t *handle, + dcp_hash_algo_t algo, + const uint8_t *input, + size_t inputSize, + uint8_t *output, + size_t *outputSize); + +/*! + *@} + */ /* end of dcp_driver_hash */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_DCP_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_dmamux.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_dmamux.c new file mode 100644 index 0000000000..8bfbe6c367 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_dmamux.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_dmamux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dmamux" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for DMAMUX. + * + * @param base DMAMUX peripheral base address. + */ +static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map DMAMUX instance number to base pointer. */ +static DMAMUX_Type *const s_dmamuxBases[] = DMAMUX_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map DMAMUX instance number to clock name. */ +static const clock_ip_name_t s_dmamuxClockName[] = DMAMUX_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t DMAMUX_GetInstance(DMAMUX_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dmamuxBases); instance++) + { + if (s_dmamuxBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_dmamuxBases)); + + return instance; +} + +/*! + * brief Initializes the DMAMUX peripheral. + * + * This function ungates the DMAMUX clock. + * + * param base DMAMUX peripheral base address. + * + */ +void DMAMUX_Init(DMAMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Deinitializes the DMAMUX peripheral. + * + * This function gates the DMAMUX clock. + * + * param base DMAMUX peripheral base address. + */ +void DMAMUX_Deinit(DMAMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_dmamuxClockName[DMAMUX_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_dmamux.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_dmamux.h new file mode 100644 index 0000000000..096bb851bf --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_dmamux.h @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_DMAMUX_H_ +#define _FSL_DMAMUX_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dmamux + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief DMAMUX driver version 2.0.3. */ +#define FSL_DMAMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*@}*/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name DMAMUX Initialization and de-initialization + * @{ + */ + +/*! + * @brief Initializes the DMAMUX peripheral. + * + * This function ungates the DMAMUX clock. + * + * @param base DMAMUX peripheral base address. + * + */ +void DMAMUX_Init(DMAMUX_Type *base); + +/*! + * @brief Deinitializes the DMAMUX peripheral. + * + * This function gates the DMAMUX clock. + * + * @param base DMAMUX peripheral base address. + */ +void DMAMUX_Deinit(DMAMUX_Type *base); + +/* @} */ +/*! + * @name DMAMUX Channel Operation + * @{ + */ + +/*! + * @brief Enables the DMAMUX channel. + * + * This function enables the DMAMUX channel. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_EnableChannel(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK; +} + +/*! + * @brief Disables the DMAMUX channel. + * + * This function disables the DMAMUX channel. + * + * @note The user must disable the DMAMUX channel before configuring it. + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_DisableChannel(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] &= ~(uint8_t)DMAMUX_CHCFG_ENBL_MASK; +} + +/*! + * @brief Configures the DMAMUX channel source. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + * @param source Channel source, which is used to trigger the DMA transfer. + */ +static inline void DMAMUX_SetSource(DMAMUX_Type *base, uint32_t channel, uint32_t source) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] = (uint8_t)((base->CHCFG[channel] & ~DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_SOURCE(source)); +} + +#if defined(FSL_FEATURE_DMAMUX_HAS_TRIG) && FSL_FEATURE_DMAMUX_HAS_TRIG > 0U +/*! + * @brief Enables the DMAMUX period trigger. + * + * This function enables the DMAMUX period trigger feature. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_EnablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] |= DMAMUX_CHCFG_TRIG_MASK; +} + +/*! + * @brief Disables the DMAMUX period trigger. + * + * This function disables the DMAMUX period trigger. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + */ +static inline void DMAMUX_DisablePeriodTrigger(DMAMUX_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CHCFG[channel] &= ~(uint8_t)DMAMUX_CHCFG_TRIG_MASK; +} +#endif /* FSL_FEATURE_DMAMUX_HAS_TRIG */ + +#if (defined(FSL_FEATURE_DMAMUX_HAS_A_ON) && FSL_FEATURE_DMAMUX_HAS_A_ON) +/*! + * @brief Enables the DMA channel to be always ON. + * + * This function enables the DMAMUX channel always ON feature. + * + * @param base DMAMUX peripheral base address. + * @param channel DMAMUX channel number. + * @param enable Switcher of the always ON feature. "true" means enabled, "false" means disabled. + */ +static inline void DMAMUX_EnableAlwaysOn(DMAMUX_Type *base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + if (enable) + { + base->CHCFG[channel] |= DMAMUX_CHCFG_A_ON_MASK; + } + else + { + base->CHCFG[channel] &= ~DMAMUX_CHCFG_A_ON_MASK; + } +} +#endif /* FSL_FEATURE_DMAMUX_HAS_A_ON */ + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /* _FSL_DMAMUX_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_edma.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_edma.c new file mode 100644 index 0000000000..b0456f1d0a --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_edma.c @@ -0,0 +1,2751 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.edma" +#endif + +#define EDMA_TRANSFER_ENABLED_MASK 0x80U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for EDMA. + * + * @param base EDMA peripheral base address. + */ +static uint32_t EDMA_GetInstance(DMA_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map EDMA instance number to base pointer. */ +static DMA_Type *const s_edmaBases[] = DMA_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map EDMA instance number to clock name. */ +static const clock_ip_name_t s_edmaClockName[] = EDMA_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Array to map EDMA instance number to IRQ number. */ +static const IRQn_Type s_edmaIRQNumber[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS; + +/*! @brief Pointers to transfer handle for each EDMA channel. */ +static edma_handle_t *s_EDMAHandle[FSL_FEATURE_EDMA_MODULE_CHANNEL * FSL_FEATURE_SOC_EDMA_COUNT]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t EDMA_GetInstance(DMA_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_edmaBases); instance++) + { + if (s_edmaBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_edmaBases)); + + return instance; +} + +/*! + * brief Push content of TCD structure into hardware TCD register. + * + * param base EDMA peripheral base address. + * param channel EDMA channel number. + * param tcd Point to TCD structure. + */ +void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + /* Push tcd into hardware TCD register */ + base->TCD[channel].SADDR = tcd->SADDR; + base->TCD[channel].SOFF = tcd->SOFF; + base->TCD[channel].ATTR = tcd->ATTR; + base->TCD[channel].NBYTES_MLNO = tcd->NBYTES; + base->TCD[channel].SLAST = tcd->SLAST; + base->TCD[channel].DADDR = tcd->DADDR; + base->TCD[channel].DOFF = tcd->DOFF; + base->TCD[channel].CITER_ELINKNO = tcd->CITER; + base->TCD[channel].DLAST_SGA = tcd->DLAST_SGA; + /* Clear DONE bit first, otherwise ESG cannot be set */ + base->TCD[channel].CSR = 0; + base->TCD[channel].CSR = tcd->CSR; + base->TCD[channel].BITER_ELINKNO = tcd->BITER; +} + +/*! + * brief Initializes the eDMA peripheral. + * + * This function ungates the eDMA clock and configures the eDMA peripheral according + * to the configuration structure. + * + * param base eDMA peripheral base address. + * param config A pointer to the configuration structure, see "edma_config_t". + * note This function enables the minor loop map feature. + */ +void EDMA_Init(DMA_Type *base, const edma_config_t *config) +{ + assert(config != NULL); + + uint32_t tmpreg; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate EDMA peripheral clock */ + CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* clear all the enabled request, status to make sure EDMA status is in normal condition */ + base->ERQ = 0U; + base->INT = 0xFFFFFFFFU; + base->ERR = 0xFFFFFFFFU; + /* Configure EDMA peripheral according to the configuration structure. */ + tmpreg = base->CR; + tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK); + tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) | + DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(1U)); + base->CR = tmpreg; +} + +/*! + * brief Deinitializes the eDMA peripheral. + * + * This function gates the eDMA clock. + * + * param base eDMA peripheral base address. + */ +void EDMA_Deinit(DMA_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate EDMA peripheral clock */ + CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets the eDMA default configuration structure. + * + * This function sets the configuration structure to default values. + * The default configuration is set to the following values. + * code + * config.enableContinuousLinkMode = false; + * config.enableHaltOnError = true; + * config.enableRoundRobinArbitration = false; + * config.enableDebugMode = false; + * endcode + * + * param config A pointer to the eDMA configuration structure. + */ +void EDMA_GetDefaultConfig(edma_config_t *config) +{ + assert(config != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableRoundRobinArbitration = false; + config->enableHaltOnError = true; + config->enableContinuousLinkMode = false; + config->enableDebugMode = false; +} + +/*! + * brief Sets all TCD registers to default values. + * + * This function sets TCD registers for this channel to default values. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * note This function must not be called while the channel transfer is ongoing + * or it causes unpredictable results. + * note This function enables the auto stop request feature. + */ +void EDMA_ResetChannel(DMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + + EDMA_TcdReset((edma_tcd_t *)(uint32_t)&base->TCD[channel]); +} + +/*! + * brief Configures the eDMA transfer attribute. + * + * This function configures the transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the TCD address. + * Example: + * code + * edma_transfer_t config; + * edma_tcd_t tcd; + * config.srcAddr = ..; + * config.destAddr = ..; + * ... + * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd); + * endcode + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param config Pointer to eDMA transfer configuration structure. + * param nextTcd Point to TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * note If nextTcd is not NULL, it means scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the eDMA_ResetChannel. + */ +void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(config != NULL); + assert(((uint32_t)nextTcd & 0x1FU) == 0U); + + EDMA_TcdSetTransferConfig((edma_tcd_t *)(uint32_t)&base->TCD[channel], config, nextTcd); +} + +/*! + * brief Configures the eDMA minor offset feature. + * + * The minor offset means that the signed-extended value is added to the source address or destination + * address after each minor loop. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param config A pointer to the minor offset configuration structure. + */ +void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(config != NULL); + + uint32_t tmpreg; + + tmpreg = base->TCD[channel].NBYTES_MLOFFYES; + tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); + tmpreg |= + (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); + base->TCD[channel].NBYTES_MLOFFYES = tmpreg; +} + +/*! + * brief Configures the eDMA channel preemption feature. + * + * This function configures the channel preemption attribute and the priority of the channel. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number + * param config A pointer to the channel preemption configuration structure. + */ +void EDMA_SetChannelPreemptionConfig(DMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(config != NULL); + + bool tmpEnablePreemptAbility = config->enablePreemptAbility; + bool tmpEnableChannelPreemption = config->enableChannelPreemption; + uint8_t tmpChannelPriority = config->channelPriority; + volatile uint8_t *tmpReg = &base->DCHPRI3; + + tmpReg[DMA_DCHPRI_INDEX(channel)] = + (DMA_DCHPRI0_DPA((true == tmpEnablePreemptAbility ? 0U : 1U)) | + DMA_DCHPRI0_ECP((true == tmpEnableChannelPreemption ? 1U : 0U)) | DMA_DCHPRI0_CHPRI(tmpChannelPriority)); +} + +/*! + * brief Sets the channel link for the eDMA transfer. + * + * This function configures either the minor link or the major link mode. The minor link means that the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param type A channel link type, which can be one of the following: + * arg kEDMA_LinkNone + * arg kEDMA_MinorLink + * arg kEDMA_MajorLink + * param linkedChannel The linked channel number. + * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + */ +void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + + EDMA_TcdSetChannelLink((edma_tcd_t *)(uint32_t)&base->TCD[channel], type, linkedChannel); +} + +/*! + * brief Sets the bandwidth for the eDMA transfer. + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param bandWidth A bandwidth setting, which can be one of the following: + * arg kEDMABandwidthStallNone + * arg kEDMABandwidthStall4Cycle + * arg kEDMABandwidthStall8Cycle + */ +void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + + base->TCD[channel].CSR = (uint16_t)((base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth)); +} + +/*! + * brief Sets the source modulo and the destination modulo for the eDMA transfer. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param srcModulo A source modulo value. + * param destModulo A destination modulo value. + */ +void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint16_t tmpreg; + + tmpreg = base->TCD[channel].ATTR & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); +} + +/*! + * brief Enables the interrupt source for the eDMA transfer. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + + /* Enable error interrupt */ + if (0U != (mask & (uint32_t)kEDMA_ErrorInterruptEnable)) + { + base->EEI |= ((uint32_t)0x1U << channel); + } + + /* Enable Major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) + { + base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK; + } + + /* Enable Half major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) + { + base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK; + } +} + +/*! + * brief Disables the interrupt source for the eDMA transfer. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param mask The mask of the interrupt source to be set. Use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + + /* Disable error interrupt */ + if (0U != (mask & (uint32_t)kEDMA_ErrorInterruptEnable)) + { + base->EEI &= (uint32_t)(~(0x1U << channel)); + } + + /* Disable Major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) + { + base->TCD[channel].CSR &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK; + } + + /* Disable Half major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) + { + base->TCD[channel].CSR &= ~(uint16_t)DMA_CSR_INTHALF_MASK; + } +} + +/*! + * brief Sets all fields to default values for the TCD structure. + * + * This function sets all fields for this TCD structure to default value. + * + * param tcd Pointer to the TCD structure. + * note This function enables the auto stop request feature. + */ +void EDMA_TcdReset(edma_tcd_t *tcd) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + /* Reset channel TCD */ + tcd->SADDR = 0U; + tcd->SOFF = 0U; + tcd->ATTR = 0U; + tcd->NBYTES = 0U; + tcd->SLAST = 0U; + tcd->DADDR = 0U; + tcd->DOFF = 0U; + tcd->CITER = 0U; + tcd->DLAST_SGA = 0U; + /* Enable auto disable request feature */ + tcd->CSR = DMA_CSR_DREQ(true); + tcd->BITER = 0U; +} + +/*! + * brief Configures the eDMA TCD transfer attribute. + * + * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. + * The STCD is used in the scatter-gather mode. + * This function configures the TCD transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the next TCD address. + * Example: + * code + * edma_transfer_t config = { + * ... + * } + * edma_tcd_t tcd __aligned(32); + * edma_tcd_t nextTcd __aligned(32); + * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); + * endcode + * + * param tcd Pointer to the TCD structure. + * param config Pointer to eDMA transfer configuration structure. + * param nextTcd Pointer to the next TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * note TCD address should be 32 bytes aligned or it causes an eDMA error. + * note If the nextTcd is not NULL, the scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the EDMA_TcdReset. + */ +void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + assert(config != NULL); + assert(((uint32_t)nextTcd & 0x1FU) == 0U); + + /* source address */ + tcd->SADDR = config->srcAddr; + /* destination address */ + tcd->DADDR = config->destAddr; + /* Source data and destination data transfer size */ + tcd->ATTR = DMA_ATTR_SSIZE(config->srcTransferSize) | DMA_ATTR_DSIZE(config->destTransferSize); + /* Source address signed offset */ + tcd->SOFF = (uint16_t)config->srcOffset; + /* Destination address signed offset */ + tcd->DOFF = (uint16_t)config->destOffset; + /* Minor byte transfer count */ + tcd->NBYTES = config->minorLoopBytes; + /* Current major iteration count */ + tcd->CITER = (uint16_t)config->majorLoopCounts; + /* Starting major iteration count */ + tcd->BITER = (uint16_t)config->majorLoopCounts; + /* Enable scatter/gather processing */ + if (nextTcd != NULL) + { + tcd->DLAST_SGA = (uint32_t)nextTcd; + /* + Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig, + user must call EDMA_TcdReset or EDMA_ResetChannel which will set + DREQ, so must use "|" or "&" rather than "=". + + Clear the DREQ bit because scatter gather has been enabled, so the + previous transfer is not the last transfer, and channel request should + be enabled at the next transfer(the next TCD). + */ + tcd->CSR = (tcd->CSR | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; + } +} + +/*! + * brief Configures the eDMA TCD minor offset feature. + * + * A minor offset is a signed-extended value added to the source address or a destination + * address after each minor loop. + * + * param tcd A point to the TCD structure. + * param config A pointer to the minor offset configuration structure. + */ +void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + uint32_t tmpreg; + + tmpreg = tcd->NBYTES & + ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); + tmpreg |= + (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); + tcd->NBYTES = tmpreg; +} + +/*! + * brief Sets the channel link for the eDMA TCD. + * + * This function configures either a minor link or a major link. The minor link means the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + * param tcd Point to the TCD structure. + * param type Channel link type, it can be one of: + * arg kEDMA_LinkNone + * arg kEDMA_MinorLink + * arg kEDMA_MajorLink + * param linkedChannel The linked channel number. + */ +void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + + if (type == kEDMA_MinorLink) /* Minor link config */ + { + uint16_t tmpreg; + + /* Enable minor link */ + tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK; + tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK; + /* Set linked channel */ + tmpreg = tcd->CITER & (~(uint16_t)DMA_CITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel); + tcd->CITER = tmpreg; + tmpreg = tcd->BITER & (~(uint16_t)DMA_BITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel); + tcd->BITER = tmpreg; + } + else if (type == kEDMA_MajorLink) /* Major link config */ + { + uint16_t tmpreg; + + /* Enable major link */ + tcd->CSR |= DMA_CSR_MAJORELINK_MASK; + /* Set major linked channel */ + tmpreg = tcd->CSR & (~(uint16_t)DMA_CSR_MAJORLINKCH_MASK); + tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel); + } + else /* Link none */ + { + tcd->CITER &= ~(uint16_t)DMA_CITER_ELINKYES_ELINK_MASK; + tcd->BITER &= ~(uint16_t)DMA_BITER_ELINKYES_ELINK_MASK; + tcd->CSR &= ~(uint16_t)DMA_CSR_MAJORELINK_MASK; + } +} + +/*! + * brief Sets the source modulo and the destination modulo for the eDMA TCD. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * param tcd A pointer to the TCD structure. + * param srcModulo A source modulo value. + * param destModulo A destination modulo value. + */ +void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + uint16_t tmpreg; + + tmpreg = tcd->ATTR & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); +} + +/*! + * brief Enables the interrupt source for the eDMA TCD. + * + * param tcd Point to the TCD structure. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask) +{ + assert(tcd != NULL); + + /* Enable Major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) + { + tcd->CSR |= DMA_CSR_INTMAJOR_MASK; + } + + /* Enable Half major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) + { + tcd->CSR |= DMA_CSR_INTHALF_MASK; + } +} + +/*! + * brief Disables the interrupt source for the eDMA TCD. + * + * param tcd Point to the TCD structure. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) +{ + assert(tcd != NULL); + + /* Disable Major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) + { + tcd->CSR &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK; + } + + /* Disable Half major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) + { + tcd->CSR &= ~(uint16_t)DMA_CSR_INTHALF_MASK; + } +} + +/*! + * brief Gets the remaining major loop count from the eDMA current channel TCD. + * + * This function checks the TCD (Task Control Descriptor) status for a specified + * eDMA channel and returns the number of major loop count that has not finished. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * return Major loop count which has not been transferred yet for the current TCD. + * note 1. This function can only be used to get unfinished major loop count of transfer without + * the next TCD, or it might be inaccuracy. + * 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while + * the channel is running. + * Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO + * register is needed while the eDMA IP does not support getting it while a channel is active. + * In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine + * is working with while a channel is running. + * Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example + * copied before enabling the channel) is needed. The formula to calculate it is shown below: + * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) + */ +uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint32_t remainingCount = 0; + + if (0U != (DMA_CSR_DONE_MASK & base->TCD[channel].CSR)) + { + remainingCount = 0; + } + else + { + /* Calculate the unfinished bytes */ + if (0U != (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK)) + { + remainingCount = (((uint32_t)base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> + DMA_CITER_ELINKYES_CITER_SHIFT); + } + else + { + remainingCount = (((uint32_t)base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> + DMA_CITER_ELINKNO_CITER_SHIFT); + } + } + + return remainingCount; +} + +/*! + * brief Gets the eDMA channel status flags. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * return The mask of channel status flags. Users need to use the + * _edma_channel_status_flags type to decode the return variables. + */ +uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint32_t retval = 0; + + /* Get DONE bit flag */ + retval |= (((uint32_t)base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT); + /* Get ERROR bit flag */ + retval |= ((((uint32_t)base->ERR >> channel) & 0x1U) << 1U); + /* Get INT bit flag */ + retval |= ((((uint32_t)base->INT >> channel) & 0x1U) << 2U); + + return retval; +} + +/*! + * brief Clears the eDMA channel status flags. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param mask The mask of channel status to be cleared. Users need to use + * the defined _edma_channel_status_flags type. + */ +void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + + /* Clear DONE bit flag */ + if (0U != (mask & (uint32_t)kEDMA_DoneFlag)) + { + base->CDNE = (uint8_t)channel; + } + /* Clear ERROR bit flag */ + if (0U != (mask & (uint32_t)kEDMA_ErrorFlag)) + { + base->CERR = (uint8_t)channel; + } + /* Clear INT bit flag */ + if (0U != (mask & (uint32_t)kEDMA_InterruptFlag)) + { + base->CINT = (uint8_t)channel; + } +} + +static uint8_t Get_StartInstance(void) +{ + static uint8_t StartInstanceNum; + +#if defined(DMA0) + StartInstanceNum = (uint8_t)EDMA_GetInstance(DMA0); +#elif defined(DMA1) + StartInstanceNum = EDMA_GetInstance(DMA1); +#elif defined(DMA2) + StartInstanceNum = EDMA_GetInstance(DMA2); +#elif defined(DMA3) + StartInstanceNum = EDMA_GetInstance(DMA3); +#endif + + return StartInstanceNum; +} + +/*! + * brief Creates the eDMA handle. + * + * This function is called if using the transactional API for eDMA. This function + * initializes the internal state of the eDMA handle. + * + * param handle eDMA handle pointer. The eDMA handle stores callback function and + * parameters. + * param base eDMA peripheral base address. + * param channel eDMA channel number. + */ +void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel) +{ + assert(handle != NULL); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + + uint32_t edmaInstance; + uint32_t channelIndex; + uint8_t StartInstance; + edma_tcd_t *tcdRegs; + + /* Zero the handle */ + (void)memset(handle, 0, sizeof(*handle)); + + handle->base = base; + handle->channel = (uint8_t)channel; + /* Get the DMA instance number */ + edmaInstance = EDMA_GetInstance(base); + StartInstance = Get_StartInstance(); + channelIndex = ((edmaInstance - StartInstance) * (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel; + s_EDMAHandle[channelIndex] = handle; + + /* Enable NVIC interrupt */ + (void)EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]); + + /* + Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set), + CSR will be 0. Because in order to suit EDMA busy check mechanism in + EDMA_SubmitTransfer, CSR must be set 0. + */ + tcdRegs = (edma_tcd_t *)(uint32_t)&handle->base->TCD[handle->channel]; + tcdRegs->SADDR = 0; + tcdRegs->SOFF = 0; + tcdRegs->ATTR = 0; + tcdRegs->NBYTES = 0; + tcdRegs->SLAST = 0; + tcdRegs->DADDR = 0; + tcdRegs->DOFF = 0; + tcdRegs->CITER = 0; + tcdRegs->DLAST_SGA = 0; + tcdRegs->CSR = 0; + tcdRegs->BITER = 0; +} + +/*! + * brief Installs the TCDs memory pool into the eDMA handle. + * + * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used + * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block + * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. + * Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer. + * + * param handle eDMA handle pointer. + * param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned. + * param tcdSize The number of TCD slots. + */ +void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize) +{ + assert(handle != NULL); + assert(((uint32_t)tcdPool & 0x1FU) == 0U); + + /* Initialize tcd queue attribute. */ + handle->header = 0; + handle->tail = 0; + handle->tcdUsed = 0; + handle->tcdSize = (int8_t)tcdSize; + handle->flags = 0; + handle->tcdPool = tcdPool; +} + +/*! + * brief Installs a callback function for the eDMA transfer. + * + * This callback is called in the eDMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. This function will be called every time one tcd finished transfer. + * + * param handle eDMA handle pointer. + * param callback eDMA callback function pointer. + * param userData A parameter for the callback function. + */ +void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData) +{ + assert(handle != NULL); + + handle->callback = callback; + handle->userData = userData; +} + +/*! + * brief Prepares the eDMA transfer structure. + * + * This function prepares the transfer configuration structure according to the user input. + * + * param config The user configuration structure of type edma_transfer_t. + * param srcAddr eDMA transfer source address. + * param srcWidth eDMA transfer source address width(bytes). + * param destAddr eDMA transfer destination address. + * param destWidth eDMA transfer destination address width(bytes). + * param bytesEachRequest eDMA transfer bytes per channel request. + * param transferBytes eDMA transfer bytes to be transferred. + * param type eDMA transfer type. + * note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ +void EDMA_PrepareTransfer(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + void *destAddr, + uint32_t destWidth, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_transfer_type_t type) +{ + assert(config != NULL); + assert(srcAddr != NULL); + assert(destAddr != NULL); + assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 8U) || (srcWidth == 16U) || + (srcWidth == 32U)); + assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 8U) || (destWidth == 16U) || + (destWidth == 32U)); + assert((transferBytes % bytesEachRequest) == 0U); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->destAddr = (uint32_t)(uint32_t *)destAddr; + config->srcAddr = (uint32_t)(uint32_t *)srcAddr; + config->minorLoopBytes = bytesEachRequest; + config->majorLoopCounts = transferBytes / bytesEachRequest; + switch (srcWidth) + { + case 1U: + config->srcTransferSize = kEDMA_TransferSize1Bytes; + break; + case 2U: + config->srcTransferSize = kEDMA_TransferSize2Bytes; + break; + case 4U: + config->srcTransferSize = kEDMA_TransferSize4Bytes; + break; +#if (defined(FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) + case 8U: + config->srcTransferSize = kEDMA_TransferSize8Bytes; + break; +#endif +#if (defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) + case 16U: + config->srcTransferSize = kEDMA_TransferSize16Bytes; + break; +#endif + case 32U: + config->srcTransferSize = kEDMA_TransferSize32Bytes; + break; + default: + /* All the cases have been listed above, the default clause should not be reached. */ + assert(false); + break; + } + switch (destWidth) + { + case 1U: + config->destTransferSize = kEDMA_TransferSize1Bytes; + break; + case 2U: + config->destTransferSize = kEDMA_TransferSize2Bytes; + break; + case 4U: + config->destTransferSize = kEDMA_TransferSize4Bytes; + break; +#if (defined(FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) + case 8U: + config->destTransferSize = kEDMA_TransferSize8Bytes; + break; +#endif +#if (defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) + case 16U: + config->destTransferSize = kEDMA_TransferSize16Bytes; + break; +#endif + case 32U: + config->destTransferSize = kEDMA_TransferSize32Bytes; + break; + default: + /* All the cases have been listed above, the default clause should not be reached. */ + assert(false); + break; + } + switch (type) + { + case kEDMA_MemoryToMemory: + config->destOffset = (int16_t)destWidth; + config->srcOffset = (int16_t)srcWidth; + break; + case kEDMA_MemoryToPeripheral: + config->destOffset = 0; + config->srcOffset = (int16_t)srcWidth; + break; + case kEDMA_PeripheralToMemory: + config->destOffset = (int16_t)destWidth; + config->srcOffset = 0; + break; + default: + /* All the cases have been listed above, the default clause should not be reached. */ + assert(false); + break; + } +} + +/*! + * brief Submits the eDMA transfer request. + * + * This function submits the eDMA transfer request according to the transfer configuration structure. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. + * + * param handle eDMA handle pointer. + * param config Pointer to eDMA transfer configuration structure. + * retval kStatus_EDMA_Success It means submit transfer request succeed. + * retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config) +{ + assert(handle != NULL); + assert(config != NULL); + uint32_t tmpCSR = 0; + + edma_tcd_t *tcdRegs = (edma_tcd_t *)(uint32_t)&handle->base->TCD[handle->channel]; + + if (handle->tcdPool == NULL) + { + /* + Check if EDMA is busy: if the given channel started transfer, CSR will be not zero. Because + if it is the last transfer, DREQ will be set. If not, ESG will be set. So in order to suit + this check mechanism, EDMA_CreatHandle will clear CSR register. + */ + tmpCSR = tcdRegs->CSR; + if ((tmpCSR != 0U) && ((tmpCSR & DMA_CSR_DONE_MASK) == 0U)) + { + return kStatus_EDMA_Busy; + } + else + { + EDMA_SetTransferConfig(handle->base, handle->channel, config, NULL); + /* Enable auto disable request feature */ + handle->base->TCD[handle->channel].CSR |= DMA_CSR_DREQ_MASK; + /* Enable major interrupt */ + handle->base->TCD[handle->channel].CSR |= DMA_CSR_INTMAJOR_MASK; + + return kStatus_Success; + } + } + else /* Use the TCD queue. */ + { + uint32_t primask; + uint16_t csr; + int8_t currentTcd; + int8_t previousTcd; + int8_t nextTcd; + int8_t tmpTcdUsed; + int8_t tmpTcdSize; + + /* Check if tcd pool is full. */ + primask = DisableGlobalIRQ(); + tmpTcdUsed = handle->tcdUsed; + tmpTcdSize = handle->tcdSize; + if (tmpTcdUsed >= tmpTcdSize) + { + EnableGlobalIRQ(primask); + + return kStatus_EDMA_QueueFull; + } + currentTcd = handle->tail; + handle->tcdUsed++; + /* Calculate index of next TCD */ + nextTcd = currentTcd + 1; + if (nextTcd == handle->tcdSize) + { + nextTcd = 0; + } + /* Advance queue tail index */ + handle->tail = nextTcd; + EnableGlobalIRQ(primask); + /* Calculate index of previous TCD */ + previousTcd = currentTcd != 0 ? currentTcd - 1 : (handle->tcdSize - 1); + /* Configure current TCD block. */ + EDMA_TcdReset(&handle->tcdPool[currentTcd]); + EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL); + /* Enable major interrupt */ + handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK; + /* Link current TCD with next TCD for identification of current TCD */ + handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd]; + /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ + if (currentTcd != previousTcd) + { + /* Enable scatter/gather feature in the previous TCD block. */ + csr = (uint16_t)((handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK); + handle->tcdPool[previousTcd].CSR = csr; + /* + Check if the TCD block in the registers is the previous one (points to current TCD block). It + is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to + link the TCD register in case link the current TCD with the dead chain when TCD loading occurs + before link the previous TCD block. + */ + if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd]) + { + /* Clear the DREQ bits for the dynamic scatter gather */ + tcdRegs->CSR |= DMA_CSR_DREQ_MASK; + /* Enable scatter/gather also in the TCD registers. */ + csr = tcdRegs->CSR | DMA_CSR_ESG_MASK; + /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ + tcdRegs->CSR = csr; + /* + It is very important to check the ESG bit! + Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can + be used to check if the dynamic TCD link operation is successful. If ESG bit is not set + and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and + the current TCD block has been loaded into TCD registers), it means transfer finished + and TCD link operation fail, so must install TCD content into TCD registers and enable + transfer again. And if ESG is set, it means transfer has not finished, so TCD dynamic + link succeed. + */ + if (0U != (tcdRegs->CSR & DMA_CSR_ESG_MASK)) + { + tcdRegs->CSR &= ~(uint16_t)DMA_CSR_DREQ_MASK; + return kStatus_Success; + } + /* + Check whether the current TCD block is already loaded in the TCD registers. It is another + condition when ESG bit is not set: it means the dynamic TCD link succeed and the current + TCD block has been loaded into TCD registers. + */ + if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd]) + { + return kStatus_Success; + } + /* + If go to this, means the previous transfer finished, and the DONE bit is set. + So shall configure TCD registers. + */ + } + else if (tcdRegs->DLAST_SGA != 0U) + { + /* The current TCD block has been linked successfully. */ + return kStatus_Success; + } + else + { + /* + DLAST_SGA is 0 and it means the first submit transfer, so shall configure + TCD registers. + */ + } + } + /* There is no live chain, TCD block need to be installed in TCD registers. */ + EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); + /* Enable channel request again. */ + if (0U != (handle->flags & EDMA_TRANSFER_ENABLED_MASK)) + { + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + + return kStatus_Success; + } +} + +/*! + * brief eDMA starts transfer. + * + * This function enables the channel request. Users can call this function after submitting the transfer request + * or before submitting the transfer request. + * + * param handle eDMA handle pointer. + */ +void EDMA_StartTransfer(edma_handle_t *handle) +{ + assert(handle != NULL); + uint32_t tmpCSR = 0; + + if (handle->tcdPool == NULL) + { + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + else /* Use the TCD queue. */ + { + uint32_t primask; + edma_tcd_t *tcdRegs = (edma_tcd_t *)(uint32_t)&handle->base->TCD[handle->channel]; + + handle->flags |= EDMA_TRANSFER_ENABLED_MASK; + + /* Check if there was at least one descriptor submitted since reset (TCD in registers is valid) */ + if (tcdRegs->DLAST_SGA != 0U) + { + primask = DisableGlobalIRQ(); + /* Check if channel request is actually disable. */ + if ((handle->base->ERQ & ((uint32_t)1U << handle->channel)) == 0U) + { + /* Check if transfer is paused. */ + tmpCSR = tcdRegs->CSR; + if ((0U == (tmpCSR & DMA_CSR_DONE_MASK)) || (0U != (tmpCSR & DMA_CSR_ESG_MASK))) + { + /* + Re-enable channel request must be as soon as possible, so must put it into + critical section to avoid task switching or interrupt service routine. + */ + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + } + EnableGlobalIRQ(primask); + } + } +} + +/*! + * brief eDMA stops transfer. + * + * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() + * again to resume the transfer. + * + * param handle eDMA handle pointer. + */ +void EDMA_StopTransfer(edma_handle_t *handle) +{ + assert(handle != NULL); + + handle->flags &= (~(uint8_t)EDMA_TRANSFER_ENABLED_MASK); + handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); +} + +/*! + * brief eDMA aborts transfer. + * + * This function disables the channel request and clear transfer status bits. + * Users can submit another transfer after calling this API. + * + * param handle DMA handle pointer. + */ +void EDMA_AbortTransfer(edma_handle_t *handle) +{ + handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); + /* + Clear CSR to release channel. Because if the given channel started transfer, + CSR will be not zero. Because if it is the last transfer, DREQ will be set. + If not, ESG will be set. + */ + handle->base->TCD[handle->channel].CSR = 0; + /* Cancel all next TCD transfer. */ + handle->base->TCD[handle->channel].DLAST_SGA = 0; + + /* Handle the tcd */ + if (handle->tcdPool != NULL) + { + handle->header = 0; + handle->tail = 0; + handle->tcdUsed = 0; + } +} + +/*! + * brief eDMA IRQ handler for the current major loop transfer completion. + * + * This function clears the channel major interrupt flag and calls + * the callback function if it is not NULL. + * + * Note: + * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. + * These include the final address adjustments and reloading of the BITER field into the CITER. + * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from + * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled). + * + * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. + * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index + * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be + * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have + * been loaded into the eDMA engine at this point already.). + * + * For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not + * load a new TCD) from the memory pool to the eDMA engine when major loop completes. + * Therefore, ensure that the header and tcdUsed updated are identical for them. + * tcdUsed are both 0 in this case as no TCD to be loaded. + * + * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for + * further details. + * + * param handle eDMA handle pointer. + */ +void EDMA_HandleIRQ(edma_handle_t *handle) +{ + assert(handle != NULL); + + bool transfer_done; + + /* Clear EDMA interrupt flag */ + handle->base->CINT = handle->channel; + /* Check if transfer is already finished. */ + transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0U); + + if (handle->tcdPool == NULL) + { + if (handle->callback != NULL) + { + (handle->callback)(handle, handle->userData, transfer_done, 0); + } + } + else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */ + { + uint32_t sga = handle->base->TCD[handle->channel].DLAST_SGA; + uint32_t sga_index; + int32_t tcds_done; + uint8_t new_header; + + /* Get the offset of the next transfer TCD blocks to be loaded into the eDMA engine. */ + sga -= (uint32_t)handle->tcdPool; + /* Get the index of the next transfer TCD blocks to be loaded into the eDMA engine. */ + sga_index = sga / sizeof(edma_tcd_t); + /* Adjust header positions. */ + if (transfer_done) + { + /* New header shall point to the next TCD to be loaded (current one is already finished) */ + new_header = (uint8_t)sga_index; + } + else + { + /* New header shall point to this descriptor currently loaded (not finished yet) */ + new_header = sga_index != 0U ? (uint8_t)sga_index - 1U : (uint8_t)handle->tcdSize - 1U; + } + /* Calculate the number of finished TCDs */ + if (new_header == (uint8_t)handle->header) + { + int8_t tmpTcdUsed = handle->tcdUsed; + int8_t tmpTcdSize = handle->tcdSize; + + if (tmpTcdUsed == tmpTcdSize) + { + tcds_done = handle->tcdUsed; + } + else + { + /* No TCD in the memory are going to be loaded or internal error occurs. */ + tcds_done = 0; + } + } + else + { + tcds_done = (uint32_t)new_header - (uint32_t)handle->header; + if (tcds_done < 0) + { + tcds_done += handle->tcdSize; + } + } + /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */ + handle->header = (int8_t)new_header; + /* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */ + handle->tcdUsed -= (int8_t)tcds_done; + /* Invoke callback function. */ + if (NULL != handle->callback) + { + (handle->callback)(handle, handle->userData, transfer_done, tcds_done); + } + + /* clear the DONE bit here is meaningful for below cases: + *1.A new TCD has been loaded to EDMA already: + * need to clear the DONE bit in the IRQ handler to avoid TCD in EDMA been overwritten + * if peripheral request isn't coming before next transfer request. + *2.A new TCD has not been loaded to EDMA: + * for the case that transfer request occur in the privious edma callback, this is a case that doesn't + * need scatter gather, so keep DONE bit during the next transfer request will re-install the TCD. + */ + if (transfer_done) + { + handle->base->CDNE = handle->channel; + } + } +} + +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET) && \ + (FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET == 4) +/* 8 channels (Shared): kl28 */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL == 8U) + +#if defined(DMA0) +void DMA0_04_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[0]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[4]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_15_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[1]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[5]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_26_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[2]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[6]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_37_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[3]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[7]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(DMA1) + +#if defined(DMA0) +void DMA1_04_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[8]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[12]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_15_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[9]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[13]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_26_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[10]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[14]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_37_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[11]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[15]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#else +void DMA1_04_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[0]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[4]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_15_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[1]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[5]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_26_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[2]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[6]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_37_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[3]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[7]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif +#endif /* 8 channels (Shared) */ +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET */ + +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET) && \ + (FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET == 8) +/* 16 channels (Shared): K32H844P */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL == 16U) + +void DMA0_08_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[0]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[8]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_19_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[1]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[9]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_210_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[2]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[10]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_311_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[3]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[11]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_412_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[4]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[12]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_513_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[5]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[13]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_614_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[6]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[14]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_715_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[7]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[15]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#if defined(DMA1) +void DMA1_08_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[16]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 8U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[24]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_19_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[17]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 9U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[25]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_210_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[18]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 10U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[26]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_311_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[19]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 11U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[27]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_412_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[20]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 12U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[28]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_513_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[21]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 13U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[29]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_614_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[22]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 14U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[30]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_715_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[23]); + } + if ((EDMA_GetChannelStatusFlags(DMA1, 15U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[31]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif /* 16 channels (Shared) */ +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET */ + +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET) && \ + (FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET == 16) +/* 32 channels (Shared): k80 */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U + +void DMA0_DMA16_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[0]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[16]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_DMA17_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[1]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[17]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA2_DMA18_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[2]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[18]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA3_DMA19_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[3]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[19]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA4_DMA20_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[4]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[20]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA5_DMA21_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[5]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[21]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA6_DMA22_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[6]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[22]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA7_DMA23_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[7]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[23]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA8_DMA24_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[8]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[24]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA9_DMA25_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[9]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[25]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA10_DMA26_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[10]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[26]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA11_DMA27_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[11]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[27]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA12_DMA28_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[12]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[28]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA13_DMA29_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[13]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[29]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA14_DMA30_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[14]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[30]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA15_DMA31_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[15]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[31]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* 32 channels (Shared) */ +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET */ + +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET) && \ + (FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET == 4) +/* 32 channels (Shared): MCIMX7U5_M4 */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U) + +void DMA0_0_4_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[0]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[4]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_1_5_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[1]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[5]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_2_6_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[2]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[6]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_3_7_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[3]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[7]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_8_12_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[8]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[12]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_9_13_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[9]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[13]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_10_14_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[10]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[14]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_11_15_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[11]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[15]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_16_20_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[16]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[20]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_17_21_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[17]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[21]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_18_22_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[18]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[22]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_19_23_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[19]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[23]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_24_28_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[24]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[28]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_25_29_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[25]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[29]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_26_30_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[26]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[30]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA0_27_31_DriverIRQHandler(void) +{ + if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[27]); + } + if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[31]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* 32 channels (Shared): MCIMX7U5 */ +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET */ + +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET) && \ + (FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET == 0) +/* 4 channels (No Shared): kv10 */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL > 0) + +void DMA0_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA1_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA2_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[2]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA3_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[3]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +/* 8 channels (No Shared) */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U) + +void DMA4_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[4]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA5_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[5]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA6_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[6]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA7_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[7]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 8 */ + +/* 16 channels (No Shared) */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL > 8U) + +void DMA8_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[8]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA9_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[9]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA10_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[10]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA11_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[11]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA12_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[12]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA13_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[13]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA14_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[14]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA15_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[15]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 16 */ + +/* 32 channels (No Shared) */ +#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && (FSL_FEATURE_EDMA_MODULE_CHANNEL > 16U) + +void DMA16_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[16]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA17_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[17]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA18_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[18]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA19_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[19]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA20_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[20]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA21_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[21]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA22_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[22]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA23_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[23]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA24_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[24]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA25_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[25]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA26_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[26]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA27_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[27]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA28_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[28]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA29_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[29]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA30_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[30]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void DMA31_DriverIRQHandler(void) +{ + EDMA_HandleIRQ(s_EDMAHandle[31]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 32 */ + +#endif /* 4/8/16/32 channels (No Shared) */ +#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_edma.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_edma.h new file mode 100644 index 0000000000..6fe8de688d --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_edma.h @@ -0,0 +1,921 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_EDMA_H_ +#define _FSL_EDMA_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup edma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief eDMA driver version */ +#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 7)) /*!< Version 2.1.7. */ +/*@}*/ + +/*! @brief Compute the offset unit from DCHPRI3 */ +#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3U - ((channel)&0x03U))) + +/*! @brief eDMA transfer configuration */ +typedef enum _edma_transfer_size +{ + kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */ + kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */ + kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */ + kEDMA_TransferSize8Bytes = 0x3U, /*!< Source/Destination data transfer size is 8 bytes every time */ + kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */ + kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */ +} edma_transfer_size_t; + +/*! @brief eDMA modulo configuration */ +typedef enum _edma_modulo +{ + kEDMA_ModuloDisable = 0x0U, /*!< Disable modulo */ + kEDMA_Modulo2bytes, /*!< Circular buffer size is 2 bytes. */ + kEDMA_Modulo4bytes, /*!< Circular buffer size is 4 bytes. */ + kEDMA_Modulo8bytes, /*!< Circular buffer size is 8 bytes. */ + kEDMA_Modulo16bytes, /*!< Circular buffer size is 16 bytes. */ + kEDMA_Modulo32bytes, /*!< Circular buffer size is 32 bytes. */ + kEDMA_Modulo64bytes, /*!< Circular buffer size is 64 bytes. */ + kEDMA_Modulo128bytes, /*!< Circular buffer size is 128 bytes. */ + kEDMA_Modulo256bytes, /*!< Circular buffer size is 256 bytes. */ + kEDMA_Modulo512bytes, /*!< Circular buffer size is 512 bytes. */ + kEDMA_Modulo1Kbytes, /*!< Circular buffer size is 1 K bytes. */ + kEDMA_Modulo2Kbytes, /*!< Circular buffer size is 2 K bytes. */ + kEDMA_Modulo4Kbytes, /*!< Circular buffer size is 4 K bytes. */ + kEDMA_Modulo8Kbytes, /*!< Circular buffer size is 8 K bytes. */ + kEDMA_Modulo16Kbytes, /*!< Circular buffer size is 16 K bytes. */ + kEDMA_Modulo32Kbytes, /*!< Circular buffer size is 32 K bytes. */ + kEDMA_Modulo64Kbytes, /*!< Circular buffer size is 64 K bytes. */ + kEDMA_Modulo128Kbytes, /*!< Circular buffer size is 128 K bytes. */ + kEDMA_Modulo256Kbytes, /*!< Circular buffer size is 256 K bytes. */ + kEDMA_Modulo512Kbytes, /*!< Circular buffer size is 512 K bytes. */ + kEDMA_Modulo1Mbytes, /*!< Circular buffer size is 1 M bytes. */ + kEDMA_Modulo2Mbytes, /*!< Circular buffer size is 2 M bytes. */ + kEDMA_Modulo4Mbytes, /*!< Circular buffer size is 4 M bytes. */ + kEDMA_Modulo8Mbytes, /*!< Circular buffer size is 8 M bytes. */ + kEDMA_Modulo16Mbytes, /*!< Circular buffer size is 16 M bytes. */ + kEDMA_Modulo32Mbytes, /*!< Circular buffer size is 32 M bytes. */ + kEDMA_Modulo64Mbytes, /*!< Circular buffer size is 64 M bytes. */ + kEDMA_Modulo128Mbytes, /*!< Circular buffer size is 128 M bytes. */ + kEDMA_Modulo256Mbytes, /*!< Circular buffer size is 256 M bytes. */ + kEDMA_Modulo512Mbytes, /*!< Circular buffer size is 512 M bytes. */ + kEDMA_Modulo1Gbytes, /*!< Circular buffer size is 1 G bytes. */ + kEDMA_Modulo2Gbytes, /*!< Circular buffer size is 2 G bytes. */ +} edma_modulo_t; + +/*! @brief Bandwidth control */ +typedef enum _edma_bandwidth +{ + kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */ + kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */ + kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */ +} edma_bandwidth_t; + +/*! @brief Channel link type */ +typedef enum _edma_channel_link_type +{ + kEDMA_LinkNone = 0x0U, /*!< No channel link */ + kEDMA_MinorLink, /*!< Channel link after each minor loop */ + kEDMA_MajorLink, /*!< Channel link while major loop count exhausted */ +} edma_channel_link_type_t; + +/*!@brief eDMA channel status flags. */ +enum _edma_channel_status_flags +{ + kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/ + kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */ + kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */ +}; + +/*! @brief eDMA channel error status flags. */ +enum _edma_error_status_flags +{ + kEDMA_DestinationBusErrorFlag = DMA_ES_DBE_MASK, /*!< Bus error on destination address */ + kEDMA_SourceBusErrorFlag = DMA_ES_SBE_MASK, /*!< Bus error on the source address */ + kEDMA_ScatterGatherErrorFlag = DMA_ES_SGE_MASK, /*!< Error on the Scatter/Gather address, not 32byte aligned. */ + kEDMA_NbytesErrorFlag = DMA_ES_NCE_MASK, /*!< NBYTES/CITER configuration error */ + kEDMA_DestinationOffsetErrorFlag = DMA_ES_DOE_MASK, /*!< Destination offset not aligned with destination size */ + kEDMA_DestinationAddressErrorFlag = DMA_ES_DAE_MASK, /*!< Destination address not aligned with destination size */ + kEDMA_SourceOffsetErrorFlag = DMA_ES_SOE_MASK, /*!< Source offset not aligned with source size */ + kEDMA_SourceAddressErrorFlag = DMA_ES_SAE_MASK, /*!< Source address not aligned with source size*/ + kEDMA_ErrorChannelFlag = DMA_ES_ERRCHN_MASK, /*!< Error channel number of the cancelled channel number */ + kEDMA_ChannelPriorityErrorFlag = DMA_ES_CPE_MASK, /*!< Channel priority is not unique. */ + kEDMA_TransferCanceledFlag = DMA_ES_ECX_MASK, /*!< Transfer cancelled */ +#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1) + kEDMA_GroupPriorityErrorFlag = DMA_ES_GPE_MASK, /*!< Group priority is not unique. */ +#endif + kEDMA_ValidFlag = (int)DMA_ES_VLD_MASK, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */ +}; + +/*! @brief eDMA interrupt source */ +typedef enum _edma_interrupt_enable +{ + kEDMA_ErrorInterruptEnable = 0x1U, /*!< Enable interrupt while channel error occurs. */ + kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */ + kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */ +} edma_interrupt_enable_t; + +/*! @brief eDMA transfer type */ +typedef enum _edma_transfer_type +{ + kEDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory */ + kEDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory */ + kEDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral */ +} edma_transfer_type_t; + +/*! @brief eDMA transfer status */ +enum _edma_transfer_status +{ + kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */ + kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the + transfer request. */ +}; + +/*! @brief eDMA global configuration structure.*/ +typedef struct _edma_config +{ + bool enableContinuousLinkMode; /*!< Enable (true) continuous link mode. Upon minor loop completion, the channel + activates again if that channel has a minor loop channel link enabled and + the link channel is itself. */ + bool enableHaltOnError; /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set. + Subsequently, all service requests are ignored until the HALT bit is cleared.*/ + bool enableRoundRobinArbitration; /*!< Enable (true) round robin channel arbitration method or fixed priority + arbitration is used for channel selection */ + bool enableDebugMode; /*!< Enable(true) eDMA debug mode. When in debug mode, the eDMA stalls the start of + a new channel. Executing channels are allowed to complete. */ +} edma_config_t; + +/*! + * @brief eDMA transfer configuration + * + * This structure configures the source/destination transfer attribute. + */ +typedef struct _edma_transfer_config +{ + uint32_t srcAddr; /*!< Source data address. */ + uint32_t destAddr; /*!< Destination data address. */ + edma_transfer_size_t srcTransferSize; /*!< Source data transfer size. */ + edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */ + int16_t srcOffset; /*!< Sign-extended offset applied to the current source address to + form the next-state value as each source read is completed. */ + int16_t destOffset; /*!< Sign-extended offset applied to the current destination address to + form the next-state value as each destination write is completed. */ + uint32_t minorLoopBytes; /*!< Bytes to transfer in a minor loop*/ + uint32_t majorLoopCounts; /*!< Major loop iteration count. */ +} edma_transfer_config_t; + +/*! @brief eDMA channel priority configuration */ +typedef struct _edma_channel_Preemption_config +{ + bool enableChannelPreemption; /*!< If true: a channel can be suspended by other channel with higher priority */ + bool enablePreemptAbility; /*!< If true: a channel can suspend other channel with low priority */ + uint8_t channelPriority; /*!< Channel priority */ +} edma_channel_Preemption_config_t; + +/*! @brief eDMA minor offset configuration */ +typedef struct _edma_minor_offset_config +{ + bool enableSrcMinorOffset; /*!< Enable(true) or Disable(false) source minor loop offset. */ + bool enableDestMinorOffset; /*!< Enable(true) or Disable(false) destination minor loop offset. */ + uint32_t minorOffset; /*!< Offset for a minor loop mapping. */ +} edma_minor_offset_config_t; + +/*! + * @brief eDMA TCD. + * + * This structure is same as TCD register which is described in reference manual, + * and is used to configure the scatter/gather feature as a next hardware TCD. + */ +typedef struct _edma_tcd +{ + __IO uint32_t SADDR; /*!< SADDR register, used to save source address */ + __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */ + __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */ + __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */ + __IO uint32_t SLAST; /*!< SLAST register */ + __IO uint32_t DADDR; /*!< DADDR register, used for destination address */ + __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */ + __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/ + __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */ + __IO uint16_t CSR; /*!< CSR register, for TCD control status */ + __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */ +} edma_tcd_t; + +/*! @brief Callback for eDMA */ +struct _edma_handle; + +/*! @brief Define callback function for eDMA. + * + * This callback function is called in the EDMA interrupt handle. + * In normal mode, run into callback function means the transfer users need is done. + * In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not + * all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber. + * + * @param handle EDMA handle pointer, users shall not touch the values inside. + * @param userData The callback user parameter pointer. Users can use this parameter to involve things users need to + * change in EDMA callback function. + * @param transferDone If the current loaded transfer done. In normal mode it means if all transfer done. In scatter + * gather mode, this parameter shows is the current transfer block in EDMA register is done. As the + * load of core is different, it will be different if the new tcd loaded into EDMA registers while + * this callback called. If true, it always means new tcd still not loaded into registers, while + * false means new tcd already loaded into registers. + * @param tcds How many tcds are done from the last callback. This parameter only used in scatter gather mode. It + * tells user how many tcds are finished between the last callback and this. + */ +typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds); + +/*! @brief eDMA transfer handle structure */ +typedef struct _edma_handle +{ + edma_callback callback; /*!< Callback function for major count exhausted. */ + void *userData; /*!< Callback function parameter. */ + DMA_Type *base; /*!< eDMA peripheral base address. */ + edma_tcd_t *tcdPool; /*!< Pointer to memory stored TCDs. */ + uint8_t channel; /*!< eDMA channel number. */ + volatile int8_t header; /*!< The first TCD index. Should point to the next TCD to be loaded into the eDMA engine. */ + volatile int8_t tail; /*!< The last TCD index. Should point to the next TCD to be stored into the memory pool. */ + volatile int8_t tcdUsed; /*!< The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in + the memory. */ + volatile int8_t tcdSize; /*!< The total number of TCD slots in the queue. */ + uint8_t flags; /*!< The status of the current channel. */ +} edma_handle_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name eDMA initialization and de-initialization + * @{ + */ + +/*! + * @brief Initializes the eDMA peripheral. + * + * This function ungates the eDMA clock and configures the eDMA peripheral according + * to the configuration structure. + * + * @param base eDMA peripheral base address. + * @param config A pointer to the configuration structure, see "edma_config_t". + * @note This function enables the minor loop map feature. + */ +void EDMA_Init(DMA_Type *base, const edma_config_t *config); + +/*! + * @brief Deinitializes the eDMA peripheral. + * + * This function gates the eDMA clock. + * + * @param base eDMA peripheral base address. + */ +void EDMA_Deinit(DMA_Type *base); + +/*! + * @brief Push content of TCD structure into hardware TCD register. + * + * @param base EDMA peripheral base address. + * @param channel EDMA channel number. + * @param tcd Point to TCD structure. + */ +void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd); + +/*! + * @brief Gets the eDMA default configuration structure. + * + * This function sets the configuration structure to default values. + * The default configuration is set to the following values. + * @code + * config.enableContinuousLinkMode = false; + * config.enableHaltOnError = true; + * config.enableRoundRobinArbitration = false; + * config.enableDebugMode = false; + * @endcode + * + * @param config A pointer to the eDMA configuration structure. + */ +void EDMA_GetDefaultConfig(edma_config_t *config); + +/* @} */ +/*! + * @name eDMA Channel Operation + * @{ + */ + +/*! + * @brief Sets all TCD registers to default values. + * + * This function sets TCD registers for this channel to default values. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @note This function must not be called while the channel transfer is ongoing + * or it causes unpredictable results. + * @note This function enables the auto stop request feature. + */ +void EDMA_ResetChannel(DMA_Type *base, uint32_t channel); + +/*! + * @brief Configures the eDMA transfer attribute. + * + * This function configures the transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the TCD address. + * Example: + * @code + * edma_transfer_t config; + * edma_tcd_t tcd; + * config.srcAddr = ..; + * config.destAddr = ..; + * ... + * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd); + * @endcode + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param config Pointer to eDMA transfer configuration structure. + * @param nextTcd Point to TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * @note If nextTcd is not NULL, it means scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the eDMA_ResetChannel. + */ +void EDMA_SetTransferConfig(DMA_Type *base, + uint32_t channel, + const edma_transfer_config_t *config, + edma_tcd_t *nextTcd); + +/*! + * @brief Configures the eDMA minor offset feature. + * + * The minor offset means that the signed-extended value is added to the source address or destination + * address after each minor loop. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param config A pointer to the minor offset configuration structure. + */ +void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config); + +/*! + * @brief Configures the eDMA channel preemption feature. + * + * This function configures the channel preemption attribute and the priority of the channel. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number + * @param config A pointer to the channel preemption configuration structure. + */ +void EDMA_SetChannelPreemptionConfig(DMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config); + +/*! + * @brief Sets the channel link for the eDMA transfer. + * + * This function configures either the minor link or the major link mode. The minor link means that the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param type A channel link type, which can be one of the following: + * @arg kEDMA_LinkNone + * @arg kEDMA_MinorLink + * @arg kEDMA_MajorLink + * @param linkedChannel The linked channel number. + * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + */ +void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel); + +/*! + * @brief Sets the bandwidth for the eDMA transfer. + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param bandWidth A bandwidth setting, which can be one of the following: + * @arg kEDMABandwidthStallNone + * @arg kEDMABandwidthStall4Cycle + * @arg kEDMABandwidthStall8Cycle + */ +void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth); + +/*! + * @brief Sets the source modulo and the destination modulo for the eDMA transfer. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param srcModulo A source modulo value. + * @param destModulo A destination modulo value. + */ +void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo); + +#if defined(FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT) && FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT +/*! + * @brief Enables an async request for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_EnableAsyncRequest(DMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->EARS = (base->EARS & (uint32_t)(~(1U << channel))) | ((true == enable ? 1U : 0U) << channel); +} +#endif /* FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT */ + +/*! + * @brief Enables an auto stop request for the eDMA transfer. + * + * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_EnableAutoStopRequest(DMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->TCD[channel].CSR = + (uint16_t)((base->TCD[channel].CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ((true == enable ? 1U : 0U))); +} + +/*! + * @brief Enables the interrupt source for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask); + +/*! + * @brief Disables the interrupt source for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of the interrupt source to be set. Use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask); + +/* @} */ +/*! + * @name eDMA TCD Operation + * @{ + */ + +/*! + * @brief Sets all fields to default values for the TCD structure. + * + * This function sets all fields for this TCD structure to default value. + * + * @param tcd Pointer to the TCD structure. + * @note This function enables the auto stop request feature. + */ +void EDMA_TcdReset(edma_tcd_t *tcd); + +/*! + * @brief Configures the eDMA TCD transfer attribute. + * + * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. + * The STCD is used in the scatter-gather mode. + * This function configures the TCD transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the next TCD address. + * Example: + * @code + * edma_transfer_t config = { + * ... + * } + * edma_tcd_t tcd __aligned(32); + * edma_tcd_t nextTcd __aligned(32); + * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); + * @endcode + * + * @param tcd Pointer to the TCD structure. + * @param config Pointer to eDMA transfer configuration structure. + * @param nextTcd Pointer to the next TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * @note TCD address should be 32 bytes aligned or it causes an eDMA error. + * @note If the nextTcd is not NULL, the scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the EDMA_TcdReset. + */ +void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd); + +/*! + * @brief Configures the eDMA TCD minor offset feature. + * + * A minor offset is a signed-extended value added to the source address or a destination + * address after each minor loop. + * + * @param tcd A point to the TCD structure. + * @param config A pointer to the minor offset configuration structure. + */ +void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config); + +/*! + * @brief Sets the channel link for the eDMA TCD. + * + * This function configures either a minor link or a major link. The minor link means the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + * @param tcd Point to the TCD structure. + * @param type Channel link type, it can be one of: + * @arg kEDMA_LinkNone + * @arg kEDMA_MinorLink + * @arg kEDMA_MajorLink + * @param linkedChannel The linked channel number. + */ +void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel); + +/*! + * @brief Sets the bandwidth for the eDMA TCD. + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * @param tcd A pointer to the TCD structure. + * @param bandWidth A bandwidth setting, which can be one of the following: + * @arg kEDMABandwidthStallNone + * @arg kEDMABandwidthStall4Cycle + * @arg kEDMABandwidthStall8Cycle + */ +static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + tcd->CSR = (uint16_t)((tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth)); +} + +/*! + * @brief Sets the source modulo and the destination modulo for the eDMA TCD. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * @param tcd A pointer to the TCD structure. + * @param srcModulo A source modulo value. + * @param destModulo A destination modulo value. + */ +void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo); + +/*! + * @brief Sets the auto stop request for the eDMA TCD. + * + * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. + * + * @param tcd A pointer to the TCD structure. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + tcd->CSR = (uint16_t)((tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ((true == enable ? 1U : 0U))); +} + +/*! + * @brief Enables the interrupt source for the eDMA TCD. + * + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask); + +/*! + * @brief Disables the interrupt source for the eDMA TCD. + * + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask); + +/*! @} */ +/*! + * @name eDMA Channel Transfer Operation + * @{ + */ + +/*! + * @brief Enables the eDMA hardware channel request. + * + * This function enables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_EnableChannelRequest(DMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->SERQ = DMA_SERQ_SERQ(channel); +} + +/*! + * @brief Disables the eDMA hardware channel request. + * + * This function disables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_DisableChannelRequest(DMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->CERQ = DMA_CERQ_CERQ(channel); +} + +/*! + * @brief Starts the eDMA transfer by using the software trigger. + * + * This function starts a minor loop transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + + base->SSRT = DMA_SSRT_SSRT(channel); +} + +/*! @} */ +/*! + * @name eDMA Channel Status Operation + * @{ + */ + +/*! + * @brief Gets the remaining major loop count from the eDMA current channel TCD. + * + * This function checks the TCD (Task Control Descriptor) status for a specified + * eDMA channel and returns the number of major loop count that has not finished. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @return Major loop count which has not been transferred yet for the current TCD. + * @note 1. This function can only be used to get unfinished major loop count of transfer without + * the next TCD, or it might be inaccuracy. + * 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while + * the channel is running. + * Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO + * register is needed while the eDMA IP does not support getting it while a channel is active. + * In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine + * is working with while a channel is running. + * Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example + * copied before enabling the channel) is needed. The formula to calculate it is shown below: + * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) + */ +uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel); + +/*! + * @brief Gets the eDMA channel error status flags. + * + * @param base eDMA peripheral base address. + * @return The mask of error status flags. Users need to use the + * _edma_error_status_flags type to decode the return variables. + */ +static inline uint32_t EDMA_GetErrorStatusFlags(DMA_Type *base) +{ + return base->ES; +} + +/*! + * @brief Gets the eDMA channel status flags. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @return The mask of channel status flags. Users need to use the + * _edma_channel_status_flags type to decode the return variables. + */ +uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel); + +/*! + * @brief Clears the eDMA channel status flags. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of channel status to be cleared. Users need to use + * the defined _edma_channel_status_flags type. + */ +void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask); + +/*! @} */ +/*! + * @name eDMA Transactional Operation + */ + +/*! + * @brief Creates the eDMA handle. + * + * This function is called if using the transactional API for eDMA. This function + * initializes the internal state of the eDMA handle. + * + * @param handle eDMA handle pointer. The eDMA handle stores callback function and + * parameters. + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel); + +/*! + * @brief Installs the TCDs memory pool into the eDMA handle. + * + * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used + * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block + * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. + * Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer. + * + * @param handle eDMA handle pointer. + * @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned. + * @param tcdSize The number of TCD slots. + */ +void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize); + +/*! + * @brief Installs a callback function for the eDMA transfer. + * + * This callback is called in the eDMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. This function will be called every time one tcd finished transfer. + * + * @param handle eDMA handle pointer. + * @param callback eDMA callback function pointer. + * @param userData A parameter for the callback function. + */ +void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData); + +/*! + * @brief Prepares the eDMA transfer structure. + * + * This function prepares the transfer configuration structure according to the user input. + * + * @param config The user configuration structure of type edma_transfer_t. + * @param srcAddr eDMA transfer source address. + * @param srcWidth eDMA transfer source address width(bytes). + * @param destAddr eDMA transfer destination address. + * @param destWidth eDMA transfer destination address width(bytes). + * @param bytesEachRequest eDMA transfer bytes per channel request. + * @param transferBytes eDMA transfer bytes to be transferred. + * @param type eDMA transfer type. + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ +void EDMA_PrepareTransfer(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + void *destAddr, + uint32_t destWidth, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_transfer_type_t type); + +/*! + * @brief Submits the eDMA transfer request. + * + * This function submits the eDMA transfer request according to the transfer configuration structure. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. + * + * @param handle eDMA handle pointer. + * @param config Pointer to eDMA transfer configuration structure. + * @retval kStatus_EDMA_Success It means submit transfer request succeed. + * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config); + +/*! + * @brief eDMA starts transfer. + * + * This function enables the channel request. Users can call this function after submitting the transfer request + * or before submitting the transfer request. + * + * @param handle eDMA handle pointer. + */ +void EDMA_StartTransfer(edma_handle_t *handle); + +/*! + * @brief eDMA stops transfer. + * + * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() + * again to resume the transfer. + * + * @param handle eDMA handle pointer. + */ +void EDMA_StopTransfer(edma_handle_t *handle); + +/*! + * @brief eDMA aborts transfer. + * + * This function disables the channel request and clear transfer status bits. + * Users can submit another transfer after calling this API. + * + * @param handle DMA handle pointer. + */ +void EDMA_AbortTransfer(edma_handle_t *handle); + +/*! + * @brief Get unused TCD slot number. + * + * This function gets current tcd index which is run. If the TCD pool pointer is NULL, it will return 0. + * + * @param handle DMA handle pointer. + * @return The unused tcd slot number. + */ +static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle) +{ + int8_t tmpTcdSize = handle->tcdSize; + int8_t tmpTcdUsed = handle->tcdUsed; + return ((uint32_t)tmpTcdSize - (uint32_t)tmpTcdUsed); +} + +/*! + * @brief Get the next tcd address. + * + * This function gets the next tcd address. If this is last TCD, return 0. + * + * @param handle DMA handle pointer. + * @return The next TCD address. + */ +static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle) +{ + return (handle->base->TCD[handle->channel].DLAST_SGA); +} + +/*! + * @brief eDMA IRQ handler for the current major loop transfer completion. + * + * This function clears the channel major interrupt flag and calls + * the callback function if it is not NULL. + * + * Note: + * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. + * These include the final address adjustments and reloading of the BITER field into the CITER. + * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from + * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled). + * + * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. + * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index + * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be + * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have + * been loaded into the eDMA engine at this point already.). + * + * For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not + * load a new TCD) from the memory pool to the eDMA engine when major loop completes. + * Therefore, ensure that the header and tcdUsed updated are identical for them. + * tcdUsed are both 0 in this case as no TCD to be loaded. + * + * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for + * further details. + * + * @param handle eDMA handle pointer. + */ +void EDMA_HandleIRQ(edma_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/* @} */ + +#endif /*_FSL_EDMA_H_*/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_enc.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_enc.c new file mode 100644 index 0000000000..0c90627759 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_enc.c @@ -0,0 +1,590 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_enc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.enc" +#endif + +#define ENC_CTRL_W1C_FLAGS (ENC_CTRL_HIRQ_MASK | ENC_CTRL_XIRQ_MASK | ENC_CTRL_DIRQ_MASK | ENC_CTRL_CMPIRQ_MASK) +#define ENC_CTRL2_W1C_FLAGS (ENC_CTRL2_SABIRQ_MASK | ENC_CTRL2_ROIRQ_MASK | ENC_CTRL2_RUIRQ_MASK) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for ENC module. + * + * @param base ENC peripheral base address + */ +static uint32_t ENC_GetInstance(ENC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to ENC bases for each instance. */ +static ENC_Type *const s_encBases[] = ENC_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to ENC clocks for each instance. */ +static const clock_ip_name_t s_encClocks[] = ENC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t ENC_GetInstance(ENC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_encBases); instance++) + { + if (s_encBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_encBases)); + + return instance; +} + +/*! + * brief Initialization for the ENC module. + * + * This function is to make the initialization for the ENC module. It should be called firstly before any operation to + * the ENC with the operations like: + * - Enable the clock for ENC module. + * - Configure the ENC's working attributes. + * + * param base ENC peripheral base address. + * param config Pointer to configuration structure. See to "enc_config_t". + */ +void ENC_Init(ENC_Type *base, const enc_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp16; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_encClocks[ENC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* ENC_CTRL. */ + tmp16 = base->CTRL & (uint16_t)(~(ENC_CTRL_W1C_FLAGS | ENC_CTRL_HIP_MASK | ENC_CTRL_HNE_MASK | ENC_CTRL_REV_MASK | + ENC_CTRL_PH1_MASK | ENC_CTRL_XIP_MASK | ENC_CTRL_XNE_MASK | ENC_CTRL_WDE_MASK)); + /* For HOME trigger. */ + if (kENC_HOMETriggerDisabled != config->HOMETriggerMode) + { + tmp16 |= ENC_CTRL_HIP_MASK; + if (kENC_HOMETriggerOnFallingEdge == config->HOMETriggerMode) + { + tmp16 |= ENC_CTRL_HNE_MASK; + } + } + /* For encoder work mode. */ + if (config->enableReverseDirection) + { + tmp16 |= ENC_CTRL_REV_MASK; + } + if (kENC_DecoderWorkAsSignalPhaseCountMode == config->decoderWorkMode) + { + tmp16 |= ENC_CTRL_PH1_MASK; + } + /* For INDEX trigger. */ + if (kENC_INDEXTriggerDisabled != config->INDEXTriggerMode) + { + tmp16 |= ENC_CTRL_XIP_MASK; + if (kENC_INDEXTriggerOnFallingEdge == config->INDEXTriggerMode) + { + tmp16 |= ENC_CTRL_XNE_MASK; + } + } + /* Watchdog. */ + if (config->enableWatchdog) + { + tmp16 |= ENC_CTRL_WDE_MASK; + base->WTR = config->watchdogTimeoutValue; /* WDOG can be only available when the feature is enabled. */ + } + base->CTRL = tmp16; + + /* ENC_FILT. */ + base->FILT = ENC_FILT_FILT_CNT(config->filterCount) | ENC_FILT_FILT_PER(config->filterSamplePeriod); + + /* ENC_CTRL2. */ + tmp16 = base->CTRL2 & (uint16_t)(~(ENC_CTRL2_W1C_FLAGS | ENC_CTRL2_OUTCTL_MASK | ENC_CTRL2_REVMOD_MASK | + ENC_CTRL2_MOD_MASK | ENC_CTRL2_UPDPOS_MASK | ENC_CTRL2_UPDHLD_MASK)); + if (kENC_POSMATCHOnReadingAnyPositionCounter == config->positionMatchMode) + { + tmp16 |= ENC_CTRL2_OUTCTL_MASK; + } + if (kENC_RevolutionCountOnRollOverModulus == config->revolutionCountCondition) + { + tmp16 |= ENC_CTRL2_REVMOD_MASK; + } + if (config->enableModuloCountMode) + { + tmp16 |= ENC_CTRL2_MOD_MASK; + /* Set modulus value. */ + base->UMOD = (uint16_t)(config->positionModulusValue >> 16U); /* Upper 16 bits. */ + base->LMOD = (uint16_t)(config->positionModulusValue); /* Lower 16 bits. */ + } + if (config->enableTRIGGERClearPositionCounter) + { + tmp16 |= ENC_CTRL2_UPDPOS_MASK; + } + if (config->enableTRIGGERClearHoldPositionCounter) + { + tmp16 |= ENC_CTRL2_UPDHLD_MASK; + } + base->CTRL2 = tmp16; + + /* ENC_UCOMP & ENC_LCOMP. */ + base->UCOMP = (uint16_t)(config->positionCompareValue >> 16U); /* Upper 16 bits. */ + base->LCOMP = (uint16_t)(config->positionCompareValue); /* Lower 16 bits. */ + + /* ENC_UINIT & ENC_LINIT. */ + base->UINIT = (uint16_t)(config->positionInitialValue >> 16U); /* Upper 16 bits. */ + base->LINIT = (uint16_t)(config->positionInitialValue); /* Lower 16 bits. */ +} + +/*! + * brief De-initialization for the ENC module. + * + * This function is to make the de-initialization for the ENC module. It could be called when ENC is no longer used with + * the operations like: + * - Disable the clock for ENC module. + * + * param base ENC peripheral base address. + */ +void ENC_Deinit(ENC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_encClocks[ENC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Get an available pre-defined settings for ENC's configuration. + * + * This function initializes the ENC configuration structure with an available settings, the default value are: + * code + * config->enableReverseDirection = false; + * config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; + * config->HOMETriggerMode = kENC_HOMETriggerDisabled; + * config->INDEXTriggerMode = kENC_INDEXTriggerDisabled; + * config->enableTRIGGERClearPositionCounter = false; + * config->enableTRIGGERClearHoldPositionCounter = false; + * config->enableWatchdog = false; + * config->watchdogTimeoutValue = 0U; + * config->filterCount = 0U; + * config->filterSamplePeriod = 0U; + * config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue; + * config->positionCompareValue = 0xFFFFFFFFU; + * config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse; + * config->enableModuloCountMode = false; + * config->positionModulusValue = 0U; + * config->positionInitialValue = 0U; + * endcode + * param config Pointer to a variable of configuration structure. See to "enc_config_t". + */ +void ENC_GetDefaultConfig(enc_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->enableReverseDirection = false; + config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; + config->HOMETriggerMode = kENC_HOMETriggerDisabled; + config->INDEXTriggerMode = kENC_INDEXTriggerDisabled; + config->enableTRIGGERClearPositionCounter = false; + config->enableTRIGGERClearHoldPositionCounter = false; + config->enableWatchdog = false; + config->watchdogTimeoutValue = 0U; + config->filterCount = 0U; + config->filterSamplePeriod = 0U; + config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue; + config->positionCompareValue = 0xFFFFFFFFU; + config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse; + config->enableModuloCountMode = false; + config->positionModulusValue = 0U; + config->positionInitialValue = 0U; +} + +/*! + * brief Load the initial position value to position counter. + * + * This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and + * LPOS), so that to provide the consistent operation the position counter registers. + * + * param base ENC peripheral base address. + */ +void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base) +{ + uint16_t tmp16 = base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS); + + tmp16 |= ENC_CTRL_SWIP_MASK; /* Write 1 to trigger the command for loading initial position value. */ + base->CTRL = tmp16; +} + +/*! + * brief Enable and configure the self test function. + * + * This function is to enable and configuration the self test function. It controls and sets the frequency of a + * quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module. + * It is a factory test feature; however, it may be useful to customers' software development and testing. + * + * param base ENC peripheral base address. + * param config Pointer to configuration structure. See to "enc_self_test_config_t". Pass "NULL" to disable. + */ +void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config) +{ + uint16_t tmp16 = 0U; + + if (NULL == config) /* Pass "NULL" to disable the feature. */ + { + base->TST = 0U; + return; + } + tmp16 = ENC_TST_TEN_MASK | ENC_TST_TCE_MASK | ENC_TST_TEST_PERIOD(config->signalPeriod) | + ENC_TST_TEST_COUNT(config->signalCount); + if (kENC_SelfTestDirectionNegative == config->signalDirection) + { + tmp16 |= ENC_TST_QDN_MASK; + } + base->TST = tmp16; +} + +/*! + * brief Enable watchdog for ENC module. + * + * param base ENC peripheral base address + * param enable Enables or disables the watchdog + */ +void ENC_EnableWatchdog(ENC_Type *base, bool enable) +{ + uint16_t tmp16 = base->CTRL & (uint16_t)(~(ENC_CTRL_W1C_FLAGS | ENC_CTRL_WDE_MASK)); + + if (enable) + { + tmp16 |= ENC_CTRL_WDE_MASK; + } + base->CTRL = tmp16; +} + +/*! + * brief Get the status flags. + * + * param base ENC peripheral base address. + * + * return Mask value of status flags. For available mask, see to "_enc_status_flags". + */ +uint32_t ENC_GetStatusFlags(ENC_Type *base) +{ + uint32_t ret32 = 0U; + + /* ENC_CTRL. */ + if (ENC_CTRL_HIRQ_MASK == (ENC_CTRL_HIRQ_MASK & base->CTRL)) + { + ret32 |= kENC_HOMETransitionFlag; + } + if (ENC_CTRL_XIRQ_MASK == (ENC_CTRL_XIRQ_MASK & base->CTRL)) + { + ret32 |= kENC_INDEXPulseFlag; + } + if (ENC_CTRL_DIRQ_MASK == (ENC_CTRL_DIRQ_MASK & base->CTRL)) + { + ret32 |= kENC_WatchdogTimeoutFlag; + } + if (ENC_CTRL_CMPIRQ_MASK == (ENC_CTRL_CMPIRQ_MASK & base->CTRL)) + { + ret32 |= kENC_PositionCompareFlag; + } + + /* ENC_CTRL2. */ + if (ENC_CTRL2_SABIRQ_MASK == (ENC_CTRL2_SABIRQ_MASK & base->CTRL2)) + { + ret32 |= kENC_SimultBothPhaseChangeFlag; + } + if (ENC_CTRL2_ROIRQ_MASK == (ENC_CTRL2_ROIRQ_MASK & base->CTRL2)) + { + ret32 |= kENC_PositionRollOverFlag; + } + if (ENC_CTRL2_RUIRQ_MASK == (ENC_CTRL2_RUIRQ_MASK & base->CTRL2)) + { + ret32 |= kENC_PositionRollUnderFlag; + } + if (ENC_CTRL2_DIR_MASK == (ENC_CTRL2_DIR_MASK & base->CTRL2)) + { + ret32 |= kENC_LastCountDirectionFlag; + } + + return ret32; +} + +/*! + * brief Clear the status flags. + * + * param base ENC peripheral base address. + * param mask Mask value of status flags to be cleared. For available mask, see to "_enc_status_flags". + */ +void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask) +{ + uint32_t tmp16 = 0U; + + /* ENC_CTRL. */ + if (kENC_HOMETransitionFlag == (kENC_HOMETransitionFlag & mask)) + { + tmp16 |= ENC_CTRL_HIRQ_MASK; + } + if (kENC_INDEXPulseFlag == (kENC_INDEXPulseFlag & mask)) + { + tmp16 |= ENC_CTRL_XIRQ_MASK; + } + if (kENC_WatchdogTimeoutFlag == (kENC_WatchdogTimeoutFlag & mask)) + { + tmp16 |= ENC_CTRL_DIRQ_MASK; + } + if (kENC_PositionCompareFlag == (kENC_PositionCompareFlag & mask)) + { + tmp16 |= ENC_CTRL_CMPIRQ_MASK; + } + if (0U != tmp16) + { + base->CTRL = (base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS)) | tmp16; + } + + /* ENC_CTRL2. */ + tmp16 = 0U; + if (kENC_SimultBothPhaseChangeFlag == (kENC_SimultBothPhaseChangeFlag & mask)) + { + tmp16 |= ENC_CTRL2_SABIRQ_MASK; + } + if (kENC_PositionRollOverFlag == (kENC_PositionRollOverFlag & mask)) + { + tmp16 |= ENC_CTRL2_ROIRQ_MASK; + } + if (kENC_PositionRollUnderFlag == (kENC_PositionRollUnderFlag & mask)) + { + tmp16 |= ENC_CTRL2_RUIRQ_MASK; + } + if (0U != tmp16) + { + base->CTRL2 = (base->CTRL2 & (uint16_t)(~ENC_CTRL2_W1C_FLAGS)) | tmp16; + } +} + +/*! + * brief Enable the interrupts. + * + * param base ENC peripheral base address. + * param mask Mask value of interrupts to be enabled. For available mask, see to "_enc_interrupt_enable". + */ +void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask) +{ + uint32_t tmp16 = 0U; + + /* ENC_CTRL. */ + if (kENC_HOMETransitionInterruptEnable == (kENC_HOMETransitionInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL_HIE_MASK; + } + if (kENC_INDEXPulseInterruptEnable == (kENC_INDEXPulseInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL_XIE_MASK; + } + if (kENC_WatchdogTimeoutInterruptEnable == (kENC_WatchdogTimeoutInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL_DIE_MASK; + } + if (kENC_PositionCompareInerruptEnable == (kENC_PositionCompareInerruptEnable & mask)) + { + tmp16 |= ENC_CTRL_CMPIE_MASK; + } + if (tmp16 != 0U) + { + base->CTRL = (base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS)) | tmp16; + } + /* ENC_CTRL2. */ + tmp16 = 0U; + if (kENC_SimultBothPhaseChangeInterruptEnable == (kENC_SimultBothPhaseChangeInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL2_SABIE_MASK; + } + if (kENC_PositionRollOverInterruptEnable == (kENC_PositionRollOverInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL2_ROIE_MASK; + } + if (kENC_PositionRollUnderInterruptEnable == (kENC_PositionRollUnderInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL2_RUIE_MASK; + } + if (tmp16 != 0U) + { + base->CTRL2 = (base->CTRL2 & (uint16_t)(~ENC_CTRL2_W1C_FLAGS)) | tmp16; + } +} + +/*! + * brief Disable the interrupts. + * + * param base ENC peripheral base address. + * param mask Mask value of interrupts to be disabled. For available mask, see to "_enc_interrupt_enable". + */ +void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask) +{ + uint16_t tmp16 = 0U; + + /* ENC_CTRL. */ + if (kENC_HOMETransitionInterruptEnable == (kENC_HOMETransitionInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL_HIE_MASK; + } + if (kENC_INDEXPulseInterruptEnable == (kENC_INDEXPulseInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL_XIE_MASK; + } + if (kENC_WatchdogTimeoutInterruptEnable == (kENC_WatchdogTimeoutInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL_DIE_MASK; + } + if (kENC_PositionCompareInerruptEnable == (kENC_PositionCompareInerruptEnable & mask)) + { + tmp16 |= ENC_CTRL_CMPIE_MASK; + } + if (0U != tmp16) + { + base->CTRL = (uint16_t)(base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS)) & (uint16_t)(~tmp16); + } + /* ENC_CTRL2. */ + tmp16 = 0U; + if (kENC_SimultBothPhaseChangeInterruptEnable == (kENC_SimultBothPhaseChangeInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL2_SABIE_MASK; + } + if (kENC_PositionRollOverInterruptEnable == (kENC_PositionRollOverInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL2_ROIE_MASK; + } + if (kENC_PositionRollUnderInterruptEnable == (kENC_PositionRollUnderInterruptEnable & mask)) + { + tmp16 |= ENC_CTRL2_RUIE_MASK; + } + if (tmp16 != 0U) + { + base->CTRL2 = (uint16_t)(base->CTRL2 & (uint16_t)(~ENC_CTRL2_W1C_FLAGS)) & (uint16_t)(~tmp16); + } +} + +/*! + * brief Get the enabled interrupts' flags. + * + * param base ENC peripheral base address. + * + * return Mask value of enabled interrupts. + */ +uint32_t ENC_GetEnabledInterrupts(ENC_Type *base) +{ + uint32_t ret32 = 0U; + + /* ENC_CTRL. */ + if (ENC_CTRL_HIE_MASK == (ENC_CTRL_HIE_MASK & base->CTRL)) + { + ret32 |= kENC_HOMETransitionInterruptEnable; + } + if (ENC_CTRL_XIE_MASK == (ENC_CTRL_XIE_MASK & base->CTRL)) + { + ret32 |= kENC_INDEXPulseInterruptEnable; + } + if (ENC_CTRL_DIE_MASK == (ENC_CTRL_DIE_MASK & base->CTRL)) + { + ret32 |= kENC_WatchdogTimeoutInterruptEnable; + } + if (ENC_CTRL_CMPIE_MASK == (ENC_CTRL_CMPIE_MASK & base->CTRL)) + { + ret32 |= kENC_PositionCompareInerruptEnable; + } + /* ENC_CTRL2. */ + if (ENC_CTRL2_SABIE_MASK == (ENC_CTRL2_SABIE_MASK & base->CTRL2)) + { + ret32 |= kENC_SimultBothPhaseChangeInterruptEnable; + } + if (ENC_CTRL2_ROIE_MASK == (ENC_CTRL2_ROIE_MASK & base->CTRL2)) + { + ret32 |= kENC_PositionRollOverInterruptEnable; + } + if (ENC_CTRL2_RUIE_MASK == (ENC_CTRL2_RUIE_MASK & base->CTRL2)) + { + ret32 |= kENC_PositionRollUnderInterruptEnable; + } + return ret32; +} + +/*! + * brief Set initial position value for ENC module. + * + * param base ENC peripheral base address + * param value Positive initial value + */ +void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value) +{ + base->UINIT = (uint16_t)(value >> 16U); /* Set upper 16 bits. */ + base->LINIT = (uint16_t)(value); /* Set lower 16 bits. */ +} + +/*! + * brief Get the current position counter's value. + * + * param base ENC peripheral base address. + * + * return Current position counter's value. + */ +uint32_t ENC_GetPositionValue(ENC_Type *base) +{ + uint32_t ret32; + + ret32 = base->UPOS; /* Get upper 16 bits and make a snapshot. */ + ret32 <<= 16U; + ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */ + + return ret32; +} + +/*! + * brief Get the hold position counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * param base ENC peripheral base address. + * + * return Hold position counter's value. + */ +uint32_t ENC_GetHoldPositionValue(ENC_Type *base) +{ + uint32_t ret32; + + ret32 = base->UPOSH; /* Get upper 16 bits and make a snapshot. */ + ret32 <<= 16U; + ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */ + + return ret32; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_enc.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_enc.h new file mode 100644 index 0000000000..badd234cf2 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_enc.h @@ -0,0 +1,458 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_ENC_H_ +#define _FSL_ENC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup enc + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define FSL_ENC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + +/*! + * @brief Interrupt enable/disable mask. + */ +enum _enc_interrupt_enable +{ + kENC_HOMETransitionInterruptEnable = (1U << 0U), /*!< HOME interrupt enable. */ + kENC_INDEXPulseInterruptEnable = (1U << 1U), /*!< INDEX pulse interrupt enable. */ + kENC_WatchdogTimeoutInterruptEnable = (1U << 2U), /*!< Watchdog timeout interrupt enable. */ + kENC_PositionCompareInerruptEnable = (1U << 3U), /*!< Position compare interrupt enable. */ + kENC_SimultBothPhaseChangeInterruptEnable = + (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt enable. */ + kENC_PositionRollOverInterruptEnable = (1U << 5U), /*!< Roll-over interrupt enable. */ + kENC_PositionRollUnderInterruptEnable = (1U << 6U), /*!< Roll-under interrupt enable. */ +}; + +/*! + * @brief Status flag mask. + * + * These flags indicate the counter's events. + */ +enum _enc_status_flags +{ + kENC_HOMETransitionFlag = (1U << 0U), /*!< HOME signal transition interrupt request. */ + kENC_INDEXPulseFlag = (1U << 1U), /*!< INDEX Pulse Interrupt Request. */ + kENC_WatchdogTimeoutFlag = (1U << 2U), /*!< Watchdog timeout interrupt request. */ + kENC_PositionCompareFlag = (1U << 3U), /*!< Position compare interrupt request. */ + kENC_SimultBothPhaseChangeFlag = (1U << 4U), /*!< Simultaneous PHASEA and PHASEB change interrupt request. */ + kENC_PositionRollOverFlag = (1U << 5U), /*!< Roll-over interrupt request. */ + kENC_PositionRollUnderFlag = (1U << 6U), /*!< Roll-under interrupt request. */ + kENC_LastCountDirectionFlag = (1U << 7U), /*!< Last count was in the up direction, or the down direction. */ +}; + +/*! + * @brief Signal status flag mask. + * + * These flags indicate the counter's signal. + */ +enum _enc_signal_status_flags +{ + kENC_RawHOMEStatusFlag = ENC_IMR_HOME_MASK, /*!< Raw HOME input. */ + kENC_RawINDEXStatusFlag = ENC_IMR_INDEX_MASK, /*!< Raw INDEX input. */ + kENC_RawPHBStatusFlag = ENC_IMR_PHB_MASK, /*!< Raw PHASEB input. */ + kENC_RawPHAEXStatusFlag = ENC_IMR_PHA_MASK, /*!< Raw PHASEA input. */ + kENC_FilteredHOMEStatusFlag = ENC_IMR_FHOM_MASK, /*!< The filtered version of HOME input. */ + kENC_FilteredINDEXStatusFlag = ENC_IMR_FIND_MASK, /*!< The filtered version of INDEX input. */ + kENC_FilteredPHBStatusFlag = ENC_IMR_FPHB_MASK, /*!< The filtered version of PHASEB input. */ + kENC_FilteredPHAStatusFlag = ENC_IMR_FPHA_MASK, /*!< The filtered version of PHASEA input. */ +}; + +/*! + * @brief Define HOME signal's trigger mode. + * + * The ENC would count the trigger from HOME signal line. + */ +typedef enum _enc_home_trigger_mode +{ + kENC_HOMETriggerDisabled = 0U, /*!< HOME signal's trigger is disabled. */ + kENC_HOMETriggerOnRisingEdge, /*!< Use positive going edge-to-trigger initialization of position counters. */ + kENC_HOMETriggerOnFallingEdge, /*!< Use negative going edge-to-trigger initialization of position counters. */ +} enc_home_trigger_mode_t; + +/*! + * @brief Define INDEX signal's trigger mode. + * + * The ENC would count the trigger from INDEX signal line. + */ +typedef enum _enc_index_trigger_mode +{ + kENC_INDEXTriggerDisabled = 0U, /*!< INDEX signal's trigger is disabled. */ + kENC_INDEXTriggerOnRisingEdge, /*!< Use positive going edge-to-trigger initialization of position counters. */ + kENC_INDEXTriggerOnFallingEdge, /*!< Use negative going edge-to-trigger initialization of position counters. */ +} enc_index_trigger_mode_t; + +/*! + * @brief Define type for decoder work mode. + * + * The normal work mode uses the standard quadrature decoder with PHASEA and PHASEB. When in signal phase count mode, + * a positive transition of the PHASEA input generates a count signal while the PHASEB input and the reverse direction + * control the counter direction. If the reverse direction is not enabled, PHASEB = 0 means counting up and PHASEB = 1 + * means counting down. Otherwise, the direction is reversed. + */ +typedef enum _enc_decoder_work_mode +{ + kENC_DecoderWorkAsNormalMode = 0U, /*!< Use standard quadrature decoder with PHASEA and PHASEB. */ + kENC_DecoderWorkAsSignalPhaseCountMode, /*!< PHASEA input generates a count signal while PHASEB input control the + direction. */ +} enc_decoder_work_mode_t; + +/*! + * @brief Define type for the condition of POSMATCH pulses. + */ +typedef enum _enc_position_match_mode +{ + kENC_POSMATCHOnPositionCounterEqualToComapreValue = 0U, /*!< POSMATCH pulses when a match occurs between the + position counters (POS) and the compare value (COMP). */ + kENC_POSMATCHOnReadingAnyPositionCounter, /*!< POSMATCH pulses when any position counter register is read. */ +} enc_position_match_mode_t; + +/*! + * @brief Define type for determining how the revolution counter (REV) is incremented/decremented. + */ +typedef enum _enc_revolution_count_condition +{ + kENC_RevolutionCountOnINDEXPulse = 0U, /*!< Use INDEX pulse to increment/decrement revolution counter. */ + kENC_RevolutionCountOnRollOverModulus, /*!< Use modulus counting roll-over/under to increment/decrement revolution + counter. */ +} enc_revolution_count_condition_t; + +/*! + * @brief Define type for direction of self test generated signal. + */ +typedef enum _enc_self_test_direction +{ + kENC_SelfTestDirectionPositive = 0U, /*!< Self test generates the signal in positive direction. */ + kENC_SelfTestDirectionNegative, /*!< Self test generates the signal in negative direction. */ +} enc_self_test_direction_t; + +/*! + * @brief Define user configuration structure for ENC module. + */ +typedef struct _enc_config +{ + /* Basic counter. */ + bool enableReverseDirection; /*!< Enable reverse direction counting. */ + enc_decoder_work_mode_t decoderWorkMode; /*!< Enable signal phase count mode. */ + + /* Signal detection. */ + enc_home_trigger_mode_t HOMETriggerMode; /*!< Enable HOME to initialize position counters. */ + enc_index_trigger_mode_t INDEXTriggerMode; /*!< Enable INDEX to initialize position counters. */ + bool enableTRIGGERClearPositionCounter; /*!< Clear POSD, REV, UPOS and LPOS on rising edge of TRIGGER, or not. */ + bool enableTRIGGERClearHoldPositionCounter; /*!< Enable update of hold registers on rising edge of TRIGGER, or not. + */ + + /* Watchdog. */ + bool enableWatchdog; /*!< Enable the watchdog to detect if the target is moving or not. */ + uint16_t watchdogTimeoutValue; /*!< Watchdog timeout count value. It stores the timeout count for the quadrature + decoder module watchdog timer. This field is only available when + "enableWatchdog" = true. The available value is a 16-bit unsigned number.*/ + + /* Filter for PHASEA, PHASEB, INDEX and HOME. */ + uint16_t filterCount; /*!< Input Filter Sample Count. This value should be chosen to reduce the probability of + noisy samples causing an incorrect transition to be recognized. The value represent the + number of consecutive samples that must agree prior to the input filter accepting an + input transition. A value of 0x0 represents 3 samples. A value of 0x7 represents 10 + samples. The Available range is 0 - 7.*/ + uint16_t filterSamplePeriod; /*!< Input Filter Sample Period. This value should be set such that the sampling period + is larger than the period of the expected noise. This value represents the + sampling period (in IPBus clock cycles) of the decoder input signals. + The available range is 0 - 255. */ + + /* Position compare. */ + enc_position_match_mode_t positionMatchMode; /*!< The condition of POSMATCH pulses. */ + uint32_t positionCompareValue; /*!< Position compare value. The available value is a 32-bit number.*/ + + /* Modulus counting. */ + enc_revolution_count_condition_t revolutionCountCondition; /*!< Revolution Counter Modulus Enable. */ + bool enableModuloCountMode; /*!< Enable Modulo Counting. */ + uint32_t positionModulusValue; /*!< Position modulus value. This value would be available only when + "enableModuloCountMode" = true. The available value is a 32-bit number. */ + uint32_t positionInitialValue; /*!< Position initial value. The available value is a 32-bit number. */ +} enc_config_t; + +/*! + * @brief Define configuration structure for self test module. + * + * The self test module provides a quadrature test signal to the inputs of the quadrature decoder module. + * This is a factory test feature. It is also useful to customers' software development and testing. + */ +typedef struct _enc_self_test_config +{ + enc_self_test_direction_t signalDirection; /*!< Direction of self test generated signal. */ + uint16_t signalCount; /*!< Hold the number of quadrature advances to generate. The available range is 0 - 255.*/ + uint16_t signalPeriod; /*!< Hold the period of quadrature phase in IPBus clock cycles. + The available range is 0 - 31. */ +} enc_self_test_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @name Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initialization for the ENC module. + * + * This function is to make the initialization for the ENC module. It should be called firstly before any operation to + * the ENC with the operations like: + * - Enable the clock for ENC module. + * - Configure the ENC's working attributes. + * + * @param base ENC peripheral base address. + * @param config Pointer to configuration structure. See to "enc_config_t". + */ +void ENC_Init(ENC_Type *base, const enc_config_t *config); + +/*! + * @brief De-initialization for the ENC module. + * + * This function is to make the de-initialization for the ENC module. It could be called when ENC is no longer used with + * the operations like: + * - Disable the clock for ENC module. + * + * @param base ENC peripheral base address. + */ +void ENC_Deinit(ENC_Type *base); + +/*! + * @brief Get an available pre-defined settings for ENC's configuration. + * + * This function initializes the ENC configuration structure with an available settings, the default value are: + * @code + * config->enableReverseDirection = false; + * config->decoderWorkMode = kENC_DecoderWorkAsNormalMode; + * config->HOMETriggerMode = kENC_HOMETriggerDisabled; + * config->INDEXTriggerMode = kENC_INDEXTriggerDisabled; + * config->enableTRIGGERClearPositionCounter = false; + * config->enableTRIGGERClearHoldPositionCounter = false; + * config->enableWatchdog = false; + * config->watchdogTimeoutValue = 0U; + * config->filterCount = 0U; + * config->filterSamplePeriod = 0U; + * config->positionMatchMode = kENC_POSMATCHOnPositionCounterEqualToComapreValue; + * config->positionCompareValue = 0xFFFFFFFFU; + * config->revolutionCountCondition = kENC_RevolutionCountOnINDEXPulse; + * config->enableModuloCountMode = false; + * config->positionModulusValue = 0U; + * config->positionInitialValue = 0U; + * @endcode + * @param config Pointer to a variable of configuration structure. See to "enc_config_t". + */ +void ENC_GetDefaultConfig(enc_config_t *config); + +/*! + * @brief Load the initial position value to position counter. + * + * This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and + * LPOS), so that to provide the consistent operation the position counter registers. + * + * @param base ENC peripheral base address. + */ +void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base); + +/*! + * @brief Enable and configure the self test function. + * + * This function is to enable and configuration the self test function. It controls and sets the frequency of a + * quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module. + * It is a factory test feature; however, it may be useful to customers' software development and testing. + * + * @param base ENC peripheral base address. + * @param config Pointer to configuration structure. See to "enc_self_test_config_t". Pass "NULL" to disable. + */ +void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config); + +/*! + * @brief Enable watchdog for ENC module. + * + * @param base ENC peripheral base address + * @param enable Enables or disables the watchdog + */ +void ENC_EnableWatchdog(ENC_Type *base, bool enable); + +/*! + * @brief Set initial position value for ENC module. + * + * @param base ENC peripheral base address + * @param value Positive initial value + */ +void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value); + +/* @} */ + +/*! + * @name Status + * @{ + */ +/*! + * @brief Get the status flags. + * + * @param base ENC peripheral base address. + * + * @return Mask value of status flags. For available mask, see to "_enc_status_flags". + */ +uint32_t ENC_GetStatusFlags(ENC_Type *base); + +/*! + * @brief Clear the status flags. + * + * @param base ENC peripheral base address. + * @param mask Mask value of status flags to be cleared. For available mask, see to "_enc_status_flags". + */ +void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask); + +/*! + * @brief Get the signals' real-time status. + * + * @param base ENC peripheral base address. + * + * @return Mask value of signals' real-time status. For available mask, see to "_enc_signal_status_flags" + */ +static inline uint16_t ENC_GetSignalStatusFlags(ENC_Type *base) +{ + return base->IMR; +} +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enable the interrupts. + * + * @param base ENC peripheral base address. + * @param mask Mask value of interrupts to be enabled. For available mask, see to "_enc_interrupt_enable". + */ +void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask); + +/*! + * @brief Disable the interrupts. + * + * @param base ENC peripheral base address. + * @param mask Mask value of interrupts to be disabled. For available mask, see to "_enc_interrupt_enable". + */ +void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask); + +/*! + * @brief Get the enabled interrupts' flags. + * + * @param base ENC peripheral base address. + * + * @return Mask value of enabled interrupts. + */ +uint32_t ENC_GetEnabledInterrupts(ENC_Type *base); + +/* @} */ + +/*! + * @name Value Operation + * @{ + */ + +/*! + * @brief Get the current position counter's value. + * + * @param base ENC peripheral base address. + * + * @return Current position counter's value. + */ +uint32_t ENC_GetPositionValue(ENC_Type *base); + +/*! + * @brief Get the hold position counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * @param base ENC peripheral base address. + * + * @return Hold position counter's value. + */ +uint32_t ENC_GetHoldPositionValue(ENC_Type *base); + +/*! + * @brief Get the position difference counter's value. + * + * @param base ENC peripheral base address. + * + * @return The position difference counter's value. + */ +static inline uint16_t ENC_GetPositionDifferenceValue(ENC_Type *base) +{ + return base->POSD; +} + +/*! + * @brief Get the hold position difference counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * @param base ENC peripheral base address. + * + * @return Hold position difference counter's value. + */ +static inline uint16_t ENC_GetHoldPositionDifferenceValue(ENC_Type *base) +{ + return base->POSDH; +} + +/*! + * @brief Get the position revolution counter's value. + * + * @param base ENC peripheral base address. + * + * @return The position revolution counter's value. + */ +static inline uint16_t ENC_GetRevolutionValue(ENC_Type *base) +{ + return base->REV; +} +/*! + * @brief Get the hold position revolution counter's value. + * + * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold + * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to + * be attained. + * + * @param base ENC peripheral base address. + * + * @return Hold position revolution counter's value. + */ +static inline uint16_t ENC_GetHoldRevolutionValue(ENC_Type *base) +{ + return base->REVH; +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/* + * @} + */ +#endif /* _FSL_ENC_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_enet.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_enet.c new file mode 100644 index 0000000000..e30d9f2312 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_enet.c @@ -0,0 +1,3460 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_enet.h" +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL +#include "fsl_cache.h" +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.enet" +#endif + +/*! @brief IPv4 PTP message IP version offset. */ +#define ENET_PTP1588_IPVERSION_OFFSET 0x0EU +/*! @brief IPv4 PTP message UDP protocol offset. */ +#define ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET 0x17U +/*! @brief IPv4 PTP message UDP port offset. */ +#define ENET_PTP1588_IPV4_UDP_PORT_OFFSET 0x24U +/*! @brief IPv4 PTP message UDP message type offset. */ +#define ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET 0x2AU +/*! @brief IPv4 PTP message UDP version offset. */ +#define ENET_PTP1588_IPV4_UDP_VERSION_OFFSET 0x2BU +/*! @brief IPv4 PTP message UDP clock id offset. */ +#define ENET_PTP1588_IPV4_UDP_CLKID_OFFSET 0x3EU +/*! @brief IPv4 PTP message UDP sequence id offset. */ +#define ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET 0x48U +/*! @brief IPv4 PTP message UDP control offset. */ +#define ENET_PTP1588_IPV4_UDP_CTL_OFFSET 0x4AU +/*! @brief IPv6 PTP message UDP protocol offset. */ +#define ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET 0x14U +/*! @brief IPv6 PTP message UDP port offset. */ +#define ENET_PTP1588_IPV6_UDP_PORT_OFFSET 0x38U +/*! @brief IPv6 PTP message UDP message type offset. */ +#define ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET 0x3EU +/*! @brief IPv6 PTP message UDP version offset. */ +#define ENET_PTP1588_IPV6_UDP_VERSION_OFFSET 0x3FU +/*! @brief IPv6 PTP message UDP clock id offset. */ +#define ENET_PTP1588_IPV6_UDP_CLKID_OFFSET 0x52U +/*! @brief IPv6 PTP message UDP sequence id offset. */ +#define ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET 0x5CU +/*! @brief IPv6 PTP message UDP control offset. */ +#define ENET_PTP1588_IPV6_UDP_CTL_OFFSET 0x5EU +/*! @brief PTPv2 message Ethernet packet type offset. */ +#define ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET 0x0CU +/*! @brief PTPv2 message Ethernet message type offset. */ +#define ENET_PTP1588_ETHL2_MSGTYPE_OFFSET 0x0EU +/*! @brief PTPv2 message Ethernet version type offset. */ +#define ENET_PTP1588_ETHL2_VERSION_OFFSET 0X0FU +/*! @brief PTPv2 message Ethernet clock id offset. */ +#define ENET_PTP1588_ETHL2_CLOCKID_OFFSET 0x22 +/*! @brief PTPv2 message Ethernet sequence id offset. */ +#define ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET 0x2c +/*! @brief Packet type Ethernet IEEE802.3 for PTPv2. */ +#define ENET_ETHERNETL2 0x88F7U +/*! @brief Packet type IPv4. */ +#define ENET_IPV4 0x0800U +/*! @brief Packet type IPv6. */ +#define ENET_IPV6 0x86ddU +/*! @brief Packet type VLAN. */ +#define ENET_8021QVLAN 0x8100U +/*! @brief UDP protocol type. */ +#define ENET_UDPVERSION 0x0011U +/*! @brief Packet IP version IPv4. */ +#define ENET_IPV4VERSION 0x0004U +/*! @brief Packet IP version IPv6. */ +#define ENET_IPV6VERSION 0x0006U +/*! @brief Ethernet mac address length. */ +#define ENET_FRAME_MACLEN 6U +/*! @brief Ethernet VLAN header length. */ +#define ENET_FRAME_VLAN_TAGLEN 4U +/*! @brief MDC frequency. */ +#define ENET_MDC_FREQUENCY 2500000U +/*! @brief NanoSecond in one second. */ +#define ENET_NANOSECOND_ONE_SECOND 1000000000U +/*! @brief Define a common clock cycle delays used for time stamp capture. */ +#ifndef ENET_1588TIME_DELAY_COUNT +#define ENET_1588TIME_DELAY_COUNT 10U +#endif + +/*! @brief Defines the macro for converting constants from host byte order to network byte order. */ +#define ENET_HTONS(n) __REV16(n) +#define ENET_HTONL(n) __REV(n) +#define ENET_NTOHS(n) __REV16(n) +#define ENET_NTOHL(n) __REV(n) + +/*! @brief Define the ENET ring/class bumber . */ +enum _enet_ring_number +{ + kENET_Ring0 = 0U, /*!< ENET ring/class 0. */ +#if FSL_FEATURE_ENET_QUEUE > 1 + kENET_Ring1 = 1U, /*!< ENET ring/class 1. */ + kENET_Ring2 = 2U /*!< ENET ring/class 2. */ +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +}; + +/*! @brief Define interrupt IRQ handler. */ +#if FSL_FEATURE_ENET_QUEUE > 1 +typedef void (*enet_isr_ring_t)(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the ENET instance from peripheral base address. + * + * @param base ENET peripheral base address. + * @return ENET instance. + */ +uint32_t ENET_GetInstance(ENET_Type *base); +/*! + * @brief Set ENET MAC controller with the configuration. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + * @param config ENET Mac configuration. + * @param bufferConfig ENET buffer configuration. + * @param macAddr ENET six-byte mac address. + * @param srcClock_Hz ENET module clock source, normally it's system clock. + */ +static void ENET_SetMacController(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz); +/*! + * @brief Set ENET handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + * @param config ENET configuration stucture pointer. + * @param bufferConfig ENET buffer configuration. + */ +static void ENET_SetHandler(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig); +/*! + * @brief Set ENET MAC transmit buffer descriptors. + * + * @param handle The ENET handle pointer. + * @param config The ENET configuration structure. + * @param bufferConfig The ENET buffer configuration. + */ +static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig); + +/*! + * @brief Set ENET MAC receive buffer descriptors. + * + * @param handle The ENET handle pointer. + * @param config The ENET configuration structure. + * @param bufferConfig The ENET buffer configuration. + */ +static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig); + +/*! + * @brief Updates the ENET read buffer descriptors. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + * @param ringId The descriptor ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. + * 0 ----- for single ring kinetis platform. + * 0 ~ 2 for mulit-ring supported IMX8qm. + */ +static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); + +/*! + * @brief Activates ENET send for multiple tx rings. + * + * @param base ENET peripheral base address. + * @param ringId The descriptor ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. + * 0 ----- for single ring kinetis platform. + * 0 ~ 2 for mulit-ring supported IMX8qm. + * + * @note This must be called after the MAC configuration and + * state are ready. It must be called after the ENET_Init() and + * this should be called when the ENET receive required. + */ +static void ENET_ActiveSend(ENET_Type *base, uint32_t ringId); +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * @brief Parses the ENET frame for time-stamp process of PTP 1588 frame. + * + * @param data The ENET read data for frame parse. + * @param ptpTsData The ENET PTP message and time-stamp data pointer. + * @param isFastEnabled The fast parse flag. + * - true , Fast processing, only check if this is a PTP message. + * - false, Store the PTP message data after check the PTP message. + */ +static bool ENET_Ptp1588ParseFrame(const uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled); + +/*! + * @brief Updates the new PTP 1588 time-stamp to the time-stamp buffer ring. + * + * @param ptpTsDataRing The PTP message and time-stamp data ring pointer. + * @param ptpTimeData The new PTP 1588 time-stamp data pointer. + */ +static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData); + +/*! + * @brief Search up the right PTP 1588 time-stamp from the time-stamp buffer ring. + * + * @param ptpTsDataRing The PTP message and time-stamp data ring pointer. + * @param ptpTimeData The find out right PTP 1588 time-stamp data pointer with the specific PTP message. + */ +static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata); + +/*! + * @brief Store the transmit time-stamp for event PTP frame in the time-stamp buffer ring. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + * @param ringId The descriptor ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. + * 0 ----- for single ring kinetis platform. + * 0 ~ 2 for mulit-ring supported IMX8qm. + */ +static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); + +/*! + * @brief Store the receive time-stamp for event PTP frame in the time-stamp buffer ring. + * + * @param base ENET peripheral base address. + * @param handle The ENET handle pointer. + * @param ptpTimeData The PTP 1588 time-stamp data pointer. + */ +static status_t ENET_StoreRxFrameTime(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_AVB +/*! + * @brief Gets the ring index for transmission. + * + * @param base ENET peripheral base address. + * @param data The ENET transmit data. + * @param handle The ENET handle pointer. + * + * @note This must be called after the MAC configuration and + * state are ready. It must be called after the ENET_Init() and + * this should be called when the ENET receive required. + */ +static uint8_t ENET_GetTxRingId(ENET_Type *base, uint8_t *data, enet_handle_t *handle); +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to enet handles for each instance. */ +static enet_handle_t *s_ENETHandle[FSL_FEATURE_SOC_ENET_COUNT] = {NULL}; + +/*! @brief Pointers to enet clocks for each instance. */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +const clock_ip_name_t s_enetClock[] = ENET_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to enet transmit IRQ number for each instance. */ +static const IRQn_Type s_enetTxIrqId[] = ENET_Transmit_IRQS; +/*! @brief Pointers to enet receive IRQ number for each instance. */ +static const IRQn_Type s_enetRxIrqId[] = ENET_Receive_IRQS; +#if defined(ENET_ENHANCEDBUFFERDESCRIPTOR_MODE) && ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @brief Pointers to enet timestamp IRQ number for each instance. */ +static const IRQn_Type s_enetTsIrqId[] = ENET_1588_Timer_IRQS; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +/*! @brief Pointers to enet error IRQ number for each instance. */ +static const IRQn_Type s_enetErrIrqId[] = ENET_Error_IRQS; + +/*! @brief Pointers to enet bases for each instance. */ +static ENET_Type *const s_enetBases[] = ENET_BASE_PTRS; + +/* ENET ISR for transactional APIs. */ +#if FSL_FEATURE_ENET_QUEUE > 1 +static enet_isr_ring_t s_enetTxIsr; +static enet_isr_ring_t s_enetRxIsr; +#else +static enet_isr_t s_enetTxIsr; +static enet_isr_t s_enetRxIsr; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +static enet_isr_t s_enetErrIsr; +static enet_isr_t s_enetTsIsr; +/******************************************************************************* + * Code + ******************************************************************************/ + +uint32_t ENET_GetInstance(ENET_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_enetBases); instance++) + { + if (s_enetBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_enetBases)); + + return instance; +} + +/*! + * brief Gets the ENET default configuration structure. + * + * The purpose of this API is to get the default ENET MAC controller + * configure structure for ENET_Init(). User may use the initialized + * structure unchanged in ENET_Init(), or modify some fields of the + * structure before calling ENET_Init(). + * Example: + code + enet_config_t config; + ENET_GetDefaultConfig(&config); + endcode + * param config The ENET mac controller configuration structure pointer. + */ +void ENET_GetDefaultConfig(enet_config_t *config) +{ + /* Checks input parameter. */ + assert(config); + + /* Initializes the MAC configure structure to zero. */ + memset(config, 0, sizeof(enet_config_t)); + +/* Sets MII mode, full duplex, 100Mbps for MAC and PHY data interface. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + config->miiMode = kENET_RgmiiMode; +#else + config->miiMode = kENET_RmiiMode; +#endif + config->miiSpeed = kENET_MiiSpeed100M; + config->miiDuplex = kENET_MiiFullDuplex; + + config->ringNum = 1; + + /* Sets the maximum receive frame length. */ + config->rxMaxFrameLen = ENET_FRAME_MAX_FRAMELEN; +} + +/*! + * brief Initializes the ENET module. + * + * This function ungates the module clock and initializes it with the ENET configuration. + * + * param base ENET peripheral base address. + * param handle ENET handler pointer. + * param config ENET mac configuration structure pointer. + * The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig + * can be used directly. It is also possible to verify the Mac configuration using other methods. + * param bufferConfig ENET buffer configuration structure pointer. + * The buffer configuration should be prepared for ENET Initialization. + * It is the start address of "ringNum" enet_buffer_config structures. + * To support added multi-ring features in some soc and compatible with the previous + * enet driver version. For single ring supported, this bufferConfig is a buffer + * configure structure pointer, for multi-ring supported and used case, this bufferConfig + * pointer should be a buffer configure structure array pointer. + * param macAddr ENET mac address of Ethernet device. This MAC address should be + * provided. + * param srcClock_Hz The internal module clock source for MII clock. + * + * note ENET has two buffer descriptors legacy buffer descriptors and + * enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To + * use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor + * by defining "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" and calling ENET_Ptp1588Configure() + * to configure the 1588 feature and related buffers after calling ENET_Init(). + */ +void ENET_Init(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz) +{ + /* Checks input parameters. */ + assert(handle); + assert(config); + assert(bufferConfig); + assert(macAddr); + assert(config->ringNum <= FSL_FEATURE_ENET_QUEUE); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = ENET_GetInstance(base); + + /* Ungate ENET clock. */ + CLOCK_EnableClock(s_enetClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* Reset ENET module. */ + ENET_Reset(base); + + /* Initializes the ENET transmit buffer descriptors. */ + ENET_SetTxBufferDescriptors(handle, config, bufferConfig); + + /* Initializes the ENET receive buffer descriptors. */ + ENET_SetRxBufferDescriptors(handle, config, bufferConfig); + + /* Initializes the ENET MAC controller with basic function. */ + ENET_SetMacController(base, handle, config, bufferConfig, macAddr, srcClock_Hz); + + /* Set all buffers or data in handler for data transmit/receive process. */ + ENET_SetHandler(base, handle, config, bufferConfig); +} + +/*! + * brief Deinitializes the ENET module. + + * This function gates the module clock, clears ENET interrupts, and disables the ENET module. + * + * param base ENET peripheral base address. + */ +void ENET_Deinit(ENET_Type *base) +{ + /* Disable interrupt. */ + base->EIMR = 0; + + /* Disable ENET. */ + base->ECR &= ~ENET_ECR_ETHEREN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disables the clock source. */ + CLOCK_DisableClock(s_enetClock[ENET_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Sets the callback function. + * This API is provided for the application callback required case when ENET + * interrupt is enabled. This API should be called after calling ENET_Init. + * + * param handle ENET handler pointer. Should be provided by application. + * param callback The ENET callback function. + * param userData The callback function parameter. + */ +void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData) +{ + assert(handle); + + /* Set callback and userData. */ + handle->callback = callback; + handle->userData = userData; +} + +static void ENET_SetHandler(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig) +{ + uint8_t count; + uint32_t instance = ENET_GetInstance(base); + const enet_buffer_config_t *buffCfg = bufferConfig; + + /* Store transfer parameters in handle pointer. */ + memset(handle, 0, sizeof(enet_handle_t)); + + handle->ringNum = (config->ringNum > FSL_FEATURE_ENET_QUEUE) ? FSL_FEATURE_ENET_QUEUE : config->ringNum; + for (count = 0; count < handle->ringNum; count++) + { + assert(buffCfg->rxBuffSizeAlign * buffCfg->rxBdNumber > config->rxMaxFrameLen); + + handle->rxBdBase[count] = buffCfg->rxBdStartAddrAlign; + handle->rxBdCurrent[count] = buffCfg->rxBdStartAddrAlign; + handle->rxBuffSizeAlign[count] = buffCfg->rxBuffSizeAlign; + handle->txBdBase[count] = buffCfg->txBdStartAddrAlign; + handle->txBdCurrent[count] = buffCfg->txBdStartAddrAlign; + handle->txBuffSizeAlign[count] = buffCfg->txBuffSizeAlign; + buffCfg++; + } + + /* Save the handle pointer in the global variables. */ + s_ENETHandle[instance] = handle; + + /* Set the IRQ handler when the interrupt is enabled. */ + if (config->interrupt & ENET_TX_INTERRUPT) + { + s_enetTxIsr = ENET_TransmitIRQHandler; + EnableIRQ(s_enetTxIrqId[instance]); + } + if (config->interrupt & ENET_RX_INTERRUPT) + { + s_enetRxIsr = ENET_ReceiveIRQHandler; + EnableIRQ(s_enetRxIrqId[instance]); + } + if (config->interrupt & ENET_ERR_INTERRUPT) + { + s_enetErrIsr = ENET_ErrorIRQHandler; + EnableIRQ(s_enetErrIrqId[instance]); + } +} + +static void ENET_SetMacController(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz) +{ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + /* Check the MII mode/speed/duplex setting. */ + if (config->miiSpeed == kENET_MiiSpeed1000M) + { + /* Only RGMII mode has the 1000M bit/s. The 1000M only support full duplex. */ + assert(config->miiMode == kENET_RgmiiMode); + assert(config->miiDuplex == kENET_MiiFullDuplex); + } +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + + uint32_t rcr = 0; + uint32_t tcr = 0; + uint32_t ecr = base->ECR; + uint32_t macSpecialConfig = config->macSpecialConfig; + uint32_t maxFrameLen = config->rxMaxFrameLen; + + /* Maximum frame length check. */ + if ((macSpecialConfig & kENET_ControlVLANTagEnable) && (maxFrameLen <= ENET_FRAME_MAX_FRAMELEN)) + { + maxFrameLen = (ENET_FRAME_MAX_FRAMELEN + ENET_FRAME_VLAN_TAGLEN); +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + if (macSpecialConfig & kENET_ControlSVLANEnable) + { + /* Double vlan tag (SVLAN) supported. */ + maxFrameLen += ENET_FRAME_VLAN_TAGLEN; + } + ecr |= ((macSpecialConfig & kENET_ControlSVLANEnable) ? (ENET_ECR_SVLANEN_MASK | ENET_ECR_SVLANDBL_MASK) : 0) | + ((macSpecialConfig & kENET_ControlVLANUseSecondTag) ? ENET_ECR_VLANUSE2ND_MASK : 0); +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + } + + /* Configures MAC receive controller with user configure structure. */ + rcr = ((macSpecialConfig & kENET_ControlRxPayloadCheckEnable) ? ENET_RCR_NLC_MASK : 0) | + ((macSpecialConfig & kENET_ControlFlowControlEnable) ? ENET_RCR_CFEN_MASK : 0) | + ((macSpecialConfig & kENET_ControlFlowControlEnable) ? ENET_RCR_FCE_MASK : 0) | + ((macSpecialConfig & kENET_ControlRxPadRemoveEnable) ? ENET_RCR_PADEN_MASK : 0) | + ((macSpecialConfig & kENET_ControlRxBroadCastRejectEnable) ? ENET_RCR_BC_REJ_MASK : 0) | + ((macSpecialConfig & kENET_ControlPromiscuousEnable) ? ENET_RCR_PROM_MASK : 0) | + ENET_RCR_MAX_FL(maxFrameLen) | ENET_RCR_CRCFWD_MASK; + +/* Set the RGMII or RMII, MII mode and control register. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + if (config->miiMode == kENET_RgmiiMode) + { + rcr |= ENET_RCR_RGMII_EN_MASK; + rcr &= ~ENET_RCR_MII_MODE_MASK; + } + else + { + rcr &= ~ENET_RCR_RGMII_EN_MASK; +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + rcr |= ENET_RCR_MII_MODE_MASK; + if (config->miiMode == kENET_RmiiMode) + { + rcr |= ENET_RCR_RMII_MODE_MASK; + } +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + } +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + /* Speed. */ + if (config->miiSpeed == kENET_MiiSpeed10M) + { + rcr |= ENET_RCR_RMII_10T_MASK; + } +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + if (config->miiSpeed == kENET_MiiSpeed1000M) + { + ecr |= ENET_ECR_SPEED_MASK; + } +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + + /* Receive setting for half duplex. */ + if (config->miiDuplex == kENET_MiiHalfDuplex) + { + rcr |= ENET_RCR_DRT_MASK; + } + /* Sets internal loop only for MII mode. */ + if ((config->macSpecialConfig & kENET_ControlMIILoopEnable) && (config->miiMode != kENET_RmiiMode)) + { + rcr |= ENET_RCR_LOOP_MASK; + rcr &= ~ENET_RCR_DRT_MASK; + } + base->RCR = rcr; + + /* Configures MAC transmit controller: duplex mode, mac address insertion. */ + tcr = base->TCR & ~(ENET_TCR_FDEN_MASK | ENET_TCR_ADDINS_MASK); + tcr |= (config->miiDuplex ? ENET_TCR_FDEN_MASK : 0) | + ((macSpecialConfig & kENET_ControlMacAddrInsert) ? ENET_TCR_ADDINS_MASK : 0); + base->TCR = tcr; + + /* Configures receive and transmit accelerator. */ + base->TACC = config->txAccelerConfig; + base->RACC = config->rxAccelerConfig; + + /* Sets the pause duration and FIFO threshold for the flow control enabled case. */ + if (macSpecialConfig & kENET_ControlFlowControlEnable) + { + uint32_t reemReg; + base->OPD = config->pauseDuration; + reemReg = ENET_RSEM_RX_SECTION_EMPTY(config->rxFifoEmptyThreshold); +#if defined(FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD + reemReg |= ENET_RSEM_STAT_SECTION_EMPTY(config->rxFifoStatEmptyThreshold); +#endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */ + base->RSEM = reemReg; + } + + /* FIFO threshold setting for store and forward enable/disable case. */ + if (macSpecialConfig & kENET_ControlStoreAndFwdDisable) + { + /* Transmit fifo watermark settings. */ + base->TFWR = config->txFifoWatermark & ENET_TFWR_TFWR_MASK; + /* Receive fifo full threshold settings. */ + base->RSFL = config->rxFifoFullThreshold & ENET_RSFL_RX_SECTION_FULL_MASK; + } + else + { + /* Transmit fifo watermark settings. */ + base->TFWR = ENET_TFWR_STRFWD_MASK; + base->RSFL = 0; + } + + /* Enable store and forward when accelerator is enabled */ + if (config->txAccelerConfig & (kENET_TxAccelIpCheckEnabled | kENET_TxAccelProtoCheckEnabled)) + { + base->TFWR = ENET_TFWR_STRFWD_MASK; + } + if (config->rxAccelerConfig & (kENET_RxAccelIpCheckEnabled | kENET_RxAccelProtoCheckEnabled)) + { + base->RSFL = 0; + } + +/* Initializes the ring 0. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + base->TDSR = MEMORY_ConvertMemoryMapAddress((uint32_t)bufferConfig->txBdStartAddrAlign, kMEMORY_Local2DMA); + base->RDSR = MEMORY_ConvertMemoryMapAddress((uint32_t)bufferConfig->rxBdStartAddrAlign, kMEMORY_Local2DMA); +#else + base->TDSR = (uint32_t)bufferConfig->txBdStartAddrAlign; + base->RDSR = (uint32_t)bufferConfig->rxBdStartAddrAlign; +#endif + base->MRBR = bufferConfig->rxBuffSizeAlign; + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + const enet_buffer_config_t *buffCfg = bufferConfig; + + if (config->ringNum > 1) + { + /* Initializes the ring 1. */ + buffCfg++; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + base->TDSR1 = MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->txBdStartAddrAlign, kMEMORY_Local2DMA); + base->RDSR1 = MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->rxBdStartAddrAlign, kMEMORY_Local2DMA); +#else + base->TDSR1 = (uint32_t)buffCfg->txBdStartAddrAlign; + base->RDSR1 = (uint32_t)buffCfg->rxBdStartAddrAlign; +#endif + base->MRBR1 = buffCfg->rxBuffSizeAlign; + /* Enable the DMAC for ring 1 and with no rx classification set. */ + base->DMACFG[0] = ENET_DMACFG_DMA_CLASS_EN_MASK; + } + if (config->ringNum > 2) + { + /* Initializes the ring 2. */ + buffCfg++; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + base->TDSR2 = MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->txBdStartAddrAlign, kMEMORY_Local2DMA); + base->RDSR2 = MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->rxBdStartAddrAlign, kMEMORY_Local2DMA); +#else + base->TDSR2 = (uint32_t)buffCfg->txBdStartAddrAlign; + base->RDSR2 = (uint32_t)buffCfg->rxBdStartAddrAlign; +#endif + base->MRBR2 = buffCfg->rxBuffSizeAlign; + /* Enable the DMAC for ring 2 and with no rx classification set. */ + base->DMACFG[1] = ENET_DMACFG_DMA_CLASS_EN_MASK; + } + + /* Default the class/ring 1 and 2 are not enabled and the receive classification is disabled + * so we set the default transmit scheme with the round-robin mode. beacuse the legacy bd mode + * only support the round-robin mode. if the avb feature is required, just call the setup avb + * feature API. */ + base->QOS |= ENET_QOS_TX_SCHEME(1); +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + + /* Configures the Mac address. */ + ENET_SetMacAddr(base, macAddr); + + /* Initialize the SMI if uninitialized. */ + if (!ENET_GetSMI(base)) + { + ENET_SetSMI(base, srcClock_Hz, !!(config->macSpecialConfig & kENET_ControlSMIPreambleDisable)); + } + +/* Enables Ethernet interrupt, enables the interrupt coalsecing if it is required. */ +#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE + if (config->intCoalesceCfg) + { + uint32_t intMask = (ENET_EIMR_TXB_MASK | ENET_EIMR_RXB_MASK); + +#if FSL_FEATURE_ENET_QUEUE > 1 + uint8_t queue = 0; + intMask |= ENET_EIMR_TXB2_MASK | ENET_EIMR_RXB2_MASK | ENET_EIMR_TXB1_MASK | ENET_EIMR_RXB1_MASK; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + + /* Clear all buffer interrupts. */ + base->EIMR &= ~intMask; + +/* Set the interrupt coalescence. */ +#if FSL_FEATURE_ENET_QUEUE > 1 + for (queue = 0; queue < FSL_FEATURE_ENET_QUEUE; queue++) + { + base->TXIC[queue] = ENET_TXIC_ICFT(config->intCoalesceCfg->txCoalesceFrameCount[queue]) | + config->intCoalesceCfg->txCoalesceTimeCount[queue] | ENET_TXIC_ICCS_MASK | + ENET_TXIC_ICEN_MASK; + base->RXIC[queue] = ENET_RXIC_ICFT(config->intCoalesceCfg->rxCoalesceFrameCount[queue]) | + config->intCoalesceCfg->rxCoalesceTimeCount[queue] | ENET_RXIC_ICCS_MASK | + ENET_RXIC_ICEN_MASK; + } +#else + base->TXIC = ENET_TXIC_ICFT(config->intCoalesceCfg->txCoalesceFrameCount[0]) | + config->intCoalesceCfg->txCoalesceTimeCount[0] | ENET_TXIC_ICCS_MASK | ENET_TXIC_ICEN_MASK; + base->RXIC = ENET_RXIC_ICFT(config->intCoalesceCfg->rxCoalesceFrameCount[0]) | + config->intCoalesceCfg->rxCoalesceTimeCount[0] | ENET_RXIC_ICCS_MASK | ENET_RXIC_ICEN_MASK; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } +#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ + ENET_EnableInterrupts(base, config->interrupt); + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* Sets the 1588 enhanced feature. */ + ecr |= ENET_ECR_EN1588_MASK; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* Enables Ethernet module after all configuration except the buffer descriptor active. */ + ecr |= ENET_ECR_ETHEREN_MASK | ENET_ECR_DBSWP_MASK; + base->ECR = ecr; +} + +static void ENET_SetTxBufferDescriptors(enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig) +{ + assert(config); + assert(bufferConfig); + + /* Default single ring is supported. */ + uint8_t ringNum; + uint32_t count; + uint32_t txBuffSizeAlign; + uint8_t *txBuffer; + const enet_buffer_config_t *buffCfg = bufferConfig; + + /* Check the input parameters. */ + for (ringNum = 0; ringNum < config->ringNum; ringNum++) + { + if ((buffCfg->txBdStartAddrAlign > 0) && (buffCfg->txBufferAlign > 0)) + { + volatile enet_tx_bd_struct_t *curBuffDescrip = buffCfg->txBdStartAddrAlign; + txBuffSizeAlign = buffCfg->txBuffSizeAlign; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + txBuffer = (uint8_t *)MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->txBufferAlign, kMEMORY_Local2DMA); +#else + txBuffer = buffCfg->txBufferAlign; +#endif + for (count = 0; count < buffCfg->txBdNumber; count++) + { + /* Set data buffer address. */ + curBuffDescrip->buffer = (uint8_t *)((uint32_t)&txBuffer[count * txBuffSizeAlign]); + /* Initializes data length. */ + curBuffDescrip->length = 0; + /* Sets the crc. */ + curBuffDescrip->control = ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK; + /* Sets the last buffer descriptor with the wrap flag. */ + if (count == buffCfg->txBdNumber - 1) + { + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_WRAP_MASK; + } + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* Enable transmit interrupt for store the transmit timestamp. */ + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_INTERRUPT_MASK; +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + /* Set the type of the frame when the credit-based scheme is used. */ + curBuffDescrip->controlExtend1 |= ENET_BD_FTYPE(ringNum); +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* Increase the index. */ + curBuffDescrip++; + } + } + buffCfg++; + } +} + +static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig) +{ + assert(config); + assert(bufferConfig); + + /* Default single ring is supported. */ + uint8_t ringNum; + uint32_t count; + uint32_t rxBuffSizeAlign; + uint8_t *rxBuffer; + const enet_buffer_config_t *buffCfg = bufferConfig; +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint32_t mask = (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Check the input parameters. */ + for (ringNum = 0; ringNum < config->ringNum; ringNum++) + { + assert(buffCfg->rxBuffSizeAlign >= ENET_RX_MIN_BUFFERSIZE); +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +#if FSL_FEATURE_ENET_QUEUE > 1 + if (ringNum == 1) + { + mask = (kENET_RxFrame1Interrupt | kENET_RxBuffer1Interrupt); + } + else if (ringNum == 2) + { + mask = (kENET_RxFrame2Interrupt | kENET_RxBuffer2Interrupt); + } +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + if ((buffCfg->rxBdStartAddrAlign > 0) && (buffCfg->rxBufferAlign > 0)) + { + volatile enet_rx_bd_struct_t *curBuffDescrip = buffCfg->rxBdStartAddrAlign; + rxBuffSizeAlign = buffCfg->rxBuffSizeAlign; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + rxBuffer = (uint8_t *)MEMORY_ConvertMemoryMapAddress((uint32_t)buffCfg->rxBufferAlign, kMEMORY_Local2DMA); +#else + rxBuffer = buffCfg->rxBufferAlign; +#endif + +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Invalidate rx buffers before DMA transfer data into them. */ + DCACHE_InvalidateByRange((uint32_t)rxBuffer, (buffCfg->rxBdNumber * rxBuffSizeAlign)); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + + for (count = 0; count < buffCfg->rxBdNumber; count++) + { + /* Set data buffer and the length. */ + curBuffDescrip->buffer = (uint8_t *)((uint32_t)&rxBuffer[count * rxBuffSizeAlign]); + curBuffDescrip->length = 0; + + /* Initializes the buffer descriptors with empty bit. */ + curBuffDescrip->control = ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + /* Sets the last buffer descriptor with the wrap flag. */ + if (count == buffCfg->rxBdNumber - 1) + { + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_RX_WRAP_MASK; + } + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + if (config->interrupt & mask) + { + /* Enable receive interrupt. */ + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_RX_INTERRUPT_MASK; + } + else + { + curBuffDescrip->controlExtend1 = 0; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* Increase the index. */ + curBuffDescrip++; + } + } + buffCfg++; + } +} + +static void ENET_ActiveSend(ENET_Type *base, uint32_t ringId) +{ + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + /* Ensure previous data update is completed with Data Synchronization Barrier before activing Tx BD. */ + __DSB(); + + switch (ringId) + { + case kENET_Ring0: + base->TDAR = ENET_TDAR_TDAR_MASK; + break; +#if FSL_FEATURE_ENET_QUEUE > 1 + case kENET_Ring1: + base->TDAR1 = ENET_TDAR1_TDAR_MASK; + break; + case kENET_Ring2: + base->TDAR2 = ENET_TDAR2_TDAR_MASK; + break; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + default: + base->TDAR = ENET_TDAR_TDAR_MASK; + break; + } +} + +/*! + * brief Sets the ENET MII speed and duplex. + * + * This API is provided to dynamically change the speed and dulpex for MAC. + * + * param base ENET peripheral base address. + * param speed The speed of the RMII mode. + * param duplex The duplex of the RMII mode. + */ +void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex) +{ + uint32_t rcr = base->RCR; + uint32_t tcr = base->TCR; + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + uint32_t ecr = base->ECR; + + if (kENET_MiiSpeed1000M == speed) + { + assert(duplex == kENET_MiiFullDuplex); + ecr |= ENET_ECR_SPEED_MASK; + } + else + { + ecr &= ~ENET_ECR_SPEED_MASK; + } + + base->ECR = ecr; +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + + /* Sets speed mode. */ + if (kENET_MiiSpeed10M == speed) + { + rcr |= ENET_RCR_RMII_10T_MASK; + } + else + { + rcr &= ~ENET_RCR_RMII_10T_MASK; + } + /* Set duplex mode. */ + if (duplex == kENET_MiiHalfDuplex) + { + rcr |= ENET_RCR_DRT_MASK; + tcr &= ~ENET_TCR_FDEN_MASK; + } + else + { + rcr &= ~ENET_RCR_DRT_MASK; + tcr |= ENET_TCR_FDEN_MASK; + } + + base->RCR = rcr; + base->TCR = tcr; +} + +/*! + * brief Sets the ENET module Mac address. + * + * param base ENET peripheral base address. + * param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ +void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr) +{ + uint32_t address; + + /* Set physical address lower register. */ + address = (uint32_t)(((uint32_t)macAddr[0] << 24U) | ((uint32_t)macAddr[1] << 16U) | ((uint32_t)macAddr[2] << 8U) | + (uint32_t)macAddr[3]); + base->PALR = address; + /* Set physical address high register. */ + address = (uint32_t)(((uint32_t)macAddr[4] << 8U) | ((uint32_t)macAddr[5])); + base->PAUR = address << ENET_PAUR_PADDR2_SHIFT; +} + +/*! + * brief Gets the ENET module Mac address. + * + * param base ENET peripheral base address. + * param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ +void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr) +{ + assert(macAddr); + + uint32_t address; + + /* Get from physical address lower register. */ + address = base->PALR; + macAddr[0] = 0xFFU & (address >> 24U); + macAddr[1] = 0xFFU & (address >> 16U); + macAddr[2] = 0xFFU & (address >> 8U); + macAddr[3] = 0xFFU & address; + + /* Get from physical address high register. */ + address = (base->PAUR & ENET_PAUR_PADDR2_MASK) >> ENET_PAUR_PADDR2_SHIFT; + macAddr[4] = 0xFFU & (address >> 8U); + macAddr[5] = 0xFFU & address; +} + +/*! + * brief Sets the ENET SMI(serial management interface)- MII management interface. + * + * param base ENET peripheral base address. + * param srcClock_Hz This is the ENET module clock frequency. Normally it's the system clock. See clock distribution. + * param isPreambleDisabled The preamble disable flag. + * - true Enables the preamble. + * - false Disables the preamble. + */ +void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled) +{ + assert(srcClock_Hz); + + uint32_t clkCycle = 0; + uint32_t speed = 0; + uint32_t mscr = 0; + + /* Calculate the MII speed which controls the frequency of the MDC. */ + speed = srcClock_Hz / (2 * ENET_MDC_FREQUENCY); + /* Calculate the hold time on the MDIO output. */ + clkCycle = (10 + ENET_NANOSECOND_ONE_SECOND / srcClock_Hz - 1) / (ENET_NANOSECOND_ONE_SECOND / srcClock_Hz) - 1; + /* Build the configuration for MDC/MDIO control. */ + mscr = + ENET_MSCR_MII_SPEED(speed) | ENET_MSCR_HOLDTIME(clkCycle) | (isPreambleDisabled ? ENET_MSCR_DIS_PRE_MASK : 0); + base->MSCR = mscr; +} + +/*! + * brief Starts an SMI write command. + * + * Used for standard IEEE802.3 MDIO Clause 22 format. + * + * param base ENET peripheral base address. + * param phyAddr The PHY address. + * param phyReg The PHY register. Range from 0 ~ 31. + * param operation The write operation. + * param data The data written to PHY. + */ +void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data) +{ + uint32_t mmfr = 0; + + /* Build MII write command. */ + mmfr = ENET_MMFR_ST(1) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(phyReg) | ENET_MMFR_TA(2) | + (data & 0xFFFF); + base->MMFR = mmfr; +} + +/*! + * brief Starts an SMI (Serial Management Interface) read command. + * + * Used for standard IEEE802.3 MDIO Clause 22 format. + * + * param base ENET peripheral base address. + * param phyAddr The PHY address. + * param phyReg The PHY register. Range from 0 ~ 31. + * param operation The read operation. + */ +void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation) +{ + uint32_t mmfr = 0; + + /* Build MII read command. */ + mmfr = ENET_MMFR_ST(1) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(phyReg) | ENET_MMFR_TA(2); + base->MMFR = mmfr; +} + +#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO +/*! + * brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI write command. + * + * param base ENET peripheral base address. + * param phyAddr The PHY address. + * param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, + * the phyReg is a 21-bits combination of the devaddr (5 bits device address) + * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. + * param data The data written to PHY. + */ +void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) +{ + uint32_t mmfr = 0; + + /* Parse the address from the input register. */ + uint16_t devAddr = (phyReg >> ENET_MMFR_TA_SHIFT) & 0x1FU; + uint16_t regAddr = (uint16_t)(phyReg & 0xFFFFU); + + /* Address write firstly. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr); + base->MMFR = mmfr; + + /* Build MII write command. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiWriteFrame_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2) | ENET_MMFR_DATA(data); + base->MMFR = mmfr; +} + +/*! + * brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI read command. + * + * param base ENET peripheral base address. + * param phyAddr The PHY address. + * param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, + * the phyReg is a 21-bits combination of the devaddr (5 bits device address) + * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. + */ +void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg) +{ + uint32_t mmfr = 0; + + /* Parse the address from the input register. */ + uint16_t devAddr = (phyReg >> ENET_MMFR_TA_SHIFT) & 0x1FU; + uint16_t regAddr = (uint16_t)(phyReg & 0xFFFFU); + + /* Address write firstly. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr); + base->MMFR = mmfr; + + /* Build MII read command. */ + mmfr = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiReadFrame_C45) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(devAddr) | + ENET_MMFR_TA(2); + base->MMFR = mmfr; +} +#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ + +/*! + * brief Gets the error statistics of a received frame for ENET single ring. + * + * This API must be called after the ENET_GetRxFrameSize and before the ENET_ReadFrame(). + * If the ENET_GetRxFrameSize returns kStatus_ENET_RxFrameError, + * the ENET_GetRxErrBeforeReadFrame can be used to get the exact error statistics. + * This is an example. + * code + * status = ENET_GetRxFrameSize(&g_handle, &length); + * if (status == kStatus_ENET_RxFrameError) + * { + * // Get the error information of the received frame. + * ENET_GetRxErrBeforeReadFrame(&g_handle, &eErrStatic); + * // update the receive buffer. + * ENET_ReadFrame(EXAMPLE_ENET, &g_handle, NULL, 0); + * } + * endcode + * param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. + * param eErrorStatic The error statistics structure pointer. + */ +void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic) +{ + assert(handle); + assert(handle->rxBdCurrent[0]); + assert(eErrorStatic); + + uint16_t control = 0; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[0]; + + do + { + /* The last buffer descriptor of a frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + control = curBuffDescrip->control; + if (control & ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK) + { + /* The receive truncate error. */ + eErrorStatic->statsRxTruncateErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK) + { + /* The receive over run error. */ + eErrorStatic->statsRxOverRunErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK) + { + /* The receive length violation error. */ + eErrorStatic->statsRxLenGreaterErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK) + { + /* The receive alignment error. */ + eErrorStatic->statsRxAlignErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_CRC_MASK) + { + /* The receive CRC error. */ + eErrorStatic->statsRxFcsErr++; + } +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint16_t controlExt = curBuffDescrip->controlExtend1; + if (controlExt & ENET_BUFFDESCRIPTOR_RX_MACERR_MASK) + { + /* The MAC error. */ + eErrorStatic->statsRxMacErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK) + { + /* The PHY error. */ + eErrorStatic->statsRxPhyErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK) + { + /* The receive collision error. */ + eErrorStatic->statsRxCollisionErr++; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + break; + } + + /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + curBuffDescrip = handle->rxBdBase[0]; + } + else + { + curBuffDescrip++; + } + + } while (curBuffDescrip != handle->rxBdCurrent[0]); +} + +/*! + * brief Gets the size of the read frame for single ring. + * + * This function gets a received frame size from the ENET buffer descriptors. + * note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. + * After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the + * receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". + * + * param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * param length The length of the valid frame received. + * retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame. + * retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data + * and NULL length to update the receive buffers. + * retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame + * should be called with the right data buffer and the captured data length input. + */ +status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length) +{ + assert(handle); + assert(handle->rxBdCurrent[0]); + assert(length); + + /* Reset the length to zero. */ + *length = 0; + + uint16_t validLastMask = ENET_BUFFDESCRIPTOR_RX_LAST_MASK | ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[0]; + + /* Check the current buffer descriptor's empty flag. if empty means there is no frame received. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK) + { + return kStatus_ENET_RxFrameEmpty; + } + + do + { + /* Add check for abnormal case. */ + if ((!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK)) && (!curBuffDescrip->length)) + { + return kStatus_ENET_RxFrameError; + } + + /* Find the last buffer descriptor. */ + if ((curBuffDescrip->control & validLastMask) == ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + /* The last buffer descriptor in the frame check the status of the received frame. */ + if ((curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_ERR_MASK) +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + || (curBuffDescrip->controlExtend1 & ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK) +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + ) + { + return kStatus_ENET_RxFrameError; + } + /* FCS is removed by MAC. */ + *length = curBuffDescrip->length; + return kStatus_Success; + } + /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + curBuffDescrip = handle->rxBdBase[0]; + } + else + { + curBuffDescrip++; + } + + } while (curBuffDescrip != handle->rxBdCurrent[0]); + + /* The frame is on processing - set to empty status to make application to receive it next time. */ + return kStatus_ENET_RxFrameEmpty; +} + +/*! + * brief Reads a frame from the ENET device for single ring. + * This function reads a frame (both the data and the length) from the ENET buffer descriptors. + * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer. + * This is an example: + * code + * uint32_t length; + * enet_handle_t g_handle; + * //Get the received frame size firstly. + * status = ENET_GetRxFrameSize(&g_handle, &length); + * if (length != 0) + * { + * //Allocate memory here with the size of "length" + * uint8_t *data = memory allocate interface; + * if (!data) + * { + * ENET_ReadFrame(ENET, &g_handle, NULL, 0); + * //Add the console warning log. + * } + * else + * { + * status = ENET_ReadFrame(ENET, &g_handle, data, length); + * //Call stack input API to deliver the data to stack + * } + * } + * else if (status == kStatus_ENET_RxFrameError) + * { + * //Update the received buffer when a error frame is received. + * ENET_ReadFrame(ENET, &g_handle, NULL, 0); + * } + * endcode + * param base ENET peripheral base address. + * param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * param data The data buffer provided by user to store the frame which memory size should be at least "length". + * param length The size of the data buffer which is still the length of the received frame. + * return The execute status, successful or failure. + */ +status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length) +{ + assert(handle); + assert(handle->rxBdCurrent[0]); + + uint32_t len = 0; + uint32_t offset = 0; + uint16_t control; + bool isLastBuff = false; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[0]; + status_t result = kStatus_Success; + uint32_t address; + + /* For data-NULL input, only update the buffer descriptor. */ + if (!data) + { + do + { + /* Update the control flag. */ + control = handle->rxBdCurrent[0]->control; + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, 0); + + /* Find the last buffer descriptor for the frame. */ + if (control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + break; + } + + } while (handle->rxBdCurrent[0] != curBuffDescrip); + + return result; + } + else + { +/* A frame on one buffer or several receive buffers are both considered. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache invalidate maintain. */ + DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + enet_ptp_time_data_t ptpTimestamp; + bool isPtpEventMessage = false; + /* Parse the PTP message according to the header message. */ + isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimestamp, false); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + while (!isLastBuff) + { + /* The last buffer descriptor of a frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + /* This is a valid frame. */ + isLastBuff = true; + if (length == curBuffDescrip->length) + { + /* Copy the frame to user's buffer without FCS. */ + len = curBuffDescrip->length - offset; + memcpy(data + offset, (void *)address, len); +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* Store the PTP 1588 timestamp for received PTP event frame. */ + if (isPtpEventMessage) + { + /* Set the timestamp to the timestamp ring. */ + ptpTimestamp.timeStamp.nanosecond = curBuffDescrip->timestamp; + result = ENET_StoreRxFrameTime(base, handle, &ptpTimestamp); + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, 0); + return result; + } + else + { + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, 0); + } + } + else + { + /* Store a frame on several buffer descriptors. */ + isLastBuff = false; + /* Length check. */ + if (offset >= length) + { + break; + } + + memcpy(data + offset, (void *)address, handle->rxBuffSizeAlign[0]); + offset += handle->rxBuffSizeAlign[0]; + + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, 0); + } + + /* Get the current buffer descriptor. */ + curBuffDescrip = handle->rxBdCurrent[0]; +/* Add the cache invalidate maintain. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + } + } + + return kStatus_ENET_RxFrameFail; +} + +static void ENET_UpdateReadBuffers(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) +{ + assert(handle); + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + /* Clears status. */ + handle->rxBdCurrent[ringId]->control &= ENET_BUFFDESCRIPTOR_RX_WRAP_MASK; + /* Sets the receive buffer descriptor with the empty flag. */ + handle->rxBdCurrent[ringId]->control |= ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + + /* Increase current buffer descriptor to the next one. */ + if (handle->rxBdCurrent[ringId]->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + handle->rxBdCurrent[ringId] = handle->rxBdBase[ringId]; + } + else + { + handle->rxBdCurrent[ringId]++; + } + + /* Ensure previous data update is completed with Data Synchronization Barrier before activing Rx BD. */ + __DSB(); + + /* Actives the receive buffer descriptor. */ + switch (ringId) + { + case kENET_Ring0: + base->RDAR = ENET_RDAR_RDAR_MASK; + break; +#if FSL_FEATURE_ENET_QUEUE > 1 + case kENET_Ring1: + base->RDAR1 = ENET_RDAR1_RDAR_MASK; + break; + case kENET_Ring2: + base->RDAR2 = ENET_RDAR2_RDAR_MASK; + break; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + default: + base->RDAR = ENET_RDAR_RDAR_MASK; + break; + } +} + +/*! + * brief Transmits an ENET frame for single ring. + * note The CRC is automatically appended to the data. Input the data + * to send without the CRC. + * + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. + * param data The data buffer provided by user to be send. + * param length The length of the data to be send. + * retval kStatus_Success Send frame succeed. + * retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. + * The transmit busy happens when the data send rate is over the MAC capacity. + * The waiting mechanism is recommended to be added after each call return with + * kStatus_ENET_TxFrameBusy. + */ +status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length) +{ + assert(handle); + assert(data); + + volatile enet_tx_bd_struct_t *curBuffDescrip; + uint32_t len = 0; + uint32_t sizeleft = 0; + uint32_t address; + + /* Check the frame length. */ + if (length > ENET_FRAME_MAX_FRAMELEN) + { + return kStatus_ENET_TxFrameOverLen; + } + + /* Check if the transmit buffer is ready. */ + curBuffDescrip = handle->txBdCurrent[0]; + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + bool isPtpEventMessage = false; + /* Check PTP message with the PTP header. */ + isPtpEventMessage = ENET_Ptp1588ParseFrame(data, NULL, true); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* One transmit buffer is enough for one frame. */ + if (handle->txBuffSizeAlign[0] >= length) + { +/* Copy data to the buffer for uDMA transfer. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + memcpy((void *)address, data, length); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + DCACHE_CleanByRange(address, length); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Set data length. */ + curBuffDescrip->length = length; +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* For enable the timestamp. */ + if (isPtpEventMessage) + { + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + else + { + curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK); + + /* Increase the buffer descriptor address. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent[0] = handle->txBdBase[0]; + } + else + { + handle->txBdCurrent[0]++; + } + /* Active the transmit buffer descriptor. */ + ENET_ActiveSend(base, 0); + + return kStatus_Success; + } + else + { + /* One frame requires more than one transmit buffers. */ + do + { +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* For enable the timestamp. */ + if (isPtpEventMessage) + { + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + else + { + curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Increase the buffer descriptor address. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent[0] = handle->txBdBase[0]; + } + else + { + handle->txBdCurrent[0]++; + } + /* update the size left to be transmit. */ + sizeleft = length - len; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + if (sizeleft > handle->txBuffSizeAlign[0]) + { + /* Data copy. */ + memcpy((void *)address, data + len, handle->txBuffSizeAlign[0]); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Data length update. */ + curBuffDescrip->length = handle->txBuffSizeAlign[0]; + len += handle->txBuffSizeAlign[0]; + /* Sets the control flag. */ + curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK; + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK; + /* Active the transmit buffer descriptor*/ + ENET_ActiveSend(base, 0); + } + else + { + memcpy((void *)address, data + len, sizeleft); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, sizeleft); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + curBuffDescrip->length = sizeleft; + /* Set Last buffer wrap flag. */ + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; + /* Active the transmit buffer descriptor. */ + ENET_ActiveSend(base, 0); + + return kStatus_Success; + } + + /* Get the current buffer descriptor address. */ + curBuffDescrip = handle->txBdCurrent[0]; + + } while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)); + + return kStatus_ENET_TxFrameBusy; + } +} + +#if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief Gets the error statistics of received frame for extended multi-ring. + * + * This API must be called after the ENET_GetRxFrameSizeMultiRing and before the ENET_ReadFrameMultiRing(). + * If the ENET_GetRxFrameSizeMultiRing returns kStatus_ENET_RxFrameError, + * the ENET_GetRxErrBeforeReadFrameMultiRing can be used to get the exact error statistics. + * + * param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. + * param eErrorStatic The error statistics structure pointer. + * param ringId The ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. + */ +void ENET_GetRxErrBeforeReadFrameMultiRing(enet_handle_t *handle, + enet_data_error_stats_t *eErrorStatic, + uint32_t ringId) +{ + assert(handle); + assert(eErrorStatic); + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + uint16_t control = 0; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[ringId]; + + do + { + /* The last buffer descriptor of a frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + control = curBuffDescrip->control; + if (control & ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK) + { + /* The receive truncate error. */ + eErrorStatic->statsRxTruncateErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK) + { + /* The receive over run error. */ + eErrorStatic->statsRxOverRunErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK) + { + /* The receive length violation error. */ + eErrorStatic->statsRxLenGreaterErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK) + { + /* The receive alignment error. */ + eErrorStatic->statsRxAlignErr++; + } + if (control & ENET_BUFFDESCRIPTOR_RX_CRC_MASK) + { + /* The receive CRC error. */ + eErrorStatic->statsRxFcsErr++; + } +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint16_t controlExt = curBuffDescrip->controlExtend1; + if (controlExt & ENET_BUFFDESCRIPTOR_RX_MACERR_MASK) + { + /* The MAC error. */ + eErrorStatic->statsRxMacErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK) + { + /* The PHY error. */ + eErrorStatic->statsRxPhyErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK) + { + /* The receive collision error. */ + eErrorStatic->statsRxCollisionErr++; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + break; + } + + /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + curBuffDescrip = handle->rxBdBase[ringId]; + } + else + { + curBuffDescrip++; + } + + } while (curBuffDescrip != handle->rxBdCurrent[ringId]); +} + +/*! + * brief Gets the size of the read frame for extended mutli-ring. + * + * This function gets a received frame size from the ENET buffer descriptors. + * note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. + * After calling ENET_GetRxFrameSizeMultiRing, ENET_ReadFrameMultiRing() should be called to update the + * receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". The usage is + * the same to the single ring, refer to ENET_GetRxFrameSize. + * + * param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * param length The length of the valid frame received. + * param ringId The ring index or ring number; + * retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrameMultiRing to read frame. + * retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrameMultiRing should be called with NULL data + * and NULL length to update the receive buffers. + * retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame + * should be called with the right data buffer and the captured data length input. + */ +status_t ENET_GetRxFrameSizeMultiRing(enet_handle_t *handle, uint32_t *length, uint32_t ringId) +{ + assert(handle); + assert(length); + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + /* Reset the length to zero. */ + *length = 0; + uint16_t validLastMask = ENET_BUFFDESCRIPTOR_RX_LAST_MASK | ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK; + volatile enet_rx_bd_struct_t *curBuffDescrip; + + curBuffDescrip = handle->rxBdCurrent[ringId]; + /* Check the current buffer descriptor's empty flag. if empty means there is no frame received. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK) + { + return kStatus_ENET_RxFrameEmpty; + } + + do + { + /* Add check for abnormal case. */ + if ((!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK)) && (!curBuffDescrip->length)) + { + return kStatus_ENET_RxFrameError; + } + /* Find the last buffer descriptor. */ + if ((curBuffDescrip->control & validLastMask) == ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + /* The last buffer descriptor in the frame check the status of the received frame. */ + if ((curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_ERR_MASK) +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + || (curBuffDescrip->controlExtend1 & ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK) +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + ) + { + return kStatus_ENET_RxFrameError; + } + /* FCS is removed by MAC. */ + *length = curBuffDescrip->length; + return kStatus_Success; + } + /* Increase the buffer descriptor, if it is the last one, increase to first one of the ring buffer. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_WRAP_MASK) + { + curBuffDescrip = handle->rxBdBase[ringId]; + } + else + { + curBuffDescrip++; + } + } while (curBuffDescrip != handle->rxBdCurrent[ringId]); + + /* The frame is on processing - set to empty status to make application to receive it next time. */ + return kStatus_ENET_RxFrameEmpty; +} + +/*! + * brief Reads a frame from the ENET device for multi-ring. + * + * This function reads a frame (both the data and the length) from the ENET buffer descriptors. + * The ENET_GetRxFrameSizeMultiRing should be used to get the size of the prepared data buffer. + * This usage is the same as the single ring, refer to ENET_ReadFrame. + + * param base ENET peripheral base address. + * param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * param data The data buffer provided by user to store the frame which memory size should be at least "length". + * param length The size of the data buffer which is still the length of the received frame. + * param ringId The ring index or ring number; + * return The execute status, successful or failure. + */ +status_t ENET_ReadFrameMultiRing( + ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId) +{ + assert(handle); + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + uint32_t len = 0; + uint32_t offset = 0; + uint16_t control; + bool isLastBuff = false; + volatile enet_rx_bd_struct_t *curBuffDescrip = handle->rxBdCurrent[ringId]; + status_t result = kStatus_Success; + uint32_t address; + + /* For data-NULL input, only update the buffer descriptor. */ + if (!data) + { + do + { + /* Update the control flag. */ + control = handle->rxBdCurrent[ringId]->control; + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, ringId); + + /* Find the last buffer descriptor for the frame. */ + if (control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + break; + } + + } while (handle->rxBdCurrent[ringId] != curBuffDescrip); + + return result; + } + else + { +/* A frame on one buffer or several receive buffers are both considered. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache invalidate maintain. */ + DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[ringId]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + enet_ptp_time_data_t ptpTimestamp; + bool isPtpEventMessage = false; + /* Parse the PTP message according to the header message. */ + isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimestamp, false); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + while (!isLastBuff) + { + /* The last buffer descriptor of a frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_RX_LAST_MASK) + { + /* This is a valid frame. */ + isLastBuff = true; + if (length == curBuffDescrip->length) + { + /* Copy the frame to user's buffer without FCS. */ + len = curBuffDescrip->length - offset; + memcpy(data + offset, (void *)address, len); +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* Store the PTP 1588 timestamp for received PTP event frame. */ + if (isPtpEventMessage) + { + /* Set the timestamp to the timestamp ring. */ + ptpTimestamp.timeStamp.nanosecond = curBuffDescrip->timestamp; + result = ENET_StoreRxFrameTime(base, handle, &ptpTimestamp); + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, ringId); + return result; + } + else + { + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, ringId); + } + } + else + { + /* Store a frame on several buffer descriptors. */ + isLastBuff = false; + /* Length check. */ + if (offset >= length) + { + break; + } + memcpy(data + offset, (void *)address, handle->rxBuffSizeAlign[ringId]); + offset += handle->rxBuffSizeAlign[ringId]; + + /* Updates the receive buffer descriptors. */ + ENET_UpdateReadBuffers(base, handle, ringId); + } + + /* Get the current buffer descriptor. */ + + curBuffDescrip = handle->rxBdCurrent[ringId]; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache invalidate maintain. */ + DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[ringId]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + } + } + + return kStatus_ENET_RxFrameFail; +} + +/*! + * brief Transmits an ENET frame for extended multi-ring. + * note The CRC is automatically appended to the data. Input the data + * to send without the CRC. + * + * In this API, multiple-ring are mainly used for extended avb frames are supported. + * The transmit scheme for avb frames is the credit-based scheme, the AVB class A, AVB class B + * and the non-AVB frame are transmitted in ring 1, ring 2 and ring 0 independently. + * So application should care about the transmit ring index when use multiple-ring transmission. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. + * param data The data buffer provided by user to be send. + * param length The length of the data to be send. + * param ringId The ring index for transmission. + * retval kStatus_Success Send frame succeed. + * retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. + * The transmit busy happens when the data send rate is over the MAC capacity. + * The waiting mechanism is recommended to be added after each call return with + * kStatus_ENET_TxFrameBusy. + */ +status_t ENET_SendFrameMultiRing( + ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId) +{ + assert(handle); + assert(data); + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + volatile enet_tx_bd_struct_t *curBuffDescrip; + uint32_t len = 0; + uint32_t sizeleft = 0; + uint32_t address; + + /* Check the frame length. */ + if (length > ENET_FRAME_MAX_FRAMELEN) + { + return kStatus_ENET_TxFrameOverLen; + } + + /* Check if the transmit buffer is ready. */ + curBuffDescrip = handle->txBdCurrent[ringId]; + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + bool isPtpEventMessage = false; + /* Check PTP message with the PTP header. */ + isPtpEventMessage = ENET_Ptp1588ParseFrame(data, NULL, true); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + /* One transmit buffer is enough for one frame. */ + if (handle->txBuffSizeAlign[ringId] >= length) + { +/* Copy data to the buffer for uDMA transfer. */ +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + memcpy((void *)address, data, length); + +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, length); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + + /* Set data length. */ + curBuffDescrip->length = length; +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* For enable the timestamp. */ + if (isPtpEventMessage) + { + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + else + { + curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + curBuffDescrip->control |= (ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK); + + /* Increase the buffer descriptor address. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent[ringId] = handle->txBdBase[ringId]; + } + else + { + handle->txBdCurrent[ringId]++; + } + + /* Active the transmit buffer descriptor. */ + ENET_ActiveSend(base, ringId); + + return kStatus_Success; + } + else + { + /* One frame requires more than one transmit buffers. */ + do + { +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + /* For enable the timestamp. */ + if (isPtpEventMessage) + { + curBuffDescrip->controlExtend1 |= ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } + else + { + curBuffDescrip->controlExtend1 &= ~ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK; + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Increase the buffer descriptor address. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdCurrent[ringId] = handle->txBdBase[ringId]; + } + else + { + handle->txBdCurrent[ringId]++; + } + /* update the size left to be transmit. */ + sizeleft = length - len; +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); +#else + address = (uint32_t)curBuffDescrip->buffer; +#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + if (sizeleft > handle->txBuffSizeAlign[ringId]) + { + /* Data copy. */ + memcpy((void *)address, data + len, handle->txBuffSizeAlign[ringId]); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, handle->txBuffSizeAlign[ringId]); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + /* Data length update. */ + curBuffDescrip->length = handle->txBuffSizeAlign[ringId]; + len += handle->txBuffSizeAlign[ringId]; + /* Sets the control flag. */ + curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK; + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK; + + /* Active the transmit buffer descriptor*/ + ENET_ActiveSend(base, ringId); + } + else + { + memcpy((void *)address, data + len, sizeleft); +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + /* Add the cache clean maintain. */ + DCACHE_CleanByRange(address, sizeleft); +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + curBuffDescrip->length = sizeleft; + /* Set Last buffer wrap flag. */ + curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK; + + /* Active the transmit buffer descriptor. */ + ENET_ActiveSend(base, ringId); + + return kStatus_Success; + } + + /* Get the current buffer descriptor address. */ + curBuffDescrip = handle->txBdCurrent[ringId]; + } while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)); + + return kStatus_ENET_TxFrameBusy; + } +} +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + +/*! + * brief Adds the ENET device to a multicast group. + * + * param base ENET peripheral base address. + * param address The six-byte multicast group address which is provided by application. + */ +void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address) +{ + assert(address); + + uint32_t crc = 0xFFFFFFFFU; + uint32_t count1 = 0; + uint32_t count2 = 0; + + /* Calculates the CRC-32 polynomial on the multicast group address. */ + for (count1 = 0; count1 < ENET_FRAME_MACLEN; count1++) + { + uint8_t c = address[count1]; + for (count2 = 0; count2 < 0x08U; count2++) + { + if ((c ^ crc) & 1U) + { + crc >>= 1U; + c >>= 1U; + crc ^= 0xEDB88320U; + } + else + { + crc >>= 1U; + c >>= 1U; + } + } + } + + /* Enable a multicast group address. */ + if (!((crc >> 0x1FU) & 1U)) + { + base->GALR |= 1U << ((crc >> 0x1AU) & 0x1FU); + } + else + { + base->GAUR |= 1U << ((crc >> 0x1AU) & 0x1FU); + } +} + +/*! + * brief Moves the ENET device from a multicast group. + * + * param base ENET peripheral base address. + * param address The six-byte multicast group address which is provided by application. + */ +void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address) +{ + assert(address); + + uint32_t crc = 0xFFFFFFFFU; + uint32_t count1 = 0; + uint32_t count2 = 0; + + /* Calculates the CRC-32 polynomial on the multicast group address. */ + for (count1 = 0; count1 < ENET_FRAME_MACLEN; count1++) + { + uint8_t c = address[count1]; + for (count2 = 0; count2 < 0x08U; count2++) + { + if ((c ^ crc) & 1U) + { + crc >>= 1U; + c >>= 1U; + crc ^= 0xEDB88320U; + } + else + { + crc >>= 1U; + c >>= 1U; + } + } + } + + /* Set the hash table. */ + if (!((crc >> 0x1FU) & 1U)) + { + base->GALR &= ~(1U << ((crc >> 0x1AU) & 0x1FU)); + } + else + { + base->GAUR &= ~(1U << ((crc >> 0x1AU) & 0x1FU)); + } +} + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * brief Gets the ENET transmit frame statistics after the data send for single ring. + * + * This interface gets the error statistics of the transmit frame. + * Because the error information is reported by the uDMA after the data delivery, this interface + * should be called after the data transmit API. It is recommended to call this function on + * transmit interrupt handler. After calling the ENET_SendFrame, the + * transmit interrupt notifies the transmit completion. + * + * param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. + * param eErrorStatic The error statistics structure pointer. + * return The execute status. + */ +status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic) +{ + assert(handle); + assert(eErrorStatic); + + uint16_t control = 0; + uint16_t controlExt = 0; + + do + { + /* Get the current dirty transmit buffer descriptor. */ + control = handle->txBdDirtyStatic[0]->control; + controlExt = handle->txBdDirtyStatic[0]->controlExtend0; + + /* Get the control status data, If the buffer descriptor has not been processed break out. */ + if (control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } + /* Increase the transmit dirty static pointer. */ + if (handle->txBdDirtyStatic[0]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdDirtyStatic[0] = handle->txBdBase[0]; + } + else + { + handle->txBdDirtyStatic[0]++; + } + + /* If the transmit buffer descriptor is ready and the last buffer descriptor, store packet statistic. */ + if (control & ENET_BUFFDESCRIPTOR_TX_LAST_MASK) + { + if (controlExt & ENET_BUFFDESCRIPTOR_TX_ERR_MASK) + { + /* Transmit error. */ + eErrorStatic->statsTxErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK) + { + /* Transmit excess collision error. */ + eErrorStatic->statsTxExcessCollisionErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK) + { + /* Transmit late collision error. */ + eErrorStatic->statsTxLateCollisionErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK) + { + /* Transmit under flow error. */ + eErrorStatic->statsTxUnderFlowErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK) + { + /* Transmit over flow error. */ + eErrorStatic->statsTxOverFlowErr++; + } + return kStatus_Success; + } + + } while (handle->txBdDirtyStatic[0] != handle->txBdCurrent[0]); + + return kStatus_ENET_TxFrameFail; +} + +#if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief Gets the ENET transmit frame statistics after the data send for extended multi-ring. + * + * This interface gets the error statistics of the transmit frame. + * Because the error information is reported by the uDMA after the data delivery, this interface + * should be called after the data transmit API and shall be called by transmit interrupt handler. + * After calling the ENET_SendFrame, the transmit interrupt notifies the transmit completion. + * + * param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. + * param eErrorStatic The error statistics structure pointer. + * param ringId The ring index. + * return The execute status. + */ +status_t ENET_GetTxErrAfterSendFrameMultiRing(enet_handle_t *handle, + enet_data_error_stats_t *eErrorStatic, + uint32_t ringId) +{ + assert(handle); + assert(eErrorStatic); + assert(ringId < FSL_FEATURE_ENET_QUEUE); + + uint16_t control = 0; + uint16_t controlExt = 0; + + do + { + /* Get the current dirty transmit buffer descriptor. */ + control = handle->txBdDirtyStatic[ringId]->control; + controlExt = handle->txBdDirtyStatic[ringId]->controlExtend0; + /* Get the control status data, If the buffer descriptor has not been processed break out. */ + if (control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } + /* Increase the transmit dirty static pointer. */ + if (handle->txBdDirtyStatic[ringId]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdDirtyStatic[ringId] = handle->txBdBase[ringId]; + } + else + { + handle->txBdDirtyStatic[ringId]++; + } + + /* If the transmit buffer descriptor is ready and the last buffer descriptor, store packet statistic. */ + if (control & ENET_BUFFDESCRIPTOR_TX_LAST_MASK) + { + if (controlExt & ENET_BUFFDESCRIPTOR_TX_ERR_MASK) + { + /* Transmit error. */ + eErrorStatic->statsTxErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK) + { + /* Transmit excess collision error. */ + eErrorStatic->statsTxExcessCollisionErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK) + { + /* Transmit late collision error. */ + eErrorStatic->statsTxLateCollisionErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK) + { + /* Transmit under flow error. */ + eErrorStatic->statsTxUnderFlowErr++; + } + if (controlExt & ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK) + { + /* Transmit over flow error. */ + eErrorStatic->statsTxOverFlowErr++; + } + return kStatus_Success; + } + + } while (handle->txBdDirtyStatic[ringId] != handle->txBdCurrent[ringId]); + + return kStatus_ENET_TxFrameFail; +} +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + +static bool ENET_Ptp1588ParseFrame(const uint8_t *data, enet_ptp_time_data_t *ptpTsData, bool isFastEnabled) +{ + assert(data); + if (!isFastEnabled) + { + assert(ptpTsData); + } + + bool isPtpMsg = false; + const uint8_t *buffer = data; + uint16_t ptpType; + + /* Check for VLAN frame. + * Add Double vlan tag check for receiving extended QIN vlan frame. */ + if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == (ENET_HTONS(ENET_8021QVLAN) +#if defined(FSL_FEATUR_ENET_HAS_AVB) && FSL_FEATURE_HAS_AVB + || ENET_HTONS(ENET_8021QSVLAN) +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + )) + { + buffer += ENET_FRAME_VLAN_TAGLEN; +#if defined(FSL_FEATUR_ENET_HAS_AVB) && FSL_FEATURE_HAS_AVB + if (*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET) == ENET_HTONS(ENET_8021QVLAN) + { + buffer += ENET_FRAME_VLAN_TAGLEN; + } +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + } + + ptpType = *(uint16_t *)(buffer + ENET_PTP1588_ETHL2_PACKETTYPE_OFFSET); + switch (ENET_HTONS(ptpType)) + { /* Ethernet layer 2. */ + case ENET_ETHERNETL2: + if ((*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET) & 0x0F) <= kENET_PtpEventMsgType) + { + isPtpMsg = true; + if (!isFastEnabled) + { + /* It's a ptpv2 message and store the ptp header information. */ + ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_VERSION_OFFSET)) & 0x0F; + ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET)) & 0x0F; + ptpTsData->sequenceId = ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_ETHL2_SEQUENCEID_OFFSET)); + memcpy((void *)&ptpTsData->sourcePortId[0], (void *)(buffer + ENET_PTP1588_ETHL2_CLOCKID_OFFSET), + kENET_PtpSrcPortIdLen); + } + } + break; + /* IPV4. */ + case ENET_IPV4: + if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV4VERSION) + { + if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) && + (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION)) + { + /* Set the PTP message flag. */ + isPtpMsg = true; + if (!isFastEnabled) + { + /* It's a IPV4 ptp message and store the ptp header information. */ + ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_VERSION_OFFSET)) & 0x0F; + ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV4_UDP_MSGTYPE_OFFSET)) & 0x0F; + ptpTsData->sequenceId = + ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV4_UDP_SEQUENCEID_OFFSET)); + memcpy((void *)&ptpTsData->sourcePortId[0], + (void *)(buffer + ENET_PTP1588_IPV4_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen); + } + } + } + break; + /* IPV6. */ + case ENET_IPV6: + if ((*(uint8_t *)(buffer + ENET_PTP1588_IPVERSION_OFFSET) >> 4) == ENET_IPV6VERSION) + { + if (((*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_PORT_OFFSET)) == ENET_HTONS(kENET_PtpEventPort)) && + (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_PROTOCOL_OFFSET) == ENET_UDPVERSION)) + { + /* Set the PTP message flag. */ + isPtpMsg = true; + if (!isFastEnabled) + { + /* It's a IPV6 ptp message and store the ptp header information. */ + ptpTsData->version = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_VERSION_OFFSET)) & 0x0F; + ptpTsData->messageType = (*(uint8_t *)(buffer + ENET_PTP1588_IPV6_UDP_MSGTYPE_OFFSET)) & 0x0F; + ptpTsData->sequenceId = + ENET_HTONS(*(uint16_t *)(buffer + ENET_PTP1588_IPV6_UDP_SEQUENCEID_OFFSET)); + memcpy((void *)&ptpTsData->sourcePortId[0], + (void *)(buffer + ENET_PTP1588_IPV6_UDP_CLKID_OFFSET), kENET_PtpSrcPortIdLen); + } + } + } + break; + default: + break; + } + return isPtpMsg; +} + +/*! + * brief Configures the ENET PTP IEEE 1588 feature with the basic configuration. + * The function sets the clock for PTP 1588 timer and enables + * time stamp interrupts and transmit interrupts for PTP 1588 features. + * This API should be called when the 1588 feature is enabled + * or the ENET_ENHANCEDBUFFERDESCRIPTOR_MODE is defined. + * ENET_Init should be called before calling this API. + * + * note The PTP 1588 time-stamp second increase though time-stamp interrupt handler + * and the transmit time-stamp store is done through transmit interrupt handler. + * As a result, the TS interrupt and TX interrupt are enabled when you call this API. + * + * param base ENET peripheral base address. + * param handle ENET handler pointer. + * param ptpConfig The ENET PTP1588 configuration. + */ +void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig) +{ + assert(handle); + assert(ptpConfig); + uint8_t count; + + uint32_t instance = ENET_GetInstance(base); + uint32_t mask = kENET_TxBufferInterrupt; +#if FSL_FEATURE_ENET_QUEUE > 1 + mask |= kENET_TxBuffer1Interrupt | kENET_TxBuffer2Interrupt; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + + /* Start the 1588 timer. */ + ENET_Ptp1588StartTimer(base, ptpConfig->ptp1588ClockSrc_Hz); + + for (count = 0; count < handle->ringNum; count++) + { + handle->txBdDirtyTime[count] = handle->txBdBase[count]; + handle->txBdDirtyStatic[count] = handle->txBdBase[count]; + } + + /* Setting the receive and transmit state for transaction. */ + handle->rxPtpTsDataRing.ptpTsData = ptpConfig->rxPtpTsData; + handle->rxPtpTsDataRing.size = ptpConfig->ptpTsRxBuffNum; + handle->rxPtpTsDataRing.front = 0; + handle->rxPtpTsDataRing.end = 0; + handle->txPtpTsDataRing.ptpTsData = ptpConfig->txPtpTsData; + handle->txPtpTsDataRing.size = ptpConfig->ptpTsTxBuffNum; + handle->txPtpTsDataRing.front = 0; + handle->txPtpTsDataRing.end = 0; + handle->msTimerSecond = 0; + + /* Set the IRQ handler when the interrupt is enabled. */ + s_enetTxIsr = ENET_TransmitIRQHandler; + s_enetTsIsr = ENET_Ptp1588TimerIRQHandler; + + /* Enables the time stamp interrupt and transmit frame interrupt to + * handle the time-stamp . */ + ENET_EnableInterrupts(base, (ENET_TS_INTERRUPT | ENET_TX_INTERRUPT)); + ENET_DisableInterrupts(base, mask); + + EnableIRQ(s_enetTsIrqId[instance]); + EnableIRQ(s_enetTxIrqId[instance]); +} + +/*! + * brief Starts the ENET PTP 1588 Timer. + * This function is used to initialize the PTP timer. After the PTP starts, + * the PTP timer starts running. + * + * param base ENET peripheral base address. + * param ptpClkSrc The clock source of the PTP timer. + */ +void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc) +{ + /* Restart PTP 1588 timer, master clock. */ + base->ATCR = ENET_ATCR_RESTART_MASK; + + /* Initializes PTP 1588 timer. */ + base->ATINC = ENET_ATINC_INC(ENET_NANOSECOND_ONE_SECOND / ptpClkSrc); + base->ATPER = ENET_NANOSECOND_ONE_SECOND; + /* Sets periodical event and the event signal output assertion and Actives PTP 1588 timer. */ + base->ATCR = ENET_ATCR_PEREN_MASK | ENET_ATCR_PINPER_MASK | ENET_ATCR_EN_MASK; +} + +/*! + * brief Gets the current ENET time from the PTP 1588 timer. + * + * param base ENET peripheral base address. + * param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * param ptpTime The PTP timer structure. + */ +void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime) +{ + assert(handle); + assert(ptpTime); + uint16_t count = ENET_1588TIME_DELAY_COUNT; + uint32_t primask; + + /* Disables the interrupt. */ + primask = DisableGlobalIRQ(); + + /* Get the current PTP time. */ + ptpTime->second = handle->msTimerSecond; + /* Get the nanosecond from the master timer. */ + base->ATCR |= ENET_ATCR_CAPTURE_MASK; + /* Add at least six clock cycle delay to get accurate time. + It's the requirement when the 1588 clock source is slower + than the register clock. + */ + while (count--) + { + __NOP(); + } + /* Get the captured time. */ + ptpTime->nanosecond = base->ATVR; + + /* Get PTP timer wrap event. */ + if (base->EIR & kENET_TsTimerInterrupt) + { + ptpTime->second++; + } + + /* Enables the interrupt. */ + EnableGlobalIRQ(primask); +} + +/*! + * brief Sets the ENET PTP 1588 timer to the assigned time. + * + * param base ENET peripheral base address. + * param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * param ptpTime The timer to be set to the PTP timer. + */ +void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime) +{ + assert(handle); + assert(ptpTime); + + uint32_t primask; + + /* Disables the interrupt. */ + primask = DisableGlobalIRQ(); + + /* Sets PTP timer. */ + handle->msTimerSecond = ptpTime->second; + base->ATVR = ptpTime->nanosecond; + + /* Enables the interrupt. */ + EnableGlobalIRQ(primask); +} + +/*! + * brief Adjusts the ENET PTP 1588 timer. + * + * param base ENET peripheral base address. + * param corrIncrease The correction increment value. This value is added every time the correction + * timer expires. A value less than the PTP timer frequency(1/ptpClkSrc) slows down the timer, + * a value greater than the 1/ptpClkSrc speeds up the timer. + * param corrPeriod The PTP timer correction counter wrap-around value. This defines after how + * many timer clock the correction counter should be reset and trigger a correction + * increment on the timer. A value of 0 disables the correction counter and no correction occurs. + */ +void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod) +{ + /* Set correction for PTP timer increment. */ + base->ATINC = (base->ATINC & ~ENET_ATINC_INC_CORR_MASK) | (corrIncrease << ENET_ATINC_INC_CORR_SHIFT); + /* Set correction for PTP timer period. */ + base->ATCOR = (base->ATCOR & ~ENET_ATCOR_COR_MASK) | (corrPeriod << ENET_ATCOR_COR_SHIFT); +} + +static status_t ENET_Ptp1588UpdateTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimeData) +{ + assert(ptpTsDataRing); + assert(ptpTsDataRing->ptpTsData); + assert(ptpTimeData); + + uint16_t usedBuffer = 0; + + /* Check if the buffers ring is full. */ + if (ptpTsDataRing->end >= ptpTsDataRing->front) + { + usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front; + } + else + { + usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end); + } + + if (usedBuffer == (ptpTsDataRing->size - 1)) + { + /* Ptp timestamp ring full, drop one in the front. */ + ptpTsDataRing->front = (ptpTsDataRing->front + 1) % ptpTsDataRing->size; + } + + /* Copy the new data into the buffer. */ + memcpy((ptpTsDataRing->ptpTsData + ptpTsDataRing->end), ptpTimeData, sizeof(enet_ptp_time_data_t)); + + /* Increase the buffer pointer to the next empty one. */ + ptpTsDataRing->end = (ptpTsDataRing->end + 1) % ptpTsDataRing->size; + + return kStatus_Success; +} + +static status_t ENET_Ptp1588SearchTimeRing(enet_ptp_time_data_ring_t *ptpTsDataRing, enet_ptp_time_data_t *ptpTimedata) +{ + assert(ptpTsDataRing); + assert(ptpTsDataRing->ptpTsData); + assert(ptpTimedata); + + uint32_t index; + uint32_t size; + uint16_t usedBuffer = 0; + bool isRingBufferFull = false; + + /* Check the PTP 1588 timestamp ring. */ + if (ptpTsDataRing->front == ptpTsDataRing->end) + { + return kStatus_ENET_PtpTsRingEmpty; + } + + /* Check if buffers is full. */ + if (ptpTsDataRing->end >= ptpTsDataRing->front) + { + usedBuffer = ptpTsDataRing->end - ptpTsDataRing->front; + } + else + { + usedBuffer = ptpTsDataRing->size - (ptpTsDataRing->front - ptpTsDataRing->end); + } + + if (usedBuffer == (ptpTsDataRing->size-1)) + { + isRingBufferFull = true; + } + + /* Search the element in the ring buffer */ + index = ptpTsDataRing->front; + size = ptpTsDataRing->size; + while (index != ptpTsDataRing->end) + { + if (((ptpTsDataRing->ptpTsData + index)->sequenceId == ptpTimedata->sequenceId) && + (!memcmp(((void *)&(ptpTsDataRing->ptpTsData + index)->sourcePortId[0]), + (void *)&ptpTimedata->sourcePortId[0], kENET_PtpSrcPortIdLen)) && + ((ptpTsDataRing->ptpTsData + index)->version == ptpTimedata->version) && + ((ptpTsDataRing->ptpTsData + index)->messageType == ptpTimedata->messageType)) + { + break; + } + + /* Increase the ptp ring index. */ + index = (index + 1) % size; + } + + if (index == ptpTsDataRing->end) + { + if (isRingBufferFull == true) + { + /* PTP timestamp buffer ring full, data in index ptpTsDataRing->end is valid. */ + if (((ptpTsDataRing->ptpTsData + index)->sequenceId != ptpTimedata->sequenceId) || + (memcmp(((void *)&(ptpTsDataRing->ptpTsData + index)->sourcePortId[0]), + (void *)&ptpTimedata->sourcePortId[0], kENET_PtpSrcPortIdLen)) || + ((ptpTsDataRing->ptpTsData + index)->version != ptpTimedata->version) || + ((ptpTsDataRing->ptpTsData + index)->messageType != ptpTimedata->messageType)) + { + return kStatus_ENET_PtpTsRingFull; + } + } + else + { + return kStatus_ENET_PtpTsRingFull; + } + } + + /* Get the right timestamp of the required ptp messag. */ + ptpTimedata->timeStamp.second = (ptpTsDataRing->ptpTsData + index)->timeStamp.second; + ptpTimedata->timeStamp.nanosecond = (ptpTsDataRing->ptpTsData + index)->timeStamp.nanosecond; + + if( isRingBufferFull == true) + { + /* If ring buffer full, move front pointer to next pointer behind end pointer, then next + read will still read whole ring. */ + ptpTsDataRing->end = index; + } + + /* Drop previous ptp stamp. */ + ptpTsDataRing->front = (index + 1) % size; + + return kStatus_Success; +} + +static status_t ENET_StoreRxFrameTime(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) +{ + assert(handle); + assert(ptpTimeData); + + enet_ptp_time_t ptpTimer; + + /* Get current PTP timer nanosecond value. */ + ENET_Ptp1588GetTimer(base, handle, &ptpTimer); + + /* Get transmit time stamp second. */ + if (ptpTimer.nanosecond >= ptpTimeData->timeStamp.nanosecond) + { + ptpTimeData->timeStamp.second = ptpTimer.second; + } + else + { + ptpTimeData->timeStamp.second = ptpTimer.second - 1; + } + + /* Store the timestamp to the receive time stamp ring. */ + /* Check if the buffers ring is full. */ + return ENET_Ptp1588UpdateTimeRing(&handle->rxPtpTsDataRing, ptpTimeData); +} + +static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) +{ + assert(handle); + + bool isPtpEventMessage = false; + enet_ptp_time_data_t ptpTimeData; + volatile enet_tx_bd_struct_t *curBuffDescrip; + volatile enet_tx_bd_struct_t *endBuffDescrip; + uint32_t address; + bool isReadLastBd = false; + bool readLastBd = false; + + /* Treat the txBdCurrent[ringId] as the tx bd write buffer pointer, + txBdDirtyTime[ringId] as the tx bd read buffer pointer. Considering + that the tx frame time read is driven by tx frame send, so the read + pointer txBdDirtyTime[ringId] should always behind write pointer + txBdDirtyTime[ringId]. Then if the read pointer equals write pointer, + we could treat the tx bd buffer is full. We could read out all + available bds. */ + if(handle->txBdDirtyTime[ringId] == handle->txBdCurrent[ringId]) + { + isReadLastBd = true; + if(handle->txBdDirtyTime[ringId] == handle->txBdBase[ringId]) + { + endBuffDescrip = handle->txBdDirtyTime[ringId] + 3; + } + else + { + endBuffDescrip = handle->txBdDirtyTime[ringId] - 1; + } + } + else + { + endBuffDescrip = handle->txBdCurrent[ringId]; + } + + /* Read tx bd buffer until read pointer txBdDirtyTime[ringId] equals to the end pointer of + tx bd buffer. */ + while((handle->txBdDirtyTime[ringId] != endBuffDescrip) || (readLastBd == true)) + { + curBuffDescrip = handle->txBdDirtyTime[ringId]; + + /* Get the control status data, If the buffer descriptor has not been processed break out. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK) + { + return kStatus_ENET_TxFrameBusy; + } + + /* Parse the PTP message. */ + #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET + address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer, kMEMORY_DMA2Local); + #else + address = (uint32_t)curBuffDescrip->buffer; + #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */ + isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimeData, false); + if (isPtpEventMessage) + { + /* Only store tx timestamp for ptp event message. */ + /* Increase current buffer descriptor to the next one. */ + if (handle->txBdDirtyTime[ringId]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdDirtyTime[ringId] = handle->txBdBase[ringId]; + } + else + { + handle->txBdDirtyTime[ringId]++; + } + + /* Do time stamp check on the last buffer descriptor of the frame. */ + if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_LAST_MASK) + { + /* Get current PTP timer nanosecond value. */ + ENET_Ptp1588GetTimer(base, handle, &ptpTimeData.timeStamp); + + /* Get transmit time stamp second. */ + if (ptpTimeData.timeStamp.nanosecond < curBuffDescrip->timestamp) + { + ptpTimeData.timeStamp.second--; + } + + /* Save transmit time stamp nanosecond. */ + ptpTimeData.timeStamp.nanosecond = curBuffDescrip->timestamp; + + /* Store the timestamp to the transmit timestamp ring. */ + ENET_Ptp1588UpdateTimeRing(&handle->txPtpTsDataRing, &ptpTimeData); + } + } + else + { + /* Only increase current buffer descriptor to the next one. */ + if (handle->txBdDirtyTime[ringId]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK) + { + handle->txBdDirtyTime[ringId] = handle->txBdBase[ringId]; + } + else + { + handle->txBdDirtyTime[ringId]++; + } + } + + if(readLastBd == true) + { + break; + } + + /* If if read pointer equals write pointer, the end pointer is set at the pointer before + current write pointer and the buffer in the end pointer is available, so read last bd at + the end pointer. */ + if((isReadLastBd == true) && (handle->txBdDirtyTime[ringId] == endBuffDescrip)) + { + readLastBd = true; + } + } + return kStatus_Success; +} + +/*! + * brief Gets the time stamp of the transmit frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * retval kStatus_Success Get 1588 timestamp success. + * retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ +status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) +{ + assert(handle); + assert(ptpTimeData); + + return ENET_Ptp1588SearchTimeRing(&handle->txPtpTsDataRing, ptpTimeData); +} + +/*! + * brief Gets the time stamp of the received frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * retval kStatus_Success Get 1588 timestamp success. + * retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ +status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData) +{ + assert(handle); + assert(ptpTimeData); + + return ENET_Ptp1588SearchTimeRing(&handle->rxPtpTsDataRing, ptpTimeData); +} + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +/*! + * brief Sets the ENET AVB feature. + * + * ENET AVB feature configuration, set the Receive classification match and transmit + * bandwidth. This API is called when the AVB feature is required. + * + * Note: The AVB frames transmission scheme is credit-based tx scheme and it's only supported + * with the Enhanced buffer descriptors. so the AVB configuration should only done with + * Enhanced buffer descriptor. so when the AVB feature is required, please make sure the + * the "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" is defined. + * + * param base ENET peripheral base address. + * param handle ENET handler pointer. + * param config The ENET AVB feature configuration structure. + */ +void ENET_AVBConfigure(ENET_Type *base, enet_handle_t *handle, const enet_avb_config_t *config) +{ + assert(config); + + uint8_t count = 0; + + for (count = 0; count < FSL_FEATURE_ENET_QUEUE - 1; count++) + { + /* Set the AVB receive ring classification match when the match is not 0. */ + if (config->rxClassifyMatch[count]) + { + base->RCMR[count] = (config->rxClassifyMatch[count] & 0xFFFF) | ENET_RCMR_MATCHEN_MASK; + } + /* Set the dma controller for the extended ring. */ + base->DMACFG[count] |= ENET_DMACFG_IDLE_SLOPE(config->idleSlope[count]); + } + + /* Shall use the credit-based scheme for avb. */ + base->QOS &= ~ENET_QOS_TX_SCHEME_MASK; + base->QOS |= ENET_QOS_RX_FLUSH0_MASK; +} +#endif /* FSL_FETAURE_ENET_HAS_AVB */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +#if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief The transmit IRQ handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ +void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) +#else +/*! + * brief The transmit IRQ handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ +void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle) +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +{ + assert(handle); + uint32_t mask = kENET_TxBufferInterrupt | kENET_TxFrameInterrupt; +#if defined(ENET_ENHANCEDBUFFERDESCRIPTOR_MODE) || (FSL_FEATURE_ENET_QUEUE > 1) + uint32_t index = 0; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTORMODE || (FSL_FEATURE_ENET_QUEUE > 1) */ + +/* Check if the transmit interrupt happen. */ +#if FSL_FEATURE_ENET_QUEUE > 1 + switch (ringId) + { + case kENET_Ring1: + mask = (kENET_TxFrame1Interrupt | kENET_TxBuffer1Interrupt); + break; + case kENET_Ring2: + mask = (kENET_TxFrame2Interrupt | kENET_TxBuffer2Interrupt); + break; + default: + break; + } + index = ringId; +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + + while (mask & base->EIR) + { +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + if (base->EIR & kENET_TxFrameInterrupt) + { + /* Store the transmit timestamp from the buffer descriptor should be done here. */ + ENET_StoreTxFrameTime(base, handle, index); + } +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + + /* Clear the transmit interrupt event. */ + base->EIR = mask; + + /* Callback function. */ + if (handle->callback) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + handle->callback(base, handle, index, kENET_TxEvent, handle->userData); +#else + handle->callback(base, handle, kENET_TxEvent, handle->userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + } +} + +#if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief The receive IRQ handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ +void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId) +#else +/*! + * brief The receive IRQ handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ +void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle) +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +{ + assert(handle); + uint32_t mask = kENET_RxFrameInterrupt | kENET_RxBufferInterrupt; + +/* Check if the receive interrupt happen. */ +#if FSL_FEATURE_ENET_QUEUE > 1 + switch (ringId) + { + case kENET_Ring1: + mask = (kENET_RxFrame1Interrupt | kENET_RxBuffer1Interrupt); + break; + case kENET_Ring2: + mask = (kENET_RxFrame2Interrupt | kENET_RxBuffer2Interrupt); + break; + default: + break; + } +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + + while (mask & base->EIR) + { + /* Clear the transmit interrupt event. */ + base->EIR = mask; + + /* Callback function. */ + if (handle->callback) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + handle->callback(base, handle, ringId, kENET_RxEvent, handle->userData); +#else + handle->callback(base, handle, kENET_RxEvent, handle->userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + } +} + +/*! + * brief Some special IRQ handler including the error, mii, wakeup irq handler. + * + * param base ENET peripheral base address. + * param handle The ENET handler pointer. + */ +void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle) +{ + assert(handle); + + uint32_t errMask = kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | kENET_PayloadRxInterrupt | + kENET_LateCollisionInterrupt | kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt; + + /* Check if the error interrupt happen. */ + if (kENET_WakeupInterrupt & base->EIR) + { + /* Clear the wakeup interrupt. */ + base->EIR = kENET_WakeupInterrupt; + /* wake up and enter the normal mode. */ + ENET_EnableSleepMode(base, false); + /* Callback function. */ + if (handle->callback) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + handle->callback(base, handle, 0, kENET_WakeUpEvent, handle->userData); +#else + handle->callback(base, handle, kENET_WakeUpEvent, handle->userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + } + else + { + /* Clear the error interrupt event status. */ + errMask &= base->EIR; + base->EIR = errMask; + /* Callback function. */ + if (handle->callback) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + handle->callback(base, handle, 0, kENET_ErrEvent, handle->userData); +#else + handle->callback(base, handle, kENET_ErrEvent, handle->userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * brief The IEEE 1588 PTP time stamp interrupt handler. + * + * param base ENET peripheral base address. + * param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + */ +void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle) +{ + assert(handle); + + /* Check if the PTP time stamp interrupt happen. */ + if (kENET_TsTimerInterrupt & base->EIR) + { + /* Clear the time stamp interrupt. */ + base->EIR = kENET_TsTimerInterrupt; + + /* Increase timer second counter. */ + handle->msTimerSecond++; + + /* Callback function. */ + if (handle->callback) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + handle->callback(base, handle, 0, kENET_TimeStampEvent, handle->userData); +#else + handle->callback(base, handle, kENET_TimeStampEvent, handle->userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + } + else + { + /* Clear the time stamp interrupt. */ + base->EIR = kENET_TsAvailInterrupt; + /* Callback function. */ + if (handle->callback) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + handle->callback(base, handle, 0, kENET_TimeStampAvailEvent, handle->userData); +#else + handle->callback(base, handle, kENET_TimeStampAvailEvent, handle->userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! + * brief the common IRQ handler for the tx/rx/error etc irq handler. + * + * This is used for the combined tx/rx/error interrupt for single/mutli-ring (frame 0). + * + * param base ENET peripheral base address. + */ +void ENET_CommonFrame0IRQHandler(ENET_Type *base) +{ + uint32_t event = base->EIR; + uint32_t instance = ENET_GetInstance(base); + + if (event & (kENET_TxBufferInterrupt | kENET_TxFrameInterrupt)) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + s_enetTxIsr(base, s_ENETHandle[instance], 0); +#else + s_enetTxIsr(base, s_ENETHandle[instance]); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + + if (event & (kENET_RxBufferInterrupt | kENET_RxFrameInterrupt)) + { +#if FSL_FEATURE_ENET_QUEUE > 1 + s_enetRxIsr(base, s_ENETHandle[instance], 0); +#else + s_enetRxIsr(base, s_ENETHandle[instance]); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + } + + if (event & ENET_TS_INTERRUPT) + { + s_enetTsIsr(base, s_ENETHandle[instance]); + } + if (event & ENET_ERR_INTERRUPT) + { + s_enetErrIsr(base, s_ENETHandle[instance]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * brief the common IRQ handler for the tx/rx irq handler. + * + * This is used for the combined tx/rx interrupt for multi-ring (frame 1). + * + * param base ENET peripheral base address. + */ +void ENET_CommonFrame1IRQHandler(ENET_Type *base) +{ + uint32_t event = base->EIR; + uint32_t instance = ENET_GetInstance(base); + + if (event & (kENET_TxBuffer1Interrupt | kENET_TxFrame1Interrupt)) + { + s_enetTxIsr(base, s_ENETHandle[instance], 1); + } + + if (event & (kENET_RxBuffer1Interrupt | kENET_RxFrame1Interrupt)) + { + s_enetRxIsr(base, s_ENETHandle[instance], 1); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +/*! + * brief the common IRQ handler for the tx/rx irq handler. + * + * This is used for the combined tx/rx interrupt for multi-ring (frame 2). + * + * param base ENET peripheral base address. + */ +void ENET_CommonFrame2IRQHandler(ENET_Type *base) +{ + uint32_t event = base->EIR; + uint32_t instance = ENET_GetInstance(base); + + if (event & (kENET_TxBuffer2Interrupt | kENET_TxFrame2Interrupt)) + { + s_enetTxIsr(base, s_ENETHandle[instance], 2); + } + + if (event & (kENET_RxBuffer2Interrupt | kENET_RxFrame2Interrupt)) + { + s_enetRxIsr(base, s_ENETHandle[instance], 2); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + +#if defined(ENET) +void ENET_Transmit_IRQHandler(void) +{ + s_enetTxIsr(ENET, s_ENETHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void ENET_Receive_IRQHandler(void) +{ + s_enetRxIsr(ENET, s_ENETHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void ENET_Error_IRQHandler(void) +{ + s_enetErrIsr(ENET, s_ENETHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void ENET_1588_Timer_IRQHandler(void) +{ + s_enetTsIsr(ENET, s_ENETHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void ENET_DriverIRQHandler(void) +{ + ENET_CommonFrame0IRQHandler(ENET); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#endif + +#if defined(ENET1) +void ENET1_DriverIRQHandler(void) +{ + ENET_CommonFrame0IRQHandler(ENET1); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ENET2) +void ENET2_DriverIRQHandler(void) +{ + ENET_CommonFrame0IRQHandler(ENET2); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CONNECTIVITY__ENET0) +void CONNECTIVITY_ENET0_FRAME0_EVENT_INT_DriverIRQHandler(void) +{ + ENET_CommonFrame0IRQHandler(CONNECTIVITY__ENET0); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#if FSL_FEATURE_ENET_QUEUE > 1 +void CONNECTIVITY_ENET0_FRAME1_INT_DriverIRQHandler(void) +{ + ENET_CommonFrame1IRQHandler(CONNECTIVITY__ENET0); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void CONNECTIVITY_ENET0_FRAME2_INT_DriverIRQHandler(void) +{ + ENET_CommonFrame2IRQHandler(CONNECTIVITY__ENET0); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif +#if defined(CONNECTIVITY__ENET1) +void CONNECTIVITY_ENET1_FRAME0_EVENT_INT_DriverIRQHandler(void) +{ + ENET_CommonFrame0IRQHandler(CONNECTIVITY__ENET1); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#if FSL_FEATURE_ENET_QUEUE > 1 +void CONNECTIVITY_ENET1_FRAME1_INT_DriverIRQHandler(void) +{ + ENET_CommonFrame1IRQHandler(CONNECTIVITY__ENET1); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void CONNECTIVITY_ENET1_FRAME2_INT_DriverIRQHandler(void) +{ + ENET_CommonFrame2IRQHandler(CONNECTIVITY__ENET1); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_enet.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_enet.h new file mode 100644 index 0000000000..1cc60b0b05 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_enet.h @@ -0,0 +1,1608 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_ENET_H_ +#define _FSL_ENET_H_ + +#include "fsl_common.h" +#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET +#include "fsl_memory.h" +#endif +/*! + * @addtogroup enet + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines the driver version. */ +#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 2, 4)) /*!< Version 2.2.4. */ +/*@}*/ + +/*! @name ENET DESCRIPTOR QUEUE */ +/*@{*/ +/*! @brief Defines the queue number. */ +#ifndef FSL_FEATURE_ENET_QUEUE +#define FSL_FEATURE_ENET_QUEUE 1 /* Singal queue for previous IP. */ +#endif +/*@}*/ + +/*! @name Control and status region bit masks of the receive buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK 0x8000U /*!< Empty bit mask. */ +#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER1_MASK 0x4000U /*!< Software owner one mask. */ +#define ENET_BUFFDESCRIPTOR_RX_WRAP_MASK 0x2000U /*!< Next buffer descriptor is the start address. */ +#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER2_Mask 0x1000U /*!< Software owner two mask. */ +#define ENET_BUFFDESCRIPTOR_RX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_MISS_MASK 0x0100U /*!< Received because of the promiscuous mode. */ +#define ENET_BUFFDESCRIPTOR_RX_BROADCAST_MASK 0x0080U /*!< Broadcast packet mask. */ +#define ENET_BUFFDESCRIPTOR_RX_MULTICAST_MASK 0x0040U /*!< Multicast packet mask. */ +#define ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK 0x0020U /*!< Length violation mask. */ +#define ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK 0x0010U /*!< Non-octet aligned frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_CRC_MASK 0x0004U /*!< CRC error mask. */ +#define ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK 0x0002U /*!< FIFO overrun mask. */ +#define ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK 0x0001U /*!< Frame is truncated mask. */ +/*@}*/ + +/*! @name Control and status bit masks of the transmit buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_TX_READY_MASK 0x8000U /*!< Ready bit mask. */ +#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER1_MASK 0x4000U /*!< Software owner one mask. */ +#define ENET_BUFFDESCRIPTOR_TX_WRAP_MASK 0x2000U /*!< Wrap buffer descriptor mask. */ +#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER2_MASK 0x1000U /*!< Software owner two mask. */ +#define ENET_BUFFDESCRIPTOR_TX_LAST_MASK 0x0800U /*!< Last BD of the frame mask. */ +#define ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK 0x0400U /*!< Transmit CRC mask. */ +/*@}*/ + +/* Extended control regions for enhanced buffer descriptors. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @name First extended control region bit masks of the receive buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_RX_IPV4_MASK 0x0001U /*!< Ipv4 frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_IPV6_MASK 0x0002U /*!< Ipv6 frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_VLAN_MASK 0x0004U /*!< VLAN frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_PROTOCOLCHECKSUM_MASK 0x0010U /*!< Protocol checksum error mask. */ +#define ENET_BUFFDESCRIPTOR_RX_IPHEADCHECKSUM_MASK 0x0020U /*!< IP header checksum error mask. */ +/*@}*/ + +/*! @name Second extended control region bit masks of the receive buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_RX_INTERRUPT_MASK 0x0080U /*!< BD interrupt mask. */ +#define ENET_BUFFDESCRIPTOR_RX_UNICAST_MASK 0x0100U /*!< Unicast frame mask. */ +#define ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK 0x0200U /*!< BD collision mask. */ +#define ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK 0x0400U /*!< PHY error mask. */ +#define ENET_BUFFDESCRIPTOR_RX_MACERR_MASK 0x8000U /*!< Mac error mask. */ +/*@}*/ + +/*! @name First extended control region bit masks of the transmit buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_TX_ERR_MASK 0x8000U /*!< Transmit error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK 0x2000U /*!< Underflow error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK 0x1000U /*!< Excess collision error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_FRAMEERR_MASK 0x0800U /*!< Frame error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK 0x0400U /*!< Late collision error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK 0x0200U /*!< Overflow error mask. */ +#define ENET_BUFFDESCRIPTOR_TX_TIMESTAMPERR_MASK 0x0100U /*!< Timestamp error mask. */ +/*@}*/ + +/*! @name Second extended control region bit masks of the transmit buffer descriptor. */ +/*@{*/ +#define ENET_BUFFDESCRIPTOR_TX_INTERRUPT_MASK 0x4000U /*!< Interrupt mask. */ +#define ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK 0x2000U /*!< Timestamp flag mask. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +#define ENET_BUFFDESCRIPTOR_TX_USETXLAUNCHTIME_MASK 0x0100U /*!< Use the transmit launch time. */ +#define ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_MASK 0x00F0U /*!< Frame type mask. */ +#define ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_SHIFT 4U /*!< Frame type shift. */ +#define ENET_BD_FTYPE(n) ((n << ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_SHIFT) & ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_MASK) +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +/*@}*/ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! @brief Defines the receive error status flag mask. */ +#define ENET_BUFFDESCRIPTOR_RX_ERR_MASK \ + (ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK | ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK | \ + ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK | ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK | ENET_BUFFDESCRIPTOR_RX_CRC_MASK) +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +#define ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK \ + (ENET_BUFFDESCRIPTOR_RX_MACERR_MASK | ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK | ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK) +#endif + +/*! @name Defines some Ethernet parameters. */ +/*@{*/ +#define ENET_FRAME_MAX_FRAMELEN 1518U /*!< Default maximum Ethernet frame size. */ + +#define ENET_FIFO_MIN_RX_FULL 5U /*!< ENET minimum receive FIFO full. */ +#define ENET_RX_MIN_BUFFERSIZE 256U /*!< ENET minimum buffer size. */ +#define ENET_PHY_MAXADDRESS (ENET_MMFR_PA_MASK >> ENET_MMFR_PA_SHIFT) +#if FSL_FEATURE_ENET_QUEUE > 1 +#define ENET_TX_INTERRUPT \ + (kENET_TxFrameInterrupt | kENET_TxBufferInterrupt | kENET_TxFrame1Interrupt | kENET_TxBuffer1Interrupt | \ + kENET_TxFrame2Interrupt | kENET_TxBuffer2Interrupt) +#define ENET_RX_INTERRUPT \ + (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt | kENET_RxFrame1Interrupt | kENET_RxBuffer1Interrupt | \ + kENET_RxFrame2Interrupt | kENET_RxBuffer2Interrupt) +#else +#define ENET_TX_INTERRUPT (kENET_TxFrameInterrupt | kENET_TxBufferInterrupt) +#define ENET_RX_INTERRUPT (kENET_RxFrameInterrupt | kENET_RxBufferInterrupt) +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ +#define ENET_TS_INTERRUPT (kENET_TsTimerInterrupt | kENET_TsAvailInterrupt) +#define ENET_ERR_INTERRUPT \ + (kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | kENET_LateCollisionInterrupt | \ + kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt | kENET_PayloadRxInterrupt) +#define ENET_ERR_INTERRUPT \ + (kENET_BabrInterrupt | kENET_BabtInterrupt | kENET_EBusERInterrupt | kENET_LateCollisionInterrupt | \ + kENET_RetryLimitInterrupt | kENET_UnderrunInterrupt | kENET_PayloadRxInterrupt) +/*@}*/ + +/*! @brief Defines the status return codes for transaction. */ +enum _enet_status +{ + kStatus_ENET_RxFrameError = MAKE_STATUS(kStatusGroup_ENET, 0U), /*!< A frame received but data error happen. */ + kStatus_ENET_RxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 1U), /*!< Failed to receive a frame. */ + kStatus_ENET_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET, 2U), /*!< No frame arrive. */ + kStatus_ENET_TxFrameOverLen = MAKE_STATUS(kStatusGroup_ENET, 3U), /*!< Tx frame over length. */ + kStatus_ENET_TxFrameBusy = MAKE_STATUS(kStatusGroup_ENET, 4U), /*!< Tx buffer descriptors are under process. */ + kStatus_ENET_TxFrameFail = MAKE_STATUS(kStatusGroup_ENET, 5U) /*!< Transmit frame fail. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + , + kStatus_ENET_PtpTsRingFull = MAKE_STATUS(kStatusGroup_ENET, 6U), /*!< Timestamp ring full. */ + kStatus_ENET_PtpTsRingEmpty = MAKE_STATUS(kStatusGroup_ENET, 7U) /*!< Timestamp ring empty. */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +}; + +/*! @brief Defines the MII/RMII/RGMII mode for data interface between the MAC and the PHY. */ +typedef enum _enet_mii_mode +{ + kENET_MiiMode = 0U, /*!< MII mode for data interface. */ + kENET_RmiiMode = 1U, /*!< RMII mode for data interface. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + kENET_RgmiiMode = 2U /*!< RGMII mode for data interface. */ +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +} enet_mii_mode_t; + +/*! @brief Defines the 10/100/1000 Mbps speed for the MII data interface. + * + * Notice: "kENET_MiiSpeed1000M" only supported when mii mode is "kENET_RgmiiMode". + */ +typedef enum _enet_mii_speed +{ + kENET_MiiSpeed10M = 0U, /*!< Speed 10 Mbps. */ + kENET_MiiSpeed100M = 1U, /*!< Speed 100 Mbps. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + kENET_MiiSpeed1000M = 2U /*!< Speed 1000M bps. */ +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +} enet_mii_speed_t; + +/*! @brief Defines the half or full duplex for the MII data interface. */ +typedef enum _enet_mii_duplex +{ + kENET_MiiHalfDuplex = 0U, /*!< Half duplex mode. */ + kENET_MiiFullDuplex /*!< Full duplex mode. */ +} enet_mii_duplex_t; + +/*! @brief Define the MII opcode for normal MDIO_CLAUSES_22 Frame. */ +typedef enum _enet_mii_write +{ + kENET_MiiWriteNoCompliant = 0U, /*!< Write frame operation, but not MII-compliant. */ + kENET_MiiWriteValidFrame /*!< Write frame operation for a valid MII management frame. */ +} enet_mii_write_t; + +/*! @brief Defines the read operation for the MII management frame. */ +typedef enum _enet_mii_read +{ + kENET_MiiReadValidFrame = 2U, /*!< Read frame operation for a valid MII management frame. */ + kENET_MiiReadNoCompliant = 3U /*!< Read frame operation, but not MII-compliant. */ +} enet_mii_read_t; + +#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO +/*! @brief Define the MII opcode for extended MDIO_CLAUSES_45 Frame. */ +typedef enum _enet_mii_extend_opcode +{ + kENET_MiiAddrWrite_C45 = 0U, /*!< Address Write operation. */ + kENET_MiiWriteFrame_C45 = 1U, /*!< Write frame operation for a valid MII management frame. */ + kENET_MiiReadFrame_C45 = 3U /*!< Read frame operation for a valid MII management frame. */ +} enet_mii_extend_opcode; +#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ + +/*! @brief Defines a special configuration for ENET MAC controller. + * + * These control flags are provided for special user requirements. + * Normally, these control flags are unused for ENET initialization. + * For special requirements, set the flags to + * macSpecialConfig in the enet_config_t. + * The kENET_ControlStoreAndFwdDisable is used to disable the FIFO store + * and forward. FIFO store and forward means that the FIFO read/send is started + * when a complete frame is stored in TX/RX FIFO. If this flag is set, + * configure rxFifoFullThreshold and txFifoWatermark + * in the enet_config_t. + */ +typedef enum _enet_special_control_flag +{ + kENET_ControlFlowControlEnable = 0x0001U, /*!< Enable ENET flow control: pause frame. */ + kENET_ControlRxPayloadCheckEnable = 0x0002U, /*!< Enable ENET receive payload length check. */ + kENET_ControlRxPadRemoveEnable = 0x0004U, /*!< Padding is removed from received frames. */ + kENET_ControlRxBroadCastRejectEnable = 0x0008U, /*!< Enable broadcast frame reject. */ + kENET_ControlMacAddrInsert = 0x0010U, /*!< Enable MAC address insert. */ + kENET_ControlStoreAndFwdDisable = 0x0020U, /*!< Enable FIFO store and forward. */ + kENET_ControlSMIPreambleDisable = 0x0040U, /*!< Enable SMI preamble. */ + kENET_ControlPromiscuousEnable = 0x0080U, /*!< Enable promiscuous mode. */ + kENET_ControlMIILoopEnable = 0x0100U, /*!< Enable ENET MII loop back. */ + kENET_ControlVLANTagEnable = 0x0200U, /*!< Enable normal VLAN (single vlan tag). */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + kENET_ControlSVLANEnable = 0x0400U, /*!< Enable S-VLAN. */ + kENET_ControlVLANUseSecondTag = 0x0800U /*!< Enable extracting the second vlan tag for further processing. */ +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +} enet_special_control_flag_t; + +/*! @brief List of interrupts supported by the peripheral. This + * enumeration uses one-bot encoding to allow a logical OR of multiple + * members. Members usually map to interrupt enable bits in one or more + * peripheral registers. + */ +typedef enum _enet_interrupt_enable +{ + kENET_BabrInterrupt = ENET_EIR_BABR_MASK, /*!< Babbling receive error interrupt source */ + kENET_BabtInterrupt = ENET_EIR_BABT_MASK, /*!< Babbling transmit error interrupt source */ + kENET_GraceStopInterrupt = ENET_EIR_GRA_MASK, /*!< Graceful stop complete interrupt source */ + kENET_TxFrameInterrupt = ENET_EIR_TXF_MASK, /*!< TX FRAME interrupt source */ + kENET_TxBufferInterrupt = ENET_EIR_TXB_MASK, /*!< TX BUFFER interrupt source */ + kENET_RxFrameInterrupt = ENET_EIR_RXF_MASK, /*!< RX FRAME interrupt source */ + kENET_RxBufferInterrupt = ENET_EIR_RXB_MASK, /*!< RX BUFFER interrupt source */ + kENET_MiiInterrupt = ENET_EIR_MII_MASK, /*!< MII interrupt source */ + kENET_EBusERInterrupt = ENET_EIR_EBERR_MASK, /*!< Ethernet bus error interrupt source */ + kENET_LateCollisionInterrupt = ENET_EIR_LC_MASK, /*!< Late collision interrupt source */ + kENET_RetryLimitInterrupt = ENET_EIR_RL_MASK, /*!< Collision Retry Limit interrupt source */ + kENET_UnderrunInterrupt = ENET_EIR_UN_MASK, /*!< Transmit FIFO underrun interrupt source */ + kENET_PayloadRxInterrupt = ENET_EIR_PLR_MASK, /*!< Payload Receive error interrupt source */ + kENET_WakeupInterrupt = ENET_EIR_WAKEUP_MASK, /*!< WAKEUP interrupt source */ +#if FSL_FEATURE_ENET_QUEUE > 1 + kENET_RxFlush2Interrupt = ENET_EIR_RXFLUSH_2_MASK, /*!< Rx DMA ring2 flush indication. */ + kENET_RxFlush1Interrupt = ENET_EIR_RXFLUSH_1_MASK, /*!< Rx DMA ring1 flush indication. */ + kENET_RxFlush0Interrupt = ENET_EIR_RXFLUSH_0_MASK, /*!< RX DMA ring0 flush indication. */ + kENET_TxFrame2Interrupt = ENET_EIR_TXF2_MASK, /*!< Tx frame interrupt for Tx ring/class 2. */ + kENET_TxBuffer2Interrupt = ENET_EIR_TXB2_MASK, /*!< Tx buffer interrupt for Tx ring/class 2. */ + kENET_RxFrame2Interrupt = ENET_EIR_RXF2_MASK, /*!< Rx frame interrupt for Rx ring/class 2. */ + kENET_RxBuffer2Interrupt = ENET_EIR_RXB2_MASK, /*!< Rx buffer interrupt for Rx ring/class 2. */ + kENET_TxFrame1Interrupt = ENET_EIR_TXF1_MASK, /*!< Tx frame interrupt for Tx ring/class 1. */ + kENET_TxBuffer1Interrupt = ENET_EIR_TXB1_MASK, /*!< Tx buffer interrupt for Tx ring/class 1. */ + kENET_RxFrame1Interrupt = ENET_EIR_RXF1_MASK, /*!< Rx frame interrupt for Rx ring/class 1. */ + kENET_RxBuffer1Interrupt = ENET_EIR_RXB1_MASK, /*!< Rx buffer interrupt for Rx ring/class 1. */ +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + kENET_TsAvailInterrupt = ENET_EIR_TS_AVAIL_MASK, /*!< TS AVAIL interrupt source for PTP */ + kENET_TsTimerInterrupt = ENET_EIR_TS_TIMER_MASK /*!< TS WRAP interrupt source for PTP */ +} enet_interrupt_enable_t; + +/*! @brief Defines the common interrupt event for callback use. */ +typedef enum _enet_event +{ + kENET_RxEvent, /*!< Receive event. */ + kENET_TxEvent, /*!< Transmit event. */ + kENET_ErrEvent, /*!< Error event: BABR/BABT/EBERR/LC/RL/UN/PLR . */ + kENET_WakeUpEvent, /*!< Wake up from sleep mode event. */ + kENET_TimeStampEvent, /*!< Time stamp event. */ + kENET_TimeStampAvailEvent /*!< Time stamp available event.*/ +} enet_event_t; + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +/*! @brief Defines certain idle slope for bandwidth fraction. */ +typedef enum _enet_idle_slope +{ + kENET_IdleSlope1 = 1U, /*!< The bandwidth fraction is about 0.002. */ + kENET_IdleSlope2 = 2U, /*!< The bandwidth fraction is about 0.003. */ + kENET_IdleSlope4 = 4U, /*!< The bandwidth fraction is about 0.008. */ + kENET_IdleSlope8 = 8U, /*!< The bandwidth fraction is about 0.02. */ + kENET_IdleSlope16 = 16U, /*!< The bandwidth fraction is about 0.03. */ + kENET_IdleSlope32 = 32U, /*!< The bandwidth fraction is about 0.06. */ + kENET_IdleSlope64 = 64U, /*!< The bandwidth fraction is about 0.11. */ + kENET_IdleSlope128 = 128U, /*!< The bandwidth fraction is about 0.20. */ + kENET_IdleSlope256 = 256U, /*!< The bandwidth fraction is about 0.33. */ + kENET_IdleSlope384 = 384U, /*!< The bandwidth fraction is about 0.43. */ + kENET_IdleSlope512 = 512U, /*!< The bandwidth fraction is about 0.50. */ + kENET_IdleSlope640 = 640U, /*!< The bandwidth fraction is about 0.56. */ + kENET_IdleSlope768 = 768U, /*!< The bandwidth fraction is about 0.60. */ + kENET_IdleSlope896 = 896U, /*!< The bandwidth fraction is about 0.64. */ + kENET_IdleSlope1024 = 1024U, /*!< The bandwidth fraction is about 0.67. */ + kENET_IdleSlope1152 = 1152U, /*!< The bandwidth fraction is about 0.69. */ + kENET_IdleSlope1280 = 1280U, /*!< The bandwidth fraction is about 0.71. */ + kENET_IdleSlope1408 = 1408U, /*!< The bandwidth fraction is about 0.73. */ + kENET_IdleSlope1536 = 1536U /*!< The bandwidth fraction is about 0.75. */ +} enet_idle_slope_t; +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + +/*! @brief Defines the transmit accelerator configuration. */ +typedef enum _enet_tx_accelerator +{ + kENET_TxAccelIsShift16Enabled = ENET_TACC_SHIFT16_MASK, /*!< Transmit FIFO shift-16. */ + kENET_TxAccelIpCheckEnabled = ENET_TACC_IPCHK_MASK, /*!< Insert IP header checksum. */ + kENET_TxAccelProtoCheckEnabled = ENET_TACC_PROCHK_MASK /*!< Insert protocol checksum. */ +} enet_tx_accelerator_t; + +/*! @brief Defines the receive accelerator configuration. */ +typedef enum _enet_rx_accelerator +{ + kENET_RxAccelPadRemoveEnabled = ENET_RACC_PADREM_MASK, /*!< Padding removal for short IP frames. */ + kENET_RxAccelIpCheckEnabled = ENET_RACC_IPDIS_MASK, /*!< Discard with wrong IP header checksum. */ + kENET_RxAccelProtoCheckEnabled = ENET_RACC_PRODIS_MASK, /*!< Discard with wrong protocol checksum. */ + kENET_RxAccelMacCheckEnabled = ENET_RACC_LINEDIS_MASK, /*!< Discard with Mac layer errors. */ + kENET_RxAccelisShift16Enabled = ENET_RACC_SHIFT16_MASK /*!< Receive FIFO shift-16. */ +} enet_rx_accelerator_t; + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @brief Defines the ENET PTP message related constant. */ +typedef enum _enet_ptp_event_type +{ + kENET_PtpEventMsgType = 3U, /*!< PTP event message type. */ + kENET_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */ + kENET_PtpEventPort = 319U, /*!< PTP event port number. */ + kENET_PtpGnrlPort = 320U /*!< PTP general port number. */ +} enet_ptp_event_type_t; + +/*! @brief Defines the IEEE 1588 PTP timer channel numbers. */ +typedef enum _enet_ptp_timer_channel +{ + kENET_PtpTimerChannel1 = 0U, /*!< IEEE 1588 PTP timer Channel 1. */ + kENET_PtpTimerChannel2, /*!< IEEE 1588 PTP timer Channel 2. */ + kENET_PtpTimerChannel3, /*!< IEEE 1588 PTP timer Channel 3. */ + kENET_PtpTimerChannel4 /*!< IEEE 1588 PTP timer Channel 4. */ +} enet_ptp_timer_channel_t; + +/*! @brief Defines the capture or compare mode for IEEE 1588 PTP timer channels. */ +typedef enum _enet_ptp_timer_channel_mode +{ + kENET_PtpChannelDisable = 0U, /*!< Disable timer channel. */ + kENET_PtpChannelRisingCapture = 1U, /*!< Input capture on rising edge. */ + kENET_PtpChannelFallingCapture = 2U, /*!< Input capture on falling edge. */ + kENET_PtpChannelBothCapture = 3U, /*!< Input capture on both edges. */ + kENET_PtpChannelSoftCompare = 4U, /*!< Output compare software only. */ + kENET_PtpChannelToggleCompare = 5U, /*!< Toggle output on compare. */ + kENET_PtpChannelClearCompare = 6U, /*!< Clear output on compare. */ + kENET_PtpChannelSetCompare = 7U, /*!< Set output on compare. */ + kENET_PtpChannelClearCompareSetOverflow = 10U, /*!< Clear output on compare, set output on overflow. */ + kENET_PtpChannelSetCompareClearOverflow = 11U, /*!< Set output on compare, clear output on overflow. */ + kENET_PtpChannelPulseLowonCompare = 14U, /*!< Pulse output low on compare for one IEEE 1588 clock cycle. */ + kENET_PtpChannelPulseHighonCompare = 15U /*!< Pulse output high on compare for one IEEE 1588 clock cycle. */ +} enet_ptp_timer_channel_mode_t; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! @brief Defines the receive buffer descriptor structure for the little endian system.*/ +typedef struct _enet_rx_bd_struct +{ + uint16_t length; /*!< Buffer descriptor data length. */ + uint16_t control; /*!< Buffer descriptor control and status. */ + uint8_t *buffer; /*!< Data buffer pointer. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ + uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ + uint16_t payloadCheckSum; /*!< Internal payload checksum. */ + uint8_t headerLength; /*!< Header length. */ + uint8_t protocolTyte; /*!< Protocol type. */ + uint16_t reserved0; + uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ + uint32_t timestamp; /*!< Timestamp. */ + uint16_t reserved1; + uint16_t reserved2; + uint16_t reserved3; + uint16_t reserved4; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_rx_bd_struct_t; + +/*! @brief Defines the enhanced transmit buffer descriptor structure for the little endian system. */ +typedef struct _enet_tx_bd_struct +{ + uint16_t length; /*!< Buffer descriptor data length. */ + uint16_t control; /*!< Buffer descriptor control and status. */ + uint8_t *buffer; /*!< Data buffer pointer. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint16_t controlExtend0; /*!< Extend buffer descriptor control0. */ + uint16_t controlExtend1; /*!< Extend buffer descriptor control1. */ +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB + int8_t *txLaunchTime; /*!< Transmit launch time. */ +#else + uint16_t reserved0; + uint16_t reserved1; +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + uint16_t reserved2; + uint16_t controlExtend2; /*!< Extend buffer descriptor control2. */ + uint32_t timestamp; /*!< Timestamp. */ + uint16_t reserved3; + uint16_t reserved4; + uint16_t reserved5; + uint16_t reserved6; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_tx_bd_struct_t; + +/*! @brief Defines the ENET data error statistics structure. */ +typedef struct _enet_data_error_stats +{ + uint32_t statsRxLenGreaterErr; /*!< Receive length greater than RCR[MAX_FL]. */ + uint32_t statsRxAlignErr; /*!< Receive non-octet alignment/ */ + uint32_t statsRxFcsErr; /*!< Receive CRC error. */ + uint32_t statsRxOverRunErr; /*!< Receive over run. */ + uint32_t statsRxTruncateErr; /*!< Receive truncate. */ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + uint32_t statsRxProtocolChecksumErr; /*!< Receive protocol checksum error. */ + uint32_t statsRxIpHeadChecksumErr; /*!< Receive IP header checksum error. */ + uint32_t statsRxMacErr; /*!< Receive Mac error. */ + uint32_t statsRxPhyErr; /*!< Receive PHY error. */ + uint32_t statsRxCollisionErr; /*!< Receive collision. */ + uint32_t statsTxErr; /*!< The error happen when transmit the frame. */ + uint32_t statsTxFrameErr; /*!< The transmit frame is error. */ + uint32_t statsTxOverFlowErr; /*!< Transmit overflow. */ + uint32_t statsTxLateCollisionErr; /*!< Transmit late collision. */ + uint32_t statsTxExcessCollisionErr; /*!< Transmit excess collision.*/ + uint32_t statsTxUnderFlowErr; /*!< Transmit under flow error. */ + uint32_t statsTxTsErr; /*!< Transmit time stamp error. */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +} enet_data_error_stats_t; + +/*! @brief Defines the receive buffer descriptor configuration structure. + * + * Note that for the internal DMA requirements, the buffers have a corresponding alignment requirements. + * 1. The aligned receive and transmit buffer size must be evenly divisible by ENET_BUFF_ALIGNMENT. + * when the data buffers are in cacheable region when cache is enabled, all those size should be + * aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size. + * 2. The aligned transmit and receive buffer descriptor start address must be at + * least 64 bit aligned. However, it's recommended to be evenly divisible by ENET_BUFF_ALIGNMENT. + * buffer descriptors should be put in non-cacheable region when cache is enabled. + * 3. The aligned transmit and receive data buffer start address must be evenly divisible by ENET_BUFF_ALIGNMENT. + * Receive buffers should be continuous with the total size equal to "rxBdNumber * rxBuffSizeAlign". + * Transmit buffers should be continuous with the total size equal to "txBdNumber * txBuffSizeAlign". + * when the data buffers are in cacheable region when cache is enabled, all those size should be + * aligned to the maximum value of "ENET_BUFF_ALIGNMENT" and the cache line size. + */ +typedef struct _enet_buffer_config +{ + uint16_t rxBdNumber; /*!< Receive buffer descriptor number. */ + uint16_t txBdNumber; /*!< Transmit buffer descriptor number. */ + uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */ + uint32_t txBuffSizeAlign; /*!< Aligned transmit data buffer size. */ + volatile enet_rx_bd_struct_t + *rxBdStartAddrAlign; /*!< Aligned receive buffer descriptor start address: should be non-cacheable. */ + volatile enet_tx_bd_struct_t + *txBdStartAddrAlign; /*!< Aligned transmit buffer descriptor start address: should be non-cacheable. */ + uint8_t *rxBufferAlign; /*!< Receive data buffer start address. */ + uint8_t *txBufferAlign; /*!< Transmit data buffer start address. */ +} enet_buffer_config_t; + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! @brief Defines the ENET PTP time stamp structure. */ +typedef struct _enet_ptp_time +{ + uint64_t second; /*!< Second. */ + uint32_t nanosecond; /*!< Nanosecond. */ +} enet_ptp_time_t; + +/*! @brief Defines the structure for the ENET PTP message data and timestamp data.*/ +typedef struct _enet_ptp_time_data +{ + uint8_t version; /*!< PTP version. */ + uint8_t sourcePortId[kENET_PtpSrcPortIdLen]; /*!< PTP source port ID. */ + uint16_t sequenceId; /*!< PTP sequence ID. */ + uint8_t messageType; /*!< PTP message type. */ + enet_ptp_time_t timeStamp; /*!< PTP timestamp. */ +} enet_ptp_time_data_t; + +/*! @brief Defines the ENET PTP ring buffer structure for the PTP message timestamp store.*/ +typedef struct _enet_ptp_time_data_ring +{ + uint32_t front; /*!< The first index of the ring. */ + uint32_t end; /*!< The end index of the ring. */ + uint32_t size; /*!< The size of the ring. */ + enet_ptp_time_data_t *ptpTsData; /*!< PTP message data structure. */ +} enet_ptp_time_data_ring_t; + +/*! @brief Defines the ENET PTP configuration structure. */ +typedef struct _enet_ptp_config +{ + uint8_t ptpTsRxBuffNum; /*!< Receive 1588 timestamp buffer number*/ + uint8_t ptpTsTxBuffNum; /*!< Transmit 1588 timestamp buffer number*/ + enet_ptp_time_data_t *rxPtpTsData; /*!< The start address of 1588 receive timestamp buffers */ + enet_ptp_time_data_t *txPtpTsData; /*!< The start address of 1588 transmit timestamp buffers */ + enet_ptp_timer_channel_t channel; /*!< Used for ERRATA_2579: the PTP 1588 timer channel for time interrupt. */ + uint32_t ptp1588ClockSrc_Hz; /*!< The clock source of the PTP 1588 timer. */ +} enet_ptp_config_t; +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE +/*! @brief Defines the interrupt coalescing configure structure. */ +typedef struct _enet_intcoalesce_config +{ + uint8_t txCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing frame count threshold. */ + uint16_t txCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit interrupt coalescing timer count threshold. */ + uint8_t rxCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing frame count threshold. */ + uint16_t rxCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; /*!< Receive interrupt coalescing timer count threshold. */ +} enet_intcoalesce_config_t; +#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +/*! @brief Defines the ENET AVB Configure structure. + * + * This is used for to configure the extended ring 1 and ring 2. + * 1. The classification match format is (CMP3 << 12) | (CMP2 << 8) | (CMP1 << 4) | CMP0. + * composed of four 3-bit compared VLAN priority field cmp0~cmp3, cm0 ~ cmp3 are used in parallel. + * + * If CMP1,2,3 are not unused, please set them to the same value as CMP0. + * 2. The idleSlope is used to calculate the Band Width fraction, BW fraction = 1 / (1 + 512/idleSlope). + * For avb configuration, the BW fraction of Class 1 and Class 2 combined must not exceed 0.75. + */ +typedef struct _enet_avb_config +{ + uint16_t rxClassifyMatch[FSL_FEATURE_ENET_QUEUE - 1]; /*!< The classification match value for the ring. */ + enet_idle_slope_t idleSlope[FSL_FEATURE_ENET_QUEUE - 1]; /*!< The idle slope for certian bandwidth fraction. */ +} enet_avb_config_t; +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + +/*! @brief Defines the basic configuration structure for the ENET device. + * + * Note: + * 1. macSpecialConfig is used for a special control configuration, A logical OR of + * "enet_special_control_flag_t". For a special configuration for MAC, + * set this parameter to 0. + * 2. txWatermark is used for a cut-through operation. It is in steps of 64 bytes: + * 0/1 - 64 bytes written to TX FIFO before transmission of a frame begins. + * 2 - 128 bytes written to TX FIFO .... + * 3 - 192 bytes written to TX FIFO .... + * The maximum of txWatermark is 0x2F - 4032 bytes written to TX FIFO .... + * txWatermark allows minimizing the transmit latency to set the txWatermark to 0 or 1 + * or for larger bus access latency 3 or larger due to contention for the system bus. + * 3. rxFifoFullThreshold is similar to the txWatermark for cut-through operation in RX. + * It is in 64-bit words. The minimum is ENET_FIFO_MIN_RX_FULL and the maximum is 0xFF. + * If the end of the frame is stored in FIFO and the frame size if smaller than the + * txWatermark, the frame is still transmitted. The rule is the + * same for rxFifoFullThreshold in the receive direction. + * 4. When "kENET_ControlFlowControlEnable" is set in the macSpecialConfig, ensure + * that the pauseDuration, rxFifoEmptyThreshold, and rxFifoStatEmptyThreshold + * are set for flow control enabled case. + * 5. When "kENET_ControlStoreAndFwdDisabled" is set in the macSpecialConfig, ensure + * that the rxFifoFullThreshold and txFifoWatermark are set for store and forward disable. + * 6. The rxAccelerConfig and txAccelerConfig default setting with 0 - accelerator + * are disabled. The "enet_tx_accelerator_t" and "enet_rx_accelerator_t" are + * recommended to be used to enable the transmit and receive accelerator. + * After the accelerators are enabled, the store and forward feature should be enabled. + * As a result, kENET_ControlStoreAndFwdDisabled should not be set. + * 7. The intCoalesceCfg can be used in the rx or tx enabled cases to decrese the CPU loading. + */ +typedef struct _enet_config +{ + uint32_t macSpecialConfig; /*!< Mac special configuration. A logical OR of "enet_special_control_flag_t". */ + uint32_t interrupt; /*!< Mac interrupt source. A logical OR of "enet_interrupt_enable_t". */ + uint16_t rxMaxFrameLen; /*!< Receive maximum frame length. */ + enet_mii_mode_t miiMode; /*!< MII mode. */ + enet_mii_speed_t miiSpeed; /*!< MII Speed. */ + enet_mii_duplex_t miiDuplex; /*!< MII duplex. */ + uint8_t rxAccelerConfig; /*!< Receive accelerator, A logical OR of "enet_rx_accelerator_t". */ + uint8_t txAccelerConfig; /*!< Transmit accelerator, A logical OR of "enet_rx_accelerator_t". */ + uint16_t pauseDuration; /*!< For flow control enabled case: Pause duration. */ + uint8_t rxFifoEmptyThreshold; /*!< For flow control enabled case: when RX FIFO level reaches this value, + it makes MAC generate XOFF pause frame. */ +#if defined(FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD + uint8_t rxFifoStatEmptyThreshold; /*!< For flow control enabled case: number of frames in the receive FIFO, + independent of size, that can be accept. If the limit is reached, reception + continues and a pause frame is triggered. */ +#endif /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */ + uint8_t rxFifoFullThreshold; /*!< For store and forward disable case, the data required in RX FIFO to notify + the MAC receive ready status. */ + uint8_t txFifoWatermark; /*!< For store and forward disable case, the data required in TX FIFO + before a frame transmit start. */ +#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE + enet_intcoalesce_config_t *intCoalesceCfg; /* If the interrupt coalsecence is not required in the ring n(0,1,2), + please set to NULL. */ +#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */ + uint8_t ringNum; /*!< Number of used rings. default with 1 -- single ring. */ +} enet_config_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _enet_handle enet_handle_t; + +/*! @brief ENET callback function. */ +#if FSL_FEATURE_ENET_QUEUE > 1 +typedef void (*enet_callback_t)( + ENET_Type *base, enet_handle_t *handle, uint32_t ringId, enet_event_t event, void *userData); +#else +typedef void (*enet_callback_t)(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *userData); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + +/*! @brief Defines the ENET handler structure. */ +struct _enet_handle +{ + volatile enet_rx_bd_struct_t + *rxBdBase[FSL_FEATURE_ENET_QUEUE]; /*!< Receive buffer descriptor base address pointer. */ + volatile enet_rx_bd_struct_t + *rxBdCurrent[FSL_FEATURE_ENET_QUEUE]; /*!< The current available receive buffer descriptor pointer. */ + volatile enet_tx_bd_struct_t + *txBdBase[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit buffer descriptor base address pointer. */ + volatile enet_tx_bd_struct_t + *txBdCurrent[FSL_FEATURE_ENET_QUEUE]; /*!< The current available transmit buffer descriptor pointer. */ + uint32_t rxBuffSizeAlign[FSL_FEATURE_ENET_QUEUE]; /*!< Receive buffer size alignment. */ + uint32_t txBuffSizeAlign[FSL_FEATURE_ENET_QUEUE]; /*!< Transmit buffer size alignment. */ + uint8_t ringNum; /*!< Number of used rings. */ + enet_callback_t callback; /*!< Callback function. */ + void *userData; /*!< Callback function parameter.*/ +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE + volatile enet_tx_bd_struct_t + *txBdDirtyStatic[FSL_FEATURE_ENET_QUEUE]; /*!< The dirty transmit buffer descriptor for error static update. */ + volatile enet_tx_bd_struct_t + *txBdDirtyTime[FSL_FEATURE_ENET_QUEUE]; /*!< The dirty transmit buffer descriptor for time stamp update. */ + uint64_t msTimerSecond; /*!< The second for Master PTP timer .*/ + enet_ptp_time_data_ring_t rxPtpTsDataRing; /*!< Receive PTP 1588 time stamp data ring buffer. */ + enet_ptp_time_data_ring_t txPtpTsDataRing; /*!< Transmit PTP 1588 time stamp data ring buffer. */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and De-initialization + * @{ + */ + +/*! + * @brief Gets the ENET default configuration structure. + * + * The purpose of this API is to get the default ENET MAC controller + * configure structure for ENET_Init(). User may use the initialized + * structure unchanged in ENET_Init(), or modify some fields of the + * structure before calling ENET_Init(). + * Example: + @code + enet_config_t config; + ENET_GetDefaultConfig(&config); + @endcode + * @param config The ENET mac controller configuration structure pointer. + */ +void ENET_GetDefaultConfig(enet_config_t *config); + +/*! + * @brief Initializes the ENET module. + * + * This function ungates the module clock and initializes it with the ENET configuration. + * + * @param base ENET peripheral base address. + * @param handle ENET handler pointer. + * @param config ENET mac configuration structure pointer. + * The "enet_config_t" type mac configuration return from ENET_GetDefaultConfig + * can be used directly. It is also possible to verify the Mac configuration using other methods. + * @param bufferConfig ENET buffer configuration structure pointer. + * The buffer configuration should be prepared for ENET Initialization. + * It is the start address of "ringNum" enet_buffer_config structures. + * To support added multi-ring features in some soc and compatible with the previous + * enet driver version. For single ring supported, this bufferConfig is a buffer + * configure structure pointer, for multi-ring supported and used case, this bufferConfig + * pointer should be a buffer configure structure array pointer. + * @param macAddr ENET mac address of Ethernet device. This MAC address should be + * provided. + * @param srcClock_Hz The internal module clock source for MII clock. + * + * @note ENET has two buffer descriptors legacy buffer descriptors and + * enhanced IEEE 1588 buffer descriptors. The legacy descriptor is used by default. To + * use the IEEE 1588 feature, use the enhanced IEEE 1588 buffer descriptor + * by defining "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" and calling ENET_Ptp1588Configure() + * to configure the 1588 feature and related buffers after calling ENET_Init(). + */ +void ENET_Init(ENET_Type *base, + enet_handle_t *handle, + const enet_config_t *config, + const enet_buffer_config_t *bufferConfig, + uint8_t *macAddr, + uint32_t srcClock_Hz); +/*! + * @brief Deinitializes the ENET module. + + * This function gates the module clock, clears ENET interrupts, and disables the ENET module. + * + * @param base ENET peripheral base address. + */ +void ENET_Deinit(ENET_Type *base); + +/*! + * @brief Resets the ENET module. + * + * This function restores the ENET module to reset state. + * Note that this function sets all registers to + * reset state. As a result, the ENET module can't work after calling this function. + * + * @param base ENET peripheral base address. + */ +static inline void ENET_Reset(ENET_Type *base) +{ + base->ECR |= ENET_ECR_RESET_MASK; +} + +/* @} */ + +/*! + * @name MII interface operation + * @{ + */ + +/*! + * @brief Sets the ENET MII speed and duplex. + * + * This API is provided to dynamically change the speed and dulpex for MAC. + * + * @param base ENET peripheral base address. + * @param speed The speed of the RMII mode. + * @param duplex The duplex of the RMII mode. + */ +void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex); + +/*! + * @brief Sets the ENET SMI(serial management interface)- MII management interface. + * + * @param base ENET peripheral base address. + * @param srcClock_Hz This is the ENET module clock frequency. Normally it's the system clock. See clock distribution. + * @param isPreambleDisabled The preamble disable flag. + * - true Enables the preamble. + * - false Disables the preamble. + */ +void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled); + +/*! + * @brief Gets the ENET SMI- MII management interface configuration. + * + * This API is used to get the SMI configuration to check whether the MII management + * interface has been set. + * + * @param base ENET peripheral base address. + * @return The SMI setup status true or false. + */ +static inline bool ENET_GetSMI(ENET_Type *base) +{ + return (0 != (base->MSCR & 0x7E)); +} + +/*! + * @brief Reads data from the PHY register through an SMI interface. + * + * @param base ENET peripheral base address. + * @return The data read from PHY + */ +static inline uint32_t ENET_ReadSMIData(ENET_Type *base) +{ + return (uint32_t)((base->MMFR & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT); +} + +/*! + * @brief Starts an SMI (Serial Management Interface) read command. + * + * Used for standard IEEE802.3 MDIO Clause 22 format. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. Range from 0 ~ 31. + * @param operation The read operation. + */ +void ENET_StartSMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation); + +/*! + * @brief Starts an SMI write command. + * + * Used for standard IEEE802.3 MDIO Clause 22 format. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. Range from 0 ~ 31. + * @param operation The write operation. + * @param data The data written to PHY. + */ +void ENET_StartSMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data); + +#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO +/*! + * @brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI read command. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, + * the phyReg is a 21-bits combination of the devaddr (5 bits device address) + * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. + */ +void ENET_StartExtC45SMIRead(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg); + +/*! + * @brief Starts the extended IEEE802.3 Clause 45 MDIO format SMI write command. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. For MDIO IEEE802.3 Clause 45, + * the phyReg is a 21-bits combination of the devaddr (5 bits device address) + * and the regAddr (16 bits phy register): phyReg = (devaddr << 16) | regAddr. + * @param data The data written to PHY. + */ +void ENET_StartExtC45SMIWrite(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); +#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */ + +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +/*! + * @brief Control the usage of the delayed tx/rx RGMII clock. + * + * @param base ENET peripheral base address. + * @param txEnabled Enable or disable to generate the delayed version of RGMII_TXC. + * @param rxEnabled Enable or disable to use the delayed version of RGMII_RXC. + */ + +static inline void ENET_SetRGMIIClockDelay(ENET_Type *base, bool txEnabled, bool rxEnabled) +{ + uint32_t ecrReg = base->ECR; + + /* Set for transmit clock delay. */ + if (txEnabled) + { + ecrReg |= ENET_ECR_TXC_DLY_MASK; + } + else + { + ecrReg &= ~ENET_ECR_TXC_DLY_MASK; + } + + /* Set for receive clock delay. */ + if (rxEnabled) + { + ecrReg |= ENET_ECR_RXC_DLY_MASK; + } + else + { + ecrReg &= ~ENET_ECR_RXC_DLY_MASK; + } +} +#endif /* FSL_FEATURE_ENET_HAS_AVB */ + /* @} */ + +/*! + * @name MAC Address Filter + * @{ + */ + +/*! + * @brief Sets the ENET module Mac address. + * + * @param base ENET peripheral base address. + * @param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ +void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr); + +/*! + * @brief Gets the ENET module Mac address. + * + * @param base ENET peripheral base address. + * @param macAddr The six-byte Mac address pointer. + * The pointer is allocated by application and input into the API. + */ +void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr); + +/*! + * @brief Adds the ENET device to a multicast group. + * + * @param base ENET peripheral base address. + * @param address The six-byte multicast group address which is provided by application. + */ +void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address); + +/*! + * @brief Moves the ENET device from a multicast group. + * + * @param base ENET peripheral base address. + * @param address The six-byte multicast group address which is provided by application. + */ +void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address); + +/* @} */ + +/*! + * @name Other basic operation + * @{ + */ + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB +/*! + * @brief Sets the ENET AVB feature. + * + * ENET AVB feature configuration, set the Receive classification match and transmit + * bandwidth. This API is called when the AVB feature is required. + * + * Note: The AVB frames transmission scheme is credit-based tx scheme and it's only supported + * with the Enhanced buffer descriptors. so the AVB configuration should only done with + * Enhanced buffer descriptor. so when the AVB feature is required, please make sure the + * the "ENET_ENHANCEDBUFFERDESCRIPTOR_MODE" is defined. + * + * @param base ENET peripheral base address. + * @param handle ENET handler pointer. + * @param config The ENET AVB feature configuration structure. + */ +void ENET_AVBConfigure(ENET_Type *base, enet_handle_t *handle, const enet_avb_config_t *config); +#endif /* FSL_FEATURE_ENET_HAS_AVB */ +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! + * @brief Activates ENET read or receive. + * + * This function is to active the enet read process. It is + * used for single descriptor ring/queue. + * + * @param base ENET peripheral base address. + * + * @note This must be called after the MAC configuration and + * state are ready. It must be called after the ENET_Init() and + * ENET_Ptp1588Configure(). This should be called when the ENET receive required. + */ +static inline void ENET_ActiveRead(ENET_Type *base) +{ + base->RDAR = ENET_RDAR_RDAR_MASK; +} + +#if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * @brief Activates ENET read or receive for multiple-queue/ring. + * + * This function is to active the enet read process. It is + * used for extended multiple descriptor rings/queues. + * + * @param base ENET peripheral base address. + * + * @note This must be called after the MAC configuration and + * state are ready. It must be called after the ENET_Init() and + * ENET_Ptp1588Configure(). This should be called when the ENET receive required. + */ +static inline void ENET_ActiveReadMultiRing(ENET_Type *base) +{ + base->RDAR = ENET_RDAR_RDAR_MASK; + base->RDAR1 = ENET_RDAR1_RDAR_MASK; + base->RDAR2 = ENET_RDAR2_RDAR_MASK; +} +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + +/*! + * @brief Enables/disables the MAC to enter sleep mode. + * This function is used to set the MAC enter sleep mode. + * When entering sleep mode, the magic frame wakeup interrupt should be enabled + * to wake up MAC from the sleep mode and reset it to normal mode. + * + * @param base ENET peripheral base address. + * @param enable True enable sleep mode, false disable sleep mode. + */ +static inline void ENET_EnableSleepMode(ENET_Type *base, bool enable) +{ + if (enable) + { + /* When this field is set, MAC enters sleep mode. */ + base->ECR |= ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK; + } + else + { /* MAC exits sleep mode. */ + base->ECR &= ~(ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK); + } +} + +/*! + * @brief Gets ENET transmit and receive accelerator functions from MAC controller. + * + * @param base ENET peripheral base address. + * @param txAccelOption The transmit accelerator option. The "enet_tx_accelerator_t" is + * recommended to be used to as the mask to get the exact the accelerator option. + * @param rxAccelOption The receive accelerator option. The "enet_rx_accelerator_t" is + * recommended to be used to as the mask to get the exact the accelerator option. + */ +static inline void ENET_GetAccelFunction(ENET_Type *base, uint32_t *txAccelOption, uint32_t *rxAccelOption) +{ + assert(txAccelOption); + assert(txAccelOption); + + *txAccelOption = base->TACC; + *rxAccelOption = base->RACC; +} + +/* @} */ + +/*! + * @name Interrupts. + * @{ + */ + +/*! + * @brief Enables the ENET interrupt. + * + * This function enables the ENET interrupt according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t. + * For example, to enable the TX frame interrupt and RX frame interrupt, do the following. + * @code + * ENET_EnableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupts to enable. This is a logical OR of the + * enumeration :: enet_interrupt_enable_t. + */ +static inline void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask) +{ + base->EIMR |= mask; +} + +/*! + * @brief Disables the ENET interrupt. + * + * This function disables the ENET interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref enet_interrupt_enable_t. + * For example, to disable the TX frame interrupt and RX frame interrupt, do the following. + * @code + * ENET_DisableInterrupts(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupts to disable. This is a logical OR of the + * enumeration :: enet_interrupt_enable_t. + */ +static inline void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask) +{ + base->EIMR &= ~mask; +} + +/*! + * @brief Gets the ENET interrupt status flag. + * + * @param base ENET peripheral base address. + * @return The event status of the interrupt source. This is the logical OR of members + * of the enumeration :: enet_interrupt_enable_t. + */ +static inline uint32_t ENET_GetInterruptStatus(ENET_Type *base) +{ + return base->EIR; +} + +/*! + * @brief Clears the ENET interrupt events status flag. + * + * This function clears enabled ENET interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See the @ref enet_interrupt_enable_t. + * For example, to clear the TX frame interrupt and RX frame interrupt, do the following. + * @code + * ENET_ClearInterruptStatus(ENET, kENET_TxFrameInterrupt | kENET_RxFrameInterrupt); + * @endcode + * + * @param base ENET peripheral base address. + * @param mask ENET interrupt source to be cleared. + * This is the logical OR of members of the enumeration :: enet_interrupt_enable_t. + */ +static inline void ENET_ClearInterruptStatus(ENET_Type *base, uint32_t mask) +{ + base->EIR = mask; +} +/* @} */ + +/*! + * @name Transactional operation + * @{ + */ + +/*! + * @brief Sets the callback function. + * This API is provided for the application callback required case when ENET + * interrupt is enabled. This API should be called after calling ENET_Init. + * + * @param handle ENET handler pointer. Should be provided by application. + * @param callback The ENET callback function. + * @param userData The callback function parameter. + */ +void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData); + +/*! + * @brief Gets the error statistics of a received frame for ENET single ring. + * + * This API must be called after the ENET_GetRxFrameSize and before the ENET_ReadFrame(). + * If the ENET_GetRxFrameSize returns kStatus_ENET_RxFrameError, + * the ENET_GetRxErrBeforeReadFrame can be used to get the exact error statistics. + * This is an example. + * @code + * status = ENET_GetRxFrameSize(&g_handle, &length); + * if (status == kStatus_ENET_RxFrameError) + * { + * // Get the error information of the received frame. + * ENET_GetRxErrBeforeReadFrame(&g_handle, &eErrStatic); + * // update the receive buffer. + * ENET_ReadFrame(EXAMPLE_ENET, &g_handle, NULL, 0); + * } + * @endcode + * @param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. + * @param eErrorStatic The error statistics structure pointer. + */ +void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic); + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * @brief Gets the ENET transmit frame statistics after the data send for single ring. + * + * This interface gets the error statistics of the transmit frame. + * Because the error information is reported by the uDMA after the data delivery, this interface + * should be called after the data transmit API. It is recommended to call this function on + * transmit interrupt handler. After calling the ENET_SendFrame, the + * transmit interrupt notifies the transmit completion. + * + * @param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. + * @param eErrorStatic The error statistics structure pointer. + * @return The execute status. + */ +status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! + * @brief Gets the size of the read frame for single ring. + * + * This function gets a received frame size from the ENET buffer descriptors. + * @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. + * After calling ENET_GetRxFrameSize, ENET_ReadFrame() should be called to update the + * receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". + * + * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * @param length The length of the valid frame received. + * @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrame to read frame. + * @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrame should be called with NULL data + * and NULL length to update the receive buffers. + * @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame + * should be called with the right data buffer and the captured data length input. + */ +status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length); + +/*! + * @brief Reads a frame from the ENET device for single ring. + * This function reads a frame (both the data and the length) from the ENET buffer descriptors. + * The ENET_GetRxFrameSize should be used to get the size of the prepared data buffer. + * This is an example: + * @code + * uint32_t length; + * enet_handle_t g_handle; + * //Get the received frame size firstly. + * status = ENET_GetRxFrameSize(&g_handle, &length); + * if (length != 0) + * { + * //Allocate memory here with the size of "length" + * uint8_t *data = memory allocate interface; + * if (!data) + * { + * ENET_ReadFrame(ENET, &g_handle, NULL, 0); + * //Add the console warning log. + * } + * else + * { + * status = ENET_ReadFrame(ENET, &g_handle, data, length); + * //Call stack input API to deliver the data to stack + * } + * } + * else if (status == kStatus_ENET_RxFrameError) + * { + * //Update the received buffer when a error frame is received. + * ENET_ReadFrame(ENET, &g_handle, NULL, 0); + * } + * @endcode + * @param base ENET peripheral base address. + * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to store the frame which memory size should be at least "length". + * @param length The size of the data buffer which is still the length of the received frame. + * @return The execute status, successful or failure. + */ +status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length); + +/*! + * @brief Transmits an ENET frame for single ring. + * @note The CRC is automatically appended to the data. Input the data + * to send without the CRC. + * + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to be send. + * @param length The length of the data to be send. + * @retval kStatus_Success Send frame succeed. + * @retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. + * The transmit busy happens when the data send rate is over the MAC capacity. + * The waiting mechanism is recommended to be added after each call return with + * kStatus_ENET_TxFrameBusy. + */ +status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *data, uint32_t length); + +#if FSL_FEATURE_ENET_QUEUE > 1 +/*! + * @brief Gets the error statistics of received frame for extended multi-ring. + * + * This API must be called after the ENET_GetRxFrameSizeMultiRing and before the ENET_ReadFrameMultiRing(). + * If the ENET_GetRxFrameSizeMultiRing returns kStatus_ENET_RxFrameError, + * the ENET_GetRxErrBeforeReadFrameMultiRing can be used to get the exact error statistics. + * + * @param handle The ENET handler structure pointer. This is the same handler pointer used in the ENET_Init. + * @param eErrorStatic The error statistics structure pointer. + * @param ringId The ring index, range from 0 ~ FSL_FEATURE_ENET_QUEUE - 1. + */ +void ENET_GetRxErrBeforeReadFrameMultiRing(enet_handle_t *handle, + enet_data_error_stats_t *eErrorStatic, + uint32_t ringId); + +/*! + * @brief Transmits an ENET frame for extended multi-ring. + * @note The CRC is automatically appended to the data. Input the data + * to send without the CRC. + * + * In this API, multiple-ring are mainly used for extended avb frames are supported. + * The transmit scheme for avb frames is the credit-based scheme, the AVB class A, AVB class B + * and the non-AVB frame are transmitted in ring 1, ring 2 and ring 0 independently. + * So application should care about the transmit ring index when use multiple-ring transmission. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to be send. + * @param length The length of the data to be send. + * @param ringId The ring index for transmission. + * @retval kStatus_Success Send frame succeed. + * @retval kStatus_ENET_TxFrameBusy Transmit buffer descriptor is busy under transmission. + * The transmit busy happens when the data send rate is over the MAC capacity. + * The waiting mechanism is recommended to be added after each call return with + * kStatus_ENET_TxFrameBusy. + */ +status_t ENET_SendFrameMultiRing( + ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId); + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * @brief Gets the ENET transmit frame statistics after the data send for extended multi-ring. + * + * This interface gets the error statistics of the transmit frame. + * Because the error information is reported by the uDMA after the data delivery, this interface + * should be called after the data transmit API and shall be called by transmit interrupt handler. + * After calling the ENET_SendFrame, the transmit interrupt notifies the transmit completion. + * + * @param handle The PTP handler pointer. This is the same handler pointer used in the ENET_Init. + * @param eErrorStatic The error statistics structure pointer. + * @param ringId The ring index. + * @return The execute status. + */ +status_t ENET_GetTxErrAfterSendFrameMultiRing(enet_handle_t *handle, + enet_data_error_stats_t *eErrorStatic, + uint32_t ringId); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ + +/*! + * @brief Gets the size of the read frame for extended mutli-ring. + * + * This function gets a received frame size from the ENET buffer descriptors. + * @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS. + * After calling ENET_GetRxFrameSizeMultiRing, ENET_ReadFrameMultiRing() should be called to update the + * receive buffers If the result is not "kStatus_ENET_RxFrameEmpty". The usage is + * the same to the single ring, refer to ENET_GetRxFrameSize. + * + * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * @param length The length of the valid frame received. + * @param ringId The ring index or ring number; + * @retval kStatus_ENET_RxFrameEmpty No frame received. Should not call ENET_ReadFrameMultiRing to read frame. + * @retval kStatus_ENET_RxFrameError Data error happens. ENET_ReadFrameMultiRing should be called with NULL data + * and NULL length to update the receive buffers. + * @retval kStatus_Success Receive a frame Successfully then the ENET_ReadFrame + * should be called with the right data buffer and the captured data length input. + */ +status_t ENET_GetRxFrameSizeMultiRing(enet_handle_t *handle, uint32_t *length, uint32_t ringId); + +/*! + * @brief Reads a frame from the ENET device for multi-ring. + * + * This function reads a frame (both the data and the length) from the ENET buffer descriptors. + * The ENET_GetRxFrameSizeMultiRing should be used to get the size of the prepared data buffer. + * This usage is the same as the single ring, refer to ENET_ReadFrame. + + * @param base ENET peripheral base address. + * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_Init. + * @param data The data buffer provided by user to store the frame which memory size should be at least "length". + * @param length The size of the data buffer which is still the length of the received frame. + * @param ringId The ring index or ring number; + * @return The execute status, successful or failure. + */ +status_t ENET_ReadFrameMultiRing( + ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint32_t ringId); + +/*! + * @brief The transmit IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + * @param ringId The ring id or ring number. + */ +void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); + +/*! + * @brief The receive IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + * @param ringId The ring id or ring number. + */ +void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId); + +/*! + * @brief the common IRQ handler for the tx/rx irq handler. + * + * This is used for the combined tx/rx interrupt for multi-ring (frame 1). + * + * @param base ENET peripheral base address. + */ +void ENET_CommonFrame1IRQHandler(ENET_Type *base); + +/*! + * @brief the common IRQ handler for the tx/rx irq handler. + * + * This is used for the combined tx/rx interrupt for multi-ring (frame 2). + * + * @param base ENET peripheral base address. + */ +void ENET_CommonFrame2IRQHandler(ENET_Type *base); +#else +/*! + * @brief The transmit IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief The receive IRQ handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle); +#endif /* FSL_FEATURE_ENET_QUEUE > 1 */ + +/*! + * @brief Some special IRQ handler including the error, mii, wakeup irq handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET handler pointer. + */ +void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief the common IRQ handler for the tx/rx/error etc irq handler. + * + * This is used for the combined tx/rx/error interrupt for single/mutli-ring (frame 0). + * + * @param base ENET peripheral base address. + */ +void ENET_CommonFrame0IRQHandler(ENET_Type *base); +/* @} */ + +#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE +/*! + * @name ENET PTP 1588 function operation + * @{ + */ + +/*! + * @brief Configures the ENET PTP IEEE 1588 feature with the basic configuration. + * The function sets the clock for PTP 1588 timer and enables + * time stamp interrupts and transmit interrupts for PTP 1588 features. + * This API should be called when the 1588 feature is enabled + * or the ENET_ENHANCEDBUFFERDESCRIPTOR_MODE is defined. + * ENET_Init should be called before calling this API. + * + * @note The PTP 1588 time-stamp second increase though time-stamp interrupt handler + * and the transmit time-stamp store is done through transmit interrupt handler. + * As a result, the TS interrupt and TX interrupt are enabled when you call this API. + * + * @param base ENET peripheral base address. + * @param handle ENET handler pointer. + * @param ptpConfig The ENET PTP1588 configuration. + */ +void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig); + +/*! + * @brief Starts the ENET PTP 1588 Timer. + * This function is used to initialize the PTP timer. After the PTP starts, + * the PTP timer starts running. + * + * @param base ENET peripheral base address. + * @param ptpClkSrc The clock source of the PTP timer. + */ +void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc); + +/*! + * @brief Stops the ENET PTP 1588 Timer. + * This function is used to stops the ENET PTP timer. + * + * @param base ENET peripheral base address. + */ +static inline void ENET_Ptp1588StopTimer(ENET_Type *base) +{ + /* Disable PTP timer and reset the timer. */ + base->ATCR &= ~ENET_ATCR_EN_MASK; + base->ATCR |= ENET_ATCR_RESTART_MASK; +} + +/*! + * @brief Adjusts the ENET PTP 1588 timer. + * + * @param base ENET peripheral base address. + * @param corrIncrease The correction increment value. This value is added every time the correction + * timer expires. A value less than the PTP timer frequency(1/ptpClkSrc) slows down the timer, + * a value greater than the 1/ptpClkSrc speeds up the timer. + * @param corrPeriod The PTP timer correction counter wrap-around value. This defines after how + * many timer clock the correction counter should be reset and trigger a correction + * increment on the timer. A value of 0 disables the correction counter and no correction occurs. + */ +void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod); + +/*! + * @brief Sets the ENET PTP 1588 timer channel mode. + * + * @param base ENET peripheral base address. + * @param channel The ENET PTP timer channel number. + * @param mode The PTP timer channel mode, see "enet_ptp_timer_channel_mode_t". + * @param intEnable Enables or disables the interrupt. + */ +static inline void ENET_Ptp1588SetChannelMode(ENET_Type *base, + enet_ptp_timer_channel_t channel, + enet_ptp_timer_channel_mode_t mode, + bool intEnable) +{ + uint32_t tcrReg = 0; + + tcrReg = ENET_TCSR_TMODE(mode) | (intEnable ? ENET_TCSR_TIE_MASK : 0); + + /* Disable channel mode first. */ + base->CHANNEL[channel].TCSR = 0; + base->CHANNEL[channel].TCSR = tcrReg; +} + +#if defined(FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL) && FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL +/*! + * @brief Sets ENET PTP 1588 timer channel mode pulse width. + * + * For the input "mode" in ENET_Ptp1588SetChannelMode, the kENET_PtpChannelPulseLowonCompare + * kENET_PtpChannelPulseHighonCompare only support the pulse width for one 1588 clock. + * this function is extended for control the pulse width from 1 to 32 1588 clock cycles. + * so call this function if you need to set the timer channel mode for + * kENET_PtpChannelPulseLowonCompare or kENET_PtpChannelPulseHighonCompare + * with pulse width more than one 1588 clock, + * + * @param base ENET peripheral base address. + * @param channel The ENET PTP timer channel number. + * @param isOutputLow True --- timer channel is configured for output compare + * pulse output low. + * false --- timer channel is configured for output compare + * pulse output high. + * @param pulseWidth The pulse width control value, range from 0 ~ 31. + * 0 --- pulse width is one 1588 clock cycle. + * 31 --- pulse width is thirty two 1588 clock cycles. + * @param intEnable Enables or disables the interrupt. + */ +static inline void ENET_Ptp1588SetChannelOutputPulseWidth( + ENET_Type *base, enet_ptp_timer_channel_t channel, bool isOutputLow, uint8_t pulseWidth, bool intEnable) +{ + uint32_t tcrReg; + + tcrReg = ENET_TCSR_TIE(intEnable) | ENET_TCSR_TPWC(pulseWidth); + + if (isOutputLow) + { + tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseLowonCompare); + } + else + { + tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseHighonCompare); + } + + /* Disable channel mode first. */ + base->CHANNEL[channel].TCSR = 0; + base->CHANNEL[channel].TCSR = tcrReg; +} +#endif /* FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL */ + +/*! + * @brief Sets the ENET PTP 1588 timer channel comparison value. + * + * @param base ENET peripheral base address. + * @param channel The PTP timer channel, see "enet_ptp_timer_channel_t". + * @param cmpValue The compare value for the compare setting. + */ +static inline void ENET_Ptp1588SetChannelCmpValue(ENET_Type *base, enet_ptp_timer_channel_t channel, uint32_t cmpValue) +{ + base->CHANNEL[channel].TCCR = cmpValue; +} + +/*! + * @brief Gets the ENET PTP 1588 timer channel status. + * + * @param base ENET peripheral base address. + * @param channel The IEEE 1588 timer channel number. + * @return True or false, Compare or capture operation status + */ +static inline bool ENET_Ptp1588GetChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) +{ + return (0 != (base->CHANNEL[channel].TCSR & ENET_TCSR_TF_MASK)); +} + +/*! + * @brief Clears the ENET PTP 1588 timer channel status. + * + * @param base ENET peripheral base address. + * @param channel The IEEE 1588 timer channel number. + */ +static inline void ENET_Ptp1588ClearChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel) +{ + base->CHANNEL[channel].TCSR |= ENET_TCSR_TF_MASK; + base->TGSR = (1U << channel); +} + +/*! + * @brief Gets the current ENET time from the PTP 1588 timer. + * + * @param base ENET peripheral base address. + * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * @param ptpTime The PTP timer structure. + */ +void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); + +/*! + * @brief Sets the ENET PTP 1588 timer to the assigned time. + * + * @param base ENET peripheral base address. + * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + * @param ptpTime The timer to be set to the PTP timer. + */ +void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime); + +/*! + * @brief The IEEE 1588 PTP time stamp interrupt handler. + * + * @param base ENET peripheral base address. + * @param handle The ENET state pointer. This is the same state pointer used in the ENET_Init. + */ +void ENET_Ptp1588TimerIRQHandler(ENET_Type *base, enet_handle_t *handle); + +/*! + * @brief Gets the time stamp of the received frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * @param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * @retval kStatus_Success Get 1588 timestamp success. + * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ +status_t ENET_GetRxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); + +/*! + * @brief Gets the time stamp of the transmit frame. + * + * This function is used for PTP stack to get the timestamp captured by the ENET driver. + * + * @param handle The ENET handler pointer.This is the same state pointer used in + * ENET_Init. + * @param ptpTimeData The special PTP timestamp data for search the receive timestamp. + * @retval kStatus_Success Get 1588 timestamp success. + * @retval kStatus_ENET_PtpTsRingEmpty 1588 timestamp ring empty. + * @retval kStatus_ENET_PtpTsRingFull 1588 timestamp ring full. + */ +status_t ENET_GetTxFrameTime(enet_handle_t *handle, enet_ptp_time_data_t *ptpTimeData); +#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */ +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_ENET_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_ewm.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_ewm.c new file mode 100644 index 0000000000..15182e15fa --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_ewm.c @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_ewm.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ewm" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Initializes the EWM peripheral. + * + * This function is used to initialize the EWM. After calling, the EWM + * runs immediately according to the configuration. + * Note that, except for the interrupt enable control bit, other control bits and registers are write once after a + * CPU reset. Modifying them more than once generates a bus transfer error. + * + * This is an example. + * code + * ewm_config_t config; + * EWM_GetDefaultConfig(&config); + * config.compareHighValue = 0xAAU; + * EWM_Init(ewm_base,&config); + * endcode + * + * param base EWM peripheral base address + * param config The configuration of the EWM + */ +void EWM_Init(EWM_Type *base, const ewm_config_t *config) +{ + assert(config); + + uint32_t value = 0U; + +#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \ + (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(kCLOCK_Ewm0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif + value = EWM_CTRL_EWMEN(config->enableEwm) | EWM_CTRL_ASSIN(config->setInputAssertLogic) | + EWM_CTRL_INEN(config->enableEwmInput) | EWM_CTRL_INTEN(config->enableInterrupt); +#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER + base->CLKPRESCALER = config->prescaler; +#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ + +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT + base->CLKCTRL = config->clockSource; +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/ + + base->CMPL = config->compareLowValue; + base->CMPH = config->compareHighValue; + base->CTRL = value; +} + +/*! + * brief Deinitializes the EWM peripheral. + * + * This function is used to shut down the EWM. + * + * param base EWM peripheral base address + */ +void EWM_Deinit(EWM_Type *base) +{ + EWM_DisableInterrupts(base, kEWM_InterruptEnable); +#if !((defined(FSL_FEATURE_SOC_PCC_COUNT) && FSL_FEATURE_SOC_PCC_COUNT) && \ + (defined(FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE) && FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(kCLOCK_Ewm0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* FSL_FEATURE_PCC_SUPPORT_EWM_CLOCK_REMOVE */ +} + +/*! + * brief Initializes the EWM configuration structure. + * + * This function initializes the EWM configuration structure to default values. The default + * values are as follows. + * code + * ewmConfig->enableEwm = true; + * ewmConfig->enableEwmInput = false; + * ewmConfig->setInputAssertLogic = false; + * ewmConfig->enableInterrupt = false; + * ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0; + * ewmConfig->prescaler = 0; + * ewmConfig->compareLowValue = 0; + * ewmConfig->compareHighValue = 0xFEU; + * endcode + * + * param config Pointer to the EWM configuration structure. + * see ewm_config_t + */ +void EWM_GetDefaultConfig(ewm_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->enableEwm = true; + config->enableEwmInput = false; + config->setInputAssertLogic = false; + config->enableInterrupt = false; +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT + config->clockSource = kEWM_LpoClockSource0; +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT*/ +#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER + config->prescaler = 0U; +#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ + config->compareLowValue = 0U; + config->compareHighValue = 0xFEU; +} + +/*! + * brief Services the EWM. + * + * This function resets the EWM counter to zero. + * + * param base EWM peripheral base address + */ +void EWM_Refresh(EWM_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupt to protect refresh sequence */ + primaskValue = DisableGlobalIRQ(); + base->SERV = (uint8_t)0xB4U; + base->SERV = (uint8_t)0x2CU; + EnableGlobalIRQ(primaskValue); +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_ewm.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_ewm.h new file mode 100644 index 0000000000..3b5fd3a7de --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_ewm.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_EWM_H_ +#define _FSL_EWM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ewm + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief EWM driver version 2.0.1. */ +#define FSL_EWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @brief Describes EWM clock source. */ +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT +typedef enum _ewm_lpo_clock_source +{ + kEWM_LpoClockSource0 = 0U, /*!< EWM clock sourced from lpo_clk[0]*/ + kEWM_LpoClockSource1 = 1U, /*!< EWM clock sourced from lpo_clk[1]*/ + kEWM_LpoClockSource2 = 2U, /*!< EWM clock sourced from lpo_clk[2]*/ + kEWM_LpoClockSource3 = 3U, /*!< EWM clock sourced from lpo_clk[3]*/ +} ewm_lpo_clock_source_t; +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */ + +/*! + * @brief Data structure for EWM configuration. + * + * This structure is used to configure the EWM. + */ +typedef struct _ewm_config +{ + bool enableEwm; /*!< Enable EWM module */ + bool enableEwmInput; /*!< Enable EWM_in input */ + bool setInputAssertLogic; /*!< EWM_in signal assertion state */ + bool enableInterrupt; /*!< Enable EWM interrupt */ +#if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT + ewm_lpo_clock_source_t clockSource; /*!< Clock source select */ +#endif /* FSL_FEATURE_EWM_HAS_CLOCK_SELECT */ +#if defined(FSL_FEATURE_EWM_HAS_PRESCALER) && FSL_FEATURE_EWM_HAS_PRESCALER + uint8_t prescaler; /*!< Clock prescaler value */ +#endif /* FSL_FEATURE_EWM_HAS_PRESCALER */ + uint8_t compareLowValue; /*!< Compare low-register value */ + uint8_t compareHighValue; /*!< Compare high-register value */ +} ewm_config_t; + +/*! + * @brief EWM interrupt configuration structure with default settings all disabled. + * + * This structure contains the settings for all of EWM interrupt configurations. + */ +enum _ewm_interrupt_enable_t +{ + kEWM_InterruptEnable = EWM_CTRL_INTEN_MASK, /*!< Enable the EWM to generate an interrupt*/ +}; + +/*! + * @brief EWM status flags. + * + * This structure contains the constants for the EWM status flags for use in the EWM functions. + */ +enum _ewm_status_flags_t +{ + kEWM_RunningFlag = EWM_CTRL_EWMEN_MASK, /*!< Running flag, set when EWM is enabled*/ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name EWM initialization and de-initialization + * @{ + */ + +/*! + * @brief Initializes the EWM peripheral. + * + * This function is used to initialize the EWM. After calling, the EWM + * runs immediately according to the configuration. + * Note that, except for the interrupt enable control bit, other control bits and registers are write once after a + * CPU reset. Modifying them more than once generates a bus transfer error. + * + * This is an example. + * @code + * ewm_config_t config; + * EWM_GetDefaultConfig(&config); + * config.compareHighValue = 0xAAU; + * EWM_Init(ewm_base,&config); + * @endcode + * + * @param base EWM peripheral base address + * @param config The configuration of the EWM + */ +void EWM_Init(EWM_Type *base, const ewm_config_t *config); + +/*! + * @brief Deinitializes the EWM peripheral. + * + * This function is used to shut down the EWM. + * + * @param base EWM peripheral base address + */ +void EWM_Deinit(EWM_Type *base); + +/*! + * @brief Initializes the EWM configuration structure. + * + * This function initializes the EWM configuration structure to default values. The default + * values are as follows. + * @code + * ewmConfig->enableEwm = true; + * ewmConfig->enableEwmInput = false; + * ewmConfig->setInputAssertLogic = false; + * ewmConfig->enableInterrupt = false; + * ewmConfig->ewm_lpo_clock_source_t = kEWM_LpoClockSource0; + * ewmConfig->prescaler = 0; + * ewmConfig->compareLowValue = 0; + * ewmConfig->compareHighValue = 0xFEU; + * @endcode + * + * @param config Pointer to the EWM configuration structure. + * @see ewm_config_t + */ +void EWM_GetDefaultConfig(ewm_config_t *config); + +/* @} */ + +/*! + * @name EWM functional Operation + * @{ + */ + +/*! + * @brief Enables the EWM interrupt. + * + * This function enables the EWM interrupt. + * + * @param base EWM peripheral base address + * @param mask The interrupts to enable + * The parameter can be combination of the following source if defined + * @arg kEWM_InterruptEnable + */ +static inline void EWM_EnableInterrupts(EWM_Type *base, uint32_t mask) +{ + base->CTRL |= mask; +} + +/*! + * @brief Disables the EWM interrupt. + * + * This function enables the EWM interrupt. + * + * @param base EWM peripheral base address + * @param mask The interrupts to disable + * The parameter can be combination of the following source if defined + * @arg kEWM_InterruptEnable + */ +static inline void EWM_DisableInterrupts(EWM_Type *base, uint32_t mask) +{ + base->CTRL &= ~mask; +} + +/*! + * @brief Gets all status flags. + * + * This function gets all status flags. + * + * This is an example for getting the running flag. + * @code + * uint32_t status; + * status = EWM_GetStatusFlags(ewm_base) & kEWM_RunningFlag; + * @endcode + * @param base EWM peripheral base address + * @return State of the status flag: asserted (true) or not-asserted (false).@see _ewm_status_flags_t + * - True: a related status flag has been set. + * - False: a related status flag is not set. + */ +static inline uint32_t EWM_GetStatusFlags(EWM_Type *base) +{ + return (base->CTRL & EWM_CTRL_EWMEN_MASK); +} + +/*! + * @brief Services the EWM. + * + * This function resets the EWM counter to zero. + * + * @param base EWM peripheral base address + */ +void EWM_Refresh(EWM_Type *base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_EWM_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexcan.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexcan.c new file mode 100644 index 0000000000..47cea9785d --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexcan.c @@ -0,0 +1,3251 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexcan.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcan" +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) +#define RXINTERMISSION (CAN_DBG1_CFSM(0x2f)) +#define TXINTERMISSION (CAN_DBG1_CFSM(0x14)) +#define BUSIDLE (CAN_DBG1_CFSM(0x02)) +#define CBN_VALUE3 (CAN_DBG1_CBN(0x03)) +#define DELAY_BUSIDLE (200) +#endif + +#define IDEAL_SP_LOW (750U) +#define IDEAL_SP_MID (800U) +#define IDEAL_SP_HIGH (875U) +#define IDEAL_SP_FACTOR (1000U) + +#define MAX_PROPSEG (CAN_CTRL1_PROPSEG_MASK >> CAN_CTRL1_PROPSEG_SHIFT) +#define MAX_PSEG1 (CAN_CTRL1_PSEG1_MASK >> CAN_CTRL1_PSEG1_SHIFT) +#define MAX_PSEG2 (CAN_CTRL1_PSEG2_MASK >> CAN_CTRL1_PSEG2_SHIFT) +#define MAX_RJW (CAN_CTRL1_RJW_MASK >> CAN_CTRL1_RJW_SHIFT) +#define MAX_PRESDIV (CAN_CTRL1_PRESDIV_MASK >> CAN_CTRL1_PRESDIV_SHIFT) +#define CTRL1_MAX_TIME_QUANTA (1U + MAX_PROPSEG + 1U + MAX_PSEG1 + 1U + MAX_PSEG2 + 1U) +#define CTRL1_MIN_TIME_QUANTA (8U) + +#define MAX_EPROPSEG (CAN_CBT_EPROPSEG_MASK >> CAN_CBT_EPROPSEG_SHIFT) +#define MAX_EPSEG1 (CAN_CBT_EPSEG1_MASK >> CAN_CBT_EPSEG1_SHIFT) +#define MAX_EPSEG2 (CAN_CBT_EPSEG2_MASK >> CAN_CBT_EPSEG2_SHIFT) +#define MAX_ERJW (CAN_CBT_ERJW_MASK >> CAN_CBT_ERJW_SHIFT) +#define MAX_EPRESDIV (CAN_CBT_EPRESDIV_MASK >> CAN_CBT_EPRESDIV_SHIFT) +#define CBT_MAX_TIME_QUANTA (1U + MAX_EPROPSEG + 1U + MAX_EPSEG1 + 1U + MAX_EPSEG2 + 1U) +#define CBT_MIN_TIME_QUANTA (8U) + +#define FDCBT_MAX_TIME_QUANTA (1U + MAX_FPROPSEG + 0U + MAX_FPSEG1 + 1U + MAX_FPSEG2 + 1U) +#define FDCBT_MIN_TIME_QUANTA (5U) +#define MAX_FPROPSEG (CAN_FDCBT_FPROPSEG_MASK >> CAN_FDCBT_FPROPSEG_SHIFT) +#define MAX_FPSEG1 (CAN_FDCBT_FPSEG1_MASK >> CAN_FDCBT_FPSEG1_SHIFT) +#define MAX_FPSEG2 (CAN_FDCBT_FPSEG2_MASK >> CAN_FDCBT_FPSEG2_SHIFT) +#define MAX_FRJW (CAN_FDCBT_FRJW_MASK >> CAN_FDCBT_FRJW_SHIFT) +#define MAX_FPRESDIV (CAN_FDCBT_FPRESDIV_MASK >> CAN_FDCBT_FPRESDIV_SHIFT) + +#define MAX_CANFD_BAUDRATE (8000000U) +#define MAX_CAN_BAUDRATE (1000000U) + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) +#define CAN_ESR1_FLTCONF_BUSOFF CAN_ESR1_FLTCONF(2U) +#endif + +/*! @brief FlexCAN Internal State. */ +enum _flexcan_state +{ + kFLEXCAN_StateIdle = 0x0, /*!< MB/RxFIFO idle.*/ + kFLEXCAN_StateRxData = 0x1, /*!< MB receiving.*/ + kFLEXCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/ + kFLEXCAN_StateTxData = 0x3, /*!< MB transmitting.*/ + kFLEXCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/ + kFLEXCAN_StateRxFifo = 0x5, /*!< RxFIFO receiving.*/ +}; + +/*! @brief FlexCAN message buffer CODE for Rx buffers. */ +enum _flexcan_mb_code_rx +{ + kFLEXCAN_RxMbInactive = 0x0, /*!< MB is not active.*/ + kFLEXCAN_RxMbFull = 0x2, /*!< MB is full.*/ + kFLEXCAN_RxMbEmpty = 0x4, /*!< MB is active and empty.*/ + kFLEXCAN_RxMbOverrun = 0x6, /*!< MB is overwritten into a full buffer.*/ + kFLEXCAN_RxMbBusy = 0x8, /*!< FlexCAN is updating the contents of the MB.*/ + /*! The CPU must not access the MB.*/ + kFLEXCAN_RxMbRanswer = 0xA, /*!< A frame was configured to recognize a Remote Request Frame */ + /*! and transmit a Response Frame in return.*/ + kFLEXCAN_RxMbNotUsed = 0xF, /*!< Not used.*/ +}; + +/*! @brief FlexCAN message buffer CODE FOR Tx buffers. */ +enum _flexcan_mb_code_tx +{ + kFLEXCAN_TxMbInactive = 0x8, /*!< MB is not active.*/ + kFLEXCAN_TxMbAbort = 0x9, /*!< MB is aborted.*/ + kFLEXCAN_TxMbDataOrRemote = 0xC, /*!< MB is a TX Data Frame(when MB RTR = 0) or */ + /*!< MB is a TX Remote Request Frame (when MB RTR = 1).*/ + kFLEXCAN_TxMbTanswer = 0xE, /*!< MB is a TX Response Request Frame from */ + /*! an incoming Remote Request Frame.*/ + kFLEXCAN_TxMbNotUsed = 0xF, /*!< Not used.*/ +}; + +/* Typedef for interrupt handler. */ +typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Enter FlexCAN Freeze Mode. + * + * This function makes the FlexCAN work under Freeze Mode. + * + * @param base FlexCAN peripheral base address. + */ +static void FLEXCAN_EnterFreezeMode(CAN_Type *base); + +/*! + * @brief Exit FlexCAN Freeze Mode. + * + * This function makes the FlexCAN leave Freeze Mode. + * + * @param base FlexCAN peripheral base address. + */ +static void FLEXCAN_ExitFreezeMode(CAN_Type *base); + +#if !defined(NDEBUG) +/*! + * @brief Check if Message Buffer is occupied by Rx FIFO. + * + * This function check if Message Buffer is occupied by Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + */ +static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx); +#endif + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) +/*! + * @brief Get the first valid Message buffer ID of give FlexCAN instance. + * + * This function is a helper function for Errata 5641 workaround. + * + * @param base FlexCAN peripheral base address. + * @return The first valid Message Buffer Number. + */ +static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base); +#endif + +/*! + * @brief Check if Message Buffer interrupt is enabled. + * + * This function check if Message Buffer interrupt is enabled. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + */ +static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx); + +/*! + * @brief Reset the FlexCAN Instance. + * + * Restores the FlexCAN module to reset state, notice that this function + * will set all the registers to reset state so the FlexCAN module can not work + * after calling this API. + * + * @param base FlexCAN peripheral base address. + */ +static void FLEXCAN_Reset(CAN_Type *base); + +/*! + * @brief Set Baud Rate of FlexCAN. + * + * This function set the baud rate of FlexCAN. + * + * @param base FlexCAN peripheral base address. + * @param sourceClock_Hz Source Clock in Hz. + * @param baudRate_Bps Baud Rate in Bps. + * @param timingConfig FlexCAN timingConfig. + */ +static void FLEXCAN_SetBaudRate(CAN_Type *base, + uint32_t sourceClock_Hz, + uint32_t baudRate_Bps, + flexcan_timing_config_t timingConfig); +/*! + * @brief Calculates the segment values for a single bit time for classical CAN + * + * @param baudRate The data speed in bps + * @param tqNum Number of time quantas per bit + * @param pconfig Pointer to the FlexCAN timing configuration structure. + * + */ +static void FLEXCAN_GetSegments(uint32_t baudRate, uint32_t tqNum, flexcan_timing_config_t *pconfig); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Set Baud Rate of FlexCAN FD frame. + * + * This function set the baud rate of FlexCAN FD frame. + * + * @param base FlexCAN peripheral base address. + * @param sourceClock_Hz Source Clock in Hz. + * @param baudRateFD_Bps FD frame Baud Rate in Bps. + * @param timingConfig FlexCAN timingConfig. + */ +static void FLEXCAN_SetFDBaudRate(CAN_Type *base, + uint32_t sourceClock_Hz, + uint32_t baudRateFD_Bps, + flexcan_timing_config_t timingConfig); + +/*! + * @brief Get Mailbox offset number by dword. + * + * This function gets the offset number of the specified mailbox. + * Mailbox is not consecutive between memory regions when payload is not 8 bytes + * so need to calculate the specified mailbox address. + * For example, in the first memory region, MB[0].CS address is 0x4002_4080. For 32 bytes + * payload frame, the second mailbox is ((1/12)*512 + 1%12*40)/4 = 10, meaning 10 dword + * after the 0x4002_4080, which is actually the address of mailbox MB[1].CS. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx Mailbox index. + */ +static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx); + +/*! + * @brief Calculates the segment values for a single bit time for CANFD bus control baud Rate + * + * @param baudRate The canfd bus control speed in bps + * @param tqNum Number of time quanta per bit + * @param pconfig Pointer to the FlexCAN timing configuration structure. + * + */ +static void FLEXCAN_FDGetSegments(uint32_t baudRateFD, uint32_t tqNum, flexcan_timing_config_t *pconfig); +/*! + * @brief Calculates the segment values for a single bit time for CANFD bus data baud Rate + * + * @param baudRate The canfd bus data speed in bps + * @param tqNum Number of time quanta per bit + * @param pconfig Pointer to the FlexCAN timing configuration structure. + * + */ +static void FLEXCAN_FDGetSegmentswithBRS(uint32_t baudRateFDbrs, uint32_t tqNum, flexcan_timing_config_t *pconfig); + +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Array of FlexCAN peripheral base address. */ +static CAN_Type *const s_flexcanBases[] = CAN_BASE_PTRS; + +/* Array of FlexCAN IRQ number. */ +static const IRQn_Type s_flexcanRxWarningIRQ[] = CAN_Rx_Warning_IRQS; +static const IRQn_Type s_flexcanTxWarningIRQ[] = CAN_Tx_Warning_IRQS; +static const IRQn_Type s_flexcanWakeUpIRQ[] = CAN_Wake_Up_IRQS; +static const IRQn_Type s_flexcanErrorIRQ[] = CAN_Error_IRQS; +static const IRQn_Type s_flexcanBusOffIRQ[] = CAN_Bus_Off_IRQS; +static const IRQn_Type s_flexcanMbIRQ[] = CAN_ORed_Message_buffer_IRQS; + +/* Array of FlexCAN handle. */ +static flexcan_handle_t *s_flexcanHandle[ARRAY_SIZE(s_flexcanBases)]; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of FlexCAN clock name. */ +static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS; +#if defined(FLEXCAN_PERIPH_CLOCKS) +/* Array of FlexCAN serial clock name. */ +static const clock_ip_name_t s_flexcanPeriphClock[] = FLEXCAN_PERIPH_CLOCKS; +#endif /* FLEXCAN_PERIPH_CLOCKS */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* FlexCAN ISR for transactional APIs. */ +static flexcan_isr_t s_flexcanIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Get the FlexCAN instance from peripheral base address. + * + * param base FlexCAN peripheral base address. + * return FlexCAN instance. + */ +uint32_t FLEXCAN_GetInstance(CAN_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_flexcanBases); instance++) + { + if (s_flexcanBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_flexcanBases)); + + return instance; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) +static void FLEXCAN_EnterFreezeMode(CAN_Type *base) +{ + uint32_t u32TimeoutCount = 0U; + uint32_t u32TempMCR = 0U; + uint32_t u32TempIMASK1 = 0U; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint32_t u32TempIMASK2 = 0U; +#endif + + /* Step1: set FRZ enable in MCR. */ + base->MCR |= CAN_MCR_FRZ_MASK; + + /* Step2: to check if MDIS bit set in MCR. if yes, clear it. */ + if (0U != (base->MCR & CAN_MCR_MDIS_MASK)) + { + base->MCR &= ~CAN_MCR_MDIS_MASK; + } + + /* Step3: polling LPMACK. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT; + while ((0U == (base->MCR & CAN_MCR_LPMACK_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + + /* Step4: to check FLTCONF in ESR1 register */ + if (0U == (base->ESR1 & CAN_ESR1_FLTCONF_BUSOFF)) + { + /* Step5B: Set Halt bits. */ + base->MCR |= CAN_MCR_HALT_MASK; + + /* Step6B: Poll the MCR register until the Freeze Acknowledge (FRZACK) bit is set, timeout need more than 178 + * CAN bit length, so 20 multiply timeout is enough. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT * 20U; + while ((0U == (base->MCR & CAN_MCR_FRZACK_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + } + else + { + /* backup MCR and IMASK register. Errata document not descript it, but we need backup for step 8A and 9A. */ + u32TempMCR = base->MCR; + u32TempIMASK1 = base->IMASK1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + u32TempIMASK2 = base->IMASK2; +#endif + + /* Step5A: Set the Soft Reset bit ((SOFTRST) in the MCR.*/ + base->MCR |= CAN_MCR_SOFTRST_MASK; + + /* Step6A: Poll the MCR register until the Soft Reset (SOFTRST) bit is cleared. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT; + while ((CAN_MCR_SOFTRST_MASK == (base->MCR & CAN_MCR_SOFTRST_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + + /* Step7A: Poll the MCR register until the Freeze Acknowledge (FRZACK) bit is set. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT; + while ((0U == (base->MCR & CAN_MCR_FRZACK_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + + /* Step8A: reconfig MCR. */ + base->MCR = u32TempMCR; + + /* Step9A: reconfig IMASK. */ + base->IMASK1 = u32TempIMASK1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK2 = u32TempIMASK2; +#endif + } +} +#else +static void FLEXCAN_EnterFreezeMode(CAN_Type *base) +{ + /* Set Freeze, Halt bits. */ + base->MCR |= CAN_MCR_FRZ_MASK; + base->MCR |= CAN_MCR_HALT_MASK; + while (0U == (base->MCR & CAN_MCR_FRZACK_MASK)) + { + } +} +#endif + +static void FLEXCAN_ExitFreezeMode(CAN_Type *base) +{ + /* Clear Freeze, Halt bits. */ + base->MCR &= ~CAN_MCR_HALT_MASK; + base->MCR &= ~CAN_MCR_FRZ_MASK; + + /* Wait until the FlexCAN Module exit freeze mode. */ + while (0U != (base->MCR & CAN_MCR_FRZACK_MASK)) + { + } +} + +#if !defined(NDEBUG) +static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) +{ + uint8_t lastOccupiedMb; + + /* Is Rx FIFO enabled? */ + if (base->MCR & CAN_MCR_RFEN_MASK) + { + /* Get RFFN value. */ + lastOccupiedMb = (uint8_t)((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + /* Calculate the number of last Message Buffer occupied by Rx FIFO. */ + lastOccupiedMb = ((lastOccupiedMb + 1U) * 2U) + 5U; + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + if (mbIdx <= (lastOccupiedMb + 1U)) +#else + if (mbIdx <= lastOccupiedMb) +#endif + { + return true; + } + else + { + return false; + } + } + else + { +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + if (0U == mbIdx) + { + return true; + } + else + { + return false; + } +#else + return false; +#endif + } +} +#endif + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) +static uint32_t FLEXCAN_GetFirstValidMb(CAN_Type *base) +{ + uint32_t firstValidMbNum; + + if (base->MCR & CAN_MCR_RFEN_MASK) + { + firstValidMbNum = ((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + firstValidMbNum = ((firstValidMbNum + 1U) * 2U) + 6U; + } + else + { + firstValidMbNum = 0; + } + + return firstValidMbNum; +} +#endif + +static bool FLEXCAN_IsMbIntEnabled(CAN_Type *base, uint8_t mbIdx) +{ + /* Assertion. */ + assert(mbIdx < (uint8_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)); + +#if (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + if (mbIdx < 32U) + { +#endif + if (0U != (base->IMASK1 & (((uint32_t)1U << mbIdx)))) + { + return true; + } + else + { + return false; + } +#if (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + } + else + { + if (base->IMASK2 & (1U << (mbIdx - 32U))) + { + return true; + } + else + { + return false; + } + } +#endif +} + +static void FLEXCAN_Reset(CAN_Type *base) +{ + /* The module must should be first exit from low power + * mode, and then soft reset can be applied. + */ + assert(0U == (base->MCR & CAN_MCR_MDIS_MASK)); + + uint8_t i; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + if (0 != (FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(base))) + { + /* De-assert DOZE Enable Bit. */ + base->MCR &= ~CAN_MCR_DOZE_MASK; + } +#endif + + /* Wait until FlexCAN exit from any Low Power Mode. */ + while (0U != (base->MCR & CAN_MCR_LPMACK_MASK)) + { + } + + /* Assert Soft Reset Signal. */ + base->MCR |= CAN_MCR_SOFTRST_MASK; + /* Wait until FlexCAN reset completes. */ + while (0U != (base->MCR & CAN_MCR_SOFTRST_MASK)) + { + } + +/* Reset MCR register. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) && FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) + base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK | + CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); +#else + base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB(FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1); +#endif + +/* Reset CTRL1 and CTRL2 register. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + /* SMP bit cannot be asserted when CAN FD is enabled */ + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { + base->CTRL1 = 0x0; + } + else + { + base->CTRL1 = CAN_CTRL1_SMP_MASK; + } +#else + base->CTRL1 = CAN_CTRL1_SMP_MASK; +#endif + base->CTRL2 = CAN_CTRL2_TASD(0x16) | CAN_CTRL2_RRS_MASK | CAN_CTRL2_EACEN_MASK; + + /* Clean all individual Rx Mask of Message Buffers. */ + for (i = 0; i < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++) + { + base->RXIMR[i] = 0x3FFFFFFF; + } + + /* Clean Global Mask of Message Buffers. */ + base->RXMGMASK = 0x3FFFFFFF; + /* Clean Global Mask of Message Buffer 14. */ + base->RX14MASK = 0x3FFFFFFF; + /* Clean Global Mask of Message Buffer 15. */ + base->RX15MASK = 0x3FFFFFFF; + /* Clean Global Mask of Rx FIFO. */ + base->RXFGMASK = 0x3FFFFFFF; + + /* Clean all Message Buffer CS fields. */ + for (i = 0; i < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++) + { + base->MB[i].CS = 0x0; + } +} + +static void FLEXCAN_SetBaudRate(CAN_Type *base, + uint32_t sourceClock_Hz, + uint32_t baudRate_Bps, + flexcan_timing_config_t timingConfig) +{ + /* FlexCAN timing setting formula: + * quantum = 1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1); + */ + uint32_t quantum = (1U + ((uint32_t)timingConfig.phaseSeg1 + 1U) + ((uint32_t)timingConfig.phaseSeg2 + 1U) + + ((uint32_t)timingConfig.propSeg + 1U)); + uint32_t priDiv = baudRate_Bps * quantum; + + /* Assertion: Desired baud rate is too high. */ + assert(baudRate_Bps <= 1000000U); + /* Assertion: Source clock should greater than baud rate * quantum. */ + assert(priDiv <= sourceClock_Hz); + + if (0U == priDiv) + { + priDiv = 1; + } + + priDiv = (sourceClock_Hz / priDiv) - 1U; + + /* Desired baud rate is too low. */ + if (priDiv > 0xFFU) + { + priDiv = 0xFF; + } + + timingConfig.preDivider = (uint16_t)priDiv; + + /* Update actual timing characteristic. */ + FLEXCAN_SetTimingConfig(base, (const flexcan_timing_config_t *)(uint32_t)&timingConfig); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +static void FLEXCAN_SetFDBaudRate(CAN_Type *base, + uint32_t sourceClock_Hz, + uint32_t baudRateFD_Bps, + flexcan_timing_config_t timingConfig) +{ + /* FlexCAN FD timing setting formula: + * quantum = 1 + (FPSEG1 + 1) + (FPSEG2 + 1) + FPROPSEG; + */ + uint32_t quantum = (1U + ((uint32_t)timingConfig.fphaseSeg1 + 1U) + ((uint32_t)timingConfig.fphaseSeg2 + 1U) + + (uint32_t)timingConfig.fpropSeg); + uint32_t priDiv = baudRateFD_Bps * quantum; + + /* Assertion: Desired baud rate is too high. */ + assert(baudRateFD_Bps <= 8000000U); + /* Assertion: Source clock should greater than baud rate * FLEXCAN_TIME_QUANTA_NUM. */ + assert(priDiv <= sourceClock_Hz); + + if (0U == priDiv) + { + priDiv = 1; + } + + priDiv = (sourceClock_Hz / priDiv) - 1U; + + /* Desired baud rate is too low. */ + if (priDiv > 0xFFU) + { + priDiv = 0xFF; + } + + timingConfig.fpreDivider = (uint16_t)priDiv; + + /* Update actual timing characteristic. */ + FLEXCAN_SetFDTimingConfig(base, (const flexcan_timing_config_t *)(uint32_t)&timingConfig); +} +#endif + +/*! + * brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_Init function by passing in these parameters. + * code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc; + * flexcanConfig.baudRate = 1000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_Init(CAN0, &flexcanConfig, 8000000UL); + * endcode + * + * param base FlexCAN peripheral base address. + * param config Pointer to the user-defined configuration structure. + * param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + */ +void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz) +{ + uint32_t mcrTemp; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance; +#endif + + /* Assertion. */ + assert(NULL != config); + assert((config->maxMbNum > 0U) && + (config->maxMbNum <= (uint8_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base))); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + instance = FLEXCAN_GetInstance(base); + /* Enable FlexCAN clock. */ + CLOCK_EnableClock(s_flexcanClock[instance]); +#if defined(FLEXCAN_PERIPH_CLOCKS) + /* Enable FlexCAN serial clock. */ + CLOCK_EnableClock(s_flexcanPeriphClock[instance]); +#endif /* FLEXCAN_PERIPH_CLOCKS */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE + /* Disable FlexCAN Module. */ + FLEXCAN_Enable(base, false); + + /* Protocol-Engine clock source selection, This bit must be set + * when FlexCAN Module in Disable Mode. + */ + base->CTRL1 = (kFLEXCAN_ClkSrcOsc == config->clkSrc) ? (base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK) : + (base->CTRL1 | CAN_CTRL1_CLKSRC_MASK); +#else +#if defined(CAN_CTRL1_CLKSRC_MASK) + if (!FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(base)) + { + /* Disable FlexCAN Module. */ + FLEXCAN_Enable(base, false); + + /* Protocol-Engine clock source selection, This bit must be set + * when FlexCAN Module in Disable Mode. + */ + base->CTRL1 = (kFLEXCAN_ClkSrcOsc == config->clkSrc) ? (base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK) : + (base->CTRL1 | CAN_CTRL1_CLKSRC_MASK); + } +#endif +#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ + + /* Enable FlexCAN Module for configuration. */ + FLEXCAN_Enable(base, true); + + /* Reset to known status. */ + FLEXCAN_Reset(base); + + /* Save current MCR value and enable to enter Freeze mode(enabled by default). */ + mcrTemp = base->MCR; + + /* Set the maximum number of Message Buffers */ + mcrTemp = (mcrTemp & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB((uint32_t)config->maxMbNum - 1U); + + /* Enable Loop Back Mode? */ + base->CTRL1 = + (true == config->enableLoopBack) ? (base->CTRL1 | CAN_CTRL1_LPB_MASK) : (base->CTRL1 & ~CAN_CTRL1_LPB_MASK); + + /* Enable Timer Sync? */ + base->CTRL1 = + (true == config->enableTimerSync) ? (base->CTRL1 | CAN_CTRL1_TSYN_MASK) : (base->CTRL1 & ~CAN_CTRL1_TSYN_MASK); + + /* Enable Self Wake Up Mode and configure the wake up source. */ + mcrTemp = (true == config->enableSelfWakeup) ? (mcrTemp | CAN_MCR_SLFWAK_MASK) : (mcrTemp & ~CAN_MCR_SLFWAK_MASK); + mcrTemp = (kFLEXCAN_WakeupSrcFiltered == config->wakeupSrc) ? (mcrTemp | CAN_MCR_WAKSRC_MASK) : + (mcrTemp & ~CAN_MCR_WAKSRC_MASK); + + /* Enable Individual Rx Masking? */ + mcrTemp = (true == config->enableIndividMask) ? (mcrTemp | CAN_MCR_IRMQ_MASK) : (mcrTemp & ~CAN_MCR_IRMQ_MASK); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(base)) + { + /* Enable Doze Mode? */ + mcrTemp = (true == config->enableDoze) ? (mcrTemp | CAN_MCR_DOZE_MASK) : (mcrTemp & ~CAN_MCR_DOZE_MASK); + } +#endif + + /* Save MCR Configuration. */ + base->MCR = mcrTemp; + + /* Baud Rate Configuration.*/ + FLEXCAN_SetBaudRate(base, sourceClock_Hz, config->baudRate, config->timingConfig); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_FDInit function by passing in these parameters. + * code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc; + * flexcanConfig.baudRate = 1000000U; + * flexcanConfig.baudRateFD = 2000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_FDInit(CAN0, &flexcanConfig, 8000000UL, kFLEXCAN_16BperMB, false); + * endcode + * + * param base FlexCAN peripheral base address. + * param config Pointer to the user-defined configuration structure. + * param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + * param dataSize FlexCAN FD frame payload size. + * param brs If bitrate switch is enabled in FD mode. + */ +void FLEXCAN_FDInit( + CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs) +{ + uint32_t fdctrl = 0U; + assert((uint32_t)dataSize <= 3U); + + /* Initialization of classical CAN. */ + FLEXCAN_Init(base, config, sourceClock_Hz); + + /* Extra bitrate setting for CANFD. */ + FLEXCAN_SetFDBaudRate(base, sourceClock_Hz, config->baudRateFD, config->timingConfig); + + /* read FDCTRL register. */ + fdctrl = base->FDCTRL; + + /* Enable FD operation and set bitrate switch. */ + if (brs) + { + fdctrl &= CAN_FDCTRL_FDRATE_MASK; + } + else + { + fdctrl &= ~CAN_FDCTRL_FDRATE_MASK; + } + + if ((true == brs) && (false == config->enableLoopBack)) + { + /* Before use "|=" operation for multi-bits field, CPU should Clean previous Setting. */ + fdctrl = (fdctrl & ~CAN_FDCTRL_TDCOFF_MASK) | CAN_FDCTRL_TDCOFF(0x2U); + } + + /* Before use "|=" operation for multi-bits field, CPU should clean previous Setting. */ + fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR0_MASK) | CAN_FDCTRL_MBDSR0(dataSize); +#if defined(CAN_FDCTRL_MBDSR1_MASK) + fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR1_MASK) | CAN_FDCTRL_MBDSR1(dataSize); +#endif +#if defined(CAN_FDCTRL_MBDSR2_MASK) + fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR2_MASK) | CAN_FDCTRL_MBDSR2(dataSize); +#endif +#if defined(CAN_FDCTRL_MBDSR3_MASK) + fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR3_MASK) | CAN_FDCTRL_MBDSR3(dataSize); +#endif + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + base->MCR |= CAN_MCR_FDEN_MASK; + + /* update the FDCTL register. */ + base->FDCTRL = fdctrl; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} +#endif + +/*! + * brief De-initializes a FlexCAN instance. + * + * This function disables the FlexCAN module clock and sets all register values + * to the reset value. + * + * param base FlexCAN peripheral base address. + */ +void FLEXCAN_Deinit(CAN_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance; +#endif + /* Reset all Register Contents. */ + FLEXCAN_Reset(base); + + /* Disable FlexCAN module. */ + FLEXCAN_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + instance = FLEXCAN_GetInstance(base); +#if defined(FLEXCAN_PERIPH_CLOCKS) + /* Disable FlexCAN serial clock. */ + CLOCK_DisableClock(s_flexcanPeriphClock[instance]); +#endif /* FLEXCAN_PERIPH_CLOCKS */ + /* Disable FlexCAN clock. */ + CLOCK_DisableClock(s_flexcanClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the FlexCAN configuration structure to default values. The default + * values are as follows. + * flexcanConfig->clkSrc = kFLEXCAN_ClkSrcOsc; + * flexcanConfig->baudRate = 1000000U; + * flexcanConfig->baudRateFD = 2000000U; + * flexcanConfig->maxMbNum = 16; + * flexcanConfig->enableLoopBack = false; + * flexcanConfig->enableSelfWakeup = false; + * flexcanConfig->enableIndividMask = false; + * flexcanConfig->enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * + * param config Pointer to the FlexCAN configuration structure. + */ +void FLEXCAN_GetDefaultConfig(flexcan_config_t *config) +{ + /* Assertion. */ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Initialize FlexCAN Module config struct with default value. */ + config->clkSrc = kFLEXCAN_ClkSrcOsc; + config->baudRate = 1000000U; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + config->baudRateFD = 2000000U; +#endif + config->maxMbNum = 16; + config->enableLoopBack = false; + config->enableTimerSync = true; + config->enableSelfWakeup = false; + config->wakeupSrc = kFLEXCAN_WakeupSrcUnfiltered; + config->enableIndividMask = false; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + config->enableDoze = false; +#endif + /* Default protocol timing configuration, time quantum is 10. */ + config->timingConfig.phaseSeg1 = 3; + config->timingConfig.phaseSeg2 = 2; + config->timingConfig.propSeg = 1; + config->timingConfig.rJumpwidth = 1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + config->timingConfig.fphaseSeg1 = 3; + config->timingConfig.fphaseSeg2 = 3; + config->timingConfig.fpropSeg = 1; + config->timingConfig.frJumpwidth = 1; +#endif +} + +/*! + * brief Sets the FlexCAN protocol timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the FLEXCAN_Init() and fill the baud rate field with a desired value. + * This provides the default timing characteristics to the module. + * + * Note that calling FLEXCAN_SetTimingConfig() overrides the baud rate set + * in FLEXCAN_Init(). + * + * param base FlexCAN peripheral base address. + * param config Pointer to the timing configuration structure. + */ +void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config) +{ + /* Assertion. */ + assert(NULL != config); + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { + /* Cleaning previous Timing Setting. */ + base->CBT &= ~(CAN_CBT_EPRESDIV_MASK | CAN_CBT_ERJW_MASK | CAN_CBT_EPSEG1_MASK | CAN_CBT_EPSEG2_MASK | + CAN_CBT_EPROPSEG_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->CBT |= + (CAN_CBT_EPRESDIV(config->preDivider) | CAN_CBT_ERJW(config->rJumpwidth) | + CAN_CBT_EPSEG1(config->phaseSeg1) | CAN_CBT_EPSEG2(config->phaseSeg2) | CAN_CBT_EPROPSEG(config->propSeg)); + } + else + { + /* Cleaning previous Timing Setting. */ + base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | + CAN_CTRL1_PROPSEG_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->CTRL1 |= (CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) | + CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | + CAN_CTRL1_PROPSEG(config->propSeg)); + } +#else + /* Cleaning previous Timing Setting. */ + base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | + CAN_CTRL1_PROPSEG_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->CTRL1 |= + (CAN_CTRL1_PRESDIV(config->preDivider) | CAN_CTRL1_RJW(config->rJumpwidth) | + CAN_CTRL1_PSEG1(config->phaseSeg1) | CAN_CTRL1_PSEG2(config->phaseSeg2) | CAN_CTRL1_PROPSEG(config->propSeg)); +#endif + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Sets the FlexCAN FD protocol timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the FLEXCAN_Init() and fill the baud rate field with a desired value. + * This provides the default timing characteristics to the module. + * + * Note that calling FLEXCAN_SetFDTimingConfig() overrides the baud rate set + * in FLEXCAN_Init(). + * + * param base FlexCAN peripheral base address. + * param config Pointer to the timing configuration structure. + */ +void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config) +{ + /* Assertion. */ + assert(NULL != config); + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + base->CBT |= CAN_CBT_BTF(1); + /* Cleaning previous Timing Setting. */ + base->FDCBT &= ~(CAN_FDCBT_FPRESDIV_MASK | CAN_FDCBT_FRJW_MASK | CAN_FDCBT_FPSEG1_MASK | CAN_FDCBT_FPSEG2_MASK | + CAN_FDCBT_FPROPSEG_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->FDCBT |= (CAN_FDCBT_FPRESDIV(config->fpreDivider) | CAN_FDCBT_FRJW(config->frJumpwidth) | + CAN_FDCBT_FPSEG1(config->fphaseSeg1) | CAN_FDCBT_FPSEG2(config->fphaseSeg2) | + CAN_FDCBT_FPROPSEG(config->fpropSeg)); + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} +#endif + +/*! + * brief Sets the FlexCAN receive message buffer global mask. + * + * This function sets the global mask for the FlexCAN message buffer in a matching process. + * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init(). + * + * param base FlexCAN peripheral base address. + * param mask Rx Message Buffer Global Mask value. + */ +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) +{ + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Setting Rx Message Buffer Global Mask value. */ + base->RXMGMASK = mask; + base->RX14MASK = mask; + base->RX15MASK = mask; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +/*! + * brief Sets the FlexCAN receive FIFO global mask. + * + * This function sets the global mask for FlexCAN FIFO in a matching process. + * + * param base FlexCAN peripheral base address. + * param mask Rx Fifo Global Mask value. + */ +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) +{ + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Setting Rx FIFO Global Mask value. */ + base->RXFGMASK = mask; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +/*! + * brief Sets the FlexCAN receive individual mask. + * + * This function sets the individual mask for the FlexCAN matching process. + * The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). + * If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. + * If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to + * the Rx Filter with the same index. Note that only the first 32 + * individual masks can be used as the Rx FIFO filter mask. + * + * param base FlexCAN peripheral base address. + * param maskIdx The Index of individual Mask. + * param mask Rx Individual Mask value. + */ +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) +{ + assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Setting Rx Individual Mask value. */ + base->RXIMR[maskIdx] = mask; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +/*! + * brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + + /* Inactivate Message Buffer. */ + if (enable) + { + base->MB[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + } + else + { + base->MB[mbIdx].CS = 0; + } + + /* Clean Message Buffer content. */ + base->MB[mbIdx].ID = 0x0; + base->MB[mbIdx].WORD0 = 0x0; + base->MB[mbIdx].WORD1 = 0x0; +} + +/*! + * @brief Calculates the segment values for a single bit time for classical CAN + * + * @param baudRate The data speed in bps + * @param tqNum Number of time quantas per bit + * @param pconfig Pointer to the FlexCAN timing configuration structure. + * + */ +static void FLEXCAN_GetSegments(uint32_t baudRate, uint32_t tqNum, flexcan_timing_config_t *pconfig) +{ + uint32_t ideal_sp; + uint32_t p1; + + /* get ideal sample point. */ + if (baudRate >= 1000000) + ideal_sp = IDEAL_SP_LOW; + else if (baudRate >= 800000) + ideal_sp = IDEAL_SP_MID; + else + ideal_sp = IDEAL_SP_HIGH; + + /* distribute time quanta. */ + p1 = tqNum * (uint32_t)ideal_sp; + pconfig->propSeg = 0; + pconfig->phaseSeg1 = p1 / IDEAL_SP_FACTOR - 2U; + if (pconfig->phaseSeg1 > (MAX_PSEG1 + MAX_PROPSEG)) + { + pconfig->phaseSeg1 = MAX_PSEG1; + pconfig->propSeg = MAX_PROPSEG; + } + else if (pconfig->phaseSeg1 > MAX_PSEG1) + { + pconfig->propSeg = pconfig->phaseSeg1 - MAX_PSEG1; + pconfig->phaseSeg1 = MAX_PSEG1; + } + pconfig->phaseSeg2 = tqNum - (1U + pconfig->phaseSeg1 + 1U + pconfig->propSeg + 1U + 1U); + assert(pconfig->phaseSeg2 <= MAX_PSEG2); + + /* subtract one TQ for sync seg. */ + /* sjw is 20% of total TQ, rounded to nearest int. */ + pconfig->rJumpwidth = (tqNum + (5 - 1)) / 5 - 1U; + if (pconfig->rJumpwidth > MAX_RJW) + { + pconfig->rJumpwidth = MAX_RJW; + } +} + +/*! + * @brief Calculates the improved timing values by specific baudrates for classical CAN + * + * @param baudRate The classical CAN speed in bps defined by user + * @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching + * @param pconfig Pointer to the FlexCAN timing configuration structure. + * + * @return TRUE if timing configuration found, FALSE if failed to find configuration + */ +bool FLEXCAN_CalculateImprovedTimingValues(uint32_t baudRate, uint32_t sourceClock_Hz, flexcan_timing_config_t *pconfig) +{ + uint32_t clk; /* the clock is tqNumb x baudRateFD. */ + uint32_t clk2; /* the clock2 is clk2 / Pre-scaler Division Factor. */ + uint32_t tqNum; /* Numbers of TQ. */ + + /* observe baud rate maximums. */ + assert(baudRate <= MAX_CAN_BAUDRATE); + + /* Auto Improved Protocal timing for CBT. */ + for (tqNum = CTRL1_MAX_TIME_QUANTA; tqNum >= CTRL1_MIN_TIME_QUANTA; tqNum--) + { + clk = baudRate * tqNum; + if (clk > sourceClock_Hz) + { + continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */ + } + + for (pconfig->preDivider = 0x00; pconfig->preDivider <= MAX_PRESDIV; (pconfig->preDivider)++) + { + /* Consider some proessor not contain FPU, the parameter need to be exact division. */ + if ((clk / (pconfig->preDivider + 1U) * (pconfig->preDivider + 1U)) != clk) + { + continue; /* clk need to be exact division by preDivider + 1. */ + } + clk2 = clk / (pconfig->preDivider + 1U); + if (((sourceClock_Hz / clk2) * clk2) != sourceClock_Hz) + { + continue; /* sourceClock_Hz need to be exact division by preDivider. */ + } + FLEXCAN_GetSegments(baudRate, tqNum, pconfig); + return true; + } + } + /* failed to find solution. */ + return false; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx) +{ + uint32_t dataSize; + uint32_t offset = 0; + dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + switch (dataSize) + { + case (uint32_t)kFLEXCAN_8BperMB: + offset = (((uint32_t)mbIdx / 32U) * 512U + ((uint32_t)mbIdx % 32U) * 16U); + break; + case (uint32_t)kFLEXCAN_16BperMB: + offset = (((uint32_t)mbIdx / 21U) * 512U + ((uint32_t)mbIdx % 21U) * 24U); + break; + case (uint32_t)kFLEXCAN_32BperMB: + offset = (((uint32_t)mbIdx / 12U) * 512U + ((uint32_t)mbIdx % 12U) * 40U); + break; + case (uint32_t)kFLEXCAN_64BperMB: + offset = (((uint32_t)mbIdx / 7U) * 512U + ((uint32_t)mbIdx % 7U) * 72U); + break; + default: + /* All the cases have been listed above, the default clause should not be reached. */ + assert(false); + break; + } + /* To get the dword aligned offset, need to divide by 4. */ + offset = offset / 4U; + return offset; +} + +/*! + * @brief Calculates the segment values for a single bit time for CANFD bus control baud Rate + * + * @param baudRate The canfd bus control speed in bps + * @param tqNum Number of time quanta per bit + * @param pconfig Pointer to the FlexCAN timing configuration structure. + * + */ +static void FLEXCAN_FDGetSegments(uint32_t baudRate, uint32_t tqNum, flexcan_timing_config_t *pconfig) +{ + uint32_t ideal_sp; + uint32_t p1; + + /* get ideal sample point. */ + if (baudRate >= 1000000) + ideal_sp = IDEAL_SP_LOW; + else if (baudRate >= 800000) + ideal_sp = IDEAL_SP_MID; + else + ideal_sp = IDEAL_SP_HIGH; + + /* distribute time quanta. */ + p1 = tqNum * (uint32_t)ideal_sp; + pconfig->propSeg = 0; + pconfig->phaseSeg1 = p1 / IDEAL_SP_FACTOR - 2U; + if (pconfig->phaseSeg1 > (MAX_EPSEG1 + MAX_EPROPSEG)) + { + pconfig->phaseSeg1 = MAX_EPSEG1; + pconfig->propSeg = MAX_EPROPSEG; + } + else if (pconfig->phaseSeg1 > MAX_EPSEG1) + { + pconfig->propSeg = pconfig->phaseSeg1 - MAX_EPSEG1; + pconfig->phaseSeg1 = MAX_EPSEG1; + } + + pconfig->phaseSeg2 = tqNum - (1U + pconfig->phaseSeg1 + 1U + pconfig->propSeg + 1U + 1U); + assert(pconfig->phaseSeg2 <= MAX_EPSEG2); + + /* subtract one TQ for sync seg. */ + /* sjw is 20% of total TQ, rounded to nearest int. */ + pconfig->rJumpwidth = (tqNum + (5 - 1)) / 5 - 1U; + /* the max tqNum for CBT will reach to 129, ERJW would not larger than 26. */ + /* Consider and max ERJW is 31, so rJumpwidth will always smaller than MAX_ERJW. */ + assert(pconfig->rJumpwidth <= MAX_ERJW); +} + +/*! + * @brief Calculates the segment values for a single bit time for CANFD bus data baud Rate + * + * @param baudRate The canfd bus data speed in bps + * @param tqNum Number of time quanta per bit + * @param pconfig Pointer to the FlexCAN timing configuration structure. + * + */ +static void FLEXCAN_FDGetSegmentswithBRS(uint32_t baudRateFD, uint32_t tqNum, flexcan_timing_config_t *pconfig) +{ + uint32_t ideal_sp; + uint32_t p1; + + /* get ideal sample point. */ + if (baudRateFD >= 1000000) + ideal_sp = IDEAL_SP_LOW; + else if (baudRateFD >= 800000) + ideal_sp = IDEAL_SP_MID; + else + ideal_sp = IDEAL_SP_HIGH; + + /* distribute time quanta. */ + p1 = tqNum * (uint32_t)ideal_sp; + pconfig->fpropSeg = 0; + pconfig->fphaseSeg1 = p1 / IDEAL_SP_FACTOR - 1U; + if (pconfig->fphaseSeg1 > (MAX_FPSEG1 + MAX_FPROPSEG)) + { + pconfig->fphaseSeg1 = MAX_FPSEG1; + pconfig->fpropSeg = MAX_FPROPSEG; + } + else if (pconfig->fphaseSeg1 > MAX_FPSEG1) + { + pconfig->fpropSeg = pconfig->fphaseSeg1 - MAX_FPSEG1; + pconfig->fphaseSeg1 = MAX_FPSEG1; + } + + pconfig->fphaseSeg2 = tqNum - (1U + pconfig->fphaseSeg1 + 1U + pconfig->fpropSeg + 0U + 1U); + + assert(pconfig->fphaseSeg2 <= MAX_FPSEG2); + + /* subtract one TQ for sync seg. */ + /* sjw is 20% of total TQ, rounded to nearest int. */ + pconfig->frJumpwidth = (tqNum + (5 - 1)) / 5 - 1U; + + if (pconfig->frJumpwidth > MAX_FRJW) + { + pconfig->frJumpwidth = MAX_FRJW; + } +} + +/*! + * @brief Calculates the improved timing values by specific baudrates for CANFD + * + * @param baudRate The CANFD bus control speed in bps defined by user + * @param baudRateFD The CANFD bus data speed in bps defined by user + * @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching + * @param pconfig Pointer to the FlexCAN timing configuration structure. + * + * @return TRUE if timing configuration found, FALSE if failed to find configuration + */ +bool FLEXCAN_FDCalculateImprovedTimingValues(uint32_t baudRate, + uint32_t baudRateFD, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pconfig) +{ + uint32_t clk, clkbrs; + uint32_t clk2, clkbrs2; + uint32_t tqNum, tqNumbrs; /* Numbers of TQ. */ + + /* observe baud rate maximums */ + assert(baudRate <= MAX_CAN_BAUDRATE); + assert(baudRateFD <= MAX_CANFD_BAUDRATE); + + /* Auto Improved Protocal timing for CBT. */ + for (tqNum = CBT_MAX_TIME_QUANTA; tqNum >= CBT_MIN_TIME_QUANTA; tqNum--) + { + clk = baudRate * tqNum; + if (clk > sourceClock_Hz) + { + continue; /* tqNum too large, clk x tqNum has been exceed sourceClock_Hz. */ + } + + for (pconfig->preDivider = 0x00; pconfig->preDivider <= MAX_EPRESDIV; (pconfig->preDivider)++) + { + /* Consider some proessor not contain FPU, the parameter need to be exact division. */ + if ((clk / (pconfig->preDivider + 1U) * (pconfig->preDivider + 1U)) != clk) + { + continue; /* clk need to be exact division by preDivider + 1. */ + } + clk2 = clk / (pconfig->preDivider + 1U); + + if ((sourceClock_Hz / clk2 * clk2) != sourceClock_Hz) + { + continue; /* sourceClock_Hz need to be exact division by clk2. */ + } + FLEXCAN_FDGetSegments(baudRate, tqNum, pconfig); + /* After calculate for CBT, continue to calculate FBCBT field timing configuration. */ + for (tqNumbrs = FDCBT_MAX_TIME_QUANTA; tqNumbrs >= FDCBT_MIN_TIME_QUANTA; tqNumbrs--) + { + clkbrs = baudRateFD * tqNumbrs; + if (clkbrs > sourceClock_Hz) + { + continue; /* tqNumbrs too large, clkbrs x tqNumbrs has been exceed sourceClock_Hz. */ + } + for (pconfig->fpreDivider = 0x00; pconfig->fpreDivider <= MAX_FPRESDIV; (pconfig->fpreDivider)++) + { + /* Consider some proessor not contain FPU, the parameter need to be exact division. */ + if ((clkbrs / (pconfig->fpreDivider + 1U) * (pconfig->fpreDivider + 1U)) != clkbrs) + { + continue; /* clk need to be exact division by preDivider + 1. */ + } + clkbrs2 = clkbrs / (pconfig->fpreDivider + 1U); + if ((sourceClock_Hz / clkbrs2 * clkbrs2) != sourceClock_Hz) + { + continue; /* sourceClock_Hz need to be exact division by preDivider. */ + } + FLEXCAN_FDGetSegmentswithBRS(baudRateFD, tqNumbrs, pconfig); + return true; + } + } + } + } + /* failed to find solution. */ + return false; +} +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + uint8_t cnt = 0; + uint8_t payload_dword = 1; + uint32_t dataSize; + dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); +#endif + + /* Inactivate Message Buffer. */ + if (enable) + { + /* Inactivate by writing CS. */ + mbAddr[offset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + } + else + { + mbAddr[offset] = 0x0; + } + + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < (dataSize + 1U); cnt++) + { + payload_dword *= 2U; + } + + /* Clean ID. */ + mbAddr[offset + 1U] = 0x0U; + /* Clean Message Buffer content, DWORD by DWORD. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + mbAddr[offset + 2U + cnt] = 0x0U; + } + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif +} +#endif + +/*! + * brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param config Pointer to the FlexCAN Message Buffer configuration structure. + * param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(((NULL != config) || (false == enable))); + assert(false == FLEXCAN_IsMbOccupied(base, mbIdx)); + + uint32_t cs_temp = 0; + + /* Inactivate Message Buffer. */ + base->MB[mbIdx].CS = 0; + + /* Clean Message Buffer content. */ + base->MB[mbIdx].ID = 0x0; + base->MB[mbIdx].WORD0 = 0x0; + base->MB[mbIdx].WORD1 = 0x0; + + if (enable) + { + /* Setup Message Buffer ID. */ + base->MB[mbIdx].ID = config->id; + + /* Setup Message Buffer format. */ + if (kFLEXCAN_FrameFormatExtend == config->format) + { + cs_temp |= CAN_CS_IDE_MASK; + } + + /* Setup Message Buffer type. */ + if (kFLEXCAN_FrameTypeRemote == config->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + /* Activate Rx Message Buffer. */ + cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty); + base->MB[mbIdx].CS = cs_temp; + } +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param config Pointer to the FlexCAN Message Buffer configuration structure. + * param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(((NULL != config) || (false == enable))); + assert(false == FLEXCAN_IsMbOccupied(base, mbIdx)); + + uint32_t cs_temp = 0; + uint8_t cnt = 0; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + uint8_t payload_dword = 1; + uint32_t dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + payload_dword = (2U << dataSize); + for (cnt = 0; cnt < payload_dword; cnt++) + { + mbAddr[offset + 2U + cnt] = 0x0; + } + + if (enable) + { + /* Setup Message Buffer ID. */ + mbAddr[offset + 1U] = config->id; + + /* Setup Message Buffer format. */ + if (kFLEXCAN_FrameFormatExtend == config->format) + { + cs_temp |= CAN_CS_IDE_MASK; + } + + /* Setup Message Buffer type. */ + if (kFLEXCAN_FrameTypeRemote == config->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + /* Activate Rx Message Buffer. */ + cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty); + mbAddr[offset] = cs_temp; + } +} +#endif + +/*! + * brief Configures the FlexCAN Rx FIFO. + * + * This function configures the Rx FIFO with given Rx FIFO configuration. + * + * param base FlexCAN peripheral base address. + * param config Pointer to the FlexCAN Rx FIFO configuration structure. + * param enable Enable/disable Rx FIFO. + * - true: Enable Rx FIFO. + * - false: Disable Rx FIFO. + */ +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable) +{ + /* Assertion. */ + assert((NULL != config) || (false == enable)); + + volatile uint32_t *idFilterRegion = (volatile uint32_t *)(&base->MB[6].CS); + uint8_t i, rffn = 0; + uint32_t setup_mb = 0; + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + { + assert(config->idFilterNum <= 128U); + + /* Get the setup_mb value. */ + setup_mb = (uint8_t)((base->MCR & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT); + setup_mb = (setup_mb < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) ? + setup_mb : + (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); + + /* Determine RFFN value. */ + for (i = 0; i <= 0xFU; i++) + { + if ((8U * (i + 1U)) >= config->idFilterNum) + { + rffn = i; + assert(((setup_mb - 8U) - (2U * rffn)) > 0U); + + base->CTRL2 = (base->CTRL2 & ~CAN_CTRL2_RFFN_MASK) | CAN_CTRL2_RFFN(rffn); + break; + } + } + } + else + { + rffn = (uint8_t)((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + } + + /* Clean ID filter table occuyied Message Buffer Region. */ + rffn = (uint8_t)((rffn + 1U) * 8U); + for (i = 0; i < rffn; i++) + { + idFilterRegion[i] = 0x0; + } + + if (enable) + { + /* Disable unused Rx FIFO Filter. */ + for (i = config->idFilterNum; i < rffn; i++) + { + idFilterRegion[i] = 0xFFFFFFFFU; + } + + /* Copy ID filter table to Message Buffer Region. */ + for (i = 0; i < config->idFilterNum; i++) + { + idFilterRegion[i] = config->idFilterTable[i]; + } + + /* Setup ID Fitlter Type. */ + switch (config->idFilterType) + { + case kFLEXCAN_RxFifoFilterTypeA: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x0); + break; + case kFLEXCAN_RxFifoFilterTypeB: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x1); + break; + case kFLEXCAN_RxFifoFilterTypeC: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x2); + break; + case kFLEXCAN_RxFifoFilterTypeD: + /* All frames rejected. */ + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x3); + break; + default: + /* All the cases have been listed above, the default clause should not be reached. */ + assert(false); + break; + } + + /* Setting Message Reception Priority. */ + base->CTRL2 = (config->priority == kFLEXCAN_RxFifoPrioHigh) ? (base->CTRL2 & ~CAN_CTRL2_MRP_MASK) : + (base->CTRL2 | CAN_CTRL2_MRP_MASK); + + /* Enable Rx Message FIFO. */ + base->MCR |= CAN_MCR_RFEN_MASK; + } + else + { + /* Disable Rx Message FIFO. */ + base->MCR &= ~CAN_MCR_RFEN_MASK; + + /* Clean MB0 ~ MB5. */ + FLEXCAN_SetRxMbConfig(base, 0, NULL, false); + FLEXCAN_SetRxMbConfig(base, 1, NULL, false); + FLEXCAN_SetRxMbConfig(base, 2, NULL, false); + FLEXCAN_SetRxMbConfig(base, 3, NULL, false); + FLEXCAN_SetRxMbConfig(base, 4, NULL, false); + FLEXCAN_SetRxMbConfig(base, 5, NULL, false); + } + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) +/*! + * brief Enables or disables the FlexCAN Rx FIFO DMA request. + * + * This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO. + * + * param base FlexCAN peripheral base address. + * param enable true to enable, false to disable. + */ +void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable) +{ + if (enable) + { + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Enable FlexCAN DMA. */ + base->MCR |= CAN_MCR_DMA_MASK; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); + } + else + { + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Disable FlexCAN DMA. */ + base->MCR &= ~CAN_MCR_DMA_MASK; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); + } +} +#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) +/*! + * FlexCAN: A frame with wrong ID or payload is transmitted into + * the CAN bus when the Message Buffer under transmission is + * either aborted or deactivated while the CAN bus is in the Bus Idle state + * + * This function to do workaround for ERR006032 + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + */ +static void FLEXCAN_ERRATA_6032(CAN_Type *base, volatile uint32_t *mbCSAddr) +{ + uint32_t dbg_temp = 0U; + uint32_t u32TempCS = 0U; + uint32_t u32Timeout = DELAY_BUSIDLE; + uint32_t u32TempIMASK1 = base->IMASK1; +/*after backup all interruption, disable ALL interruption*/ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint32_t u32TempIMASK2 = base->IMASK2; + base->IMASK2 = 0; +#endif + base->IMASK1 = 0; + dbg_temp = (uint32_t)(base->DBG1); + switch (dbg_temp & CAN_DBG1_CFSM_MASK) + { + case RXINTERMISSION: + if (CBN_VALUE3 == (dbg_temp & CAN_DBG1_CBN_MASK)) + { + /*wait until CFSM is different from RXINTERMISSION */ + while (RXINTERMISSION == (base->DBG1 & CAN_DBG1_CFSM_MASK)) + { + __NOP(); + } + } + break; + case TXINTERMISSION: + if (CBN_VALUE3 == (dbg_temp & CAN_DBG1_CBN_MASK)) + { + /*wait until CFSM is different from TXINTERMISSION*/ + while (TXINTERMISSION == (base->DBG1 & CAN_DBG1_CFSM_MASK)) + { + __NOP(); + } + } + break; + default: + break; + } + /*Anyway, BUSIDLE need to delay*/ + if (BUSIDLE == (base->DBG1 & CAN_DBG1_CFSM_MASK)) + { + while (u32Timeout-- > 0) + { + __NOP(); + } + + /*Write 0x0 into Code field of CS word.*/ + u32TempCS = (uint32_t)(*mbCSAddr); + u32TempCS &= ~CAN_CS_CODE_MASK; + *mbCSAddr = u32TempCS; + } + /*restore interruption*/ + base->IMASK1 = u32TempIMASK1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK2 = u32TempIMASK2; +#endif +} +#endif + +/*! + * brief Writes a FlexCAN Message to the Transmit Message Buffer. + * + * This function writes a CAN Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN Message transmit. After + * that the function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + * param txFrame Pointer to CAN message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *txFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(NULL != txFrame); + assert(txFrame->length <= 8U); + assert(false == FLEXCAN_IsMbOccupied(base, mbIdx)); + + uint32_t cs_temp = 0; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) + FLEXCAN_ERRATA_6032(base, &(base->MB[mbIdx].CS)); +#endif + /* Check if Message Buffer is available. */ + if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK)) + { + /* Inactive Tx Message Buffer. */ + base->MB[mbIdx].CS = (base->MB[mbIdx].CS & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); + + /* Fill Message ID field. */ + base->MB[mbIdx].ID = txFrame->id; + + /* Fill Message Format field. */ + if ((uint32_t)kFLEXCAN_FrameFormatExtend == txFrame->format) + { + cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK; + } + + /* Fill Message Type field. */ + if ((uint32_t)kFLEXCAN_FrameTypeRemote == txFrame->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(txFrame->length); + + /* Load Message Payload. */ + base->MB[mbIdx].WORD0 = txFrame->dataWord0; + base->MB[mbIdx].WORD1 = txFrame->dataWord1; + + /* Activate Tx Message Buffer. */ + base->MB[mbIdx].CS = cs_temp; + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif + + return kStatus_Success; + } + else + { + /* Tx Message Buffer is activated, return immediately. */ + return kStatus_Fail; + } +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Writes a FlexCAN FD Message to the Transmit Message Buffer. + * + * This function writes a CAN FD Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN FD Message transmit. After + * that the function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN FD Message Buffer index. + * param txFrame Pointer to CAN FD message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *txFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(NULL != txFrame); + assert(false == FLEXCAN_IsMbOccupied(base, mbIdx)); + + uint32_t cs_temp = 0; + uint8_t cnt = 0; + uint32_t can_cs = 0; + uint8_t payload_dword = 1; + uint32_t dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); +#endif + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) + FLEXCAN_ERRATA_6032(base, &(mbAddr[offset])); +#endif + + can_cs = mbAddr[offset]; + /* Check if Message Buffer is available. */ + if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (can_cs & CAN_CS_CODE_MASK)) + { + /* Inactive Tx Message Buffer and Fill Message ID field. */ + mbAddr[offset] = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); + mbAddr[offset + 1U] = txFrame->id; + + /* Fill Message Format field. */ + if ((uint32_t)kFLEXCAN_FrameFormatExtend == txFrame->format) + { + cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK; + } + + /* Fill Message Type field. */ + if ((uint32_t)kFLEXCAN_FrameTypeRemote == txFrame->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(txFrame->length) | CAN_CS_EDL(1) | + CAN_CS_BRS(txFrame->brs); + + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < (dataSize + 1U); cnt++) + { + payload_dword *= 2U; + } + + /* Load Message Payload and Activate Tx Message Buffer. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + mbAddr[offset + 2U + cnt] = txFrame->dataWord[cnt]; + } + mbAddr[offset] = cs_temp; + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif + + return kStatus_Success; + } + else + { + /* Tx Message Buffer is activated, return immediately. */ + return kStatus_Fail; + } +} +#endif + +/*! + * brief Reads a FlexCAN Message from Receive Message Buffer. + * + * This function reads a CAN message from a specified Receive Message Buffer. + * The function fills a receive CAN message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + * param rxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(NULL != rxFrame); + assert(false == FLEXCAN_IsMbOccupied(base, mbIdx)); + + uint32_t cs_temp; + uint32_t rx_code; + + /* Read CS field of Rx Message Buffer to lock Message Buffer. */ + cs_temp = base->MB[mbIdx].CS; + /* Get Rx Message Buffer Code field. */ + rx_code = (cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT; + + /* Check to see if Rx Message Buffer is full. */ + if (((uint32_t)kFLEXCAN_RxMbFull == rx_code) || ((uint32_t)kFLEXCAN_RxMbOverrun == rx_code)) + { + /* Store Message ID. */ + rxFrame->id = base->MB[mbIdx].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) != 0U ? (uint32_t)kFLEXCAN_FrameFormatExtend : + (uint32_t)kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + rxFrame->type = + (cs_temp & CAN_CS_RTR_MASK) != 0U ? (uint32_t)kFLEXCAN_FrameTypeRemote : (uint32_t)kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + rxFrame->length = (uint8_t)((cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT); + + /* Get the time stamp. */ + rxFrame->timestamp = (uint16_t)((cs_temp & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + /* Store Message Payload. */ + rxFrame->dataWord0 = base->MB[mbIdx].WORD0; + rxFrame->dataWord1 = base->MB[mbIdx].WORD1; + + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + if ((uint32_t)kFLEXCAN_RxMbFull == rx_code) + { + return kStatus_Success; + } + else + { + return kStatus_FLEXCAN_RxOverflow; + } + } + else + { + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + return kStatus_Fail; + } +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Reads a FlexCAN FD Message from Receive Message Buffer. + * + * This function reads a CAN FD message from a specified Receive Message Buffer. + * The function fills a receive CAN FD message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN FD Message Buffer index. + * param rxFrame Pointer to CAN FD message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(NULL != rxFrame); + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); + + uint32_t cs_temp; + uint8_t rx_code; + uint8_t cnt = 0; + uint32_t can_id = 0; + uint32_t dataSize; + dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + uint8_t payload_dword = 1; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + + /* Read CS field of Rx Message Buffer to lock Message Buffer. */ + cs_temp = mbAddr[offset]; + can_id = mbAddr[offset + 1U]; + + /* Get Rx Message Buffer Code field. */ + rx_code = (uint8_t)((cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT); + + /* Check to see if Rx Message Buffer is full. */ + if (((uint8_t)kFLEXCAN_RxMbFull == rx_code) || ((uint8_t)kFLEXCAN_RxMbOverrun == rx_code)) + { + /* Store Message ID. */ + rxFrame->id = can_id & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) != 0U ? (uint32_t)kFLEXCAN_FrameFormatExtend : + (uint32_t)kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + rxFrame->type = + (cs_temp & CAN_CS_RTR_MASK) != 0U ? (uint32_t)kFLEXCAN_FrameTypeRemote : (uint32_t)kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + rxFrame->length = (uint8_t)((cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT); + + /* Get the time stamp. */ + rxFrame->timestamp = (uint16_t)((cs_temp & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < (dataSize + 1U); cnt++) + { + payload_dword *= 2U; + } + + /* Store Message Payload. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + rxFrame->dataWord[cnt] = mbAddr[offset + 2U + cnt]; + } + + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + if ((uint32_t)kFLEXCAN_RxMbFull == rx_code) + { + return kStatus_Success; + } + else + { + return kStatus_FLEXCAN_RxOverflow; + } + } + else + { + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + return kStatus_Fail; + } +} +#endif + +/*! + * brief Reads a FlexCAN Message from Rx FIFO. + * + * This function reads a CAN message from the FlexCAN build-in Rx FIFO. + * + * param base FlexCAN peripheral base address. + * param rxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame) +{ + /* Assertion. */ + assert(NULL != rxFrame); + + uint32_t cs_temp; + + /* Check if Rx FIFO is Enabled. */ + if (0U != (base->MCR & CAN_MCR_RFEN_MASK)) + { + /* Read CS field of Rx Message Buffer to lock Message Buffer. */ + cs_temp = base->MB[0].CS; + + /* Read data from Rx FIFO output port. */ + /* Store Message ID. */ + rxFrame->id = base->MB[0].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + rxFrame->format = (cs_temp & CAN_CS_IDE_MASK) != 0U ? (uint32_t)kFLEXCAN_FrameFormatExtend : + (uint32_t)kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + rxFrame->type = + (cs_temp & CAN_CS_RTR_MASK) != 0U ? (uint32_t)kFLEXCAN_FrameTypeRemote : (uint32_t)kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + rxFrame->length = (uint8_t)((cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT); + + /* Get the time stamp. */ + rxFrame->timestamp = (uint16_t)((cs_temp & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + /* Store Message Payload. */ + rxFrame->dataWord0 = base->MB[0].WORD0; + rxFrame->dataWord1 = base->MB[0].WORD1; + + /* Store ID Filter Hit Index. */ + rxFrame->idhit = (uint8_t)(base->RXFIR & CAN_RXFIR_IDHIT_MASK); + + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + return kStatus_Success; + } + else + { + return kStatus_Fail; + } +} + +/*! + * brief Performs a polling send transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN Message Buffer index. + * param txFrame Pointer to CAN message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame) +{ + /* Write Tx Message Buffer to initiate a data sending. */ + if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, (const flexcan_frame_t *)(uint32_t)txFrame)) + { +/* Wait until CAN Message send out. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64flag = 1; + while (0U == FLEXCAN_GetMbStatusFlags(base, u64flag << mbIdx)) +#else + uint32_t u32flag = 1; + while (0U == FLEXCAN_GetMbStatusFlags(base, u32flag << mbIdx)) +#endif + { + } + +/* Clean Tx Message Buffer Flag. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_ClearMbStatusFlags(base, u64flag << mbIdx); +#else + FLEXCAN_ClearMbStatusFlags(base, u32flag << mbIdx); +#endif + /*After TX MB tranfered success, update the Timestamp from MB[mbIdx].CS register*/ + txFrame->timestamp = (uint16_t)((base->MB[mbIdx].CS & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + return kStatus_Success; + } + else + { + return kStatus_Fail; + } +} + +/*! + * brief Performs a polling receive transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN Message Buffer index. + * param rxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame) +{ +/* Wait until Rx Message Buffer non-empty. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64flag = 1; + while (0U == FLEXCAN_GetMbStatusFlags(base, u64flag << mbIdx)) +#else + uint32_t u32flag = 1; + while (0U == FLEXCAN_GetMbStatusFlags(base, u32flag << mbIdx)) +#endif + { + } + +/* Clean Rx Message Buffer Flag. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_ClearMbStatusFlags(base, u64flag << mbIdx); +#else + FLEXCAN_ClearMbStatusFlags(base, u32flag << mbIdx); +#endif + + /* Read Received CAN Message. */ + return FLEXCAN_ReadRxMb(base, mbIdx, rxFrame); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Performs a polling send transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + * param txFrame Pointer to CAN FD message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *txFrame) +{ + /* Write Tx Message Buffer to initiate a data sending. */ + if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, (const flexcan_fd_frame_t *)(uint32_t)txFrame)) + { +/* Wait until CAN Message send out. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64flag = 1; + while (0U == FLEXCAN_GetMbStatusFlags(base, u64flag << mbIdx)) +#else + uint32_t u32flag = 1; + while (0U == FLEXCAN_GetMbStatusFlags(base, u32flag << mbIdx)) +#endif + { + } + +/* Clean Tx Message Buffer Flag. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_ClearMbStatusFlags(base, u64flag << mbIdx); +#else + FLEXCAN_ClearMbStatusFlags(base, u32flag << mbIdx); +#endif + /*After TX MB tranfered success, update the Timestamp from base->MB[offset for CANFD].CS register*/ + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + txFrame->timestamp = (uint16_t)((mbAddr[offset] & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + return kStatus_Success; + } + else + { + return kStatus_Fail; + } +} + +/*! + * brief Performs a polling receive transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + * param rxFrame Pointer to CAN FD message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame) +{ +/* Wait until Rx Message Buffer non-empty. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64flag = 1; + while (0U == FLEXCAN_GetMbStatusFlags(base, u64flag << mbIdx)) +#else + uint32_t u32flag = 1; + while (0U == FLEXCAN_GetMbStatusFlags(base, u32flag << mbIdx)) +#endif + { + } + +/* Clean Rx Message Buffer Flag. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_ClearMbStatusFlags(base, u64flag << mbIdx); +#else + FLEXCAN_ClearMbStatusFlags(base, u32flag << mbIdx); +#endif + + /* Read Received CAN Message. */ + return FLEXCAN_ReadFDRxMb(base, mbIdx, rxFrame); +} +#endif + +/*! + * brief Performs a polling receive transaction from Rx FIFO on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param rxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame) +{ + status_t rxFifoStatus; + + /* Wait until Rx FIFO non-empty. */ + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag)) + { + } + + /* */ + rxFifoStatus = FLEXCAN_ReadRxFifo(base, rxFrame); + + /* Clean Rx Fifo available flag. */ + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); + + return rxFifoStatus; +} + +/*! + * brief Initializes the FlexCAN handle. + * + * This function initializes the FlexCAN handle, which can be used for other FlexCAN + * transactional APIs. Usually, for a specified FlexCAN instance, + * call this API once to get the initialized handle. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param callback The callback function. + * param userData The parameter of the callback function. + */ +void FLEXCAN_TransferCreateHandle(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_transfer_callback_t callback, + void *userData) +{ + assert(NULL != handle); + + uint8_t instance; + + /* Clean FlexCAN transfer handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Get instance from peripheral base address. */ + instance = (uint8_t)FLEXCAN_GetInstance(base); + + /* Save the context in global variables to support the double weak mechanism. */ + s_flexcanHandle[instance] = handle; + + /* Register Callback function. */ + handle->callback = callback; + handle->userData = userData; + + s_flexcanIsr = FLEXCAN_TransferHandleIRQ; + + /* We Enable Error & Status interrupt here, because this interrupt just + * report current status of FlexCAN module through Callback function. + * It is insignificance without a available callback function. + */ + if (handle->callback != NULL) + { + FLEXCAN_EnableInterrupts( + base, (uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | + (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable | + (uint32_t)kFLEXCAN_WakeUpInterruptEnable); + } + else + { + FLEXCAN_DisableInterrupts( + base, (uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | + (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable | + (uint32_t)kFLEXCAN_WakeUpInterruptEnable); + } + + /* Enable interrupts in NVIC. */ + (void)EnableIRQ((IRQn_Type)(s_flexcanRxWarningIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanTxWarningIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanWakeUpIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanErrorIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanBusOffIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanMbIRQ[instance])); +} + +/*! + * brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success Start Tx Message Buffer sending process successfully. + * retval kStatus_Fail Write Tx Message Buffer failed. + * retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != xfer); + assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(false == FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) + { + /* Distinguish transmit type. */ + if ((uint32_t)kFLEXCAN_FrameTypeRemote == xfer->frame->type) + { + handle->mbState[xfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxRemote; + } + else + { + handle->mbState[xfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxData; + } + + /* Register user Frame buffer to the handle. */ + handle->mbFrameBuf[xfer->mbIdx] = xfer->frame; + + if (kStatus_Success == FLEXCAN_WriteTxMb(base, xfer->mbIdx, (const flexcan_frame_t *)(uint32_t)xfer->frame)) + { +/* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64mask = 1; + FLEXCAN_EnableMbInterrupts(base, u64mask << xfer->mbIdx); +#else + uint32_t u32mask = 1; + FLEXCAN_EnableMbInterrupts(base, u32mask << xfer->mbIdx); +#endif + + return kStatus_Success; + } + else + { + handle->mbState[xfer->mbIdx] = (uint8_t)kFLEXCAN_StateIdle; + return kStatus_Fail; + } + } + else + { + return kStatus_FLEXCAN_TxBusy; + } +} + +/*! + * brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != xfer); + assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(false == FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) + { + handle->mbState[xfer->mbIdx] = (uint8_t)kFLEXCAN_StateRxData; + + /* Register Message Buffer. */ + handle->mbFrameBuf[xfer->mbIdx] = xfer->frame; + +/* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64mask = 1; + FLEXCAN_EnableMbInterrupts(base, u64mask << xfer->mbIdx); +#else + uint32_t u32mask = 1; + FLEXCAN_EnableMbInterrupts(base, u32mask << xfer->mbIdx); +#endif + + return kStatus_Success; + } + else + { + return kStatus_FLEXCAN_RxBusy; + } +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param xfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success Start Tx Message Buffer sending process successfully. + * retval kStatus_Fail Write Tx Message Buffer failed. + * retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != xfer); + assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(false == FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) + { + /* Distinguish transmit type. */ + if ((uint32_t)kFLEXCAN_FrameTypeRemote == xfer->framefd->type) + { + handle->mbState[xfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxRemote; + } + else + { + handle->mbState[xfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxData; + } + + /* Register user Frame buffer to the handle. */ + handle->mbFDFrameBuf[xfer->mbIdx] = xfer->framefd; + + if (kStatus_Success == + FLEXCAN_WriteFDTxMb(base, xfer->mbIdx, (const flexcan_fd_frame_t *)(uint32_t)xfer->framefd)) + { +/* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64mask = 1; + FLEXCAN_EnableMbInterrupts(base, u64mask << xfer->mbIdx); +#else + uint32_t u32mask = 1; + FLEXCAN_EnableMbInterrupts(base, u32mask << xfer->mbIdx); +#endif + + return kStatus_Success; + } + else + { + handle->mbState[xfer->mbIdx] = (uint8_t)kFLEXCAN_StateIdle; + return kStatus_Fail; + } + } + else + { + return kStatus_FLEXCAN_TxBusy; + } +} + +/*! + * brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param xfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != xfer); + assert(xfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(false == FLEXCAN_IsMbOccupied(base, xfer->mbIdx)); + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[xfer->mbIdx]) + { + handle->mbState[xfer->mbIdx] = (uint8_t)kFLEXCAN_StateRxData; + + /* Register Message Buffer. */ + handle->mbFDFrameBuf[xfer->mbIdx] = xfer->framefd; + +/* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64mask = 1; + FLEXCAN_EnableMbInterrupts(base, u64mask << xfer->mbIdx); +#else + uint32_t u32mask = 1; + FLEXCAN_EnableMbInterrupts(base, u32mask << xfer->mbIdx); +#endif + + return kStatus_Success; + } + else + { + return kStatus_FLEXCAN_RxBusy; + } +} +#endif + +/*! + * brief Receives a message from Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param xfer FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t. + * retval kStatus_Success - Start Rx FIFO receiving process successfully. + * retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. + */ +status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_fifo_transfer_t *xfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != xfer); + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->rxFifoState) + { + handle->rxFifoState = (uint8_t)kFLEXCAN_StateRxFifo; + + /* Register Message Buffer. */ + handle->rxFifoFrameBuf = xfer->frame; + + /* Enable Message Buffer Interrupt. */ + FLEXCAN_EnableMbInterrupts(base, (uint32_t)kFLEXCAN_RxFifoOverflowFlag | (uint32_t)kFLEXCAN_RxFifoWarningFlag | + (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); + + return kStatus_Success; + } + else + { + return kStatus_FLEXCAN_RxFifoBusy; + } +} + +/*! + * brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(NULL != handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(NULL != handle->mbFrameBuf[mbIdx]); + assert(false == FLEXCAN_IsMbOccupied(base, mbIdx)); + +/* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64mask = 1; + FLEXCAN_DisableMbInterrupts(base, u64mask << mbIdx); +#else + uint32_t u32mask = 1; + FLEXCAN_DisableMbInterrupts(base, u32mask << mbIdx); +#endif + + /*Update the TX frame 's time stamp by MB[mbIdx].cs*/ + handle->mbFrameBuf[mbIdx]->timestamp = + (uint16_t)((base->MB[mbIdx].CS & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + /* Un-register handle. */ + handle->mbFrameBuf[mbIdx] = NULL; + + /* Clean Message Buffer. */ + FLEXCAN_SetTxMbConfig(base, mbIdx, true); + + handle->mbState[mbIdx] = (uint8_t)kFLEXCAN_StateIdle; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + */ +void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(NULL != handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(NULL != handle->mbFDFrameBuf[mbIdx]); + assert(false == FLEXCAN_IsMbOccupied(base, mbIdx)); + +/* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64mask = 1; + FLEXCAN_DisableMbInterrupts(base, u64mask << mbIdx); +#else + uint32_t u32mask = 1; + FLEXCAN_DisableMbInterrupts(base, u32mask << mbIdx); +#endif + + /*Update the TX frame 's time stamp by base->MB[offset for CANFD].CS*/ + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + handle->mbFDFrameBuf[mbIdx]->timestamp = + (uint16_t)((mbAddr[offset] & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + /* Un-register handle. */ + handle->mbFDFrameBuf[mbIdx] = NULL; + + /* Clean Message Buffer. */ + FLEXCAN_SetFDTxMbConfig(base, mbIdx, true); + + handle->mbState[mbIdx] = (uint8_t)kFLEXCAN_StateIdle; +} + +/*! + * brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + */ +void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(NULL != handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(false == FLEXCAN_IsMbOccupied(base, mbIdx)); + +/* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64mask = 1; + FLEXCAN_DisableMbInterrupts(base, u64mask << mbIdx); +#else + uint32_t u32mask = 1; + FLEXCAN_DisableMbInterrupts(base, u32mask << mbIdx); +#endif + + /* Un-register handle. */ + handle->mbFDFrameBuf[mbIdx] = NULL; + handle->mbState[mbIdx] = (uint8_t)kFLEXCAN_StateIdle; +} +#endif + +/*! + * brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(NULL != handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(false == FLEXCAN_IsMbOccupied(base, mbIdx)); + +/* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64mask = 1; + FLEXCAN_DisableMbInterrupts(base, (u64mask << mbIdx)); +#else + uint32_t u32mask = 1; + FLEXCAN_DisableMbInterrupts(base, (u32mask << mbIdx)); +#endif + + /* Un-register handle. */ + handle->mbFrameBuf[mbIdx] = NULL; + handle->mbState[mbIdx] = (uint8_t)kFLEXCAN_StateIdle; +} + +/*! + * brief Aborts the interrupt driven message receive from Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Rx FIFO process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle) +{ + /* Assertion. */ + assert(NULL != handle); + + /* Check if Rx FIFO is enabled. */ + if (0U != (base->MCR & CAN_MCR_RFEN_MASK)) + { + /* Disable Rx Message FIFO Interrupts. */ + FLEXCAN_DisableMbInterrupts(base, (uint32_t)kFLEXCAN_RxFifoOverflowFlag | (uint32_t)kFLEXCAN_RxFifoWarningFlag | + (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); + + /* Un-register handle. */ + handle->rxFifoFrameBuf = NULL; + } + + handle->rxFifoState = (uint8_t)kFLEXCAN_StateIdle; +} + +/*! + * brief FlexCAN IRQ handle function. + * + * This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) +{ + /* Assertion. */ + assert(NULL != handle); + + status_t status = kStatus_FLEXCAN_UnHandled; + uint32_t result = 0U; + /* Store Current FlexCAN Module Error and Status. */ + uint32_t EsrStatus = base->ESR1; + + do + { + /* Solve FlexCAN Error and Status Interrupt. */ + if (0U != (EsrStatus & ((uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag | + (uint32_t)kFLEXCAN_BusOffIntFlag | (uint32_t)kFLEXCAN_ErrorIntFlag))) + { + status = kStatus_FLEXCAN_ErrorStatus; + + /* Clear FlexCAN Error and Status Interrupt. */ + FLEXCAN_ClearStatusFlags(base, (uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag | + (uint32_t)kFLEXCAN_BusOffIntFlag | (uint32_t)kFLEXCAN_ErrorIntFlag); + } + else if (0U != (EsrStatus & (uint32_t)kFLEXCAN_WakeUpIntFlag)) + { + status = kStatus_FLEXCAN_WakeUp; + FLEXCAN_ClearStatusFlags(base, (uint32_t)kFLEXCAN_WakeUpIntFlag); + } + /* Solve FlexCAN Rx FIFO & Message Buffer Interrupt. */ + else + { + /* For this implementation, we solve the Message with lowest MB index first. */ + for (result = 0U; result < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); result++) + { +/* Get the lowest unhandled Message Buffer */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64flag = 1; + if (0U != FLEXCAN_GetMbStatusFlags(base, (u64flag << result))) + { + if (true == FLEXCAN_IsMbIntEnabled(base, result)) +#else + uint32_t u32flag = 1; + if (0U != FLEXCAN_GetMbStatusFlags(base, (u32flag << result))) + { + if (true == FLEXCAN_IsMbIntEnabled(base, (uint8_t)result)) +#endif + { + break; + } + } + } + + /* Does not find Message to deal with. */ + if (result == (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) + { + break; + } + + /* Solve Rx FIFO interrupt. */ + if (((uint8_t)kFLEXCAN_StateIdle != handle->rxFifoState) && (result <= (uint32_t)CAN_IFLAG1_BUF7I_SHIFT)) + { + uint32_t u32mask = 1; + switch (u32mask << result) + { + case (int32_t)kFLEXCAN_RxFifoOverflowFlag: + status = kStatus_FLEXCAN_RxFifoOverflow; + break; + + case (int32_t)kFLEXCAN_RxFifoWarningFlag: + status = kStatus_FLEXCAN_RxFifoWarning; + break; + + case (int32_t)kFLEXCAN_RxFifoFrameAvlFlag: + status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); + if (kStatus_Success == status) + { + status = kStatus_FLEXCAN_RxFifoIdle; + } + FLEXCAN_TransferAbortReceiveFifo(base, handle); + break; + + default: + status = kStatus_FLEXCAN_UnHandled; + break; + } + } + else + { + /* Get current State of Message Buffer. */ + switch (handle->mbState[result]) + { + /* Solve Rx Data Frame or Rx Remote Frame. */ + case (uint8_t)kFLEXCAN_StateRxData: + case (uint8_t)kFLEXCAN_StateRxRemote: +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) + { + status = FLEXCAN_ReadFDRxMb(base, (uint8_t)result, handle->mbFDFrameBuf[result]); + } + else + { + status = FLEXCAN_ReadRxMb(base, (uint8_t)result, handle->mbFrameBuf[result]); + } +#else + status = FLEXCAN_ReadRxMb(base, result, handle->mbFrameBuf[result]); +#endif + if (kStatus_Success == status) + { + status = kStatus_FLEXCAN_RxIdle; + } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) + { + FLEXCAN_TransferFDAbortReceive(base, handle, (uint8_t)result); + } + else + { + FLEXCAN_TransferAbortReceive(base, handle, (uint8_t)result); + } +#else + FLEXCAN_TransferAbortReceive(base, handle, result); +#endif + break; + + /* Solve Tx Data Frame. */ + case (uint8_t)kFLEXCAN_StateTxData: + status = kStatus_FLEXCAN_TxIdle; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) + { + FLEXCAN_TransferFDAbortSend(base, handle, (uint8_t)result); + } + else + { + FLEXCAN_TransferAbortSend(base, handle, (uint8_t)result); + } +#else + FLEXCAN_TransferAbortSend(base, handle, result); +#endif + break; + + /* Solve Tx Remote Frame. */ + case (uint8_t)kFLEXCAN_StateTxRemote: + handle->mbState[result] = (uint8_t)kFLEXCAN_StateRxRemote; + status = kStatus_FLEXCAN_TxSwitchToRx; + break; + + default: + status = kStatus_FLEXCAN_UnHandled; + break; + } + } + +/* Clear resolved Message Buffer IRQ. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64flag = 1; + FLEXCAN_ClearMbStatusFlags(base, u64flag << result); +#else + uint32_t u32flag = 1; + FLEXCAN_ClearMbStatusFlags(base, u32flag << result); +#endif + } + + /* Calling Callback Function if has one. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, status, result, handle->userData); + } + + /* Reset return status */ + status = kStatus_FLEXCAN_UnHandled; + + /* Store Current FlexCAN Module Error and Status. */ + EsrStatus = base->ESR1; + } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + while ((0U != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFFFFFFFFFU)) || + (0U != (EsrStatus & ((uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag | + (uint32_t)kFLEXCAN_BusOffIntFlag | (uint32_t)kFLEXCAN_ErrorIntFlag | + (uint32_t)kFLEXCAN_WakeUpIntFlag)))); +#else + while ((0U != FLEXCAN_GetMbStatusFlags(base, 0xFFFFFFFFU)) || + (0U != (EsrStatus & ((uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag | + (uint32_t)kFLEXCAN_BusOffIntFlag | (uint32_t)kFLEXCAN_ErrorIntFlag | + (uint32_t)kFLEXCAN_WakeUpIntFlag)))); +#endif +} + +#if defined(CAN0) +void CAN0_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[0]); + + s_flexcanIsr(CAN0, s_flexcanHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CAN1) +void CAN1_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[1]); + + s_flexcanIsr(CAN1, s_flexcanHandle[1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CAN2) +void CAN2_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[2]); + + s_flexcanIsr(CAN2, s_flexcanHandle[2]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CAN3) +void CAN3_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[3]); + + s_flexcanIsr(CAN3, s_flexcanHandle[3]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CAN4) +void CAN4_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[4]); + + s_flexcanIsr(CAN4, s_flexcanHandle[4]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(DMA__CAN0) +void DMA_FLEXCAN0_INT_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]); + + s_flexcanIsr(DMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(DMA__CAN1) +void DMA_FLEXCAN1_INT_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]); + + s_flexcanIsr(DMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(DMA__CAN2) +void DMA_FLEXCAN2_INT_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]); + + s_flexcanIsr(DMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__CAN0) +void ADMA_FLEXCAN0_INT_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); + + s_flexcanIsr(ADMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__CAN1) +void ADMA_FLEXCAN1_INT_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); + + s_flexcanIsr(ADMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__CAN2) +void ADMA_FLEXCAN2_INT_DriverIRQHandler(void) +{ + assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); + + s_flexcanIsr(ADMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexcan.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexcan.h new file mode 100644 index 0000000000..9fe1b43996 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexcan.h @@ -0,0 +1,1368 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_FLEXCAN_H_ +#define _FSL_FLEXCAN_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexcan_driver + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexCAN driver version 2.4.0. */ +#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) +/*@}*/ + +#if !(defined(FLEXCAN_WAIT_TIMEOUT) && FLEXCAN_WAIT_TIMEOUT) +/* Define to 1000 means keep waiting 1000 times until the flag is assert/deassert. */ +#define FLEXCAN_WAIT_TIMEOUT (1000U) +#endif + +/*! @brief FlexCAN Frame ID helper macro. */ +#define FLEXCAN_ID_STD(id) \ + (((uint32_t)(((uint32_t)(id)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) /*!< Standard Frame ID helper macro. */ +#define FLEXCAN_ID_EXT(id) \ + (((uint32_t)(((uint32_t)(id)) << CAN_ID_EXT_SHIFT)) & \ + (CAN_ID_EXT_MASK | CAN_ID_STD_MASK)) /*!< Extend Frame ID helper macro. */ + +/*! @brief FlexCAN Rx Message Buffer Mask helper macro. */ +#define FLEXCAN_RX_MB_STD_MASK(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + FLEXCAN_ID_STD(id)) /*!< Standard Rx Message Buffer Mask helper macro. */ +#define FLEXCAN_RX_MB_EXT_MASK(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + FLEXCAN_ID_EXT(id)) /*!< Extend Rx Message Buffer Mask helper macro. */ + +/*! @brief FlexCAN Rx FIFO Mask helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (FLEXCAN_ID_STD(id) << 1)) /*!< Standard Rx FIFO Mask helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (((uint32_t)(id)&0x7FF) << 19)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ + (((uint32_t)(id)&0x7FF) << 3)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id) \ + (((uint32_t)(id)&0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id) \ + (((uint32_t)(id)&0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id) \ + (((uint32_t)(id)&0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) \ + (((uint32_t)(id)&0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \ + ( \ + ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) \ + << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \ + 15)) /*!< Extend Rx FIFO Mask helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) << 3) /*!< Extend Rx FIFO Mask helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \ + 5) /*!< Extend Rx FIFO Mask helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \ + 13) /*!< Extend Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> 21) /*!< Extend Rx FIFO Mask helper macro Type C lower part helper macro. */ + +/*! @brief FlexCAN Rx FIFO Filter helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_HIGH(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH( \ + id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_LOW(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW( \ + id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_HIGH(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_HIGH(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH( \ + id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW( \ + id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_LOW(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_LOW(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) /*!< Extend Rx FIFO Filter helper macro Type C lower part helper macro. */ + +/*! @brief FlexCAN transfer status. */ +enum _flexcan_status +{ + kStatus_FLEXCAN_TxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 0), /*!< Tx Message Buffer is Busy. */ + kStatus_FLEXCAN_TxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 1), /*!< Tx Message Buffer is Idle. */ + kStatus_FLEXCAN_TxSwitchToRx = MAKE_STATUS( + kStatusGroup_FLEXCAN, 2), /*!< Remote Message is send out and Message buffer changed to Receive one. */ + kStatus_FLEXCAN_RxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 3), /*!< Rx Message Buffer is Busy. */ + kStatus_FLEXCAN_RxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 4), /*!< Rx Message Buffer is Idle. */ + kStatus_FLEXCAN_RxOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 5), /*!< Rx Message Buffer is Overflowed. */ + kStatus_FLEXCAN_RxFifoBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 6), /*!< Rx Message FIFO is Busy. */ + kStatus_FLEXCAN_RxFifoIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 7), /*!< Rx Message FIFO is Idle. */ + kStatus_FLEXCAN_RxFifoOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 8), /*!< Rx Message FIFO is overflowed. */ + kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 9), /*!< Rx Message FIFO is almost overflowed. */ + kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 10), /*!< FlexCAN Module Error and Status. */ + kStatus_FLEXCAN_WakeUp = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< FlexCAN is waken up from STOP mode. */ + kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 12), /*!< UnHadled Interrupt asserted. */ +}; + +/*! @brief FlexCAN frame format. */ +typedef enum _flexcan_frame_format +{ + kFLEXCAN_FrameFormatStandard = 0x0U, /*!< Standard frame format attribute. */ + kFLEXCAN_FrameFormatExtend = 0x1U, /*!< Extend frame format attribute. */ +} flexcan_frame_format_t; + +/*! @brief FlexCAN frame type. */ +typedef enum _flexcan_frame_type +{ + kFLEXCAN_FrameTypeData = 0x0U, /*!< Data frame type attribute. */ + kFLEXCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */ +} flexcan_frame_type_t; + +/*! @brief FlexCAN clock source. */ +typedef enum _flexcan_clock_source +{ + kFLEXCAN_ClkSrcOsc = 0x0U, /*!< FlexCAN Protocol Engine clock from Oscillator. */ + kFLEXCAN_ClkSrcPeri = 0x1U, /*!< FlexCAN Protocol Engine clock from Peripheral Clock. */ +} flexcan_clock_source_t; + +/*! @brief FlexCAN wake up source. */ +typedef enum _flexcan_wake_up_source +{ + kFLEXCAN_WakeupSrcUnfiltered = 0x0U, /*!< FlexCAN uses unfiltered Rx input to detect edge. */ + kFLEXCAN_WakeupSrcFiltered = 0x1U, /*!< FlexCAN uses filtered Rx input to detect edge. */ +} flexcan_wake_up_source_t; + +/*! @brief FlexCAN Rx Fifo Filter type. */ +typedef enum _flexcan_rx_fifo_filter_type +{ + kFLEXCAN_RxFifoFilterTypeA = 0x0U, /*!< One full ID (standard and extended) per ID Filter element. */ + kFLEXCAN_RxFifoFilterTypeB = + 0x1U, /*!< Two full standard IDs or two partial 14-bit ID slices per ID Filter Table element. */ + kFLEXCAN_RxFifoFilterTypeC = + 0x2U, /*!< Four partial 8-bit Standard or extended ID slices per ID Filter Table element. */ + kFLEXCAN_RxFifoFilterTypeD = 0x3U, /*!< All frames rejected. */ +} flexcan_rx_fifo_filter_type_t; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief FlexCAN Message Buffer Data Size. + */ +typedef enum _flexcan_mb_size +{ + kFLEXCAN_8BperMB = 0x0U, /*!< Selects 8 bytes per Message Buffer. */ + kFLEXCAN_16BperMB = 0x1U, /*!< Selects 16 bytes per Message Buffer. */ + kFLEXCAN_32BperMB = 0x2U, /*!< Selects 32 bytes per Message Buffer. */ + kFLEXCAN_64BperMB = 0x3U, /*!< Selects 64 bytes per Message Buffer. */ +} flexcan_mb_size_t; +#endif + +/*! + * @brief FlexCAN Rx FIFO priority. + * + * The matching process starts from the Rx MB(or Rx FIFO) with higher priority. + * If no MB(or Rx FIFO filter) is satisfied, the matching process goes on with + * the Rx FIFO(or Rx MB) with lower priority. + */ +typedef enum _flexcan_rx_fifo_priority +{ + kFLEXCAN_RxFifoPrioLow = 0x0U, /*!< Matching process start from Rx Message Buffer first*/ + kFLEXCAN_RxFifoPrioHigh = 0x1U, /*!< Matching process start from Rx FIFO first*/ +} flexcan_rx_fifo_priority_t; + +/*! + * @brief FlexCAN interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the FlexCAN Module interrupt configurations. + * Note: FlexCAN Message Buffers and Rx FIFO have their own interrupts. + */ +enum _flexcan_interrupt_enable +{ + kFLEXCAN_BusOffInterruptEnable = CAN_CTRL1_BOFFMSK_MASK, /*!< Bus Off interrupt. */ + kFLEXCAN_ErrorInterruptEnable = CAN_CTRL1_ERRMSK_MASK, /*!< Error interrupt. */ + kFLEXCAN_RxWarningInterruptEnable = CAN_CTRL1_RWRNMSK_MASK, /*!< Rx Warning interrupt. */ + kFLEXCAN_TxWarningInterruptEnable = CAN_CTRL1_TWRNMSK_MASK, /*!< Tx Warning interrupt. */ + kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK, /*!< Wake Up interrupt. */ +}; + +/*! + * @brief FlexCAN status flags. + * + * This provides constants for the FlexCAN status flags for use in the FlexCAN functions. + * Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to + * read FlEXCAN_ErrorFlag and distinguish which error is occur using + * @ref _flexcan_error_flags enumerations. + */ +enum _flexcan_flags +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + kFLEXCAN_FDErrorIntFlag = CAN_ESR1_ERRINT_FAST_MASK, /*!< Error Overrun Status. */ + kFLEXCAN_BusoffDoneIntFlag = CAN_ESR1_BOFFDONEINT_MASK, /*!< Error Overrun Status. */ +#endif + kFLEXCAN_SynchFlag = CAN_ESR1_SYNCH_MASK, /*!< CAN Synchronization Status. */ + kFLEXCAN_TxWarningIntFlag = CAN_ESR1_TWRNINT_MASK, /*!< Tx Warning Interrupt Flag. */ + kFLEXCAN_RxWarningIntFlag = CAN_ESR1_RWRNINT_MASK, /*!< Rx Warning Interrupt Flag. */ + kFLEXCAN_TxErrorWarningFlag = CAN_ESR1_TXWRN_MASK, /*!< Tx Error Warning Status. */ + kFLEXCAN_RxErrorWarningFlag = CAN_ESR1_RXWRN_MASK, /*!< Rx Error Warning Status. */ + kFLEXCAN_IdleFlag = CAN_ESR1_IDLE_MASK, /*!< CAN IDLE Status Flag. */ + kFLEXCAN_FaultConfinementFlag = CAN_ESR1_FLTCONF_MASK, /*!< Fault Confinement State Flag. */ + kFLEXCAN_TransmittingFlag = CAN_ESR1_TX_MASK, /*!< FlexCAN In Transmission Status. */ + kFLEXCAN_ReceivingFlag = CAN_ESR1_RX_MASK, /*!< FlexCAN In Reception Status. */ + kFLEXCAN_BusOffIntFlag = CAN_ESR1_BOFFINT_MASK, /*!< Bus Off Interrupt Flag. */ + kFLEXCAN_ErrorIntFlag = CAN_ESR1_ERRINT_MASK, /*!< Error Interrupt Flag. */ + kFLEXCAN_WakeUpIntFlag = CAN_ESR1_WAKINT_MASK, /*!< Wake-Up Interrupt Flag. */ + kFLEXCAN_ErrorFlag = (int)( /*!< All FlexCAN Error Status. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + CAN_ESR1_STFERR_FAST_MASK | CAN_ESR1_FRMERR_FAST_MASK | CAN_ESR1_CRCERR_FAST_MASK | + CAN_ESR1_BIT0ERR_FAST_MASK | CAN_ESR1_BIT1ERR_FAST_MASK | CAN_ESR1_ERROVR_MASK | +#endif + CAN_ESR1_BIT1ERR_MASK | CAN_ESR1_BIT0ERR_MASK | CAN_ESR1_ACKERR_MASK | + CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK | CAN_ESR1_STFERR_MASK), +}; + +/*! + * @brief FlexCAN error status flags. + * + * The FlexCAN Error Status enumerations is used to report current error of the FlexCAN bus. + * This enumerations should be used with KFLEXCAN_ErrorFlag in @ref _flexcan_flags enumerations + * to ditermine which error is generated. + */ +enum _flexcan_error_flags +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + kFLEXCAN_FDStuffingError = CAN_ESR1_STFERR_FAST_MASK, /*!< Stuffing Error. */ + kFLEXCAN_FDFormError = CAN_ESR1_FRMERR_FAST_MASK, /*!< Form Error. */ + kFLEXCAN_FDCrcError = CAN_ESR1_CRCERR_FAST_MASK, /*!< Cyclic Redundancy Check Error. */ + kFLEXCAN_FDBit0Error = CAN_ESR1_BIT0ERR_FAST_MASK, /*!< Unable to send dominant bit. */ + kFLEXCAN_FDBit1Error = (int)CAN_ESR1_BIT1ERR_FAST_MASK, /*!< Unable to send recessive bit. */ + kFLEXCAN_OverrunError = CAN_ESR1_ERROVR_MASK, /*!< Error Overrun Status. */ +#endif + kFLEXCAN_StuffingError = CAN_ESR1_STFERR_MASK, /*!< Stuffing Error. */ + kFLEXCAN_FormError = CAN_ESR1_FRMERR_MASK, /*!< Form Error. */ + kFLEXCAN_CrcError = CAN_ESR1_CRCERR_MASK, /*!< Cyclic Redundancy Check Error. */ + kFLEXCAN_AckError = CAN_ESR1_ACKERR_MASK, /*!< Received no ACK on transmission. */ + kFLEXCAN_Bit0Error = CAN_ESR1_BIT0ERR_MASK, /*!< Unable to send dominant bit. */ + kFLEXCAN_Bit1Error = CAN_ESR1_BIT1ERR_MASK, /*!< Unable to send recessive bit. */ +}; + +/*! + * @brief FlexCAN Rx FIFO status flags. + * + * The FlexCAN Rx FIFO Status enumerations are used to determine the status of the + * Rx FIFO. Because Rx FIFO occupy the MB0 ~ MB7 (Rx Fifo filter also occupies + * more Message Buffer space), Rx FIFO status flags are mapped to the corresponding + * Message Buffer status flags. + */ +enum _flexcan_rx_fifo_flags +{ + kFLEXCAN_RxFifoOverflowFlag = CAN_IFLAG1_BUF7I_MASK, /*!< Rx FIFO overflow flag. */ + kFLEXCAN_RxFifoWarningFlag = CAN_IFLAG1_BUF6I_MASK, /*!< Rx FIFO almost full flag. */ + kFLEXCAN_RxFifoFrameAvlFlag = CAN_IFLAG1_BUF5I_MASK, /*!< Frames available in Rx FIFO flag. */ +}; + +#if defined(__CC_ARM) +#pragma anon_unions +#endif +/*! @brief FlexCAN message frame structure. */ +typedef struct _flexcan_frame +{ + struct + { + uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ + uint32_t length : 4; /*!< CAN frame payload length in bytes(Range: 0~8). */ + uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ + uint32_t : 1; /*!< Reserved. */ + uint32_t idhit : 9; /*!< CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode). */ + }; + struct + { + uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ + uint32_t : 3; /*!< Reserved. */ + }; + union + { + struct + { + uint32_t dataWord0; /*!< CAN Frame payload word0. */ + uint32_t dataWord1; /*!< CAN Frame payload word1. */ + }; + struct + { + uint8_t dataByte3; /*!< CAN Frame payload byte3. */ + uint8_t dataByte2; /*!< CAN Frame payload byte2. */ + uint8_t dataByte1; /*!< CAN Frame payload byte1. */ + uint8_t dataByte0; /*!< CAN Frame payload byte0. */ + uint8_t dataByte7; /*!< CAN Frame payload byte7. */ + uint8_t dataByte6; /*!< CAN Frame payload byte6. */ + uint8_t dataByte5; /*!< CAN Frame payload byte5. */ + uint8_t dataByte4; /*!< CAN Frame payload byte4. */ + }; + }; +} flexcan_frame_t; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! @brief CAN FDmessage frame structure. */ +typedef struct _flexcan_fd_frame +{ + struct + { + uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ + uint32_t length : 4; /*!< CAN frame payload length in bytes(Range: 0~8). */ + uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ + uint32_t srr : 1; /*!< Substitute Remote request. */ + uint32_t : 1; + uint32_t code : 4; /*!< Message Buffer Code. */ + uint32_t : 1; + uint32_t esi : 1; /*!< Error State Indicator. */ + uint32_t brs : 1; /*!< Bit Rate Switch. */ + uint32_t edl : 1; /*!< Extended Data Length. */ + }; + struct + { + uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ + uint32_t : 3; /*!< Reserved. */ + }; + union + { + struct + { + uint32_t dataWord[16]; /*!< CAN FD Frame payload, 16 double word maximum. */ + }; + /* Note: the maximum databyte* below is actually 64, user can add them if needed, + or just use dataWord[*] instead. */ + struct + { + uint8_t dataByte3; /*!< CAN Frame payload byte3. */ + uint8_t dataByte2; /*!< CAN Frame payload byte2. */ + uint8_t dataByte1; /*!< CAN Frame payload byte1. */ + uint8_t dataByte0; /*!< CAN Frame payload byte0. */ + uint8_t dataByte7; /*!< CAN Frame payload byte7. */ + uint8_t dataByte6; /*!< CAN Frame payload byte6. */ + uint8_t dataByte5; /*!< CAN Frame payload byte5. */ + uint8_t dataByte4; /*!< CAN Frame payload byte4. */ + }; + }; +} flexcan_fd_frame_t; +#endif + +/*! @brief FlexCAN protocol timing characteristic configuration structure. */ +typedef struct _flexcan_timing_config +{ + uint16_t preDivider; /*!< Clock Pre-scaler Division Factor. */ + uint8_t rJumpwidth; /*!< Re-sync Jump Width. */ + uint8_t phaseSeg1; /*!< Phase Segment 1. */ + uint8_t phaseSeg2; /*!< Phase Segment 2. */ + uint8_t propSeg; /*!< Propagation Segment. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + uint16_t fpreDivider; /*!< Fast Clock Pre-scaler Division Factor. */ + uint8_t frJumpwidth; /*!< Fast Re-sync Jump Width. */ + uint8_t fphaseSeg1; /*!< Fast Phase Segment 1. */ + uint8_t fphaseSeg2; /*!< Fast Phase Segment 2. */ + uint8_t fpropSeg; /*!< Fast Propagation Segment. */ +#endif +} flexcan_timing_config_t; + +/*! @brief FlexCAN module configuration structure. */ +typedef struct _flexcan_config +{ + uint32_t baudRate; /*!< FlexCAN baud rate in bps. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + uint32_t baudRateFD; /*!< FlexCAN FD baud rate in bps. */ +#endif + flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */ + flexcan_wake_up_source_t wakeupSrc; /*!< Wake up source selection. */ + uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */ + bool enableLoopBack; /*!< Enable or Disable Loop Back Self Test Mode. */ + bool enableTimerSync; /*!< Enable or Disable Timer Synchronization. */ + bool enableSelfWakeup; /*!< Enable or Disable Self Wakeup Mode. */ + bool enableIndividMask; /*!< Enable or Disable Rx Individual Mask. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + bool enableDoze; /*!< Enable or Disable Doze Mode. */ +#endif + flexcan_timing_config_t timingConfig; /* Protocol timing . */ +} flexcan_config_t; + +/*! + * @brief FlexCAN Receive Message Buffer configuration structure + * + * This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function. + * The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive + * Message Buffer. The function abort previous receiving process, clean the + * Message Buffer and activate the Rx Message Buffer using given Message Buffer + * setting. + */ +typedef struct _flexcan_rx_mb_config +{ + uint32_t id; /*!< CAN Message Buffer Frame Identifier, should be set using + FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ + flexcan_frame_format_t format; /*!< CAN Frame Identifier format(Standard of Extend). */ + flexcan_frame_type_t type; /*!< CAN Frame Type(Data or Remote). */ +} flexcan_rx_mb_config_t; + +/*! @brief FlexCAN Rx FIFO configuration structure. */ +typedef struct _flexcan_rx_fifo_config +{ + uint32_t *idFilterTable; /*!< Pointer to the FlexCAN Rx FIFO identifier filter table. */ + uint8_t idFilterNum; /*!< The quantity of filter elements. */ + flexcan_rx_fifo_filter_type_t idFilterType; /*!< The FlexCAN Rx FIFO Filter type. */ + flexcan_rx_fifo_priority_t priority; /*!< The FlexCAN Rx FIFO receive priority. */ +} flexcan_rx_fifo_config_t; + +/*! @brief FlexCAN Message Buffer transfer. */ +typedef struct _flexcan_mb_transfer +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + flexcan_fd_frame_t *framefd; +#endif + flexcan_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */ + uint8_t mbIdx; /*!< The index of Message buffer used to transfer Message. */ +} flexcan_mb_transfer_t; + +/*! @brief FlexCAN Rx FIFO transfer. */ +typedef struct _flexcan_fifo_transfer +{ + flexcan_frame_t *frame; /*!< The buffer of CAN Message to be received from Rx FIFO. */ +} flexcan_fifo_transfer_t; + +/*! @brief FlexCAN handle structure definition. */ +typedef struct _flexcan_handle flexcan_handle_t; + +/*! @brief FlexCAN transfer callback function. + * + * The FlexCAN transfer callback returns a value from the underlying layer. + * If the status equals to kStatus_FLEXCAN_ErrorStatus, the result parameter is the Content of + * FlexCAN status register which can be used to get the working status(or error status) of FlexCAN module. + * If the status equals to other FlexCAN Message Buffer transfer status, the result is the index of + * Message Buffer that generate transfer event. + * If the status equals to other FlexCAN Message Buffer transfer status, the result is meaningless and should be + * Ignored. + */ +typedef void (*flexcan_transfer_callback_t)( + CAN_Type *base, flexcan_handle_t *handle, status_t status, uint32_t result, void *userData); + +/*! @brief FlexCAN handle structure. */ +struct _flexcan_handle +{ + flexcan_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< FlexCAN callback function parameter.*/ + flexcan_frame_t *volatile mbFrameBuf[CAN_WORD1_COUNT]; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + flexcan_fd_frame_t *volatile mbFDFrameBuf[CAN_WORD1_COUNT]; +#endif + /*!< The buffer for received data from Message Buffers. */ + flexcan_frame_t *volatile rxFifoFrameBuf; /*!< The buffer for received data from Rx FIFO. */ + volatile uint8_t mbState[CAN_WORD1_COUNT]; /*!< Message Buffer transfer state. */ + volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */ +}; + +/****************************************************************************** + * API + *****************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Get the FlexCAN instance from peripheral base address. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN instance. + */ +uint32_t FLEXCAN_GetInstance(CAN_Type *base); +/*! + * @brief Calculates the improved timing values by specific baudrates for classical CAN + * + * @param baudRate The classical CAN speed in bps defined by user + * @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching + * @param pconfig Pointer to the FlexCAN timing configuration structure. + * + * @return TRUE if timing configuration found, FALSE if failed to find configuration + */ +bool FLEXCAN_CalculateImprovedTimingValues(uint32_t baudRate, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pconfig); + +/*! + * @brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_Init function by passing in these parameters. + * @code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc; + * flexcanConfig.baudRate = 1000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_Init(CAN0, &flexcanConfig, 8000000UL); + * @endcode + * + * @param base FlexCAN peripheral base address. + * @param config Pointer to the user-defined configuration structure. + * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + */ +void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Calculates the improved timing values by specific baudrates for CANFD + * + * @param baudRate The CANFD bus control speed in bps defined by user + * @param baudRateFD The CANFD bus data speed in bps defined by user + * @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching + * @param pconfig Pointer to the FlexCAN timing configuration structure. + * + * @return TRUE if timing configuration found, FALSE if failed to find configuration + */ +bool FLEXCAN_FDCalculateImprovedTimingValues(uint32_t baudRate, + uint32_t baudRateFD, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pconfig); +/*! + * @brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_FDInit function by passing in these parameters. + * @code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc; + * flexcanConfig.baudRate = 1000000U; + * flexcanConfig.baudRateFD = 2000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_FDInit(CAN0, &flexcanConfig, 8000000UL, kFLEXCAN_16BperMB, false); + * @endcode + * + * @param base FlexCAN peripheral base address. + * @param config Pointer to the user-defined configuration structure. + * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + * @param dataSize FlexCAN FD frame payload size. + * @param brs If bitrate switch is enabled in FD mode. + */ +void FLEXCAN_FDInit( + CAN_Type *base, const flexcan_config_t *config, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs); +#endif + +/*! + * @brief De-initializes a FlexCAN instance. + * + * This function disables the FlexCAN module clock and sets all register values + * to the reset value. + * + * @param base FlexCAN peripheral base address. + */ +void FLEXCAN_Deinit(CAN_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the FlexCAN configuration structure to default values. The default + * values are as follows. + * flexcanConfig->clkSrc = kFLEXCAN_ClkSrcOsc; + * flexcanConfig->baudRate = 1000000U; + * flexcanConfig->baudRateFD = 2000000U; + * flexcanConfig->maxMbNum = 16; + * flexcanConfig->enableLoopBack = false; + * flexcanConfig->enableSelfWakeup = false; + * flexcanConfig->enableIndividMask = false; + * flexcanConfig->enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * + * @param config Pointer to the FlexCAN configuration structure. + */ +void FLEXCAN_GetDefaultConfig(flexcan_config_t *config); + +/* @} */ + +/*! + * @name Configuration. + * @{ + */ + +/*! + * @brief Sets the FlexCAN protocol timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the FLEXCAN_Init() and fill the baud rate field with a desired value. + * This provides the default timing characteristics to the module. + * + * Note that calling FLEXCAN_SetTimingConfig() overrides the baud rate set + * in FLEXCAN_Init(). + * + * @param base FlexCAN peripheral base address. + * @param config Pointer to the timing configuration structure. + */ +void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Sets the FlexCAN FD protocol timing characteristic. + * + * This function gives user settings to CAN bus timing characteristic. + * The function is for an experienced user. For less experienced users, call + * the FLEXCAN_Init() and fill the baud rate field with a desired value. + * This provides the default timing characteristics to the module. + * + * Note that calling FLEXCAN_SetFDTimingConfig() overrides the baud rate set + * in FLEXCAN_Init(). + * + * @param base FlexCAN peripheral base address. + * @param config Pointer to the timing configuration structure. + */ +void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *config); +#endif + +/*! + * @brief Sets the FlexCAN receive message buffer global mask. + * + * This function sets the global mask for the FlexCAN message buffer in a matching process. + * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init(). + * + * @param base FlexCAN peripheral base address. + * @param mask Rx Message Buffer Global Mask value. + */ +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); + +/*! + * @brief Sets the FlexCAN receive FIFO global mask. + * + * This function sets the global mask for FlexCAN FIFO in a matching process. + * + * @param base FlexCAN peripheral base address. + * @param mask Rx Fifo Global Mask value. + */ +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); + +/*! + * @brief Sets the FlexCAN receive individual mask. + * + * This function sets the individual mask for the FlexCAN matching process. + * The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). + * If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. + * If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to + * the Rx Filter with the same index. Note that only the first 32 + * individual masks can be used as the Rx FIFO filter mask. + * + * @param base FlexCAN peripheral base address. + * @param maskIdx The Index of individual Mask. + * @param mask Rx Individual Mask value. + */ +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask); + +/*! + * @brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable); +#endif + +/*! + * @brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param config Pointer to the FlexCAN Message Buffer configuration structure. + * @param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param config Pointer to the FlexCAN Message Buffer configuration structure. + * @param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *config, bool enable); +#endif + +/*! + * @brief Configures the FlexCAN Rx FIFO. + * + * This function configures the Rx FIFO with given Rx FIFO configuration. + * + * @param base FlexCAN peripheral base address. + * @param config Pointer to the FlexCAN Rx FIFO configuration structure. + * @param enable Enable/disable Rx FIFO. + * - true: Enable Rx FIFO. + * - false: Disable Rx FIFO. + */ +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *config, bool enable); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexCAN module interrupt flags. + * + * This function gets all FlexCAN status flags. The flags are returned as the logical + * OR value of the enumerators @ref _flexcan_flags. To check the specific status, + * compare the return value with enumerators in @ref _flexcan_flags. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN status flags which are ORed by the enumerators in the _flexcan_flags. + */ +static inline uint32_t FLEXCAN_GetStatusFlags(CAN_Type *base) +{ + return base->ESR1; +} + +/*! + * @brief Clears status flags with the provided mask. + * + * This function clears the FlexCAN status flags with a provided mask. An automatically cleared flag + * can't be cleared by this function. + * + * @param base FlexCAN peripheral base address. + * @param mask The status flags to be cleared, it is logical OR value of @ref _flexcan_flags. + */ +static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask) +{ + /* Write 1 to clear status flag. */ + base->ESR1 = mask; +} + +/*! + * @brief Gets the FlexCAN Bus Error Counter value. + * + * This function gets the FlexCAN Bus Error Counter value for both Tx and + * Rx direction. These values may be needed in the upper layer error handling. + * + * @param base FlexCAN peripheral base address. + * @param txErrBuf Buffer to store Tx Error Counter value. + * @param rxErrBuf Buffer to store Rx Error Counter value. + */ +static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf) +{ + if (NULL != txErrBuf) + { + *txErrBuf = (uint8_t)((base->ECR & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT); + } + + if (NULL != rxErrBuf) + { + *rxErrBuf = (uint8_t)((base->ECR & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT); + } +} + +/*! + * @brief Gets the FlexCAN Message Buffer interrupt flags. + * + * This function gets the interrupt flags of a given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + * @return The status of given Message Buffers. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline uint64_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint64_t mask) +#else +static inline uint32_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + return ((((uint64_t)base->IFLAG1) & mask) | ((((uint64_t)base->IFLAG2) << 32) & mask)); +#else + return (base->IFLAG1 & mask); +#endif +} + +/*! + * @brief Clears the FlexCAN Message Buffer interrupt flags. + * + * This function clears the interrupt flags of a given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IFLAG1 = (uint32_t)(mask & 0xFFFFFFFFU); + base->IFLAG2 = (uint32_t)(mask >> 32); +#else + base->IFLAG1 = mask; +#endif +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables FlexCAN interrupts according to the provided mask. + * + * This function enables the FlexCAN interrupts according to the provided mask. The mask + * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable. + * + * @param base FlexCAN peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _flexcan_interrupt_enable. + */ +static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask) +{ + /* Solve Wake Up Interrupt. */ + if ((uint32_t)kFLEXCAN_WakeUpInterruptEnable == (mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable)) + { + base->MCR |= CAN_MCR_WAKMSK_MASK; + } + + /* Solve others. */ + base->CTRL1 |= (mask & (~((uint32_t)kFLEXCAN_WakeUpInterruptEnable))); +} + +/*! + * @brief Disables FlexCAN interrupts according to the provided mask. + * + * This function disables the FlexCAN interrupts according to the provided mask. The mask + * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable. + * + * @param base FlexCAN peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _flexcan_interrupt_enable. + */ +static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask) +{ + /* Solve Wake Up Interrupt. */ + if ((uint32_t)kFLEXCAN_WakeUpInterruptEnable == (mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable)) + { + base->MCR &= ~CAN_MCR_WAKMSK_MASK; + } + + /* Solve others. */ + base->CTRL1 &= ~(mask & (~((uint32_t)kFLEXCAN_WakeUpInterruptEnable))); +} + +/*! + * @brief Enables FlexCAN Message Buffer interrupts. + * + * This function enables the interrupts of given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFFU); + base->IMASK2 |= (uint32_t)(mask >> 32); +#else + base->IMASK1 |= mask; +#endif +} + +/*! + * @brief Disables FlexCAN Message Buffer interrupts. + * + * This function disables the interrupts of given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFFU)); + base->IMASK2 &= ~((uint32_t)(mask >> 32)); +#else + base->IMASK1 &= ~mask; +#endif +} + +/* @} */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables or disables the FlexCAN Rx FIFO DMA request. + * + * This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param enable true to enable, false to disable. + */ +void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable); + +/*! + * @brief Gets the Rx FIFO Head address. + * + * This function returns the FlexCAN Rx FIFO Head address, which is mainly used for the DMA/eDMA use case. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN Rx FIFO Head address. + */ +static inline uint32_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base) +{ + return (uint32_t) & (base->MB[0].CS); +} + +/* @} */ +#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables or disables the FlexCAN module operation. + * + * This function enables or disables the FlexCAN module. + * + * @param base FlexCAN base pointer. + * @param enable true to enable, false to disable. + */ +static inline void FLEXCAN_Enable(CAN_Type *base, bool enable) +{ + if (enable) + { + base->MCR &= ~CAN_MCR_MDIS_MASK; + + /* Wait FlexCAN exit from low-power mode. */ + while (0U != (base->MCR & CAN_MCR_LPMACK_MASK)) + { + } + } + else + { + base->MCR |= CAN_MCR_MDIS_MASK; + + /* Wait FlexCAN enter low-power mode. */ + while (0U == (base->MCR & CAN_MCR_LPMACK_MASK)) + { + } + } +} + +/*! + * @brief Writes a FlexCAN Message to the Transmit Message Buffer. + * + * This function writes a CAN Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN Message transmit. After + * that the function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + * @param txFrame Pointer to CAN message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *txFrame); + +/*! + * @brief Reads a FlexCAN Message from Receive Message Buffer. + * + * This function reads a CAN message from a specified Receive Message Buffer. + * The function fills a receive CAN message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + * @param rxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Writes a FlexCAN FD Message to the Transmit Message Buffer. + * + * This function writes a CAN FD Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN FD Message transmit. After + * that the function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param txFrame Pointer to CAN FD message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *txFrame); + +/*! + * @brief Reads a FlexCAN FD Message from Receive Message Buffer. + * + * This function reads a CAN FD message from a specified Receive Message Buffer. + * The function fills a receive CAN FD message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param rxFrame Pointer to CAN FD message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame); +#endif + +/*! + * @brief Reads a FlexCAN Message from Rx FIFO. + * + * This function reads a CAN message from the FlexCAN build-in Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param rxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *rxFrame); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Performs a polling send transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param txFrame Pointer to CAN FD message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *txFrame); + +/*! + * @brief Performs a polling receive transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param rxFrame Pointer to CAN FD message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *rxFrame); + +/*! + * @brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param xfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success Start Tx Message Buffer sending process successfully. + * @retval kStatus_Fail Write Tx Message Buffer failed. + * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer); + +/*! + * @brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param xfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN FD Message Buffer index. + */ +void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN FD Message Buffer index. + */ +void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); +#endif + +/*! + * @brief Performs a polling send transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN Message Buffer index. + * @param txFrame Pointer to CAN message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *txFrame); + +/*! + * @brief Performs a polling receive transaction on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN Message Buffer index. + * @param rxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *rxFrame); + +/*! + * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus. + * + * Note that a transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param rxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *rxFrame); + +/*! + * @brief Initializes the FlexCAN handle. + * + * This function initializes the FlexCAN handle, which can be used for other FlexCAN + * transactional APIs. Usually, for a specified FlexCAN instance, + * call this API once to get the initialized handle. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +void FLEXCAN_TransferCreateHandle(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success Start Tx Message Buffer sending process successfully. + * @retval kStatus_Fail Write Tx Message Buffer failed. + * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer); + +/*! + * @brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param xfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *xfer); + +/*! + * @brief Receives a message from Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param xfer FlexCAN Rx FIFO transfer structure. See the @ref flexcan_fifo_transfer_t. + * @retval kStatus_Success - Start Rx FIFO receiving process successfully. + * @retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. + */ +status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_fifo_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message receive from Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Rx FIFO process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle); + +/*! + * @brief FlexCAN IRQ handle function. + * + * This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_FLEXCAN_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio.c new file mode 100644 index 0000000000..9cb5046e05 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio.c @@ -0,0 +1,427 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio" +#endif + +/*< @brief user configurable flexio handle count. */ +#define FLEXIO_HANDLE_COUNT 2 + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to flexio bases for each instance. */ +FLEXIO_Type *const s_flexioBases[] = FLEXIO_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to flexio clocks for each instance. */ +const clock_ip_name_t s_flexioClocks[] = FLEXIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*< @brief pointer to array of FLEXIO handle. */ +static void *s_flexioHandle[FLEXIO_HANDLE_COUNT]; + +/*< @brief pointer to array of FLEXIO IP types. */ +static void *s_flexioType[FLEXIO_HANDLE_COUNT]; + +/*< @brief pointer to array of FLEXIO Isr. */ +static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT]; + +/******************************************************************************* + * Codes + ******************************************************************************/ + +/*! + * brief Get instance number for FLEXIO module. + * + * param base FLEXIO peripheral base address. + */ +uint32_t FLEXIO_GetInstance(FLEXIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_flexioBases); instance++) + { + if (s_flexioBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_flexioBases)); + + return instance; +} + +/*! + * brief Configures the FlexIO with a FlexIO configuration. The configuration structure + * can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig(). + * + * Example + code + flexio_config_t config = { + .enableFlexio = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false + }; + FLEXIO_Configure(base, &config); + endcode + * + * param base FlexIO peripheral base address + * param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig) +{ + uint32_t ctrlReg = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(s_flexioClocks[FLEXIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + FLEXIO_Reset(base); + + ctrlReg = base->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DBGE(userConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(userConfig->enableFlexio)); + if (!userConfig->enableInDoze) + { + ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->CTRL = ctrlReg; +} + +/*! + * brief Gates the FlexIO clock. Call this API to stop the FlexIO clock. + * + * note After calling this API, call the FLEXO_Init to use the FlexIO module. + * + * param base FlexIO peripheral base address + */ +void FLEXIO_Deinit(FLEXIO_Type *base) +{ + FLEXIO_Enable(base, false); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_flexioClocks[FLEXIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets the default configuration to configure the FlexIO module. The configuration + * can used directly to call the FLEXIO_Configure(). + * + * Example: + code + flexio_config_t config; + FLEXIO_GetDefaultConfig(&config); + endcode + * + * param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig) +{ + assert(userConfig); + + /* Initializes the configure structure to zero. */ + memset(userConfig, 0, sizeof(*userConfig)); + + userConfig->enableFlexio = true; + userConfig->enableInDoze = false; + userConfig->enableInDebug = true; + userConfig->enableFastAccess = false; +} + +/*! + * brief Resets the FlexIO module. + * + * param base FlexIO peripheral base address + */ +void FLEXIO_Reset(FLEXIO_Type *base) +{ + /*do software reset, software reset operation affect all other FLEXIO registers except CTRL*/ + base->CTRL |= FLEXIO_CTRL_SWRST_MASK; + base->CTRL = 0; +} + +/*! + * brief Gets the shifter buffer address for the DMA transfer usage. + * + * param base FlexIO peripheral base address + * param type Shifter type of flexio_shifter_buffer_type_t + * param index Shifter index + * return Corresponding shifter buffer index + */ +uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index) +{ + assert(index < FLEXIO_SHIFTBUF_COUNT); + + uint32_t address = 0; + + switch (type) + { + case kFLEXIO_ShifterBuffer: + address = (uint32_t) & (base->SHIFTBUF[index]); + break; + + case kFLEXIO_ShifterBufferBitSwapped: + address = (uint32_t) & (base->SHIFTBUFBIS[index]); + break; + + case kFLEXIO_ShifterBufferByteSwapped: + address = (uint32_t) & (base->SHIFTBUFBYS[index]); + break; + + case kFLEXIO_ShifterBufferBitByteSwapped: + address = (uint32_t) & (base->SHIFTBUFBBS[index]); + break; + +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP + case kFLEXIO_ShifterBufferNibbleByteSwapped: + address = (uint32_t) & (base->SHIFTBUFNBS[index]); + break; + +#endif +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP + case kFLEXIO_ShifterBufferHalfWordSwapped: + address = (uint32_t) & (base->SHIFTBUFHWS[index]); + break; + +#endif +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP + case kFLEXIO_ShifterBufferNibbleSwapped: + address = (uint32_t) & (base->SHIFTBUFNIS[index]); + break; + +#endif + default: + break; + } + return address; +} + +/*! + * brief Configures the shifter with the shifter configuration. The configuration structure + * covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper + * mode, select which timer controls the shifter to shift, whether to generate start bit/stop + * bit, and the polarity of start bit and stop bit. + * + * Example + code + flexio_shifter_config_t config = { + .timerSelect = 0, + .timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinPolarity = kFLEXIO_PinActiveLow, + .shifterMode = kFLEXIO_ShifterModeTransmit, + .inputSource = kFLEXIO_ShifterInputFromPin, + .shifterStop = kFLEXIO_ShifterStopBitHigh, + .shifterStart = kFLEXIO_ShifterStartBitLow + }; + FLEXIO_SetShifterConfig(base, &config); + endcode + * + * param base FlexIO peripheral base address + * param index Shifter index + * param shifterConfig Pointer to flexio_shifter_config_t structure +*/ +void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig) +{ + base->SHIFTCFG[index] = FLEXIO_SHIFTCFG_INSRC(shifterConfig->inputSource) +#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH + | FLEXIO_SHIFTCFG_PWIDTH(shifterConfig->parallelWidth) +#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */ + | FLEXIO_SHIFTCFG_SSTOP(shifterConfig->shifterStop) | + FLEXIO_SHIFTCFG_SSTART(shifterConfig->shifterStart); + + base->SHIFTCTL[index] = + FLEXIO_SHIFTCTL_TIMSEL(shifterConfig->timerSelect) | FLEXIO_SHIFTCTL_TIMPOL(shifterConfig->timerPolarity) | + FLEXIO_SHIFTCTL_PINCFG(shifterConfig->pinConfig) | FLEXIO_SHIFTCTL_PINSEL(shifterConfig->pinSelect) | + FLEXIO_SHIFTCTL_PINPOL(shifterConfig->pinPolarity) | FLEXIO_SHIFTCTL_SMOD(shifterConfig->shifterMode); +} + +/*! + * brief Configures the timer with the timer configuration. The configuration structure + * covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper + * mode, select trigger source for timer and the timer pin output and the timing for timer. + * + * Example + code + flexio_timer_config_t config = { + .triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0), + .triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow, + .triggerSource = kFLEXIO_TimerTriggerSourceInternal, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinSelect = 0, + .pinPolarity = kFLEXIO_PinActiveHigh, + .timerMode = kFLEXIO_TimerModeDual8BitBaudBit, + .timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset, + .timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput, + .timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput, + .timerDisable = kFLEXIO_TimerDisableOnTimerCompare, + .timerEnable = kFLEXIO_TimerEnableOnTriggerHigh, + .timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable, + .timerStart = kFLEXIO_TimerStartBitEnabled + }; + FLEXIO_SetTimerConfig(base, &config); + endcode + * + * param base FlexIO peripheral base address + * param index Timer index + * param timerConfig Pointer to the flexio_timer_config_t structure +*/ +void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig) +{ + base->TIMCFG[index] = + FLEXIO_TIMCFG_TIMOUT(timerConfig->timerOutput) | FLEXIO_TIMCFG_TIMDEC(timerConfig->timerDecrement) | + FLEXIO_TIMCFG_TIMRST(timerConfig->timerReset) | FLEXIO_TIMCFG_TIMDIS(timerConfig->timerDisable) | + FLEXIO_TIMCFG_TIMENA(timerConfig->timerEnable) | FLEXIO_TIMCFG_TSTOP(timerConfig->timerStop) | + FLEXIO_TIMCFG_TSTART(timerConfig->timerStart); + + base->TIMCMP[index] = FLEXIO_TIMCMP_CMP(timerConfig->timerCompare); + + base->TIMCTL[index] = FLEXIO_TIMCTL_TRGSEL(timerConfig->triggerSelect) | + FLEXIO_TIMCTL_TRGPOL(timerConfig->triggerPolarity) | + FLEXIO_TIMCTL_TRGSRC(timerConfig->triggerSource) | + FLEXIO_TIMCTL_PINCFG(timerConfig->pinConfig) | FLEXIO_TIMCTL_PINSEL(timerConfig->pinSelect) | + FLEXIO_TIMCTL_PINPOL(timerConfig->pinPolarity) | FLEXIO_TIMCTL_TIMOD(timerConfig->timerMode); +} + +/*! + * brief Registers the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * param base Pointer to the FlexIO simulated peripheral type. + * param handle Pointer to the handler for FlexIO simulated peripheral. + * param isr FlexIO simulated peripheral interrupt handler. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr) +{ + assert(base); + assert(handle); + assert(isr); + + uint8_t index = 0; + + /* Find the an empty handle pointer to store the handle. */ + for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) + { + if (s_flexioHandle[index] == NULL) + { + /* Register FLEXIO simulated driver base, handle and isr. */ + s_flexioType[index] = base; + s_flexioHandle[index] = handle; + s_flexioIsr[index] = isr; + break; + } + } + + if (index == FLEXIO_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + else + { + return kStatus_Success; + } +} + +/*! + * brief Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * param base Pointer to the FlexIO simulated peripheral type. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_UnregisterHandleIRQ(void *base) +{ + assert(base); + + uint8_t index = 0; + + /* Find the index from base address mappings. */ + for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) + { + if (s_flexioType[index] == base) + { + /* Unregister FLEXIO simulated driver handle and isr. */ + s_flexioType[index] = NULL; + s_flexioHandle[index] = NULL; + s_flexioIsr[index] = NULL; + break; + } + } + + if (index == FLEXIO_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + else + { + return kStatus_Success; + } +} + +void FLEXIO_CommonIRQHandler(void) +{ + uint8_t index; + + for (index = 0; index < FLEXIO_HANDLE_COUNT; index++) + { + if (s_flexioHandle[index]) + { + s_flexioIsr[index](s_flexioType[index], s_flexioHandle[index]); + } + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void FLEXIO_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO0_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO1_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void UART2_FLEXIO_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO2_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO3_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio.h new file mode 100644 index 0000000000..b54a1dc2f6 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio.h @@ -0,0 +1,700 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_FLEXIO_H_ +#define _FSL_FLEXIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexio_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO driver version 2.0.2. */ +#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! @brief Calculate FlexIO timer trigger.*/ +#define FLEXIO_TIMER_TRIGGER_SEL_PININPUT(x) ((uint32_t)(x) << 1U) +#define FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(x) (((uint32_t)(x) << 2U) | 0x1U) +#define FLEXIO_TIMER_TRIGGER_SEL_TIMn(x) (((uint32_t)(x) << 2U) | 0x3U) + +/*! @brief Define time of timer trigger polarity.*/ +typedef enum _flexio_timer_trigger_polarity +{ + kFLEXIO_TimerTriggerPolarityActiveHigh = 0x0U, /*!< Active high. */ + kFLEXIO_TimerTriggerPolarityActiveLow = 0x1U, /*!< Active low. */ +} flexio_timer_trigger_polarity_t; + +/*! @brief Define type of timer trigger source.*/ +typedef enum _flexio_timer_trigger_source +{ + kFLEXIO_TimerTriggerSourceExternal = 0x0U, /*!< External trigger selected. */ + kFLEXIO_TimerTriggerSourceInternal = 0x1U, /*!< Internal trigger selected. */ +} flexio_timer_trigger_source_t; + +/*! @brief Define type of timer/shifter pin configuration.*/ +typedef enum _flexio_pin_config +{ + kFLEXIO_PinConfigOutputDisabled = 0x0U, /*!< Pin output disabled. */ + kFLEXIO_PinConfigOpenDrainOrBidirection = 0x1U, /*!< Pin open drain or bidirectional output enable. */ + kFLEXIO_PinConfigBidirectionOutputData = 0x2U, /*!< Pin bidirectional output data. */ + kFLEXIO_PinConfigOutput = 0x3U, /*!< Pin output. */ +} flexio_pin_config_t; + +/*! @brief Definition of pin polarity.*/ +typedef enum _flexio_pin_polarity +{ + kFLEXIO_PinActiveHigh = 0x0U, /*!< Active high. */ + kFLEXIO_PinActiveLow = 0x1U, /*!< Active low. */ +} flexio_pin_polarity_t; + +/*! @brief Define type of timer work mode.*/ +typedef enum _flexio_timer_mode +{ + kFLEXIO_TimerModeDisabled = 0x0U, /*!< Timer Disabled. */ + kFLEXIO_TimerModeDual8BitBaudBit = 0x1U, /*!< Dual 8-bit counters baud/bit mode. */ + kFLEXIO_TimerModeDual8BitPWM = 0x2U, /*!< Dual 8-bit counters PWM mode. */ + kFLEXIO_TimerModeSingle16Bit = 0x3U, /*!< Single 16-bit counter mode. */ +} flexio_timer_mode_t; + +/*! @brief Define type of timer initial output or timer reset condition.*/ +typedef enum _flexio_timer_output +{ + kFLEXIO_TimerOutputOneNotAffectedByReset = 0x0U, /*!< Logic one when enabled and is not affected by timer + reset. */ + kFLEXIO_TimerOutputZeroNotAffectedByReset = 0x1U, /*!< Logic zero when enabled and is not affected by timer + reset. */ + kFLEXIO_TimerOutputOneAffectedByReset = 0x2U, /*!< Logic one when enabled and on timer reset. */ + kFLEXIO_TimerOutputZeroAffectedByReset = 0x3U, /*!< Logic zero when enabled and on timer reset. */ +} flexio_timer_output_t; + +/*! @brief Define type of timer decrement.*/ +typedef enum _flexio_timer_decrement_source +{ + kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput = 0x0U, /*!< Decrement counter on FlexIO clock, Shift clock + equals Timer output. */ + kFLEXIO_TimerDecSrcOnTriggerInputShiftTimerOutput = 0x1U, /*!< Decrement counter on Trigger input (both edges), + Shift clock equals Timer output. */ + kFLEXIO_TimerDecSrcOnPinInputShiftPinInput = 0x2U, /*!< Decrement counter on Pin input (both edges), + Shift clock equals Pin input. */ + kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput = 0x3U, /*!< Decrement counter on Trigger input (both edges), + Shift clock equals Trigger input. */ +} flexio_timer_decrement_source_t; + +/*! @brief Define type of timer reset condition.*/ +typedef enum _flexio_timer_reset_condition +{ + kFLEXIO_TimerResetNever = 0x0U, /*!< Timer never reset. */ + kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput = 0x2U, /*!< Timer reset on Timer Pin equal to Timer Output. */ + kFLEXIO_TimerResetOnTimerTriggerEqualToTimerOutput = 0x3U, /*!< Timer reset on Timer Trigger equal to + Timer Output. */ + kFLEXIO_TimerResetOnTimerPinRisingEdge = 0x4U, /*!< Timer reset on Timer Pin rising edge. */ + kFLEXIO_TimerResetOnTimerTriggerRisingEdge = 0x6U, /*!< Timer reset on Trigger rising edge. */ + kFLEXIO_TimerResetOnTimerTriggerBothEdge = 0x7U, /*!< Timer reset on Trigger rising or falling edge. */ +} flexio_timer_reset_condition_t; + +/*! @brief Define type of timer disable condition.*/ +typedef enum _flexio_timer_disable_condition +{ + kFLEXIO_TimerDisableNever = 0x0U, /*!< Timer never disabled. */ + kFLEXIO_TimerDisableOnPreTimerDisable = 0x1U, /*!< Timer disabled on Timer N-1 disable. */ + kFLEXIO_TimerDisableOnTimerCompare = 0x2U, /*!< Timer disabled on Timer compare. */ + kFLEXIO_TimerDisableOnTimerCompareTriggerLow = 0x3U, /*!< Timer disabled on Timer compare and Trigger Low. */ + kFLEXIO_TimerDisableOnPinBothEdge = 0x4U, /*!< Timer disabled on Pin rising or falling edge. */ + kFLEXIO_TimerDisableOnPinBothEdgeTriggerHigh = 0x5U, /*!< Timer disabled on Pin rising or falling edge provided + Trigger is high. */ + kFLEXIO_TimerDisableOnTriggerFallingEdge = 0x6U, /*!< Timer disabled on Trigger falling edge. */ +} flexio_timer_disable_condition_t; + +/*! @brief Define type of timer enable condition.*/ +typedef enum _flexio_timer_enable_condition +{ + kFLEXIO_TimerEnabledAlways = 0x0U, /*!< Timer always enabled. */ + kFLEXIO_TimerEnableOnPrevTimerEnable = 0x1U, /*!< Timer enabled on Timer N-1 enable. */ + kFLEXIO_TimerEnableOnTriggerHigh = 0x2U, /*!< Timer enabled on Trigger high. */ + kFLEXIO_TimerEnableOnTriggerHighPinHigh = 0x3U, /*!< Timer enabled on Trigger high and Pin high. */ + kFLEXIO_TimerEnableOnPinRisingEdge = 0x4U, /*!< Timer enabled on Pin rising edge. */ + kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh = 0x5U, /*!< Timer enabled on Pin rising edge and Trigger high. */ + kFLEXIO_TimerEnableOnTriggerRisingEdge = 0x6U, /*!< Timer enabled on Trigger rising edge. */ + kFLEXIO_TimerEnableOnTriggerBothEdge = 0x7U, /*!< Timer enabled on Trigger rising or falling edge. */ +} flexio_timer_enable_condition_t; + +/*! @brief Define type of timer stop bit generate condition.*/ +typedef enum _flexio_timer_stop_bit_condition +{ + kFLEXIO_TimerStopBitDisabled = 0x0U, /*!< Stop bit disabled. */ + kFLEXIO_TimerStopBitEnableOnTimerCompare = 0x1U, /*!< Stop bit is enabled on timer compare. */ + kFLEXIO_TimerStopBitEnableOnTimerDisable = 0x2U, /*!< Stop bit is enabled on timer disable. */ + kFLEXIO_TimerStopBitEnableOnTimerCompareDisable = 0x3U, /*!< Stop bit is enabled on timer compare and timer + disable. */ +} flexio_timer_stop_bit_condition_t; + +/*! @brief Define type of timer start bit generate condition.*/ +typedef enum _flexio_timer_start_bit_condition +{ + kFLEXIO_TimerStartBitDisabled = 0x0U, /*!< Start bit disabled. */ + kFLEXIO_TimerStartBitEnabled = 0x1U, /*!< Start bit enabled. */ +} flexio_timer_start_bit_condition_t; + +/*! @brief Define type of timer polarity for shifter control. */ +typedef enum _flexio_shifter_timer_polarity +{ + kFLEXIO_ShifterTimerPolarityOnPositive = 0x0U, /*!< Shift on positive edge of shift clock. */ + kFLEXIO_ShifterTimerPolarityOnNegitive = 0x1U, /*!< Shift on negative edge of shift clock. */ +} flexio_shifter_timer_polarity_t; + +/*! @brief Define type of shifter working mode.*/ +typedef enum _flexio_shifter_mode +{ + kFLEXIO_ShifterDisabled = 0x0U, /*!< Shifter is disabled. */ + kFLEXIO_ShifterModeReceive = 0x1U, /*!< Receive mode. */ + kFLEXIO_ShifterModeTransmit = 0x2U, /*!< Transmit mode. */ + kFLEXIO_ShifterModeMatchStore = 0x4U, /*!< Match store mode. */ + kFLEXIO_ShifterModeMatchContinuous = 0x5U, /*!< Match continuous mode. */ +#if FSL_FEATURE_FLEXIO_HAS_STATE_MODE + kFLEXIO_ShifterModeState = 0x6U, /*!< SHIFTBUF contents are used for storing + programmable state attributes. */ +#endif /* FSL_FEATURE_FLEXIO_HAS_STATE_MODE */ +#if FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE + kFLEXIO_ShifterModeLogic = 0x7U, /*!< SHIFTBUF contents are used for implementing + programmable logic look up table. */ +#endif /* FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE */ +} flexio_shifter_mode_t; + +/*! @brief Define type of shifter input source.*/ +typedef enum _flexio_shifter_input_source +{ + kFLEXIO_ShifterInputFromPin = 0x0U, /*!< Shifter input from pin. */ + kFLEXIO_ShifterInputFromNextShifterOutput = 0x1U, /*!< Shifter input from Shifter N+1. */ +} flexio_shifter_input_source_t; + +/*! @brief Define of STOP bit configuration.*/ +typedef enum _flexio_shifter_stop_bit +{ + kFLEXIO_ShifterStopBitDisable = 0x0U, /*!< Disable shifter stop bit. */ + kFLEXIO_ShifterStopBitLow = 0x2U, /*!< Set shifter stop bit to logic low level. */ + kFLEXIO_ShifterStopBitHigh = 0x3U, /*!< Set shifter stop bit to logic high level. */ +} flexio_shifter_stop_bit_t; + +/*! @brief Define type of START bit configuration.*/ +typedef enum _flexio_shifter_start_bit +{ + kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable = 0x0U, /*!< Disable shifter start bit, transmitter loads + data on enable. */ + kFLEXIO_ShifterStartBitDisabledLoadDataOnShift = 0x1U, /*!< Disable shifter start bit, transmitter loads + data on first shift. */ + kFLEXIO_ShifterStartBitLow = 0x2U, /*!< Set shifter start bit to logic low level. */ + kFLEXIO_ShifterStartBitHigh = 0x3U, /*!< Set shifter start bit to logic high level. */ +} flexio_shifter_start_bit_t; + +/*! @brief Define FlexIO shifter buffer type*/ +typedef enum _flexio_shifter_buffer_type +{ + kFLEXIO_ShifterBuffer = 0x0U, /*!< Shifter Buffer N Register. */ + kFLEXIO_ShifterBufferBitSwapped = 0x1U, /*!< Shifter Buffer N Bit Byte Swapped Register. */ + kFLEXIO_ShifterBufferByteSwapped = 0x2U, /*!< Shifter Buffer N Byte Swapped Register. */ + kFLEXIO_ShifterBufferBitByteSwapped = 0x3U, /*!< Shifter Buffer N Bit Swapped Register. */ +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP + kFLEXIO_ShifterBufferNibbleByteSwapped = 0x4U, /*!< Shifter Buffer N Nibble Byte Swapped Register. */ +#endif /*FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP*/ +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP + kFLEXIO_ShifterBufferHalfWordSwapped = 0x5U, /*!< Shifter Buffer N Half Word Swapped Register. */ +#endif +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP + kFLEXIO_ShifterBufferNibbleSwapped = 0x6U, /*!< Shifter Buffer N Nibble Swapped Register. */ +#endif +} flexio_shifter_buffer_type_t; + +/*! @brief Define FlexIO user configuration structure. */ +typedef struct _flexio_config_ +{ + bool enableFlexio; /*!< Enable/disable FlexIO module */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires + the FlexIO clock to be at least twice the frequency of the bus clock. */ +} flexio_config_t; + +/*! @brief Define FlexIO timer configuration structure. */ +typedef struct _flexio_timer_config +{ + /* Trigger. */ + uint32_t triggerSelect; /*!< The internal trigger selection number using MACROs. */ + flexio_timer_trigger_polarity_t triggerPolarity; /*!< Trigger Polarity. */ + flexio_timer_trigger_source_t triggerSource; /*!< Trigger Source, internal (see 'trgsel') or external. */ + /* Pin. */ + flexio_pin_config_t pinConfig; /*!< Timer Pin Configuration. */ + uint32_t pinSelect; /*!< Timer Pin number Select. */ + flexio_pin_polarity_t pinPolarity; /*!< Timer Pin Polarity. */ + /* Timer. */ + flexio_timer_mode_t timerMode; /*!< Timer work Mode. */ + flexio_timer_output_t timerOutput; /*!< Configures the initial state of the Timer Output and + whether it is affected by the Timer reset. */ + flexio_timer_decrement_source_t timerDecrement; /*!< Configures the source of the Timer decrement and the + source of the Shift clock. */ + flexio_timer_reset_condition_t timerReset; /*!< Configures the condition that causes the timer counter + (and optionally the timer output) to be reset. */ + flexio_timer_disable_condition_t timerDisable; /*!< Configures the condition that causes the Timer to be + disabled and stop decrementing. */ + flexio_timer_enable_condition_t timerEnable; /*!< Configures the condition that causes the Timer to be + enabled and start decrementing. */ + flexio_timer_stop_bit_condition_t timerStop; /*!< Timer STOP Bit generation. */ + flexio_timer_start_bit_condition_t timerStart; /*!< Timer STRAT Bit generation. */ + uint32_t timerCompare; /*!< Value for Timer Compare N Register. */ +} flexio_timer_config_t; + +/*! @brief Define FlexIO shifter configuration structure. */ +typedef struct _flexio_shifter_config +{ + /* Timer. */ + uint32_t timerSelect; /*!< Selects which Timer is used for controlling the + logic/shift register and generating the Shift clock. */ + flexio_shifter_timer_polarity_t timerPolarity; /*!< Timer Polarity. */ + /* Pin. */ + flexio_pin_config_t pinConfig; /*!< Shifter Pin Configuration. */ + uint32_t pinSelect; /*!< Shifter Pin number Select. */ + flexio_pin_polarity_t pinPolarity; /*!< Shifter Pin Polarity. */ + /* Shifter. */ + flexio_shifter_mode_t shifterMode; /*!< Configures the mode of the Shifter. */ +#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH + uint32_t parallelWidth; /*!< Configures the parallel width when using parallel mode.*/ +#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */ + flexio_shifter_input_source_t inputSource; /*!< Selects the input source for the shifter. */ + flexio_shifter_stop_bit_t shifterStop; /*!< Shifter STOP bit. */ + flexio_shifter_start_bit_t shifterStart; /*!< Shifter START bit. */ +} flexio_shifter_config_t; + +/*! @brief typedef for FlexIO simulated driver interrupt handler.*/ +typedef void (*flexio_isr_t)(void *base, void *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to flexio bases for each instance. */ +extern FLEXIO_Type *const s_flexioBases[]; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to flexio clocks for each instance. */ +extern const clock_ip_name_t s_flexioClocks[]; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name FlexIO Initialization and De-initialization + * @{ + */ + +/*! + * @brief Gets the default configuration to configure the FlexIO module. The configuration + * can used directly to call the FLEXIO_Configure(). + * + * Example: + @code + flexio_config_t config; + FLEXIO_GetDefaultConfig(&config); + @endcode + * + * @param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig); + +/*! + * @brief Configures the FlexIO with a FlexIO configuration. The configuration structure + * can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig(). + * + * Example + @code + flexio_config_t config = { + .enableFlexio = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false + }; + FLEXIO_Configure(base, &config); + @endcode + * + * @param base FlexIO peripheral base address + * @param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig); + +/*! + * @brief Gates the FlexIO clock. Call this API to stop the FlexIO clock. + * + * @note After calling this API, call the FLEXO_Init to use the FlexIO module. + * + * @param base FlexIO peripheral base address + */ +void FLEXIO_Deinit(FLEXIO_Type *base); + +/*! + * @brief Get instance number for FLEXIO module. + * + * @param base FLEXIO peripheral base address. + */ +uint32_t FLEXIO_GetInstance(FLEXIO_Type *base); + +/* @} */ + +/*! + * @name FlexIO Basic Operation + * @{ + */ + +/*! + * @brief Resets the FlexIO module. + * + * @param base FlexIO peripheral base address + */ +void FLEXIO_Reset(FLEXIO_Type *base); + +/*! + * @brief Enables the FlexIO module operation. + * + * @param base FlexIO peripheral base address + * @param enable true to enable, false to disable. + */ +static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } + else + { + base->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; + } +} + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS +/*! + * @brief Reads the input data on each of the FlexIO pins. + * + * @param base FlexIO peripheral base address + * @return FlexIO pin input data + */ +static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base) +{ + return base->PIN; +} +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/ + +#if defined(FSL_FEATURE_FLEXIO_HAS_STATE_MODE) && FSL_FEATURE_FLEXIO_HAS_STATE_MODE +/*! + * @brief Gets the current state pointer for state mode use. + * + * @param base FlexIO peripheral base address + * @return current State pointer + */ +static inline uint8_t FLEXIO_GetShifterState(FLEXIO_Type *base) +{ + return ((base->SHIFTSTATE) & FLEXIO_SHIFTSTATE_STATE_MASK); +} +#endif /*FSL_FEATURE_FLEXIO_HAS_STATE_MODE*/ + +/*! + * @brief Configures the shifter with the shifter configuration. The configuration structure + * covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper + * mode, select which timer controls the shifter to shift, whether to generate start bit/stop + * bit, and the polarity of start bit and stop bit. + * + * Example + @code + flexio_shifter_config_t config = { + .timerSelect = 0, + .timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinPolarity = kFLEXIO_PinActiveLow, + .shifterMode = kFLEXIO_ShifterModeTransmit, + .inputSource = kFLEXIO_ShifterInputFromPin, + .shifterStop = kFLEXIO_ShifterStopBitHigh, + .shifterStart = kFLEXIO_ShifterStartBitLow + }; + FLEXIO_SetShifterConfig(base, &config); + @endcode + * + * @param base FlexIO peripheral base address + * @param index Shifter index + * @param shifterConfig Pointer to flexio_shifter_config_t structure +*/ +void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig); +/*! + * @brief Configures the timer with the timer configuration. The configuration structure + * covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper + * mode, select trigger source for timer and the timer pin output and the timing for timer. + * + * Example + @code + flexio_timer_config_t config = { + .triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0), + .triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow, + .triggerSource = kFLEXIO_TimerTriggerSourceInternal, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinSelect = 0, + .pinPolarity = kFLEXIO_PinActiveHigh, + .timerMode = kFLEXIO_TimerModeDual8BitBaudBit, + .timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset, + .timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput, + .timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput, + .timerDisable = kFLEXIO_TimerDisableOnTimerCompare, + .timerEnable = kFLEXIO_TimerEnableOnTriggerHigh, + .timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable, + .timerStart = kFLEXIO_TimerStartBitEnabled + }; + FLEXIO_SetTimerConfig(base, &config); + @endcode + * + * @param base FlexIO peripheral base address + * @param index Timer index + * @param timerConfig Pointer to the flexio_timer_config_t structure +*/ +void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig); + +/* @} */ + +/*! + * @name FlexIO Interrupt Operation + * @{ + */ + +/*! + * @brief Enables the shifter status interrupt. The interrupt generates when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTSIEN |= mask; +} + +/*! + * @brief Disables the shifter status interrupt. The interrupt won't generate when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTSIEN &= ~mask; +} + +/*! + * @brief Enables the shifter error interrupt. The interrupt generates when the corresponding SEF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter error mask which can be calculated by (1 << shifter index) + * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTEIEN |= mask; +} + +/*! + * @brief Disables the shifter error interrupt. The interrupt won't generate when the corresponding SEF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter error mask which can be calculated by (1 << shifter index) + * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTEIEN &= ~mask; +} + +/*! + * @brief Enables the timer status interrupt. The interrupt generates when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The timer status mask which can be calculated by (1 << timer index) + * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate + * the mask by using ((1 << timer index0) | (1 << timer index1)) + */ +static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->TIMIEN |= mask; +} + +/*! + * @brief Disables the timer status interrupt. The interrupt won't generate when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The timer status mask which can be calculated by (1 << timer index) + * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate + * the mask by using ((1 << timer index0) | (1 << timer index1)) + */ +static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->TIMIEN &= ~mask; +} + +/* @} */ + +/*! + * @name FlexIO Status Operation + * @{ + */ + +/*! + * @brief Gets the shifter status flags. + * + * @param base FlexIO peripheral base address + * @return Shifter status flags + */ +static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base) +{ + return ((base->SHIFTSTAT) & FLEXIO_SHIFTSTAT_SSF_MASK); +} + +/*! + * @brief Clears the shifter status flags. + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @note For clearing multiple shifter status flags, for example, two shifter status flags, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTSTAT = mask; +} + +/*! + * @brief Gets the shifter error flags. + * + * @param base FlexIO peripheral base address + * @return Shifter error flags + */ +static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base) +{ + return ((base->SHIFTERR) & FLEXIO_SHIFTERR_SEF_MASK); +} + +/*! + * @brief Clears the shifter error flags. + * + * @param base FlexIO peripheral base address + * @param mask The shifter error mask which can be calculated by (1 << shifter index) + * @note For clearing multiple shifter error flags, for example, two shifter error flags, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTERR = mask; +} + +/*! + * @brief Gets the timer status flags. + * + * @param base FlexIO peripheral base address + * @return Timer status flags + */ +static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base) +{ + return ((base->TIMSTAT) & FLEXIO_TIMSTAT_TSF_MASK); +} + +/*! + * @brief Clears the timer status flags. + * + * @param base FlexIO peripheral base address + * @param mask The timer status mask which can be calculated by (1 << timer index) + * @note For clearing multiple timer status flags, for example, two timer status flags, can calculate + * the mask by using ((1 << timer index0) | (1 << timer index1)) + */ +static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask) +{ + base->TIMSTAT = mask; +} + +/* @} */ + +/*! + * @name FlexIO DMA Operation + * @{ + */ + +/*! + * @brief Enables/disables the shifter status DMA. The DMA request generates when the corresponding SSF is set. + * + * @note For multiple shifter status DMA enables, for example, calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @param enable True to enable, false to disable. + */ +static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->SHIFTSDEN |= mask; + } + else + { + base->SHIFTSDEN &= ~mask; + } +} + +/*! + * @brief Gets the shifter buffer address for the DMA transfer usage. + * + * @param base FlexIO peripheral base address + * @param type Shifter type of flexio_shifter_buffer_type_t + * @param index Shifter index + * @return Corresponding shifter buffer index + */ +uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index); + +/*! + * @brief Registers the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * @param base Pointer to the FlexIO simulated peripheral type. + * @param handle Pointer to the handler for FlexIO simulated peripheral. + * @param isr FlexIO simulated peripheral interrupt handler. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr); + +/*! + * @brief Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * @param base Pointer to the FlexIO simulated peripheral type. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_UnregisterHandleIRQ(void *base); +/* @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /*_FSL_FLEXIO_H_*/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_camera.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_camera.c new file mode 100644 index 0000000000..e699522c62 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_camera.c @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_camera.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_camera" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Codes + ******************************************************************************/ + +static uint32_t FLEXIO_CAMERA_GetInstance(FLEXIO_CAMERA_Type *base) +{ + return FLEXIO_GetInstance(base->flexioBase); +} + +/*! + * brief Gets the default configuration to configure the FlexIO Camera. The configuration + * can be used directly for calling the FLEXIO_CAMERA_Init(). + * Example: + code + flexio_camera_config_t config; + FLEXIO_CAMERA_GetDefaultConfig(&userConfig); + endcode + * param config Pointer to the flexio_camera_config_t structure +*/ +void FLEXIO_CAMERA_GetDefaultConfig(flexio_camera_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->enablecamera = false; + config->enableInDoze = false; + config->enableInDebug = false; + config->enableFastAccess = false; +} + +/*! + * brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO Camera. + * + * param base Pointer to FLEXIO_CAMERA_Type structure + * param config Pointer to flexio_camera_config_t structure + */ +void FLEXIO_CAMERA_Init(FLEXIO_CAMERA_Type *base, const flexio_camera_config_t *config) +{ + assert(base && config); + + volatile uint32_t i = 0; + volatile uint32_t controlVal = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate flexio clock. */ + CLOCK_EnableClock(s_flexioClocks[FLEXIO_CAMERA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + + /* Clear the shifterConfig & timerConfig struct. */ + memset(&shifterConfig, 0, sizeof(shifterConfig)); + memset(&timerConfig, 0, sizeof(timerConfig)); + + /* Configure flexio camera */ + controlVal = base->flexioBase->CTRL; + controlVal &= + ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + controlVal |= (FLEXIO_CTRL_DBGE(config->enableInDebug) | FLEXIO_CTRL_FASTACC(config->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(config->enablecamera)); + if (!config->enableInDoze) + { + controlVal |= FLEXIO_CTRL_DOZEN_MASK; + } + base->flexioBase->CTRL = controlVal; + + /* FLEXIO_CAMERA shifter config */ + shifterConfig.timerSelect = base->timerIdx; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->datPinStartIdx; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.parallelWidth = FLEXIO_CAMERA_PARALLEL_DATA_WIDTH - 1U; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromNextShifterOutput; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + /* Configure the shifters as FIFO buffer. */ + for (i = base->shifterStartIdx; i < (base->shifterStartIdx + base->shifterCount - 1U); i++) + { + FLEXIO_SetShifterConfig(base->flexioBase, i, &shifterConfig); + } + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + FLEXIO_SetShifterConfig(base->flexioBase, i, &shifterConfig); + + /* FLEXIO_CAMERA timer config, the PCLK's clk is source of timer to drive the shifter, the HREF is the selecting + * signal for available data. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->hrefPinIdx); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->pclkPinIdx; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; + timerConfig.timerReset = kFLEXIO_TimerResetOnTimerTriggerRisingEdge; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTriggerFallingEdge; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerRisingEdge; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + timerConfig.timerCompare = 8U * base->shifterCount - 1U; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIdx, &timerConfig); + /* Clear flags. */ + FLEXIO_ClearShifterErrorFlags(base->flexioBase, ((1U << (base->shifterCount)) - 1U) << (base->shifterStartIdx)); + FLEXIO_ClearTimerStatusFlags(base->flexioBase, 1U << (base->timerIdx)); +} + +/*! + * brief Resets the FLEXIO_CAMERA shifer and timer config. + * + * note After calling this API, call FLEXO_CAMERA_Init to use the FlexIO Camera module. + * + * param base Pointer to FLEXIO_CAMERA_Type structure + */ +void FLEXIO_CAMERA_Deinit(FLEXIO_CAMERA_Type *base) +{ + base->flexioBase->SHIFTCFG[base->shifterStartIdx] = 0; + base->flexioBase->SHIFTCTL[base->shifterStartIdx] = 0; + base->flexioBase->TIMCFG[base->timerIdx] = 0; + base->flexioBase->TIMCMP[base->timerIdx] = 0; + base->flexioBase->TIMCTL[base->timerIdx] = 0; + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = (1U << base->shifterStartIdx); + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1U << base->timerIdx); +} + +/*! + * brief Gets the FlexIO Camera status flags. + * + * param base Pointer to FLEXIO_CAMERA_Type structure + * return FlexIO shifter status flags + * arg FLEXIO_SHIFTSTAT_SSF_MASK + * arg 0 + */ +uint32_t FLEXIO_CAMERA_GetStatusFlags(FLEXIO_CAMERA_Type *base) +{ + uint32_t status = 0; + status = ((FLEXIO_GetShifterStatusFlags(base->flexioBase) >> (base->shifterStartIdx)) & + ((1U << (base->shifterCount)) - 1U)); + return status; +} + +/*! + * brief Clears the receive buffer full flag manually. + * + * param base Pointer to the device. + * param mask status flag + * The parameter can be any combination of the following values: + * arg kFLEXIO_CAMERA_RxDataRegFullFlag + * arg kFLEXIO_CAMERA_RxErrorFlag + */ +void FLEXIO_CAMERA_ClearStatusFlags(FLEXIO_CAMERA_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_CAMERA_RxDataRegFullFlag) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, ((1U << (base->shifterCount)) - 1U) + << (base->shifterStartIdx)); + } + if (mask & kFLEXIO_CAMERA_RxErrorFlag) + { /* Clear error flags if they are asserted to make sure the buffer would be available. */ + FLEXIO_ClearShifterErrorFlags(base->flexioBase, ((1U << (base->shifterCount)) - 1U) << (base->shifterStartIdx)); + } +} + +/*! + * brief Switches on the interrupt for receive buffer full event. + * + * param base Pointer to the device. + */ +void FLEXIO_CAMERA_EnableInterrupt(FLEXIO_CAMERA_Type *base) +{ + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << (base->shifterStartIdx)); +} + +/*! + * brief Switches off the interrupt for receive buffer full event. + * + * param base Pointer to the device. + * + */ +void FLEXIO_CAMERA_DisableInterrupt(FLEXIO_CAMERA_Type *base) +{ + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << (base->shifterStartIdx)); +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_camera.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_camera.h new file mode 100644 index 0000000000..6d7fec2574 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_camera.h @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_FLEXIO_CAMERA_H_ +#define _FSL_FLEXIO_CAMERA_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" +/*! + * @addtogroup flexio_camera + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO Camera driver version 2.1.2. */ +#define FSL_FLEXIO_CAMERA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) +/*@}*/ + +/*! @brief Define the Camera CPI interface is constantly 8-bit width. */ +#define FLEXIO_CAMERA_PARALLEL_DATA_WIDTH (8U) + +/*! @brief Error codes for the Camera driver. */ +enum _flexio_camera_status +{ + kStatus_FLEXIO_CAMERA_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_CAMERA, 0), /*!< Receiver is busy. */ + kStatus_FLEXIO_CAMERA_RxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_CAMERA, 1), /*!< Camera receiver is idle. */ +}; + +/*! @brief Define FlexIO Camera status mask. */ +enum _flexio_camera_status_flags +{ + kFLEXIO_CAMERA_RxDataRegFullFlag = 0x1U, /*!< Receive buffer full flag. */ + kFLEXIO_CAMERA_RxErrorFlag = 0x2U, /*!< Receive buffer error flag. */ +}; + +/*! + * @brief Define structure of configuring the FlexIO Camera device. + */ +typedef struct _flexio_camera_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO module base address. */ + uint32_t datPinStartIdx; /*!< First data pin (D0) index for flexio_camera. + Then the successive following FLEXIO_CAMERA_DATA_WIDTH-1 pins + are used as D1-D7.*/ + uint32_t pclkPinIdx; /*!< Pixel clock pin (PCLK) index for flexio_camera. */ + uint32_t hrefPinIdx; /*!< Horizontal sync pin (HREF) index for flexio_camera. */ + + uint32_t shifterStartIdx; /*!< First shifter index used for flexio_camera data FIFO. */ + uint32_t shifterCount; /*!< The count of shifters that are used as flexio_camera data FIFO. */ + uint32_t timerIdx; /*!< Timer index used for flexio_camera in FlexIO. */ +} FLEXIO_CAMERA_Type; + +/*! @brief Define FlexIO Camera user configuration structure. */ +typedef struct _flexio_camera_config +{ + bool enablecamera; /*!< Enable/disable FlexIO Camera TX & RX. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode*/ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode*/ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, + fast access requires the FlexIO clock to be at least + twice the frequency of the bus clock. */ +} flexio_camera_config_t; + +/*! @brief Define FlexIO Camera transfer structure. */ +typedef struct _flexio_camera_transfer +{ + uint32_t dataAddress; /*!< Transfer buffer*/ + uint32_t dataNum; /*!< Transfer num*/ +} flexio_camera_transfer_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and configuration + * @{ + */ + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO Camera. + * + * @param base Pointer to FLEXIO_CAMERA_Type structure + * @param config Pointer to flexio_camera_config_t structure + */ +void FLEXIO_CAMERA_Init(FLEXIO_CAMERA_Type *base, const flexio_camera_config_t *config); + +/*! + * @brief Resets the FLEXIO_CAMERA shifer and timer config. + * + * @note After calling this API, call FLEXO_CAMERA_Init to use the FlexIO Camera module. + * + * @param base Pointer to FLEXIO_CAMERA_Type structure + */ +void FLEXIO_CAMERA_Deinit(FLEXIO_CAMERA_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO Camera. The configuration + * can be used directly for calling the FLEXIO_CAMERA_Init(). + * Example: + @code + flexio_camera_config_t config; + FLEXIO_CAMERA_GetDefaultConfig(&userConfig); + @endcode + * @param config Pointer to the flexio_camera_config_t structure +*/ +void FLEXIO_CAMERA_GetDefaultConfig(flexio_camera_config_t *config); + +/*! + * @brief Enables/disables the FlexIO Camera module operation. + * + * @param base Pointer to the FLEXIO_CAMERA_Type + * @param enable True to enable, false does not have any effect. + */ +static inline void FLEXIO_CAMERA_Enable(FLEXIO_CAMERA_Type *base, bool enable) +{ + if (enable) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexIO Camera status flags. + * + * @param base Pointer to FLEXIO_CAMERA_Type structure + * @return FlexIO shifter status flags + * @arg FLEXIO_SHIFTSTAT_SSF_MASK + * @arg 0 + */ +uint32_t FLEXIO_CAMERA_GetStatusFlags(FLEXIO_CAMERA_Type *base); + +/*! + * @brief Clears the receive buffer full flag manually. + * + * @param base Pointer to the device. + * @param mask status flag + * The parameter can be any combination of the following values: + * @arg kFLEXIO_CAMERA_RxDataRegFullFlag + * @arg kFLEXIO_CAMERA_RxErrorFlag + */ +void FLEXIO_CAMERA_ClearStatusFlags(FLEXIO_CAMERA_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Switches on the interrupt for receive buffer full event. + * + * @param base Pointer to the device. + */ +void FLEXIO_CAMERA_EnableInterrupt(FLEXIO_CAMERA_Type *base); + +/*! + * @brief Switches off the interrupt for receive buffer full event. + * + * @param base Pointer to the device. + * + */ +void FLEXIO_CAMERA_DisableInterrupt(FLEXIO_CAMERA_Type *base); + +/*! @} */ + +/*! + * @name DMA support + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO Camera receive DMA. + * + * @param base Pointer to FLEXIO_CAMERA_Type structure + * @param enable True to enable, false to disable. + * + * The FlexIO Camera mode can't work without the DMA or eDMA support, + * Usually, it needs at least two DMA or eDMA channels, one for transferring data from + * Camera, such as 0V7670 to FlexIO buffer, another is for transferring data from FlexIO + * buffer to LCD. + * + */ +static inline void FLEXIO_CAMERA_EnableRxDMA(FLEXIO_CAMERA_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->shifterStartIdx, enable); +} + +/*! + * @brief Gets the data from the receive buffer. + * + * @param base Pointer to the device. + * @return data Pointer to the buffer that keeps the data with count of base->shifterCount . + */ +static inline uint32_t FLEXIO_CAMERA_GetRxBufferAddress(FLEXIO_CAMERA_Type *base) +{ + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterStartIdx); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + +/*@}*/ + +#endif /*_FSL_FLEXIO_CAMERA_H_*/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_camera_edma.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_camera_edma.c new file mode 100644 index 0000000000..5fb650bb63 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_camera_edma.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_camera_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_camera_edma" +#endif + +/*base, cameraPrivateHandle->handle); + + if (cameraPrivateHandle->handle->callback) + { + cameraPrivateHandle->handle->callback(cameraPrivateHandle->base, cameraPrivateHandle->handle, + kStatus_FLEXIO_CAMERA_RxIdle, cameraPrivateHandle->handle->userData); + } + } +} +/*! + * brief Initializes the Camera handle, which is used in transactional functions. + * + * param base Pointer to the FLEXIO_CAMERA_Type. + * param handle Pointer to flexio_camera_edma_handle_t structure. + * param callback The callback function. + * param userData The parameter of the callback function. + * param rxEdmaHandle User requested DMA handle for RX DMA transfer. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO Camera eDMA type/handle table out of range. + */ +status_t FLEXIO_CAMERA_TransferCreateHandleEDMA(FLEXIO_CAMERA_Type *base, + flexio_camera_edma_handle_t *handle, + flexio_camera_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *rxEdmaHandle) +{ + assert(handle); + + uint8_t index = 0; + + /* Find the an empty handle pointer to store the handle. */ + for (index = 0; index < FLEXIO_CAMERA_HANDLE_COUNT; index++) + { + if (s_edmaPrivateHandle[index].base == NULL) + { + s_edmaPrivateHandle[index].base = base; + s_edmaPrivateHandle[index].handle = handle; + break; + } + } + + if (index == FLEXIO_CAMERA_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + + s_edmaPrivateHandle[index].base = base; + s_edmaPrivateHandle[index].handle = handle; + + memset(handle, 0, sizeof(*handle)); + + handle->rxState = kFLEXIO_CAMERA_RxIdle; + handle->rxEdmaHandle = rxEdmaHandle; + + handle->callback = callback; + handle->userData = userData; + + /* Configure RX. */ + if (rxEdmaHandle) + { + EDMA_SetCallback(handle->rxEdmaHandle, FLEXIO_CAMERA_TransferReceiveEDMACallback, &s_edmaPrivateHandle); + } + + return kStatus_Success; +} + +/*! + * brief Receives data using eDMA. + * + * This function receives data using eDMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * param base Pointer to the FLEXIO_CAMERA_Type. + * param handle Pointer to the flexio_camera_edma_handle_t structure. + * param xfer Camera eDMA transfer structure, see #flexio_camera_transfer_t. + * retval kStatus_Success if succeeded, others failed. + * retval kStatus_CAMERA_RxBusy Previous transfer on going. + */ +status_t FLEXIO_CAMERA_TransferReceiveEDMA(FLEXIO_CAMERA_Type *base, + flexio_camera_edma_handle_t *handle, + flexio_camera_transfer_t *xfer) +{ + assert(handle->rxEdmaHandle); + + edma_transfer_config_t xferConfig; + status_t status; + + /* If previous RX not finished. */ + if (kFLEXIO_CAMERA_RxBusy == handle->rxState) + { + status = kStatus_FLEXIO_CAMERA_RxBusy; + } + else + { + handle->rxState = kFLEXIO_CAMERA_RxBusy; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, (void *)FLEXIO_CAMERA_GetRxBufferAddress(base), 32, (void *)xfer->dataAddress, + 32, 32, xfer->dataNum, kEDMA_PeripheralToMemory); + + /* Store the initially configured eDMA minor byte transfer count into the FLEXIO CAMERA handle */ + handle->nbytes = 32; + + /* Submit transfer. */ + EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig); + EDMA_StartTransfer(handle->rxEdmaHandle); + /* Enable CAMERA RX EDMA. */ + FLEXIO_CAMERA_EnableRxDMA(base, true); + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the receive data which used the eDMA. + * + * This function aborts the receive data which used the eDMA. + * + * param base Pointer to the FLEXIO_CAMERA_Type. + * param handle Pointer to the flexio_camera_edma_handle_t structure. + */ +void FLEXIO_CAMERA_TransferAbortReceiveEDMA(FLEXIO_CAMERA_Type *base, flexio_camera_edma_handle_t *handle) +{ + assert(handle->rxEdmaHandle); + + /* Disable CAMERA RX EDMA. */ + FLEXIO_CAMERA_EnableRxDMA(base, false); + + /* Stop transfer. */ + EDMA_StopTransfer(handle->rxEdmaHandle); + + handle->rxState = kFLEXIO_CAMERA_RxIdle; +} + +/*! + * brief Gets the remaining bytes to be received. + * + * This function gets the number of bytes still not received. + * + * param base Pointer to the FLEXIO_CAMERA_Type. + * param handle Pointer to the flexio_camera_edma_handle_t structure. + * param count Number of bytes sent so far by the non-blocking transaction. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_InvalidArgument The count parameter is invalid. + */ +status_t FLEXIO_CAMERA_TransferGetReceiveCountEDMA(FLEXIO_CAMERA_Type *base, + flexio_camera_edma_handle_t *handle, + size_t *count) +{ + assert(handle->rxEdmaHandle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + if (kFLEXIO_CAMERA_RxBusy == handle->rxState) + { + *count = (handle->rxSize - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel)); + } + else + { + *count = handle->rxSize; + } + + return kStatus_Success; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_camera_edma.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_camera_edma.h new file mode 100644 index 0000000000..303eac4048 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_camera_edma.h @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_FLEXIO_CAMERA_EDMA_H_ +#define _FSL_FLEXIO_CAMERA_EDMA_H_ + +#include "fsl_flexio_camera.h" +#include "fsl_edma.h" + +/*! + * @addtogroup flexio_edma_camera + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO Camera EDMA driver version 2.1.2. */ +#define FSL_FLEXIO_CAMERA_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) +/*@}*/ + +/*! @brief Forward declaration of the handle typedef. */ +typedef struct _flexio_camera_edma_handle flexio_camera_edma_handle_t; + +/*! @brief Camera transfer callback function. */ +typedef void (*flexio_camera_edma_transfer_callback_t)(FLEXIO_CAMERA_Type *base, + flexio_camera_edma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief Camera eDMA handle + */ +struct _flexio_camera_edma_handle +{ + flexio_camera_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< Camera callback function parameter.*/ + size_t rxSize; /*!< Total bytes to be received. */ + edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the Camera handle, which is used in transactional functions. + * + * @param base Pointer to the FLEXIO_CAMERA_Type. + * @param handle Pointer to flexio_camera_edma_handle_t structure. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO Camera eDMA type/handle table out of range. + */ +status_t FLEXIO_CAMERA_TransferCreateHandleEDMA(FLEXIO_CAMERA_Type *base, + flexio_camera_edma_handle_t *handle, + flexio_camera_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *rxEdmaHandle); + +/*! + * @brief Receives data using eDMA. + * + * This function receives data using eDMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base Pointer to the FLEXIO_CAMERA_Type. + * @param handle Pointer to the flexio_camera_edma_handle_t structure. + * @param xfer Camera eDMA transfer structure, see #flexio_camera_transfer_t. + * @retval kStatus_Success if succeeded, others failed. + * @retval kStatus_CAMERA_RxBusy Previous transfer on going. + */ +status_t FLEXIO_CAMERA_TransferReceiveEDMA(FLEXIO_CAMERA_Type *base, + flexio_camera_edma_handle_t *handle, + flexio_camera_transfer_t *xfer); + +/*! + * @brief Aborts the receive data which used the eDMA. + * + * This function aborts the receive data which used the eDMA. + * + * @param base Pointer to the FLEXIO_CAMERA_Type. + * @param handle Pointer to the flexio_camera_edma_handle_t structure. + */ +void FLEXIO_CAMERA_TransferAbortReceiveEDMA(FLEXIO_CAMERA_Type *base, flexio_camera_edma_handle_t *handle); + +/*! + * @brief Gets the remaining bytes to be received. + * + * This function gets the number of bytes still not received. + * + * @param base Pointer to the FLEXIO_CAMERA_Type. + * @param handle Pointer to the flexio_camera_edma_handle_t structure. + * @param count Number of bytes sent so far by the non-blocking transaction. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_InvalidArgument The count parameter is invalid. + */ +status_t FLEXIO_CAMERA_TransferGetReceiveCountEDMA(FLEXIO_CAMERA_Type *base, + flexio_camera_edma_handle_t *handle, + size_t *count); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CAMERA_EDMA_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_i2c_master.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_i2c_master.c new file mode 100644 index 0000000000..a3a237a35c --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_i2c_master.c @@ -0,0 +1,1017 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_i2c_master.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_i2c_master" +#endif + +/*! @brief FLEXIO I2C transfer state */ +enum _flexio_i2c_master_transfer_states +{ + kFLEXIO_I2C_Idle = 0x0U, /*!< I2C bus idle */ + kFLEXIO_I2C_CheckAddress = 0x1U, /*!< 7-bit address check state */ + kFLEXIO_I2C_SendCommand = 0x2U, /*!< Send command byte phase */ + kFLEXIO_I2C_SendData = 0x3U, /*!< Send data transfer phase*/ + kFLEXIO_I2C_ReceiveDataBegin = 0x4U, /*!< Receive data begin transfer phase*/ + kFLEXIO_I2C_ReceiveData = 0x5U, /*!< Receive data transfer phase*/ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Set up master transfer, send slave address and decide the initial + * transfer state. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param transfer pointer to flexio_i2c_master_transfer_t structure + */ +static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer); + +/*! + * @brief Master run transfer state machine to perform a byte of transfer. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param statusFlags flexio i2c hardware status + * @retval kStatus_Success Successfully run state machine + * @retval kStatus_FLEXIO_I2C_Nak Receive Nak during transfer + */ +static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags); + +/*! + * @brief Complete transfer, disable interrupt and call callback. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param status flexio transfer status + */ +static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + status_t status); + +/******************************************************************************* + * Codes + ******************************************************************************/ + +static uint32_t FLEXIO_I2C_GetInstance(FLEXIO_I2C_Type *base) +{ + return FLEXIO_GetInstance(base->flexioBase); +} + +static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer) +{ + bool needRestart; + uint32_t byteCount; + + /* Init the handle member. */ + handle->transfer.slaveAddress = xfer->slaveAddress; + handle->transfer.direction = xfer->direction; + handle->transfer.subaddress = xfer->subaddress; + handle->transfer.subaddressSize = xfer->subaddressSize; + handle->transfer.data = xfer->data; + handle->transfer.dataSize = xfer->dataSize; + handle->transfer.flags = xfer->flags; + handle->transferSize = xfer->dataSize; + + /* Initial state, i2c check address state. */ + handle->state = kFLEXIO_I2C_CheckAddress; + + /* Clear all status before transfer. */ + FLEXIO_I2C_MasterClearStatusFlags(base, kFLEXIO_I2C_ReceiveNakFlag); + + /* Calculate whether need to send re-start. */ + needRestart = (handle->transfer.subaddressSize != 0) && (handle->transfer.direction == kFLEXIO_I2C_Read); + + /* Calculate total byte count in a frame. */ + byteCount = 1; + + if (!needRestart) + { + byteCount += handle->transfer.dataSize; + } + + if (handle->transfer.subaddressSize != 0) + { + byteCount += handle->transfer.subaddressSize; + /* Next state, send command byte. */ + handle->state = kFLEXIO_I2C_SendCommand; + } + + /* Configure data count. */ + if (FLEXIO_I2C_MasterSetTransferCount(base, byteCount) != kStatus_Success) + { + return kStatus_InvalidArgument; + } + + while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) + { + } + + /* Send address byte first. */ + if (needRestart) + { + FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Write); + } + else + { + FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, handle->transfer.direction); + } + + return kStatus_Success; +} + +static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags) +{ + if (statusFlags & kFLEXIO_I2C_ReceiveNakFlag) + { + /* Clear receive nak flag. */ + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); + + if ((!((handle->state == kFLEXIO_I2C_SendData) && (handle->transfer.dataSize == 0U))) && + (!(((handle->state == kFLEXIO_I2C_ReceiveData) || (handle->state == kFLEXIO_I2C_ReceiveDataBegin)) && + (handle->transfer.dataSize == 1U)))) + { + (void)FLEXIO_I2C_MasterReadByte(base); + + FLEXIO_I2C_MasterAbortStop(base); + + handle->state = kFLEXIO_I2C_Idle; + + return kStatus_FLEXIO_I2C_Nak; + } + } + + if (handle->state == kFLEXIO_I2C_CheckAddress) + { + if (handle->transfer.direction == kFLEXIO_I2C_Write) + { + /* Next state, send data. */ + handle->state = kFLEXIO_I2C_SendData; + } + else + { + /* Next state, receive data begin. */ + handle->state = kFLEXIO_I2C_ReceiveDataBegin; + } + } + + if ((statusFlags & kFLEXIO_I2C_RxFullFlag) && (handle->state != kFLEXIO_I2C_ReceiveData)) + { + (void)FLEXIO_I2C_MasterReadByte(base); + } + + switch (handle->state) + { + case kFLEXIO_I2C_SendCommand: + if (statusFlags & kFLEXIO_I2C_TxEmptyFlag) + { + if (handle->transfer.subaddressSize > 0) + { + handle->transfer.subaddressSize--; + FLEXIO_I2C_MasterWriteByte( + base, ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize))); + + if (handle->transfer.subaddressSize == 0) + { + /* Load re-start in advance. */ + if (handle->transfer.direction == kFLEXIO_I2C_Read) + { + while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) + { + } + FLEXIO_I2C_MasterRepeatedStart(base); + } + } + } + else + { + if (handle->transfer.direction == kFLEXIO_I2C_Write) + { + /* Send first byte of data. */ + if (handle->transfer.dataSize > 0) + { + /* Next state, send data. */ + handle->state = kFLEXIO_I2C_SendData; + + FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data); + handle->transfer.data++; + handle->transfer.dataSize--; + } + else + { + FLEXIO_I2C_MasterStop(base); + + while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag)) + { + } + (void)FLEXIO_I2C_MasterReadByte(base); + + handle->state = kFLEXIO_I2C_Idle; + } + } + else + { + FLEXIO_I2C_MasterSetTransferCount(base, (handle->transfer.dataSize + 1)); + FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Read); + + /* Next state, receive data begin. */ + handle->state = kFLEXIO_I2C_ReceiveDataBegin; + } + } + } + break; + + /* Send command byte. */ + case kFLEXIO_I2C_SendData: + if (statusFlags & kFLEXIO_I2C_TxEmptyFlag) + { + /* Send one byte of data. */ + if (handle->transfer.dataSize > 0) + { + FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data); + + handle->transfer.data++; + handle->transfer.dataSize--; + } + else + { + FLEXIO_I2C_MasterStop(base); + + while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag)) + { + } + (void)FLEXIO_I2C_MasterReadByte(base); + + handle->state = kFLEXIO_I2C_Idle; + } + } + break; + + case kFLEXIO_I2C_ReceiveDataBegin: + if (statusFlags & kFLEXIO_I2C_RxFullFlag) + { + handle->state = kFLEXIO_I2C_ReceiveData; + /* Send nak at the last receive byte. */ + if (handle->transfer.dataSize == 1) + { + FLEXIO_I2C_MasterEnableAck(base, false); + while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) + { + } + FLEXIO_I2C_MasterStop(base); + } + else + { + FLEXIO_I2C_MasterEnableAck(base, true); + } + } + else if (statusFlags & kFLEXIO_I2C_TxEmptyFlag) + { + /* Read one byte of data. */ + FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); + } + else + { + } + break; + + case kFLEXIO_I2C_ReceiveData: + if (statusFlags & kFLEXIO_I2C_RxFullFlag) + { + *handle->transfer.data = FLEXIO_I2C_MasterReadByte(base); + handle->transfer.data++; + if (handle->transfer.dataSize--) + { + if (handle->transfer.dataSize == 0) + { + FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_RxFullInterruptEnable); + handle->state = kFLEXIO_I2C_Idle; + } + + /* Send nak at the last receive byte. */ + if (handle->transfer.dataSize == 1) + { + FLEXIO_I2C_MasterEnableAck(base, false); + while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])))) + { + } + FLEXIO_I2C_MasterStop(base); + } + } + } + else if (statusFlags & kFLEXIO_I2C_TxEmptyFlag) + { + if (handle->transfer.dataSize > 1) + { + FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); + } + } + else + { + } + break; + + default: + break; + } + + return kStatus_Success; +} + +static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + status_t status) +{ + FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable); + + if (handle->completionCallback) + { + handle->completionCallback(base, handle, status, handle->userData); + } +} + +/*! + * brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C + * hardware configuration. + * + * Example + code + FLEXIO_I2C_Type base = { + .flexioBase = FLEXIO, + .SDAPinIndex = 0, + .SCLPinIndex = 1, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_i2c_master_config_t config = { + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 100000 + }; + FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz); + endcode + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param masterConfig Pointer to flexio_i2c_master_config_t structure. + * param srcClock_Hz FlexIO source clock in Hz. + * retval kStatus_Success Initialization successful + * retval kStatus_InvalidArgument The source clock exceed upper range limitation +*/ +status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(base && masterConfig); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t controlVal = 0; + uint16_t timerDiv = 0; + status_t result = kStatus_Success; + + memset(&shifterConfig, 0, sizeof(shifterConfig)); + memset(&timerConfig, 0, sizeof(timerConfig)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate flexio clock. */ + CLOCK_EnableClock(s_flexioClocks[FLEXIO_I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[1]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection; + shifterConfig.pinSelect = base->SDAPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveLow; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /* 2. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[1]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->SDAPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /*3. Configure the timer 0 for generating bit clock. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection; + timerConfig.pinSelect = base->SCLPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1. */ + timerDiv = (srcClock_Hz / masterConfig->baudRate_Bps) / 2 - 1; + + if (timerDiv > 0xFFU) + { + result = kStatus_InvalidArgument; + return result; + } + + timerConfig.timerCompare = timerDiv; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); + + /* 4. Configure the timer 1 for controlling shifters. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->SCLPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerCompare; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + /* Set TIMCMP[15:0] = (number of bits x 2) - 1. */ + timerConfig.timerCompare = 8 * 2 - 1; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); + + /* Configure FLEXIO I2C Master. */ + controlVal = base->flexioBase->CTRL; + controlVal &= + ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + controlVal |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster)); + if (!masterConfig->enableInDoze) + { + controlVal |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->flexioBase->CTRL = controlVal; + return result; +} + +/*! + * brief De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master + * shifer and timer config, module can't work unless the FLEXIO_I2C_MasterInit is called. + * + * param base pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base) +{ + base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[0]); + base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[1]); + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1U << base->timerIndex[0]); + base->flexioBase->TIMSTAT = (1U << base->timerIndex[1]); +} + +/*! + * brief Gets the default configuration to configure the FlexIO module. The configuration + * can be used directly for calling the FLEXIO_I2C_MasterInit(). + * + * Example: + code + flexio_i2c_master_config_t config; + FLEXIO_I2C_MasterGetDefaultConfig(&config); + endcode + * param masterConfig Pointer to flexio_i2c_master_config_t structure. +*/ +void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig) +{ + assert(masterConfig); + + /* Initializes the configure structure to zero. */ + memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->enableMaster = true; + masterConfig->enableInDoze = false; + masterConfig->enableInDebug = true; + masterConfig->enableFastAccess = false; + + /* Default baud rate at 100kbps. */ + masterConfig->baudRate_Bps = 100000U; +} + +/*! + * brief Gets the FlexIO I2C master status flags. + * + * param base Pointer to FLEXIO_I2C_Type structure + * return Status flag, use status flag to AND #_flexio_i2c_master_status_flags can get the related status. + */ + +uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base) +{ + uint32_t status = 0; + + status = + ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]); + status |= + (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 1U); + status |= + (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 2U); + + return status; +} + +/*! + * brief Clears the FlexIO I2C master status flags. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param mask Status flag. + * The parameter can be any combination of the following values: + * arg kFLEXIO_I2C_RxFullFlag + * arg kFLEXIO_I2C_ReceiveNakFlag + */ + +void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_I2C_TxEmptyFlag) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]); + } + + if (mask & kFLEXIO_I2C_RxFullFlag) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]); + } + + if (mask & kFLEXIO_I2C_ReceiveNakFlag) + { + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +/*! + * brief Enables the FlexIO i2c master interrupt requests. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param mask Interrupt source. + * Currently only one interrupt request source: + * arg kFLEXIO_I2C_TransferCompleteInterruptEnable + */ +void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); + } + if (mask & kFLEXIO_I2C_RxFullInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +/*! + * brief Disables the FlexIO I2C master interrupt requests. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param mask Interrupt source. + */ +void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); + } + if (mask & kFLEXIO_I2C_RxFullInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +/*! + * brief Sets the FlexIO I2C master transfer baudrate. + * + * param base Pointer to FLEXIO_I2C_Type structure + * param baudRate_Bps the baud rate value in HZ + * param srcClock_Hz source clock in HZ + */ +void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; + FLEXIO_Type *flexioBase = base->flexioBase; + + /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/ + timerDiv = srcClock_Hz / baudRate_Bps; + timerDiv = timerDiv / 2 - 1U; + + timerCmp = flexioBase->TIMCMP[base->timerIndex[0]]; + timerCmp &= 0xFF00; + timerCmp |= timerDiv; + + flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; +} + +/*! + * brief Sets the number of bytes to be transferred from a start signal to a stop signal. + * + * note Call this API before a transfer begins because the timer generates a number of clocks according + * to the number of bytes that need to be transferred. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param count Number of bytes need to be transferred from a start signal to a re-start/stop signal + * retval kStatus_Success Successfully configured the count. + * retval kStatus_InvalidArgument Input argument is invalid. + */ +status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count) +{ + if (count > 14U) + { + return kStatus_InvalidArgument; + } + + uint16_t timerCmp = 0; + uint32_t timerConfig = 0; + FLEXIO_Type *flexioBase = base->flexioBase; + + timerCmp = flexioBase->TIMCMP[base->timerIndex[0]]; + timerCmp &= 0x00FFU; + timerCmp |= (count * 18 + 1U) << 8U; + flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; + timerConfig = flexioBase->TIMCFG[base->timerIndex[0]]; + timerConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK; + timerConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare); + flexioBase->TIMCFG[base->timerIndex[0]] = timerConfig; + + return kStatus_Success; +} + +/*! + * brief Sends START + 7-bit address to the bus. + * + * note This API should be called when the transfer configuration is ready to send a START signal + * and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address + * is put into the data register but the address transfer is not finished on the bus. Ensure that + * the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API. + * param base Pointer to FLEXIO_I2C_Type structure. + * param address 7-bit address. + * param direction transfer direction. + * This parameter is one of the values in flexio_i2c_direction_t: + * arg kFLEXIO_I2C_Write: Transmit + * arg kFLEXIO_I2C_Read: Receive + */ + +void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction) +{ + uint32_t data; + + data = ((uint32_t)address) << 1U | ((direction == kFLEXIO_I2C_Read) ? 1U : 0U); + + FLEXIO_I2C_MasterWriteByte(base, data); +} + +/*! + * brief Sends the repeated start signal on the bus. + * + * param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base) +{ + /* Prepare for RESTART condition, no stop.*/ + FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); +} + +/*! + * brief Sends the stop signal on the bus. + * + * param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base) +{ + /* Prepare normal stop. */ + FLEXIO_I2C_MasterSetTransferCount(base, 0x0U); + FLEXIO_I2C_MasterWriteByte(base, 0x0U); +} + +/*! + * brief Sends the stop signal when transfer is still on-going. + * + * param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base) +{ + uint32_t tmpConfig; + + /* Prepare abort stop. */ + tmpConfig = base->flexioBase->TIMCFG[base->timerIndex[0]]; + tmpConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK; + tmpConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnPinBothEdge); + base->flexioBase->TIMCFG[base->timerIndex[0]] = tmpConfig; +} + +/*! + * brief Configures the sent ACK/NAK for the following byte. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param enable True to configure send ACK, false configure to send NAK. + */ +void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable) +{ + uint32_t tmpConfig = 0; + + tmpConfig = base->flexioBase->SHIFTCFG[base->shifterIndex[0]]; + tmpConfig &= ~FLEXIO_SHIFTCFG_SSTOP_MASK; + if (enable) + { + tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitLow); + } + else + { + tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitHigh); + } + base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = tmpConfig; +} + +/*! + * brief Sends a buffer of data in bytes. + * + * note This function blocks via polling until all bytes have been sent. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param txBuff The data bytes to send. + * param txSize The number of data bytes to send. + * retval kStatus_Success Successfully write data. + * retval kStatus_FLEXIO_I2C_Nak Receive NAK during writing data. + */ +status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize) +{ + assert(txBuff); + assert(txSize); + + uint32_t status; + + while (txSize--) + { + FLEXIO_I2C_MasterWriteByte(base, *txBuff++); + + /* Wait until data transfer complete. */ + while (!((status = FLEXIO_I2C_MasterGetStatusFlags(base)) & kFLEXIO_I2C_RxFullFlag)) + { + } + + if (status & kFLEXIO_I2C_ReceiveNakFlag) + { + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); + return kStatus_FLEXIO_I2C_Nak; + } + } + return kStatus_Success; +} + +/*! + * brief Receives a buffer of bytes. + * + * note This function blocks via polling until all bytes have been received. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param rxBuff The buffer to store the received bytes. + * param rxSize The number of data bytes to be received. + */ +void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize) +{ + assert(rxBuff); + assert(rxSize); + + while (rxSize--) + { + /* Wait until data transfer complete. */ + while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag)) + { + } + + *rxBuff++ = FLEXIO_I2C_MasterReadByte(base); + } +} + +/*! + * brief Performs a master polling transfer on the I2C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to receiving NAK. + * + * param base pointer to FLEXIO_I2C_Type structure. + * param xfer pointer to flexio_i2c_master_transfer_t structure. + * return status of status_t. + */ +status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer) +{ + assert(xfer); + + flexio_i2c_master_handle_t tmpHandle; + uint32_t statusFlags; + uint32_t result = kStatus_Success; + + /* Zero the handle. */ + memset(&tmpHandle, 0, sizeof(tmpHandle)); + + /* Set up transfer machine. */ + FLEXIO_I2C_MasterTransferInitStateMachine(base, &tmpHandle, xfer); + + do + { + /* Wait either tx empty or rx full flag is asserted. */ + while (!((statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base)) & + (kFLEXIO_I2C_TxEmptyFlag | kFLEXIO_I2C_RxFullFlag))) + { + } + FLEXIO_ClearTimerStatusFlags(base->flexioBase, ((1 << base->timerIndex[0]) | (1 << base->timerIndex[1]))); + result = FLEXIO_I2C_MasterTransferRunStateMachine(base, &tmpHandle, statusFlags); + + } while ((tmpHandle.state != kFLEXIO_I2C_Idle) && (result == kStatus_Success)); + + /* Timer disable on timer compare, wait until bit clock TSF set, which means timer disable and stop has been sent. */ + while(0U == (FLEXIO_GetTimerStatusFlags(base->flexioBase) & (1 << base->timerIndex[0]))) + { + } + + return result; +} + +/*! + * brief Initializes the I2C handle which is used in transactional functions. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param handle Pointer to flexio_i2c_master_handle_t structure to store the transfer state. + * param callback Pointer to user callback function. + * param userData User param passed to the callback function. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/isr table out of range. + */ +status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Register callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Enable interrupt in NVIC. */ + EnableIRQ(flexio_irqs[FLEXIO_I2C_GetInstance(base)]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2C_MasterTransferHandleIRQ); +} + +/*! + * brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * note The API returns immediately after the transfer initiates. + * Call FLEXIO_I2C_MasterGetTransferCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer + * is finished. + * + * param base Pointer to FLEXIO_I2C_Type structure + * param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * param xfer pointer to flexio_i2c_master_transfer_t structure + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_FLEXIO_I2C_Busy FlexIO I2C is not idle, is running another transfer. + */ +status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + if (handle->state != kFLEXIO_I2C_Idle) + { + return kStatus_FLEXIO_I2C_Busy; + } + else + { + /* Set up transfer machine. */ + FLEXIO_I2C_MasterTransferInitStateMachine(base, handle, xfer); + + /* Enable both tx empty and rxfull interrupt. */ + FLEXIO_I2C_MasterEnableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable); + + return kStatus_Success; + } +} + +/*! + * brief Aborts an interrupt non-blocking transfer early. + * + * note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base Pointer to FLEXIO_I2C_Type structure + * param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state + */ +void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle) +{ + assert(handle); + + /* Disable interrupts. */ + FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable); + + /* Reset to idle state. */ + handle->state = kFLEXIO_I2C_Idle; +} + +/*! + * brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count) +{ + if (!count) + { + return kStatus_InvalidArgument; + } + + *count = handle->transferSize - handle->transfer.dataSize; + + return kStatus_Success; +} + +/*! + * brief Master interrupt handler. + * + * param i2cType Pointer to FLEXIO_I2C_Type structure + * param i2cHandle Pointer to flexio_i2c_master_transfer_t structure + */ +void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle) +{ + FLEXIO_I2C_Type *base = (FLEXIO_I2C_Type *)i2cType; + flexio_i2c_master_handle_t *handle = (flexio_i2c_master_handle_t *)i2cHandle; + uint32_t statusFlags; + status_t result; + + statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base); + + result = FLEXIO_I2C_MasterTransferRunStateMachine(base, handle, statusFlags); + + if (handle->state == kFLEXIO_I2C_Idle) + { + FLEXIO_I2C_MasterTransferComplete(base, handle, result); + } +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_i2c_master.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_i2c_master.h new file mode 100644 index 0000000000..c55d476a80 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_i2c_master.h @@ -0,0 +1,461 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_FLEXIO_I2C_MASTER_H_ +#define _FSL_FLEXIO_I2C_MASTER_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_i2c_master + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO I2C master driver version 2.1.7. */ +#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 1, 7)) +/*@}*/ + +/*! @brief FlexIO I2C transfer status*/ +enum _flexio_i2c_status +{ + kStatus_FLEXIO_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 0), /*!< I2C is busy doing transfer. */ + kStatus_FLEXIO_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 1), /*!< I2C is busy doing transfer. */ + kStatus_FLEXIO_I2C_Nak = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 2), /*!< NAK received during transfer. */ +}; + +/*! @brief Define FlexIO I2C master interrupt mask. */ +enum _flexio_i2c_master_interrupt +{ + kFLEXIO_I2C_TxEmptyInterruptEnable = 0x1U, /*!< Tx buffer empty interrupt enable. */ + kFLEXIO_I2C_RxFullInterruptEnable = 0x2U, /*!< Rx buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO I2C master status mask. */ +enum _flexio_i2c_master_status_flags +{ + kFLEXIO_I2C_TxEmptyFlag = 0x1U, /*!< Tx shifter empty flag. */ + kFLEXIO_I2C_RxFullFlag = 0x2U, /*!< Rx shifter full/Transfer complete flag. */ + kFLEXIO_I2C_ReceiveNakFlag = 0x4U, /*!< Receive NAK flag. */ +}; + +/*! @brief Direction of master transfer.*/ +typedef enum _flexio_i2c_direction +{ + kFLEXIO_I2C_Write = 0x0U, /*!< Master send to slave. */ + kFLEXIO_I2C_Read = 0x1U, /*!< Master receive from slave. */ +} flexio_i2c_direction_t; + +/*! @brief Define FlexIO I2C master access structure typedef. */ +typedef struct _flexio_i2c_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ + uint8_t SDAPinIndex; /*!< Pin select for I2C SDA. */ + uint8_t SCLPinIndex; /*!< Pin select for I2C SCL. */ + uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO I2C. */ + uint8_t timerIndex[2]; /*!< Timer index used in FlexIO I2C. */ +} FLEXIO_I2C_Type; + +/*! @brief Define FlexIO I2C master user configuration structure. */ +typedef struct _flexio_i2c_master_config +{ + bool enableMaster; /*!< Enables the FlexIO I2C peripheral at initialization time. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires + the FlexIO clock to be at least twice the frequency of the bus clock. */ + uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ +} flexio_i2c_master_config_t; + +/*! @brief Define FlexIO I2C master transfer structure. */ +typedef struct _flexio_i2c_master_transfer +{ + uint32_t flags; /*!< Transfer flag which controls the transfer, reserved for FlexIO I2C. */ + uint8_t slaveAddress; /*!< 7-bit slave address. */ + flexio_i2c_direction_t direction; /*!< Transfer direction, read or write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + uint8_t subaddressSize; /*!< Size of command buffer. */ + uint8_t volatile *data; /*!< Transfer buffer. */ + volatile size_t dataSize; /*!< Transfer size. */ +} flexio_i2c_master_transfer_t; + +/*! @brief FlexIO I2C master handle typedef. */ +typedef struct _flexio_i2c_master_handle flexio_i2c_master_handle_t; + +/*! @brief FlexIO I2C master transfer callback typedef. */ +typedef void (*flexio_i2c_master_transfer_callback_t)(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FlexIO I2C master handle structure. */ +struct _flexio_i2c_master_handle +{ + flexio_i2c_master_transfer_t transfer; /*!< FlexIO I2C master transfer copy. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t state; /*!< Transfer state maintained during transfer. */ + flexio_i2c_master_transfer_callback_t completionCallback; /*!< Callback function called at transfer event. */ + /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback function. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C + * hardware configuration. + * + * Example + @code + FLEXIO_I2C_Type base = { + .flexioBase = FLEXIO, + .SDAPinIndex = 0, + .SCLPinIndex = 1, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_i2c_master_config_t config = { + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 100000 + }; + FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz); + @endcode + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param masterConfig Pointer to flexio_i2c_master_config_t structure. + * @param srcClock_Hz FlexIO source clock in Hz. + * @retval kStatus_Success Initialization successful + * @retval kStatus_InvalidArgument The source clock exceed upper range limitation +*/ +status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master + * shifer and timer config, module can't work unless the FLEXIO_I2C_MasterInit is called. + * + * @param base pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO module. The configuration + * can be used directly for calling the FLEXIO_I2C_MasterInit(). + * + * Example: + @code + flexio_i2c_master_config_t config; + FLEXIO_I2C_MasterGetDefaultConfig(&config); + @endcode + * @param masterConfig Pointer to flexio_i2c_master_config_t structure. +*/ +void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig); + +/*! + * @brief Enables/disables the FlexIO module operation. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param enable Pass true to enable module, false does not have any effect. + */ +static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable) +{ + if (enable) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexIO I2C master status flags. + * + * @param base Pointer to FLEXIO_I2C_Type structure + * @return Status flag, use status flag to AND #_flexio_i2c_master_status_flags can get the related status. + */ + +uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base); + +/*! + * @brief Clears the FlexIO I2C master status flags. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param mask Status flag. + * The parameter can be any combination of the following values: + * @arg kFLEXIO_I2C_RxFullFlag + * @arg kFLEXIO_I2C_ReceiveNakFlag + */ + +void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO i2c master interrupt requests. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param mask Interrupt source. + * Currently only one interrupt request source: + * @arg kFLEXIO_I2C_TransferCompleteInterruptEnable + */ +void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO I2C master interrupt requests. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param mask Interrupt source. + */ +void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Sets the FlexIO I2C master transfer baudrate. + * + * @param base Pointer to FLEXIO_I2C_Type structure + * @param baudRate_Bps the baud rate value in HZ + * @param srcClock_Hz source clock in HZ + */ +void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sends START + 7-bit address to the bus. + * + * @note This API should be called when the transfer configuration is ready to send a START signal + * and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address + * is put into the data register but the address transfer is not finished on the bus. Ensure that + * the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API. + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param address 7-bit address. + * @param direction transfer direction. + * This parameter is one of the values in flexio_i2c_direction_t: + * @arg kFLEXIO_I2C_Write: Transmit + * @arg kFLEXIO_I2C_Read: Receive + */ + +void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction); + +/*! + * @brief Sends the stop signal on the bus. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base); + +/*! + * @brief Sends the repeated start signal on the bus. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base); + +/*! + * @brief Sends the stop signal when transfer is still on-going. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base); + +/*! + * @brief Configures the sent ACK/NAK for the following byte. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param enable True to configure send ACK, false configure to send NAK. + */ +void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable); + +/*! + * @brief Sets the number of bytes to be transferred from a start signal to a stop signal. + * + * @note Call this API before a transfer begins because the timer generates a number of clocks according + * to the number of bytes that need to be transferred. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param count Number of bytes need to be transferred from a start signal to a re-start/stop signal + * @retval kStatus_Success Successfully configured the count. + * @retval kStatus_InvalidArgument Input argument is invalid. + */ +status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count); + +/*! + * @brief Writes one byte of data to the I2C bus. + * + * @note This is a non-blocking API, which returns directly after the data is put into the + * data register but the data transfer is not finished on the bus. Ensure that + * the TxEmptyFlag is asserted before calling this API. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param data a byte of data. + */ +static inline void FLEXIO_I2C_MasterWriteByte(FLEXIO_I2C_Type *base, uint32_t data) +{ + base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data; +} + +/*! + * @brief Reads one byte of data from the I2C bus. + * + * @note This is a non-blocking API, which returns directly after the data is read from the + * data register. Ensure that the data is ready in the register. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @return data byte read. + */ +static inline uint8_t FLEXIO_I2C_MasterReadByte(FLEXIO_I2C_Type *base) +{ + return base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]; +} + +/*! + * @brief Sends a buffer of data in bytes. + * + * @note This function blocks via polling until all bytes have been sent. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param txBuff The data bytes to send. + * @param txSize The number of data bytes to send. + * @retval kStatus_Success Successfully write data. + * @retval kStatus_FLEXIO_I2C_Nak Receive NAK during writing data. + */ +status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks via polling until all bytes have been received. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param rxBuff The buffer to store the received bytes. + * @param rxSize The number of data bytes to be received. + */ +void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to receiving NAK. + * + * @param base pointer to FLEXIO_I2C_Type structure. + * @param xfer pointer to flexio_i2c_master_transfer_t structure. + * @return status of status_t. + */ +status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer); +/*@}*/ + +/*Transactional APIs*/ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param handle Pointer to flexio_i2c_master_handle_t structure to store the transfer state. + * @param callback Pointer to user callback function. + * @param userData User param passed to the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/isr table out of range. + */ +status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * @note The API returns immediately after the transfer initiates. + * Call FLEXIO_I2C_MasterGetTransferCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer + * is finished. + * + * @param base Pointer to FLEXIO_I2C_Type structure + * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param xfer pointer to flexio_i2c_master_transfer_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_FLEXIO_I2C_Busy FlexIO I2C is not idle, is running another transfer. + */ +status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer); + +/*! + * @brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an interrupt non-blocking transfer early. + * + * @note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base Pointer to FLEXIO_I2C_Type structure + * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state + */ +void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle); + +/*! + * @brief Master interrupt handler. + * + * @param i2cType Pointer to FLEXIO_I2C_Type structure + * @param i2cHandle Pointer to flexio_i2c_master_transfer_t structure + */ +void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /*_FSL_FLEXIO_I2C_MASTER_H_*/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_i2s.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_i2s.c new file mode 100644 index 0000000000..acf2ea32a7 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_i2s.c @@ -0,0 +1,850 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_i2s.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_i2s" +#endif + +/******************************************************************************* + * Definitations + ******************************************************************************/ +enum _sai_transfer_state +{ + kFLEXIO_I2S_Busy = 0x0U, /*!< FLEXIO_I2S is busy */ + kFLEXIO_I2S_Idle, /*!< Transfer is done. */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Receive a piece of data in non-blocking way. + * + * @param base FLEXIO I2S base pointer + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size); + +/*! + * @brief sends a piece of data in non-blocking way. + * + * @param base FLEXIO I2S base pointer + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size); +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t FLEXIO_I2S_GetInstance(FLEXIO_I2S_Type *base) +{ + return FLEXIO_GetInstance(base->flexioBase); +} + +static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size) +{ + uint32_t i = 0; + uint8_t j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + uint32_t temp = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + for (j = 0; j < bytesPerWord; j++) + { + temp = (uint32_t)(*txData); + data |= (temp << (8U * j)); + txData++; + } + base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = data << (32U - bitWidth); + data = 0; + } +} + +static void FLEXIO_I2S_ReadNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size) +{ + uint32_t i = 0; + uint8_t j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + data = (base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex]); + for (j = 0; j < bytesPerWord; j++) + { + *rxData = (data >> (8U * j)) & 0xFF; + rxData++; + } + } +} + +/*! + * brief Initializes the FlexIO I2S. + * + * This API configures FlexIO pins and shifter to I2S and configures the FlexIO I2S with a configuration structure. + * The configuration structure can be filled by the user, or be set with default values by + * FLEXIO_I2S_GetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the FlexIO I2S driver. Otherwise, any access to the FlexIO I2S module can cause hard fault + * because the clock is not enabled. + * + * param base FlexIO I2S base pointer + * param config FlexIO I2S configure structure. + */ +void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config) +{ + assert(base && config); + + flexio_shifter_config_t shifterConfig = {0}; + flexio_timer_config_t timerConfig = {0}; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate flexio clock. */ + CLOCK_EnableClock(s_flexioClocks[FLEXIO_I2S_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* reset Flexio */ + FLEXIO_Reset(base->flexioBase); + + /* Set shifter for I2S Tx data */ + shifterConfig.timerSelect = base->bclkTimerIndex; + shifterConfig.pinSelect = base->txPinIndex; + shifterConfig.timerPolarity = config->txTimerPolarity; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinPolarity = config->txPinPolarity; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + if (config->masterSlave == kFLEXIO_I2S_Master) + { + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; + } + else + { + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->txShifterIndex, &shifterConfig); + + /* Set shifter for I2S Rx Data */ + shifterConfig.timerSelect = base->bclkTimerIndex; + shifterConfig.pinSelect = base->rxPinIndex; + shifterConfig.timerPolarity = config->rxTimerPolarity; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinPolarity = config->rxPinPolarity; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + + FLEXIO_SetShifterConfig(base->flexioBase, base->rxShifterIndex, &shifterConfig); + + /* Set Timer to I2S frame sync */ + if (config->masterSlave == kFLEXIO_I2S_Master) + { + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->txPinIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinSelect = base->fsPinIndex; + timerConfig.pinPolarity = config->fsPinPolarity; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableNever; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + } + else + { + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->bclkPinIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->fsPinIndex; + timerConfig.pinPolarity = config->fsPinPolarity; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + } + FLEXIO_SetTimerConfig(base->flexioBase, base->fsTimerIndex, &timerConfig); + + /* Set Timer to I2S bit clock */ + if (config->masterSlave == kFLEXIO_I2S_Master) + { + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinSelect = base->bclkPinIndex; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinPolarity = config->bclkPinPolarity; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableNever; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + } + else + { + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->fsTimerIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinSelect = base->bclkPinIndex; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinPolarity = config->bclkPinPolarity; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompareTriggerLow; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + } + FLEXIO_SetTimerConfig(base->flexioBase, base->bclkTimerIndex, &timerConfig); + + /* If enable flexio I2S */ + if (config->enableI2S) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } + else + { + base->flexioBase->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/*! + * brief Sets the FlexIO I2S configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in FLEXIO_I2S_Init(). + * Users may use the initialized structure unchanged in FLEXIO_I2S_Init() or modify + * some fields of the structure before calling FLEXIO_I2S_Init(). + * + * param config pointer to master configuration structure + */ +void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config) +{ + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->masterSlave = kFLEXIO_I2S_Master; + config->enableI2S = true; + config->txPinPolarity = kFLEXIO_PinActiveHigh; + config->rxPinPolarity = kFLEXIO_PinActiveHigh; + config->bclkPinPolarity = kFLEXIO_PinActiveHigh; + config->fsPinPolarity = kFLEXIO_PinActiveLow; + config->txTimerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + config->rxTimerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; +} + +/*! + * brief De-initializes the FlexIO I2S. + * + * Calling this API resets the FlexIO I2S shifter and timer config. After calling this API, + * call the FLEXO_I2S_Init to use the FlexIO I2S module. + * + * param base FlexIO I2S base pointer + */ +void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base) +{ + base->flexioBase->SHIFTCFG[base->txShifterIndex] = 0; + base->flexioBase->SHIFTCTL[base->txShifterIndex] = 0; + base->flexioBase->SHIFTCFG[base->rxShifterIndex] = 0; + base->flexioBase->SHIFTCTL[base->rxShifterIndex] = 0; + base->flexioBase->TIMCFG[base->fsTimerIndex] = 0; + base->flexioBase->TIMCMP[base->fsTimerIndex] = 0; + base->flexioBase->TIMCTL[base->fsTimerIndex] = 0; + base->flexioBase->TIMCFG[base->bclkTimerIndex] = 0; + base->flexioBase->TIMCMP[base->bclkTimerIndex] = 0; + base->flexioBase->TIMCTL[base->bclkTimerIndex] = 0; +} + +/*! + * brief Enables the FlexIO I2S interrupt. + * + * This function enables the FlexIO UART interrupt. + * + * param base Pointer to FLEXIO_I2S_Type structure + * param mask interrupt source + */ +void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->txShifterIndex); + } + if (mask & kFLEXIO_I2S_RxDataRegFullInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->rxShifterIndex); + } +} + +/*! + * brief Gets the FlexIO I2S status flags. + * + * param base Pointer to FLEXIO_I2S_Type structure + * return Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags. + */ +uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base) +{ + uint32_t status = 0; + status = ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->txShifterIndex)) >> base->txShifterIndex); + status |= + (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->rxShifterIndex)) >> (base->rxShifterIndex)) + << 1U); + return status; +} + +/*! + * brief Disables the FlexIO I2S interrupt. + * + * This function enables the FlexIO UART interrupt. + * + * param base pointer to FLEXIO_I2S_Type structure + * param mask interrupt source + */ +void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_I2S_TxDataRegEmptyInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->txShifterIndex); + } + if (mask & kFLEXIO_I2S_RxDataRegFullInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->rxShifterIndex); + } +} + +/*! + * brief Configures the FlexIO I2S audio format in master mode. + * + * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data + * format to be transferred. + * + * param base Pointer to FLEXIO_I2S_Type structure + * param format Pointer to FlexIO I2S audio data format structure. + * param srcClock_Hz I2S master clock source frequency in Hz. + */ +void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz) +{ + uint32_t timDiv = srcClock_Hz / (format->sampleRate_Hz * format->bitWidth * 2U); + uint32_t bclkDiv = 0; + + /* Shall keep bclk and fs div an integer */ + if (timDiv % 2) + { + timDiv += 1U; + } + /* Set Frame sync timer cmp */ + base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * timDiv - 1U); + + /* Set bit clock timer cmp */ + bclkDiv = ((timDiv / 2U - 1U) | ((format->bitWidth * 2U - 1U) << 8U)); + base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(bclkDiv); +} + +/*! + * brief Configures the FlexIO I2S audio format in slave mode. + * + * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data + * format to be transferred. + * + * param base Pointer to FLEXIO_I2S_Type structure + * param format Pointer to FlexIO I2S audio data format structure. + */ +void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format) +{ + /* Set Frame sync timer cmp */ + base->flexioBase->TIMCMP[base->fsTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * 4U - 3U); + + /* Set bit clock timer cmp */ + base->flexioBase->TIMCMP[base->bclkTimerIndex] = FLEXIO_TIMCMP_CMP(format->bitWidth * 2U - 1U); +} + +/*! + * brief Sends data using a blocking method. + * + * note This function blocks via polling until data is ready to be sent. + * + * param base FlexIO I2S base pointer. + * param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * param txData Pointer to the data to be written. + * param size Bytes to be written. + */ +void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size) +{ + uint32_t i = 0; + uint8_t bytesPerWord = bitWidth / 8U; + + for (i = 0; i < size / bytesPerWord; i++) + { + /* Wait until it can write data */ + while ((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) == 0) + { + } + + FLEXIO_I2S_WriteNonBlocking(base, bitWidth, txData, bytesPerWord); + txData += bytesPerWord; + } + + /* Wait until the last data is sent */ + while ((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) == 0) + { + } +} + +/*! + * brief Receives a piece of data using a blocking method. + * + * note This function blocks via polling until data is ready to be sent. + * + * param base FlexIO I2S base pointer + * param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * param rxData Pointer to the data to be read. + * param size Bytes to be read. + */ +void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size) +{ + uint32_t i = 0; + uint8_t bytesPerWord = bitWidth / 8U; + + for (i = 0; i < size / bytesPerWord; i++) + { + /* Wait until data is received */ + while (!(FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->rxShifterIndex))) + { + } + + FLEXIO_I2S_ReadNonBlocking(base, bitWidth, rxData, bytesPerWord); + rxData += bytesPerWord; + } +} + +/*! + * brief Initializes the FlexIO I2S handle. + * + * This function initializes the FlexIO I2S handle which can be used for other + * FlexIO I2S transactional APIs. Call this API once to get the + * initialized handle. + * + * param base Pointer to FLEXIO_I2S_Type structure + * param handle Pointer to flexio_i2s_handle_t structure to store the transfer state. + * param callback FlexIO I2S callback function, which is called while finished a block. + * param userData User parameter for the FlexIO I2S callback. + */ +void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_callback_t callback, + void *userData) +{ + assert(handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Store callback and user data. */ + handle->callback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2S_TransferTxHandleIRQ); + + /* Set the TX/RX state. */ + handle->state = kFLEXIO_I2S_Idle; + + /* Enable interrupt in NVIC. */ + EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]); +} + +/*! + * brief Initializes the FlexIO I2S receive handle. + * + * This function initializes the FlexIO I2S handle which can be used for other + * FlexIO I2S transactional APIs. Call this API once to get the + * initialized handle. + * + * param base Pointer to FLEXIO_I2S_Type structure. + * param handle Pointer to flexio_i2s_handle_t structure to store the transfer state. + * param callback FlexIO I2S callback function, which is called while finished a block. + * param userData User parameter for the FlexIO I2S callback. + */ +void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_callback_t callback, + void *userData) +{ + assert(handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Store callback and user data. */ + handle->callback = callback; + handle->userData = userData; + + /* Save the context in global variables to support the double weak mechanism. */ + FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2S_TransferRxHandleIRQ); + + /* Set the TX/RX state. */ + handle->state = kFLEXIO_I2S_Idle; + + /* Enable interrupt in NVIC. */ + EnableIRQ(flexio_irqs[FLEXIO_I2S_GetInstance(base)]); +} + +/*! + * brief Configures the FlexIO I2S audio format. + * + * Audio format can be changed at run-time of FlexIO I2S. This function configures the sample rate and audio data + * format to be transferred. + * + * param base Pointer to FLEXIO_I2S_Type structure. + * param handle FlexIO I2S handle pointer. + * param format Pointer to audio data format structure. + * param srcClock_Hz FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode. + */ +void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_format_t *format, + uint32_t srcClock_Hz) +{ + assert(handle && format); + + /* Set the bitWidth to handle */ + handle->bitWidth = format->bitWidth; + + /* Set sample rate */ + if (srcClock_Hz != 0) + { + /* It is master */ + FLEXIO_I2S_MasterSetFormat(base, format, srcClock_Hz); + } + else + { + FLEXIO_I2S_SlaveSetFormat(base, format); + } +} + +/*! + * brief Performs an interrupt non-blocking send transfer on FlexIO I2S. + * + * note The API returns immediately after transfer initiates. + * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status and check whether + * the transfer is finished. If the return status is 0, the transfer is finished. + * + * param base Pointer to FLEXIO_I2S_Type structure. + * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + * param xfer Pointer to flexio_i2s_transfer_t structure + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_FLEXIO_I2S_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->queue[handle->queueUser].data) + { + return kStatus_FLEXIO_I2S_QueueFull; + } + if ((xfer->dataSize == 0) || (xfer->data == NULL)) + { + return kStatus_InvalidArgument; + } + + /* Add into queue */ + handle->queue[handle->queueUser].data = xfer->data; + handle->queue[handle->queueUser].dataSize = xfer->dataSize; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + + /* Set the state to busy */ + handle->state = kFLEXIO_I2S_Busy; + + FLEXIO_I2S_EnableInterrupts(base, kFLEXIO_I2S_TxDataRegEmptyInterruptEnable); + + /* Enable Tx transfer */ + FLEXIO_I2S_Enable(base, true); + + return kStatus_Success; +} + +/*! + * brief Performs an interrupt non-blocking receive transfer on FlexIO I2S. + * + * note The API returns immediately after transfer initiates. + * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status to check whether + * the transfer is finished. If the return status is 0, the transfer is finished. + * + * param base Pointer to FLEXIO_I2S_Type structure. + * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + * param xfer Pointer to flexio_i2s_transfer_t structure + * retval kStatus_Success Successfully start the data receive. + * retval kStatus_FLEXIO_I2S_RxBusy Previous receive still not finished. + * retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->queue[handle->queueUser].data) + { + return kStatus_FLEXIO_I2S_QueueFull; + } + + if ((xfer->dataSize == 0) || (xfer->data == NULL)) + { + return kStatus_InvalidArgument; + } + + /* Add into queue */ + handle->queue[handle->queueUser].data = xfer->data; + handle->queue[handle->queueUser].dataSize = xfer->dataSize; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + + /* Set state to busy */ + handle->state = kFLEXIO_I2S_Busy; + + /* Enable interrupt */ + FLEXIO_I2S_EnableInterrupts(base, kFLEXIO_I2S_RxDataRegFullInterruptEnable); + + /* Enable Rx transfer */ + FLEXIO_I2S_Enable(base, true); + + return kStatus_Success; +} + +/*! + * brief Aborts the current send. + * + * note This API can be called at any time when interrupt non-blocking transfer initiates + * to abort the transfer in a early time. + * + * param base Pointer to FLEXIO_I2S_Type structure. + * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + */ +void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle) +{ + assert(handle); + + /* Stop Tx transfer and disable interrupt */ + FLEXIO_I2S_DisableInterrupts(base, kFLEXIO_I2S_TxDataRegEmptyInterruptEnable); + handle->state = kFLEXIO_I2S_Idle; + + /* Clear the queue */ + memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +/*! + * brief Aborts the current receive. + * + * note This API can be called at any time when interrupt non-blocking transfer initiates + * to abort the transfer in a early time. + * + * param base Pointer to FLEXIO_I2S_Type structure. + * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + */ +void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle) +{ + assert(handle); + + /* Stop rx transfer and disable interrupt */ + FLEXIO_I2S_DisableInterrupts(base, kFLEXIO_I2S_RxDataRegFullInterruptEnable); + handle->state = kFLEXIO_I2S_Idle; + + /* Clear the queue */ + memset(handle->queue, 0, sizeof(flexio_i2s_transfer_t) * FLEXIO_I2S_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +/*! + * brief Gets the remaining bytes to be sent. + * + * param base Pointer to FLEXIO_I2S_Type structure. + * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + * param count Bytes sent. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kFLEXIO_I2S_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->queue[handle->queueDriver].dataSize); + } + + return status; +} + +/*! + * brief Gets the remaining bytes to be received. + * + * param base Pointer to FLEXIO_I2S_Type structure. + * param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + * return count Bytes received. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kFLEXIO_I2S_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->queue[handle->queueDriver].dataSize); + } + + return status; +} + +/*! + * brief Tx interrupt handler. + * + * param i2sBase Pointer to FLEXIO_I2S_Type structure. + * param i2sHandle Pointer to flexio_i2s_handle_t structure + */ +void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle) +{ + assert(i2sHandle); + + flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle; + FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase; + uint8_t *buffer = handle->queue[handle->queueDriver].data; + uint8_t dataSize = handle->bitWidth / 8U; + + /* Handle error */ + if (FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->txShifterIndex)) + { + FLEXIO_ClearShifterErrorFlags(base->flexioBase, (1U << base->txShifterIndex)); + } + /* Handle transfer */ + if (((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_TxDataRegEmptyFlag) != 0) && + (handle->queue[handle->queueDriver].data != NULL)) + { + FLEXIO_I2S_WriteNonBlocking(base, handle->bitWidth, buffer, dataSize); + + /* Update internal counter */ + handle->queue[handle->queueDriver].dataSize -= dataSize; + handle->queue[handle->queueDriver].data += dataSize; + } + + /* If finished a block, call the callback function */ + if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL)) + { + memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_Success, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->queue[handle->queueDriver].data == NULL) + { + FLEXIO_I2S_TransferAbortSend(base, handle); + } +} + +/*! + * brief Rx interrupt handler. + * + * param i2sBase Pointer to FLEXIO_I2S_Type structure. + * param i2sHandle Pointer to flexio_i2s_handle_t structure. + */ +void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle) +{ + assert(i2sHandle); + + flexio_i2s_handle_t *handle = (flexio_i2s_handle_t *)i2sHandle; + FLEXIO_I2S_Type *base = (FLEXIO_I2S_Type *)i2sBase; + uint8_t *buffer = handle->queue[handle->queueDriver].data; + uint8_t dataSize = handle->bitWidth / 8U; + + /* Handle transfer */ + if (((FLEXIO_I2S_GetStatusFlags(base) & kFLEXIO_I2S_RxDataRegFullFlag) != 0) && + (handle->queue[handle->queueDriver].data != NULL)) + { + FLEXIO_I2S_ReadNonBlocking(base, handle->bitWidth, buffer, dataSize); + + /* Update internal state */ + handle->queue[handle->queueDriver].dataSize -= dataSize; + handle->queue[handle->queueDriver].data += dataSize; + } + + /* If finished a block, call the callback function */ + if ((handle->queue[handle->queueDriver].dataSize == 0U) && (handle->queue[handle->queueDriver].data != NULL)) + { + memset(&handle->queue[handle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_Success, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->queue[handle->queueDriver].data == NULL) + { + FLEXIO_I2S_TransferAbortReceive(base, handle); + } +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_i2s.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_i2s.h new file mode 100644 index 0000000000..32e792596b --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_i2s.h @@ -0,0 +1,548 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_FLEXIO_I2S_H_ +#define _FSL_FLEXIO_I2S_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_i2s + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO I2S driver version 2.1.6. */ +#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 6)) +/*@}*/ + +/*! @brief FlexIO I2S transfer status */ +enum _flexio_i2s_status +{ + kStatus_FLEXIO_I2S_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 0), /*!< FlexIO I2S is in idle state */ + kStatus_FLEXIO_I2S_TxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 1), /*!< FlexIO I2S Tx is busy */ + kStatus_FLEXIO_I2S_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 2), /*!< FlexIO I2S Tx is busy */ + kStatus_FLEXIO_I2S_Error = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 3), /*!< FlexIO I2S error occurred */ + kStatus_FLEXIO_I2S_QueueFull = MAKE_STATUS(kStatusGroup_FLEXIO_I2S, 4), /*!< FlexIO I2S transfer queue is full. */ +}; + +/*! @brief Define FlexIO I2S access structure typedef */ +typedef struct _flexio_i2s_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer */ + uint8_t txPinIndex; /*!< Tx data pin index in FlexIO pins */ + uint8_t rxPinIndex; /*!< Rx data pin index */ + uint8_t bclkPinIndex; /*!< Bit clock pin index */ + uint8_t fsPinIndex; /*!< Frame sync pin index */ + uint8_t txShifterIndex; /*!< Tx data shifter index */ + uint8_t rxShifterIndex; /*!< Rx data shifter index */ + uint8_t bclkTimerIndex; /*!< Bit clock timer index */ + uint8_t fsTimerIndex; /*!< Frame sync timer index */ +} FLEXIO_I2S_Type; + +/*! @brief Master or slave mode */ +typedef enum _flexio_i2s_master_slave +{ + kFLEXIO_I2S_Master = 0x0U, /*!< Master mode */ + kFLEXIO_I2S_Slave = 0x1U /*!< Slave mode */ +} flexio_i2s_master_slave_t; + +/*! @brief Define FlexIO FlexIO I2S interrupt mask. */ +enum _flexio_i2s_interrupt_enable +{ + kFLEXIO_I2S_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ + kFLEXIO_I2S_RxDataRegFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO FlexIO I2S status mask. */ +enum _flexio_i2s_status_flags +{ + kFLEXIO_I2S_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ + kFLEXIO_I2S_RxDataRegFullFlag = 0x2U, /*!< Receive buffer full flag. */ +}; + +/*! @brief FlexIO I2S configure structure */ +typedef struct _flexio_i2s_config +{ + bool enableI2S; /*!< Enable FlexIO I2S */ + flexio_i2s_master_slave_t masterSlave; /*!< Master or slave */ + flexio_pin_polarity_t txPinPolarity; /*!< Tx data pin polarity, active high or low */ + flexio_pin_polarity_t rxPinPolarity; /*!< Rx data pin polarity */ + flexio_pin_polarity_t bclkPinPolarity; /*!< Bit clock pin polarity */ + flexio_pin_polarity_t fsPinPolarity; /*!< Frame sync pin polarity */ + flexio_shifter_timer_polarity_t txTimerPolarity; /*!< Tx data valid on bclk rising or falling edge */ + flexio_shifter_timer_polarity_t rxTimerPolarity; /*!< Rx data valid on bclk rising or falling edge */ +} flexio_i2s_config_t; + +/*! @brief FlexIO I2S audio format, FlexIO I2S only support the same format in Tx and Rx */ +typedef struct _flexio_i2s_format +{ + uint8_t bitWidth; /*!< Bit width of audio data, always 8/16/24/32 bits */ + uint32_t sampleRate_Hz; /*!< Sample rate of the audio data */ +} flexio_i2s_format_t; + +/*!@brief FlexIO I2S transfer queue size, user can refine it according to use case. */ +#define FLEXIO_I2S_XFER_QUEUE_SIZE (4) + +/*! @brief Audio sample rate */ +typedef enum _flexio_i2s_sample_rate +{ + kFLEXIO_I2S_SampleRate8KHz = 8000U, /*!< Sample rate 8000Hz */ + kFLEXIO_I2S_SampleRate11025Hz = 11025U, /*!< Sample rate 11025Hz */ + kFLEXIO_I2S_SampleRate12KHz = 12000U, /*!< Sample rate 12000Hz */ + kFLEXIO_I2S_SampleRate16KHz = 16000U, /*!< Sample rate 16000Hz */ + kFLEXIO_I2S_SampleRate22050Hz = 22050U, /*!< Sample rate 22050Hz */ + kFLEXIO_I2S_SampleRate24KHz = 24000U, /*!< Sample rate 24000Hz */ + kFLEXIO_I2S_SampleRate32KHz = 32000U, /*!< Sample rate 32000Hz */ + kFLEXIO_I2S_SampleRate44100Hz = 44100U, /*!< Sample rate 44100Hz */ + kFLEXIO_I2S_SampleRate48KHz = 48000U, /*!< Sample rate 48000Hz */ + kFLEXIO_I2S_SampleRate96KHz = 96000U /*!< Sample rate 96000Hz */ +} flexio_i2s_sample_rate_t; + +/*! @brief Audio word width */ +typedef enum _flexio_i2s_word_width +{ + kFLEXIO_I2S_WordWidth8bits = 8U, /*!< Audio data width 8 bits */ + kFLEXIO_I2S_WordWidth16bits = 16U, /*!< Audio data width 16 bits */ + kFLEXIO_I2S_WordWidth24bits = 24U, /*!< Audio data width 24 bits */ + kFLEXIO_I2S_WordWidth32bits = 32U /*!< Audio data width 32 bits */ +} flexio_i2s_word_width_t; + +/*! @brief Define FlexIO I2S transfer structure. */ +typedef struct _flexio_i2s_transfer +{ + uint8_t *data; /*!< Data buffer start pointer */ + size_t dataSize; /*!< Bytes to be transferred. */ +} flexio_i2s_transfer_t; + +typedef struct _flexio_i2s_handle flexio_i2s_handle_t; + +/*! @brief FlexIO I2S xfer callback prototype */ +typedef void (*flexio_i2s_callback_t)(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FlexIO I2S handle structure. */ +struct _flexio_i2s_handle +{ + uint32_t state; /*!< Internal state */ + flexio_i2s_callback_t callback; /*!< Callback function called at transfer event*/ + void *userData; /*!< Callback parameter passed to callback function*/ + uint8_t bitWidth; /*!< Bit width for transfer, 8/16/24/32bits */ + flexio_i2s_transfer_t queue[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ + size_t transferSize[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the FlexIO I2S. + * + * This API configures FlexIO pins and shifter to I2S and configures the FlexIO I2S with a configuration structure. + * The configuration structure can be filled by the user, or be set with default values by + * FLEXIO_I2S_GetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the FlexIO I2S driver. Otherwise, any access to the FlexIO I2S module can cause hard fault + * because the clock is not enabled. + * + * @param base FlexIO I2S base pointer + * @param config FlexIO I2S configure structure. + */ +void FLEXIO_I2S_Init(FLEXIO_I2S_Type *base, const flexio_i2s_config_t *config); + +/*! + * @brief Sets the FlexIO I2S configuration structure to default values. + * + * The purpose of this API is to get the configuration structure initialized for use in FLEXIO_I2S_Init(). + * Users may use the initialized structure unchanged in FLEXIO_I2S_Init() or modify + * some fields of the structure before calling FLEXIO_I2S_Init(). + * + * @param config pointer to master configuration structure + */ +void FLEXIO_I2S_GetDefaultConfig(flexio_i2s_config_t *config); + +/*! + * @brief De-initializes the FlexIO I2S. + * + * Calling this API resets the FlexIO I2S shifter and timer config. After calling this API, + * call the FLEXO_I2S_Init to use the FlexIO I2S module. + * + * @param base FlexIO I2S base pointer + */ +void FLEXIO_I2S_Deinit(FLEXIO_I2S_Type *base); + +/*! + * @brief Enables/disables the FlexIO I2S module operation. + * + * @param base Pointer to FLEXIO_I2S_Type + * @param enable True to enable, false dose not have any effect. + */ +static inline void FLEXIO_I2S_Enable(FLEXIO_I2S_Type *base, bool enable) +{ + if (enable) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexIO I2S status flags. + * + * @param base Pointer to FLEXIO_I2S_Type structure + * @return Status flag, which are ORed by the enumerators in the _flexio_i2s_status_flags. + */ +uint32_t FLEXIO_I2S_GetStatusFlags(FLEXIO_I2S_Type *base); + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO I2S interrupt. + * + * This function enables the FlexIO UART interrupt. + * + * @param base Pointer to FLEXIO_I2S_Type structure + * @param mask interrupt source + */ +void FLEXIO_I2S_EnableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO I2S interrupt. + * + * This function enables the FlexIO UART interrupt. + * + * @param base pointer to FLEXIO_I2S_Type structure + * @param mask interrupt source + */ +void FLEXIO_I2S_DisableInterrupts(FLEXIO_I2S_Type *base, uint32_t mask); + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO I2S Tx DMA requests. + * + * @param base FlexIO I2S base pointer + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void FLEXIO_I2S_TxEnableDMA(FLEXIO_I2S_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->txShifterIndex, enable); +} + +/*! + * @brief Enables/disables the FlexIO I2S Rx DMA requests. + * + * @param base FlexIO I2S base pointer + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void FLEXIO_I2S_RxEnableDMA(FLEXIO_I2S_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->rxShifterIndex, enable); +} + +/*! + * @brief Gets the FlexIO I2S send data register address. + * + * This function returns the I2S data register address, mainly used by DMA/eDMA. + * + * @param base Pointer to FLEXIO_I2S_Type structure + * @return FlexIO i2s send data register address. + */ +static inline uint32_t FLEXIO_I2S_TxGetDataRegisterAddress(FLEXIO_I2S_Type *base) +{ + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->txShifterIndex); +} + +/*! + * @brief Gets the FlexIO I2S receive data register address. + * + * This function returns the I2S data register address, mainly used by DMA/eDMA. + * + * @param base Pointer to FLEXIO_I2S_Type structure + * @return FlexIO i2s receive data register address. + */ +static inline uint32_t FLEXIO_I2S_RxGetDataRegisterAddress(FLEXIO_I2S_Type *base) +{ + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->rxShifterIndex); +} + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Configures the FlexIO I2S audio format in master mode. + * + * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base Pointer to FLEXIO_I2S_Type structure + * @param format Pointer to FlexIO I2S audio data format structure. + * @param srcClock_Hz I2S master clock source frequency in Hz. + */ +void FLEXIO_I2S_MasterSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format, uint32_t srcClock_Hz); + +/*! + * @brief Configures the FlexIO I2S audio format in slave mode. + * + * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base Pointer to FLEXIO_I2S_Type structure + * @param format Pointer to FlexIO I2S audio data format structure. + */ +void FLEXIO_I2S_SlaveSetFormat(FLEXIO_I2S_Type *base, flexio_i2s_format_t *format); + +/*! + * @brief Sends data using a blocking method. + * + * @note This function blocks via polling until data is ready to be sent. + * + * @param base FlexIO I2S base pointer. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param txData Pointer to the data to be written. + * @param size Bytes to be written. + */ +void FLEXIO_I2S_WriteBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *txData, size_t size); + +/*! + * @brief Writes data into a data register. + * + * @param base FlexIO I2S base pointer. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param data Data to be written. + */ +static inline void FLEXIO_I2S_WriteData(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint32_t data) +{ + base->flexioBase->SHIFTBUFBIS[base->txShifterIndex] = (data << (32U - bitWidth)); +} + +/*! + * @brief Receives a piece of data using a blocking method. + * + * @note This function blocks via polling until data is ready to be sent. + * + * @param base FlexIO I2S base pointer + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param rxData Pointer to the data to be read. + * @param size Bytes to be read. + */ +void FLEXIO_I2S_ReadBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth, uint8_t *rxData, size_t size); + +/*! + * @brief Reads a data from the data register. + * + * @param base FlexIO I2S base pointer + * @return Data read from data register. + */ +static inline uint32_t FLEXIO_I2S_ReadData(FLEXIO_I2S_Type *base) +{ + return base->flexioBase->SHIFTBUFBIS[base->rxShifterIndex]; +} + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the FlexIO I2S handle. + * + * This function initializes the FlexIO I2S handle which can be used for other + * FlexIO I2S transactional APIs. Call this API once to get the + * initialized handle. + * + * @param base Pointer to FLEXIO_I2S_Type structure + * @param handle Pointer to flexio_i2s_handle_t structure to store the transfer state. + * @param callback FlexIO I2S callback function, which is called while finished a block. + * @param userData User parameter for the FlexIO I2S callback. + */ +void FLEXIO_I2S_TransferTxCreateHandle(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_callback_t callback, + void *userData); + +/*! + * @brief Configures the FlexIO I2S audio format. + * + * Audio format can be changed at run-time of FlexIO I2S. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base Pointer to FLEXIO_I2S_Type structure. + * @param handle FlexIO I2S handle pointer. + * @param format Pointer to audio data format structure. + * @param srcClock_Hz FlexIO I2S bit clock source frequency in Hz. This parameter should be 0 while in slave mode. + */ +void FLEXIO_I2S_TransferSetFormat(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_format_t *format, + uint32_t srcClock_Hz); + +/*! + * @brief Initializes the FlexIO I2S receive handle. + * + * This function initializes the FlexIO I2S handle which can be used for other + * FlexIO I2S transactional APIs. Call this API once to get the + * initialized handle. + * + * @param base Pointer to FLEXIO_I2S_Type structure. + * @param handle Pointer to flexio_i2s_handle_t structure to store the transfer state. + * @param callback FlexIO I2S callback function, which is called while finished a block. + * @param userData User parameter for the FlexIO I2S callback. + */ +void FLEXIO_I2S_TransferRxCreateHandle(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_callback_t callback, + void *userData); + +/*! + * @brief Performs an interrupt non-blocking send transfer on FlexIO I2S. + * + * @note The API returns immediately after transfer initiates. + * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status and check whether + * the transfer is finished. If the return status is 0, the transfer is finished. + * + * @param base Pointer to FLEXIO_I2S_Type structure. + * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + * @param xfer Pointer to flexio_i2s_transfer_t structure + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_FLEXIO_I2S_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t FLEXIO_I2S_TransferSendNonBlocking(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_transfer_t *xfer); + +/*! + * @brief Performs an interrupt non-blocking receive transfer on FlexIO I2S. + * + * @note The API returns immediately after transfer initiates. + * Call FLEXIO_I2S_GetRemainingBytes to poll the transfer status to check whether + * the transfer is finished. If the return status is 0, the transfer is finished. + * + * @param base Pointer to FLEXIO_I2S_Type structure. + * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + * @param xfer Pointer to flexio_i2s_transfer_t structure + * @retval kStatus_Success Successfully start the data receive. + * @retval kStatus_FLEXIO_I2S_RxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t FLEXIO_I2S_TransferReceiveNonBlocking(FLEXIO_I2S_Type *base, + flexio_i2s_handle_t *handle, + flexio_i2s_transfer_t *xfer); + +/*! + * @brief Aborts the current send. + * + * @note This API can be called at any time when interrupt non-blocking transfer initiates + * to abort the transfer in a early time. + * + * @param base Pointer to FLEXIO_I2S_Type structure. + * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + */ +void FLEXIO_I2S_TransferAbortSend(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle); + +/*! + * @brief Aborts the current receive. + * + * @note This API can be called at any time when interrupt non-blocking transfer initiates + * to abort the transfer in a early time. + * + * @param base Pointer to FLEXIO_I2S_Type structure. + * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + */ +void FLEXIO_I2S_TransferAbortReceive(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle); + +/*! + * @brief Gets the remaining bytes to be sent. + * + * @param base Pointer to FLEXIO_I2S_Type structure. + * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + * @param count Bytes sent. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t FLEXIO_I2S_TransferGetSendCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count); + +/*! + * @brief Gets the remaining bytes to be received. + * + * @param base Pointer to FLEXIO_I2S_Type structure. + * @param handle Pointer to flexio_i2s_handle_t structure which stores the transfer state + * @return count Bytes received. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t FLEXIO_I2S_TransferGetReceiveCount(FLEXIO_I2S_Type *base, flexio_i2s_handle_t *handle, size_t *count); + +/*! + * @brief Tx interrupt handler. + * + * @param i2sBase Pointer to FLEXIO_I2S_Type structure. + * @param i2sHandle Pointer to flexio_i2s_handle_t structure + */ +void FLEXIO_I2S_TransferTxHandleIRQ(void *i2sBase, void *i2sHandle); + +/*! + * @brief Rx interrupt handler. + * + * @param i2sBase Pointer to FLEXIO_I2S_Type structure. + * @param i2sHandle Pointer to flexio_i2s_handle_t structure. + */ +void FLEXIO_I2S_TransferRxHandleIRQ(void *i2sBase, void *i2sHandle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + +/*! @} */ + +#endif /* _FSL_FLEXIO_I2S_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_i2s_edma.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_i2s_edma.c new file mode 100644 index 0000000000..5774768afe --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_i2s_edma.c @@ -0,0 +1,446 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_i2s_edma.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_i2s_edma" +#endif + +/******************************************************************************* + * Definitations + ******************************************************************************/ +/* Used for 32byte aligned */ +#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)(address) + 32) & ~0x1FU) + +/*handle; + + /* If finished a block, call the callback function */ + memset(&flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); + flexio_i2sHandle->queueDriver = (flexio_i2sHandle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + if (flexio_i2sHandle->callback) + { + (flexio_i2sHandle->callback)(privHandle->base, flexio_i2sHandle, kStatus_Success, flexio_i2sHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver].data == NULL) + { + FLEXIO_I2S_TransferAbortSendEDMA(privHandle->base, flexio_i2sHandle); + } +} + +static void FLEXIO_I2S_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) +{ + flexio_i2s_edma_private_handle_t *privHandle = (flexio_i2s_edma_private_handle_t *)userData; + flexio_i2s_edma_handle_t *flexio_i2sHandle = privHandle->handle; + + /* If finished a block, call the callback function */ + memset(&flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver], 0, sizeof(flexio_i2s_transfer_t)); + flexio_i2sHandle->queueDriver = (flexio_i2sHandle->queueDriver + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + if (flexio_i2sHandle->callback) + { + (flexio_i2sHandle->callback)(privHandle->base, flexio_i2sHandle, kStatus_Success, flexio_i2sHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (flexio_i2sHandle->queue[flexio_i2sHandle->queueDriver].data == NULL) + { + FLEXIO_I2S_TransferAbortReceiveEDMA(privHandle->base, flexio_i2sHandle); + } +} + +/*! + * brief Initializes the FlexIO I2S eDMA handle. + * + * This function initializes the FlexIO I2S master DMA handle which can be used for other FlexIO I2S master + * transactional APIs. + * Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle. + * + * param base FlexIO I2S peripheral base address. + * param handle FlexIO I2S eDMA handle pointer. + * param callback FlexIO I2S eDMA callback function called while finished a block. + * param userData User parameter for callback. + * param dmaHandle eDMA handle for FlexIO I2S. This handle is a static value allocated by users. + */ +void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_edma_callback_t callback, + void *userData, + edma_handle_t *dmaHandle) +{ + assert(handle && dmaHandle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set flexio_i2s base to handle */ + handle->dmaHandle = dmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set FLEXIO I2S state to idle */ + handle->state = kFLEXIO_I2S_Idle; + + s_edmaPrivateHandle[0].base = base; + s_edmaPrivateHandle[0].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), FLEXIO_I2S_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel */ + EDMA_SetCallback(dmaHandle, FLEXIO_I2S_TxEDMACallback, &s_edmaPrivateHandle[0]); +} + +/*! + * brief Initializes the FlexIO I2S Rx eDMA handle. + * + * This function initializes the FlexIO I2S slave DMA handle which can be used for other FlexIO I2S master transactional + * APIs. + * Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle. + * + * param base FlexIO I2S peripheral base address. + * param handle FlexIO I2S eDMA handle pointer. + * param callback FlexIO I2S eDMA callback function called while finished a block. + * param userData User parameter for callback. + * param dmaHandle eDMA handle for FlexIO I2S. This handle is a static value allocated by users. + */ +void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_edma_callback_t callback, + void *userData, + edma_handle_t *dmaHandle) +{ + assert(handle && dmaHandle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set flexio_i2s base to handle */ + handle->dmaHandle = dmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set FLEXIO I2S state to idle */ + handle->state = kFLEXIO_I2S_Idle; + + s_edmaPrivateHandle[1].base = base; + s_edmaPrivateHandle[1].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), FLEXIO_I2S_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel */ + EDMA_SetCallback(dmaHandle, FLEXIO_I2S_RxEDMACallback, &s_edmaPrivateHandle[1]); +} + +/*! + * brief Configures the FlexIO I2S Tx audio format. + * + * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to format. + * + * param base FlexIO I2S peripheral base address. + * param handle FlexIO I2S eDMA handle pointer + * param format Pointer to FlexIO I2S audio data format structure. + * param srcClock_Hz FlexIO I2S clock source frequency in Hz, it should be 0 while in slave mode. + * retval kStatus_Success Audio format set successfully. + * retval kStatus_InvalidArgument The input arguments is invalid. + */ +void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_format_t *format, + uint32_t srcClock_Hz) +{ + assert(handle && format); + + /* Configure the audio format to FLEXIO I2S registers */ + if (srcClock_Hz != 0) + { + /* It is master */ + FLEXIO_I2S_MasterSetFormat(base, format, srcClock_Hz); + } + else + { + FLEXIO_I2S_SlaveSetFormat(base, format); + } + + /* Get the transfer size from format, this should be used in EDMA configuration */ + handle->bytesPerFrame = format->bitWidth / 8U; +} + +/*! + * brief Performs a non-blocking FlexIO I2S transfer using DMA. + * + * note This interface returned immediately after transfer initiates. Users should call + * FLEXIO_I2S_GetTransferStatus to poll the transfer status and check whether the FlexIO I2S transfer is finished. + * + * param base FlexIO I2S peripheral base address. + * param handle FlexIO I2S DMA handle pointer. + * param xfer Pointer to DMA transfer structure. + * retval kStatus_Success Start a FlexIO I2S eDMA send successfully. + * retval kStatus_InvalidArgument The input arguments is invalid. + * retval kStatus_TxBusy FlexIO I2S is busy sending data. + */ +status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_transfer_t *xfer) +{ + assert(handle && xfer); + + edma_transfer_config_t config = {0}; + uint32_t destAddr = FLEXIO_I2S_TxGetDataRegisterAddress(base) + (4U - handle->bytesPerFrame); + + /* Check if input parameter invalid */ + if ((xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + if (handle->queue[handle->queueUser].data) + { + return kStatus_FLEXIO_I2S_QueueFull; + } + + /* Change the state of handle */ + handle->state = kFLEXIO_I2S_Busy; + + /* Update the queue state */ + handle->queue[handle->queueUser].data = xfer->data; + handle->queue[handle->queueUser].dataSize = xfer->dataSize; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (void *)destAddr, handle->bytesPerFrame, + handle->bytesPerFrame, xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Store the initially configured eDMA minor byte transfer count into the FLEXIO I2S handle */ + handle->nbytes = handle->bytesPerFrame; + + EDMA_SubmitTransfer(handle->dmaHandle, &config); + + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + FLEXIO_I2S_TxEnableDMA(base, true); + + /* Enable FLEXIO I2S Tx clock */ + FLEXIO_I2S_Enable(base, true); + + return kStatus_Success; +} + +/*! + * brief Performs a non-blocking FlexIO I2S receive using eDMA. + * + * note This interface returned immediately after transfer initiates. Users should call + * FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status and check whether the FlexIO I2S transfer is + * finished. + * + * param base FlexIO I2S peripheral base address. + * param handle FlexIO I2S DMA handle pointer. + * param xfer Pointer to DMA transfer structure. + * retval kStatus_Success Start a FlexIO I2S eDMA receive successfully. + * retval kStatus_InvalidArgument The input arguments is invalid. + * retval kStatus_RxBusy FlexIO I2S is busy receiving data. + */ +status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_transfer_t *xfer) +{ + assert(handle && xfer); + + edma_transfer_config_t config = {0}; + uint32_t srcAddr = FLEXIO_I2S_RxGetDataRegisterAddress(base); + + /* Check if input parameter invalid */ + if ((xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + if (handle->queue[handle->queueUser].data) + { + return kStatus_FLEXIO_I2S_QueueFull; + } + + /* Change the state of handle */ + handle->state = kFLEXIO_I2S_Busy; + + /* Update queue state */ + handle->queue[handle->queueUser].data = xfer->data; + handle->queue[handle->queueUser].dataSize = xfer->dataSize; + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame, + handle->bytesPerFrame, xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Store the initially configured eDMA minor byte transfer count into the FLEXIO I2S handle */ + handle->nbytes = handle->bytesPerFrame; + + EDMA_SubmitTransfer(handle->dmaHandle, &config); + + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + FLEXIO_I2S_RxEnableDMA(base, true); + + /* Enable FLEXIO I2S Rx clock */ + FLEXIO_I2S_Enable(base, true); + + return kStatus_Success; +} + +/*! + * brief Aborts a FlexIO I2S transfer using eDMA. + * + * param base FlexIO I2S peripheral base address. + * param handle FlexIO I2S DMA handle pointer. + */ +void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable DMA enable bit */ + FLEXIO_I2S_TxEnableDMA(base, false); + + /* Set the handle state */ + handle->state = kFLEXIO_I2S_Idle; +} + +/*! + * brief Aborts a FlexIO I2S receive using eDMA. + * + * param base FlexIO I2S peripheral base address. + * param handle FlexIO I2S DMA handle pointer. + */ +void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable DMA enable bit */ + FLEXIO_I2S_RxEnableDMA(base, false); + + /* Set the handle state */ + handle->state = kFLEXIO_I2S_Idle; +} + +/*! + * brief Gets the remaining bytes to be sent. + * + * param base FlexIO I2S peripheral base address. + * param handle FlexIO I2S DMA handle pointer. + * param count Bytes sent. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kFLEXIO_I2S_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = handle->transferSize[handle->queueDriver] - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel); + } + + return status; +} + +/*! + * brief Get the remaining bytes to be received. + * + * param base FlexIO I2S peripheral base address. + * param handle FlexIO I2S DMA handle pointer. + * param count Bytes received. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t FLEXIO_I2S_TransferGetReceiveCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kFLEXIO_I2S_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = handle->transferSize[handle->queueDriver] - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel); + } + + return status; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_i2s_edma.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_i2s_edma.h new file mode 100644 index 0000000000..817f197059 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_i2s_edma.h @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_FLEXIO_I2S_EDMA_H_ +#define _FSL_FLEXIO_I2S_EDMA_H_ + +#include "fsl_flexio_i2s.h" +#include "fsl_edma.h" + +/*! + * @addtogroup flexio_edma_i2s + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO I2S EDMA driver version 2.1.5. */ +#define FSL_FLEXIO_I2S_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) +/*@}*/ + +typedef struct _flexio_i2s_edma_handle flexio_i2s_edma_handle_t; + +/*! @brief FlexIO I2S eDMA transfer callback function for finish and error */ +typedef void (*flexio_i2s_edma_callback_t)(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO I2S DMA transfer handle, users should not touch the content of the handle.*/ +struct _flexio_i2s_edma_handle +{ + edma_handle_t *dmaHandle; /*!< DMA handler for FlexIO I2S send */ + uint8_t bytesPerFrame; /*!< Bytes in a frame */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + uint32_t state; /*!< Internal state for FlexIO I2S eDMA transfer */ + flexio_i2s_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurred */ + void *userData; /*!< User callback parameter */ + edma_tcd_t tcd[FLEXIO_I2S_XFER_QUEUE_SIZE + 1U]; /*!< TCD pool for eDMA transfer. */ + flexio_i2s_transfer_t queue[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ + size_t transferSize[FLEXIO_I2S_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA Transactional + * @{ + */ + +/*! + * @brief Initializes the FlexIO I2S eDMA handle. + * + * This function initializes the FlexIO I2S master DMA handle which can be used for other FlexIO I2S master + * transactional APIs. + * Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S eDMA handle pointer. + * @param callback FlexIO I2S eDMA callback function called while finished a block. + * @param userData User parameter for callback. + * @param dmaHandle eDMA handle for FlexIO I2S. This handle is a static value allocated by users. + */ +void FLEXIO_I2S_TransferTxCreateHandleEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_edma_callback_t callback, + void *userData, + edma_handle_t *dmaHandle); + +/*! + * @brief Initializes the FlexIO I2S Rx eDMA handle. + * + * This function initializes the FlexIO I2S slave DMA handle which can be used for other FlexIO I2S master transactional + * APIs. + * Usually, for a specified FlexIO I2S instance, call this API once to get the initialized handle. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S eDMA handle pointer. + * @param callback FlexIO I2S eDMA callback function called while finished a block. + * @param userData User parameter for callback. + * @param dmaHandle eDMA handle for FlexIO I2S. This handle is a static value allocated by users. + */ +void FLEXIO_I2S_TransferRxCreateHandleEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_edma_callback_t callback, + void *userData, + edma_handle_t *dmaHandle); + +/*! + * @brief Configures the FlexIO I2S Tx audio format. + * + * Audio format can be changed in run-time of FlexIO I2S. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to format. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S eDMA handle pointer + * @param format Pointer to FlexIO I2S audio data format structure. + * @param srcClock_Hz FlexIO I2S clock source frequency in Hz, it should be 0 while in slave mode. + * @retval kStatus_Success Audio format set successfully. + * @retval kStatus_InvalidArgument The input arguments is invalid. + */ +void FLEXIO_I2S_TransferSetFormatEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_format_t *format, + uint32_t srcClock_Hz); + +/*! + * @brief Performs a non-blocking FlexIO I2S transfer using DMA. + * + * @note This interface returned immediately after transfer initiates. Users should call + * FLEXIO_I2S_GetTransferStatus to poll the transfer status and check whether the FlexIO I2S transfer is finished. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + * @param xfer Pointer to DMA transfer structure. + * @retval kStatus_Success Start a FlexIO I2S eDMA send successfully. + * @retval kStatus_InvalidArgument The input arguments is invalid. + * @retval kStatus_TxBusy FlexIO I2S is busy sending data. + */ +status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking FlexIO I2S receive using eDMA. + * + * @note This interface returned immediately after transfer initiates. Users should call + * FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status and check whether the FlexIO I2S transfer is + * finished. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + * @param xfer Pointer to DMA transfer structure. + * @retval kStatus_Success Start a FlexIO I2S eDMA receive successfully. + * @retval kStatus_InvalidArgument The input arguments is invalid. + * @retval kStatus_RxBusy FlexIO I2S is busy receiving data. + */ +status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base, + flexio_i2s_edma_handle_t *handle, + flexio_i2s_transfer_t *xfer); + +/*! + * @brief Aborts a FlexIO I2S transfer using eDMA. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + */ +void FLEXIO_I2S_TransferAbortSendEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle); + +/*! + * @brief Aborts a FlexIO I2S receive using eDMA. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + */ +void FLEXIO_I2S_TransferAbortReceiveEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle); + +/*! + * @brief Gets the remaining bytes to be sent. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + * @param count Bytes sent. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t FLEXIO_I2S_TransferGetSendCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count); + +/*! + * @brief Get the remaining bytes to be received. + * + * @param base FlexIO I2S peripheral base address. + * @param handle FlexIO I2S DMA handle pointer. + * @param count Bytes received. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t FLEXIO_I2S_TransferGetReceiveCountEDMA(FLEXIO_I2S_Type *base, flexio_i2s_edma_handle_t *handle, size_t *count); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_mculcd.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_mculcd.c new file mode 100644 index 0000000000..e5d5b5d8c6 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_mculcd.c @@ -0,0 +1,1286 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_mculcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_mculcd" +#endif + +/******************************************************************************* + * Definitations + ******************************************************************************/ + +enum _mculcd_transfer_state +{ + kFLEXIO_MCULCD_StateIdle, /*!< No transfer in progress. */ + kFLEXIO_MCULCD_StateReadArray, /*!< Reading array in progress. */ + kFLEXIO_MCULCD_StateWriteArray, /*!< Writing array in progress. */ + kFLEXIO_MCULCD_StateWriteSameValue, /*!< Writing the same value in progress. */ +}; + +/* The TIMCFG[0:7] is used for baud rate divider in dual 8-bit counters baud/bit mode. */ +#define FLEXIO_BAUDRATE_DIV_MASK 0xFFU + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Ungates the FlexIO clock, resets the FlexIO module, configures the + * FlexIO MCULCD hardware, and configures the FlexIO MCULCD with FlexIO MCULCD + * configuration. + * The configuration structure can be filled by the user, or be set with default + * values + * by the ref FLEXIO_MCULCD_GetDefaultConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param config Pointer to the flexio_mculcd_config_t structure. + * param srcClock_Hz FlexIO source clock in Hz. + * retval kStatus_Success Initialization success. + * retval kStatus_InvalidArgument Initialization failed because of invalid + * argument. + */ +status_t FLEXIO_MCULCD_Init(FLEXIO_MCULCD_Type *base, flexio_mculcd_config_t *config, uint32_t srcClock_Hz) +{ + assert(config); + + flexio_config_t flexioConfig = {config->enable, config->enableInDoze, config->enableInDebug, + config->enableFastAccess}; + + FLEXIO_Init(base->flexioBase, &flexioConfig); + + if (kStatus_Success != FLEXIO_MCULCD_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz)) + { + return kStatus_Success; + } + + base->setCSPin(true); + base->setRSPin(true); + + return kStatus_Success; +} + +/*! + * brief Resets the FLEXIO_MCULCD timer and shifter configuration. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + */ +void FLEXIO_MCULCD_Deinit(FLEXIO_MCULCD_Type *base) +{ + FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base); + FLEXIO_MCULCD_ClearSingleBeatReadConfig(base); +} + +/*! + * brief Gets the default configuration to configure the FlexIO MCULCD. + * + * The default configuration value is: + * code + * config->enable = true; + * config->enableInDoze = false; + * config->enableInDebug = true; + * config->enableFastAccess = true; + * config->baudRate_Bps = 96000000U; + * endcode + * param Config Pointer to the flexio_mculcd_config_t structure. + */ +void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->enable = true; + config->enableInDoze = false; + config->enableInDebug = true; + config->enableFastAccess = true; + config->baudRate_Bps = 96000000U; +} + +/*! + * brief Set desired baud rate. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param baudRate_Bps Desired baud rate. + * param srcClock_Hz FLEXIO clock frequency in Hz. + * retval kStatus_Success Set successfully. + * retval kStatus_InvalidArgument Could not set the baud rate. + */ +status_t FLEXIO_MCULCD_SetBaudRate(FLEXIO_MCULCD_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t baudRateDiv; + uint32_t baudRatePerDataLine; + uint32_t timerCompare; + + baudRatePerDataLine = baudRate_Bps / FLEXIO_MCULCD_DATA_BUS_WIDTH; + + baudRateDiv = (srcClock_Hz + baudRatePerDataLine) / (baudRatePerDataLine * 2); + + if ((0 == baudRateDiv) || (baudRateDiv > (FLEXIO_BAUDRATE_DIV_MASK + 1U))) + { + return kStatus_InvalidArgument; + } + + baudRateDiv--; + + timerCompare = base->flexioBase->TIMCMP[base->timerIndex]; + + timerCompare = (timerCompare & ~FLEXIO_BAUDRATE_DIV_MASK) | baudRateDiv; + + base->flexioBase->TIMCMP[base->timerIndex] = timerCompare; + + return kStatus_Success; +} + +/*! + * brief Gets FlexIO MCULCD status flags. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * return status flag; OR'ed value or the ref _flexio_mculcd_status_flags. + * + * note Don't use this function with DMA APIs. + */ +uint32_t FLEXIO_MCULCD_GetStatusFlags(FLEXIO_MCULCD_Type *base) +{ + uint32_t ret = 0U; + uint32_t flags; + + /* Get shifter status. */ + flags = FLEXIO_GetShifterStatusFlags(base->flexioBase); + + if (flags & (1U << base->rxShifterEndIndex)) + { + ret |= kFLEXIO_MCULCD_RxFullFlag; + } + + if (flags & (1U << base->txShifterStartIndex)) + { + ret |= kFLEXIO_MCULCD_TxEmptyFlag; + } + + return ret; +} + +/*! + * brief Clears FlexIO MCULCD status flags. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param mask Status to clear, it is the OR'ed value of ref + * _flexio_mculcd_status_flags. + * + * note Don't use this function with DMA APIs. + */ +void FLEXIO_MCULCD_ClearStatusFlags(FLEXIO_MCULCD_Type *base, uint32_t mask) +{ + uint32_t flags = 0U; + + /* Clear the shifter flags. */ + if (mask & kFLEXIO_MCULCD_RxFullFlag) + { + flags |= (1U << base->rxShifterEndIndex); + } + + if (mask & kFLEXIO_MCULCD_TxEmptyFlag) + { + flags |= (1U << base->txShifterStartIndex); + } + + FLEXIO_ClearShifterStatusFlags(base->flexioBase, flags); +} + +/*! + * brief Enables the FlexIO MCULCD interrupt. + * + * This function enables the FlexIO MCULCD interrupt. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param mask Interrupts to enable, it is the OR'ed value of ref + * _flexio_mculcd_interrupt_enable. + */ +void FLEXIO_MCULCD_EnableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask) +{ + uint32_t interrupts = 0U; + + /* Enable shifter interrupts. */ + if (mask & kFLEXIO_MCULCD_RxFullFlag) + { + interrupts |= (1U << base->rxShifterEndIndex); + } + + if (mask & kFLEXIO_MCULCD_TxEmptyFlag) + { + interrupts |= (1U << base->txShifterStartIndex); + } + + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, interrupts); +} + +/*! + * brief Disables the FlexIO MCULCD interrupt. + * + * This function disables the FlexIO MCULCD interrupt. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param mask Interrupts to disable, it is the OR'ed value of ref + * _flexio_mculcd_interrupt_enable. + */ +void FLEXIO_MCULCD_DisableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask) +{ + uint32_t interrupts = 0U; + + /* Disable shifter interrupts. */ + if (mask & kFLEXIO_MCULCD_RxFullFlag) + { + interrupts |= (1U << base->rxShifterEndIndex); + } + + if (mask & kFLEXIO_MCULCD_TxEmptyFlag) + { + interrupts |= (1U << base->txShifterStartIndex); + } + + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, interrupts); +} + +/*! + * brief Read data from the FLEXIO MCULCD RX shifter buffer. + * + * Read data from the RX shift buffer directly, it does no check whether the + * buffer is empty or not. + * + * If the data bus width is 8-bit: + * code + * uint8_t value; + * value = (uint8_t)FLEXIO_MCULCD_ReadData(base); + * endcode + * + * If the data bus width is 16-bit: + * code + * uint16_t value; + * value = (uint16_t)FLEXIO_MCULCD_ReadData(base); + * endcode + * + * note This function returns the RX shifter buffer value (32-bit) directly. + * The return value should be converted according to data bus width. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * return The data read out. + * + * note Don't use this function with DMA APIs. + */ +uint32_t FLEXIO_MCULCD_ReadData(FLEXIO_MCULCD_Type *base) +{ +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + return base->flexioBase->SHIFTBUFBYS[base->rxShifterEndIndex]; +#else + return base->flexioBase->SHIFTBUFHWS[base->rxShifterEndIndex]; +#endif +} + +/*! + * brief Configures the FLEXIO MCULCD to multiple beats write mode. + * + * At the begining multiple beats write operation, the FLEXIO MCULCD is configured to + * multiple beats write mode using this function. After write operation, the configuration + * is cleared by ref FLEXIO_MCULCD_ClearSingleBeatWriteConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base) +{ + /* + * This function will be called at the beginning of every data writing. For + * performance consideration, it access the FlexIO registers directly, but not + * call FlexIO driver APIs. + */ + + uint32_t timerCompare; + + /* Enable the TX Shifter output. */ + base->flexioBase->SHIFTCFG[base->txShifterStartIndex] = + FLEXIO_SHIFTCFG_PWIDTH(FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U) | + FLEXIO_SHIFTCFG_INSRC(kFLEXIO_ShifterInputFromNextShifterOutput); + + base->flexioBase->SHIFTCTL[base->txShifterStartIndex] = + FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnPositive) | + FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutput) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) | + FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit); + + timerCompare = base->flexioBase->TIMCMP[base->timerIndex] & 0xFFU; + + /* + * TIMCMP[15:8] = (number of beats x 2) - 1. Because the number of beat is 1, + * so the TIMCMP[15:8] is 1. + */ + base->flexioBase->TIMCMP[base->timerIndex] = (1U << 8U) | timerCompare; + + /* Use TX shifter flag as the inverted timer trigger. Timer output to WR/EN pin. */ + base->flexioBase->TIMCFG[base->timerIndex] = + FLEXIO_TIMCFG_TIMOUT(kFLEXIO_TimerOutputOneNotAffectedByReset) | + FLEXIO_TIMCFG_TIMDEC(kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput) | + FLEXIO_TIMCFG_TIMRST(kFLEXIO_TimerResetNever) | FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare) | + FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled) | + FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled); + + base->flexioBase->TIMCTL[base->timerIndex] = + FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterStartIndex)) | + FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) | + FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput) | + FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) | + FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit); +} + +/*! + * brief Clear the FLEXIO MCULCD multiple beats write mode configuration. + * + * Clear the write configuration set by ref FLEXIO_MCULCD_SetSingleBeatWriteConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base) +{ + /* Disable the timer. */ + base->flexioBase->TIMCTL[base->timerIndex] = 0U; + base->flexioBase->TIMCFG[base->timerIndex] = 0U; + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1U << base->timerIndex); + /* Stop the TX shifter. */ + base->flexioBase->SHIFTCTL[base->txShifterStartIndex] = 0U; + base->flexioBase->SHIFTCFG[base->txShifterStartIndex] = 0U; + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = (1U << base->txShifterStartIndex); +} + +/*! + * brief Configures the FLEXIO MCULCD to multiple beats read mode. + * + * At the begining or multiple beats read operation, the FLEXIO MCULCD is configured + * to multiple beats read mode using this function. After read operation, the configuration + * is cleared by ref FLEXIO_MCULCD_ClearSingleBeatReadConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetSingleBeatReadConfig(FLEXIO_MCULCD_Type *base) +{ + /* + * This function will be called at the beginning of every data reading. For + * performance consideration, it access the FlexIO registers directly, but not + * call FlexIO driver APIs. + */ + + uint8_t timerPin; + uint32_t timerCompare; + flexio_pin_polarity_t timerPinPolarity; + + /* Timer output to RD pin (8080 mode), to WR/EN pin in 6800 mode. */ + if (kFLEXIO_MCULCD_8080 == base->busType) + { + timerPin = base->RDPinIndex; + timerPinPolarity = kFLEXIO_PinActiveLow; + } + else + { + timerPin = base->ENWRPinIndex; + timerPinPolarity = kFLEXIO_PinActiveHigh; + } + + /* Enable the RX Shifter input. */ + base->flexioBase->SHIFTCFG[base->rxShifterEndIndex] = FLEXIO_SHIFTCFG_PWIDTH(FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U); + + base->flexioBase->SHIFTCTL[base->rxShifterEndIndex] = + FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive) | + FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutputDisabled) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) | + FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeReceive); + + /* Use RX shifter flag as the inverted timer trigger. */ + base->flexioBase->TIMCFG[base->timerIndex] = + FLEXIO_TIMCFG_TIMOUT(kFLEXIO_TimerOutputOneNotAffectedByReset) | + FLEXIO_TIMCFG_TIMDEC(kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput) | + FLEXIO_TIMCFG_TIMRST(kFLEXIO_TimerResetNever) | FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare) | + FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable) | + FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled); + + timerCompare = base->flexioBase->TIMCMP[base->timerIndex] & 0xFFU; + + /* + * TIMCMP[15:8] = (number of beats x 2) - 1. Because the number of beat is 1, + * so the TIMCMP[15:8] is 1. + */ + base->flexioBase->TIMCMP[base->timerIndex] = (1U << 8U) | timerCompare; + + base->flexioBase->TIMCTL[base->timerIndex] |= + FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->rxShifterEndIndex)) | + FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) | + FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput) | + FLEXIO_TIMCTL_PINSEL(timerPin) | FLEXIO_TIMCTL_PINPOL(timerPinPolarity) | + FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit); +} + +/*! + * brief Clear the FLEXIO MCULCD multiple beats read mode configuration. + * + * Clear the read configuration set by ref FLEXIO_MCULCD_SetSingleBeatReadConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearSingleBeatReadConfig(FLEXIO_MCULCD_Type *base) +{ + /* Disable the timer. */ + base->flexioBase->TIMCTL[base->timerIndex] = 0U; + base->flexioBase->TIMCFG[base->timerIndex] = 0U; + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1U << base->timerIndex); + /* Stop the RX shifter. */ + base->flexioBase->SHIFTCTL[base->rxShifterEndIndex] = 0U; + base->flexioBase->SHIFTCFG[base->rxShifterEndIndex] = 0U; + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = (1U << base->rxShifterEndIndex); +} + +/*! + * brief Configures the FLEXIO MCULCD to multiple beats write mode. + * + * At the begining multiple beats write operation, the FLEXIO MCULCD is configured to + * multiple beats write mode using this function. After write operation, the configuration + * is cleared by ref FLEXIO_MCULCD_ClearMultBeatsWriteConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base) +{ + /* + * This function will be called at the beginning of every data writing. For + * performance consideration, it access the FlexIO registers directly, but not + * call FlexIO driver APIs. + */ + + uint32_t timerCompare; + uint8_t beats; + uint8_t i; + + /* Enable the TX Shifter output. */ + base->flexioBase->SHIFTCFG[base->txShifterStartIndex] = + FLEXIO_SHIFTCFG_PWIDTH(FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U) | + FLEXIO_SHIFTCFG_INSRC(kFLEXIO_ShifterInputFromNextShifterOutput); + + base->flexioBase->SHIFTCTL[base->txShifterStartIndex] = + FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnPositive) | + FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutput) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) | + FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit); + + for (i = base->txShifterStartIndex + 1U; i <= base->txShifterEndIndex; i++) + { + base->flexioBase->SHIFTCFG[i] = FLEXIO_SHIFTCFG_PWIDTH(FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U) | + FLEXIO_SHIFTCFG_INSRC(kFLEXIO_ShifterInputFromNextShifterOutput); + + base->flexioBase->SHIFTCTL[i] = + FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnPositive) | + FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutputDisabled) | FLEXIO_SHIFTCTL_PINSEL(0) | + FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit); + } + + timerCompare = base->flexioBase->TIMCMP[base->timerIndex] & 0xFFU; + +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + beats = 4U * (base->txShifterEndIndex - base->txShifterStartIndex + 1U); +#else + beats = 2U * (base->txShifterEndIndex - base->txShifterStartIndex + 1U); +#endif + + /* + * TIMCMP[15:8] = (number of beats x 2) - 1. + */ + base->flexioBase->TIMCMP[base->timerIndex] = ((beats * 2U - 1U) << 8U) | timerCompare; + + /* Use TX shifter flag as the inverted timer trigger. Timer output to WR/EN pin. */ + base->flexioBase->TIMCFG[base->timerIndex] = + FLEXIO_TIMCFG_TIMOUT(kFLEXIO_TimerOutputOneNotAffectedByReset) | + FLEXIO_TIMCFG_TIMDEC(kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput) | + FLEXIO_TIMCFG_TIMRST(kFLEXIO_TimerResetNever) | FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare) | + FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled) | + FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled); + + base->flexioBase->TIMCTL[base->timerIndex] = + FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterEndIndex)) | + FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) | + FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput) | + FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) | + FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit); +} + +/*! + * brief Clear the FLEXIO MCULCD multiple beats write mode configuration. + * + * Clear the write configuration set by ref FLEXIO_MCULCD_SetMultBeatsWriteConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base) +{ + uint8_t i; + uint32_t statusFlags = 0U; + + /* Disable the timer. */ + base->flexioBase->TIMCTL[base->timerIndex] = 0U; + base->flexioBase->TIMCFG[base->timerIndex] = 0U; + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1U << base->timerIndex); + + /* Stop the TX shifter. */ + for (i = base->txShifterStartIndex; i <= base->txShifterEndIndex; i++) + { + base->flexioBase->SHIFTCFG[i] = 0U; + base->flexioBase->SHIFTCTL[i] = 0U; + statusFlags |= (1U << i); + } + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = statusFlags; +} + +/*! + * brief Configures the FLEXIO MCULCD to multiple beats read mode. + * + * At the begining or multiple beats read operation, the FLEXIO MCULCD is configured + * to multiple beats read mode using this function. After read operation, the configuration + * is cleared by ref FLEXIO_MCULCD_ClearMultBeatsReadConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base) +{ + /* + * This function will be called at the beginning of every data reading. For + * performance consideration, it access the FlexIO registers directly, but not + * call FlexIO driver APIs. + */ + + uint8_t timerPin; + uint8_t beats; + uint8_t i; + uint32_t timerCompare; + flexio_pin_polarity_t timerPinPolarity; + + /* Timer output to RD pin (8080 mode), to WR/EN pin in 6800 mode. */ + if (kFLEXIO_MCULCD_8080 == base->busType) + { + timerPin = base->RDPinIndex; + timerPinPolarity = kFLEXIO_PinActiveLow; + } + else + { + timerPin = base->ENWRPinIndex; + timerPinPolarity = kFLEXIO_PinActiveHigh; + } + + /* Enable the RX Shifter input. */ + for (i = base->rxShifterStartIndex; i < base->rxShifterEndIndex; i++) + { + base->flexioBase->SHIFTCFG[i] = FLEXIO_SHIFTCFG_PWIDTH(FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U) | + FLEXIO_SHIFTCFG_INSRC(kFLEXIO_ShifterInputFromNextShifterOutput); + + base->flexioBase->SHIFTCTL[i] = + FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive) | + FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutputDisabled) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) | + FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeReceive); + } + + base->flexioBase->SHIFTCFG[base->rxShifterEndIndex] = FLEXIO_SHIFTCFG_PWIDTH(FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U); + base->flexioBase->SHIFTCTL[base->rxShifterEndIndex] = + FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive) | + FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutputDisabled) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) | + FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeReceive); + + timerCompare = base->flexioBase->TIMCMP[base->timerIndex] & 0xFFU; + +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + beats = 4U * (base->rxShifterEndIndex - base->rxShifterStartIndex + 1U); +#else + beats = 2U * (base->rxShifterEndIndex - base->rxShifterStartIndex + 1U); +#endif + + /* + * TIMCMP[15:8] = (number of beats x 2) - 1. + */ + base->flexioBase->TIMCMP[base->timerIndex] = ((beats * 2U - 1U) << 8U) | timerCompare; + + /* Use RX shifter flag as the inverted timer trigger. */ + base->flexioBase->TIMCFG[base->timerIndex] = + FLEXIO_TIMCFG_TIMOUT(kFLEXIO_TimerOutputOneNotAffectedByReset) | + FLEXIO_TIMCFG_TIMDEC(kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput) | + FLEXIO_TIMCFG_TIMRST(kFLEXIO_TimerResetNever) | FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare) | + FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable) | + FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled); + + base->flexioBase->TIMCTL[base->timerIndex] |= + FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->rxShifterEndIndex)) | + FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) | + FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput) | + FLEXIO_TIMCTL_PINSEL(timerPin) | FLEXIO_TIMCTL_PINPOL(timerPinPolarity) | + FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit); +} + +/*! + * brief Clear the FLEXIO MCULCD multiple beats read mode configuration. + * + * Clear the read configuration set by ref FLEXIO_MCULCD_SetMultBeatsReadConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base) +{ + uint8_t i; + uint32_t statusFlags = 0U; + + /* Disable the timer. */ + base->flexioBase->TIMCTL[base->timerIndex] = 0U; + base->flexioBase->TIMCFG[base->timerIndex] = 0U; + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1U << base->timerIndex); + /* Stop the RX shifter. */ + for (i = base->rxShifterStartIndex; i <= base->rxShifterEndIndex; i++) + { + base->flexioBase->SHIFTCTL[i] = 0U; + base->flexioBase->SHIFTCFG[i] = 0U; + statusFlags |= (1U << i); + } + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = statusFlags; +} + +/*! + * brief Wait for transmit data send out finished. + * + * Currently there is no effective method to wait for the data send out + * from the shiter, so here use a while loop to wait. + * + * note This is an internal used function. + */ +void FLEXIO_MCULCD_WaitTransmitComplete(void) +{ + uint32_t i = FLEXIO_MCULCD_WAIT_COMPLETE_TIME; + + while (i--) + { + __NOP(); + } +} + +/*! + * brief Send command in blocking way. + * + * This function sends the command and returns when the command has been sent + * out. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param command The command to send. + */ +void FLEXIO_MCULCD_WriteCommandBlocking(FLEXIO_MCULCD_Type *base, uint32_t command) +{ + FLEXIO_Type *flexioBase = base->flexioBase; + + /* De-assert the RS pin. */ + base->setRSPin(false); + + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + + /* Configure the timer and TX shifter. */ + FLEXIO_MCULCD_SetSingleBeatWriteConfig(base); + + /* Write command to shifter buffer. */ + flexioBase->SHIFTBUF[base->txShifterStartIndex] = command; + + /* Wait for command send out. */ + while (!((1U << base->timerIndex) & FLEXIO_GetTimerStatusFlags(flexioBase))) + { + } + + /* Stop the timer and TX shifter. */ + FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base); + + /* Assert the RS pin. */ + base->setRSPin(true); + /* For 6800, assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(true); + } +} + +/*! + * brief Send data array in blocking way. + * + * This function sends the data array and returns when the data sent out. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param data The data array to send. + * param size How many bytes to write. + */ +void FLEXIO_MCULCD_WriteDataArrayBlocking(FLEXIO_MCULCD_Type *base, void *data, size_t size) +{ + assert(size); + + uint32_t i; +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + uint8_t *data8Bit; +#else + uint16_t *data16Bit; +#endif + FLEXIO_Type *flexioBase = base->flexioBase; + + /* Assert the RS pin. */ + base->setRSPin(true); + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + + /* Configure the timer and TX shifter. */ + FLEXIO_MCULCD_SetSingleBeatWriteConfig(base); + +/* If data bus width is 8. */ +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + data8Bit = (uint8_t *)data; + + for (i = 0; i < size; i++) + { + flexioBase->SHIFTBUF[base->txShifterStartIndex] = data8Bit[i]; + + /* Wait for the data send out. */ + while (!((1U << base->timerIndex) & flexioBase->TIMSTAT)) + { + } + + /* Clear the timer stat. */ + flexioBase->TIMSTAT = 1U << base->timerIndex; + } +#else + data16Bit = (uint16_t *)data; + size /= 2; + + for (i = 0; i < size; i++) + { + flexioBase->SHIFTBUF[base->txShifterStartIndex] = data16Bit[i]; + + /* Wait for the data send out. */ + while (!((1U << base->timerIndex) & flexioBase->TIMSTAT)) + { + } + + /* Clear the timer stat. */ + flexioBase->TIMSTAT = 1U << base->timerIndex; + } +#endif + + /* Stop the timer and TX shifter. */ + FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base); +} + +/*! + * brief Read data into array in blocking way. + * + * This function reads the data into array and returns when the data read + * finished. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param data The array to save the data. + * param size How many bytes to read. + */ +void FLEXIO_MCULCD_ReadDataArrayBlocking(FLEXIO_MCULCD_Type *base, void *data, size_t size) +{ + assert(size); + + uint32_t i; + +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + uint8_t *data8Bit = (uint8_t *)data; +#else + uint16_t *data16Bit = (uint16_t *)data; +#endif + FLEXIO_Type *flexioBase = base->flexioBase; + + /* Assert the RS pin. */ + base->setRSPin(true); + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + + /* Enable the timer and RX shifter. */ + FLEXIO_MCULCD_SetSingleBeatReadConfig(base); + +/* If data bus width is 8. */ +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + for (i = 0; i < (size - 1); i++) + { + /* Wait for shifter buffer full. */ + while (!((1U << base->rxShifterEndIndex) & FLEXIO_GetShifterStatusFlags(flexioBase))) + { + } + + data8Bit[i] = (uint8_t)flexioBase->SHIFTBUFBYS[base->rxShifterEndIndex]; + } +#else + /* Data bus width is 16. */ + size /= 2; + + for (i = 0; i < (size - 1); i++) + { + /* Wait for shifter buffer full. */ + while (!((1U << base->rxShifterEndIndex) & FLEXIO_GetShifterStatusFlags(flexioBase))) + { + } + + data16Bit[i] = (uint16_t)flexioBase->SHIFTBUFHWS[base->rxShifterEndIndex]; + } +#endif + + /* Wait for shifter buffer full. */ + while (!((1U << base->rxShifterEndIndex) & FLEXIO_GetShifterStatusFlags(flexioBase))) + { + } + + /* Stop the timer and disable the RX shifter. */ + FLEXIO_MCULCD_ClearSingleBeatReadConfig(base); + +/* Read out the last data. */ +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + data8Bit[i] = (uint8_t)flexioBase->SHIFTBUFBYS[base->rxShifterEndIndex]; +#else + data16Bit[i] = (uint16_t)flexioBase->SHIFTBUFHWS[base->rxShifterEndIndex]; +#endif +} + +/*! + * brief Send the same value many times in blocking way. + * + * This function sends the same value many times. It could be used to clear the + * LCD screen. If the data bus width is 8, this function will send LSB 8 bits of + * p sameValue for p size times. If the data bus is 16, this function will send + * LSB 16 bits of p sameValue for p size / 2 times. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param sameValue The same value to send. + * param size How many bytes to send. + */ +void FLEXIO_MCULCD_WriteSameValueBlocking(FLEXIO_MCULCD_Type *base, uint32_t sameValue, size_t size) +{ + assert(size); + + uint32_t i; + FLEXIO_Type *flexioBase = base->flexioBase; + +#if (16 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + size /= 2; +#endif + + /* Assert the RS pin. */ + base->setRSPin(true); + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + + /* Configure the timer and TX shifter. */ + FLEXIO_MCULCD_SetSingleBeatWriteConfig(base); + + for (i = 0; i < size; i++) + { + flexioBase->SHIFTBUF[base->txShifterStartIndex] = sameValue; + + /* Wait for the data send out. */ + while (!((1U << base->timerIndex) & flexioBase->TIMSTAT)) + { + } + + /* Clear the timer stat. */ + flexioBase->TIMSTAT = 1U << base->timerIndex; + } + + /* Stop the timer and TX shifter. */ + FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base); +} + +/*! + * brief Performs a polling transfer. + * + * note The API does not return until the transfer finished. + * + * param base pointer to FLEXIO_MCULCD_Type structure. + * param xfer pointer to flexio_mculcd_transfer_t structure. + */ +void FLEXIO_MCULCD_TransferBlocking(FLEXIO_MCULCD_Type *base, flexio_mculcd_transfer_t *xfer) +{ + FLEXIO_MCULCD_StartTransfer(base); + + FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + + if (xfer->dataSize > 0) + { + if (kFLEXIO_MCULCD_ReadArray == xfer->mode) + { + FLEXIO_MCULCD_ReadDataArrayBlocking(base, (void *)(xfer->dataAddrOrSameValue), xfer->dataSize); + } + else if (kFLEXIO_MCULCD_WriteArray == xfer->mode) + { + FLEXIO_MCULCD_WriteDataArrayBlocking(base, (void *)(xfer->dataAddrOrSameValue), xfer->dataSize); + } + else + { + FLEXIO_MCULCD_WriteSameValueBlocking(base, xfer->dataAddrOrSameValue, xfer->dataSize); + } + } + + FLEXIO_MCULCD_StopTransfer(base); +} + +/*! + * brief Initializes the FlexIO MCULCD handle, which is used in transactional + * functions. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + * param callback The callback function. + * param userData The parameter of the callback function. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_MCULCD_TransferCreateHandle(FLEXIO_MCULCD_Type *base, + flexio_mculcd_handle_t *handle, + flexio_mculcd_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + handle->state = kFLEXIO_MCULCD_StateIdle; + + /* Register callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Enable interrupt in NVIC. */ + EnableIRQ(flexio_irqs[FLEXIO_GetInstance(base->flexioBase)]); + + /* Save the context in global variables to support the double weak mechanism. + */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_MCULCD_TransferHandleIRQ); +} + +/*! + * brief Transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which + * returns right away. When all data is sent out/received, the callback + * function is called. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + * param xfer FlexIO MCULCD transfer structure. See #flexio_mculcd_transfer_t. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_MCULCD_Busy MCULCD is busy with another transfer. + */ +status_t FLEXIO_MCULCD_TransferNonBlocking(FLEXIO_MCULCD_Type *base, + flexio_mculcd_handle_t *handle, + flexio_mculcd_transfer_t *xfer) +{ + /* If previous transfer is in progress. */ + if (kFLEXIO_MCULCD_StateIdle != handle->state) + { + return kStatus_FLEXIO_MCULCD_Busy; + } + + /* Set the state in handle. */ + if (kFLEXIO_MCULCD_ReadArray == xfer->mode) + { + handle->state = kFLEXIO_MCULCD_StateReadArray; + } + else if (kFLEXIO_MCULCD_WriteArray == xfer->mode) + { + handle->state = kFLEXIO_MCULCD_StateWriteArray; + } + else + { + handle->state = kFLEXIO_MCULCD_StateWriteSameValue; + } + + /* Assert the nCS. */ + FLEXIO_MCULCD_StartTransfer(base); + + /* Send the command. */ + FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + + /* If transfer count is 0 (only to send command), return directly. */ + if (0U == xfer->dataSize) + { + handle->state = kFLEXIO_MCULCD_StateIdle; + + /* De-assert the nCS. */ + FLEXIO_MCULCD_StopTransfer(base); + + if (handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_FLEXIO_MCULCD_Idle, handle->userData); + } + } + else + { +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + handle->dataCount = xfer->dataSize; +#else + handle->dataCount = xfer->dataSize / 2; +#endif + + handle->remainingCount = handle->dataCount; + + handle->dataAddrOrSameValue = xfer->dataAddrOrSameValue; + + /* Enable interrupt. */ + if (kFLEXIO_MCULCD_ReadArray == xfer->mode) + { + /* For 6800, assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(true); + } + FLEXIO_MCULCD_SetSingleBeatReadConfig(base); + FLEXIO_MCULCD_EnableInterrupts(base, kFLEXIO_MCULCD_RxFullInterruptEnable); + } + else + { + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + FLEXIO_MCULCD_SetSingleBeatWriteConfig(base); + FLEXIO_MCULCD_EnableInterrupts(base, kFLEXIO_MCULCD_TxEmptyInterruptEnable); + } + } + + return kStatus_Success; +} + +/*! + * brief Aborts the data transfer, which used IRQ. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + */ +void FLEXIO_MCULCD_TransferAbort(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle) +{ + /* If no transfer in process, return directly. */ + if (kFLEXIO_MCULCD_StateIdle == handle->state) + { + return; + } + + /* Disable the interrupt. */ + FLEXIO_MCULCD_DisableInterrupts(base, kFLEXIO_MCULCD_RxFullInterruptEnable | kFLEXIO_MCULCD_TxEmptyInterruptEnable); + + if (kFLEXIO_MCULCD_ReadArray == handle->state) + { + /* Stop the timer and disable the RX shifter. */ + FLEXIO_MCULCD_ClearSingleBeatReadConfig(base); + } + else + { + /* Stop the timer and disable the TX shifter. */ + FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base); + } + + /* Clean the flags. */ + FLEXIO_MCULCD_ClearStatusFlags(base, kFLEXIO_MCULCD_TxEmptyFlag | kFLEXIO_MCULCD_RxFullFlag); + + /* De-assert the nCS. */ + FLEXIO_MCULCD_StopTransfer(base); + + handle->dataCount = 0; + handle->remainingCount = 0; + handle->state = kFLEXIO_MCULCD_StateIdle; +} + +/*! + * brief Gets the data transfer status which used IRQ. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + * param count How many bytes transferred so far by the non-blocking transaction. + * retval kStatus_Success Get the transferred count Successfully. + * retval kStatus_NoTransferInProgress No transfer in process. + */ +status_t FLEXIO_MCULCD_TransferGetCount(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle, size_t *count) +{ + assert(count); + + if (kFLEXIO_MCULCD_StateIdle == handle->state) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->dataCount - handle->remainingCount; + +#if (16 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + *count *= 2; +#endif + + return kStatus_Success; +} + +/*! + * brief FlexIO MCULCD IRQ handler function. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + */ +void FLEXIO_MCULCD_TransferHandleIRQ(void *base, void *handle) +{ + FLEXIO_MCULCD_Type *flexioLcdMcuBase = (FLEXIO_MCULCD_Type *)base; + flexio_mculcd_handle_t *flexioLcdMcuHandle = (flexio_mculcd_handle_t *)handle; + uint32_t statusFlags = FLEXIO_MCULCD_GetStatusFlags(flexioLcdMcuBase); + uint32_t data; + + if (kFLEXIO_MCULCD_StateReadArray == flexioLcdMcuHandle->state) + { + /* Handle the reading process. */ + while ((kFLEXIO_MCULCD_RxFullFlag & statusFlags) && (flexioLcdMcuHandle->remainingCount > 0)) + { + if (1 == flexioLcdMcuHandle->remainingCount) + { + /* If this is the last data, stop the RX shifter and timer. */ + FLEXIO_MCULCD_DisableInterrupts(flexioLcdMcuBase, kFLEXIO_MCULCD_RxFullInterruptEnable); + FLEXIO_MCULCD_ClearSingleBeatReadConfig(flexioLcdMcuBase); + FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase); + } + + /* Read out the data. */ + data = FLEXIO_MCULCD_ReadData(flexioLcdMcuBase); + +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + *(uint8_t *)(flexioLcdMcuHandle->dataAddrOrSameValue) = (uint8_t)data; + flexioLcdMcuHandle->dataAddrOrSameValue++; +#else + *(uint16_t *)(flexioLcdMcuHandle->dataAddrOrSameValue) = (uint16_t)data; + flexioLcdMcuHandle->dataAddrOrSameValue += 2U; +#endif + + flexioLcdMcuHandle->remainingCount--; + + /* Transfer finished, call the callback. */ + if (0 == flexioLcdMcuHandle->remainingCount) + { + flexioLcdMcuHandle->state = kFLEXIO_MCULCD_StateIdle; + + if (flexioLcdMcuHandle->completionCallback) + { + flexioLcdMcuHandle->completionCallback(flexioLcdMcuBase, flexioLcdMcuHandle, + kStatus_FLEXIO_MCULCD_Idle, flexioLcdMcuHandle->userData); + } + } + + /* Is the shifter buffer ready to send the next data? */ + statusFlags = FLEXIO_MCULCD_GetStatusFlags(flexioLcdMcuBase); + } + } + else + { + /* Handle the writing process. */ + while ((kFLEXIO_MCULCD_TxEmptyFlag & statusFlags) && (flexioLcdMcuHandle->remainingCount > 0)) + { + /* Send the data. */ + if (kFLEXIO_MCULCD_StateWriteSameValue == flexioLcdMcuHandle->state) + { + data = flexioLcdMcuHandle->dataAddrOrSameValue; + } + else + { +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + data = *(uint8_t *)(flexioLcdMcuHandle->dataAddrOrSameValue); + flexioLcdMcuHandle->dataAddrOrSameValue++; +#else + data = *(uint16_t *)(flexioLcdMcuHandle->dataAddrOrSameValue); + flexioLcdMcuHandle->dataAddrOrSameValue += 2U; +#endif + } + + /* If this is the last data to send, delay to wait for the data shift out. */ + if (1 == flexioLcdMcuHandle->remainingCount) + { + FLEXIO_MCULCD_DisableInterrupts(flexioLcdMcuBase, kFLEXIO_MCULCD_TxEmptyInterruptEnable); + + /* Write the last data. */ + FLEXIO_MCULCD_WriteData(flexioLcdMcuBase, data); + + /* Wait for the last data send finished. */ + FLEXIO_MCULCD_WaitTransmitComplete(); + flexioLcdMcuHandle->remainingCount = 0; + + FLEXIO_MCULCD_ClearSingleBeatWriteConfig(flexioLcdMcuBase); + FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase); + flexioLcdMcuHandle->state = kFLEXIO_MCULCD_StateIdle; + + if (flexioLcdMcuHandle->completionCallback) + { + flexioLcdMcuHandle->completionCallback(flexioLcdMcuBase, flexioLcdMcuHandle, + kStatus_FLEXIO_MCULCD_Idle, flexioLcdMcuHandle->userData); + } + } + else + { + FLEXIO_MCULCD_WriteData(flexioLcdMcuBase, data); + flexioLcdMcuHandle->remainingCount--; + } + /* Is the shifter buffer ready to send the next data? */ + statusFlags = FLEXIO_MCULCD_GetStatusFlags(flexioLcdMcuBase); + } + } +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_mculcd.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_mculcd.h new file mode 100644 index 0000000000..feb196cb81 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_mculcd.h @@ -0,0 +1,687 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_FLEXIO_MCULCD_H_ +#define _FSL_FLEXIO_MCULCD_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_mculcd + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO MCULCD driver version 2.0.2. */ +#define FSL_FLEXIO_MCULCD_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +#ifndef FLEXIO_MCULCD_WAIT_COMPLETE_TIME +/*! + * @brief The delay time to wait for FLEXIO transmit complete. + * + * Currently there is no method to detect whether the data has been + * sent out from the shifter, so the driver use a software delay for this. When + * the data is written to shifter buffer, the driver call the delay + * function to wait for the data shift out. + * If this value is too small, then the last few bytes might be lost when writing + * data using interrupt method or DMA method. + */ +#define FLEXIO_MCULCD_WAIT_COMPLETE_TIME 512 +#endif + +#ifndef FLEXIO_MCULCD_DATA_BUS_WIDTH +/*! + * @brief The data bus width, must be 8 or 16. + */ +#define FLEXIO_MCULCD_DATA_BUS_WIDTH 16 +#endif + +#if (16 != FLEXIO_MCULCD_DATA_BUS_WIDTH) && (8 != FLEXIO_MCULCD_DATA_BUS_WIDTH) +#error Only support data bus 8-bit or 16-bit +#endif + +/*! @brief FlexIO LCD transfer status */ +enum _flexio_mculcd_status +{ + kStatus_FLEXIO_MCULCD_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_MCULCD, 0), /*!< FlexIO LCD is idle. */ + kStatus_FLEXIO_MCULCD_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_MCULCD, 1), /*!< FlexIO LCD is busy */ + kStatus_FLEXIO_MCULCD_Error = MAKE_STATUS(kStatusGroup_FLEXIO_MCULCD, 2), /*!< FlexIO LCD error occurred */ +}; + +/*! @brief Define FlexIO MCULCD pixel format. */ +typedef enum _flexio_mculcd_pixel_format +{ + kFLEXIO_MCULCD_RGB565 = 0, /*!< RGB565, 16-bit. */ + kFLEXIO_MCULCD_BGR565, /*!< BGR565, 16-bit. */ + kFLEXIO_MCULCD_RGB888, /*!< RGB888, 24-bit. */ + kFLEXIO_MCULCD_BGR888, /*!< BGR888, 24-bit. */ +} flexio_mculcd_pixel_format_t; + +/*! @brief Define FlexIO MCULCD bus type. */ +typedef enum _flexio_mculcd_bus +{ + kFLEXIO_MCULCD_8080, /*!< Using Intel 8080 bus. */ + kFLEXIO_MCULCD_6800, /*!< Using Motorola 6800 bus. */ +} flexio_mculcd_bus_t; + +/*! @brief Define FlexIO MCULCD interrupt mask. */ +enum _flexio_mculcd_interrupt_enable +{ + kFLEXIO_MCULCD_TxEmptyInterruptEnable = (1U << 0U), /*!< Transmit buffer empty interrupt enable. */ + kFLEXIO_MCULCD_RxFullInterruptEnable = (1U << 1U), /*!< Receive buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO MCULCD status mask. */ +enum _flexio_mculcd_status_flags +{ + kFLEXIO_MCULCD_TxEmptyFlag = (1U << 0U), /*!< Transmit buffer empty flag. */ + kFLEXIO_MCULCD_RxFullFlag = (1U << 1U), /*!< Receive buffer full flag. */ +}; + +/*! @brief Define FlexIO MCULCD DMA mask. */ +enum _flexio_mculcd_dma_enable +{ + kFLEXIO_MCULCD_TxDmaEnable = 0x1U, /*!< Tx DMA request source */ + kFLEXIO_MCULCD_RxDmaEnable = 0x2U, /*!< Rx DMA request source */ +}; + +/*! @brief Function to set or clear the CS and RS pin. */ +typedef void (*flexio_mculcd_pin_func_t)(bool set); + +/*! @brief Define FlexIO MCULCD access structure typedef. */ +typedef struct _flexio_mculcd_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ + flexio_mculcd_bus_t busType; /*!< The bus type, 8080 or 6800. */ + uint8_t dataPinStartIndex; /*!< Start index of the data pin, the FlexIO pin dataPinStartIndex + to (dataPinStartIndex + FLEXIO_MCULCD_DATA_BUS_WIDTH -1) + will be used for data transfer. Only support data bus width 8 and 16. */ + uint8_t ENWRPinIndex; /*!< Pin select for WR(8080 mode), EN(6800 mode). */ + uint8_t RDPinIndex; /*!< Pin select for RD(8080 mode), not used in 6800 mode. */ + uint8_t txShifterStartIndex; /*!< Start index of shifters used for data write, it must be 0 or 4. */ + uint8_t txShifterEndIndex; /*!< End index of shifters used for data write. */ + uint8_t rxShifterStartIndex; /*!< Start index of shifters used for data read. */ + uint8_t rxShifterEndIndex; /*!< End index of shifters used for data read, it must be 3 or 7. */ + uint8_t timerIndex; /*!< Timer index used in FlexIO MCULCD. */ + flexio_mculcd_pin_func_t setCSPin; /*!< Function to set or clear the CS pin. */ + flexio_mculcd_pin_func_t setRSPin; /*!< Function to set or clear the RS pin. */ + flexio_mculcd_pin_func_t setRDWRPin; /*!< Function to set or clear the RD/WR pin, only used in 6800 mode. */ +} FLEXIO_MCULCD_Type; + +/*! @brief Define FlexIO MCULCD configuration structure. */ +typedef struct _flexio_mculcd_config +{ + bool enable; /*!< Enable/disable FlexIO MCULCD after configuration. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, + fast access requires the FlexIO clock to be at least + twice the frequency of the bus clock. */ + uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ +} flexio_mculcd_config_t; + +/*! @brief Transfer mode.*/ +typedef enum _flexio_mculcd_transfer_mode +{ + kFLEXIO_MCULCD_ReadArray, /*!< Read data into an array. */ + kFLEXIO_MCULCD_WriteArray, /*!< Write data from an array. */ + kFLEXIO_MCULCD_WriteSameValue, /*!< Write the same value many times. */ +} flexio_mculcd_transfer_mode_t; + +/*! @brief Define FlexIO MCULCD transfer structure. */ +typedef struct _flexio_mculcd_transfer +{ + uint32_t command; /*!< Command to send. */ + flexio_mculcd_transfer_mode_t mode; /*!< Transfer mode. */ + uint32_t dataAddrOrSameValue; /*!< When sending the same value for many times, + this is the value to send. When writing or reading array, + this is the address of the data array. */ + size_t dataSize; /*!< How many bytes to transfer. */ +} flexio_mculcd_transfer_t; + +/*! @brief typedef for flexio_mculcd_handle_t in advance. */ +typedef struct _flexio_mculcd_handle flexio_mculcd_handle_t; + +/*! @brief FlexIO MCULCD callback for finished transfer. + * + * When transfer finished, the callback function is called and returns the + * @p status as kStatus_FLEXIO_MCULCD_Idle. + */ +typedef void (*flexio_mculcd_transfer_callback_t)(FLEXIO_MCULCD_Type *base, + flexio_mculcd_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FlexIO MCULCD handle structure. */ +struct _flexio_mculcd_handle +{ + uint32_t dataAddrOrSameValue; /*!< When sending the same value for many times, + this is the value to send. When writing or reading array, + this is the address of the data array. */ + size_t dataCount; /*!< Total count to be transferred. */ + volatile size_t remainingCount; /*!< Remaining count to transfer. */ + volatile uint32_t state; /*!< FlexIO MCULCD internal state. */ + flexio_mculcd_transfer_callback_t completionCallback; /*!< FlexIO MCULCD transfer completed callback. */ + void *userData; /*!< Callback parameter. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name FlexIO MCULCD Configuration + * @{ + */ + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the + * FlexIO MCULCD hardware, and configures the FlexIO MCULCD with FlexIO MCULCD + * configuration. + * The configuration structure can be filled by the user, or be set with default + * values + * by the @ref FLEXIO_MCULCD_GetDefaultConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param config Pointer to the flexio_mculcd_config_t structure. + * @param srcClock_Hz FlexIO source clock in Hz. + * @retval kStatus_Success Initialization success. + * @retval kStatus_InvalidArgument Initialization failed because of invalid + * argument. + */ +status_t FLEXIO_MCULCD_Init(FLEXIO_MCULCD_Type *base, flexio_mculcd_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Resets the FLEXIO_MCULCD timer and shifter configuration. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + */ +void FLEXIO_MCULCD_Deinit(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO MCULCD. + * + * The default configuration value is: + * @code + * config->enable = true; + * config->enableInDoze = false; + * config->enableInDebug = true; + * config->enableFastAccess = true; + * config->baudRate_Bps = 96000000U; + * @endcode + * @param Config Pointer to the flexio_mculcd_config_t structure. + */ +void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config); + +/*@}*/ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets FlexIO MCULCD status flags. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @return status flag; OR'ed value or the @ref _flexio_mculcd_status_flags. + * + * @note Don't use this function with DMA APIs. + */ +uint32_t FLEXIO_MCULCD_GetStatusFlags(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Clears FlexIO MCULCD status flags. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param mask Status to clear, it is the OR'ed value of @ref + * _flexio_mculcd_status_flags. + * + * @note Don't use this function with DMA APIs. + */ +void FLEXIO_MCULCD_ClearStatusFlags(FLEXIO_MCULCD_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO MCULCD interrupt. + * + * This function enables the FlexIO MCULCD interrupt. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param mask Interrupts to enable, it is the OR'ed value of @ref + * _flexio_mculcd_interrupt_enable. + */ +void FLEXIO_MCULCD_EnableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO MCULCD interrupt. + * + * This function disables the FlexIO MCULCD interrupt. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param mask Interrupts to disable, it is the OR'ed value of @ref + * _flexio_mculcd_interrupt_enable. + */ +void FLEXIO_MCULCD_DisableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO MCULCD transmit DMA. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param mask MCULCD DMA source. + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void FLEXIO_MCULCD_EnableTxDMA(FLEXIO_MCULCD_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, (1U << base->txShifterStartIndex), enable); +} + +/*! + * @brief Enables/disables the FlexIO MCULCD receive DMA. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param mask MCULCD DMA source. + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void FLEXIO_MCULCD_EnableRxDMA(FLEXIO_MCULCD_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, (1U << base->rxShifterEndIndex), enable); +} + +/*! + * @brief Gets the FlexIO MCULCD transmit data register address. + * + * This function returns the MCULCD data register address, which is mainly used + * by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @return FlexIO MCULCD transmit data register address. + */ +static inline uint32_t FLEXIO_MCULCD_GetTxDataRegisterAddress(FLEXIO_MCULCD_Type *base) +{ + return (uint32_t) & (base->flexioBase->SHIFTBUF[base->txShifterStartIndex]); +} + +/*! + * @brief Gets the FlexIO MCULCD receive data register address. + * + * This function returns the MCULCD data register address, which is mainly used + * by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @return FlexIO MCULCD receive data register address. + */ +static inline uint32_t FLEXIO_MCULCD_GetRxDataRegisterAddress(FLEXIO_MCULCD_Type *base) +{ + return (uint32_t) & (base->flexioBase->SHIFTBUF[base->rxShifterStartIndex]); +} + +/*@}*/ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Set desired baud rate. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param baudRate_Bps Desired baud rate. + * @param srcClock_Hz FLEXIO clock frequency in Hz. + * @retval kStatus_Success Set successfully. + * @retval kStatus_InvalidArgument Could not set the baud rate. + */ +status_t FLEXIO_MCULCD_SetBaudRate(FLEXIO_MCULCD_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Configures the FLEXIO MCULCD to multiple beats write mode. + * + * At the begining multiple beats write operation, the FLEXIO MCULCD is configured to + * multiple beats write mode using this function. After write operation, the configuration + * is cleared by @ref FLEXIO_MCULCD_ClearSingleBeatWriteConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Clear the FLEXIO MCULCD multiple beats write mode configuration. + * + * Clear the write configuration set by @ref FLEXIO_MCULCD_SetSingleBeatWriteConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Configures the FLEXIO MCULCD to multiple beats read mode. + * + * At the begining or multiple beats read operation, the FLEXIO MCULCD is configured + * to multiple beats read mode using this function. After read operation, the configuration + * is cleared by @ref FLEXIO_MCULCD_ClearSingleBeatReadConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetSingleBeatReadConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Clear the FLEXIO MCULCD multiple beats read mode configuration. + * + * Clear the read configuration set by @ref FLEXIO_MCULCD_SetSingleBeatReadConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearSingleBeatReadConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Configures the FLEXIO MCULCD to multiple beats write mode. + * + * At the begining multiple beats write operation, the FLEXIO MCULCD is configured to + * multiple beats write mode using this function. After write operation, the configuration + * is cleared by @ref FLEXIO_MCULCD_ClearMultBeatsWriteConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Clear the FLEXIO MCULCD multiple beats write mode configuration. + * + * Clear the write configuration set by @ref FLEXIO_MCULCD_SetMultBeatsWriteConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Configures the FLEXIO MCULCD to multiple beats read mode. + * + * At the begining or multiple beats read operation, the FLEXIO MCULCD is configured + * to multiple beats read mode using this function. After read operation, the configuration + * is cleared by @ref FLEXIO_MCULCD_ClearMultBeatsReadConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Clear the FLEXIO MCULCD multiple beats read mode configuration. + * + * Clear the read configuration set by @ref FLEXIO_MCULCD_SetMultBeatsReadConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Enables/disables the FlexIO MCULCD module operation. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * @param enable True to enable, false does not have any effect. + */ +static inline void FLEXIO_MCULCD_Enable(FLEXIO_MCULCD_Type *base, bool enable) +{ + if (enable) + { + FLEXIO_Enable(base->flexioBase, enable); + } +} + +/*! + * @brief Read data from the FLEXIO MCULCD RX shifter buffer. + * + * Read data from the RX shift buffer directly, it does no check whether the + * buffer is empty or not. + * + * If the data bus width is 8-bit: + * @code + * uint8_t value; + * value = (uint8_t)FLEXIO_MCULCD_ReadData(base); + * @endcode + * + * If the data bus width is 16-bit: + * @code + * uint16_t value; + * value = (uint16_t)FLEXIO_MCULCD_ReadData(base); + * @endcode + * + * @note This function returns the RX shifter buffer value (32-bit) directly. + * The return value should be converted according to data bus width. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @return The data read out. + * + * @note Don't use this function with DMA APIs. + */ +uint32_t FLEXIO_MCULCD_ReadData(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Write data into the FLEXIO MCULCD TX shifter buffer. + * + * Write data into the TX shift buffer directly, it does no check whether the + * buffer is full or not. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param data The data to write. + * + * @note Don't use this function with DMA APIs. + */ +static inline void FLEXIO_MCULCD_WriteData(FLEXIO_MCULCD_Type *base, uint32_t data) +{ + base->flexioBase->SHIFTBUF[base->txShifterStartIndex] = data; +} + +/*! + * @brief Assert the nCS to start transfer. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + */ +static inline void FLEXIO_MCULCD_StartTransfer(FLEXIO_MCULCD_Type *base) +{ + base->setCSPin(false); +} + +/*! + * @brief De-assert the nCS to stop transfer. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + */ +static inline void FLEXIO_MCULCD_StopTransfer(FLEXIO_MCULCD_Type *base) +{ + base->setCSPin(true); +} + +/*! + * @brief Wait for transmit data send out finished. + * + * Currently there is no effective method to wait for the data send out + * from the shiter, so here use a while loop to wait. + * + * @note This is an internal used function. + */ +void FLEXIO_MCULCD_WaitTransmitComplete(void); + +/*! + * @brief Send command in blocking way. + * + * This function sends the command and returns when the command has been sent + * out. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param command The command to send. + */ +void FLEXIO_MCULCD_WriteCommandBlocking(FLEXIO_MCULCD_Type *base, uint32_t command); + +/*! + * @brief Send data array in blocking way. + * + * This function sends the data array and returns when the data sent out. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param data The data array to send. + * @param size How many bytes to write. + */ +void FLEXIO_MCULCD_WriteDataArrayBlocking(FLEXIO_MCULCD_Type *base, void *data, size_t size); + +/*! + * @brief Read data into array in blocking way. + * + * This function reads the data into array and returns when the data read + * finished. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param data The array to save the data. + * @param size How many bytes to read. + */ +void FLEXIO_MCULCD_ReadDataArrayBlocking(FLEXIO_MCULCD_Type *base, void *data, size_t size); + +/*! + * @brief Send the same value many times in blocking way. + * + * This function sends the same value many times. It could be used to clear the + * LCD screen. If the data bus width is 8, this function will send LSB 8 bits of + * @p sameValue for @p size times. If the data bus is 16, this function will send + * LSB 16 bits of @p sameValue for @p size / 2 times. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param sameValue The same value to send. + * @param size How many bytes to send. + */ +void FLEXIO_MCULCD_WriteSameValueBlocking(FLEXIO_MCULCD_Type *base, uint32_t sameValue, size_t size); + +/*! + * @brief Performs a polling transfer. + * + * @note The API does not return until the transfer finished. + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param xfer pointer to flexio_mculcd_transfer_t structure. + */ +void FLEXIO_MCULCD_TransferBlocking(FLEXIO_MCULCD_Type *base, flexio_mculcd_transfer_t *xfer); +/*@}*/ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the FlexIO MCULCD handle, which is used in transactional + * functions. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_MCULCD_TransferCreateHandle(FLEXIO_MCULCD_Type *base, + flexio_mculcd_handle_t *handle, + flexio_mculcd_transfer_callback_t callback, + void *userData); + +/*! + * @brief Transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which + * returns right away. When all data is sent out/received, the callback + * function is called. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + * @param xfer FlexIO MCULCD transfer structure. See #flexio_mculcd_transfer_t. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_MCULCD_Busy MCULCD is busy with another transfer. + */ +status_t FLEXIO_MCULCD_TransferNonBlocking(FLEXIO_MCULCD_Type *base, + flexio_mculcd_handle_t *handle, + flexio_mculcd_transfer_t *xfer); + +/*! + * @brief Aborts the data transfer, which used IRQ. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + */ +void FLEXIO_MCULCD_TransferAbort(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle); + +/*! + * @brief Gets the data transfer status which used IRQ. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + * @param count How many bytes transferred so far by the non-blocking transaction. + * @retval kStatus_Success Get the transferred count Successfully. + * @retval kStatus_NoTransferInProgress No transfer in process. + */ +status_t FLEXIO_MCULCD_TransferGetCount(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle, size_t *count); + +/*! + * @brief FlexIO MCULCD IRQ handler function. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + */ +void FLEXIO_MCULCD_TransferHandleIRQ(void *base, void *handle); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /*_FSL_FLEXIO_MCULCD_H_*/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_mculcd_edma.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_mculcd_edma.c new file mode 100644 index 0000000000..0b5187833f --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_mculcd_edma.c @@ -0,0 +1,564 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_mculcd_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_mculcd_edma" +#endif + +#define EDMA_MAX_MAJOR_COUNT (DMA_CITER_ELINKNO_CITER_MASK >> DMA_CITER_ELINKNO_CITER_SHIFT) + +enum _MCULCD_transfer_state +{ + kFLEXIO_MCULCD_StateIdle, /*!< No transfer in progress. */ + kFLEXIO_MCULCD_StateReadArray, /*!< Reading array in progress. */ + kFLEXIO_MCULCD_StateWriteArray, /*!< Writing array in progress. */ + kFLEXIO_MCULCD_StateWriteSameValue, /*!< Writing the same value in progress. + */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief EDMA callback function for FLEXIO MCULCD TX. + * + * For details, see @ref edma_callback. + */ +static void FLEXIO_MCULCD_TxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds); + +/*! + * @brief EDMA callback function for FLEXIO MCULCD RX. + * + * For details, see @ref edma_callback. + */ +static void FLEXIO_MCULCD_RxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds); + +/*! + * @brief Set EDMA config for FLEXIO MCULCD transfer. + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param handle pointer to flexio_mculcd_edma_handle_t structure to store the + * transfer state. + */ +static void FLEXIO_MCULCD_EDMAConfig(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle); + +/*! + * @brief Convert the FlexIO shifter number to eDMA modulo. + * + * @param shifterNum The FlexIO shifter number. + * @param modulo The modulo number. + * @retval Get the modulo successfully. + * @retval Could not get the modulo for the shifter number. + */ +static bool FLEXIO_MCULCD_GetEDMAModulo(uint8_t shifterNum, edma_modulo_t *modulo); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void FLEXIO_MCULCD_TxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds) +{ + tcds = tcds; + flexio_mculcd_edma_handle_t *flexioLcdMcuHandle = (flexio_mculcd_edma_handle_t *)param; + FLEXIO_MCULCD_Type *flexioLcdMcuBase = flexioLcdMcuHandle->base; + + if (transferDone) + { + if (flexioLcdMcuHandle->remainingCount >= flexioLcdMcuHandle->minorLoopBytes) + { + FLEXIO_MCULCD_EDMAConfig(flexioLcdMcuBase, flexioLcdMcuHandle); + EDMA_StartTransfer(flexioLcdMcuHandle->txDmaHandle); + } + else + { + FLEXIO_MCULCD_EnableTxDMA(flexioLcdMcuBase, false); + + /* Now the data are in shifter, wait for the data send out from the shifter. */ + FLEXIO_MCULCD_WaitTransmitComplete(); + + /* Disable the TX shifter and the timer. */ + FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(flexioLcdMcuBase); + + /* Send the remaining data. */ + if (flexioLcdMcuHandle->remainingCount) + { + if (kFLEXIO_MCULCD_StateWriteSameValue == flexioLcdMcuHandle->state) + { + FLEXIO_MCULCD_WriteSameValueBlocking(flexioLcdMcuBase, flexioLcdMcuHandle->dataAddrOrSameValue, + flexioLcdMcuHandle->remainingCount); + } + else + { + FLEXIO_MCULCD_WriteDataArrayBlocking(flexioLcdMcuBase, + (void *)flexioLcdMcuHandle->dataAddrOrSameValue, + flexioLcdMcuHandle->remainingCount); + } + } + + /* De-assert nCS. */ + FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase); + + /* Change the state. */ + flexioLcdMcuHandle->state = kFLEXIO_MCULCD_StateIdle; + flexioLcdMcuHandle->dataCount = 0; + flexioLcdMcuHandle->remainingCount = 0; + + /* Callback to inform upper layer. */ + if (flexioLcdMcuHandle->completionCallback) + { + flexioLcdMcuHandle->completionCallback(flexioLcdMcuBase, flexioLcdMcuHandle, kStatus_FLEXIO_MCULCD_Idle, + flexioLcdMcuHandle->userData); + } + } + } +} + +static void FLEXIO_MCULCD_RxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds) +{ + tcds = tcds; + uint32_t i; + uint32_t rxBufAddr; + flexio_mculcd_edma_handle_t *flexioLcdMcuHandle = (flexio_mculcd_edma_handle_t *)param; + FLEXIO_MCULCD_Type *flexioLcdMcuBase = flexioLcdMcuHandle->base; + FLEXIO_Type *flexioBase = flexioLcdMcuBase->flexioBase; + + if (transferDone) + { + if (flexioLcdMcuHandle->remainingCount >= (2 * flexioLcdMcuHandle->minorLoopBytes)) + { + FLEXIO_MCULCD_EDMAConfig(flexioLcdMcuBase, flexioLcdMcuHandle); + EDMA_StartTransfer(flexioLcdMcuHandle->rxDmaHandle); + } + else + { + FLEXIO_MCULCD_EnableRxDMA(flexioLcdMcuBase, false); + + /* Wait the data saved to the shifter buffer. */ + while (!((1U << flexioLcdMcuBase->rxShifterEndIndex) & FLEXIO_GetShifterStatusFlags(flexioBase))) + { + } + + /* Disable the RX shifter and the timer. */ + FLEXIO_MCULCD_ClearMultiBeatsReadConfig(flexioLcdMcuBase); + + rxBufAddr = FLEXIO_MCULCD_GetRxDataRegisterAddress(flexioLcdMcuBase); + +/* Read out the data. */ +#if (defined(__CORTEX_M) && (__CORTEX_M == 0)) + /* Cortex M0 and M0+ only support aligned access. */ + for (i = 0; i < flexioLcdMcuHandle->rxShifterNum * 4; i++) + { + ((uint8_t *)(flexioLcdMcuHandle->dataAddrOrSameValue))[i] = ((volatile uint8_t *)rxBufAddr)[i]; + } +#else + for (i = 0; i < flexioLcdMcuHandle->rxShifterNum; i++) + { + ((uint32_t *)(flexioLcdMcuHandle->dataAddrOrSameValue))[i] = ((volatile uint32_t *)rxBufAddr)[i]; + } +#endif + flexioLcdMcuHandle->remainingCount -= flexioLcdMcuHandle->minorLoopBytes; + + if (flexioLcdMcuHandle->remainingCount) + { + FLEXIO_MCULCD_ReadDataArrayBlocking( + flexioLcdMcuBase, + (void *)(flexioLcdMcuHandle->dataAddrOrSameValue + flexioLcdMcuHandle->minorLoopBytes), + flexioLcdMcuHandle->remainingCount); + } + + /* De-assert nCS. */ + FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase); + + /* Change the state. */ + flexioLcdMcuHandle->state = kFLEXIO_MCULCD_StateIdle; + flexioLcdMcuHandle->dataCount = 0; + flexioLcdMcuHandle->remainingCount = 0; + + /* Callback to inform upper layer. */ + if (flexioLcdMcuHandle->completionCallback) + { + flexioLcdMcuHandle->completionCallback(flexioLcdMcuBase, flexioLcdMcuHandle, kStatus_FLEXIO_MCULCD_Idle, + flexioLcdMcuHandle->userData); + } + } + } +} + +static void FLEXIO_MCULCD_EDMAConfig(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle) +{ + edma_transfer_config_t xferConfig = {0}; + edma_transfer_size_t transferSize = kEDMA_TransferSize1Bytes; + int16_t offset; + uint32_t majorLoopCounts; + uint32_t transferCount; + +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + transferSize = kEDMA_TransferSize1Bytes; + offset = 1; +#else + transferSize = kEDMA_TransferSize2Bytes; + offset = 2; +#endif + + majorLoopCounts = handle->remainingCount / handle->minorLoopBytes; + + /* For reading, the last minor loop data is not tranfered by DMA. */ + if (kFLEXIO_MCULCD_StateReadArray == handle->state) + { + majorLoopCounts--; + } + + if (majorLoopCounts > EDMA_MAX_MAJOR_COUNT) + { + majorLoopCounts = EDMA_MAX_MAJOR_COUNT; + } + + transferCount = majorLoopCounts * handle->minorLoopBytes; + + if (kFLEXIO_MCULCD_StateReadArray == handle->state) + { + xferConfig.srcAddr = FLEXIO_MCULCD_GetRxDataRegisterAddress(base); + xferConfig.destAddr = handle->dataAddrOrSameValue; + xferConfig.srcTransferSize = kEDMA_TransferSize4Bytes; + xferConfig.destTransferSize = transferSize; + xferConfig.srcOffset = 4; + xferConfig.destOffset = offset; + xferConfig.minorLoopBytes = handle->minorLoopBytes; + xferConfig.majorLoopCounts = majorLoopCounts; + handle->remainingCount -= transferCount; + handle->dataAddrOrSameValue += transferCount; + EDMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); + EDMA_SetModulo(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, handle->rxEdmaModulo, + kEDMA_ModuloDisable); + } + else + { + if (kFLEXIO_MCULCD_StateWriteArray == handle->state) + { + xferConfig.srcAddr = handle->dataAddrOrSameValue; + xferConfig.srcOffset = offset; + handle->dataAddrOrSameValue += transferCount; + } + else + { + xferConfig.srcAddr = (uint32_t)(&(handle->dataAddrOrSameValue)); + xferConfig.srcOffset = 0; + } + xferConfig.destAddr = FLEXIO_MCULCD_GetTxDataRegisterAddress(base); + xferConfig.srcTransferSize = transferSize; + xferConfig.destTransferSize = kEDMA_TransferSize4Bytes; + xferConfig.destOffset = 4; + xferConfig.minorLoopBytes = handle->minorLoopBytes; + xferConfig.majorLoopCounts = majorLoopCounts; + handle->remainingCount -= transferCount; + EDMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); + EDMA_SetModulo(handle->txDmaHandle->base, handle->txDmaHandle->channel, kEDMA_ModuloDisable, + handle->txEdmaModulo); + } +} + +static bool FLEXIO_MCULCD_GetEDMAModulo(uint8_t shifterNum, edma_modulo_t *modulo) +{ + bool ret = true; + + switch (shifterNum) + { + case 1U: + *modulo = kEDMA_Modulo4bytes; + break; + case 2U: + *modulo = kEDMA_Modulo8bytes; + break; + case 4U: + *modulo = kEDMA_Modulo16bytes; + break; + case 8U: + *modulo = kEDMA_Modulo32bytes; + break; + default: + ret = false; + break; + } + + return ret; +} + +/*! + * brief Initializes the FLEXO MCULCD master eDMA handle. + * + * This function initializes the FLEXO MCULCD master eDMA handle which can be + * used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD + * instance, call this API once to get the initialized handle. + * + * param base Pointer to FLEXIO_MCULCD_Type structure. + * param handle Pointer to flexio_mculcd_edma_handle_t structure to store the + * transfer state. + * param callback MCULCD transfer complete callback, NULL means no callback. + * param userData callback function parameter. + * param txDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA TX, + * the DMA request source of this handle should be the first of TX shifters. + * param rxDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA RX, + * the DMA request source of this handle should be the last of RX shifters. + * retval kStatus_Success Successfully create the handle. + */ +status_t FLEXIO_MCULCD_TransferCreateHandleEDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + flexio_mculcd_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txDmaHandle, + edma_handle_t *rxDmaHandle) +{ + assert(handle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Initialize the state. */ + handle->state = kFLEXIO_MCULCD_StateIdle; + + /* Register callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + handle->base = base; + handle->txShifterNum = base->txShifterEndIndex - base->txShifterStartIndex + 1U; + handle->rxShifterNum = base->rxShifterEndIndex - base->rxShifterStartIndex + 1U; + + if (rxDmaHandle) + { + if (!FLEXIO_MCULCD_GetEDMAModulo(handle->rxShifterNum, &handle->rxEdmaModulo)) + { + return kStatus_InvalidArgument; + } + + handle->rxDmaHandle = rxDmaHandle; + EDMA_SetCallback(rxDmaHandle, FLEXIO_MCULCD_RxEDMACallback, handle); + } + + if (txDmaHandle) + { + if (!FLEXIO_MCULCD_GetEDMAModulo(handle->txShifterNum, &handle->txEdmaModulo)) + { + return kStatus_InvalidArgument; + } + + handle->txDmaHandle = txDmaHandle; + EDMA_SetCallback(txDmaHandle, FLEXIO_MCULCD_TxEDMACallback, handle); + } + + return kStatus_Success; +} + +/*! + * brief Performs a non-blocking FlexIO MCULCD transfer using eDMA. + * + * This function returns immediately after transfer initiates. To check whether + * the transfer is completed, user could: + * 1. Use the transfer completed callback; + * 2. Polling function ref FLEXIO_MCULCD_GetTransferCountEDMA + * + * param base pointer to FLEXIO_MCULCD_Type structure. + * param handle pointer to flexio_mculcd_edma_handle_t structure to store the + * transfer state. + * param xfer Pointer to FlexIO MCULCD transfer structure. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another + * transfer. + */ +status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + flexio_mculcd_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + /* + * The data transfer mechanism: + * + * Read: + * Assume the data length is Lr = (n1 * minorLoopBytes + n2), where + * n2 < minorLoopBytes. + * If (n1 <= 1), then all data are sent using blocking method. + * If (n1 > 1), then the beginning ((n1-1) * minorLoopBytes) are read + * using DMA, the left (minorLoopBytes + n2) are read using blocking method. + * + * Write: + * Assume the data length is Lw = (n1 * minorLoopBytes + n2), where + * n2 < minorLoopBytes. + * If (n1 = 0), then all data are sent using blocking method. + * If (n1 >= 1), then the beginning (n1 * minorLoopBytes) are sent + * using DMA, the left n2 are sent using blocking method. + */ + + /* Check if the device is busy. */ + if (kFLEXIO_MCULCD_StateIdle != handle->state) + { + return kStatus_FLEXIO_MCULCD_Busy; + } + + /* Set the state in handle. */ + if (kFLEXIO_MCULCD_ReadArray == xfer->mode) + { + handle->state = kFLEXIO_MCULCD_StateReadArray; + handle->minorLoopBytes = handle->rxShifterNum * 4U; + } + else + { + handle->minorLoopBytes = handle->txShifterNum * 4U; + + if (kFLEXIO_MCULCD_WriteArray == xfer->mode) + { + handle->state = kFLEXIO_MCULCD_StateWriteArray; + } + else + { + handle->state = kFLEXIO_MCULCD_StateWriteSameValue; + } + } + + /* + * For TX, if data is less than one minor loop, then use polling method. + * For RX, if data is less than two minor loop, then use polling method. + */ + if ((xfer->dataSize < handle->minorLoopBytes) || + ((kFLEXIO_MCULCD_ReadArray == xfer->mode) && (xfer->dataSize < 2 * (handle->minorLoopBytes)))) + { + FLEXIO_MCULCD_TransferBlocking(base, xfer); + + handle->state = kFLEXIO_MCULCD_StateIdle; + + /* Callback to inform upper layer. */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_FLEXIO_MCULCD_Idle, handle->userData); + } + } + else + { + handle->dataCount = xfer->dataSize; + handle->remainingCount = xfer->dataSize; + handle->dataAddrOrSameValue = xfer->dataAddrOrSameValue; + + /* Setup DMA to transfer data. */ + /* Assert the nCS. */ + FLEXIO_MCULCD_StartTransfer(base); + /* Send the command. */ + FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + + /* Setup the DMA configuration. */ + FLEXIO_MCULCD_EDMAConfig(base, handle); + + /* Start the transfer. */ + if (kFLEXIO_MCULCD_ReadArray == xfer->mode) + { + /* For 6800, assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(true); + } + FLEXIO_MCULCD_SetMultiBeatsReadConfig(base); + FLEXIO_MCULCD_EnableRxDMA(base, true); + EDMA_StartTransfer(handle->rxDmaHandle); + } + else + { + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + FLEXIO_MCULCD_SetMultiBeatsWriteConfig(base); + FLEXIO_MCULCD_EnableTxDMA(base, true); + EDMA_StartTransfer(handle->txDmaHandle); + } + } + + return kStatus_Success; +} + +/*! + * brief Aborts a FlexIO MCULCD transfer using eDMA. + * + * param base pointer to FLEXIO_MCULCD_Type structure. + * param handle FlexIO MCULCD eDMA handle pointer. + */ +void FLEXIO_MCULCD_TransferAbortEDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma. */ + if (handle->txDmaHandle) + { + EDMA_AbortTransfer(handle->txDmaHandle); + } + if (handle->rxDmaHandle) + { + EDMA_AbortTransfer(handle->rxDmaHandle); + } + + /* Disable DMA enable bit. */ + FLEXIO_MCULCD_EnableTxDMA(handle->base, false); + FLEXIO_MCULCD_EnableRxDMA(handle->base, false); + + /* Set the handle state. */ + handle->state = kFLEXIO_MCULCD_StateIdle; + handle->dataCount = 0; +} + +/*! + * brief Gets the remaining bytes for FlexIO MCULCD eDMA transfer. + * + * param base pointer to FLEXIO_MCULCD_Type structure. + * param handle FlexIO MCULCD eDMA handle pointer. + * param count Number of count transferred so far by the eDMA transaction. + * retval kStatus_Success Get the transferred count Successfully. + * retval kStatus_NoTransferInProgress No transfer in process. + */ +status_t FLEXIO_MCULCD_TransferGetCountEDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + size_t *count) +{ + assert(handle); + assert(count); + uint32_t state = handle->state; + + if (kFLEXIO_MCULCD_StateIdle == state) + { + return kStatus_NoTransferInProgress; + } + else + { + *count = handle->dataCount - handle->remainingCount; + + if (kFLEXIO_MCULCD_StateReadArray == state) + { + *count -= handle->minorLoopBytes * + EDMA_GetRemainingMajorLoopCount(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + } + else + { + *count -= handle->minorLoopBytes * + EDMA_GetRemainingMajorLoopCount(handle->txDmaHandle->base, handle->txDmaHandle->channel); + } + } + + return kStatus_Success; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_mculcd_edma.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_mculcd_edma.h new file mode 100644 index 0000000000..c9b000b400 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_mculcd_edma.h @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_FLEXIO_MCULCD_EDMA_H_ +#define _FSL_FLEXIO_MCULCD_EDMA_H_ + +#include "fsl_edma.h" +#include "fsl_flexio_mculcd.h" + +/*! + * @addtogroup flexio_edma_mculcd + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*@{*/ +/*! @brief FlexIO MCULCD EDMA driver version 2.0.2. */ +#define FSL_FLEXIO_MCULCD_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! @brief typedef for flexio_mculcd_edma_handle_t in advance. */ +typedef struct _flexio_mculcd_edma_handle flexio_mculcd_edma_handle_t; + +/*! @brief FlexIO MCULCD master callback for transfer complete. + * + * When transfer finished, the callback function is called and returns the + * @p status as kStatus_FLEXIO_MCULCD_Idle. + */ +typedef void (*flexio_mculcd_edma_transfer_callback_t)(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO MCULCD eDMA transfer handle, users should not touch the + * content of the handle.*/ +struct _flexio_mculcd_edma_handle +{ + FLEXIO_MCULCD_Type *base; /*!< Pointer to the FLEXIO_MCULCD_Type. */ + uint8_t txShifterNum; /*!< Number of shifters used for TX. */ + uint8_t rxShifterNum; /*!< Number of shifters used for RX. */ + uint32_t minorLoopBytes; /*!< eDMA transfer minor loop bytes. */ + edma_modulo_t txEdmaModulo; /*!< Modulo value for the FlexIO shifter buffer access. */ + edma_modulo_t rxEdmaModulo; /*!< Modulo value for the FlexIO shifter buffer access. */ + uint32_t dataAddrOrSameValue; /*!< When sending the same value for many times, + this is the value to send. When writing or + reading array, this is the address of the + data array. */ + size_t dataCount; /*!< Total count to be transferred. */ + volatile size_t remainingCount; /*!< Remaining count still not transfered. */ + volatile uint32_t state; /*!< FlexIO MCULCD driver internal state. */ + edma_handle_t *txDmaHandle; /*!< DMA handle for MCULCD TX */ + edma_handle_t *rxDmaHandle; /*!< DMA handle for MCULCD RX */ + flexio_mculcd_edma_transfer_callback_t completionCallback; /*!< Callback for MCULCD DMA transfer */ + void *userData; /*!< User Data for MCULCD DMA callback */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA Transactional + * @{ + */ + +/*! + * @brief Initializes the FLEXO MCULCD master eDMA handle. + * + * This function initializes the FLEXO MCULCD master eDMA handle which can be + * used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD + * instance, call this API once to get the initialized handle. + * + * @param base Pointer to FLEXIO_MCULCD_Type structure. + * @param handle Pointer to flexio_mculcd_edma_handle_t structure to store the + * transfer state. + * @param callback MCULCD transfer complete callback, NULL means no callback. + * @param userData callback function parameter. + * @param txDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA TX, + * the DMA request source of this handle should be the first of TX shifters. + * @param rxDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA RX, + * the DMA request source of this handle should be the last of RX shifters. + * @retval kStatus_Success Successfully create the handle. + */ +status_t FLEXIO_MCULCD_TransferCreateHandleEDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + flexio_mculcd_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txDmaHandle, + edma_handle_t *rxDmaHandle); + +/*! + * @brief Performs a non-blocking FlexIO MCULCD transfer using eDMA. + * + * This function returns immediately after transfer initiates. To check whether + * the transfer is completed, user could: + * 1. Use the transfer completed callback; + * 2. Polling function @ref FLEXIO_MCULCD_GetTransferCountEDMA + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param handle pointer to flexio_mculcd_edma_handle_t structure to store the + * transfer state. + * @param xfer Pointer to FlexIO MCULCD transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another + * transfer. + */ +status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + flexio_mculcd_transfer_t *xfer); + +/*! + * @brief Aborts a FlexIO MCULCD transfer using eDMA. + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param handle FlexIO MCULCD eDMA handle pointer. + */ +void FLEXIO_MCULCD_TransferAbortEDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle); + +/*! + * @brief Gets the remaining bytes for FlexIO MCULCD eDMA transfer. + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param handle FlexIO MCULCD eDMA handle pointer. + * @param count Number of count transferred so far by the eDMA transaction. + * @retval kStatus_Success Get the transferred count Successfully. + * @retval kStatus_NoTransferInProgress No transfer in process. + */ +status_t FLEXIO_MCULCD_TransferGetCountEDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + size_t *count); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _FSL_FLEXIO_MCULCD_EDMA_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_spi.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_spi.c new file mode 100644 index 0000000000..f21de1fd02 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_spi.c @@ -0,0 +1,1239 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_spi.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_spi" +#endif + +/*! @brief FLEXIO SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */ +enum _flexio_spi_transfer_states +{ + kFLEXIO_SPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver's queue. */ + kFLEXIO_SPI_Busy, /*!< Transmiter/Receive's queue is not finished. */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Send a piece of data for SPI. + * + * This function computes the number of data to be written into D register or Tx FIFO, + * and write the data into it. At the same time, this function updates the values in + * master handle structure. + * + * @param base pointer to FLEXIO_SPI_Type structure + * @param handle Pointer to SPI master handle structure. + */ +static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); + +/*! + * @brief Receive a piece of data for SPI master. + * + * This function computes the number of data to receive from D register or Rx FIFO, + * and write the data to destination address. At the same time, this function updates + * the values in master handle structure. + * + * @param base pointer to FLEXIO_SPI_Type structure + * @param handle Pointer to SPI master handle structure. + */ +static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Codes + ******************************************************************************/ + +static uint32_t FLEXIO_SPI_GetInstance(FLEXIO_SPI_Type *base) +{ + return FLEXIO_GetInstance(base->flexioBase); +} + +static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) +{ + uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; + + if (handle->txData != NULL) + { + /* Transmit data and update tx size/buff. */ + if (handle->bytePerFrame == 1U) + { + tmpData = *(handle->txData); + handle->txData++; + } + else + { + if (handle->direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(handle->txData[0]) << 8U; + tmpData += handle->txData[1]; + } + else + { + tmpData = (uint32_t)(handle->txData[1]) << 8U; + tmpData += handle->txData[0]; + } + handle->txData += 2U; + } + } + else + { + tmpData = FLEXIO_SPI_DUMMYDATA; + } + + handle->txRemainingBytes -= handle->bytePerFrame; + + FLEXIO_SPI_WriteData(base, handle->direction, tmpData); + + if (!handle->txRemainingBytes) + { + FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable); + } +} + +static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) +{ + uint16_t tmpData; + + tmpData = FLEXIO_SPI_ReadData(base, handle->direction); + + if (handle->rxData != NULL) + { + if (handle->bytePerFrame == 1U) + { + *handle->rxData = tmpData; + handle->rxData++; + } + else + { + if (handle->direction == kFLEXIO_SPI_MsbFirst) + { + *((uint16_t *)(handle->rxData)) = tmpData; + } + else + { + *((uint16_t *)(handle->rxData)) = (((tmpData << 8) & 0xff00U) | ((tmpData >> 8) & 0x00ffU)); + } + handle->rxData += 2U; + } + } + handle->rxRemainingBytes -= handle->bytePerFrame; +} + +/*! + * brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware, + * and configures the FlexIO SPI with FlexIO SPI master configuration. The + * configuration structure can be filled by the user, or be set with default values + * by the FLEXIO_SPI_MasterGetDefaultConfig(). + * + * note FlexIO SPI master only support CPOL = 0, which means clock inactive low. + * + * Example + code + FLEXIO_SPI_Type spiDev = { + .flexioBase = FLEXIO, + .SDOPinIndex = 0, + .SDIPinIndex = 1, + .SCKPinIndex = 2, + .CSnPinIndex = 3, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_spi_master_config_t config = { + .enableMaster = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 500000, + .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, + .direction = kFLEXIO_SPI_MsbFirst, + .dataMode = kFLEXIO_SPI_8BitMode + }; + FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz); + endcode + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param masterConfig Pointer to the flexio_spi_master_config_t structure. + * param srcClock_Hz FlexIO source clock in Hz. +*/ +void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(base); + assert(masterConfig); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t ctrlReg = 0; + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; + + /* Clear the shifterConfig & timerConfig struct. */ + memset(&shifterConfig, 0, sizeof(shifterConfig)); + memset(&timerConfig, 0, sizeof(timerConfig)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate flexio clock. */ + CLOCK_EnableClock(s_flexioClocks[FLEXIO_SPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Configure FLEXIO SPI Master */ + ctrlReg = base->flexioBase->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster)); + if (!masterConfig->enableInDoze) + { + ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->flexioBase->CTRL = ctrlReg; + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinSelect = base->SDOPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /* 2. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->SDIPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /*3. Configure the timer 0 for SCK. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinSelect = base->SCKPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + timerDiv = srcClock_Hz / masterConfig->baudRate_Bps; + timerDiv = timerDiv / 2 - 1; + + timerCmp = ((uint32_t)(masterConfig->dataMode * 2 - 1U)) << 8U; + timerCmp |= timerDiv; + + timerConfig.timerCompare = timerCmp; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); + + /* 4. Configure the timer 1 for CSn. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->timerIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinSelect = base->CSnPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + + timerConfig.timerCompare = 0xFFFFU; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); +} + +/*! + * brief Resets the FlexIO SPI timer and shifter config. + * + * param base Pointer to the FLEXIO_SPI_Type. + */ +void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base) +{ + base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; +} + +/*! + * brief Gets the default configuration to configure the FlexIO SPI master. The configuration + * can be used directly by calling the FLEXIO_SPI_MasterConfigure(). + * Example: + code + flexio_spi_master_config_t masterConfig; + FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig); + endcode + * param masterConfig Pointer to the flexio_spi_master_config_t structure. +*/ +void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig) +{ + assert(masterConfig); + + /* Initializes the configure structure to zero. */ + memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->enableMaster = true; + masterConfig->enableInDoze = false; + masterConfig->enableInDebug = true; + masterConfig->enableFastAccess = false; + /* Default baud rate 500kbps. */ + masterConfig->baudRate_Bps = 500000U; + /* Default CPHA = 0. */ + masterConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge; + /* Default bit count at 8. */ + masterConfig->dataMode = kFLEXIO_SPI_8BitMode; +} + +/*! + * brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware + * configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The + * configuration structure can be filled by the user, or be set with default values + * by the FLEXIO_SPI_SlaveGetDefaultConfig(). + * + * note Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored. + * FlexIO SPI slave only support CPOL = 0, which means clock inactive low. + * Example + code + FLEXIO_SPI_Type spiDev = { + .flexioBase = FLEXIO, + .SDOPinIndex = 0, + .SDIPinIndex = 1, + .SCKPinIndex = 2, + .CSnPinIndex = 3, + .shifterIndex = {0,1}, + .timerIndex = {0} + }; + flexio_spi_slave_config_t config = { + .enableSlave = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, + .direction = kFLEXIO_SPI_MsbFirst, + .dataMode = kFLEXIO_SPI_8BitMode + }; + FLEXIO_SPI_SlaveInit(&spiDev, &config); + endcode + * param base Pointer to the FLEXIO_SPI_Type structure. + * param slaveConfig Pointer to the flexio_spi_slave_config_t structure. +*/ +void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig) +{ + assert(base && slaveConfig); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t ctrlReg = 0; + + /* Clear the shifterConfig & timerConfig struct. */ + memset(&shifterConfig, 0, sizeof(shifterConfig)); + memset(&timerConfig, 0, sizeof(timerConfig)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate flexio clock. */ + CLOCK_EnableClock(s_flexioClocks[FLEXIO_SPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Configure FLEXIO SPI Slave */ + ctrlReg = base->flexioBase->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DBGE(slaveConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(slaveConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(slaveConfig->enableSlave)); + if (!slaveConfig->enableInDoze) + { + ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->flexioBase->CTRL = ctrlReg; + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinSelect = base->SDOPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /* 2. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->SDIPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /*3. Configure the timer 0 for shift clock. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->CSnPinIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->SCKPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerRisingEdge; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + /* The configuration kFLEXIO_TimerDisableOnTimerCompare only support continuous + PCS access, change to kFLEXIO_TimerDisableNever to enable discontinuous PCS access. */ + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + } + else + { + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTriggerFallingEdge; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + } + + timerConfig.timerCompare = slaveConfig->dataMode * 2 - 1U; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); +} + +/*! + * brief Gates the FlexIO clock. + * + * param base Pointer to the FLEXIO_SPI_Type. + */ +void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base) +{ + FLEXIO_SPI_MasterDeinit(base); +} + +/*! + * brief Gets the default configuration to configure the FlexIO SPI slave. The configuration + * can be used directly for calling the FLEXIO_SPI_SlaveConfigure(). + * Example: + code + flexio_spi_slave_config_t slaveConfig; + FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig); + endcode + * param slaveConfig Pointer to the flexio_spi_slave_config_t structure. +*/ +void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + + /* Initializes the configure structure to zero. */ + memset(slaveConfig, 0, sizeof(*slaveConfig)); + + slaveConfig->enableSlave = true; + slaveConfig->enableInDoze = false; + slaveConfig->enableInDebug = true; + slaveConfig->enableFastAccess = false; + /* Default CPHA = 0. */ + slaveConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge; + /* Default bit count at 8. */ + slaveConfig->dataMode = kFLEXIO_SPI_8BitMode; +} + +/*! + * brief Enables the FlexIO SPI interrupt. + * + * This function enables the FlexIO SPI interrupt. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param mask interrupt source. The parameter can be any combination of the following values: + * arg kFLEXIO_SPI_RxFullInterruptEnable + * arg kFLEXIO_SPI_TxEmptyInterruptEnable + */ +void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[0]); + } + if (mask & kFLEXIO_SPI_RxFullInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[1]); + } +} + +/*! + * brief Disables the FlexIO SPI interrupt. + * + * This function disables the FlexIO SPI interrupt. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param mask interrupt source The parameter can be any combination of the following values: + * arg kFLEXIO_SPI_RxFullInterruptEnable + * arg kFLEXIO_SPI_TxEmptyInterruptEnable + */ +void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_SPI_TxEmptyInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[0]); + } + if (mask & kFLEXIO_SPI_RxFullInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1 << base->shifterIndex[1]); + } +} + +/*! + * brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA, + * which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param mask SPI DMA source. + * param enable True means enable DMA, false means disable DMA. + */ +void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable) +{ + if (mask & kFLEXIO_SPI_TxDmaEnable) + { + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1U << base->shifterIndex[0], enable); + } + + if (mask & kFLEXIO_SPI_RxDmaEnable) + { + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1U << base->shifterIndex[1], enable); + } +} + +/*! + * brief Gets FlexIO SPI status flags. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * return status flag; Use the status flag to AND the following flag mask and get the status. + * arg kFLEXIO_SPI_TxEmptyFlag + * arg kFLEXIO_SPI_RxEmptyFlag + */ + +uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base) +{ + uint32_t shifterStatus = FLEXIO_GetShifterStatusFlags(base->flexioBase); + uint32_t status = 0; + + status = ((shifterStatus & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]); + status |= (((shifterStatus & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) << 1U); + + return status; +} + +/*! + * brief Clears FlexIO SPI status flags. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param mask status flag + * The parameter can be any combination of the following values: + * arg kFLEXIO_SPI_TxEmptyFlag + * arg kFLEXIO_SPI_RxEmptyFlag + */ + +void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_SPI_TxBufferEmptyFlag) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]); + } + if (mask & kFLEXIO_SPI_RxBufferFullFlag) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +/*! + * brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param baudRate_Bps Baud Rate needed in Hz. + * param srcClockHz SPI source clock frequency in Hz. + */ +void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz) +{ + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; + FLEXIO_Type *flexioBase = base->flexioBase; + + /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/ + timerDiv = srcClockHz / baudRate_Bps; + timerDiv = timerDiv / 2 - 1U; + + timerCmp = flexioBase->TIMCMP[base->timerIndex[0]]; + timerCmp &= 0xFF00U; + timerCmp |= timerDiv; + + flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; +} + +/*! + * brief Sends a buffer of data bytes. + * + * note This function blocks using the polling method until all bytes have been sent. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param direction Shift direction of MSB first or LSB first. + * param buffer The data bytes to send. + * param size The number of data bytes to send. + */ +void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + const uint8_t *buffer, + size_t size) +{ + assert(buffer); + assert(size); + + while (size--) + { + /* Wait until data transfer complete. */ + while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_TxBufferEmptyFlag)) + { + } + FLEXIO_SPI_WriteData(base, direction, *buffer++); + } +} + +/*! + * brief Receives a buffer of bytes. + * + * note This function blocks using the polling method until all bytes have been received. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param direction Shift direction of MSB first or LSB first. + * param buffer The buffer to store the received bytes. + * param size The number of data bytes to be received. + * param direction Shift direction of MSB first or LSB first. + */ +void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + uint8_t *buffer, + size_t size) +{ + assert(buffer); + assert(size); + + while (size--) + { + /* Wait until data transfer complete. */ + while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_RxBufferFullFlag)) + { + } + *buffer++ = FLEXIO_SPI_ReadData(base, direction); + } +} + +/*! + * brief Receives a buffer of bytes. + * + * note This function blocks via polling until all bytes have been received. + * + * param base pointer to FLEXIO_SPI_Type structure + * param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t. + */ +void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer) +{ + flexio_spi_shift_direction_t direction; + uint8_t bytesPerFrame; + uint32_t dataMode = 0; + uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]]; + uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; + + timerCmp &= 0x00FFU; + /* Configure the values in handle. */ + switch (xfer->flags) + { + case kFLEXIO_SPI_8bitMsb: + dataMode = (8 * 2 - 1U) << 8U; + bytesPerFrame = 1; + direction = kFLEXIO_SPI_MsbFirst; + break; + + case kFLEXIO_SPI_8bitLsb: + dataMode = (8 * 2 - 1U) << 8U; + bytesPerFrame = 1; + direction = kFLEXIO_SPI_LsbFirst; + break; + + case kFLEXIO_SPI_16bitMsb: + dataMode = (16 * 2 - 1U) << 8U; + bytesPerFrame = 2; + direction = kFLEXIO_SPI_MsbFirst; + break; + + case kFLEXIO_SPI_16bitLsb: + dataMode = (16 * 2 - 1U) << 8U; + bytesPerFrame = 2; + direction = kFLEXIO_SPI_LsbFirst; + break; + + default: + dataMode = (8 * 2 - 1U) << 8U; + bytesPerFrame = 1; + direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + dataMode |= timerCmp; + + /* Configure transfer size. */ + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + while (xfer->dataSize) + { + /* Wait until data transfer complete. */ + while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_TxBufferEmptyFlag)) + { + } + if (xfer->txData != NULL) + { + /* Transmit data and update tx size/buff. */ + if (bytesPerFrame == 1U) + { + tmpData = *(xfer->txData); + xfer->txData++; + } + else + { + if (direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(xfer->txData[0]) << 8U; + tmpData += xfer->txData[1]; + } + else + { + tmpData = (uint32_t)(xfer->txData[1]) << 8U; + tmpData += xfer->txData[0]; + } + xfer->txData += 2U; + } + } + else + { + tmpData = FLEXIO_SPI_DUMMYDATA; + } + + xfer->dataSize -= bytesPerFrame; + + FLEXIO_SPI_WriteData(base, direction, tmpData); + + while (!(FLEXIO_SPI_GetStatusFlags(base) & kFLEXIO_SPI_RxBufferFullFlag)) + { + } + tmpData = FLEXIO_SPI_ReadData(base, direction); + + if (xfer->rxData != NULL) + { + if (bytesPerFrame == 1U) + { + *xfer->rxData = tmpData; + xfer->rxData++; + } + else + { + if (direction == kFLEXIO_SPI_MsbFirst) + { + *((uint16_t *)(xfer->rxData)) = tmpData; + } + else + { + *((uint16_t *)(xfer->rxData)) = (((tmpData << 8) & 0xff00U) | ((tmpData >> 8) & 0x00ffU)); + } + xfer->rxData += 2U; + } + } + } +} + +/*! + * brief Initializes the FlexIO SPI Master handle, which is used in transactional functions. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * param callback The callback function. + * param userData The parameter of the callback function. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_master_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Register callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Enable interrupt in NVIC. */ + EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_MasterTransferHandleIRQ); +} + +/*! + * brief Master transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which returns + * right away. When all data is sent out/received, the callback function is called. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + uint32_t dataMode = 0; + uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]]; + uint16_t tmpData = FLEXIO_SPI_DUMMYDATA; + + timerCmp &= 0x00FFU; + + /* Check if SPI is busy. */ + if (handle->state == kFLEXIO_SPI_Busy) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* Check if the argument is legal. */ + if ((xfer->txData == NULL) && (xfer->rxData == NULL)) + { + return kStatus_InvalidArgument; + } + + /* Configure the values in handle */ + switch (xfer->flags) + { + case kFLEXIO_SPI_8bitMsb: + dataMode = (8 * 2 - 1U) << 8U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case kFLEXIO_SPI_8bitLsb: + dataMode = (8 * 2 - 1U) << 8U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + case kFLEXIO_SPI_16bitMsb: + dataMode = (16 * 2 - 1U) << 8U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case kFLEXIO_SPI_16bitLsb: + dataMode = (16 * 2 - 1U) << 8U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + default: + dataMode = (8 * 2 - 1U) << 8U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + dataMode |= timerCmp; + + /* Configure transfer size. */ + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + handle->state = kFLEXIO_SPI_Busy; + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + handle->rxRemainingBytes = xfer->dataSize; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Send first byte of data to trigger the rx interrupt. */ + if (handle->txData != NULL) + { + /* Transmit data and update tx size/buff. */ + if (handle->bytePerFrame == 1U) + { + tmpData = *(handle->txData); + handle->txData++; + } + else + { + if (handle->direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(handle->txData[0]) << 8U; + tmpData += handle->txData[1]; + } + else + { + tmpData = (uint32_t)(handle->txData[1]) << 8U; + tmpData += handle->txData[0]; + } + handle->txData += 2U; + } + } + else + { + tmpData = FLEXIO_SPI_DUMMYDATA; + } + + handle->txRemainingBytes = xfer->dataSize - handle->bytePerFrame; + + FLEXIO_SPI_WriteData(base, handle->direction, tmpData); + + /* Enable transmit and receive interrupt to handle rx. */ + FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable); + + return kStatus_Success; +} + +/*! + * brief Gets the data transfer status which used IRQ. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Return remaing bytes in different cases. */ + if (handle->rxData) + { + *count = handle->transferSize - handle->rxRemainingBytes; + } + else + { + *count = handle->transferSize - handle->txRemainingBytes; + } + + return kStatus_Success; +} + +/*! + * brief Aborts the master data transfer, which used IRQ. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) +{ + assert(handle); + + FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable); + FLEXIO_SPI_DisableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable); + + /* Transfer finished, set the state to idle. */ + handle->state = kFLEXIO_SPI_Idle; + + /* Clear the internal state. */ + handle->rxRemainingBytes = 0; + handle->txRemainingBytes = 0; +} + +/*! + * brief FlexIO SPI master IRQ handler function. + * + * param spiType Pointer to the FLEXIO_SPI_Type structure. + * param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle) +{ + assert(spiHandle); + + flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle; + FLEXIO_SPI_Type *base; + uint32_t status; + + if (handle->state == kFLEXIO_SPI_Idle) + { + return; + } + + base = (FLEXIO_SPI_Type *)spiType; + status = FLEXIO_SPI_GetStatusFlags(base); + + /* Handle rx. */ + if ((status & kFLEXIO_SPI_RxBufferFullFlag) && (handle->rxRemainingBytes)) + { + FLEXIO_SPI_TransferReceiveTransaction(base, handle); + } + + /* Handle tx. */ + if ((status & kFLEXIO_SPI_TxBufferEmptyFlag) && (handle->txRemainingBytes)) + { + FLEXIO_SPI_TransferSendTransaction(base, handle); + } + + /* All the transfer finished. */ + if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U)) + { + FLEXIO_SPI_MasterTransferAbort(base, handle); + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData); + } + } +} + +/*! + * brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * param callback The callback function. + * param userData The parameter of the callback function. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Register callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Enable interrupt in NVIC. */ + EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_SlaveTransferHandleIRQ); +} + +/*! + * brief Slave transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which returns + * right away. When all data is sent out/received, the callback function is called. + * param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer. + */ +status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + uint32_t dataMode = 0; + + /* Check if SPI is busy. */ + if (handle->state == kFLEXIO_SPI_Busy) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* Check if the argument is legal. */ + if ((xfer->txData == NULL) && (xfer->rxData == NULL)) + { + return kStatus_InvalidArgument; + } + + /* Configure the values in handle */ + switch (xfer->flags) + { + case kFLEXIO_SPI_8bitMsb: + dataMode = 8 * 2 - 1U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case kFLEXIO_SPI_8bitLsb: + dataMode = 8 * 2 - 1U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + case kFLEXIO_SPI_16bitMsb: + dataMode = 16 * 2 - 1U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case kFLEXIO_SPI_16bitLsb: + dataMode = 16 * 2 - 1U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + default: + dataMode = 8 * 2 - 1U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + /* Configure transfer size. */ + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + handle->state = kFLEXIO_SPI_Busy; + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + handle->txRemainingBytes = xfer->dataSize; + handle->rxRemainingBytes = xfer->dataSize; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Enable transmit and receive interrupt to handle tx and rx. */ + FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_TxEmptyInterruptEnable); + FLEXIO_SPI_EnableInterrupts(base, kFLEXIO_SPI_RxFullInterruptEnable); + + return kStatus_Success; +} + +/*! + * brief FlexIO SPI slave IRQ handler function. + * + * param spiType Pointer to the FLEXIO_SPI_Type structure. + * param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle) +{ + assert(spiHandle); + + flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle; + FLEXIO_SPI_Type *base; + uint32_t status; + + if (handle->state == kFLEXIO_SPI_Idle) + { + return; + } + + base = (FLEXIO_SPI_Type *)spiType; + status = FLEXIO_SPI_GetStatusFlags(base); + + /* Handle tx. */ + if ((status & kFLEXIO_SPI_TxBufferEmptyFlag) && (handle->txRemainingBytes)) + { + FLEXIO_SPI_TransferSendTransaction(base, handle); + } + + /* Handle rx. */ + if ((status & kFLEXIO_SPI_RxBufferFullFlag) && (handle->rxRemainingBytes)) + { + FLEXIO_SPI_TransferReceiveTransaction(base, handle); + } + + /* All the transfer finished. */ + if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U)) + { + FLEXIO_SPI_SlaveTransferAbort(base, handle); + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData); + } + } +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_spi.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_spi.h new file mode 100644 index 0000000000..575ac0bd14 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_spi.h @@ -0,0 +1,681 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_FLEXIO_SPI_H_ +#define _FSL_FLEXIO_SPI_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_spi + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO SPI driver version 2.1.3. */ +#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) +/*@}*/ + +#ifndef FLEXIO_SPI_DUMMYDATA +/*! @brief FlexIO SPI dummy transfer data, the data is sent while txData is NULL. */ +#define FLEXIO_SPI_DUMMYDATA (0xFFFFU) +#endif + +/*! @brief Error codes for the FlexIO SPI driver. */ +enum _flexio_spi_status +{ + kStatus_FLEXIO_SPI_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 1), /*!< FlexIO SPI is busy. */ + kStatus_FLEXIO_SPI_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 2), /*!< SPI is idle */ + kStatus_FLEXIO_SPI_Error = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 3), /*!< FlexIO SPI error. */ +}; + +/*! @brief FlexIO SPI clock phase configuration. */ +typedef enum _flexio_spi_clock_phase +{ + kFLEXIO_SPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SPSCK occurs at the middle of the first + * cycle of a data transfer. */ + kFLEXIO_SPI_ClockPhaseSecondEdge = 0x1U, /*!< First edge on SPSCK occurs at the start of the + * first cycle of a data transfer. */ +} flexio_spi_clock_phase_t; + +/*! @brief FlexIO SPI data shifter direction options. */ +typedef enum _flexio_spi_shift_direction +{ + kFLEXIO_SPI_MsbFirst = 0, /*!< Data transfers start with most significant bit. */ + kFLEXIO_SPI_LsbFirst = 1, /*!< Data transfers start with least significant bit. */ +} flexio_spi_shift_direction_t; + +/*! @brief FlexIO SPI data length mode options. */ +typedef enum _flexio_spi_data_bitcount_mode +{ + kFLEXIO_SPI_8BitMode = 0x08U, /*!< 8-bit data transmission mode. */ + kFLEXIO_SPI_16BitMode = 0x10U, /*!< 16-bit data transmission mode. */ +} flexio_spi_data_bitcount_mode_t; + +/*! @brief Define FlexIO SPI interrupt mask. */ +enum _flexio_spi_interrupt_enable +{ + kFLEXIO_SPI_TxEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ + kFLEXIO_SPI_RxFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO SPI status mask. */ +enum _flexio_spi_status_flags +{ + kFLEXIO_SPI_TxBufferEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ + kFLEXIO_SPI_RxBufferFullFlag = 0x2U, /*!< Receive buffer full flag. */ +}; + +/*! @brief Define FlexIO SPI DMA mask. */ +enum _flexio_spi_dma_enable +{ + kFLEXIO_SPI_TxDmaEnable = 0x1U, /*!< Tx DMA request source */ + kFLEXIO_SPI_RxDmaEnable = 0x2U, /*!< Rx DMA request source */ + kFLEXIO_SPI_DmaAllEnable = 0x3U, /*!< All DMA request source*/ +}; + +/*! @brief Define FlexIO SPI transfer flags. */ +enum _flexio_spi_transfer_flags +{ + kFLEXIO_SPI_8bitMsb = 0x1U, /*!< FlexIO SPI 8-bit MSB first */ + kFLEXIO_SPI_8bitLsb = 0x2U, /*!< FlexIO SPI 8-bit LSB first */ + kFLEXIO_SPI_16bitMsb = 0x9U, /*!< FlexIO SPI 16-bit MSB first */ + kFLEXIO_SPI_16bitLsb = 0xaU, /*!< FlexIO SPI 16-bit LSB first */ +}; + +/*! @brief Define FlexIO SPI access structure typedef. */ +typedef struct _flexio_spi_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ + uint8_t SDOPinIndex; /*!< Pin select for data output. */ + uint8_t SDIPinIndex; /*!< Pin select for data input. */ + uint8_t SCKPinIndex; /*!< Pin select for clock. */ + uint8_t CSnPinIndex; /*!< Pin select for enable. */ + uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO SPI. */ + uint8_t timerIndex[2]; /*!< Timer index used in FlexIO SPI. */ +} FLEXIO_SPI_Type; + +/*! @brief Define FlexIO SPI master configuration structure. */ +typedef struct _flexio_spi_master_config +{ + bool enableMaster; /*!< Enable/disable FlexIO SPI master after configuration. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, + fast access requires the FlexIO clock to be at least + twice the frequency of the bus clock. */ + uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ + flexio_spi_clock_phase_t phase; /*!< Clock phase. */ + flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */ +} flexio_spi_master_config_t; + +/*! @brief Define FlexIO SPI slave configuration structure. */ +typedef struct _flexio_spi_slave_config +{ + bool enableSlave; /*!< Enable/disable FlexIO SPI slave after configuration. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, + fast access requires the FlexIO clock to be at least + twice the frequency of the bus clock. */ + flexio_spi_clock_phase_t phase; /*!< Clock phase. */ + flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */ +} flexio_spi_slave_config_t; + +/*! @brief Define FlexIO SPI transfer structure. */ +typedef struct _flexio_spi_transfer +{ + uint8_t *txData; /*!< Send buffer. */ + uint8_t *rxData; /*!< Receive buffer. */ + size_t dataSize; /*!< Transfer bytes. */ + uint8_t flags; /*!< FlexIO SPI control flag, MSB first or LSB first. */ +} flexio_spi_transfer_t; + +/*! @brief typedef for flexio_spi_master_handle_t in advance. */ +typedef struct _flexio_spi_master_handle flexio_spi_master_handle_t; + +/*! @brief Slave handle is the same with master handle. */ +typedef flexio_spi_master_handle_t flexio_spi_slave_handle_t; + +/*! @brief FlexIO SPI master callback for finished transmit */ +typedef void (*flexio_spi_master_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO SPI slave callback for finished transmit */ +typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FlexIO SPI handle structure. */ +struct _flexio_spi_master_handle +{ + uint8_t *txData; /*!< Transfer buffer. */ + uint8_t *rxData; /*!< Receive buffer. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + volatile size_t txRemainingBytes; /*!< Send data remaining in bytes. */ + volatile size_t rxRemainingBytes; /*!< Receive data remaining in bytes. */ + volatile uint32_t state; /*!< FlexIO SPI internal state. */ + uint8_t bytePerFrame; /*!< SPI mode, 2bytes or 1byte in a frame */ + flexio_spi_shift_direction_t direction; /*!< Shift direction. */ + flexio_spi_master_transfer_callback_t callback; /*!< FlexIO SPI callback. */ + void *userData; /*!< Callback parameter. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name FlexIO SPI Configuration + * @{ + */ + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware, + * and configures the FlexIO SPI with FlexIO SPI master configuration. The + * configuration structure can be filled by the user, or be set with default values + * by the FLEXIO_SPI_MasterGetDefaultConfig(). + * + * @note FlexIO SPI master only support CPOL = 0, which means clock inactive low. + * + * Example + @code + FLEXIO_SPI_Type spiDev = { + .flexioBase = FLEXIO, + .SDOPinIndex = 0, + .SDIPinIndex = 1, + .SCKPinIndex = 2, + .CSnPinIndex = 3, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_spi_master_config_t config = { + .enableMaster = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 500000, + .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, + .direction = kFLEXIO_SPI_MsbFirst, + .dataMode = kFLEXIO_SPI_8BitMode + }; + FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz); + @endcode + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param masterConfig Pointer to the flexio_spi_master_config_t structure. + * @param srcClock_Hz FlexIO source clock in Hz. +*/ +void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Resets the FlexIO SPI timer and shifter config. + * + * @param base Pointer to the FLEXIO_SPI_Type. + */ +void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO SPI master. The configuration + * can be used directly by calling the FLEXIO_SPI_MasterConfigure(). + * Example: + @code + flexio_spi_master_config_t masterConfig; + FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig); + @endcode + * @param masterConfig Pointer to the flexio_spi_master_config_t structure. +*/ +void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig); + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware + * configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The + * configuration structure can be filled by the user, or be set with default values + * by the FLEXIO_SPI_SlaveGetDefaultConfig(). + * + * @note Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored. + * FlexIO SPI slave only support CPOL = 0, which means clock inactive low. + * Example + @code + FLEXIO_SPI_Type spiDev = { + .flexioBase = FLEXIO, + .SDOPinIndex = 0, + .SDIPinIndex = 1, + .SCKPinIndex = 2, + .CSnPinIndex = 3, + .shifterIndex = {0,1}, + .timerIndex = {0} + }; + flexio_spi_slave_config_t config = { + .enableSlave = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, + .direction = kFLEXIO_SPI_MsbFirst, + .dataMode = kFLEXIO_SPI_8BitMode + }; + FLEXIO_SPI_SlaveInit(&spiDev, &config); + @endcode + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure. +*/ +void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig); + +/*! + * @brief Gates the FlexIO clock. + * + * @param base Pointer to the FLEXIO_SPI_Type. + */ +void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO SPI slave. The configuration + * can be used directly for calling the FLEXIO_SPI_SlaveConfigure(). + * Example: + @code + flexio_spi_slave_config_t slaveConfig; + FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig); + @endcode + * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure. +*/ +void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig); + +/*@}*/ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets FlexIO SPI status flags. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @return status flag; Use the status flag to AND the following flag mask and get the status. + * @arg kFLEXIO_SPI_TxEmptyFlag + * @arg kFLEXIO_SPI_RxEmptyFlag + */ + +uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base); + +/*! + * @brief Clears FlexIO SPI status flags. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask status flag + * The parameter can be any combination of the following values: + * @arg kFLEXIO_SPI_TxEmptyFlag + * @arg kFLEXIO_SPI_RxEmptyFlag + */ + +void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO SPI interrupt. + * + * This function enables the FlexIO SPI interrupt. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask interrupt source. The parameter can be any combination of the following values: + * @arg kFLEXIO_SPI_RxFullInterruptEnable + * @arg kFLEXIO_SPI_TxEmptyInterruptEnable + */ +void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO SPI interrupt. + * + * This function disables the FlexIO SPI interrupt. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask interrupt source The parameter can be any combination of the following values: + * @arg kFLEXIO_SPI_RxFullInterruptEnable + * @arg kFLEXIO_SPI_TxEmptyInterruptEnable + */ +void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask); + +/*@}*/ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA, + * which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask SPI DMA source. + * @param enable True means enable DMA, false means disable DMA. + */ +void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable); + +/*! + * @brief Gets the FlexIO SPI transmit data register address for MSB first transfer. + * + * This function returns the SPI data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @return FlexIO SPI transmit data register address. + */ +static inline uint32_t FLEXIO_SPI_GetTxDataRegisterAddress(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, + base->shifterIndex[0]) + + 3U; + } + else + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]); + } +} + +/*! + * @brief Gets the FlexIO SPI receive data register address for the MSB first transfer. + * + * This function returns the SPI data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @return FlexIO SPI receive data register address. + */ +static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->shifterIndex[1]); + } + else + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[1]) + 3U; + } +} + +/*@}*/ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO SPI module operation. + * + * @param base Pointer to the FLEXIO_SPI_Type. + * @param enable True to enable, false does not have any effect. + */ +static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable) +{ + if (enable) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/*! + * @brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param baudRate_Bps Baud Rate needed in Hz. + * @param srcClockHz SPI source clock frequency in Hz. + */ +void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz); + +/*! + * @brief Writes one byte of data, which is sent using the MSB method. + * + * @note This is a non-blocking API, which returns directly after the data is put into the + * data register but the data transfer is not finished on the bus. Ensure that + * the TxEmptyFlag is asserted before calling this API. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @param data 8 bit/16 bit data. + */ +static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint16_t data) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data; + } + else + { + base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = data; + } +} + +/*! + * @brief Reads 8 bit/16 bit data. + * + * @note This is a non-blocking API, which returns directly after the data is read from the + * data register. Ensure that the RxFullFlag is asserted before calling this API. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @return 8 bit/16 bit data received. + */ +static inline uint16_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + return base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]; + } + else + { + return base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; + } +} + +/*! + * @brief Sends a buffer of data bytes. + * + * @note This function blocks using the polling method until all bytes have been sent. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @param buffer The data bytes to send. + * @param size The number of data bytes to send. + */ +void FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + const uint8_t *buffer, + size_t size); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks using the polling method until all bytes have been received. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @param buffer The buffer to store the received bytes. + * @param size The number of data bytes to be received. + * @param direction Shift direction of MSB first or LSB first. + */ +void FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + uint8_t *buffer, + size_t size); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks via polling until all bytes have been received. + * + * @param base pointer to FLEXIO_SPI_Type structure + * @param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t. + */ +void FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer); + +/*Transactional APIs*/ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the FlexIO SPI Master handle, which is used in transactional functions. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Master transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which returns + * right away. When all data is sent out/received, the callback function is called. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts the master data transfer, which used IRQ. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); + +/*! + * @brief Gets the data transfer status which used IRQ. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count); + +/*! + * @brief FlexIO SPI master IRQ handler function. + * + * @param spiType Pointer to the FLEXIO_SPI_Type structure. + * @param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle); + +/*! + * @brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Slave transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which returns + * right away. When all data is sent out/received, the callback function is called. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer. + */ +status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts the slave data transfer which used IRQ, share same API with master. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + */ +static inline void FLEXIO_SPI_SlaveTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle) +{ + FLEXIO_SPI_MasterTransferAbort(base, handle); +} +/*! + * @brief Gets the data transfer status which used IRQ, share same API with master. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + size_t *count) +{ + return FLEXIO_SPI_MasterTransferGetCount(base, handle, count); +} + +/*! + * @brief FlexIO SPI slave IRQ handler function. + * + * @param spiType Pointer to the FLEXIO_SPI_Type structure. + * @param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /*_FSL_FLEXIO_SPI_H_*/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_spi_edma.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_spi_edma.c new file mode 100644 index 0000000000..e680b53371 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_spi_edma.c @@ -0,0 +1,474 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_spi_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_spi_edma" +#endif + +/*base, kFLEXIO_SPI_TxDmaEnable, false); + + /* change the state */ + spiPrivateHandle->handle->txInProgress = false; + + /* All finished, call the callback */ + if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false)) + { + if (spiPrivateHandle->handle->callback) + { + (spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success, + spiPrivateHandle->handle->userData); + } + } + } +} + +static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + tcds = tcds; + flexio_spi_master_edma_private_handle_t *spiPrivateHandle = (flexio_spi_master_edma_private_handle_t *)param; + + if (transferDone) + { + /* Disable Rx dma */ + FLEXIO_SPI_EnableDMA(spiPrivateHandle->base, kFLEXIO_SPI_RxDmaEnable, false); + + /* change the state */ + spiPrivateHandle->handle->rxInProgress = false; + + /* All finished, call the callback */ + if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false)) + { + if (spiPrivateHandle->handle->callback) + { + (spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success, + spiPrivateHandle->handle->userData); + } + } + } +} + +static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + edma_transfer_config_t xferConfig = {0}; + flexio_spi_shift_direction_t direction = kFLEXIO_SPI_MsbFirst; + uint8_t bytesPerFrame; + + /* Configure the values in handle. */ + switch (xfer->flags) + { + case kFLEXIO_SPI_8bitMsb: + bytesPerFrame = 1; + direction = kFLEXIO_SPI_MsbFirst; + break; + case kFLEXIO_SPI_8bitLsb: + bytesPerFrame = 1; + direction = kFLEXIO_SPI_LsbFirst; + break; + case kFLEXIO_SPI_16bitMsb: + bytesPerFrame = 2; + direction = kFLEXIO_SPI_MsbFirst; + break; + case kFLEXIO_SPI_16bitLsb: + bytesPerFrame = 2; + direction = kFLEXIO_SPI_LsbFirst; + break; + default: + bytesPerFrame = 1U; + direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Configure tx transfer EDMA. */ + xferConfig.destAddr = FLEXIO_SPI_GetTxDataRegisterAddress(base, direction); + xferConfig.destOffset = 0; + if (bytesPerFrame == 1U) + { + xferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + xferConfig.destTransferSize = kEDMA_TransferSize1Bytes; + xferConfig.minorLoopBytes = 1; + } + else + { + if (direction == kFLEXIO_SPI_MsbFirst) + { + xferConfig.destAddr -= 1U; + } + xferConfig.srcTransferSize = kEDMA_TransferSize2Bytes; + xferConfig.destTransferSize = kEDMA_TransferSize2Bytes; + xferConfig.minorLoopBytes = 2; + } + + /* Configure DMA channel. */ + if (xfer->txData) + { + xferConfig.srcOffset = bytesPerFrame; + xferConfig.srcAddr = (uint32_t)(xfer->txData); + } + else + { + /* Disable the source increasement and source set to dummyData. */ + xferConfig.srcOffset = 0; + xferConfig.srcAddr = (uint32_t)(&s_dummyData); + } + + xferConfig.majorLoopCounts = (xfer->dataSize / xferConfig.minorLoopBytes); + + /* Store the initially configured eDMA minor byte transfer count into the FLEXIO SPI handle */ + handle->nbytes = xferConfig.minorLoopBytes; + + if (handle->txHandle) + { + EDMA_SubmitTransfer(handle->txHandle, &xferConfig); + } + + /* Configure tx transfer EDMA. */ + if (xfer->rxData) + { + xferConfig.srcAddr = FLEXIO_SPI_GetRxDataRegisterAddress(base, direction); + if (bytesPerFrame == 2U) + { + if (direction == kFLEXIO_SPI_LsbFirst) + { + xferConfig.srcAddr -= 1U; + } + } + xferConfig.srcOffset = 0; + xferConfig.destAddr = (uint32_t)(xfer->rxData); + xferConfig.destOffset = bytesPerFrame; + EDMA_SubmitTransfer(handle->rxHandle, &xferConfig); + handle->rxInProgress = true; + FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_RxDmaEnable, true); + EDMA_StartTransfer(handle->rxHandle); + } + + /* Always start Tx transfer. */ + if (handle->txHandle) + { + handle->txInProgress = true; + FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_TxDmaEnable, true); + EDMA_StartTransfer(handle->txHandle); + } +} + +/*! + * brief Initializes the FlexIO SPI master eDMA handle. + * + * This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master + * transactional + * APIs. + * For a specified FlexIO SPI instance, call this API once to get the initialized handle. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. + * param callback SPI callback, NULL means no callback. + * param userData callback function parameter. + * param txHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer. + * param rxHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range. + */ +status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txHandle, + edma_handle_t *rxHandle) +{ + assert(handle); + + uint8_t index = 0; + + /* Find the an empty handle pointer to store the handle. */ + for (index = 0; index < FLEXIO_SPI_HANDLE_COUNT; index++) + { + if (s_edmaPrivateHandle[index].base == NULL) + { + s_edmaPrivateHandle[index].base = base; + s_edmaPrivateHandle[index].handle = handle; + break; + } + } + + if (index == FLEXIO_SPI_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + + /* Set spi base to handle. */ + handle->txHandle = txHandle; + handle->rxHandle = rxHandle; + + /* Register callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Set SPI state to idle. */ + handle->txInProgress = false; + handle->rxInProgress = false; + + /* Install callback for Tx/Rx dma channel. */ + if (handle->txHandle) + { + EDMA_SetCallback(handle->txHandle, FLEXIO_SPI_TxEDMACallback, &s_edmaPrivateHandle[index]); + } + if (handle->rxHandle) + { + EDMA_SetCallback(handle->rxHandle, FLEXIO_SPI_RxEDMACallback, &s_edmaPrivateHandle[index]); + } + + return kStatus_Success; +} + +/*! + * brief Performs a non-blocking FlexIO SPI transfer using eDMA. + * + * note This interface returns immediately after transfer initiates. Call + * FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check + * whether the FlexIO SPI transfer is finished. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. + * param xfer Pointer to FlexIO SPI transfer structure. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + uint32_t dataMode = 0; + uint16_t timerCmp = base->flexioBase->TIMCMP[base->timerIndex[0]]; + + timerCmp &= 0x00FFU; + + /* Check if the device is busy. */ + if ((handle->txInProgress) || (handle->rxInProgress)) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* Check if input parameter invalid. */ + if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + /* configure data mode. */ + if ((xfer->flags == kFLEXIO_SPI_8bitMsb) || (xfer->flags == kFLEXIO_SPI_8bitLsb)) + { + dataMode = (8 * 2 - 1U) << 8U; + } + else if ((xfer->flags == kFLEXIO_SPI_16bitMsb) || (xfer->flags == kFLEXIO_SPI_16bitLsb)) + { + dataMode = (16 * 2 - 1U) << 8U; + } + else + { + dataMode = 8 * 2 - 1U; + } + + dataMode |= timerCmp; + + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + FLEXIO_SPI_EDMAConfig(base, handle, xfer); + + return kStatus_Success; +} + +/*! + * brief Gets the remaining bytes for FlexIO SPI eDMA transfer. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle FlexIO SPI eDMA handle pointer. + * param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + if (handle->rxInProgress) + { + *count = + (handle->transferSize - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount( + handle->rxHandle->base, handle->rxHandle->channel)); + } + else + { + *count = + (handle->transferSize - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount( + handle->txHandle->base, handle->txHandle->channel)); + } + + return kStatus_Success; +} + +/*! + * brief Aborts a FlexIO SPI transfer using eDMA. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle FlexIO SPI eDMA handle pointer. + */ +void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma. */ + EDMA_StopTransfer(handle->txHandle); + EDMA_StopTransfer(handle->rxHandle); + + /* Disable DMA enable bit. */ + FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_DmaAllEnable, false); + + /* Set the handle state. */ + handle->txInProgress = false; + handle->rxInProgress = false; +} + +/*! + * brief Performs a non-blocking FlexIO SPI transfer using eDMA. + * + * note This interface returns immediately after transfer initiates. Call + * FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and + * check whether the FlexIO SPI transfer is finished. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. + * param xfer Pointer to FlexIO SPI transfer structure. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle); + assert(xfer); + + uint32_t dataMode = 0; + + /* Check if the device is busy. */ + if ((handle->txInProgress) || (handle->rxInProgress)) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* Check if input parameter invalid. */ + if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + /* configure data mode. */ + if ((xfer->flags == kFLEXIO_SPI_8bitMsb) || (xfer->flags == kFLEXIO_SPI_8bitLsb)) + { + dataMode = 8 * 2 - 1U; + } + else if ((xfer->flags == kFLEXIO_SPI_16bitMsb) || (xfer->flags == kFLEXIO_SPI_16bitLsb)) + { + dataMode = 16 * 2 - 1U; + } + else + { + dataMode = 8 * 2 - 1U; + } + + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + FLEXIO_SPI_EDMAConfig(base, handle, xfer); + + return kStatus_Success; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_spi_edma.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_spi_edma.h new file mode 100644 index 0000000000..79c6e23523 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_spi_edma.h @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_FLEXIO_SPI_EDMA_H_ +#define _FSL_FLEXIO_SPI_EDMA_H_ + +#include "fsl_flexio_spi.h" +#include "fsl_edma.h" + +/*! + * @addtogroup flexio_edma_spi + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO SPI EDMA driver version 2.1.3. */ +#define FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) +/*@}*/ + +/*! @brief typedef for flexio_spi_master_edma_handle_t in advance. */ +typedef struct _flexio_spi_master_edma_handle flexio_spi_master_edma_handle_t; + +/*! @brief Slave handle is the same with master handle. */ +typedef flexio_spi_master_edma_handle_t flexio_spi_slave_edma_handle_t; + +/*! @brief FlexIO SPI master callback for finished transmit */ +typedef void (*flexio_spi_master_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO SPI slave callback for finished transmit */ +typedef void (*flexio_spi_slave_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO SPI eDMA transfer handle, users should not touch the content of the handle.*/ +struct _flexio_spi_master_edma_handle +{ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + bool txInProgress; /*!< Send transfer in progress */ + bool rxInProgress; /*!< Receive transfer in progress */ + edma_handle_t *txHandle; /*!< DMA handler for SPI send */ + edma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ + flexio_spi_master_edma_transfer_callback_t callback; /*!< Callback for SPI DMA transfer */ + void *userData; /*!< User Data for SPI DMA callback */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA Transactional + * @{ + */ + +/*! + * @brief Initializes the FlexIO SPI master eDMA handle. + * + * This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master + * transactional + * APIs. + * For a specified FlexIO SPI instance, call this API once to get the initialized handle. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. + * @param callback SPI callback, NULL means no callback. + * @param userData callback function parameter. + * @param txHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer. + * @param rxHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range. + */ +status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txHandle, + edma_handle_t *rxHandle); + +/*! + * @brief Performs a non-blocking FlexIO SPI transfer using eDMA. + * + * @note This interface returns immediately after transfer initiates. Call + * FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check + * whether the FlexIO SPI transfer is finished. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. + * @param xfer Pointer to FlexIO SPI transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts a FlexIO SPI transfer using eDMA. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle FlexIO SPI eDMA handle pointer. + */ +void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle); + +/*! + * @brief Gets the remaining bytes for FlexIO SPI eDMA transfer. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle FlexIO SPI eDMA handle pointer. + * @param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + size_t *count); + +/*! + * @brief Initializes the FlexIO SPI slave eDMA handle. + * + * This function initializes the FlexIO SPI slave eDMA handle. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. + * @param callback SPI callback, NULL means no callback. + * @param userData callback function parameter. + * @param txHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer. + * @param rxHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer. + */ +static inline void FLEXIO_SPI_SlaveTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + flexio_spi_slave_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txHandle, + edma_handle_t *rxHandle) +{ + FLEXIO_SPI_MasterTransferCreateHandleEDMA(base, handle, callback, userData, txHandle, rxHandle); +} + +/*! + * @brief Performs a non-blocking FlexIO SPI transfer using eDMA. + * + * @note This interface returns immediately after transfer initiates. Call + * FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and + * check whether the FlexIO SPI transfer is finished. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. + * @param xfer Pointer to FlexIO SPI transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts a FlexIO SPI transfer using eDMA. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. + */ +static inline void FLEXIO_SPI_SlaveTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle) +{ + FLEXIO_SPI_MasterTransferAbortEDMA(base, handle); +} + +/*! + * @brief Gets the remaining bytes to be transferred for FlexIO SPI eDMA. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle FlexIO SPI eDMA handle pointer. + * @param count Number of bytes transferred so far by the non-blocking transaction. + */ +static inline status_t FLEXIO_SPI_SlaveTransferGetCountEDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + size_t *count) +{ + return FLEXIO_SPI_MasterTransferGetCountEDMA(base, handle, count); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_uart.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_uart.c new file mode 100644 index 0000000000..41d872add9 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_uart.c @@ -0,0 +1,949 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_uart" +#endif + +/*flexioBase); +} + +static size_t FLEXIO_UART_TransferGetRxRingBufferLength(flexio_uart_handle_t *handle) +{ + size_t size; + + if (handle->rxRingBufferTail > handle->rxRingBufferHead) + { + size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); + } + else + { + size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); + } + + return size; +} + +static bool FLEXIO_UART_TransferIsRxRingBufferFull(flexio_uart_handle_t *handle) +{ + bool full; + + if (FLEXIO_UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + + return full; +} + +/*! + * brief Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART + * hardware, and configures the FlexIO UART with FlexIO UART configuration. + * The configuration structure can be filled by the user or be set with + * default values by FLEXIO_UART_GetDefaultConfig(). + * + * Example + code + FLEXIO_UART_Type base = { + .flexioBase = FLEXIO, + .TxPinIndex = 0, + .RxPinIndex = 1, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_uart_config_t config = { + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 115200U, + .bitCountPerChar = 8 + }; + FLEXIO_UART_Init(base, &config, srcClock_Hz); + endcode + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param userConfig Pointer to the flexio_uart_config_t structure. + * param srcClock_Hz FlexIO source clock in Hz. + * retval kStatus_Success Configuration success + * retval kStatus_InvalidArgument Buadrate configuration out of range +*/ +status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz) +{ + assert(base && userConfig); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t ctrlReg = 0; + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; + status_t result = kStatus_Success; + + /* Clear the shifterConfig & timerConfig struct. */ + memset(&shifterConfig, 0, sizeof(shifterConfig)); + memset(&timerConfig, 0, sizeof(timerConfig)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate flexio clock. */ + CLOCK_EnableClock(s_flexioClocks[FLEXIO_UART_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Configure FLEXIO UART */ + ctrlReg = base->flexioBase->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DBGE(userConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(userConfig->enableUart)); + if (!userConfig->enableInDoze) + { + ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->flexioBase->CTRL = ctrlReg; + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinSelect = base->TxPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /*2. Configure the timer 0 for tx. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->TxPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + timerDiv = srcClock_Hz / userConfig->baudRate_Bps; + timerDiv = timerDiv / 2 - 1; + + if (timerDiv > 0xFFU) + { + result = kStatus_InvalidArgument; + } + + timerCmp = ((uint32_t)(userConfig->bitCountPerChar * 2 - 1)) << 8U; + timerCmp |= timerDiv; + + timerConfig.timerCompare = timerCmp; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); + + /* 3. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[1]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->RxPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /* 4. Configure the timer 1 for rx. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->RxPinIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->RxPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinRisingEdge; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + timerConfig.timerCompare = timerCmp; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); + + return result; +} + +/*! + * brief Resets the FlexIO UART shifter and timer config. + * + * note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module. + * + * param base Pointer to FLEXIO_UART_Type structure + */ +void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base) +{ + base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[0]); + base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[1]); + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1U << base->timerIndex[0]); + base->flexioBase->TIMSTAT = (1U << base->timerIndex[1]); +} + +/*! + * brief Gets the default configuration to configure the FlexIO UART. The configuration + * can be used directly for calling the FLEXIO_UART_Init(). + * Example: + code + flexio_uart_config_t config; + FLEXIO_UART_GetDefaultConfig(&userConfig); + endcode + * param userConfig Pointer to the flexio_uart_config_t structure. +*/ +void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig) +{ + assert(userConfig); + + /* Initializes the configure structure to zero. */ + memset(userConfig, 0, sizeof(*userConfig)); + + userConfig->enableUart = true; + userConfig->enableInDoze = false; + userConfig->enableInDebug = true; + userConfig->enableFastAccess = false; + /* Default baud rate 115200. */ + userConfig->baudRate_Bps = 115200U; + /* Default bit count at 8. */ + userConfig->bitCountPerChar = kFLEXIO_UART_8BitsPerChar; +} + +/*! + * brief Enables the FlexIO UART interrupt. + * + * This function enables the FlexIO UART interrupt. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param mask Interrupt source. + */ +void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); + } + if (mask & kFLEXIO_UART_RxDataRegFullInterruptEnable) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +/*! + * brief Disables the FlexIO UART interrupt. + * + * This function disables the FlexIO UART interrupt. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param mask Interrupt source. + */ +void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_UART_TxDataRegEmptyInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]); + } + if (mask & kFLEXIO_UART_RxDataRegFullInterruptEnable) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +/*! + * brief Gets the FlexIO UART status flags. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * return FlexIO UART status flags. + */ + +uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base) +{ + uint32_t status = 0; + status = + ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]); + status |= + (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 1U); + status |= + (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 2U); + return status; +} + +/*! + * brief Gets the FlexIO UART status flags. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param mask Status flag. + * The parameter can be any combination of the following values: + * arg kFLEXIO_UART_TxDataRegEmptyFlag + * arg kFLEXIO_UART_RxEmptyFlag + * arg kFLEXIO_UART_RxOverRunFlag + */ + +void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask) +{ + if (mask & kFLEXIO_UART_TxDataRegEmptyFlag) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]); + } + if (mask & kFLEXIO_UART_RxDataRegFullFlag) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]); + } + if (mask & kFLEXIO_UART_RxOverRunFlag) + { + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]); + } +} + +/*! + * brief Sends a buffer of data bytes. + * + * note This function blocks using the polling method until all bytes have been sent. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param txData The data bytes to send. + * param txSize The number of data bytes to send. + */ +void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize) +{ + assert(txData); + assert(txSize); + + while (txSize--) + { + /* Wait until data transfer complete. */ + while (!(FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))) + { + } + + base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = *txData++; + } +} + +/*! + * brief Receives a buffer of bytes. + * + * note This function blocks using the polling method until all bytes have been received. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param rxData The buffer to store the received bytes. + * param rxSize The number of data bytes to be received. + */ +void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize) +{ + assert(rxData); + assert(rxSize); + + while (rxSize--) + { + /* Wait until data transfer complete. */ + while (!(FLEXIO_UART_GetStatusFlags(base) & kFLEXIO_UART_RxDataRegFullFlag)) + { + } + + *rxData++ = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; + } +} + +/*! + * brief Initializes the UART handle. + * + * This function initializes the FlexIO UART handle, which can be used for other FlexIO + * UART transactional APIs. Call this API once to get the + * initialized handle. + * + * The UART driver supports the "background" receiving, which means that users can set up + * a RX ring buffer optionally. Data received is stored into the ring buffer even when + * the user doesn't call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data + * received in the ring buffer, users can get the received data from the ring buffer + * directly. The ring buffer is disabled if passing NULL as p ringBuffer. + * + * param base to FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param callback The callback function. + * param userData The parameter of the callback function. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set the TX/RX state. */ + handle->rxState = kFLEXIO_UART_RxIdle; + handle->txState = kFLEXIO_UART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + + /* Enable interrupt in NVIC. */ + EnableIRQ(flexio_irqs[FLEXIO_UART_GetInstance(base)]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_UART_TransferHandleIRQ); +} + +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_ReceiveNonBlocking() API. If there is already data received + * in the ring buffer, users can get the received data from the ring buffer directly. + * + * note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, only 31 bytes are used for saving data. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize Size of the ring buffer. + */ +void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize) +{ + assert(handle); + + /* Setup the ringbuffer address */ + if (ringBuffer) + { + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Enable the interrupt to accept the data when user need the ring buffer. */ + FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + } +} + +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) +{ + assert(handle); + + if (handle->rxState == kFLEXIO_UART_RxIdle) + { + FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, + * which returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in ISR, the FlexIO UART driver calls the callback + * function and passes the ref kStatus_FLEXIO_UART_TxIdle as status parameter. + * + * note The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However, it does not ensure that all data is sent out. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param xfer FlexIO UART transfer structure. See #flexio_uart_transfer_t. + * retval kStatus_Success Successfully starts the data transmission. + * retval kStatus_UART_TxBusy Previous transmission still not finished, data not written to the TX register. + */ +status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer) +{ + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* Return error if current TX busy. */ + if (kFLEXIO_UART_TxBusy == handle->txState) + { + status = kStatus_FLEXIO_UART_TxBusy; + } + else + { + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = kFLEXIO_UART_TxBusy; + + /* Enable transmiter interrupt. */ + FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt-driven data sending. Get the remainBytes to find out + * how many bytes are still not sent out. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) +{ + /* Disable the transmitter and disable the interrupt. */ + FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable); + + handle->txDataSize = 0; + handle->txState = kFLEXIO_UART_TxIdle; +} + +/*! + * brief Gets the number of bytes sent. + * + * This function gets the number of bytes sent driven by interrupt. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param count Number of bytes sent so far by the non-blocking transaction. + * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count) +{ + assert(handle); + assert(count); + + if (kFLEXIO_UART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - handle->txDataSize; + + return kStatus_Success; +} + +/*! + * brief Receives a buffer of data using the interrupt method. + * + * This function receives data using the interrupt method. This is a non-blocking function, + * which returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in ring buffer is not enough to read, the receive + * request is saved by the UART driver. When new data arrives, the receive request + * is serviced first. When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter ref kStatus_UART_RxIdle. + * For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer, + * the 5 bytes are copied to xfer->data. This function returns with the + * parameter p receivedBytes set to 5. For the last 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param xfer UART transfer structure. See #flexio_uart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into the transmit queue. + * retval kStatus_FLEXIO_UART_RxBusy Previous receive request is not finished. + */ +status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer, + size_t *receivedBytes) +{ + uint32_t i; + status_t status; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + + if (kFLEXIO_UART_RxBusy == handle->rxState) + { + status = kStatus_FLEXIO_UART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer) + { + /* Disable FLEXIO_UART RX IRQ, protect ring buffer. */ + FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = FLEXIO_UART_TransferGetRxRingBufferLength(handle); + + if (bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kFLEXIO_UART_RxBusy; + } + + /* Enable FLEXIO_UART RX IRQ if previously enabled. */ + FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + + /* Call user callback since all data are received. */ + if (0 == bytesToReceive) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kFLEXIO_UART_RxBusy; + + /* Enable RX interrupt. */ + FLEXIO_UART_EnableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + + /* Return the how many bytes have read. */ + if (receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the receive data which was using IRQ. + * + * This function aborts the receive data which was using IRQ. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) +{ + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (!handle->rxRingBuffer) + { + /* Disable RX interrupt. */ + FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + + handle->rxDataSize = 0U; + handle->rxState = kFLEXIO_UART_RxIdle; +} + +/*! + * brief Gets the number of bytes received. + * + * This function gets the number of bytes received driven by interrupt. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param count Number of bytes received so far by the non-blocking transaction. + * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count) +{ + assert(handle); + assert(count); + + if (kFLEXIO_UART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +/*! + * brief FlexIO UART IRQ handler function. + * + * This function processes the FlexIO UART transmit and receives the IRQ request. + * + * param uartType Pointer to the FLEXIO_UART_Type structure. + * param uartHandle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle) +{ + uint8_t count = 1; + FLEXIO_UART_Type *base = (FLEXIO_UART_Type *)uartType; + flexio_uart_handle_t *handle = (flexio_uart_handle_t *)uartHandle; + + /* Read the status back. */ + uint8_t status = FLEXIO_UART_GetStatusFlags(base); + + /* If RX overrun. */ + if (kFLEXIO_UART_RxOverRunFlag & status) + { + /* Clear Overrun flag. */ + FLEXIO_UART_ClearStatusFlags(base, kFLEXIO_UART_RxOverRunFlag); + + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_RxHardwareOverrun, handle->userData); + } + } + + /* Receive data register full */ + if ((kFLEXIO_UART_RxDataRegFullFlag & status) && (base->flexioBase->SHIFTSIEN & (1U << base->shifterIndex[1]))) + { + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + if (handle->rxDataSize) + { + /* Using non block API to read the data from the registers. */ + FLEXIO_UART_ReadByte(base, handle->rxData); + handle->rxDataSize--; + handle->rxData++; + count--; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (!handle->rxDataSize) + { + handle->rxState = kFLEXIO_UART_RxIdle; + + if (handle->callback) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_RxIdle, handle->userData); + } + } + } + + if (handle->rxRingBuffer) + { + if (count) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (FLEXIO_UART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overridden. */ + if (FLEXIO_UART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + handle->rxRingBuffer[handle->rxRingBufferHead] = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; + + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If no receive requst pending, stop RX interrupt. */ + else if (!handle->rxDataSize) + { + FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + else + { + } + } + + /* Send data register empty and the interrupt is enabled. */ + if ((kFLEXIO_UART_TxDataRegEmptyFlag & status) && (base->flexioBase->SHIFTSIEN & (1U << base->shifterIndex[0]))) + { + if (handle->txDataSize) + { + /* Using non block API to write the data to the registers. */ + FLEXIO_UART_WriteByte(base, handle->txData); + handle->txData++; + handle->txDataSize--; + count--; + + /* If all the data are written to data register, TX finished. */ + if (!handle->txDataSize) + { + handle->txState = kFLEXIO_UART_TxIdle; + + /* Disable TX register empty interrupt. */ + FLEXIO_UART_DisableInterrupts(base, kFLEXIO_UART_TxDataRegEmptyInterruptEnable); + + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_TxIdle, handle->userData); + } + } + } + } +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_uart.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_uart.h new file mode 100644 index 0000000000..0634c62c69 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_uart.h @@ -0,0 +1,560 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_FLEXIO_UART_H_ +#define _FSL_FLEXIO_UART_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_uart + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO UART driver version 2.1.5. */ +#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) +/*@}*/ + +/*! @brief Error codes for the UART driver. */ +enum _flexio_uart_status +{ + kStatus_FLEXIO_UART_TxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 0), /*!< Transmitter is busy. */ + kStatus_FLEXIO_UART_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 1), /*!< Receiver is busy. */ + kStatus_FLEXIO_UART_TxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 2), /*!< UART transmitter is idle. */ + kStatus_FLEXIO_UART_RxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 3), /*!< UART receiver is idle. */ + kStatus_FLEXIO_UART_ERROR = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 4), /*!< ERROR happens on UART. */ + kStatus_FLEXIO_UART_RxRingBufferOverrun = + MAKE_STATUS(kStatusGroup_FLEXIO_UART, 5), /*!< UART RX software ring buffer overrun. */ + kStatus_FLEXIO_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 6) /*!< UART RX receiver overrun. */ +}; + +/*! @brief FlexIO UART bit count per char. */ +typedef enum _flexio_uart_bit_count_per_char +{ + kFLEXIO_UART_7BitsPerChar = 7U, /*!< 7-bit data characters */ + kFLEXIO_UART_8BitsPerChar = 8U, /*!< 8-bit data characters */ + kFLEXIO_UART_9BitsPerChar = 9U, /*!< 9-bit data characters */ +} flexio_uart_bit_count_per_char_t; + +/*! @brief Define FlexIO UART interrupt mask. */ +enum _flexio_uart_interrupt_enable +{ + kFLEXIO_UART_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ + kFLEXIO_UART_RxDataRegFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO UART status mask. */ +enum _flexio_uart_status_flags +{ + kFLEXIO_UART_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ + kFLEXIO_UART_RxDataRegFullFlag = 0x2U, /*!< Receive buffer full flag. */ + kFLEXIO_UART_RxOverRunFlag = 0x4U, /*!< Receive buffer over run flag. */ +}; + +/*! @brief Define FlexIO UART access structure typedef. */ +typedef struct _flexio_uart_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ + uint8_t TxPinIndex; /*!< Pin select for UART_Tx. */ + uint8_t RxPinIndex; /*!< Pin select for UART_Rx. */ + uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO UART. */ + uint8_t timerIndex[2]; /*!< Timer index used in FlexIO UART. */ +} FLEXIO_UART_Type; + +/*! @brief Define FlexIO UART user configuration structure. */ +typedef struct _flexio_uart_config +{ + bool enableUart; /*!< Enable/disable FlexIO UART TX & RX. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode*/ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode*/ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, + fast access requires the FlexIO clock to be at least + twice the frequency of the bus clock. */ + uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ + flexio_uart_bit_count_per_char_t bitCountPerChar; /*!< number of bits, 7/8/9 -bit */ +} flexio_uart_config_t; + +/*! @brief Define FlexIO UART transfer structure. */ +typedef struct _flexio_uart_transfer +{ + uint8_t *data; /*!< Transfer buffer*/ + size_t dataSize; /*!< Transfer size*/ +} flexio_uart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _flexio_uart_handle flexio_uart_handle_t; + +/*! @brief FlexIO UART transfer callback function. */ +typedef void (*flexio_uart_transfer_callback_t)(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FLEXIO UART handle structure*/ +struct _flexio_uart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t txDataSizeAll; /*!< Total bytes to be sent. */ + size_t rxDataSizeAll; /*!< Total bytes to be received. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + flexio_uart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART + * hardware, and configures the FlexIO UART with FlexIO UART configuration. + * The configuration structure can be filled by the user or be set with + * default values by FLEXIO_UART_GetDefaultConfig(). + * + * Example + @code + FLEXIO_UART_Type base = { + .flexioBase = FLEXIO, + .TxPinIndex = 0, + .RxPinIndex = 1, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_uart_config_t config = { + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 115200U, + .bitCountPerChar = 8 + }; + FLEXIO_UART_Init(base, &config, srcClock_Hz); + @endcode + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param userConfig Pointer to the flexio_uart_config_t structure. + * @param srcClock_Hz FlexIO source clock in Hz. + * @retval kStatus_Success Configuration success + * @retval kStatus_InvalidArgument Buadrate configuration out of range +*/ +status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz); + +/*! + * @brief Resets the FlexIO UART shifter and timer config. + * + * @note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module. + * + * @param base Pointer to FLEXIO_UART_Type structure + */ +void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO UART. The configuration + * can be used directly for calling the FLEXIO_UART_Init(). + * Example: + @code + flexio_uart_config_t config; + FLEXIO_UART_GetDefaultConfig(&userConfig); + @endcode + * @param userConfig Pointer to the flexio_uart_config_t structure. +*/ +void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexIO UART status flags. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @return FlexIO UART status flags. + */ + +uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base); + +/*! + * @brief Gets the FlexIO UART status flags. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param mask Status flag. + * The parameter can be any combination of the following values: + * @arg kFLEXIO_UART_TxDataRegEmptyFlag + * @arg kFLEXIO_UART_RxEmptyFlag + * @arg kFLEXIO_UART_RxOverRunFlag + */ + +void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO UART interrupt. + * + * This function enables the FlexIO UART interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param mask Interrupt source. + */ +void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO UART interrupt. + * + * This function disables the FlexIO UART interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param mask Interrupt source. + */ +void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Gets the FlexIO UARt transmit data register address. + * + * This function returns the UART data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @return FlexIO UART transmit data register address. + */ +static inline uint32_t FLEXIO_UART_GetTxDataRegisterAddress(FLEXIO_UART_Type *base) +{ + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]); +} + +/*! + * @brief Gets the FlexIO UART receive data register address. + * + * This function returns the UART data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @return FlexIO UART receive data register address. + */ +static inline uint32_t FLEXIO_UART_GetRxDataRegisterAddress(FLEXIO_UART_Type *base) +{ + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferByteSwapped, base->shifterIndex[1]); +} + +/*! + * @brief Enables/disables the FlexIO UART transmit DMA. + * This function enables/disables the FlexIO UART Tx DMA, + * which means asserting the kFLEXIO_UART_TxDataRegEmptyFlag does/doesn't trigger the DMA request. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param enable True to enable, false to disable. + */ +static inline void FLEXIO_UART_EnableTxDMA(FLEXIO_UART_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->shifterIndex[0], enable); +} + +/*! + * @brief Enables/disables the FlexIO UART receive DMA. + * This function enables/disables the FlexIO UART Rx DMA, + * which means asserting kFLEXIO_UART_RxDataRegFullFlag does/doesn't trigger the DMA request. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param enable True to enable, false to disable. + */ +static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1 << base->shifterIndex[1], enable); +} + +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO UART module operation. + * + * @param base Pointer to the FLEXIO_UART_Type. + * @param enable True to enable, false does not have any effect. + */ +static inline void FLEXIO_UART_Enable(FLEXIO_UART_Type *base, bool enable) +{ + if (enable) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/*! + * @brief Writes one byte of data. + * + * @note This is a non-blocking API, which returns directly after the data is put into the + * data register. Ensure that the TxEmptyFlag is asserted before calling + * this API. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param buffer The data bytes to send. + */ +static inline void FLEXIO_UART_WriteByte(FLEXIO_UART_Type *base, const uint8_t *buffer) +{ + base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = *buffer; +} + +/*! + * @brief Reads one byte of data. + * + * @note This is a non-blocking API, which returns directly after the data is read from the + * data register. Ensure that the RxFullFlag is asserted before calling this API. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param buffer The buffer to store the received bytes. + */ +static inline void FLEXIO_UART_ReadByte(FLEXIO_UART_Type *base, uint8_t *buffer) +{ + *buffer = base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]; +} + +/*! + * @brief Sends a buffer of data bytes. + * + * @note This function blocks using the polling method until all bytes have been sent. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param txData The data bytes to send. + * @param txSize The number of data bytes to send. + */ +void FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks using the polling method until all bytes have been received. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param rxData The buffer to store the received bytes. + * @param rxSize The number of data bytes to be received. + */ +void FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle. + * + * This function initializes the FlexIO UART handle, which can be used for other FlexIO + * UART transactional APIs. Call this API once to get the + * initialized handle. + * + * The UART driver supports the "background" receiving, which means that users can set up + * a RX ring buffer optionally. Data received is stored into the ring buffer even when + * the user doesn't call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data + * received in the ring buffer, users can get the received data from the ring buffer + * directly. The ring buffer is disabled if passing NULL as @p ringBuffer. + * + * @param base to FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_ReceiveNonBlocking() API. If there is already data received + * in the ring buffer, users can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, only 31 bytes are used for saving data. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize Size of the ring buffer. + */ +void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, + * which returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in ISR, the FlexIO UART driver calls the callback + * function and passes the @ref kStatus_FLEXIO_UART_TxIdle as status parameter. + * + * @note The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However, it does not ensure that all data is sent out. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param xfer FlexIO UART transfer structure. See #flexio_uart_transfer_t. + * @retval kStatus_Success Successfully starts the data transmission. + * @retval kStatus_UART_TxBusy Previous transmission still not finished, data not written to the TX register. + */ +status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt-driven data sending. Get the remainBytes to find out + * how many bytes are still not sent out. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); + +/*! + * @brief Gets the number of bytes sent. + * + * This function gets the number of bytes sent driven by interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param count Number of bytes sent so far by the non-blocking transaction. + * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count); + +/*! + * @brief Receives a buffer of data using the interrupt method. + * + * This function receives data using the interrupt method. This is a non-blocking function, + * which returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in ring buffer is not enough to read, the receive + * request is saved by the UART driver. When new data arrives, the receive request + * is serviced first. When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. + * For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer, + * the 5 bytes are copied to xfer->data. This function returns with the + * parameter @p receivedBytes set to 5. For the last 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param xfer UART transfer structure. See #flexio_uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into the transmit queue. + * @retval kStatus_FLEXIO_UART_RxBusy Previous receive request is not finished. + */ +status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the receive data which was using IRQ. + * + * This function aborts the receive data which was using IRQ. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); + +/*! + * @brief Gets the number of bytes received. + * + * This function gets the number of bytes received driven by interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param count Number of bytes received so far by the non-blocking transaction. + * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count); + +/*! + * @brief FlexIO UART IRQ handler function. + * + * This function processes the FlexIO UART transmit and receives the IRQ request. + * + * @param uartType Pointer to the FLEXIO_UART_Type structure. + * @param uartHandle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*@}*/ + +#endif /*_FSL_FLEXIO_UART_H_*/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_uart_edma.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_uart_edma.c new file mode 100644 index 0000000000..bb8b1ee30f --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_uart_edma.c @@ -0,0 +1,407 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_uart_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_uart_edma" +#endif + +/*handle); + + /* Avoid the warning for unused variables. */ + handle = handle; + tcds = tcds; + + if (transferDone) + { + FLEXIO_UART_TransferAbortSendEDMA(uartPrivateHandle->base, uartPrivateHandle->handle); + + if (uartPrivateHandle->handle->callback) + { + uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, + kStatus_FLEXIO_UART_TxIdle, uartPrivateHandle->handle->userData); + } + } +} + +static void FLEXIO_UART_TransferReceiveEDMACallback(edma_handle_t *handle, + void *param, + bool transferDone, + uint32_t tcds) +{ + flexio_uart_edma_private_handle_t *uartPrivateHandle = (flexio_uart_edma_private_handle_t *)param; + + assert(uartPrivateHandle->handle); + + /* Avoid the warning for unused variables. */ + handle = handle; + tcds = tcds; + + if (transferDone) + { + /* Disable transfer. */ + FLEXIO_UART_TransferAbortReceiveEDMA(uartPrivateHandle->base, uartPrivateHandle->handle); + + if (uartPrivateHandle->handle->callback) + { + uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, + kStatus_FLEXIO_UART_RxIdle, uartPrivateHandle->handle->userData); + } + } +} + +/*! + * brief Initializes the UART handle which is used in transactional functions. + * + * param base Pointer to FLEXIO_UART_Type. + * param handle Pointer to flexio_uart_edma_handle_t structure. + * param callback The callback function. + * param userData The parameter of the callback function. + * param rxEdmaHandle User requested DMA handle for RX DMA transfer. + * param txEdmaHandle User requested DMA handle for TX DMA transfer. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range. + */ +status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle) +{ + assert(handle); + + uint8_t index = 0; + + /* Find the an empty handle pointer to store the handle. */ + for (index = 0; index < FLEXIO_UART_HANDLE_COUNT; index++) + { + if (s_edmaPrivateHandle[index].base == NULL) + { + s_edmaPrivateHandle[index].base = base; + s_edmaPrivateHandle[index].handle = handle; + break; + } + } + + if (index == FLEXIO_UART_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + + memset(handle, 0, sizeof(*handle)); + + handle->rxState = kFLEXIO_UART_RxIdle; + handle->txState = kFLEXIO_UART_TxIdle; + + handle->rxEdmaHandle = rxEdmaHandle; + handle->txEdmaHandle = txEdmaHandle; + + handle->callback = callback; + handle->userData = userData; + + /* Configure TX. */ + if (txEdmaHandle) + { + EDMA_SetCallback(handle->txEdmaHandle, FLEXIO_UART_TransferSendEDMACallback, &s_edmaPrivateHandle); + } + + /* Configure RX. */ + if (rxEdmaHandle) + { + EDMA_SetCallback(handle->rxEdmaHandle, FLEXIO_UART_TransferReceiveEDMACallback, &s_edmaPrivateHandle); + } + + return kStatus_Success; +} + +/*! + * brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent out, the send callback function is called. + * + * param base Pointer to FLEXIO_UART_Type + * param handle UART handle pointer. + * param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_FLEXIO_UART_TxBusy Previous transfer on going. + */ +status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_transfer_t *xfer) +{ + assert(handle->txEdmaHandle); + + edma_transfer_config_t xferConfig; + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous TX not finished. */ + if (kFLEXIO_UART_TxBusy == handle->txState) + { + status = kStatus_FLEXIO_UART_TxBusy; + } + else + { + handle->txState = kFLEXIO_UART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), + (void *)FLEXIO_UART_GetTxDataRegisterAddress(base), sizeof(uint8_t), sizeof(uint8_t), + xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Store the initially configured eDMA minor byte transfer count into the FLEXIO UART handle */ + handle->nbytes = sizeof(uint8_t); + + /* Submit transfer. */ + EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig); + EDMA_StartTransfer(handle->txEdmaHandle); + + /* Enable UART TX EDMA. */ + FLEXIO_UART_EnableTxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Receives data using eDMA. + * + * This function receives data using eDMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * param base Pointer to FLEXIO_UART_Type + * param handle Pointer to flexio_uart_edma_handle_t structure + * param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_UART_RxBusy Previous transfer on going. + */ +status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_transfer_t *xfer) +{ + assert(handle->rxEdmaHandle); + + edma_transfer_config_t xferConfig; + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous RX not finished. */ + if (kFLEXIO_UART_RxBusy == handle->rxState) + { + status = kStatus_FLEXIO_UART_RxBusy; + } + else + { + handle->rxState = kFLEXIO_UART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, (void *)FLEXIO_UART_GetRxDataRegisterAddress(base), sizeof(uint8_t), + xfer->data, sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Store the initially configured eDMA minor byte transfer count into the FLEXIO UART handle */ + handle->nbytes = sizeof(uint8_t); + + /* Submit transfer. */ + EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig); + EDMA_StartTransfer(handle->rxEdmaHandle); + + /* Enable UART RX EDMA. */ + FLEXIO_UART_EnableRxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the sent data which using eDMA. + * + * This function aborts sent data which using eDMA. + * + * param base Pointer to FLEXIO_UART_Type + * param handle Pointer to flexio_uart_edma_handle_t structure + */ +void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle) +{ + assert(handle->txEdmaHandle); + + /* Disable UART TX EDMA. */ + FLEXIO_UART_EnableTxDMA(base, false); + + /* Stop transfer. */ + EDMA_StopTransfer(handle->txEdmaHandle); + + handle->txState = kFLEXIO_UART_TxIdle; +} + +/*! + * brief Aborts the receive data which using eDMA. + * + * This function aborts the receive data which using eDMA. + * + * param base Pointer to FLEXIO_UART_Type + * param handle Pointer to flexio_uart_edma_handle_t structure + */ +void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle) +{ + assert(handle->rxEdmaHandle); + + /* Disable UART RX EDMA. */ + FLEXIO_UART_EnableRxDMA(base, false); + + /* Stop transfer. */ + EDMA_StopTransfer(handle->rxEdmaHandle); + + handle->rxState = kFLEXIO_UART_RxIdle; +} + +/*! + * brief Gets the number of bytes received. + * + * This function gets the number of bytes received. + * + * param base Pointer to FLEXIO_UART_Type + * param handle Pointer to flexio_uart_edma_handle_t structure + * param count Number of bytes received so far by the non-blocking transaction. + * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + size_t *count) +{ + assert(handle); + assert(handle->rxEdmaHandle); + assert(count); + + if (kFLEXIO_UART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel); + + return kStatus_Success; +} + +/*! + * brief Gets the number of bytes sent out. + * + * This function gets the number of bytes sent out. + * + * param base Pointer to FLEXIO_UART_Type + * param handle Pointer to flexio_uart_edma_handle_t structure + * param count Number of bytes sent so far by the non-blocking transaction. + * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count) +{ + assert(handle); + assert(handle->txEdmaHandle); + assert(count); + + if (kFLEXIO_UART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel); + + return kStatus_Success; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_uart_edma.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_uart_edma.h new file mode 100644 index 0000000000..5a6b36f6eb --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexio_uart_edma.h @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_FLEXIO_UART_EDMA_H_ +#define _FSL_FLEXIO_UART_EDMA_H_ + +#include "fsl_flexio_uart.h" +#include "fsl_edma.h" + +/*! + * @addtogroup flexio_edma_uart + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexIO UART EDMA driver version 2.1.4. */ +#define FSL_FLEXIO_UART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) +/*@}*/ + +/* Forward declaration of the handle typedef. */ +typedef struct _flexio_uart_edma_handle flexio_uart_edma_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*flexio_uart_edma_transfer_callback_t)(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief UART eDMA handle + */ +struct _flexio_uart_edma_handle +{ + flexio_uart_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + + size_t txDataSizeAll; /*!< Total bytes to be sent. */ + size_t rxDataSizeAll; /*!< Total bytes to be received. */ + + edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ + edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ + + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle which is used in transactional functions. + * + * @param base Pointer to FLEXIO_UART_Type. + * @param handle Pointer to flexio_uart_edma_handle_t structure. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. + * @param txEdmaHandle User requested DMA handle for TX DMA transfer. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range. + */ +status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle); + +/*! + * @brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent out, the send callback function is called. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle UART handle pointer. + * @param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_FLEXIO_UART_TxBusy Previous transfer on going. + */ +status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_transfer_t *xfer); + +/*! + * @brief Receives data using eDMA. + * + * This function receives data using eDMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + * @param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_UART_RxBusy Previous transfer on going. + */ +status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data which using eDMA. + * + * This function aborts sent data which using eDMA. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + */ +void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle); + +/*! + * @brief Aborts the receive data which using eDMA. + * + * This function aborts the receive data which using eDMA. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + */ +void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle); + +/*! + * @brief Gets the number of bytes sent out. + * + * This function gets the number of bytes sent out. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + * @param count Number of bytes sent so far by the non-blocking transaction. + * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count); + +/*! + * @brief Gets the number of bytes received. + * + * This function gets the number of bytes received. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + * @param count Number of bytes received so far by the non-blocking transaction. + * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + size_t *count); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_UART_EDMA_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexram.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexram.c new file mode 100644 index 0000000000..ee93440d94 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexram.c @@ -0,0 +1,216 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexram.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexram" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address to be used to gate or ungate the module clock + * + * @param base FLEXRAM base address + * + * @return The FLEXRAM instance + */ +static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base); + +/*! + * @brief FLEXRAM map TCM size to register value + * + * @param tcmBankNum tcm banknumber + * @retval register value correspond to the tcm size + */ +static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to FLEXRAM bases for each instance. */ +static FLEXRAM_Type *const s_flexramBases[] = FLEXRAM_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to FLEXRAM clocks for each instance. */ +static const clock_ip_name_t s_flexramClocks[] = FLEXRAM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_flexramBases); instance++) + { + if (s_flexramBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_flexramBases)); + + return instance; +} + +/*! + * brief FLEXRAM module initialization function. + * + * param base FLEXRAM base address. + */ +void FLEXRAM_Init(FLEXRAM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate ENET clock. */ + CLOCK_EnableClock(s_flexramClocks[FLEXRAM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* enable all the interrupt status */ + base->INT_STAT_EN |= kFLEXRAM_InterruptStatusAll; + /* clear all the interrupt status */ + base->INT_STATUS |= kFLEXRAM_InterruptStatusAll; + /* disable all the interrpt */ + base->INT_SIG_EN = 0U; +} + +/*! + * brief Deinitializes the FLEXRAM. + * + */ +void FLEXRAN_Deinit(FLEXRAM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate ENET clock. */ + CLOCK_DisableClock(s_flexramClocks[FLEXRAM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +static uint8_t FLEXRAM_MapTcmSizeToRegister(uint8_t tcmBankNum) +{ + uint8_t tcmSizeConfig = 0U; + uint32_t totalTcmSize = 0U; + + /* if bank number is a odd value, use a new bank number which bigger than target */ + do + { + if ((tcmBankNum & (tcmBankNum - 1U)) == 0U) + { + break; + } + } while (++tcmBankNum < FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS); + + totalTcmSize = tcmBankNum * (FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE >> 10U); + /* get bit '1' position */ + while (totalTcmSize) + { + if ((totalTcmSize & 1U) == 0U) + { + tcmSizeConfig++; + } + else + { + break; + } + totalTcmSize >>= 1U; + } + + return tcmSizeConfig + 1U; +} + +void FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum) +{ + assert(itcmBankNum <= FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS); + assert(dtcmBankNum <= FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS); + + /* dtcm configuration */ + if (dtcmBankNum != 0U) + { + IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK; + IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(FLEXRAM_MapTcmSizeToRegister(dtcmBankNum)); + IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK; + } + else + { + IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK; + } + + /* itcm configuration */ + if (itcmBankNum != 0U) + { + IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK; + IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(FLEXRAM_MapTcmSizeToRegister(itcmBankNum)); + IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK; + } + else + { + IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK; + } +} + +/*! + * brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM + * This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate + * is needed. + * param config allocate configuration. + * retval kStatus_InvalidArgument the argument is invalid + * kStatus_Success allocate success + */ +status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config) +{ + assert(config != NULL); + + uint8_t dtcmBankNum = config->dtcmBankNum; + uint8_t itcmBankNum = config->itcmBankNum; + uint8_t ocramBankNum = config->ocramBankNum; + uint32_t bankCfg = 0U, i = 0U; + + /* check the arguments */ + if (FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS < (dtcmBankNum + itcmBankNum + ocramBankNum)) + { + return kStatus_InvalidArgument; + } + /* flexram bank config value */ + for (i = 0U; i < FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS; i++) + { + if (i < ocramBankNum) + { + bankCfg |= ((uint32_t)kFLEXRAM_BankOCRAM) << (i * 2); + continue; + } + + if (i < (dtcmBankNum + ocramBankNum)) + { + bankCfg |= ((uint32_t)kFLEXRAM_BankDTCM) << (i * 2); + continue; + } + + if (i < (dtcmBankNum + ocramBankNum + itcmBankNum)) + { + bankCfg |= ((uint32_t)kFLEXRAM_BankITCM) << (i * 2); + continue; + } + } + IOMUXC_GPR->GPR17 = bankCfg; + /* set TCM size */ + FLEXRAM_SetTCMSize(itcmBankNum, dtcmBankNum); + /* select ram allocate source from FLEXRAM_BANK_CFG */ + FLEXRAM_SetAllocateRamSrc(kFLEXRAM_BankAllocateThroughBankCfg); + + return kStatus_Success; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexram.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexram.h new file mode 100644 index 0000000000..f5e1859e9f --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexram.h @@ -0,0 +1,284 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_FLEXRAM_H_ +#define _FSL_FLEXRAM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexram + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.0.4. */ +#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 4U)) +/*@}*/ + +/*! @brief flexram write read sel */ +enum _flexram_wr_rd_sel +{ + kFLEXRAM_Read = 0U, /*!< read */ + kFLEXRAM_Write = 1U, /*!< write */ +}; + +/*! @brief Interrupt status flag mask */ +enum _flexram_interrupt_status +{ + kFLEXRAM_OCRAMAccessError = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK, /*!< ocram access unallocated address */ + kFLEXRAM_DTCMAccessError = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK, /*!< dtcm access unallocated address */ + kFLEXRAM_ITCMAccessError = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< itcm access unallocated address */ + + kFLEXRAM_InterruptStatusAll = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK | + FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< all the interrupt status mask */ +}; + +/*! @brief FLEXRAM TCM access mode + * Fast access mode expected to be finished in 1-cycle + * Wait access mode expected to be finished in 2-cycle + * Wait access mode is a feature of the flexram and it should be used when + * the cpu clock too fast to finish tcm access in 1-cycle. + * Normally, fast mode is the default mode, the efficiency of the tcm access will better. + */ +typedef enum _flexram_tcm_access_mode +{ + kFLEXRAM_TCMAccessFastMode = 0U, /*!< fast access mode */ + kFLEXRAM_TCMAccessWaitMode = 1U, /*!< wait access mode */ +} flexram_tcm_access_mode_t; + +/*! @brief FLEXRAM bank type */ +enum _flexram_bank_type +{ + kFLEXRAM_BankNotUsed = 0U, /*!< bank is not used */ + kFLEXRAM_BankOCRAM = 1U, /*!< bank is OCRAM */ + kFLEXRAM_BankDTCM = 2U, /*!< bank is DTCM */ + kFLEXRAM_BankITCM = 3U, /*!< bank is ITCM */ +}; + +/*! @brief FLEXRAM tcm support size */ +enum _flexram_tcm_size +{ + kFLEXRAM_TCMSize32KB = 32 * 1024U, /*!< TCM total size 32KB */ + kFLEXRAM_TCMSize64KB = 64 * 1024U, /*!< TCM total size 64KB */ + kFLEXRAM_TCMSize128KB = 128 * 1024U, /*!< TCM total size 128KB */ + kFLEXRAM_TCMSize256KB = 256 * 1024U, /*!< TCM total size 256KB */ + kFLEXRAM_TCMSize512KB = 512 * 1024U, /*!< TCM total size 512KB */ +}; + +/*! @brief FLEXRAM bank allocate source */ +typedef enum _flexram_bank_allocate_src +{ + kFLEXRAM_BankAllocateThroughHardwareFuse = 0U, /*!< allocate ram through hardware fuse value */ + kFLEXRAM_BankAllocateThroughBankCfg = 1U, /*!< allocate ram through FLEXRAM_BANK_CFG */ +} flexram_bank_allocate_src_t; + +/*! @brief FLEXRAM allocate ocram, itcm, dtcm size */ +typedef struct _flexram_allocate_ram +{ + const uint8_t ocramBankNum; /*!< ocram banknumber which the SOC support */ + const uint8_t dtcmBankNum; /*!< dtcm bank number to allocate, the number should be power of 2 */ + const uint8_t itcmBankNum; /*!< itcm bank number to allocate, the number should be power of 2 */ +} flexram_allocate_ram_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief FLEXRAM module initialization function. + * + * @param base FLEXRAM base address. + */ +void FLEXRAM_Init(FLEXRAM_Type *base); + +/*! + * @brief Deinitializes the FLEXRAM. + * + */ +void FLEXRAN_Deinit(FLEXRAM_Type *base); + +/* @} */ + +/*! + * @name Status + * @{ + */ +/*! + * @brief FLEXRAM module get interrupt status. + * + * @param base FLEXRAM base address. + */ +static inline uint32_t FLEXRAM_GetInterruptStatus(FLEXRAM_Type *base) +{ + return base->INT_STATUS & kFLEXRAM_InterruptStatusAll; +} + +/*! + * @brief FLEXRAM module clear interrupt status. + * + * @param base FLEXRAM base address. + * @param status status to clear. + */ +static inline void FLEXRAM_ClearInterruptStatus(FLEXRAM_Type *base, uint32_t status) +{ + base->INT_STATUS |= status; +} + +/*! + * @brief FLEXRAM module enable interrupt status. + * + * @param base FLEXRAM base address. + * @param status status to enable. + */ +static inline void FLEXRAM_EnableInterruptStatus(FLEXRAM_Type *base, uint32_t status) +{ + base->INT_STAT_EN |= status; +} + +/*! + * @brief FLEXRAM module disable interrupt status. + * + * @param base FLEXRAM base address. + * @param status status to disable. + */ +static inline void FLEXRAM_DisableInterruptStatus(FLEXRAM_Type *base, uint32_t status) +{ + base->INT_STAT_EN &= ~status; +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief FLEXRAM module enable interrupt. + * + * @param base FLEXRAM base address. + * @param status status interrupt to enable. + */ +static inline void FLEXRAM_EnableInterruptSignal(FLEXRAM_Type *base, uint32_t status) +{ + base->INT_SIG_EN |= status; +} + +/*! + * @brief FLEXRAM module disable interrupt. + * + * @param base FLEXRAM base address. + * @param status status interrupt to disable. + */ +static inline void FLEXRAM_DisableInterruptSignal(FLEXRAM_Type *base, uint32_t status) +{ + base->INT_SIG_EN &= ~status; +} +/* @} */ + +/*! + * @name functional + * @{ + */ + +/*! + * @brief FLEXRAM module set TCM read access mode + * + * @param base FLEXRAM base address. + * @param mode access mode. + */ +static inline void FLEXRAM_SetTCMReadAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode) +{ + base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK; + base->TCM_CTRL |= mode; +} + +/*! + * @brief FLEXRAM module set TCM write access mode + * + * @param base FLEXRAM base address. + * @param mode access mode. + */ +static inline void FLEXRAM_SetTCMWriteAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode) +{ + base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK; + base->TCM_CTRL |= mode; +} + +/*! + * @brief FLEXRAM module force ram clock on + * + * @param base FLEXRAM base address. + * @param enable enable or disable clock force on. + */ +static inline void FLEXRAM_EnableForceRamClockOn(FLEXRAM_Type *base, bool enable) +{ + if (enable) + { + base->TCM_CTRL |= FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK; + } + else + { + base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK; + } +} + +/*! + * @brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM + * This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate + * is needed. + * @param config allocate configuration. + * @retval kStatus_InvalidArgument the argument is invalid + * kStatus_Success allocate success + */ +status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config); + +/*! + * @brief FLEXRAM set allocate on-chip ram source + * @param src bank config source select value. + */ +static inline void FLEXRAM_SetAllocateRamSrc(flexram_bank_allocate_src_t src) +{ + IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK; + IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(src); +} + +/*! + * @brief FLEXRAM configure TCM size + * This function is used to set the TCM to the target size. If a odd bank number is used, + * a new banknumber will be used which is bigger than target value, application can set tcm + * size to the biggest bank number always, then boundary access error can be captured by flexram only. + * When access to the TCM memory boundary ,hardfault will raised by core. + * @param itcmBankNum itcm bank number to allocate + * @param dtcmBankNum dtcm bank number to allocate + * + */ +void FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexspi.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexspi.c new file mode 100644 index 0000000000..7972aff3ad --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexspi.c @@ -0,0 +1,1063 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexspi.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexspi" +#endif + +/******************************************************************************* + * Definitations + ******************************************************************************/ + +#define FREQ_1MHz (1000000UL) +#define FLEXSPI_DLLCR_DEFAULT (0x100UL) +#define FLEXSPI_LUT_KEY_VAL (0x5AF05AF0ul) + +enum +{ + kFLEXSPI_DelayCellUnitMin = 75, /* 75ps. */ + kFLEXSPI_DelayCellUnitMax = 225, /* 225ps. */ +}; + +enum +{ + kFLEXSPI_FlashASampleClockSlaveDelayLocked = + FLEXSPI_STS2_ASLVLOCK_MASK, /* Flash A sample clock slave delay line locked. */ + kFLEXSPI_FlashASampleClockRefDelayLocked = + FLEXSPI_STS2_AREFLOCK_MASK, /* Flash A sample clock reference delay line locked. */ + kFLEXSPI_FlashBSampleClockSlaveDelayLocked = + FLEXSPI_STS2_BSLVLOCK_MASK, /* Flash B sample clock slave delay line locked. */ + kFLEXSPI_FlashBSampleClockRefDelayLocked = + FLEXSPI_STS2_BREFLOCK_MASK, /* Flash B sample clock reference delay line locked. */ +}; + +/*! @brief Common sets of flags used by the driver. */ +enum _flexspi_flag_constants +{ + /*! IRQ sources enabled by the non-blocking transactional API. */ + kIrqFlags = kFLEXSPI_IpTxFifoWatermarkEmpltyFlag | kFLEXSPI_IpRxFifoWatermarkAvailableFlag | + kFLEXSPI_SequenceExecutionTimeoutFlag | kFLEXSPI_IpCommandSequenceErrorFlag | + kFLEXSPI_IpCommandGrantTimeoutFlag | kFLEXSPI_IpCommandExcutionDoneFlag, + + /*! Errors to check for. */ + kErrorFlags = kFLEXSPI_SequenceExecutionTimeoutFlag | kFLEXSPI_IpCommandSequenceErrorFlag | + kFLEXSPI_IpCommandGrantTimeoutFlag, +}; + +enum _flexspi_transfer_state +{ + kFLEXSPI_Idle = 0x0U, /*!< Transfer is done. */ + kFLEXSPI_BusyWrite = 0x1U, /*!< FLEXSPI is busy write transfer. */ + kFLEXSPI_BusyRead = 0x2U, /*!< FLEXSPI is busy write transfer. */ +}; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*flexspi_isr_t)(FLEXSPI_Type *base, void *flexspiHandle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance number for FLEXSPI. + * + * @param base FLEXSPI base pointer. + */ +uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base); + +/*! + * @brief Configure flash A/B sample clock DLL. + * + * @param base FLEXSPI base pointer. + * @param config Flash configuration parameters. + */ +static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config); + +/*! + * @brief Check and clear IP command execution errors. + * + * @param base FLEXSPI base pointer. + * @param status interrupt status. + */ +status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to flexspi bases for each instance. */ +static FLEXSPI_Type *const s_flexspiBases[] = FLEXSPI_BASE_PTRS; + +/*! @brief Pointers to flexspi IRQ number for each instance. */ +static const IRQn_Type s_flexspiIrqs[] = FLEXSPI_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Clock name array */ +static const clock_ip_name_t s_flexspiClock[] = FLEXSPI_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +/*! @brief Pointers to flexspi handles for each instance. */ +static void *s_flexspiHandle[ARRAY_SIZE(s_flexspiBases)]; +#endif + +#if defined(FSL_FEATURE_FLEXSPI_HAS_RESET) && FSL_FEATURE_FLEXSPI_HAS_RESET +/*! @brief Pointers to FLEXSPI resets for each instance. */ +static const reset_ip_name_t s_flexspiResets[] = FLEXSPI_RSTS; +#endif +/******************************************************************************* + * Code + ******************************************************************************/ + +uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_flexspiBases); instance++) + { + if (s_flexspiBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_flexspiBases)); + + return instance; +} + +static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config) +{ + bool isUnifiedConfig = true; + uint32_t flexspiDllValue; + uint32_t dllValue; + uint32_t temp; + + uint8_t rxSampleClock = (base->MCR0 & FLEXSPI_MCR0_RXCLKSRC_MASK) >> FLEXSPI_MCR0_RXCLKSRC_SHIFT; + switch (rxSampleClock) + { + case kFLEXSPI_ReadSampleClkLoopbackInternally: + case kFLEXSPI_ReadSampleClkLoopbackFromDqsPad: + case kFLEXSPI_ReadSampleClkLoopbackFromSckPad: + isUnifiedConfig = true; + break; + case kFLEXSPI_ReadSampleClkExternalInputFromDqsPad: + if (config->isSck2Enabled) + { + isUnifiedConfig = true; + } + else + { + isUnifiedConfig = false; + } + break; + default: + break; + } + + if (isUnifiedConfig) + { + flexspiDllValue = FLEXSPI_DLLCR_DEFAULT; /* 1 fixed delay cells in DLL delay chain) */ + } + else + { + if (config->flexspiRootClk >= 100 * FREQ_1MHz) + { + /* DLLEN = 1, SLVDLYTARGET = 0xF, */ + flexspiDllValue = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(0x0F); + } + else + { + temp = config->dataValidTime * 1000; /* Convert data valid time in ns to ps. */ + dllValue = temp / kFLEXSPI_DelayCellUnitMin; + if (dllValue * kFLEXSPI_DelayCellUnitMin < temp) + { + dllValue++; + } + flexspiDllValue = FLEXSPI_DLLCR_OVRDEN(1) | FLEXSPI_DLLCR_OVRDVAL(dllValue); + } + } + return flexspiDllValue; +} + +status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check for error. */ + status &= kErrorFlags; + if (status) + { + /* Select the correct error code.. */ + if (status & kFLEXSPI_SequenceExecutionTimeoutFlag) + { + result = kStatus_FLEXSPI_SequenceExecutionTimeout; + } + else if (status & kFLEXSPI_IpCommandSequenceErrorFlag) + { + result = kStatus_FLEXSPI_IpCommandSequenceError; + } + else if (status & kFLEXSPI_IpCommandGrantTimeoutFlag) + { + result = kStatus_FLEXSPI_IpCommandGrantTimeout; + } + else + { + assert(false); + } + + /* Clear the flags. */ + FLEXSPI_ClearInterruptStatusFlags(base, status); + + /* Reset fifos. These flags clear automatically. */ + base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; + base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; + } + + return result; +} + +/*! + * brief Initializes the FLEXSPI module and internal state. + * + * This function enables the clock for FLEXSPI and also configures the FLEXSPI with the + * input configure parameters. Users should call this function before any FLEXSPI operations. + * + * param base FLEXSPI peripheral base address. + * param config FLEXSPI configure structure. + */ +void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config) +{ + uint32_t configValue = 0; + uint8_t i = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the flexspi clock */ + CLOCK_EnableClock(s_flexspiClock[FLEXSPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_FLEXSPI_HAS_RESET) && FSL_FEATURE_FLEXSPI_HAS_RESET + /* Reset the FLEXSPI module */ + RESET_PeripheralReset(s_flexspiResets[FLEXSPI_GetInstance(base)]); +#endif + + /* Reset peripheral before configuring it. */ + base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; + FLEXSPI_SoftwareReset(base); + + /* Configure MCR0 configuration items. */ + configValue = FLEXSPI_MCR0_RXCLKSRC(config->rxSampleClock) | FLEXSPI_MCR0_DOZEEN(config->enableDoze) | + FLEXSPI_MCR0_IPGRANTWAIT(config->ipGrantTimeoutCycle) | + FLEXSPI_MCR0_AHBGRANTWAIT(config->ahbConfig.ahbGrantTimeoutCycle) | + FLEXSPI_MCR0_SCKFREERUNEN(config->enableSckFreeRunning) | + FLEXSPI_MCR0_HSEN(config->enableHalfSpeedAccess) | + FLEXSPI_MCR0_COMBINATIONEN(config->enableCombination) | + FLEXSPI_MCR0_ATDFEN(config->ahbConfig.enableAHBWriteIpTxFifo) | + FLEXSPI_MCR0_ARDFEN(config->ahbConfig.enableAHBWriteIpRxFifo) | FLEXSPI_MCR0_MDIS_MASK; + base->MCR0 = configValue; + + /* Configure MCR1 configurations. */ + configValue = + FLEXSPI_MCR1_SEQWAIT(config->seqTimeoutCycle) | FLEXSPI_MCR1_AHBBUSWAIT(config->ahbConfig.ahbBusTimeoutCycle); + base->MCR1 = configValue; + + /* Configure MCR2 configurations. */ + configValue = base->MCR2; + configValue &= ~(FLEXSPI_MCR2_RESUMEWAIT_MASK | FLEXSPI_MCR2_SCKBDIFFOPT_MASK | FLEXSPI_MCR2_SAMEDEVICEEN_MASK | + FLEXSPI_MCR2_CLRAHBBUFOPT_MASK); + configValue |= FLEXSPI_MCR2_RESUMEWAIT(config->ahbConfig.resumeWaitCycle) | + FLEXSPI_MCR2_SCKBDIFFOPT(config->enableSckBDiffOpt) | + FLEXSPI_MCR2_SAMEDEVICEEN(config->enableSameConfigForAll) | + FLEXSPI_MCR2_CLRAHBBUFOPT(config->ahbConfig.enableClearAHBBufferOpt); + + base->MCR2 = configValue; + + /* Configure AHB control items. */ + configValue = base->AHBCR; + configValue &= ~(FLEXSPI_AHBCR_READADDROPT_MASK | FLEXSPI_AHBCR_PREFETCHEN_MASK | FLEXSPI_AHBCR_BUFFERABLEEN_MASK | + FLEXSPI_AHBCR_CACHABLEEN_MASK); + configValue |= FLEXSPI_AHBCR_READADDROPT(config->ahbConfig.enableReadAddressOpt) | + FLEXSPI_AHBCR_PREFETCHEN(config->ahbConfig.enableAHBPrefetch) | + FLEXSPI_AHBCR_BUFFERABLEEN(config->ahbConfig.enableAHBBufferable) | + FLEXSPI_AHBCR_CACHABLEEN(config->ahbConfig.enableAHBCachable); + base->AHBCR = configValue; + + /* Configure AHB rx buffers. */ + for (i = 0; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++) + { + configValue = base->AHBRXBUFCR0[i]; + + configValue &= ~(FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK | FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK | + FLEXSPI_AHBRXBUFCR0_MSTRID_MASK | FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK); + configValue |= FLEXSPI_AHBRXBUFCR0_PREFETCHEN(config->ahbConfig.buffer[i].enablePrefetch) | + FLEXSPI_AHBRXBUFCR0_PRIORITY(config->ahbConfig.buffer[i].priority) | + FLEXSPI_AHBRXBUFCR0_MSTRID(config->ahbConfig.buffer[i].masterIndex) | + FLEXSPI_AHBRXBUFCR0_BUFSZ(config->ahbConfig.buffer[i].bufferSize / 8); + base->AHBRXBUFCR0[i] = configValue; + } + + /* Configure IP Fifo watermarks. */ + base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXWMRK_MASK; + base->IPRXFCR |= FLEXSPI_IPRXFCR_RXWMRK(config->rxWatermark / 8 - 1); + base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXWMRK_MASK; + base->IPTXFCR |= FLEXSPI_IPTXFCR_TXWMRK(config->txWatermark / 8 - 1); + + /* Reset flash size on all ports */ + for (i = 0; i < kFLEXSPI_PortCount; i++) + { + base->FLSHCR0[i] = 0; + } +} + +/*! + * brief Gets default settings for FLEXSPI. + * + * param config FLEXSPI configuration structure. + */ +void FLEXSPI_GetDefaultConfig(flexspi_config_t *config) +{ + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally; + config->enableSckFreeRunning = false; + config->enableCombination = false; + config->enableDoze = true; + config->enableHalfSpeedAccess = false; + config->enableSckBDiffOpt = false; + config->enableSameConfigForAll = false; + config->seqTimeoutCycle = 0xFFFFU; + config->ipGrantTimeoutCycle = 0xFFU; + config->txWatermark = 8; + config->rxWatermark = 8; + config->ahbConfig.enableAHBWriteIpTxFifo = false; + config->ahbConfig.enableAHBWriteIpRxFifo = false; + config->ahbConfig.ahbGrantTimeoutCycle = 0xFFU; + config->ahbConfig.ahbBusTimeoutCycle = 0xFFFFU; + config->ahbConfig.resumeWaitCycle = 0x20U; + memset(config->ahbConfig.buffer, 0, sizeof(config->ahbConfig.buffer)); + for (uint8_t i = 0; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++) + { + config->ahbConfig.buffer[i].enablePrefetch = true; /* Default enable AHB prefetch. */ + config->ahbConfig.buffer[i].bufferSize = 256; /* Default buffer size 256 bytes*/ + } + config->ahbConfig.enableClearAHBBufferOpt = false; + config->ahbConfig.enableReadAddressOpt = false; + config->ahbConfig.enableAHBPrefetch = false; + config->ahbConfig.enableAHBBufferable = false; + config->ahbConfig.enableAHBCachable = false; +} + +/*! + * brief Deinitializes the FLEXSPI module. + * + * Clears the FLEXSPI state and FLEXSPI module registers. + * param base FLEXSPI peripheral base address. + */ +void FLEXSPI_Deinit(FLEXSPI_Type *base) +{ + /* Reset peripheral. */ + FLEXSPI_SoftwareReset(base); +} + +/*! + * brief Configures the connected device parameter. + * + * This function configures the connected device relevant parameters, such as the size, command, and so on. + * The flash configuration value cannot have a default value. The user needs to configure it according to the + * connected device. + * + * param base FLEXSPI peripheral base address. + * param config Flash configuration parameters. + * param port FLEXSPI Operation port. + */ +void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port) +{ + uint32_t configValue = 0; + uint32_t statusValue = 0; + uint8_t index = port >> 1; /* PortA with index 0, PortB with index 1. */ + + /* Wait for bus idle before change flash configuration. */ + while (!FLEXSPI_GetBusIdleStatus(base)) + { + } + + /* Configure flash size. */ + base->FLSHCR0[port] = config->flashSize; + + /* Configure flash parameters. */ + base->FLSHCR1[port] = FLEXSPI_FLSHCR1_CSINTERVAL(config->CSInterval) | + FLEXSPI_FLSHCR1_CSINTERVALUNIT(config->CSIntervalUnit) | + FLEXSPI_FLSHCR1_TCSH(config->CSHoldTime) | FLEXSPI_FLSHCR1_TCSS(config->CSSetupTime) | + FLEXSPI_FLSHCR1_CAS(config->columnspace) | FLEXSPI_FLSHCR1_WA(config->enableWordAddress); + + /* Configure AHB operation items. */ + configValue = base->FLSHCR2[port]; + + configValue &= ~(FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK | FLEXSPI_FLSHCR2_AWRWAIT_MASK | FLEXSPI_FLSHCR2_AWRSEQNUM_MASK | + FLEXSPI_FLSHCR2_AWRSEQID_MASK | FLEXSPI_FLSHCR2_ARDSEQNUM_MASK | FLEXSPI_FLSHCR2_AWRSEQID_MASK); + + configValue |= + FLEXSPI_FLSHCR2_AWRWAITUNIT(config->AHBWriteWaitUnit) | FLEXSPI_FLSHCR2_AWRWAIT(config->AHBWriteWaitInterval); + + if (config->AWRSeqNumber > 0U) + { + configValue |= + FLEXSPI_FLSHCR2_AWRSEQID(config->AWRSeqIndex) | FLEXSPI_FLSHCR2_AWRSEQNUM(config->AWRSeqNumber - 1U); + } + + if (config->ARDSeqNumber > 0U) + { + configValue |= + FLEXSPI_FLSHCR2_ARDSEQID(config->ARDSeqIndex) | FLEXSPI_FLSHCR2_ARDSEQNUM(config->ARDSeqNumber - 1U); + } + + base->FLSHCR2[port] = configValue; + + /* Configure DLL. */ + configValue = FLEXSPI_ConfigureDll(base, config); + base->DLLCR[index] = configValue; + + /* Configure write mask. */ + if (config->enableWriteMask) + { + base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMOPT1_MASK; + } + else + { + base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMOPT1_MASK; + } + + if (index == 0) /*PortA*/ + { + base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENA_MASK; + base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENA(config->enableWriteMask); + } + else + { + base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENB_MASK; + base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMENB(config->enableWriteMask); + } + + /* Exit stop mode. */ + base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; + + /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */ + statusValue = (index == 0) ? + (kFLEXSPI_FlashASampleClockSlaveDelayLocked | kFLEXSPI_FlashASampleClockRefDelayLocked) : + (kFLEXSPI_FlashBSampleClockSlaveDelayLocked | kFLEXSPI_FlashBSampleClockRefDelayLocked); + + if (configValue & FLEXSPI_DLLCR_DLLEN_MASK) + { + /* Wait slave delay line locked and slave reference delay line locked. */ + while ((base->STS2 & statusValue) != statusValue) + { + } + + /* Wait at least 100 NOPs*/ + for (uint8_t delay = 100; delay > 0; delay--) + { + __NOP(); + } + } +} + +/*! brief Updates the LUT table. + * + * param base FLEXSPI peripheral base address. + * param index From which index start to update. It could be any index of the LUT table, which + * also allows user to update command content inside a command. Each command consists of up to + * 8 instructions and occupy 4*32-bit memory. + * param cmd Command sequence array. + * param count Number of sequences. + */ +void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count) +{ + assert(index < 64U); + + uint8_t i = 0; + volatile uint32_t *lutBase; + + /* Wait for bus idle before change flash configuration. */ + while (!FLEXSPI_GetBusIdleStatus(base)) + { + } + + /* Unlock LUT for update. */ + base->LUTKEY = FLEXSPI_LUT_KEY_VAL; + base->LUTCR = 0x02; + + lutBase = &base->LUT[index]; + for (i = 0; i < count; i++) + { + *lutBase++ = *cmd++; + } + + /* Lock LUT. */ + base->LUTKEY = FLEXSPI_LUT_KEY_VAL; + base->LUTCR = 0x01; +} + +/*! brief Update read sample clock source + * + * param base FLEXSPI peripheral base address. + * param clockSource clockSource of type #flexspi_read_sample_clock_t + */ +void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource) +{ + uint32_t mcr0Val; + + /* Wait for bus idle before change flash configuration. */ + while (!FLEXSPI_GetBusIdleStatus(base)) + { + } + + mcr0Val = base->MCR0; + mcr0Val &= ~FLEXSPI_MCR0_RXCLKSRC_MASK; + mcr0Val |= FLEXSPI_MCR0_RXCLKSRC(clockSource); + base->MCR0 = mcr0Val; + + /* Reset peripheral. */ + FLEXSPI_SoftwareReset(base); +} + +/*! + * brief Sends a buffer of data bytes using blocking method. + * note This function blocks via polling until all bytes have been sent. + * param base FLEXSPI peripheral base address + * param buffer The data bytes to send + * param size The number of data bytes to send + * retval kStatus_Success write success without error + * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout + * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected + * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected + */ +status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) +{ + uint8_t txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1; + uint32_t status; + status_t result = kStatus_Success; + uint32_t i = 0; + + /* Send data buffer */ + while (size) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + while (!((status = base->INTR) & kFLEXSPI_IpTxFifoWatermarkEmpltyFlag)) + { + } + + result = FLEXSPI_CheckAndClearError(base, status); + + if (result) + { + return result; + } + + /* Write watermark level data into tx fifo . */ + if (size >= 8 * txWatermark) + { + for (i = 0; i < 2 * txWatermark; i++) + { + base->TFDR[i] = *buffer++; + } + + size = size - 8 * txWatermark; + } + else + { + for (i = 0; i < (size / 4 + 1); i++) + { + base->TFDR[i] = *buffer++; + } + size = 0; + } + + /* Push a watermark level datas into IP TX FIFO. */ + base->INTR |= kFLEXSPI_IpTxFifoWatermarkEmpltyFlag; + } + + return result; +} + +/*! + * brief Receives a buffer of data bytes using a blocking method. + * note This function blocks via polling until all bytes have been sent. + * param base FLEXSPI peripheral base address + * param buffer The data bytes to send + * param size The number of data bytes to receive + * retval kStatus_Success read success without error + * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout + * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected + * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected + */ +status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) +{ + uint8_t rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1; + uint32_t status; + status_t result = kStatus_Success; + uint32_t i = 0; + + /* Send data buffer */ + while (size) + { + if (size >= 8 * rxWatermark) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + while (!((status = base->INTR) & kFLEXSPI_IpRxFifoWatermarkAvailableFlag)) + { + result = FLEXSPI_CheckAndClearError(base, status); + + if (result) + { + return result; + } + } + } + else + { + /* Wait fill level. This also checks for errors. */ + while (size > ((((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U)) + { + result = FLEXSPI_CheckAndClearError(base, base->INTR); + + if (result) + { + return result; + } + } + } + + result = FLEXSPI_CheckAndClearError(base, base->INTR); + + if (result) + { + return result; + } + + /* Read watermark level data from rx fifo . */ + if (size >= 8 * rxWatermark) + { + for (i = 0; i < 2 * rxWatermark; i++) + { + *buffer++ = base->RFDR[i]; + } + + size = size - 8 * rxWatermark; + } + else + { + for (i = 0; i < (size / 4 + 1); i++) + { + *buffer++ = base->RFDR[i]; + } + size = 0; + } + + /* Pop out a watermark level datas from IP RX FIFO. */ + base->INTR |= kFLEXSPI_IpRxFifoWatermarkAvailableFlag; + } + + return result; +} + +/*! + * brief Execute command to transfer a buffer data bytes using a blocking method. + * param base FLEXSPI peripheral base address + * param xfer pointer to the transfer structure. + * retval kStatus_Success command transfer success without error + * retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout + * retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected + * retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected + */ +status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer) +{ + uint32_t configValue = 0; + status_t result = kStatus_Success; + + /* Clear sequence pointer before sending data to external devices. */ + base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK; + + /* Clear former pending status before start this transfer. */ + base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | + FLEXSPI_INTR_IPCMDGE_MASK; + + /* Configure base address. */ + base->IPCR0 = xfer->deviceAddress; + + /* Reset fifos. */ + base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; + base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; + + /* Configure data size. */ + if ((xfer->cmdType == kFLEXSPI_Read) || (xfer->cmdType == kFLEXSPI_Write) || (xfer->cmdType == kFLEXSPI_Config)) + { + configValue = FLEXSPI_IPCR1_IDATSZ(xfer->dataSize); + } + + /* Configure sequence ID. */ + configValue |= FLEXSPI_IPCR1_ISEQID(xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM(xfer->SeqNumber - 1); + base->IPCR1 = configValue; + + /* Start Transfer. */ + base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK; + + if ((xfer->cmdType == kFLEXSPI_Write) || (xfer->cmdType == kFLEXSPI_Config)) + { + result = FLEXSPI_WriteBlocking(base, xfer->data, xfer->dataSize); + } + else if (xfer->cmdType == kFLEXSPI_Read) + { + result = FLEXSPI_ReadBlocking(base, xfer->data, xfer->dataSize); + } + else + { + } + + /* Wait for bus idle. */ + while (!FLEXSPI_GetBusIdleStatus(base)) + { + } + + if (xfer->cmdType == kFLEXSPI_Command) + { + result = FLEXSPI_CheckAndClearError(base, base->INTR); + } + + return result; +} + +/*! + * brief Initializes the FLEXSPI handle which is used in transactional functions. + * + * param base FLEXSPI peripheral base address. + * param handle pointer to flexspi_handle_t structure to store the transfer state. + * param callback pointer to user callback function. + * param userData user parameter passed to the callback function. + */ +void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, + flexspi_handle_t *handle, + flexspi_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + uint32_t instance = FLEXSPI_GetInstance(base); + + /* Zero handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + +#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ + /* Save the context in global variables to support the double weak mechanism. */ + s_flexspiHandle[instance] = handle; +#endif + + /* Enable NVIC interrupt. */ + EnableIRQ(s_flexspiIrqs[instance]); +} + +/*! + * brief Performs a interrupt non-blocking transfer on the FLEXSPI bus. + * + * note Calling the API returns immediately after transfer initiates. The user needs + * to call FLEXSPI_GetTransferCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer + * is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark levle, or + * FLEXSPI could not read data properly. + * + * param base FLEXSPI peripheral base address. + * param handle pointer to flexspi_handle_t structure which stores the transfer state. + * param xfer pointer to flexspi_transfer_t structure. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_FLEXSPI_Busy Previous transmission still not finished. + */ +status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer) +{ + uint32_t configValue = 0; + status_t result = kStatus_Success; + + assert(handle); + assert(xfer); + + /* Check if the I2C bus is idle - if not return busy status. */ + if (handle->state != kFLEXSPI_Idle) + { + result = kStatus_FLEXSPI_Busy; + } + else + { + handle->data = xfer->data; + handle->dataSize = xfer->dataSize; + handle->transferTotalSize = xfer->dataSize; + handle->state = (xfer->cmdType == kFLEXSPI_Read) ? kFLEXSPI_BusyRead : kFLEXSPI_BusyWrite; + + /* Clear sequence pointer before sending data to external devices. */ + base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK; + + /* Clear former pending status before start this transfer. */ + base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK | + FLEXSPI_INTR_IPCMDGE_MASK; + + /* Configure base address. */ + base->IPCR0 = xfer->deviceAddress; + + /* Reset fifos. */ + base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; + base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; + + /* Configure data size. */ + if ((xfer->cmdType == kFLEXSPI_Read) || (xfer->cmdType == kFLEXSPI_Write)) + { + configValue = FLEXSPI_IPCR1_IDATSZ(xfer->dataSize); + } + + /* Configure sequence ID. */ + configValue |= FLEXSPI_IPCR1_ISEQID(xfer->seqIndex) | FLEXSPI_IPCR1_ISEQNUM(xfer->SeqNumber - 1); + base->IPCR1 = configValue; + + /* Start Transfer. */ + base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK; + + if (handle->state == kFLEXSPI_BusyRead) + { + FLEXSPI_EnableInterrupts(base, kFLEXSPI_IpRxFifoWatermarkAvailableFlag | + kFLEXSPI_SequenceExecutionTimeoutFlag | + kFLEXSPI_IpCommandSequenceErrorFlag | + kFLEXSPI_IpCommandGrantTimeoutFlag | kFLEXSPI_IpCommandExcutionDoneFlag); + } + else + { + FLEXSPI_EnableInterrupts(base, kFLEXSPI_IpTxFifoWatermarkEmpltyFlag | + kFLEXSPI_SequenceExecutionTimeoutFlag | + kFLEXSPI_IpCommandSequenceErrorFlag | + kFLEXSPI_IpCommandGrantTimeoutFlag | kFLEXSPI_IpCommandExcutionDoneFlag); + } + } + + return result; +} + +/*! + * brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * param base FLEXSPI peripheral base address. + * param handle pointer to flexspi_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t result = kStatus_Success; + + if (handle->state == kFLEXSPI_Idle) + { + result = kStatus_NoTransferInProgress; + } + else + { + *count = handle->transferTotalSize - handle->dataSize; + } + + return result; +} + +/*! + * brief Aborts an interrupt non-blocking transfer early. + * + * note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base FLEXSPI peripheral base address. + * param handle pointer to flexspi_handle_t structure which stores the transfer state + */ +void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle) +{ + assert(handle); + + FLEXSPI_DisableInterrupts(base, kIrqFlags); + handle->state = kFLEXSPI_Idle; +} + +/*! + * brief Master interrupt handler. + * + * param base FLEXSPI peripheral base address. + * param handle pointer to flexspi_handle_t structure. + */ +void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle) +{ + uint32_t status; + status_t result; + uint32_t intEnableStatus; + uint8_t txWatermark; + uint8_t rxWatermark; + uint8_t i = 0; + + status = base->INTR; + intEnableStatus = base->INTEN; + + /* Check if interrupt is enabled and status is alerted. */ + if ((status & intEnableStatus) == 0U) + { + return; + } + + result = FLEXSPI_CheckAndClearError(base, status); + + if ((result != kStatus_Success) && (handle->completionCallback != NULL)) + { + FLEXSPI_TransferAbort(base, handle); + if (handle->completionCallback) + { + handle->completionCallback(base, handle, result, handle->userData); + } + return; + } + + if ((status & kFLEXSPI_IpRxFifoWatermarkAvailableFlag) && (handle->state == kFLEXSPI_BusyRead)) + { + rxWatermark = ((base->IPRXFCR & FLEXSPI_IPRXFCR_RXWMRK_MASK) >> FLEXSPI_IPRXFCR_RXWMRK_SHIFT) + 1; + + /* Read watermark level data from rx fifo . */ + if (handle->dataSize >= 8 * rxWatermark) + { + /* Read watermark level data from rx fifo . */ + for (i = 0; i < 2 * rxWatermark; i++) + { + *handle->data++ = base->RFDR[i]; + } + + handle->dataSize = handle->dataSize - 8 * rxWatermark; + } + else + { + for (i = 0; i < (handle->dataSize / 4 + 1); i++) + { + *handle->data++ = base->RFDR[i]; + } + handle->dataSize = 0; + } + /* Pop out a watermark level datas from IP RX FIFO. */ + base->INTR |= kFLEXSPI_IpRxFifoWatermarkAvailableFlag; + } + + if (status & kFLEXSPI_IpCommandExcutionDoneFlag) + { + base->INTR |= kFLEXSPI_IpCommandExcutionDoneFlag; + + FLEXSPI_TransferAbort(base, handle); + + if (handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_Success, handle->userData); + } + } + + /* TX FIFO empty interrupt, push watermark level data into tx FIFO. */ + if ((status & kFLEXSPI_IpTxFifoWatermarkEmpltyFlag) && (handle->state == kFLEXSPI_BusyWrite)) + { + if (handle->dataSize) + { + txWatermark = ((base->IPTXFCR & FLEXSPI_IPTXFCR_TXWMRK_MASK) >> FLEXSPI_IPTXFCR_TXWMRK_SHIFT) + 1; + /* Write watermark level data into tx fifo . */ + if (handle->dataSize >= 8 * txWatermark) + { + for (i = 0; i < 2 * txWatermark; i++) + { + base->TFDR[i] = *handle->data++; + } + + handle->dataSize = handle->dataSize - 8 * txWatermark; + } + else + { + for (i = 0; i < (handle->dataSize / 4 + 1); i++) + { + base->TFDR[i] = *handle->data++; + } + handle->dataSize = 0; + } + + /* Push a watermark level datas into IP TX FIFO. */ + base->INTR |= kFLEXSPI_IpTxFifoWatermarkEmpltyFlag; + } + } + else + { + } +} + +#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#if defined(FLEXSPI) +void FLEXSPI_DriverIRQHandler(void) +{ + FLEXSPI_TransferHandleIRQ(FLEXSPI, s_flexspiHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXSPI0) +void FLEXSPI0_DriverIRQHandler(void) +{ + FLEXSPI_TransferHandleIRQ(FLEXSPI0, s_flexspiHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#if defined(FLEXSPI1) +void FLEXSPI1_DriverIRQHandler(void) +{ + FLEXSPI_TransferHandleIRQ(FLEXSPI1, s_flexspiHandle[1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(LSIO__FLEXSPI0) +void LSIO_OCTASPI0_INT_DriverIRQHandler(void) +{ + FLEXSPI_TransferHandleIRQ(LSIO__FLEXSPI0, s_flexspiHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#if defined(LSIO__FLEXSPI1) +void LSIO_OCTASPI1_INT_DriverIRQHandler(void) +{ + FLEXSPI_TransferHandleIRQ(LSIO__FLEXSPI1, s_flexspiHandle[1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#endif diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexspi.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexspi.h new file mode 100644 index 0000000000..fcafc20f43 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_flexspi.h @@ -0,0 +1,826 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FSL_FLEXSPI_H_ +#define __FSL_FLEXSPI_H_ + +#include +#include "fsl_device_registers.h" +#include "fsl_common.h" + +/*! + * @addtogroup flexspi + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FLEXSPI driver version 2.1.1. */ +#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ + +#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0) + +/*! @breif Formula to form FLEXSPI instructions in LUT table. */ +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +/*! @brief Status structure of FLEXSPI.*/ +enum _flexspi_status +{ + kStatus_FLEXSPI_Busy = MAKE_STATUS(kStatusGroup_FLEXSPI, 0), /*!< FLEXSPI is busy */ + kStatus_FLEXSPI_SequenceExecutionTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 1), /*!< Sequence execution timeout + error occurred during FLEXSPI transfer. */ + kStatus_FLEXSPI_IpCommandSequenceError = MAKE_STATUS(kStatusGroup_FLEXSPI, 2), /*!< IP command Sequence execution + timeout error occurred during FLEXSPI transfer. */ + kStatus_FLEXSPI_IpCommandGrantTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 3), /*!< IP command grant timeout error + occurred during FLEXSPI transfer. */ +}; + +/*! @brief CMD definition of FLEXSPI, use to form LUT instruction. */ +enum _flexspi_command +{ + kFLEXSPI_Command_STOP = 0x00U, /*!< Stop execution, deassert CS. */ + kFLEXSPI_Command_SDR = 0x01U, /*!< Transmit Command code to Flash, using SDR mode. */ + kFLEXSPI_Command_RADDR_SDR = 0x02U, /*!< Transmit Row Address to Flash, using SDR mode. */ + kFLEXSPI_Command_CADDR_SDR = 0x03U, /*!< Transmit Column Address to Flash, using SDR mode. */ + kFLEXSPI_Command_MODE1_SDR = 0x04U, /*!< Transmit 1-bit Mode bits to Flash, using SDR mode. */ + kFLEXSPI_Command_MODE2_SDR = 0x05U, /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */ + kFLEXSPI_Command_MODE4_SDR = 0x06U, /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */ + kFLEXSPI_Command_MODE8_SDR = 0x07U, /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */ + kFLEXSPI_Command_WRITE_SDR = 0x08U, /*!< Transmit Programming Data to Flash, using SDR mode. */ + kFLEXSPI_Command_READ_SDR = 0x09U, /*!< Receive Read Data from Flash, using SDR mode. */ + kFLEXSPI_Command_LEARN_SDR = 0x0AU, /*!< Receive Read Data or Preamble bit from Flash, SDR mode. */ + kFLEXSPI_Command_DATSZ_SDR = 0x0BU, /*!< Transmit Read/Program Data size (byte) to Flash, SDR mode. */ + kFLEXSPI_Command_DUMMY_SDR = 0x0CU, /*!< Leave data lines undriven by FlexSPI controller.*/ + kFLEXSPI_Command_DUMMY_RWDS_SDR = 0x0DU, /*!< Leave data lines undriven by FlexSPI controller, + dummy cycles decided by RWDS. */ + kFLEXSPI_Command_DDR = 0x21U, /*!< Transmit Command code to Flash, using DDR mode. */ + kFLEXSPI_Command_RADDR_DDR = 0x22U, /*!< Transmit Row Address to Flash, using DDR mode. */ + kFLEXSPI_Command_CADDR_DDR = 0x23U, /*!< Transmit Column Address to Flash, using DDR mode. */ + kFLEXSPI_Command_MODE1_DDR = 0x24U, /*!< Transmit 1-bit Mode bits to Flash, using DDR mode. */ + kFLEXSPI_Command_MODE2_DDR = 0x25U, /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */ + kFLEXSPI_Command_MODE4_DDR = 0x26U, /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */ + kFLEXSPI_Command_MODE8_DDR = 0x27U, /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */ + kFLEXSPI_Command_WRITE_DDR = 0x28U, /*!< Transmit Programming Data to Flash, using DDR mode. */ + kFLEXSPI_Command_READ_DDR = 0x29U, /*!< Receive Read Data from Flash, using DDR mode. */ + kFLEXSPI_Command_LEARN_DDR = 0x2AU, /*!< Receive Read Data or Preamble bit from Flash, DDR mode. */ + kFLEXSPI_Command_DATSZ_DDR = 0x2BU, /*!< Transmit Read/Program Data size (byte) to Flash, DDR mode. */ + kFLEXSPI_Command_DUMMY_DDR = 0x2CU, /*!< Leave data lines undriven by FlexSPI controller.*/ + kFLEXSPI_Command_DUMMY_RWDS_DDR = 0x2DU, /*!< Leave data lines undriven by FlexSPI controller, + dummy cycles decided by RWDS. */ + kFLEXSPI_Command_JUMP_ON_CS = 0x1FU, /*!< Stop execution, deassert CS and save operand[7:0] as the + instruction start pointer for next sequence */ +}; + +/*! @brief pad definition of FLEXSPI, use to form LUT instruction. */ +typedef enum _flexspi_pad +{ + kFLEXSPI_1PAD = 0x00U, /*!< Transmit command/address and transmit/receive data only through DATA0/DATA1. */ + kFLEXSPI_2PAD = 0x01U, /*!< Transmit command/address and transmit/receive data only through DATA[1:0]. */ + kFLEXSPI_4PAD = 0x02U, /*!< Transmit command/address and transmit/receive data only through DATA[3:0]. */ + kFLEXSPI_8PAD = 0x03U, /*!< Transmit command/address and transmit/receive data only through DATA[7:0]. */ +} flexspi_pad_t; + +/*! @brief FLEXSPI interrupt status flags.*/ +typedef enum _flexspi_flags +{ + kFLEXSPI_SequenceExecutionTimeoutFlag = FLEXSPI_INTEN_SEQTIMEOUTEN_MASK, /*!< Sequence execution timeout. */ + kFLEXSPI_AhbBusTimeoutFlag = FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK, /*!< AHB Bus timeout. */ + kFLEXSPI_SckStoppedBecauseTxEmptyFlag = + FLEXSPI_INTEN_SCKSTOPBYWREN_MASK, /*!< SCK is stopped during command + sequence because Async TX FIFO empty. */ + kFLEXSPI_SckStoppedBecauseRxFullFlag = + FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK, /*!< SCK is stopped during command + sequence because Async RX FIFO full. */ +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) + kFLEXSPI_DataLearningFailedFlag = FLEXSPI_INTEN_DATALEARNFAILEN_MASK, /*!< Data learning failed. */ +#endif + kFLEXSPI_IpTxFifoWatermarkEmpltyFlag = FLEXSPI_INTEN_IPTXWEEN_MASK, /*!< IP TX FIFO WaterMark empty. */ + kFLEXSPI_IpRxFifoWatermarkAvailableFlag = FLEXSPI_INTEN_IPRXWAEN_MASK, /*!< IP RX FIFO WaterMark available. */ + kFLEXSPI_AhbCommandSequenceErrorFlag = + FLEXSPI_INTEN_AHBCMDERREN_MASK, /*!< AHB triggered Command Sequences Error. */ + kFLEXSPI_IpCommandSequenceErrorFlag = FLEXSPI_INTEN_IPCMDERREN_MASK, /*!< IP triggered Command Sequences Error. */ + kFLEXSPI_AhbCommandGrantTimeoutFlag = + FLEXSPI_INTEN_AHBCMDGEEN_MASK, /*!< AHB triggered Command Sequences Grant Timeout. */ + kFLEXSPI_IpCommandGrantTimeoutFlag = + FLEXSPI_INTEN_IPCMDGEEN_MASK, /*!< IP triggered Command Sequences Grant Timeout. */ + kFLEXSPI_IpCommandExcutionDoneFlag = + FLEXSPI_INTEN_IPCMDDONEEN_MASK, /*!< IP triggered Command Sequences Execution finished. */ + kFLEXSPI_AllInterruptFlags = 0xFFFU, /*!< All flags. */ +} flexspi_flags_t; + +/*! @brief FLEXSPI sample clock source selection for Flash Reading.*/ +typedef enum _flexspi_read_sample_clock +{ + kFLEXSPI_ReadSampleClkLoopbackInternally = 0x0U, /*!< Dummy Read strobe generated by FlexSPI Controller + and loopback internally. */ + kFLEXSPI_ReadSampleClkLoopbackFromDqsPad = 0x1U, /*!< Dummy Read strobe generated by FlexSPI Controller + and loopback from DQS pad. */ + kFLEXSPI_ReadSampleClkLoopbackFromSckPad = 0x2U, /*!< SCK output clock and loopback from SCK pad. */ + kFLEXSPI_ReadSampleClkExternalInputFromDqsPad = 0x3U, /*!< Flash provided Read strobe and input from DQS pad. */ +} flexspi_read_sample_clock_t; + +/*! @brief FLEXSPI interval unit for flash device select.*/ +typedef enum _flexspi_cs_interval_cycle_unit +{ + kFLEXSPI_CsIntervalUnit1SckCycle = 0x0U, /*!< Chip selection interval: CSINTERVAL * 1 serial clock cycle. */ + kFLEXSPI_CsIntervalUnit256SckCycle = 0x1U, /*!< Chip selection interval: CSINTERVAL * 256 serial clock cycle. */ +} flexspi_cs_interval_cycle_unit_t; + +/*! @brief FLEXSPI AHB wait interval unit for writting.*/ +typedef enum _flexspi_ahb_write_wait_unit +{ + kFLEXSPI_AhbWriteWaitUnit2AhbCycle = 0x0U, /*!< AWRWAIT unit is 2 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit8AhbCycle = 0x1U, /*!< AWRWAIT unit is 8 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit32AhbCycle = 0x2U, /*!< AWRWAIT unit is 32 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit128AhbCycle = 0x3U, /*!< AWRWAIT unit is 128 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit512AhbCycle = 0x4U, /*!< AWRWAIT unit is 512 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit2048AhbCycle = 0x5U, /*!< AWRWAIT unit is 2048 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit8192AhbCycle = 0x6U, /*!< AWRWAIT unit is 8192 ahb clock cycle. */ + kFLEXSPI_AhbWriteWaitUnit32768AhbCycle = 0x7U, /*!< AWRWAIT unit is 32768 ahb clock cycle. */ +} flexspi_ahb_write_wait_unit_t; + +/*! @brief Error Code when IP command Error detected.*/ +typedef enum _flexspi_ip_error_code +{ + kFLEXSPI_IpCmdErrorNoError = 0x0U, /*!< No error. */ + kFLEXSPI_IpCmdErrorJumpOnCsInIpCmd = 0x2U, /*!< IP command with JMP_ON_CS instruction used. */ + kFLEXSPI_IpCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */ + kFLEXSPI_IpCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR + used in DDR sequence. */ + kFLEXSPI_IpCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR + used in SDR sequence. */ + kFLEXSPI_IpCmdErrorInvalidAddress = 0x6U, /*!< Flash access start address exceed the whole + flash address range (A1/A2/B1/B2). */ + kFLEXSPI_IpCmdErrorSequenceExecutionTimeout = 0xEU, /*!< Sequence execution timeout. */ + kFLEXSPI_IpCmdErrorFlashBoundaryAcrosss = 0xFU, /*!< Flash boundary crossed. */ +} flexspi_ip_error_code_t; + +/*! @brief Error Code when AHB command Error detected.*/ +typedef enum _flexspi_ahb_error_code +{ + kFLEXSPI_AhbCmdErrorNoError = 0x0U, /*!< No error. */ + kFLEXSPI_AhbCmdErrorJumpOnCsInWriteCmd = 0x2U, /*!< AHB Write command with JMP_ON_CS instruction + used in the sequence. */ + kFLEXSPI_AhbCmdErrorUnknownOpCode = 0x3U, /*!< Unknown instruction opcode in the sequence. */ + kFLEXSPI_AhbCmdErrorSdrDummyInDdrSequence = 0x4U, /*!< Instruction DUMMY_SDR/DUMMY_RWDS_SDR used + in DDR sequence. */ + kFLEXSPI_AhbCmdErrorDdrDummyInSdrSequence = 0x5U, /*!< Instruction DUMMY_DDR/DUMMY_RWDS_DDR + used in SDR sequence. */ + kFLEXSPI_AhbCmdSequenceExecutionTimeout = 0x6U, /*!< Sequence execution timeout. */ +} flexspi_ahb_error_code_t; + +/*! @brief FLEXSPI operation port select.*/ +typedef enum _flexspi_port +{ + kFLEXSPI_PortA1 = 0x0U, /*!< Access flash on A1 port. */ + kFLEXSPI_PortA2, /*!< Access flash on A2 port. */ + kFLEXSPI_PortB1, /*!< Access flash on B1 port. */ + kFLEXSPI_PortB2, /*!< Access flash on B2 port. */ + kFLEXSPI_PortCount +} flexspi_port_t; + +/*! @brief Trigger source of current command sequence granted by arbitrator.*/ +typedef enum _flexspi_arb_command_source +{ + kFLEXSPI_AhbReadCommand = 0x0U, + kFLEXSPI_AhbWriteCommand = 0x1U, + kFLEXSPI_IpCommand = 0x2U, + kFLEXSPI_SuspendedCommand = 0x3U, +} flexspi_arb_command_source_t; + +typedef enum _flexspi_command_type +{ + kFLEXSPI_Command, /*!< FlexSPI operation: Only command, both TX and Rx buffer are ignored. */ + kFLEXSPI_Config, /*!< FlexSPI operation: Configure device mode, the TX fifo size is fixed in LUT. */ + kFLEXSPI_Read, /* /!< FlexSPI operation: Read, only Rx Buffer is effective. */ + kFLEXSPI_Write, /* /!< FlexSPI operation: Read, only Tx Buffer is effective. */ +} flexspi_command_type_t; + +typedef struct _flexspi_ahbBuffer_config +{ + uint8_t priority; /*!< This priority for AHB Master Read which this AHB RX Buffer is assigned. */ + uint8_t masterIndex; /*!< AHB Master ID the AHB RX Buffer is assigned. */ + uint16_t bufferSize; /*!< AHB buffer size in byte. */ + bool enablePrefetch; /*!< AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master, allows + prefetch disable/enable seperately for each master. */ +} flexspi_ahbBuffer_config_t; + +/*! @brief FLEXSPI configuration structure. */ +typedef struct _flexspi_config +{ + flexspi_read_sample_clock_t rxSampleClock; /*!< Sample Clock source selection for Flash Reading. */ + bool enableSckFreeRunning; /*!< Enable/disable SCK output free-running. */ + bool enableCombination; /*!< Enable/disable combining PORT A and B Data Pins + (SIOA[3:0] and SIOB[3:0]) to support Flash Octal mode. */ + bool enableDoze; /*!< Enable/disable doze mode support. */ + bool enableHalfSpeedAccess; /*!< Enable/disable divide by 2 of the clock for half + speed commands. */ + bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock + output, when enable, Port B flash access is not available. */ + bool enableSameConfigForAll; /*!< Enable/disable same configuration for all connected devices + when enabled, same configuration in FLASHA1CRx is applied to all. */ + uint16_t seqTimeoutCycle; /*!< Timeout wait cycle for command sequence execution, + timeout after ahbGrantTimeoutCyle*1024 serial root clock cycles. */ + uint8_t ipGrantTimeoutCycle; /*!< Timeout wait cycle for IP command grant, timeout after + ipGrantTimeoutCycle*1024 AHB clock cycles. */ + uint8_t txWatermark; /*!< FLEXSPI IP transmit watermark value. */ + uint8_t rxWatermark; /*!< FLEXSPI receive watermark value. */ + struct + { + bool enableAHBWriteIpTxFifo; /*!< Enable AHB bus write access to IP TX FIFO. */ + bool enableAHBWriteIpRxFifo; /*!< Enable AHB bus write access to IP RX FIFO. */ + uint8_t ahbGrantTimeoutCycle; /*!< Timeout wait cycle for AHB command grant, + timeout after ahbGrantTimeoutCyle*1024 AHB clock cycles. */ + uint16_t ahbBusTimeoutCycle; /*!< Timeout wait cycle for AHB read/write access, + timeout after ahbBusTimeoutCycle*1024 AHB clock cycles. */ + uint8_t resumeWaitCycle; /*!< Wait cycle for idle state before suspended command sequence + resume, timeout after ahbBusTimeoutCycle AHB clock cycles. */ + flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer size. */ + bool enableClearAHBBufferOpt; /*!< Enable/disable automatically clean AHB RX Buffer and TX Buffer + when FLEXSPI returns STOP mode ACK. */ + bool enableReadAddressOpt; /*!< Enable/disable remove AHB read burst start address alignment limitation. + when eanble, there is no AHB read burst start address alignment limitation. */ + bool enableAHBPrefetch; /*!< Enable/disable AHB read prefetch feature, when enabled, FLEXSPI + will fetch more data than current AHB burst. */ + bool enableAHBBufferable; /*!< Enable/disable AHB bufferable write access support, when enabled, + FLEXSPI return before waiting for command excution finished. */ + bool enableAHBCachable; /*!< Enable AHB bus cachable read access support. */ + } ahbConfig; +} flexspi_config_t; + +/*! @brief External device configuration items. */ +typedef struct _flexspi_device_config +{ + uint32_t flexspiRootClk; /*!< FLEXSPI serial root clock. */ + bool isSck2Enabled; /*!< FLEXSPI use SCK2. */ + uint32_t flashSize; /*!< Flash size in KByte. */ + flexspi_cs_interval_cycle_unit_t CSIntervalUnit; /*!< CS interval unit, 1 or 256 cycle. */ + uint16_t CSInterval; /*!< CS line assert interval, mutiply CS interval unit to + get the CS line assert interval cycles. */ + uint8_t CSHoldTime; /*!< CS line hold time. */ + uint8_t CSSetupTime; /*!< CS line setup time. */ + uint8_t dataValidTime; /*!< Data valid time for external device. */ + uint8_t columnspace; /*!< Column space size. */ + bool enableWordAddress; /*!< If enable word address.*/ + uint8_t AWRSeqIndex; /*!< Sequence ID for AHB write command. */ + uint8_t AWRSeqNumber; /*!< Sequence number for AHB write command. */ + uint8_t ARDSeqIndex; /*!< Sequence ID for AHB read command. */ + uint8_t ARDSeqNumber; /*!< Sequence number for AHB read command. */ + flexspi_ahb_write_wait_unit_t AHBWriteWaitUnit; /*!< AHB write wait unit. */ + uint16_t AHBWriteWaitInterval; /*!< AHB write wait interval, mutiply AHB write interval + unit to get the AHB write wait cycles. */ + bool enableWriteMask; /*!< Enable/Disable FLEXSPI drive DQS pin as write mask + when writing to external device. */ +} flexspi_device_config_t; + +/*! @brief Transfer structure for FLEXSPI. */ +typedef struct _flexspi_transfer +{ + uint32_t deviceAddress; /*!< Operation device address. */ + flexspi_port_t port; /*!< Operation port. */ + flexspi_command_type_t cmdType; /*!< Execution command type. */ + uint8_t seqIndex; /*!< Sequence ID for command. */ + uint8_t SeqNumber; /*!< Sequence number for command. */ + uint32_t *data; /*!< Data buffer. */ + size_t dataSize; /*!< Data size in bytes. */ +} flexspi_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _flexspi_handle flexspi_handle_t; + +/*! @brief FLEXSPI transfer callback function. */ +typedef void (*flexspi_transfer_callback_t)(FLEXSPI_Type *base, + flexspi_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Transfer handle structure for FLEXSPI. */ +struct _flexspi_handle +{ + uint32_t state; /*!< Internal state for FLEXSPI transfer */ + uint32_t *data; /*!< Data buffer. */ + size_t dataSize; /*!< Remaining Data size in bytes. */ + size_t transferTotalSize; /*!< Total Data size in bytes. */ + flexspi_transfer_callback_t completionCallback; /*!< Callback for users while transfer finish or error occurred */ + void *userData; /*!< FLEXSPI callback function parameter.*/ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ + +/*! + * @name Initialization and deinitialization + * @{ + */ +/*! + * @brief Initializes the FLEXSPI module and internal state. + * + * This function enables the clock for FLEXSPI and also configures the FLEXSPI with the + * input configure parameters. Users should call this function before any FLEXSPI operations. + * + * @param base FLEXSPI peripheral base address. + * @param config FLEXSPI configure structure. + */ +void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config); + +/*! + * @brief Gets default settings for FLEXSPI. + * + * @param config FLEXSPI configuration structure. + */ +void FLEXSPI_GetDefaultConfig(flexspi_config_t *config); + +/*! + * @brief Deinitializes the FLEXSPI module. + * + * Clears the FLEXSPI state and FLEXSPI module registers. + * @param base FLEXSPI peripheral base address. + */ +void FLEXSPI_Deinit(FLEXSPI_Type *base); + +/*! + * @brief Configures the connected device parameter. + * + * This function configures the connected device relevant parameters, such as the size, command, and so on. + * The flash configuration value cannot have a default value. The user needs to configure it according to the + * connected device. + * + * @param base FLEXSPI peripheral base address. + * @param config Flash configuration parameters. + * @param port FLEXSPI Operation port. + */ +void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port); + +/*! + * @brief Software reset for the FLEXSPI logic. + * + * This function sets the software reset flags for both AHB and buffer domain and + * resets both AHB buffer and also IP FIFOs. + * + * @param base FLEXSPI peripheral base address. + */ +static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base) +{ + base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; + while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) + { + } +} + +/*! + * @brief Enables or disables the FLEXSPI module. + * + * @param base FLEXSPI peripheral base address. + * @param enable True means enable FLEXSPI, false means disable. + */ +static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable) +{ + if (enable) + { + base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; + } + else + { + base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; + } +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ +/*! + * @brief Enables the FLEXSPI interrupts. + * + * @param base FLEXSPI peripheral base address. + * @param mask FLEXSPI interrupt source. + */ +static inline void FLEXSPI_EnableInterrupts(FLEXSPI_Type *base, uint32_t mask) +{ + base->INTEN |= mask; +} + +/*! + * @brief Disable the FLEXSPI interrupts. + * + * @param base FLEXSPI peripheral base address. + * @param mask FLEXSPI interrupt source. + */ +static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask) +{ + base->INTEN &= ~mask; +} + +/* @} */ + +/*! @name DMA control */ +/*@{*/ + +/*! + * @brief Enables or disables FLEXSPI IP Tx FIFO DMA requests. + * + * @param base FLEXSPI peripheral base address. + * @param enable Enable flag for transmit DMA request. Pass true for enable, false for disable. + */ +static inline void FLEXSPI_EnableTxDMA(FLEXSPI_Type *base, bool enable) +{ + if (enable) + { + base->IPTXFCR |= FLEXSPI_IPTXFCR_TXDMAEN_MASK; + } + else + { + base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXDMAEN_MASK; + } +} + +/*! + * @brief Enables or disables FLEXSPI IP Rx FIFO DMA requests. + * + * @param base FLEXSPI peripheral base address. + * @param enable Enable flag for receive DMA request. Pass true for enable, false for disable. + */ +static inline void FLEXSPI_EnableRxDMA(FLEXSPI_Type *base, bool enable) +{ + if (enable) + { + base->IPRXFCR |= FLEXSPI_IPRXFCR_RXDMAEN_MASK; + } + else + { + base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXDMAEN_MASK; + } +} + +/*! + * @brief Gets FLEXSPI IP tx fifo address for DMA transfer. + * + * @param base FLEXSPI peripheral base address. + * @retval The tx fifo address. + */ +static inline uint32_t FLEXSPI_GetTxFifoAddress(FLEXSPI_Type *base) +{ + return (uint32_t)&base->TFDR[0]; +} + +/*! + * @brief Gets FLEXSPI IP rx fifo address for DMA transfer. + * + * @param base FLEXSPI peripheral base address. + * @retval The rx fifo address. + */ +static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base) +{ + return (uint32_t)&base->RFDR[0]; +} + +/*@}*/ + +/*! @name FIFO control */ +/*@{*/ + +/*! @brief Clears the FLEXSPI IP FIFO logic. + * + * @param base FLEXSPI peripheral base address. + * @param txFifo Pass true to reset TX FIFO. + * @param rxFifo Pass true to reset RX FIFO. + */ +static inline void FLEXSPI_ResetFifos(FLEXSPI_Type *base, bool txFifo, bool rxFifo) +{ + if (txFifo) + { + base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK; + } + if (rxFifo) + { + base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK; + } +} + +/*! + * @brief Gets the valid data entries in the FLEXSPI FIFOs. + * + * @param base FLEXSPI peripheral base address. + * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned. + * Pass NULL if this value is not required. + * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned. + * Pass NULL if this value is not required. + */ +static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, size_t *rxCount) +{ + if (txCount) + { + *txCount = (((base->IPTXFSTS) & FLEXSPI_IPTXFSTS_FILL_MASK) >> FLEXSPI_IPTXFSTS_FILL_SHIFT) * 8U; + } + if (rxCount) + { + *rxCount = (((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U; + } +} + +/*@}*/ + +/*! + * @name Status + * @{ + */ +/*! + * @brief Get the FLEXSPI interrupt status flags. + * + * @param base FLEXSPI peripheral base address. + * @retval interrupt status flag, use status flag to AND #flexspi_flags_t could get the related status. + */ +static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base) +{ + return base->INTR; +} + +/*! + * @brief Get the FLEXSPI interrupt status flags. + * + * @param base FLEXSPI peripheral base address. + * @param interrupt status flag. + */ +static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask) +{ + base->INTR |= mask; +} + +#if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) +/*! @brief Gets the sampling clock phase selection after Data Learning. + * + * @param base FLEXSPI peripheral base address. + * @param portAPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTA. + * @param portBPhase Pointer to a uint8_t type variable to receive the selected clock phase on PORTB. + */ +static inline void FLEXSPI_GetDataLearningPhase(FLEXSPI_Type *base, uint8_t *portAPhase, uint8_t *portBPhase) +{ + if (portAPhase) + { + *portAPhase = (base->STS0 & FLEXSPI_STS0_DATALEARNPHASEA_MASK) >> FLEXSPI_STS0_DATALEARNPHASEA_SHIFT; + } + + if (portBPhase) + { + *portBPhase = (base->STS0 & FLEXSPI_STS0_DATALEARNPHASEB_MASK) >> FLEXSPI_STS0_DATALEARNPHASEB_SHIFT; + } +} +#endif + +/*! @brief Gets the trigger source of current command sequence granted by arbitrator. + * + * @param base FLEXSPI peripheral base address. + * @retval trigger source of current command sequence. + */ +static inline flexspi_arb_command_source_t FLEXSPI_GetArbitratorCommandSource(FLEXSPI_Type *base) +{ + return (flexspi_arb_command_source_t)((base->STS0 & FLEXSPI_STS0_ARBCMDSRC_MASK) >> FLEXSPI_STS0_ARBCMDSRC_SHIFT); +} + +/*! @brief Gets the error code when IP command error detected. + * + * @param base FLEXSPI peripheral base address. + * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected. + * @retval error code when IP command error detected. + */ +static inline flexspi_ip_error_code_t FLEXSPI_GetIPCommandErrorCode(FLEXSPI_Type *base, uint8_t *index) +{ + *index = (base->STS1 & FLEXSPI_STS1_IPCMDERRID_MASK) >> FLEXSPI_STS1_IPCMDERRID_SHIFT; + return (flexspi_ip_error_code_t)((base->STS1 & FLEXSPI_STS1_IPCMDERRCODE_MASK) >> FLEXSPI_STS1_IPCMDERRCODE_SHIFT); +} + +/*! @brief Gets the error code when AHB command error detected. + * + * @param base FLEXSPI peripheral base address. + * @param index Pointer to a uint8_t type variable to receive the sequence index when error detected. + * @retval error code when AHB command error detected. + */ +static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Type *base, uint8_t *index) +{ + *index = (base->STS1 & FLEXSPI_STS1_AHBCMDERRID_MASK) >> FLEXSPI_STS1_AHBCMDERRID_SHIFT; + return (flexspi_ahb_error_code_t)((base->STS1 & FLEXSPI_STS1_AHBCMDERRCODE_MASK) >> + FLEXSPI_STS1_AHBCMDERRCODE_SHIFT); +} + +/*! @brief Returns whether the bus is idle. + * + * @param base FLEXSPI peripheral base address. + * @retval true Bus is idle. + * @retval false Bus is busy. + */ +static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base) +{ + return (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK); +} +/*@}*/ + +/*! + * @name Bus Operations + * @{ + */ + +/*! @brief Update read sample clock source + * + * @param base FLEXSPI peripheral base address. + * @param clockSource clockSource of type #flexspi_read_sample_clock_t + */ +void FLEXSPI_UpdateRxSampleClock(FLEXSPI_Type *base, flexspi_read_sample_clock_t clockSource); + +/*! @brief Enables/disables the FLEXSPI IP command parallel mode. + * + * @param base FLEXSPI peripheral base address. + * @param enable True means enable parallel mode, false means disable parallel mode. + */ +static inline void FLEXSPI_EnableIPParallelMode(FLEXSPI_Type *base, bool enable) +{ + if (enable) + { + base->IPCR1 |= FLEXSPI_IPCR1_IPAREN_MASK; + } + else + { + base->IPCR1 &= ~FLEXSPI_IPCR1_IPAREN_MASK; + } +} + +/*! @brief Enables/disables the FLEXSPI AHB command parallel mode. + * + * @param base FLEXSPI peripheral base address. + * @param enable True means enable parallel mode, false means disable parallel mode. + */ +static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable) +{ + if (enable) + { + base->AHBCR |= FLEXSPI_AHBCR_APAREN_MASK; + } + else + { + base->AHBCR &= ~FLEXSPI_AHBCR_APAREN_MASK; + } +} + +/*! @brief Updates the LUT table. + * + * @param base FLEXSPI peripheral base address. + * @param index From which index start to update. It could be any index of the LUT table, which + * also allows user to update command content inside a command. Each command consists of up to + * 8 instructions and occupy 4*32-bit memory. + * @param cmd Command sequence array. + * @param count Number of sequences. + */ +void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count); + +/*! + * @brief Writes data into FIFO. + * + * @param base FLEXSPI peripheral base address + * @param data The data bytes to send + * @param fifoIndex Destination fifo index. + */ +static inline void FLEXSPI_WriteData(FLEXSPI_Type *base, uint32_t data, uint8_t fifoIndex) +{ + base->TFDR[fifoIndex] = data; +} + +/*! + * @brief Receives data from data FIFO. + * + * @param base FLEXSPI peripheral base address + * @param fifoIndex Source fifo index. + * @return The data in the FIFO. + */ +static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex) +{ + return base->RFDR[fifoIndex]; +} + +/*! + * @brief Sends a buffer of data bytes using blocking method. + * @note This function blocks via polling until all bytes have been sent. + * @param base FLEXSPI peripheral base address + * @param buffer The data bytes to send + * @param size The number of data bytes to send + * @retval kStatus_Success write success without error + * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout + * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected + * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected + */ +status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size); + +/*! + * @brief Receives a buffer of data bytes using a blocking method. + * @note This function blocks via polling until all bytes have been sent. + * @param base FLEXSPI peripheral base address + * @param buffer The data bytes to send + * @param size The number of data bytes to receive + * @retval kStatus_Success read success without error + * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout + * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected + * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected + */ +status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size); + +/*! + * @brief Execute command to transfer a buffer data bytes using a blocking method. + * @param base FLEXSPI peripheral base address + * @param xfer pointer to the transfer structure. + * @retval kStatus_Success command transfer success without error + * @retval kStatus_FLEXSPI_SequenceExecutionTimeout sequence execution timeout + * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected + * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected + */ +status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer); +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the FLEXSPI handle which is used in transactional functions. + * + * @param base FLEXSPI peripheral base address. + * @param handle pointer to flexspi_handle_t structure to store the transfer state. + * @param callback pointer to user callback function. + * @param userData user parameter passed to the callback function. + */ +void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base, + flexspi_handle_t *handle, + flexspi_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a interrupt non-blocking transfer on the FLEXSPI bus. + * + * @note Calling the API returns immediately after transfer initiates. The user needs + * to call FLEXSPI_GetTransferCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_FLEXSPI_Busy, the transfer + * is finished. For FLEXSPI_Read, the dataSize should be multiple of rx watermark levle, or + * FLEXSPI could not read data properly. + * + * @param base FLEXSPI peripheral base address. + * @param handle pointer to flexspi_handle_t structure which stores the transfer state. + * @param xfer pointer to flexspi_transfer_t structure. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_FLEXSPI_Busy Previous transmission still not finished. + */ +status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handle, flexspi_transfer_t *xfer); + +/*! + * @brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * @param base FLEXSPI peripheral base address. + * @param handle pointer to flexspi_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXSPI_TransferGetCount(FLEXSPI_Type *base, flexspi_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an interrupt non-blocking transfer early. + * + * @note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base FLEXSPI peripheral base address. + * @param handle pointer to flexspi_handle_t structure which stores the transfer state + */ +void FLEXSPI_TransferAbort(FLEXSPI_Type *base, flexspi_handle_t *handle); + +/*! + * @brief Master interrupt handler. + * + * @param base FLEXSPI peripheral base address. + * @param handle pointer to flexspi_handle_t structure. + */ +void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle); +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ +/*@}*/ + +#endif /* __FSL_FLEXSPI_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_gpc.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_gpc.c new file mode 100644 index 0000000000..a91e16377b --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_gpc.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gpc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.gpc_1" +#endif + +/*! + * brief Enable the IRQ. + * + * param base GPC peripheral base address. + * param irqId ID number of IRQ to be enabled, available range is 32-159. + */ +void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId) +{ + uint32_t irqRegNum = irqId / 32U; + uint32_t irqRegShiftNum = irqId % 32U; + + assert(irqRegNum > 0U); + assert(irqRegNum <= GPC_IMR_COUNT); + +#if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31) + if (irqRegNum == GPC_IMR_COUNT) + { + base->IMR5 &= ~(1U << irqRegShiftNum); + } + else + { + base->IMR[irqRegNum] &= ~(1U << irqRegShiftNum); + } +#else + base->IMR[irqRegNum - 1U] &= ~(1U << irqRegShiftNum); +#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */ +} + +/*! + * brief Disable the IRQ. + * + * param base GPC peripheral base address. + * param irqId ID number of IRQ to be disabled, available range is 32-159. + */ +void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId) +{ + uint32_t irqRegNum = irqId / 32U; + uint32_t irqRegShiftNum = irqId % 32U; + + assert(irqRegNum > 0U); + assert(irqRegNum <= GPC_IMR_COUNT); + +#if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31) + if (irqRegNum == GPC_IMR_COUNT) + { + base->IMR5 |= (1U << irqRegShiftNum); + } + else + { + base->IMR[irqRegNum] |= (1U << irqRegShiftNum); + } +#else + base->IMR[irqRegNum - 1U] |= (1U << irqRegShiftNum); +#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */ +} + +/*! + * brief Get the IRQ/Event flag. + * + * param base GPC peripheral base address. + * param irqId ID number of IRQ to be enabled, available range is 32-159. + * return Indicated IRQ/Event is asserted or not. + */ +bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId) +{ + uint32_t irqRegNum = irqId / 32U; + uint32_t irqRegShiftNum = irqId % 32U; + uint32_t ret; + + assert(irqRegNum > 0U); + assert(irqRegNum <= GPC_IMR_COUNT); + +#if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31) + if (irqRegNum == GPC_IMR_COUNT) + { + ret = base->ISR5 & (1U << irqRegShiftNum); + } + else + { + ret = base->ISR[irqRegNum] & (1U << irqRegShiftNum); + } +#else + ret = base->ISR[irqRegNum - 1U] & (1U << irqRegShiftNum); +#endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */ + + return (1U << irqRegShiftNum) == ret; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_gpc.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_gpc.h new file mode 100644 index 0000000000..09dbaa15de --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_gpc.h @@ -0,0 +1,231 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_GPC_H_ +#define _FSL_GPC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief GPC driver version 2.1.0. */ +#define FSL_GPC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if (defined(FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM) && FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM) +/*! + * @brief Allow all the IRQ/Events within the charge of GPC. + * + * @param base GPC peripheral base address. + */ +static inline void GPC_AllowIRQs(GPC_Type *base) +{ + base->CNTR &= ~GPC_CNTR_GPCIRQM_MASK; /* Events would not be masked. */ +} + +/*! + * @brief Disallow all the IRQ/Events within the charge of GPC. + * + * @param base GPC peripheral base address. + */ +static inline void GPC_DisallowIRQs(GPC_Type *base) +{ + base->CNTR |= GPC_CNTR_GPCIRQM_MASK; /* Mask all the events. */ +} +#endif /* FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM */ + +/*! + * @brief Enable the IRQ. + * + * @param base GPC peripheral base address. + * @param irqId ID number of IRQ to be enabled, available range is 32-159. + */ +void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId); + +/*! + * @brief Disable the IRQ. + * + * @param base GPC peripheral base address. + * @param irqId ID number of IRQ to be disabled, available range is 32-159. + */ +void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId); + +/*! + * @brief Get the IRQ/Event flag. + * + * @param base GPC peripheral base address. + * @param irqId ID number of IRQ to be enabled, available range is 32-159. + * @return Indicated IRQ/Event is asserted or not. + */ +bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId); + +#if (defined(FSL_FEATURE_GPC_HAS_CNTR_L2PGE) && FSL_FEATURE_GPC_HAS_CNTR_L2PGE) +/*! + * @brief L2 Cache Power Gate Enable + * + * This function configures the L2 cache if it will keep power when in low power mode. + * When the L2 cache power is OFF, L2 cache will be power down once when CPU core is power down + * and will be hardware invalidated automatically when CPU core is re-power up. + * When the L2 cache power is ON, L2 cache will keep power on even if CPU core is power down and + * will not be hardware invalidated. + * When CPU core is re-power up, the default setting is OFF. + * + * @param base GPC peripheral base address. + * @param enable Enable the request or not. + */ +static inline void GPC_RequestL2CachePowerDown(GPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTR |= GPC_CNTR_L2_PGE_MASK; /* OFF. */ + } + else + { + base->CNTR &= ~GPC_CNTR_L2_PGE_MASK; /* ON. */ + } +} +#endif /* FSL_FEATURE_GPC_HAS_CNTR_L2PGE */ + +#if (defined(FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE) && FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE) +/*! + * @brief FLEXRAM PDRAM0 Power Gate Enable + * + * This function configures the FLEXRAM PDRAM0 if it will keep power when cpu core is power down. + * When the PDRAM0 Power is 1, PDRAM0 will be power down once when CPU core is power down. + * When the PDRAM0 Power is 0, PDRAM0 will keep power on even if CPU core is power down. + * When CPU core is re-power up, the default setting is 1. + * + * @param base GPC peripheral base address. + * @param enable Enable the request or not. + */ +static inline void GPC_RequestPdram0PowerDown(GPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTR |= GPC_CNTR_PDRAM0_PGE_MASK; /* OFF. */ + } + else + { + base->CNTR &= ~GPC_CNTR_PDRAM0_PGE_MASK; /* ON. */ + } +} +#endif /* FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE */ + +#if (defined(FSL_FEATURE_GPC_HAS_CNTR_VADC) && FSL_FEATURE_GPC_HAS_CNTR_VADC) +/*! + * @brief VADC power down. + * + * This function requests the VADC power down. + * + * @param base GPC peripheral base address. + * @param enable Enable the request or not. + */ +static inline void GPC_RequestVADCPowerDown(GPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTR &= ~GPC_CNTR_VADC_EXT_PWD_N_MASK; /* VADC power down. */ + } + else + { + base->CNTR |= GPC_CNTR_VADC_EXT_PWD_N_MASK; /* VADC not power down. */ + } +} + +/*! + * @brief Checks if the VADC is power off. + * + * @param base GPC peripheral base address. + * @return Whether the VADC is power off or not. + */ +static inline bool GPC_GetVADCPowerDownFlag(GPC_Type *base) +{ + return (GPC_CNTR_VADC_ANALOG_OFF_MASK == (GPC_CNTR_VADC_ANALOG_OFF_MASK & base->CNTR)); +} +#endif /* FSL_FEATURE_GPC_HAS_CNTR_VADC */ + +#if (defined(FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR) && FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR) +/*! + * @brief Checks if the DVFS0 is requesting for frequency/voltage update. + * + * @param base GPC peripheral base address. + * @return Whether the DVFS0 is requesting for frequency/voltage update. + */ +static inline bool GPC_HasDVFS0ChangeRequest(GPC_Type *base) +{ + return (GPC_CNTR_DVFS0CR_MASK == (GPC_CNTR_DVFS0CR_MASK & base->CNTR)); +} +#endif /* FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR */ + +#if (defined(FSL_FEATURE_GPC_HAS_CNTR_DISPLAY) && FSL_FEATURE_GPC_HAS_CNTR_DISPLAY) +/*! + * @brief Requests the display power switch sequence. + * + * @param base GPC peripheral base address. + * @param enable Enable the power on sequence, or the power down sequence. + */ +static inline void GPC_RequestDisplayPowerOn(GPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTR |= GPC_CNTR_DISPLAY_PUP_REQ_MASK; /* Power on sequence. */ + } + else + { + base->CNTR |= GPC_CNTR_DISPLAY_PDN_REQ_MASK; /* Power down sequence. */ + } +} +#endif /* FSL_FEATURE_GPC_HAS_CNTR_DISPLAY */ + +/*! + * @brief Requests the MEGA power switch sequence. + * + * @param base GPC peripheral base address. + * @param enable Enable the power on sequence, or the power down sequence. + */ +static inline void GPC_RequestMEGAPowerOn(GPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTR |= GPC_CNTR_MEGA_PUP_REQ_MASK; /* Power on sequence. */ + } + else + { + base->CNTR |= GPC_CNTR_MEGA_PDN_REQ_MASK; /* Power down sequence. */ + } +} + +/*! + * @} + */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_GPC_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_gpio.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_gpio.c new file mode 100644 index 0000000000..98434f323d --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_gpio.c @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gpio.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.igpio" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Array of GPIO peripheral base address. */ +static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of GPIO clock name. */ +static const clock_ip_name_t s_gpioClock[] = GPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Gets the GPIO instance according to the GPIO base + * + * @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * @retval GPIO instance + */ +static uint32_t GPIO_GetInstance(GPIO_Type *base); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t GPIO_GetInstance(GPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++) + { + if (s_gpioBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_gpioBases)); + + return instance; +} + +/*! + * brief Initializes the GPIO peripheral according to the specified + * parameters in the initConfig. + * + * param base GPIO base pointer. + * param pin Specifies the pin number + * param initConfig pointer to a ref gpio_pin_config_t structure that + * contains the configuration information. + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable GPIO clock. */ + uint32_t instance = GPIO_GetInstance(base); + + /* If The clock IP is valid, enable the clock gate. */ + if ((instance < ARRAY_SIZE(s_gpioClock)) && (kCLOCK_IpInvalid != s_gpioClock[instance])) + { + CLOCK_EnableClock(s_gpioClock[instance]); + } +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Register reset to default value */ + base->IMR &= ~(1U << pin); + + /* Configure GPIO pin direction */ + if (Config->direction == kGPIO_DigitalInput) + { + base->GDIR &= ~(1U << pin); + } + else + { + GPIO_PinWrite(base, pin, Config->outputLogic); + base->GDIR |= (1U << pin); + } + + /* Configure GPIO pin interrupt mode */ + GPIO_SetPinInterruptConfig(base, pin, Config->interruptMode); +} + +/*! + * brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * + * param base GPIO base pointer. + * param pin GPIO port pin number. + * param output GPIOpin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output) +{ + assert(pin < 32); + if (output == 0U) + { + base->DR &= ~(1U << pin); /* Set pin output to low level.*/ + } + else + { + base->DR |= (1U << pin); /* Set pin output to high level.*/ + } +} + +/*! + * brief Sets the current pin interrupt mode. + * + * param base GPIO base pointer. + * param pin GPIO port pin number. + * param pininterruptMode pointer to a ref gpio_interrupt_mode_t structure + * that contains the interrupt mode information. + */ +void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode) +{ + volatile uint32_t *icr; + uint32_t icrShift; + + icrShift = pin; + + /* Register reset to default value */ + base->EDGE_SEL &= ~(1U << pin); + + if (pin < 16) + { + icr = &(base->ICR1); + } + else + { + icr = &(base->ICR2); + icrShift -= 16; + } + switch (pinInterruptMode) + { + case (kGPIO_IntLowLevel): + *icr &= ~(3U << (2 * icrShift)); + break; + case (kGPIO_IntHighLevel): + *icr = (*icr & (~(3U << (2 * icrShift)))) | (1U << (2 * icrShift)); + break; + case (kGPIO_IntRisingEdge): + *icr = (*icr & (~(3U << (2 * icrShift)))) | (2U << (2 * icrShift)); + break; + case (kGPIO_IntFallingEdge): + *icr |= (3U << (2 * icrShift)); + break; + case (kGPIO_IntRisingOrFallingEdge): + base->EDGE_SEL |= (1U << pin); + break; + default: + break; + } +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_gpio.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_gpio.h new file mode 100644 index 0000000000..99b30f8936 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_gpio.h @@ -0,0 +1,342 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_GPIO_H_ +#define _FSL_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpio_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief GPIO driver version 2.0.2. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! @brief GPIO direction definition. */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input.*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output.*/ +} gpio_pin_direction_t; + +/*! @brief GPIO interrupt mode definition. */ +typedef enum _gpio_interrupt_mode +{ + kGPIO_NoIntmode = 0U, /*!< Set current pin general IO functionality.*/ + kGPIO_IntLowLevel = 1U, /*!< Set current pin interrupt is low-level sensitive.*/ + kGPIO_IntHighLevel = 2U, /*!< Set current pin interrupt is high-level sensitive.*/ + kGPIO_IntRisingEdge = 3U, /*!< Set current pin interrupt is rising-edge sensitive.*/ + kGPIO_IntFallingEdge = 4U, /*!< Set current pin interrupt is falling-edge sensitive.*/ + kGPIO_IntRisingOrFallingEdge = 5U, /*!< Enable the edge select bit to override the ICR register's configuration.*/ +} gpio_interrupt_mode_t; + +/*! @brief GPIO Init structure definition. */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t direction; /*!< Specifies the pin direction. */ + uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ + gpio_interrupt_mode_t + interruptMode; /*!< Specifies the pin interrupt mode, a value of @ref gpio_interrupt_mode_t. */ +} gpio_pin_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name GPIO Initialization and Configuration functions + * @{ + */ + +/*! + * @brief Initializes the GPIO peripheral according to the specified + * parameters in the initConfig. + * + * @param base GPIO base pointer. + * @param pin Specifies the pin number + * @param initConfig pointer to a @ref gpio_pin_config_t structure that + * contains the configuration information. + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config); +/*@}*/ + +/*! + * @name GPIO Reads and Write Functions + * @{ + */ + +/*! + * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param output GPIOpin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output); + +/*! + * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinWrite. + */ +static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) +{ + GPIO_PinWrite(base, pin, output); +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && (FSL_FEATURE_IGPIO_HAS_DR_SET == 1)) + base->DR_SET = mask; +#else + base->DR |= mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_SET */ +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortSet. + */ +static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortSet(base, mask); +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && (FSL_FEATURE_IGPIO_HAS_DR_CLEAR == 1)) + base->DR_CLEAR = mask; +#else + base->DR &= ~mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_CLEAR */ +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortClear. + */ +static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortClear(base, mask); +} + +/*! + * @brief Reverses the current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_TOGGLE) && (FSL_FEATURE_IGPIO_HAS_DR_TOGGLE == 1)) + base->DR_TOGGLE = mask; +#endif /* FSL_FEATURE_IGPIO_HAS_DR_TOGGLE */ +} + +/*! + * @brief Reads the current input value of the GPIO port. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @retval GPIO port input value. + */ +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin) +{ + assert(pin < 32); + + return (((base->DR) >> pin) & 0x1U); +} + +/*! + * @brief Reads the current input value of the GPIO port. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinRead. + */ +static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) +{ + return GPIO_PinRead(base, pin); +} +/*@}*/ + +/*! + * @name GPIO Reads Pad Status Functions + * @{ + */ + +/*! + * @brief Reads the current GPIO pin pad status. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @retval GPIO pin pad status value. + */ +static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin) +{ + assert(pin < 32); + + return (uint8_t)(((base->PSR) >> pin) & 0x1U); +} + +/*! + * @brief Reads the current GPIO pin pad status. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinReadPadStatus. + */ +static inline uint8_t GPIO_ReadPadStatus(GPIO_Type *base, uint32_t pin) +{ + return GPIO_PinReadPadStatus(base, pin); +} + +/*@}*/ + +/*! + * @name Interrupts and flags management functions + * @{ + */ + +/*! + * @brief Sets the current pin interrupt mode. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param pininterruptMode pointer to a @ref gpio_interrupt_mode_t structure + * that contains the interrupt mode information. + */ +void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode); + +/*! + * @brief Sets the current pin interrupt mode. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinSetInterruptConfig. + */ +static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode) +{ + GPIO_PinSetInterruptConfig(base, pin, pinInterruptMode); +} + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t mask) +{ + base->IMR |= mask; +} + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_EnableInterrupts(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortEnableInterrupts(base, mask); +} + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t mask) +{ + base->IMR &= ~mask; +} + +/*! + * @brief Disables the specific pin interrupt. + * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortDisableInterrupts. + */ +static inline void GPIO_DisableInterrupts(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortDisableInterrupts(base, mask); +} + +/*! + * @brief Reads individual pin interrupt status. + * + * @param base GPIO base pointer. + * @retval current pin interrupt status flag. + */ +static inline uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base) +{ + return base->ISR; +} + +/*! + * @brief Reads individual pin interrupt status. + * + * @param base GPIO base pointer. + * @retval current pin interrupt status flag. + */ +static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base) +{ + return GPIO_PortGetInterruptFlags(base); +} + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + base->ISR = mask; +} + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param mask GPIO pin number macro. + */ +static inline void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + GPIO_PortClearInterruptFlags(base, mask); +} +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_GPIO_H_*/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_gpt.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_gpt.c new file mode 100644 index 0000000000..697be010a7 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_gpt.c @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gpt.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.gpt" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to GPT bases for each instance. */ +static GPT_Type *const s_gptBases[] = GPT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to GPT clocks for each instance. */ +static const clock_ip_name_t s_gptClocks[] = GPT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t GPT_GetInstance(GPT_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0U; instance < ARRAY_SIZE(s_gptBases); instance++) + { + if (s_gptBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_gptBases)); + + return instance; +} + +/*! + * brief Initialize GPT to reset state and initialize running mode. + * + * param base GPT peripheral base address. + * param initConfig GPT mode setting configuration. + */ +void GPT_Init(GPT_Type *base, const gpt_config_t *initConfig) +{ + assert(initConfig); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the GPT clock*/ + CLOCK_EnableClock(s_gptClocks[GPT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + base->CR = 0U; + + GPT_SoftwareReset(base); + + base->CR = + (initConfig->enableFreeRun ? GPT_CR_FRR_MASK : 0U) | (initConfig->enableRunInWait ? GPT_CR_WAITEN_MASK : 0U) | + (initConfig->enableRunInStop ? GPT_CR_STOPEN_MASK : 0U) | + (initConfig->enableRunInDoze ? GPT_CR_DOZEEN_MASK : 0U) | + (initConfig->enableRunInDbg ? GPT_CR_DBGEN_MASK : 0U) | (initConfig->enableMode ? GPT_CR_ENMOD_MASK : 0U); + + GPT_SetClockSource(base, initConfig->clockSource); + GPT_SetClockDivider(base, initConfig->divider); +} + +/*! + * brief Disables the module and gates the GPT clock. + * + * param base GPT peripheral base address. + */ +void GPT_Deinit(GPT_Type *base) +{ + /* Disable GPT timers */ + base->CR = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the GPT clock*/ + CLOCK_DisableClock(s_gptClocks[GPT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Fills in the GPT configuration structure with default settings. + * + * The default values are: + * code + * config->clockSource = kGPT_ClockSource_Periph; + * config->divider = 1U; + * config->enableRunInStop = true; + * config->enableRunInWait = true; + * config->enableRunInDoze = false; + * config->enableRunInDbg = false; + * config->enableFreeRun = true; + * config->enableMode = true; + * endcode + * param config Pointer to the user configuration structure. + */ +void GPT_GetDefaultConfig(gpt_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->clockSource = kGPT_ClockSource_Periph; + config->divider = 1U; + config->enableRunInStop = true; + config->enableRunInWait = true; + config->enableRunInDoze = false; + config->enableRunInDbg = false; + config->enableFreeRun = false; + config->enableMode = true; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_gpt.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_gpt.h new file mode 100644 index 0000000000..3666505905 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_gpt.h @@ -0,0 +1,507 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_GPT_H_ +#define _FSL_GPT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpt + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_GPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ + /*@}*/ + +/*! + * @brief List of clock sources + * @note Actual number of clock sources is SoC dependent + */ +typedef enum _gpt_clock_source +{ + kGPT_ClockSource_Off = 0U, /*!< GPT Clock Source Off.*/ + kGPT_ClockSource_Periph = 1U, /*!< GPT Clock Source from Peripheral Clock.*/ + kGPT_ClockSource_HighFreq = 2U, /*!< GPT Clock Source from High Frequency Reference Clock.*/ + kGPT_ClockSource_Ext = 3U, /*!< GPT Clock Source from external pin.*/ + kGPT_ClockSource_LowFreq = 4U, /*!< GPT Clock Source from Low Frequency Reference Clock.*/ + kGPT_ClockSource_Osc = 5U, /*!< GPT Clock Source from Crystal oscillator.*/ +} gpt_clock_source_t; + +/*! @brief List of input capture channel number. */ +typedef enum _gpt_input_capture_channel +{ + kGPT_InputCapture_Channel1 = 0U, /*!< GPT Input Capture Channel1.*/ + kGPT_InputCapture_Channel2 = 1U, /*!< GPT Input Capture Channel2.*/ +} gpt_input_capture_channel_t; + +/*! @brief List of input capture operation mode. */ +typedef enum _gpt_input_operation_mode +{ + kGPT_InputOperation_Disabled = 0U, /*!< Don't capture.*/ + kGPT_InputOperation_RiseEdge = 1U, /*!< Capture on rising edge of input pin.*/ + kGPT_InputOperation_FallEdge = 2U, /*!< Capture on falling edge of input pin.*/ + kGPT_InputOperation_BothEdge = 3U, /*!< Capture on both edges of input pin.*/ +} gpt_input_operation_mode_t; + +/*! @brief List of output compare channel number. */ +typedef enum _gpt_output_compare_channel +{ + kGPT_OutputCompare_Channel1 = 0U, /*!< Output Compare Channel1.*/ + kGPT_OutputCompare_Channel2 = 1U, /*!< Output Compare Channel2.*/ + kGPT_OutputCompare_Channel3 = 2U, /*!< Output Compare Channel3.*/ +} gpt_output_compare_channel_t; + +/*! @brief List of output compare operation mode. */ +typedef enum _gpt_output_operation_mode +{ + kGPT_OutputOperation_Disconnected = 0U, /*!< Don't change output pin.*/ + kGPT_OutputOperation_Toggle = 1U, /*!< Toggle output pin.*/ + kGPT_OutputOperation_Clear = 2U, /*!< Set output pin low.*/ + kGPT_OutputOperation_Set = 3U, /*!< Set output pin high.*/ + kGPT_OutputOperation_Activelow = 4U, /*!< Generate a active low pulse on output pin.*/ +} gpt_output_operation_mode_t; + +/*! @brief List of GPT interrupts */ +typedef enum _gpt_interrupt_enable +{ + kGPT_OutputCompare1InterruptEnable = GPT_IR_OF1IE_MASK, /*!< Output Compare Channel1 interrupt enable*/ + kGPT_OutputCompare2InterruptEnable = GPT_IR_OF2IE_MASK, /*!< Output Compare Channel2 interrupt enable*/ + kGPT_OutputCompare3InterruptEnable = GPT_IR_OF3IE_MASK, /*!< Output Compare Channel3 interrupt enable*/ + kGPT_InputCapture1InterruptEnable = GPT_IR_IF1IE_MASK, /*!< Input Capture Channel1 interrupt enable*/ + kGPT_InputCapture2InterruptEnable = GPT_IR_IF2IE_MASK, /*!< Input Capture Channel1 interrupt enable*/ + kGPT_RollOverFlagInterruptEnable = GPT_IR_ROVIE_MASK, /*!< Counter rolled over interrupt enable*/ +} gpt_interrupt_enable_t; + +/*! @brief Status flag. */ +typedef enum _gpt_status_flag +{ + kGPT_OutputCompare1Flag = GPT_SR_OF1_MASK, /*!< Output compare channel 1 event.*/ + kGPT_OutputCompare2Flag = GPT_SR_OF2_MASK, /*!< Output compare channel 2 event.*/ + kGPT_OutputCompare3Flag = GPT_SR_OF3_MASK, /*!< Output compare channel 3 event.*/ + kGPT_InputCapture1Flag = GPT_SR_IF1_MASK, /*!< Input Capture channel 1 event.*/ + kGPT_InputCapture2Flag = GPT_SR_IF2_MASK, /*!< Input Capture channel 2 event.*/ + kGPT_RollOverFlag = GPT_SR_ROV_MASK, /*!< Counter reaches maximum value and rolled over to 0 event.*/ +} gpt_status_flag_t; + +/*! @brief Structure to configure the running mode. */ +typedef struct _gpt_init_config +{ + gpt_clock_source_t clockSource; /*!< clock source for GPT module. */ + uint32_t divider; /*!< clock divider (prescaler+1) from clock source to counter. */ + bool enableFreeRun; /*!< true: FreeRun mode, false: Restart mode. */ + bool enableRunInWait; /*!< GPT enabled in wait mode. */ + bool enableRunInStop; /*!< GPT enabled in stop mode. */ + bool enableRunInDoze; /*!< GPT enabled in doze mode. */ + bool enableRunInDbg; /*!< GPT enabled in debug mode. */ + bool enableMode; /*!< true: counter reset to 0 when enabled; + false: counter retain its value when enabled. */ +} gpt_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initialize GPT to reset state and initialize running mode. + * + * @param base GPT peripheral base address. + * @param initConfig GPT mode setting configuration. + */ +void GPT_Init(GPT_Type *base, const gpt_config_t *initConfig); + +/*! + * @brief Disables the module and gates the GPT clock. + * + * @param base GPT peripheral base address. + */ +void GPT_Deinit(GPT_Type *base); + +/*! + * @brief Fills in the GPT configuration structure with default settings. + * + * The default values are: + * @code + * config->clockSource = kGPT_ClockSource_Periph; + * config->divider = 1U; + * config->enableRunInStop = true; + * config->enableRunInWait = true; + * config->enableRunInDoze = false; + * config->enableRunInDbg = false; + * config->enableFreeRun = true; + * config->enableMode = true; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void GPT_GetDefaultConfig(gpt_config_t *config); + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Software reset of GPT module. + * + * @param base GPT peripheral base address. + */ +static inline void GPT_SoftwareReset(GPT_Type *base) +{ + base->CR |= GPT_CR_SWR_MASK; + /* Wait reset finished. */ + while ((base->CR & GPT_CR_SWR_MASK) == GPT_CR_SWR_MASK) + { + } +} + +/*! + * @name Clock source and frequency control + * @{ + */ + +/*! + * @brief Set clock source of GPT. + * + * @param base GPT peripheral base address. + * @param source Clock source (see @ref gpt_clock_source_t typedef enumeration). + */ +static inline void GPT_SetClockSource(GPT_Type *base, gpt_clock_source_t source) +{ + if (source == kGPT_ClockSource_Osc) + { + base->CR = (base->CR & ~GPT_CR_CLKSRC_MASK) | GPT_CR_EN_24M_MASK | GPT_CR_CLKSRC(source); + } + else + { + base->CR = (base->CR & ~(GPT_CR_CLKSRC_MASK | GPT_CR_EN_24M_MASK)) | GPT_CR_CLKSRC(source); + } +} + +/*! + * @brief Get clock source of GPT. + * + * @param base GPT peripheral base address. + * @return clock source (see @ref gpt_clock_source_t typedef enumeration). + */ +static inline gpt_clock_source_t GPT_GetClockSource(GPT_Type *base) +{ + return (gpt_clock_source_t)((base->CR & GPT_CR_CLKSRC_MASK) >> GPT_CR_CLKSRC_SHIFT); +} + +/*! + * @brief Set pre scaler of GPT. + * + * @param base GPT peripheral base address. + * @param divider Divider of GPT (1-4096). + */ +static inline void GPT_SetClockDivider(GPT_Type *base, uint32_t divider) +{ + assert(divider - 1 <= GPT_PR_PRESCALER_MASK); + + base->PR = (base->PR & ~GPT_PR_PRESCALER_MASK) | GPT_PR_PRESCALER(divider - 1); +} + +/*! + * @brief Get clock divider in GPT module. + * + * @param base GPT peripheral base address. + * @return clock divider in GPT module (1-4096). + */ +static inline uint32_t GPT_GetClockDivider(GPT_Type *base) +{ + return ((base->PR & GPT_PR_PRESCALER_MASK) >> GPT_PR_PRESCALER_SHIFT) + 1; +} + +/*! + * @brief OSC 24M pre-scaler before selected by clock source. + * + * @param base GPT peripheral base address. + * @param divider OSC Divider(1-16). + */ +static inline void GPT_SetOscClockDivider(GPT_Type *base, uint32_t divider) +{ + assert(divider - 1 <= (GPT_PR_PRESCALER24M_MASK >> GPT_PR_PRESCALER24M_SHIFT)); + + base->PR = (base->PR & ~GPT_PR_PRESCALER24M_MASK) | GPT_PR_PRESCALER24M(divider - 1); +} + +/*! + * @brief Get OSC 24M clock divider in GPT module. + * + * @param base GPT peripheral base address. + * @return OSC clock divider in GPT module (1-16). + */ +static inline uint32_t GPT_GetOscClockDivider(GPT_Type *base) +{ + return ((base->PR & GPT_PR_PRESCALER24M_MASK) >> GPT_PR_PRESCALER24M_SHIFT) + 1; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ +/*! + * @brief Start GPT timer. + * + * @param base GPT peripheral base address. + */ +static inline void GPT_StartTimer(GPT_Type *base) +{ + base->CR |= GPT_CR_EN_MASK; +} + +/*! + * @brief Stop GPT timer. + * + * @param base GPT peripheral base address. + */ +static inline void GPT_StopTimer(GPT_Type *base) +{ + base->CR &= ~GPT_CR_EN_MASK; +} + +/*! + * @name Read the timer period + * @{ + */ + +/*! + * @brief Reads the current GPT counting value. + * + * @param base GPT peripheral base address. + * @return Current GPT counter value. + */ +static inline uint32_t GPT_GetCurrentTimerCount(GPT_Type *base) +{ + return base->CNT; +} + +/*@}*/ + +/*! + * @name GPT Input/Output Signal Control + * @{ + */ + +/*! + * @brief Set GPT operation mode of input capture channel. + * + * @param base GPT peripheral base address. + * @param channel GPT capture channel (see @ref gpt_input_capture_channel_t typedef enumeration). + * @param mode GPT input capture operation mode (see @ref gpt_input_operation_mode_t typedef enumeration). + */ +static inline void GPT_SetInputOperationMode(GPT_Type *base, + gpt_input_capture_channel_t channel, + gpt_input_operation_mode_t mode) +{ + assert(channel <= kGPT_InputCapture_Channel2); + + base->CR = (base->CR & ~(GPT_CR_IM1_MASK << (channel * 2))) | (GPT_CR_IM1(mode) << (channel * 2)); +} + +/*! + * @brief Get GPT operation mode of input capture channel. + * + * @param base GPT peripheral base address. + * @param channel GPT capture channel (see @ref gpt_input_capture_channel_t typedef enumeration). + * @return GPT input capture operation mode (see @ref gpt_input_operation_mode_t typedef enumeration). + */ +static inline gpt_input_operation_mode_t GPT_GetInputOperationMode(GPT_Type *base, gpt_input_capture_channel_t channel) +{ + assert(channel <= kGPT_InputCapture_Channel2); + + return (gpt_input_operation_mode_t)((base->CR >> (GPT_CR_IM1_SHIFT + channel * 2)) & + (GPT_CR_IM1_MASK >> GPT_CR_IM1_SHIFT)); +} + +/*! + * @brief Get GPT input capture value of certain channel. + * + * @param base GPT peripheral base address. + * @param channel GPT capture channel (see @ref gpt_input_capture_channel_t typedef enumeration). + * @return GPT input capture value. + */ +static inline uint32_t GPT_GetInputCaptureValue(GPT_Type *base, gpt_input_capture_channel_t channel) +{ + assert(channel <= kGPT_InputCapture_Channel2); + + return *(&base->ICR[0] + channel); +} + +/*! + * @brief Set GPT operation mode of output compare channel. + * + * @param base GPT peripheral base address. + * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). + * @param mode GPT output operation mode (see @ref gpt_output_operation_mode_t typedef enumeration). + */ +static inline void GPT_SetOutputOperationMode(GPT_Type *base, + gpt_output_compare_channel_t channel, + gpt_output_operation_mode_t mode) +{ + assert(channel <= kGPT_OutputCompare_Channel3); + + base->CR = (base->CR & ~(GPT_CR_OM1_MASK << (channel * 3))) | (GPT_CR_OM1(mode) << (channel * 3)); +} + +/*! + * @brief Get GPT operation mode of output compare channel. + * + * @param base GPT peripheral base address. + * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). + * @return GPT output operation mode (see @ref gpt_output_operation_mode_t typedef enumeration). + */ +static inline gpt_output_operation_mode_t GPT_GetOutputOperationMode(GPT_Type *base, + gpt_output_compare_channel_t channel) +{ + assert(channel <= kGPT_OutputCompare_Channel3); + + return (gpt_output_operation_mode_t)((base->CR >> (GPT_CR_OM1_SHIFT + channel * 3)) & + (GPT_CR_OM1_MASK >> GPT_CR_OM1_SHIFT)); +} + +/*! + * @brief Set GPT output compare value of output compare channel. + * + * @param base GPT peripheral base address. + * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). + * @param value GPT output compare value. + */ +static inline void GPT_SetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel, uint32_t value) +{ + assert(channel <= kGPT_OutputCompare_Channel3); + + *(&base->OCR[0] + channel) = value; +} + +/*! + * @brief Get GPT output compare value of output compare channel. + * + * @param base GPT peripheral base address. + * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). + * @return GPT output compare value. + */ +static inline uint32_t GPT_GetOutputCompareValue(GPT_Type *base, gpt_output_compare_channel_t channel) +{ + assert(channel <= kGPT_OutputCompare_Channel3); + + return *(&base->OCR[0] + channel); +} + +/*! + * @brief Force GPT output action on output compare channel, ignoring comparator. + * + * @param base GPT peripheral base address. + * @param channel GPT output compare channel (see @ref gpt_output_compare_channel_t typedef enumeration). + */ +static inline void GPT_ForceOutput(GPT_Type *base, gpt_output_compare_channel_t channel) +{ + assert(channel <= kGPT_OutputCompare_Channel3); + + base->CR |= (GPT_CR_FO1_MASK << channel); +} + +/*@}*/ + +/*! + * @name GPT Interrupt and Status Interface + * @{ + */ + +/*! + * @brief Enables the selected GPT interrupts. + * + * @param base GPT peripheral base address. + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::gpt_interrupt_enable_t + */ +static inline void GPT_EnableInterrupts(GPT_Type *base, uint32_t mask) +{ + base->IR |= mask; +} + +/*! + * @brief Disables the selected GPT interrupts. + * + * @param base GPT peripheral base address + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::gpt_interrupt_enable_t + */ +static inline void GPT_DisableInterrupts(GPT_Type *base, uint32_t mask) +{ + base->IR &= ~mask; +} + +/*! + * @brief Gets the enabled GPT interrupts. + * + * @param base GPT peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::gpt_interrupt_enable_t + */ +static inline uint32_t GPT_GetEnabledInterrupts(GPT_Type *base) +{ + return (base->IR & (GPT_IR_OF1IE_MASK | GPT_IR_OF2IE_MASK | GPT_IR_OF3IE_MASK | GPT_IR_IF1IE_MASK | + GPT_IR_IF2IE_MASK | GPT_IR_ROVIE_MASK)); +} + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Get GPT status flags. + * + * @param base GPT peripheral base address. + * @param flags GPT status flag mask (see @ref gpt_status_flag_t for bit definition). + * @return GPT status, each bit represents one status flag. + */ +static inline uint32_t GPT_GetStatusFlags(GPT_Type *base, gpt_status_flag_t flags) +{ + return base->SR & flags; +} + +/*! + * @brief Clears the GPT status flags. + * + * @param base GPT peripheral base address. + * @param flags GPT status flag mask (see @ref gpt_status_flag_t for bit definition). + */ +static inline void GPT_ClearStatusFlags(GPT_Type *base, gpt_status_flag_t flags) +{ + base->SR = flags; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_GPT_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_iomuxc.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_iomuxc.h new file mode 100644 index 0000000000..5c4a5c28fa --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_iomuxc.h @@ -0,0 +1,1420 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.1. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @name Pin function ID */ +/*@{*/ +/*! @brief The pin function ID is a tuple of */ +#define IOMUXC_SNVS_WAKEUP_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8018U +#define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI 0x400A8000U, 0x7U, 0x401F8568U, 0x1U, 0x400A8018U + +#define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ 0x400A8004U, 0x0U, 0, 0, 0x400A801CU +#define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 0x400A8004U, 0x5U, 0, 0, 0x400A801CU + +#define IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ 0x400A8008U, 0x0U, 0, 0, 0x400A8020U +#define IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 0x400A8008U, 0x5U, 0, 0, 0x400A8020U + +#define IOMUXC_SNVS_TEST_MODE 0, 0, 0, 0, 0x400A800CU + +#define IOMUXC_SNVS_POR_B 0, 0, 0, 0, 0x400A8010U + +#define IOMUXC_SNVS_ONOFF 0, 0, 0, 0, 0x400A8014U + +#define IOMUXC_GPIO_EMC_00_SEMC_DATA00 0x401F8014U, 0x0U, 0, 0, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA00 0x401F8014U, 0x1U, 0x401F8494U, 0x0U, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x401F8014U, 0x2U, 0x401F8500U, 0x1U, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 0x401F8014U, 0x3U, 0x401F860CU, 0x0U, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 0x401F8014U, 0x4U, 0, 0, 0x401F8204U +#define IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x401F8014U, 0x5U, 0, 0, 0x401F8204U + +#define IOMUXC_GPIO_EMC_01_SEMC_DATA01 0x401F8018U, 0x0U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB00 0x401F8018U, 0x1U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x401F8018U, 0x2U, 0x401F84FCU, 0x1U, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_XBAR1_IN03 0x401F8018U, 0x3U, 0x401F8610U, 0x0U, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 0x401F8018U, 0x4U, 0, 0, 0x401F8208U +#define IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x401F8018U, 0x5U, 0, 0, 0x401F8208U + +#define IOMUXC_GPIO_EMC_02_SEMC_DATA02 0x401F801CU, 0x0U, 0, 0, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA01 0x401F801CU, 0x1U, 0x401F8498U, 0x0U, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x401F801CU, 0x2U, 0x401F8508U, 0x1U, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_XBAR1_INOUT04 0x401F801CU, 0x3U, 0x401F8614U, 0x0U, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 0x401F801CU, 0x4U, 0, 0, 0x401F820CU +#define IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x401F801CU, 0x5U, 0, 0, 0x401F820CU + +#define IOMUXC_GPIO_EMC_03_SEMC_DATA03 0x401F8020U, 0x0U, 0, 0, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB01 0x401F8020U, 0x1U, 0, 0, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x401F8020U, 0x2U, 0x401F8504U, 0x1U, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_XBAR1_INOUT05 0x401F8020U, 0x3U, 0x401F8618U, 0x0U, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 0x401F8020U, 0x4U, 0, 0, 0x401F8210U +#define IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x401F8020U, 0x5U, 0, 0, 0x401F8210U + +#define IOMUXC_GPIO_EMC_04_SEMC_DATA04 0x401F8024U, 0x0U, 0, 0, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA02 0x401F8024U, 0x1U, 0x401F849CU, 0x0U, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x401F8024U, 0x2U, 0, 0, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_XBAR1_INOUT06 0x401F8024U, 0x3U, 0x401F861CU, 0x0U, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04 0x401F8024U, 0x4U, 0, 0, 0x401F8214U +#define IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x401F8024U, 0x5U, 0, 0, 0x401F8214U + +#define IOMUXC_GPIO_EMC_05_SEMC_DATA05 0x401F8028U, 0x0U, 0, 0, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB02 0x401F8028U, 0x1U, 0, 0, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x401F8028U, 0x2U, 0x401F85C4U, 0x0U, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_XBAR1_INOUT07 0x401F8028U, 0x3U, 0x401F8620U, 0x0U, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05 0x401F8028U, 0x4U, 0, 0, 0x401F8218U +#define IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x401F8028U, 0x5U, 0, 0, 0x401F8218U + +#define IOMUXC_GPIO_EMC_06_SEMC_DATA06 0x401F802CU, 0x0U, 0, 0, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA00 0x401F802CU, 0x1U, 0x401F8478U, 0x0U, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x401F802CU, 0x2U, 0x401F85C0U, 0x0U, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_XBAR1_INOUT08 0x401F802CU, 0x3U, 0x401F8624U, 0x0U, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06 0x401F802CU, 0x4U, 0, 0, 0x401F821CU +#define IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x401F802CU, 0x5U, 0, 0, 0x401F821CU + +#define IOMUXC_GPIO_EMC_07_SEMC_DATA07 0x401F8030U, 0x0U, 0, 0, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB00 0x401F8030U, 0x1U, 0x401F8488U, 0x0U, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x401F8030U, 0x2U, 0x401F85B0U, 0x0U, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_XBAR1_INOUT09 0x401F8030U, 0x3U, 0x401F8628U, 0x0U, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07 0x401F8030U, 0x4U, 0, 0, 0x401F8220U +#define IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x401F8030U, 0x5U, 0, 0, 0x401F8220U + +#define IOMUXC_GPIO_EMC_08_SEMC_DM00 0x401F8034U, 0x0U, 0, 0, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA01 0x401F8034U, 0x1U, 0x401F847CU, 0x0U, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x401F8034U, 0x2U, 0x401F85B8U, 0x0U, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_XBAR1_INOUT17 0x401F8034U, 0x3U, 0x401F862CU, 0x0U, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08 0x401F8034U, 0x4U, 0, 0, 0x401F8224U +#define IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x401F8034U, 0x5U, 0, 0, 0x401F8224U + +#define IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x401F8038U, 0x0U, 0, 0, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB01 0x401F8038U, 0x1U, 0x401F848CU, 0x0U, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x401F8038U, 0x2U, 0x401F85BCU, 0x0U, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x401F8038U, 0x3U, 0, 0, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09 0x401F8038U, 0x4U, 0, 0, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x401F8038U, 0x5U, 0, 0, 0x401F8228U +#define IOMUXC_GPIO_EMC_09_FLEXSPI2_B_SS1_B 0x401F8038U, 0x8U, 0, 0, 0x401F8228U + +#define IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x401F803CU, 0x0U, 0, 0, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA02 0x401F803CU, 0x1U, 0x401F8480U, 0x0U, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x401F803CU, 0x2U, 0x401F85B4U, 0x0U, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x401F803CU, 0x3U, 0x401F8450U, 0x0U, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10 0x401F803CU, 0x4U, 0, 0, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x401F803CU, 0x5U, 0, 0, 0x401F822CU +#define IOMUXC_GPIO_EMC_10_FLEXSPI2_B_SS0_B 0x401F803CU, 0x8U, 0, 0, 0x401F822CU + +#define IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x401F8040U, 0x0U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB02 0x401F8040U, 0x1U, 0x401F8490U, 0x0U, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x401F8040U, 0x2U, 0x401F84E8U, 0x0U, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x401F8040U, 0x3U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11 0x401F8040U, 0x4U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x401F8040U, 0x5U, 0, 0, 0x401F8230U +#define IOMUXC_GPIO_EMC_11_FLEXSPI2_B_DQS 0x401F8040U, 0x8U, 0, 0, 0x401F8230U + +#define IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x401F8044U, 0x0U, 0, 0, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_XBAR1_IN24 0x401F8044U, 0x1U, 0x401F8640U, 0x0U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x401F8044U, 0x2U, 0x401F84E4U, 0x0U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_USDHC1_WP 0x401F8044U, 0x3U, 0x401F85D8U, 0x0U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA03 0x401F8044U, 0x4U, 0x401F8454U, 0x1U, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x401F8044U, 0x5U, 0, 0, 0x401F8234U +#define IOMUXC_GPIO_EMC_12_FLEXSPI2_B_SCLK 0x401F8044U, 0x8U, 0x401F8754U, 0x0U, 0x401F8234U + +#define IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x401F8048U, 0x0U, 0, 0, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_XBAR1_IN25 0x401F8048U, 0x1U, 0x401F8650U, 0x1U, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_LPUART3_TX 0x401F8048U, 0x2U, 0x401F853CU, 0x1U, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x401F8048U, 0x3U, 0, 0, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB03 0x401F8048U, 0x4U, 0x401F8464U, 0x1U, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x401F8048U, 0x5U, 0, 0, 0x401F8238U +#define IOMUXC_GPIO_EMC_13_FLEXSPI2_B_DATA00 0x401F8048U, 0x8U, 0x401F8740U, 0x0U, 0x401F8238U + +#define IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x401F804CU, 0x0U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_XBAR1_INOUT19 0x401F804CU, 0x1U, 0x401F8654U, 0x0U, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_LPUART3_RX 0x401F804CU, 0x2U, 0x401F8538U, 0x1U, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_MQS_LEFT 0x401F804CU, 0x3U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x401F804CU, 0x4U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x401F804CU, 0x5U, 0, 0, 0x401F823CU +#define IOMUXC_GPIO_EMC_14_FLEXSPI2_B_DATA01 0x401F804CU, 0x8U, 0x401F8744U, 0x0U, 0x401F823CU + +#define IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x401F8050U, 0x0U, 0, 0, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_XBAR1_IN20 0x401F8050U, 0x1U, 0x401F8634U, 0x0U, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x401F8050U, 0x2U, 0x401F8534U, 0x0U, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x401F8050U, 0x3U, 0, 0, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0 0x401F8050U, 0x4U, 0x401F857CU, 0x0U, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x401F8050U, 0x5U, 0, 0, 0x401F8240U +#define IOMUXC_GPIO_EMC_15_FLEXSPI2_B_DATA02 0x401F8050U, 0x8U, 0x401F8748U, 0x0U, 0x401F8240U + +#define IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x401F8054U, 0x0U, 0, 0, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_XBAR1_IN21 0x401F8054U, 0x1U, 0x401F8658U, 0x0U, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x401F8054U, 0x2U, 0, 0, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_SPDIF_IN 0x401F8054U, 0x3U, 0x401F85C8U, 0x1U, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1 0x401F8054U, 0x4U, 0x401F8580U, 0x1U, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x401F8054U, 0x5U, 0, 0, 0x401F8244U +#define IOMUXC_GPIO_EMC_16_FLEXSPI2_B_DATA03 0x401F8054U, 0x8U, 0x401F874CU, 0x0U, 0x401F8244U + +#define IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x401F8058U, 0x0U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA03 0x401F8058U, 0x1U, 0x401F84A0U, 0x0U, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x401F8058U, 0x2U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x401F8058U, 0x3U, 0, 0, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2 0x401F8058U, 0x4U, 0x401F8584U, 0x0U, 0x401F8248U +#define IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x401F8058U, 0x5U, 0, 0, 0x401F8248U + +#define IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x401F805CU, 0x0U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB03 0x401F805CU, 0x1U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x401F805CU, 0x2U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x401F805CU, 0x3U, 0x401F844CU, 0x1U, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3 0x401F805CU, 0x4U, 0x401F8588U, 0x0U, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x401F805CU, 0x5U, 0, 0, 0x401F824CU +#define IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x401F805CU, 0x6U, 0, 0, 0x401F824CU + +#define IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x401F8060U, 0x0U, 0, 0, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA03 0x401F8060U, 0x1U, 0x401F8474U, 0x1U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_LPUART4_TX 0x401F8060U, 0x2U, 0x401F8544U, 0x1U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_ENET_RDATA01 0x401F8060U, 0x3U, 0x401F8438U, 0x0U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0 0x401F8060U, 0x4U, 0x401F856CU, 0x0U, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x401F8060U, 0x5U, 0, 0, 0x401F8250U +#define IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x401F8060U, 0x6U, 0, 0, 0x401F8250U + +#define IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x401F8064U, 0x0U, 0, 0, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB03 0x401F8064U, 0x1U, 0x401F8484U, 0x1U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_LPUART4_RX 0x401F8064U, 0x2U, 0x401F8540U, 0x1U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_ENET_RDATA00 0x401F8064U, 0x3U, 0x401F8434U, 0x0U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1 0x401F8064U, 0x4U, 0x401F8570U, 0x0U, 0x401F8254U +#define IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x401F8064U, 0x5U, 0, 0, 0x401F8254U + +#define IOMUXC_GPIO_EMC_21_SEMC_BA0 0x401F8068U, 0x0U, 0, 0, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA03 0x401F8068U, 0x1U, 0, 0, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x401F8068U, 0x2U, 0x401F84E0U, 0x0U, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_ENET_TDATA01 0x401F8068U, 0x3U, 0, 0, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2 0x401F8068U, 0x4U, 0x401F8574U, 0x0U, 0x401F8258U +#define IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x401F8068U, 0x5U, 0, 0, 0x401F8258U + +#define IOMUXC_GPIO_EMC_22_SEMC_BA1 0x401F806CU, 0x0U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB03 0x401F806CU, 0x1U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x401F806CU, 0x2U, 0x401F84DCU, 0x0U, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_ENET_TDATA00 0x401F806CU, 0x3U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3 0x401F806CU, 0x4U, 0x401F8578U, 0x0U, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x401F806CU, 0x5U, 0, 0, 0x401F825CU +#define IOMUXC_GPIO_EMC_22_FLEXSPI2_A_SS1_B 0x401F806CU, 0x8U, 0, 0, 0x401F825CU + +#define IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x401F8070U, 0x0U, 0, 0, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA00 0x401F8070U, 0x1U, 0x401F8458U, 0x0U, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_LPUART5_TX 0x401F8070U, 0x2U, 0x401F854CU, 0x0U, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x401F8070U, 0x3U, 0x401F843CU, 0x0U, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x401F8070U, 0x4U, 0x401F875CU, 0x0U, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x401F8070U, 0x5U, 0, 0, 0x401F8260U +#define IOMUXC_GPIO_EMC_23_FLEXSPI2_A_DQS 0x401F8070U, 0x8U, 0x401F872CU, 0x1U, 0x401F8260U + +#define IOMUXC_GPIO_EMC_24_SEMC_CAS 0x401F8074U, 0x0U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB00 0x401F8074U, 0x1U, 0x401F8468U, 0x0U, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_LPUART5_RX 0x401F8074U, 0x2U, 0x401F8548U, 0x0U, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x401F8074U, 0x3U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x401F8074U, 0x4U, 0x401F8758U, 0x0U, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x401F8074U, 0x5U, 0, 0, 0x401F8264U +#define IOMUXC_GPIO_EMC_24_FLEXSPI2_A_SS0_B 0x401F8074U, 0x8U, 0, 0, 0x401F8264U + +#define IOMUXC_GPIO_EMC_25_SEMC_RAS 0x401F8078U, 0x0U, 0, 0, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA01 0x401F8078U, 0x1U, 0x401F845CU, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_LPUART6_TX 0x401F8078U, 0x2U, 0x401F8554U, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x401F8078U, 0x3U, 0x401F8448U, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x401F8078U, 0x4U, 0x401F842CU, 0x0U, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x401F8078U, 0x5U, 0, 0, 0x401F8268U +#define IOMUXC_GPIO_EMC_25_FLEXSPI2_A_SCLK 0x401F8078U, 0x8U, 0x401F8750U, 0x1U, 0x401F8268U + +#define IOMUXC_GPIO_EMC_26_SEMC_CLK 0x401F807CU, 0x0U, 0, 0, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB01 0x401F807CU, 0x1U, 0x401F846CU, 0x0U, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_LPUART6_RX 0x401F807CU, 0x2U, 0x401F8550U, 0x0U, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x401F807CU, 0x3U, 0x401F8440U, 0x0U, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12 0x401F807CU, 0x4U, 0, 0, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x401F807CU, 0x5U, 0, 0, 0x401F826CU +#define IOMUXC_GPIO_EMC_26_FLEXSPI2_A_DATA00 0x401F807CU, 0x8U, 0x401F8730U, 0x1U, 0x401F826CU + +#define IOMUXC_GPIO_EMC_27_SEMC_CKE 0x401F8080U, 0x0U, 0, 0, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA02 0x401F8080U, 0x1U, 0x401F8460U, 0x0U, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x401F8080U, 0x2U, 0, 0, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x401F8080U, 0x3U, 0x401F84F0U, 0x0U, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13 0x401F8080U, 0x4U, 0, 0, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x401F8080U, 0x5U, 0, 0, 0x401F8270U +#define IOMUXC_GPIO_EMC_27_FLEXSPI2_A_DATA01 0x401F8080U, 0x8U, 0x401F8734U, 0x1U, 0x401F8270U + +#define IOMUXC_GPIO_EMC_28_SEMC_WE 0x401F8084U, 0x0U, 0, 0, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB02 0x401F8084U, 0x1U, 0x401F8470U, 0x0U, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x401F8084U, 0x2U, 0, 0, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x401F8084U, 0x3U, 0x401F84F8U, 0x0U, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14 0x401F8084U, 0x4U, 0, 0, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x401F8084U, 0x5U, 0, 0, 0x401F8274U +#define IOMUXC_GPIO_EMC_28_FLEXSPI2_A_DATA02 0x401F8084U, 0x8U, 0x401F8738U, 0x1U, 0x401F8274U + +#define IOMUXC_GPIO_EMC_29_SEMC_CS0 0x401F8088U, 0x0U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA00 0x401F8088U, 0x1U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x401F8088U, 0x2U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x401F8088U, 0x3U, 0x401F84F4U, 0x0U, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15 0x401F8088U, 0x4U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x401F8088U, 0x5U, 0, 0, 0x401F8278U +#define IOMUXC_GPIO_EMC_29_FLEXSPI2_A_DATA03 0x401F8088U, 0x8U, 0x401F873CU, 0x1U, 0x401F8278U + +#define IOMUXC_GPIO_EMC_30_SEMC_DATA08 0x401F808CU, 0x0U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB00 0x401F808CU, 0x1U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x401F808CU, 0x2U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x401F808CU, 0x3U, 0x401F84ECU, 0x1U, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_CSI_DATA23 0x401F808CU, 0x4U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x401F808CU, 0x5U, 0, 0, 0x401F827CU +#define IOMUXC_GPIO_EMC_30_ENET2_TDATA00 0x401F808CU, 0x8U, 0, 0, 0x401F827CU + +#define IOMUXC_GPIO_EMC_31_SEMC_DATA09 0x401F8090U, 0x0U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA01 0x401F8090U, 0x1U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_LPUART7_TX 0x401F8090U, 0x2U, 0x401F855CU, 0x1U, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x401F8090U, 0x3U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_CSI_DATA22 0x401F8090U, 0x4U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x401F8090U, 0x5U, 0, 0, 0x401F8280U +#define IOMUXC_GPIO_EMC_31_ENET2_TDATA01 0x401F8090U, 0x8U, 0, 0, 0x401F8280U + +#define IOMUXC_GPIO_EMC_32_SEMC_DATA10 0x401F8094U, 0x0U, 0, 0, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB01 0x401F8094U, 0x1U, 0, 0, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_LPUART7_RX 0x401F8094U, 0x2U, 0x401F8558U, 0x1U, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY 0x401F8094U, 0x3U, 0x401F83FCU, 0x4U, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_CSI_DATA21 0x401F8094U, 0x4U, 0, 0, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x401F8094U, 0x5U, 0, 0, 0x401F8284U +#define IOMUXC_GPIO_EMC_32_ENET2_TX_EN 0x401F8094U, 0x8U, 0, 0, 0x401F8284U + +#define IOMUXC_GPIO_EMC_33_SEMC_DATA11 0x401F8098U, 0x0U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA02 0x401F8098U, 0x1U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x401F8098U, 0x2U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x401F8098U, 0x3U, 0x401F8778U, 0x0U, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_CSI_DATA20 0x401F8098U, 0x4U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x401F8098U, 0x5U, 0, 0, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_ENET2_TX_CLK 0x401F8098U, 0x8U, 0x401F8728U, 0x0U, 0x401F8288U +#define IOMUXC_GPIO_EMC_33_ENET2_REF_CLK2 0x401F8098U, 0x9U, 0x401F870CU, 0x0U, 0x401F8288U + +#define IOMUXC_GPIO_EMC_34_SEMC_DATA12 0x401F809CU, 0x0U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB02 0x401F809CU, 0x1U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x401F809CU, 0x2U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x401F809CU, 0x3U, 0x401F877CU, 0x0U, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_CSI_DATA19 0x401F809CU, 0x4U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x401F809CU, 0x5U, 0, 0, 0x401F828CU +#define IOMUXC_GPIO_EMC_34_ENET2_RX_ER 0x401F809CU, 0x8U, 0x401F8720U, 0x0U, 0x401F828CU + +#define IOMUXC_GPIO_EMC_35_SEMC_DATA13 0x401F80A0U, 0x0U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_XBAR1_INOUT18 0x401F80A0U, 0x1U, 0x401F8630U, 0x0U, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x401F80A0U, 0x2U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x401F80A0U, 0x3U, 0x401F8774U, 0x0U, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_CSI_DATA18 0x401F80A0U, 0x4U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x401F80A0U, 0x5U, 0, 0, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x401F80A0U, 0x6U, 0x401F85D4U, 0x0U, 0x401F8290U +#define IOMUXC_GPIO_EMC_35_ENET2_RDATA00 0x401F80A0U, 0x8U, 0x401F8714U, 0x0U, 0x401F8290U + +#define IOMUXC_GPIO_EMC_36_SEMC_DATA14 0x401F80A4U, 0x0U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_XBAR1_IN22 0x401F80A4U, 0x1U, 0x401F8638U, 0x0U, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x401F80A4U, 0x2U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x401F80A4U, 0x3U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_CSI_DATA17 0x401F80A4U, 0x4U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x401F80A4U, 0x5U, 0, 0, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_USDHC1_WP 0x401F80A4U, 0x6U, 0x401F85D8U, 0x1U, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_ENET2_RDATA01 0x401F80A4U, 0x8U, 0x401F8718U, 0x0U, 0x401F8294U +#define IOMUXC_GPIO_EMC_36_FLEXCAN3_TX 0x401F80A4U, 0x9U, 0, 0, 0x401F8294U + +#define IOMUXC_GPIO_EMC_37_SEMC_DATA15 0x401F80A8U, 0x0U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_XBAR1_IN23 0x401F80A8U, 0x1U, 0x401F863CU, 0x0U, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x401F80A8U, 0x2U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x401F80A8U, 0x3U, 0x401F8770U, 0x0U, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_CSI_DATA16 0x401F80A8U, 0x4U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x401F80A8U, 0x5U, 0, 0, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_USDHC2_WP 0x401F80A8U, 0x6U, 0x401F8608U, 0x0U, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_ENET2_RX_EN 0x401F80A8U, 0x8U, 0x401F871CU, 0x0U, 0x401F8298U +#define IOMUXC_GPIO_EMC_37_FLEXCAN3_RX 0x401F80A8U, 0x9U, 0x401F878CU, 0x0U, 0x401F8298U + +#define IOMUXC_GPIO_EMC_38_SEMC_DM01 0x401F80ACU, 0x0U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA03 0x401F80ACU, 0x1U, 0x401F8454U, 0x2U, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_LPUART8_TX 0x401F80ACU, 0x2U, 0x401F8564U, 0x2U, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x401F80ACU, 0x3U, 0x401F8780U, 0x0U, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_CSI_FIELD 0x401F80ACU, 0x4U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x401F80ACU, 0x5U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x401F80ACU, 0x6U, 0, 0, 0x401F829CU +#define IOMUXC_GPIO_EMC_38_ENET2_MDC 0x401F80ACU, 0x8U, 0, 0, 0x401F829CU + +#define IOMUXC_GPIO_EMC_39_SEMC_DQS 0x401F80B0U, 0x0U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB03 0x401F80B0U, 0x1U, 0x401F8464U, 0x2U, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_LPUART8_RX 0x401F80B0U, 0x2U, 0x401F8560U, 0x2U, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x401F80B0U, 0x3U, 0x401F8784U, 0x0U, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_WDOG1_WDOG_B 0x401F80B0U, 0x4U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x401F80B0U, 0x5U, 0, 0, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x401F80B0U, 0x6U, 0x401F85E0U, 0x1U, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_ENET2_MDIO 0x401F80B0U, 0x8U, 0x401F8710U, 0x0U, 0x401F82A0U +#define IOMUXC_GPIO_EMC_39_SEMC_DQS4 0x401F80B0U, 0x9U, 0x401F8788U, 0x1U, 0x401F82A0U + +#define IOMUXC_GPIO_EMC_40_SEMC_RDY 0x401F80B4U, 0x0U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x401F80B4U, 0x1U, 0x401F8768U, 0x0U, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x401F80B4U, 0x2U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x401F80B4U, 0x3U, 0x401F85CCU, 0x1U, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_ENET_MDC 0x401F80B4U, 0x4U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x401F80B4U, 0x5U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x401F80B4U, 0x6U, 0, 0, 0x401F82A4U +#define IOMUXC_GPIO_EMC_40_SEMC_CLK5 0x401F80B4U, 0x9U, 0, 0, 0x401F82A4U + +#define IOMUXC_GPIO_EMC_41_SEMC_CSX00 0x401F80B8U, 0x0U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x401F80B8U, 0x1U, 0x401F8764U, 0x0U, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x401F80B8U, 0x2U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x401F80B8U, 0x3U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_ENET_MDIO 0x401F80B8U, 0x4U, 0x401F8430U, 0x1U, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x401F80B8U, 0x5U, 0, 0, 0x401F82A8U +#define IOMUXC_GPIO_EMC_41_USDHC1_VSELECT 0x401F80B8U, 0x6U, 0, 0, 0x401F82A8U + +#define IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWMA03 0x401F80BCU, 0x0U, 0x401F8474U, 0x2U, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_XBAR1_INOUT14 0x401F80BCU, 0x1U, 0x401F8644U, 0x0U, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x401F80BCU, 0x2U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x401F80BCU, 0x3U, 0x401F83F8U, 0x0U, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x401F80BCU, 0x4U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x401F80BCU, 0x5U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x401F80BCU, 0x6U, 0, 0, 0x401F82ACU +#define IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x401F80BCU, 0x7U, 0x401F8510U, 0x0U, 0x401F82ACU + +#define IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWMB03 0x401F80C0U, 0x0U, 0x401F8484U, 0x2U, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_XBAR1_INOUT15 0x401F80C0U, 0x1U, 0x401F8648U, 0x0U, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x401F80C0U, 0x2U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x401F80C0U, 0x3U, 0x401F83F4U, 0x0U, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x401F80C0U, 0x4U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x401F80C0U, 0x5U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x401F80C0U, 0x6U, 0, 0, 0x401F82B0U +#define IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x401F80C0U, 0x7U, 0x401F8518U, 0x0U, 0x401F82B0U + +#define IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x401F80C4U, 0x0U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_XBAR1_INOUT16 0x401F80C4U, 0x1U, 0x401F864CU, 0x0U, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_LPUART6_TX 0x401F80C4U, 0x2U, 0x401F8554U, 0x1U, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x401F80C4U, 0x3U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWMX00 0x401F80C4U, 0x4U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x401F80C4U, 0x5U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x401F80C4U, 0x6U, 0, 0, 0x401F82B4U +#define IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x401F80C4U, 0x7U, 0x401F8514U, 0x0U, 0x401F82B4U + +#define IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x401F80C8U, 0x0U, 0x401F8450U, 0x1U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_XBAR1_INOUT17 0x401F80C8U, 0x1U, 0x401F862CU, 0x1U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_LPUART6_RX 0x401F80C8U, 0x2U, 0x401F8550U, 0x1U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x401F80C8U, 0x3U, 0x401F85D0U, 0x0U, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWMX01 0x401F80C8U, 0x4U, 0, 0, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x401F80C8U, 0x5U, 0, 0, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x401F80C8U, 0x6U, 0, 0, 0x401F82B8U +#define IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x401F80C8U, 0x7U, 0x401F850CU, 0x0U, 0x401F82B8U + +#define IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x401F80CCU, 0x0U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x401F80CCU, 0x1U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x401F80CCU, 0x2U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x401F80CCU, 0x3U, 0x401F85C4U, 0x1U, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x401F80CCU, 0x4U, 0x401F841CU, 0x1U, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x401F80CCU, 0x5U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x401F80CCU, 0x6U, 0, 0, 0x401F82BCU +#define IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x401F80CCU, 0x7U, 0, 0, 0x401F82BCU + +#define IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x401F80D0U, 0x0U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x401F80D0U, 0x1U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x401F80D0U, 0x2U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x401F80D0U, 0x3U, 0x401F85C0U, 0x1U, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x401F80D0U, 0x4U, 0x401F8418U, 0x1U, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x401F80D0U, 0x5U, 0, 0, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_XBAR1_INOUT17 0x401F80D0U, 0x6U, 0x401F862CU, 0x2U, 0x401F82C0U +#define IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x401F80D0U, 0x7U, 0, 0, 0x401F82C0U + +#define IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x401F80D4U, 0x0U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x401F80D4U, 0x1U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x401F80D4U, 0x2U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x401F80D4U, 0x3U, 0x401F85B4U, 0x1U, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x401F80D4U, 0x4U, 0x401F8414U, 0x1U, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x401F80D4U, 0x5U, 0, 0, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_XBAR1_INOUT18 0x401F80D4U, 0x6U, 0x401F8630U, 0x1U, 0x401F82C4U +#define IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x401F80D4U, 0x7U, 0, 0, 0x401F82C4U + +#define IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x401F80D8U, 0x0U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x401F80D8U, 0x1U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x401F80D8U, 0x2U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x401F80D8U, 0x3U, 0x401F85BCU, 0x1U, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x401F80D8U, 0x4U, 0x401F8410U, 0x1U, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x401F80D8U, 0x5U, 0, 0, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_XBAR1_INOUT19 0x401F80D8U, 0x6U, 0x401F8654U, 0x1U, 0x401F82C8U +#define IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x401F80D8U, 0x7U, 0, 0, 0x401F82C8U + +#define IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x401F80DCU, 0x0U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x401F80DCU, 0x1U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x401F80DCU, 0x2U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x401F80DCU, 0x3U, 0x401F85B8U, 0x1U, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x401F80DCU, 0x4U, 0x401F840CU, 0x1U, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x401F80DCU, 0x5U, 0, 0, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_XBAR1_IN20 0x401F80DCU, 0x6U, 0x401F8634U, 0x1U, 0x401F82CCU +#define IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x401F80DCU, 0x7U, 0, 0, 0x401F82CCU + +#define IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x401F80E0U, 0x0U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA03 0x401F80E0U, 0x1U, 0x401F8474U, 0x3U, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x401F80E0U, 0x2U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x401F80E0U, 0x3U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x401F80E0U, 0x4U, 0x401F8408U, 0x1U, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x401F80E0U, 0x5U, 0, 0, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_XBAR1_IN21 0x401F80E0U, 0x6U, 0x401F8658U, 0x1U, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x401F80E0U, 0x7U, 0x401F876CU, 0x0U, 0x401F82D0U +#define IOMUXC_GPIO_AD_B0_09_SEMC_DQS4 0x401F80E0U, 0x9U, 0x401F8788U, 0x2U, 0x401F82D0U + +#define IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x401F80E4U, 0x0U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA03 0x401F80E4U, 0x1U, 0x401F8454U, 0x3U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x401F80E4U, 0x2U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x401F80E4U, 0x3U, 0x401F85B0U, 0x1U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x401F80E4U, 0x4U, 0x401F8404U, 0x1U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x401F80E4U, 0x5U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_XBAR1_IN22 0x401F80E4U, 0x6U, 0x401F8638U, 0x1U, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x401F80E4U, 0x7U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_FLEXCAN3_TX 0x401F80E4U, 0x8U, 0, 0, 0x401F82D4U +#define IOMUXC_GPIO_AD_B0_10_ARM_TRACE_SWO 0x401F80E4U, 0x9U, 0, 0, 0x401F82D4U + +#define IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x401F80E8U, 0x0U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB03 0x401F80E8U, 0x1U, 0x401F8464U, 0x3U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_ENET_COL 0x401F80E8U, 0x2U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_WDOG1_WDOG_B 0x401F80E8U, 0x3U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x401F80E8U, 0x4U, 0x401F8400U, 0x1U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x401F80E8U, 0x5U, 0, 0, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_XBAR1_IN23 0x401F80E8U, 0x6U, 0x401F863CU, 0x1U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x401F80E8U, 0x7U, 0x401F8444U, 0x1U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_FLEXCAN3_RX 0x401F80E8U, 0x8U, 0x401F878CU, 0x2U, 0x401F82D8U +#define IOMUXC_GPIO_AD_B0_11_SEMC_CLK6 0x401F80E8U, 0x9U, 0, 0, 0x401F82D8U + +#define IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x401F80ECU, 0x0U, 0x401F84E4U, 0x1U, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x401F80ECU, 0x1U, 0x401F83FCU, 0x1U, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_LPUART1_TX 0x401F80ECU, 0x2U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_WDOG2_WDOG_B 0x401F80ECU, 0x3U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX02 0x401F80ECU, 0x4U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x401F80ECU, 0x5U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x401F80ECU, 0x6U, 0, 0, 0x401F82DCU +#define IOMUXC_GPIO_AD_B0_12_NMI_GLUE_NMI 0x401F80ECU, 0x7U, 0x401F8568U, 0x0U, 0x401F82DCU + +#define IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x401F80F0U, 0x0U, 0x401F84E8U, 0x1U, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x401F80F0U, 0x1U, 0x401F8760U, 0x0U, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_LPUART1_RX 0x401F80F0U, 0x2U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x401F80F0U, 0x3U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX03 0x401F80F0U, 0x4U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x401F80F0U, 0x5U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x401F80F0U, 0x6U, 0, 0, 0x401F82E0U +#define IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x401F80F0U, 0x7U, 0, 0, 0x401F82E0U + +#define IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x401F80F4U, 0x0U, 0x401F85CCU, 0x0U, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_XBAR1_IN24 0x401F80F4U, 0x1U, 0x401F8640U, 0x1U, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x401F80F4U, 0x2U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x401F80F4U, 0x3U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x401F80F4U, 0x4U, 0x401F8428U, 0x0U, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x401F80F4U, 0x5U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x401F80F4U, 0x6U, 0, 0, 0x401F82E4U +#define IOMUXC_GPIO_AD_B0_14_FLEXCAN3_TX 0x401F80F4U, 0x8U, 0, 0, 0x401F82E4U + +#define IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x401F80F8U, 0x0U, 0, 0, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_XBAR1_IN25 0x401F80F8U, 0x1U, 0x401F8650U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x401F80F8U, 0x2U, 0, 0, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x401F80F8U, 0x3U, 0x401F8444U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x401F80F8U, 0x4U, 0x401F8420U, 0x0U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x401F80F8U, 0x5U, 0, 0, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x401F80F8U, 0x6U, 0x401F8450U, 0x2U, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x401F80F8U, 0x7U, 0, 0, 0x401F82E8U +#define IOMUXC_GPIO_AD_B0_15_FLEXCAN3_RX 0x401F80F8U, 0x8U, 0x401F878CU, 0x1U, 0x401F82E8U + +#define IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x401F80FCU, 0x0U, 0x401F83F8U, 0x1U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0 0x401F80FCU, 0x1U, 0x401F857CU, 0x1U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x401F80FCU, 0x2U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x401F80FCU, 0x3U, 0x401F84CCU, 0x1U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x401F80FCU, 0x4U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x401F80FCU, 0x5U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x401F80FCU, 0x6U, 0x401F85D8U, 0x2U, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x401F80FCU, 0x7U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_ENET2_1588_EVENT0_OUT 0x401F80FCU, 0x8U, 0, 0, 0x401F82ECU +#define IOMUXC_GPIO_AD_B1_00_FLEXIO3_FLEXIO00 0x401F80FCU, 0x9U, 0, 0, 0x401F82ECU + +#define IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x401F8100U, 0x0U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1 0x401F8100U, 0x1U, 0x401F8580U, 0x0U, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x401F8100U, 0x2U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x401F8100U, 0x3U, 0x401F84D0U, 0x1U, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x401F8100U, 0x4U, 0x401F83FCU, 0x2U, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x401F8100U, 0x5U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x401F8100U, 0x6U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x401F8100U, 0x7U, 0, 0, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_ENET2_1588_EVENT0_IN 0x401F8100U, 0x8U, 0x401F8724U, 0x0U, 0x401F82F0U +#define IOMUXC_GPIO_AD_B1_01_FLEXIO3_FLEXIO01 0x401F8100U, 0x9U, 0, 0, 0x401F82F0U + +#define IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x401F8104U, 0x0U, 0x401F83F4U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2 0x401F8104U, 0x1U, 0x401F8584U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_LPUART2_TX 0x401F8104U, 0x2U, 0x401F8530U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x401F8104U, 0x3U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x401F8104U, 0x4U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x401F8104U, 0x5U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x401F8104U, 0x6U, 0x401F85D4U, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x401F8104U, 0x7U, 0, 0, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_GPT2_CLK 0x401F8104U, 0x8U, 0x401F876CU, 0x1U, 0x401F82F4U +#define IOMUXC_GPIO_AD_B1_02_FLEXIO3_FLEXIO02 0x401F8104U, 0x9U, 0, 0, 0x401F82F4U + +#define IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x401F8108U, 0x0U, 0x401F85D0U, 0x1U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3 0x401F8108U, 0x1U, 0x401F8588U, 0x1U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_LPUART2_RX 0x401F8108U, 0x2U, 0x401F852CU, 0x1U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x401F8108U, 0x3U, 0x401F85C8U, 0x0U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x401F8108U, 0x4U, 0, 0, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x401F8108U, 0x5U, 0, 0, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x401F8108U, 0x6U, 0x401F85E0U, 0x0U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x401F8108U, 0x7U, 0, 0, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_GPT2_CAPTURE1 0x401F8108U, 0x8U, 0x401F8764U, 0x1U, 0x401F82F8U +#define IOMUXC_GPIO_AD_B1_03_FLEXIO3_FLEXIO03 0x401F8108U, 0x9U, 0, 0, 0x401F82F8U + +#define IOMUXC_GPIO_AD_B1_04_FLEXSPIB_DATA03 0x401F810CU, 0x0U, 0x401F84C4U, 0x1U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x401F810CU, 0x1U, 0, 0, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x401F810CU, 0x2U, 0x401F8534U, 0x1U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x401F810CU, 0x3U, 0, 0, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x401F810CU, 0x4U, 0x401F8424U, 0x0U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x401F810CU, 0x5U, 0, 0, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x401F810CU, 0x6U, 0x401F85E8U, 0x1U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x401F810CU, 0x7U, 0, 0, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_GPT2_CAPTURE2 0x401F810CU, 0x8U, 0x401F8768U, 0x1U, 0x401F82FCU +#define IOMUXC_GPIO_AD_B1_04_FLEXIO3_FLEXIO04 0x401F810CU, 0x9U, 0, 0, 0x401F82FCU + +#define IOMUXC_GPIO_AD_B1_05_FLEXSPIB_DATA02 0x401F8110U, 0x0U, 0x401F84C0U, 0x1U, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x401F8110U, 0x1U, 0x401F8430U, 0x0U, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x401F8110U, 0x2U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x401F8110U, 0x3U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x401F8110U, 0x4U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x401F8110U, 0x5U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x401F8110U, 0x6U, 0x401F85ECU, 0x1U, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x401F8110U, 0x7U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_GPT2_COMPARE1 0x401F8110U, 0x8U, 0, 0, 0x401F8300U +#define IOMUXC_GPIO_AD_B1_05_FLEXIO3_FLEXIO05 0x401F8110U, 0x9U, 0, 0, 0x401F8300U + +#define IOMUXC_GPIO_AD_B1_06_FLEXSPIB_DATA01 0x401F8114U, 0x0U, 0x401F84BCU, 0x1U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x401F8114U, 0x1U, 0x401F84E0U, 0x2U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_LPUART3_TX 0x401F8114U, 0x2U, 0x401F853CU, 0x0U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x401F8114U, 0x3U, 0, 0, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x401F8114U, 0x4U, 0x401F8428U, 0x1U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x401F8114U, 0x5U, 0, 0, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x401F8114U, 0x6U, 0x401F85F0U, 0x1U, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x401F8114U, 0x7U, 0, 0, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_GPT2_COMPARE2 0x401F8114U, 0x8U, 0, 0, 0x401F8304U +#define IOMUXC_GPIO_AD_B1_06_FLEXIO3_FLEXIO06 0x401F8114U, 0x9U, 0, 0, 0x401F8304U + +#define IOMUXC_GPIO_AD_B1_07_FLEXSPIB_DATA00 0x401F8118U, 0x0U, 0x401F84B8U, 0x1U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x401F8118U, 0x1U, 0x401F84DCU, 0x2U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_LPUART3_RX 0x401F8118U, 0x2U, 0x401F8538U, 0x0U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x401F8118U, 0x3U, 0, 0, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x401F8118U, 0x4U, 0x401F8420U, 0x1U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x401F8118U, 0x5U, 0, 0, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x401F8118U, 0x6U, 0x401F85F4U, 0x1U, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x401F8118U, 0x7U, 0, 0, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_GPT2_COMPARE3 0x401F8118U, 0x8U, 0, 0, 0x401F8308U +#define IOMUXC_GPIO_AD_B1_07_FLEXIO3_FLEXIO07 0x401F8118U, 0x9U, 0, 0, 0x401F8308U + +#define IOMUXC_GPIO_AD_B1_08_FLEXSPIA_SS1_B 0x401F811CU, 0x0U, 0, 0, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWMA00 0x401F811CU, 0x1U, 0x401F8494U, 0x1U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x401F811CU, 0x2U, 0, 0, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x401F811CU, 0x3U, 0x401F83FCU, 0x3U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x401F811CU, 0x4U, 0x401F841CU, 0x0U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x401F811CU, 0x5U, 0, 0, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x401F811CU, 0x6U, 0x401F85E4U, 0x1U, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x401F811CU, 0x7U, 0, 0, 0x401F830CU +#define IOMUXC_GPIO_AD_B1_08_FLEXIO3_FLEXIO08 0x401F811CU, 0x9U, 0, 0, 0x401F830CU + +#define IOMUXC_GPIO_AD_B1_09_FLEXSPIA_DQS 0x401F8120U, 0x0U, 0x401F84A4U, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWMA01 0x401F8120U, 0x1U, 0x401F8498U, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x401F8120U, 0x2U, 0x401F844CU, 0x2U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x401F8120U, 0x3U, 0x401F858CU, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x401F8120U, 0x4U, 0x401F8418U, 0x0U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x401F8120U, 0x5U, 0, 0, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x401F8120U, 0x6U, 0x401F85DCU, 0x1U, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x401F8120U, 0x7U, 0, 0, 0x401F8310U +#define IOMUXC_GPIO_AD_B1_09_FLEXIO3_FLEXIO09 0x401F8120U, 0x9U, 0, 0, 0x401F8310U + +#define IOMUXC_GPIO_AD_B1_10_FLEXSPIA_DATA03 0x401F8124U, 0x0U, 0x401F84B4U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x401F8124U, 0x1U, 0, 0, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_LPUART8_TX 0x401F8124U, 0x2U, 0x401F8564U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x401F8124U, 0x3U, 0x401F85A4U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x401F8124U, 0x4U, 0x401F8414U, 0x0U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x401F8124U, 0x5U, 0, 0, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x401F8124U, 0x6U, 0x401F8608U, 0x1U, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x401F8124U, 0x7U, 0, 0, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_ENET2_1588_EVENT1_OUT 0x401F8124U, 0x8U, 0, 0, 0x401F8314U +#define IOMUXC_GPIO_AD_B1_10_FLEXIO3_FLEXIO10 0x401F8124U, 0x9U, 0, 0, 0x401F8314U + +#define IOMUXC_GPIO_AD_B1_11_FLEXSPIA_DATA02 0x401F8128U, 0x0U, 0x401F84B0U, 0x1U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x401F8128U, 0x1U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_LPUART8_RX 0x401F8128U, 0x2U, 0x401F8560U, 0x1U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x401F8128U, 0x3U, 0x401F8590U, 0x1U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x401F8128U, 0x4U, 0x401F8410U, 0x0U, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x401F8128U, 0x5U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x401F8128U, 0x6U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x401F8128U, 0x7U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_ENET2_1588_EVENT1_IN 0x401F8128U, 0x8U, 0, 0, 0x401F8318U +#define IOMUXC_GPIO_AD_B1_11_FLEXIO3_FLEXIO11 0x401F8128U, 0x9U, 0, 0, 0x401F8318U + +#define IOMUXC_GPIO_AD_B1_12_FLEXSPIA_DATA01 0x401F812CU, 0x0U, 0x401F84ACU, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_ACMP_OUT00 0x401F812CU, 0x1U, 0, 0, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x401F812CU, 0x2U, 0x401F850CU, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x401F812CU, 0x3U, 0x401F8594U, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x401F812CU, 0x4U, 0x401F840CU, 0x0U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x401F812CU, 0x5U, 0, 0, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x401F812CU, 0x6U, 0x401F85F8U, 0x1U, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x401F812CU, 0x7U, 0, 0, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_ENET2_1588_EVENT2_OUT 0x401F812CU, 0x8U, 0, 0, 0x401F831CU +#define IOMUXC_GPIO_AD_B1_12_FLEXIO3_FLEXIO12 0x401F812CU, 0x9U, 0, 0, 0x401F831CU + +#define IOMUXC_GPIO_AD_B1_13_FLEXSPIA_DATA00 0x401F8130U, 0x0U, 0x401F84A8U, 0x1U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_ACMP_OUT01 0x401F8130U, 0x1U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x401F8130U, 0x2U, 0x401F8514U, 0x1U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x401F8130U, 0x3U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x401F8130U, 0x4U, 0x401F8408U, 0x0U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x401F8130U, 0x5U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x401F8130U, 0x6U, 0x401F85FCU, 0x1U, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x401F8130U, 0x7U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_ENET2_1588_EVENT2_IN 0x401F8130U, 0x8U, 0, 0, 0x401F8320U +#define IOMUXC_GPIO_AD_B1_13_FLEXIO3_FLEXIO13 0x401F8130U, 0x9U, 0, 0, 0x401F8320U + +#define IOMUXC_GPIO_AD_B1_14_FLEXSPIA_SCLK 0x401F8134U, 0x0U, 0x401F84C8U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_ACMP_OUT02 0x401F8134U, 0x1U, 0, 0, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x401F8134U, 0x2U, 0x401F8518U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x401F8134U, 0x3U, 0x401F85A8U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x401F8134U, 0x4U, 0x401F8404U, 0x0U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x401F8134U, 0x5U, 0, 0, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x401F8134U, 0x6U, 0x401F8600U, 0x1U, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x401F8134U, 0x7U, 0, 0, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_ENET2_1588_EVENT3_OUT 0x401F8134U, 0x8U, 0, 0, 0x401F8324U +#define IOMUXC_GPIO_AD_B1_14_FLEXIO3_FLEXIO14 0x401F8134U, 0x9U, 0, 0, 0x401F8324U + +#define IOMUXC_GPIO_AD_B1_15_FLEXSPIA_SS0_B 0x401F8138U, 0x0U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_ACMP_OUT03 0x401F8138U, 0x1U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x401F8138U, 0x2U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x401F8138U, 0x3U, 0x401F85ACU, 0x1U, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x401F8138U, 0x4U, 0x401F8400U, 0x0U, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x401F8138U, 0x5U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x401F8138U, 0x6U, 0x401F8604U, 0x1U, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x401F8138U, 0x7U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_ENET2_1588_EVENT3_IN 0x401F8138U, 0x8U, 0, 0, 0x401F8328U +#define IOMUXC_GPIO_AD_B1_15_FLEXIO3_FLEXIO15 0x401F8138U, 0x9U, 0, 0, 0x401F8328U + +#define IOMUXC_GPIO_B0_00_LCD_CLK 0x401F813CU, 0x0U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_QTIMER1_TIMER0 0x401F813CU, 0x1U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_MQS_RIGHT 0x401F813CU, 0x2U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x401F813CU, 0x3U, 0x401F851CU, 0x0U, 0x401F832CU +#define IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00 0x401F813CU, 0x4U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_GPIO2_IO00 0x401F813CU, 0x5U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_SEMC_CSX01 0x401F813CU, 0x6U, 0, 0, 0x401F832CU +#define IOMUXC_GPIO_B0_00_ENET2_MDC 0x401F813CU, 0x8U, 0, 0, 0x401F832CU + +#define IOMUXC_GPIO_B0_01_LCD_ENABLE 0x401F8140U, 0x0U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_QTIMER1_TIMER1 0x401F8140U, 0x1U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_MQS_LEFT 0x401F8140U, 0x2U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x401F8140U, 0x3U, 0x401F8524U, 0x0U, 0x401F8330U +#define IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01 0x401F8140U, 0x4U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_GPIO2_IO01 0x401F8140U, 0x5U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_SEMC_CSX02 0x401F8140U, 0x6U, 0, 0, 0x401F8330U +#define IOMUXC_GPIO_B0_01_ENET2_MDIO 0x401F8140U, 0x8U, 0x401F8710U, 0x1U, 0x401F8330U + +#define IOMUXC_GPIO_B0_02_LCD_HSYNC 0x401F8144U, 0x0U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_QTIMER1_TIMER2 0x401F8144U, 0x1U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x401F8144U, 0x2U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x401F8144U, 0x3U, 0x401F8528U, 0x0U, 0x401F8334U +#define IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02 0x401F8144U, 0x4U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_GPIO2_IO02 0x401F8144U, 0x5U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_SEMC_CSX03 0x401F8144U, 0x6U, 0, 0, 0x401F8334U +#define IOMUXC_GPIO_B0_02_ENET2_1588_EVENT0_OUT 0x401F8144U, 0x8U, 0, 0, 0x401F8334U + +#define IOMUXC_GPIO_B0_03_LCD_VSYNC 0x401F8148U, 0x0U, 0, 0, 0x401F8338U +#define IOMUXC_GPIO_B0_03_QTIMER2_TIMER0 0x401F8148U, 0x1U, 0x401F856CU, 0x1U, 0x401F8338U +#define IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x401F8148U, 0x2U, 0x401F844CU, 0x3U, 0x401F8338U +#define IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x401F8148U, 0x3U, 0x401F8520U, 0x0U, 0x401F8338U +#define IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03 0x401F8148U, 0x4U, 0, 0, 0x401F8338U +#define IOMUXC_GPIO_B0_03_GPIO2_IO03 0x401F8148U, 0x5U, 0, 0, 0x401F8338U +#define IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x401F8148U, 0x6U, 0, 0, 0x401F8338U +#define IOMUXC_GPIO_B0_03_ENET2_1588_EVENT0_IN 0x401F8148U, 0x8U, 0x401F8724U, 0x1U, 0x401F8338U + +#define IOMUXC_GPIO_B0_04_LCD_DATA00 0x401F814CU, 0x0U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 0x401F814CU, 0x1U, 0x401F8570U, 0x1U, 0x401F833CU +#define IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x401F814CU, 0x2U, 0x401F84D4U, 0x1U, 0x401F833CU +#define IOMUXC_GPIO_B0_04_ARM_TRACE0 0x401F814CU, 0x3U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 0x401F814CU, 0x4U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_GPIO2_IO04 0x401F814CU, 0x5U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_SRC_BOOT_CFG00 0x401F814CU, 0x6U, 0, 0, 0x401F833CU +#define IOMUXC_GPIO_B0_04_ENET2_TDATA03 0x401F814CU, 0x8U, 0, 0, 0x401F833CU + +#define IOMUXC_GPIO_B0_05_LCD_DATA01 0x401F8150U, 0x0U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 0x401F8150U, 0x1U, 0x401F8574U, 0x1U, 0x401F8340U +#define IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x401F8150U, 0x2U, 0x401F84D8U, 0x1U, 0x401F8340U +#define IOMUXC_GPIO_B0_05_ARM_TRACE1 0x401F8150U, 0x3U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 0x401F8150U, 0x4U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_GPIO2_IO05 0x401F8150U, 0x5U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_SRC_BOOT_CFG01 0x401F8150U, 0x6U, 0, 0, 0x401F8340U +#define IOMUXC_GPIO_B0_05_ENET2_TDATA02 0x401F8150U, 0x8U, 0, 0, 0x401F8340U + +#define IOMUXC_GPIO_B0_06_LCD_DATA02 0x401F8154U, 0x0U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 0x401F8154U, 0x1U, 0x401F857CU, 0x2U, 0x401F8344U +#define IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA00 0x401F8154U, 0x2U, 0x401F8478U, 0x1U, 0x401F8344U +#define IOMUXC_GPIO_B0_06_ARM_TRACE2 0x401F8154U, 0x3U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 0x401F8154U, 0x4U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_GPIO2_IO06 0x401F8154U, 0x5U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_SRC_BOOT_CFG02 0x401F8154U, 0x6U, 0, 0, 0x401F8344U +#define IOMUXC_GPIO_B0_06_ENET2_RX_CLK 0x401F8154U, 0x8U, 0, 0, 0x401F8344U + +#define IOMUXC_GPIO_B0_07_LCD_DATA03 0x401F8158U, 0x0U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 0x401F8158U, 0x1U, 0x401F8580U, 0x2U, 0x401F8348U +#define IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB00 0x401F8158U, 0x2U, 0x401F8488U, 0x1U, 0x401F8348U +#define IOMUXC_GPIO_B0_07_ARM_TRACE3 0x401F8158U, 0x3U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 0x401F8158U, 0x4U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_GPIO2_IO07 0x401F8158U, 0x5U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_SRC_BOOT_CFG03 0x401F8158U, 0x6U, 0, 0, 0x401F8348U +#define IOMUXC_GPIO_B0_07_ENET2_TX_ER 0x401F8158U, 0x8U, 0, 0, 0x401F8348U + +#define IOMUXC_GPIO_B0_08_LCD_DATA04 0x401F815CU, 0x0U, 0, 0, 0x401F834CU +#define IOMUXC_GPIO_B0_08_QTIMER3_TIMER2 0x401F815CU, 0x1U, 0x401F8584U, 0x2U, 0x401F834CU +#define IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA01 0x401F815CU, 0x2U, 0x401F847CU, 0x1U, 0x401F834CU +#define IOMUXC_GPIO_B0_08_LPUART3_TX 0x401F815CU, 0x3U, 0x401F853CU, 0x2U, 0x401F834CU +#define IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08 0x401F815CU, 0x4U, 0, 0, 0x401F834CU +#define IOMUXC_GPIO_B0_08_GPIO2_IO08 0x401F815CU, 0x5U, 0, 0, 0x401F834CU +#define IOMUXC_GPIO_B0_08_SRC_BOOT_CFG04 0x401F815CU, 0x6U, 0, 0, 0x401F834CU +#define IOMUXC_GPIO_B0_08_ENET2_RDATA03 0x401F815CU, 0x8U, 0, 0, 0x401F834CU + +#define IOMUXC_GPIO_B0_09_LCD_DATA05 0x401F8160U, 0x0U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_QTIMER4_TIMER0 0x401F8160U, 0x1U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB01 0x401F8160U, 0x2U, 0x401F848CU, 0x1U, 0x401F8350U +#define IOMUXC_GPIO_B0_09_LPUART3_RX 0x401F8160U, 0x3U, 0x401F8538U, 0x2U, 0x401F8350U +#define IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09 0x401F8160U, 0x4U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_GPIO2_IO09 0x401F8160U, 0x5U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_SRC_BOOT_CFG05 0x401F8160U, 0x6U, 0, 0, 0x401F8350U +#define IOMUXC_GPIO_B0_09_ENET2_RDATA02 0x401F8160U, 0x8U, 0, 0, 0x401F8350U + +#define IOMUXC_GPIO_B0_10_LCD_DATA06 0x401F8164U, 0x0U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_QTIMER4_TIMER1 0x401F8164U, 0x1U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA02 0x401F8164U, 0x2U, 0x401F8480U, 0x1U, 0x401F8354U +#define IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x401F8164U, 0x3U, 0x401F8598U, 0x1U, 0x401F8354U +#define IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10 0x401F8164U, 0x4U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_GPIO2_IO10 0x401F8164U, 0x5U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_SRC_BOOT_CFG06 0x401F8164U, 0x6U, 0, 0, 0x401F8354U +#define IOMUXC_GPIO_B0_10_ENET2_CRS 0x401F8164U, 0x8U, 0, 0, 0x401F8354U + +#define IOMUXC_GPIO_B0_11_LCD_DATA07 0x401F8168U, 0x0U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_QTIMER4_TIMER2 0x401F8168U, 0x1U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB02 0x401F8168U, 0x2U, 0x401F8490U, 0x1U, 0x401F8358U +#define IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x401F8168U, 0x3U, 0x401F859CU, 0x1U, 0x401F8358U +#define IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11 0x401F8168U, 0x4U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_GPIO2_IO11 0x401F8168U, 0x5U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_SRC_BOOT_CFG07 0x401F8168U, 0x6U, 0, 0, 0x401F8358U +#define IOMUXC_GPIO_B0_11_ENET2_COL 0x401F8168U, 0x8U, 0, 0, 0x401F8358U + +#define IOMUXC_GPIO_B0_12_LCD_DATA08 0x401F816CU, 0x0U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_XBAR1_INOUT10 0x401F816CU, 0x1U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x401F816CU, 0x2U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x401F816CU, 0x3U, 0x401F85A0U, 0x1U, 0x401F835CU +#define IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 0x401F816CU, 0x4U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_GPIO2_IO12 0x401F816CU, 0x5U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_SRC_BOOT_CFG08 0x401F816CU, 0x6U, 0, 0, 0x401F835CU +#define IOMUXC_GPIO_B0_12_ENET2_TDATA00 0x401F816CU, 0x8U, 0, 0, 0x401F835CU + +#define IOMUXC_GPIO_B0_13_LCD_DATA09 0x401F8170U, 0x0U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_XBAR1_INOUT11 0x401F8170U, 0x1U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x401F8170U, 0x2U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_SAI1_MCLK 0x401F8170U, 0x3U, 0x401F858CU, 0x2U, 0x401F8360U +#define IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 0x401F8170U, 0x4U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_GPIO2_IO13 0x401F8170U, 0x5U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_SRC_BOOT_CFG09 0x401F8170U, 0x6U, 0, 0, 0x401F8360U +#define IOMUXC_GPIO_B0_13_ENET2_TDATA01 0x401F8170U, 0x8U, 0, 0, 0x401F8360U + +#define IOMUXC_GPIO_B0_14_LCD_DATA10 0x401F8174U, 0x0U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_XBAR1_INOUT12 0x401F8174U, 0x1U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_ARM_TXEV 0x401F8174U, 0x2U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x401F8174U, 0x3U, 0x401F85A4U, 0x2U, 0x401F8364U +#define IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14 0x401F8174U, 0x4U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_GPIO2_IO14 0x401F8174U, 0x5U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_SRC_BOOT_CFG10 0x401F8174U, 0x6U, 0, 0, 0x401F8364U +#define IOMUXC_GPIO_B0_14_ENET2_TX_EN 0x401F8174U, 0x8U, 0, 0, 0x401F8364U + +#define IOMUXC_GPIO_B0_15_LCD_DATA11 0x401F8178U, 0x0U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_XBAR1_INOUT13 0x401F8178U, 0x1U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_ARM_RXEV 0x401F8178U, 0x2U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x401F8178U, 0x3U, 0x401F8590U, 0x2U, 0x401F8368U +#define IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15 0x401F8178U, 0x4U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_GPIO2_IO15 0x401F8178U, 0x5U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_SRC_BOOT_CFG11 0x401F8178U, 0x6U, 0, 0, 0x401F8368U +#define IOMUXC_GPIO_B0_15_ENET2_TX_CLK 0x401F8178U, 0x8U, 0x401F8728U, 0x2U, 0x401F8368U +#define IOMUXC_GPIO_B0_15_ENET2_REF_CLK2 0x401F8178U, 0x9U, 0x401F870CU, 0x2U, 0x401F8368U + +#define IOMUXC_GPIO_B1_00_LCD_DATA12 0x401F817CU, 0x0U, 0, 0, 0x401F836CU +#define IOMUXC_GPIO_B1_00_XBAR1_INOUT14 0x401F817CU, 0x1U, 0x401F8644U, 0x1U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_LPUART4_TX 0x401F817CU, 0x2U, 0x401F8544U, 0x2U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x401F817CU, 0x3U, 0x401F8594U, 0x2U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16 0x401F817CU, 0x4U, 0, 0, 0x401F836CU +#define IOMUXC_GPIO_B1_00_GPIO2_IO16 0x401F817CU, 0x5U, 0, 0, 0x401F836CU +#define IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA03 0x401F817CU, 0x6U, 0x401F8454U, 0x4U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_ENET2_RX_ER 0x401F817CU, 0x8U, 0x401F8720U, 0x2U, 0x401F836CU +#define IOMUXC_GPIO_B1_00_FLEXIO3_FLEXIO16 0x401F817CU, 0x9U, 0, 0, 0x401F836CU + +#define IOMUXC_GPIO_B1_01_LCD_DATA13 0x401F8180U, 0x0U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_XBAR1_INOUT15 0x401F8180U, 0x1U, 0x401F8648U, 0x1U, 0x401F8370U +#define IOMUXC_GPIO_B1_01_LPUART4_RX 0x401F8180U, 0x2U, 0x401F8540U, 0x2U, 0x401F8370U +#define IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x401F8180U, 0x3U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17 0x401F8180U, 0x4U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_GPIO2_IO17 0x401F8180U, 0x5U, 0, 0, 0x401F8370U +#define IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB03 0x401F8180U, 0x6U, 0x401F8464U, 0x4U, 0x401F8370U +#define IOMUXC_GPIO_B1_01_ENET2_RDATA00 0x401F8180U, 0x8U, 0x401F8714U, 0x2U, 0x401F8370U +#define IOMUXC_GPIO_B1_01_FLEXIO3_FLEXIO17 0x401F8180U, 0x9U, 0, 0, 0x401F8370U + +#define IOMUXC_GPIO_B1_02_LCD_DATA14 0x401F8184U, 0x0U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_XBAR1_INOUT16 0x401F8184U, 0x1U, 0x401F864CU, 0x1U, 0x401F8374U +#define IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x401F8184U, 0x2U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x401F8184U, 0x3U, 0x401F85A8U, 0x2U, 0x401F8374U +#define IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18 0x401F8184U, 0x4U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_GPIO2_IO18 0x401F8184U, 0x5U, 0, 0, 0x401F8374U +#define IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA03 0x401F8184U, 0x6U, 0x401F8474U, 0x4U, 0x401F8374U +#define IOMUXC_GPIO_B1_02_ENET2_RDATA01 0x401F8184U, 0x8U, 0x401F8718U, 0x2U, 0x401F8374U +#define IOMUXC_GPIO_B1_02_FLEXIO3_FLEXIO18 0x401F8184U, 0x9U, 0, 0, 0x401F8374U + +#define IOMUXC_GPIO_B1_03_LCD_DATA15 0x401F8188U, 0x0U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_XBAR1_INOUT17 0x401F8188U, 0x1U, 0x401F862CU, 0x3U, 0x401F8378U +#define IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x401F8188U, 0x2U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x401F8188U, 0x3U, 0x401F85ACU, 0x2U, 0x401F8378U +#define IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19 0x401F8188U, 0x4U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_GPIO2_IO19 0x401F8188U, 0x5U, 0, 0, 0x401F8378U +#define IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB03 0x401F8188U, 0x6U, 0x401F8484U, 0x3U, 0x401F8378U +#define IOMUXC_GPIO_B1_03_ENET2_RX_EN 0x401F8188U, 0x8U, 0x401F871CU, 0x2U, 0x401F8378U +#define IOMUXC_GPIO_B1_03_FLEXIO3_FLEXIO19 0x401F8188U, 0x9U, 0, 0, 0x401F8378U + +#define IOMUXC_GPIO_B1_04_LCD_DATA16 0x401F818CU, 0x0U, 0, 0, 0x401F837CU +#define IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x401F818CU, 0x1U, 0x401F851CU, 0x1U, 0x401F837CU +#define IOMUXC_GPIO_B1_04_CSI_DATA15 0x401F818CU, 0x2U, 0, 0, 0x401F837CU +#define IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x401F818CU, 0x3U, 0x401F8434U, 0x1U, 0x401F837CU +#define IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 0x401F818CU, 0x4U, 0, 0, 0x401F837CU +#define IOMUXC_GPIO_B1_04_GPIO2_IO20 0x401F818CU, 0x5U, 0, 0, 0x401F837CU +#define IOMUXC_GPIO_B1_04_GPT1_CLK 0x401F818CU, 0x8U, 0x401F8760U, 0x1U, 0x401F837CU +#define IOMUXC_GPIO_B1_04_FLEXIO3_FLEXIO20 0x401F818CU, 0x9U, 0, 0, 0x401F837CU + +#define IOMUXC_GPIO_B1_05_LCD_DATA17 0x401F8190U, 0x0U, 0, 0, 0x401F8380U +#define IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x401F8190U, 0x1U, 0x401F8524U, 0x1U, 0x401F8380U +#define IOMUXC_GPIO_B1_05_CSI_DATA14 0x401F8190U, 0x2U, 0, 0, 0x401F8380U +#define IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x401F8190U, 0x3U, 0x401F8438U, 0x1U, 0x401F8380U +#define IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 0x401F8190U, 0x4U, 0, 0, 0x401F8380U +#define IOMUXC_GPIO_B1_05_GPIO2_IO21 0x401F8190U, 0x5U, 0, 0, 0x401F8380U +#define IOMUXC_GPIO_B1_05_GPT1_CAPTURE1 0x401F8190U, 0x8U, 0x401F8758U, 0x1U, 0x401F8380U +#define IOMUXC_GPIO_B1_05_FLEXIO3_FLEXIO21 0x401F8190U, 0x9U, 0, 0, 0x401F8380U + +#define IOMUXC_GPIO_B1_06_LCD_DATA18 0x401F8194U, 0x0U, 0, 0, 0x401F8384U +#define IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x401F8194U, 0x1U, 0x401F8528U, 0x1U, 0x401F8384U +#define IOMUXC_GPIO_B1_06_CSI_DATA13 0x401F8194U, 0x2U, 0, 0, 0x401F8384U +#define IOMUXC_GPIO_B1_06_ENET_RX_EN 0x401F8194U, 0x3U, 0x401F843CU, 0x1U, 0x401F8384U +#define IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 0x401F8194U, 0x4U, 0, 0, 0x401F8384U +#define IOMUXC_GPIO_B1_06_GPIO2_IO22 0x401F8194U, 0x5U, 0, 0, 0x401F8384U +#define IOMUXC_GPIO_B1_06_GPT1_CAPTURE2 0x401F8194U, 0x8U, 0x401F875CU, 0x1U, 0x401F8384U +#define IOMUXC_GPIO_B1_06_FLEXIO3_FLEXIO22 0x401F8194U, 0x9U, 0, 0, 0x401F8384U + +#define IOMUXC_GPIO_B1_07_LCD_DATA19 0x401F8198U, 0x0U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x401F8198U, 0x1U, 0x401F8520U, 0x1U, 0x401F8388U +#define IOMUXC_GPIO_B1_07_CSI_DATA12 0x401F8198U, 0x2U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x401F8198U, 0x3U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 0x401F8198U, 0x4U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_GPIO2_IO23 0x401F8198U, 0x5U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_GPT1_COMPARE1 0x401F8198U, 0x8U, 0, 0, 0x401F8388U +#define IOMUXC_GPIO_B1_07_FLEXIO3_FLEXIO23 0x401F8198U, 0x9U, 0, 0, 0x401F8388U + +#define IOMUXC_GPIO_B1_08_LCD_DATA20 0x401F819CU, 0x0U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 0x401F819CU, 0x1U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_CSI_DATA11 0x401F819CU, 0x2U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x401F819CU, 0x3U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24 0x401F819CU, 0x4U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_GPIO2_IO24 0x401F819CU, 0x5U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x401F819CU, 0x6U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_GPT1_COMPARE2 0x401F819CU, 0x8U, 0, 0, 0x401F838CU +#define IOMUXC_GPIO_B1_08_FLEXIO3_FLEXIO24 0x401F819CU, 0x9U, 0, 0, 0x401F838CU + +#define IOMUXC_GPIO_B1_09_LCD_DATA21 0x401F81A0U, 0x0U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_QTIMER2_TIMER3 0x401F81A0U, 0x1U, 0x401F8578U, 0x1U, 0x401F8390U +#define IOMUXC_GPIO_B1_09_CSI_DATA10 0x401F81A0U, 0x2U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_ENET_TX_EN 0x401F81A0U, 0x3U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25 0x401F81A0U, 0x4U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_GPIO2_IO25 0x401F81A0U, 0x5U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x401F81A0U, 0x6U, 0x401F8450U, 0x3U, 0x401F8390U +#define IOMUXC_GPIO_B1_09_GPT1_COMPARE3 0x401F81A0U, 0x8U, 0, 0, 0x401F8390U +#define IOMUXC_GPIO_B1_09_FLEXIO3_FLEXIO25 0x401F81A0U, 0x9U, 0, 0, 0x401F8390U + +#define IOMUXC_GPIO_B1_10_LCD_DATA22 0x401F81A4U, 0x0U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_QTIMER3_TIMER3 0x401F81A4U, 0x1U, 0x401F8588U, 0x2U, 0x401F8394U +#define IOMUXC_GPIO_B1_10_CSI_DATA00 0x401F81A4U, 0x2U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x401F81A4U, 0x3U, 0x401F8448U, 0x1U, 0x401F8394U +#define IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26 0x401F81A4U, 0x4U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_GPIO2_IO26 0x401F81A4U, 0x5U, 0, 0, 0x401F8394U +#define IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x401F81A4U, 0x6U, 0x401F842CU, 0x1U, 0x401F8394U +#define IOMUXC_GPIO_B1_10_FLEXIO3_FLEXIO26 0x401F81A4U, 0x9U, 0, 0, 0x401F8394U + +#define IOMUXC_GPIO_B1_11_LCD_DATA23 0x401F81A8U, 0x0U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_QTIMER4_TIMER3 0x401F81A8U, 0x1U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_CSI_DATA01 0x401F81A8U, 0x2U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_ENET_RX_ER 0x401F81A8U, 0x3U, 0x401F8440U, 0x1U, 0x401F8398U +#define IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27 0x401F81A8U, 0x4U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_GPIO2_IO27 0x401F81A8U, 0x5U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x401F81A8U, 0x6U, 0, 0, 0x401F8398U +#define IOMUXC_GPIO_B1_11_FLEXIO3_FLEXIO27 0x401F81A8U, 0x9U, 0, 0, 0x401F8398U + +#define IOMUXC_GPIO_B1_12_LPUART5_TX 0x401F81ACU, 0x1U, 0x401F854CU, 0x1U, 0x401F839CU +#define IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x401F81ACU, 0x2U, 0x401F8424U, 0x1U, 0x401F839CU +#define IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x401F81ACU, 0x3U, 0x401F8444U, 0x2U, 0x401F839CU +#define IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28 0x401F81ACU, 0x4U, 0, 0, 0x401F839CU +#define IOMUXC_GPIO_B1_12_GPIO2_IO28 0x401F81ACU, 0x5U, 0, 0, 0x401F839CU +#define IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x401F81ACU, 0x6U, 0x401F85D4U, 0x2U, 0x401F839CU +#define IOMUXC_GPIO_B1_12_FLEXIO3_FLEXIO28 0x401F81ACU, 0x9U, 0, 0, 0x401F839CU + +#define IOMUXC_GPIO_B1_13_WDOG1_B 0x401F81B0U, 0x0U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_LPUART5_RX 0x401F81B0U, 0x1U, 0x401F8548U, 0x1U, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_CSI_VSYNC 0x401F81B0U, 0x2U, 0x401F8428U, 0x2U, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x401F81B0U, 0x3U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29 0x401F81B0U, 0x4U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_GPIO2_IO29 0x401F81B0U, 0x5U, 0, 0, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_USDHC1_WP 0x401F81B0U, 0x6U, 0x401F85D8U, 0x3U, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_SEMC_DQS4 0x401F81B0U, 0x8U, 0x401F8788U, 0x3U, 0x401F83A0U +#define IOMUXC_GPIO_B1_13_FLEXIO3_FLEXIO29 0x401F81B0U, 0x9U, 0, 0, 0x401F83A0U + +#define IOMUXC_GPIO_B1_14_ENET_MDC 0x401F81B4U, 0x0U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA02 0x401F81B4U, 0x1U, 0x401F849CU, 0x1U, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_CSI_HSYNC 0x401F81B4U, 0x2U, 0x401F8420U, 0x2U, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_XBAR1_IN02 0x401F81B4U, 0x3U, 0x401F860CU, 0x1U, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30 0x401F81B4U, 0x4U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_GPIO2_IO30 0x401F81B4U, 0x5U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x401F81B4U, 0x6U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_ENET2_TDATA00 0x401F81B4U, 0x8U, 0, 0, 0x401F83A4U +#define IOMUXC_GPIO_B1_14_FLEXIO3_FLEXIO30 0x401F81B4U, 0x9U, 0, 0, 0x401F83A4U + +#define IOMUXC_GPIO_B1_15_ENET_MDIO 0x401F81B8U, 0x0U, 0x401F8430U, 0x2U, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA03 0x401F81B8U, 0x1U, 0x401F84A0U, 0x1U, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_CSI_MCLK 0x401F81B8U, 0x2U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_XBAR1_IN03 0x401F81B8U, 0x3U, 0x401F8610U, 0x1U, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31 0x401F81B8U, 0x4U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_GPIO2_IO31 0x401F81B8U, 0x5U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x401F81B8U, 0x6U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_ENET2_TDATA01 0x401F81B8U, 0x8U, 0, 0, 0x401F83A8U +#define IOMUXC_GPIO_B1_15_FLEXIO3_FLEXIO31 0x401F81B8U, 0x9U, 0, 0, 0x401F83A8U + +#define IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x401F81BCU, 0x0U, 0, 0, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA00 0x401F81BCU, 0x1U, 0x401F8458U, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x401F81BCU, 0x2U, 0x401F84DCU, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT04 0x401F81BCU, 0x3U, 0x401F8614U, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x401F81BCU, 0x4U, 0x401F84F0U, 0x1U, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x401F81BCU, 0x5U, 0, 0, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_FLEXSPIA_SS1_B 0x401F81BCU, 0x6U, 0, 0, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_ENET2_TX_EN 0x401F81BCU, 0x8U, 0, 0, 0x401F83ACU +#define IOMUXC_GPIO_SD_B0_00_SEMC_DQS4 0x401F81BCU, 0x9U, 0x401F8788U, 0x0U, 0x401F83ACU + +#define IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x401F81C0U, 0x0U, 0, 0, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB00 0x401F81C0U, 0x1U, 0x401F8468U, 0x1U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x401F81C0U, 0x2U, 0x401F84E0U, 0x1U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT05 0x401F81C0U, 0x3U, 0x401F8618U, 0x1U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x401F81C0U, 0x4U, 0x401F84ECU, 0x0U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x401F81C0U, 0x5U, 0, 0, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_FLEXSPIB_SS1_B 0x401F81C0U, 0x6U, 0, 0, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_ENET2_TX_CLK 0x401F81C0U, 0x8U, 0x401F8728U, 0x1U, 0x401F83B0U +#define IOMUXC_GPIO_SD_B0_01_ENET2_REF_CLK2 0x401F81C0U, 0x9U, 0x401F870CU, 0x1U, 0x401F83B0U + +#define IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x401F81C4U, 0x0U, 0, 0, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA01 0x401F81C4U, 0x1U, 0x401F845CU, 0x1U, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x401F81C4U, 0x2U, 0, 0, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT06 0x401F81C4U, 0x3U, 0x401F861CU, 0x1U, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x401F81C4U, 0x4U, 0x401F84F8U, 0x1U, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x401F81C4U, 0x5U, 0, 0, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_ENET2_RX_ER 0x401F81C4U, 0x8U, 0x401F8720U, 0x1U, 0x401F83B4U +#define IOMUXC_GPIO_SD_B0_02_SEMC_CLK5 0x401F81C4U, 0x9U, 0, 0, 0x401F83B4U + +#define IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x401F81C8U, 0x0U, 0, 0, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB01 0x401F81C8U, 0x1U, 0x401F846CU, 0x1U, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x401F81C8U, 0x2U, 0, 0, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_XBAR1_INOUT07 0x401F81C8U, 0x3U, 0x401F8620U, 0x1U, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x401F81C8U, 0x4U, 0x401F84F4U, 0x1U, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x401F81C8U, 0x5U, 0, 0, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_ENET2_RDATA00 0x401F81C8U, 0x8U, 0x401F8714U, 0x1U, 0x401F83B8U +#define IOMUXC_GPIO_SD_B0_03_SEMC_CLK6 0x401F81C8U, 0x9U, 0, 0, 0x401F83B8U + +#define IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x401F81CCU, 0x0U, 0, 0, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA02 0x401F81CCU, 0x1U, 0x401F8460U, 0x1U, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_LPUART8_TX 0x401F81CCU, 0x2U, 0x401F8564U, 0x0U, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_XBAR1_INOUT08 0x401F81CCU, 0x3U, 0x401F8624U, 0x1U, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_FLEXSPIB_SS0_B 0x401F81CCU, 0x4U, 0, 0, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x401F81CCU, 0x5U, 0, 0, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x401F81CCU, 0x6U, 0, 0, 0x401F83BCU +#define IOMUXC_GPIO_SD_B0_04_ENET2_RDATA01 0x401F81CCU, 0x8U, 0x401F8718U, 0x1U, 0x401F83BCU + +#define IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x401F81D0U, 0x0U, 0, 0, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB02 0x401F81D0U, 0x1U, 0x401F8470U, 0x1U, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_LPUART8_RX 0x401F81D0U, 0x2U, 0x401F8560U, 0x0U, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_XBAR1_INOUT09 0x401F81D0U, 0x3U, 0x401F8628U, 0x1U, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_FLEXSPIB_DQS 0x401F81D0U, 0x4U, 0, 0, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x401F81D0U, 0x5U, 0, 0, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x401F81D0U, 0x6U, 0, 0, 0x401F83C0U +#define IOMUXC_GPIO_SD_B0_05_ENET2_RX_EN 0x401F81D0U, 0x8U, 0x401F871CU, 0x1U, 0x401F83C0U + +#define IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x401F81D4U, 0x0U, 0x401F85F4U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03 0x401F81D4U, 0x1U, 0x401F84C4U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA03 0x401F81D4U, 0x2U, 0x401F8454U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x401F81D4U, 0x3U, 0x401F8598U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_LPUART4_TX 0x401F81D4U, 0x4U, 0x401F8544U, 0x0U, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x401F81D4U, 0x5U, 0, 0, 0x401F83C4U +#define IOMUXC_GPIO_SD_B1_00_SAI3_RX_DATA 0x401F81D4U, 0x8U, 0x401F8778U, 0x1U, 0x401F83C4U + +#define IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x401F81D8U, 0x0U, 0x401F85F0U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02 0x401F81D8U, 0x1U, 0x401F84C0U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB03 0x401F81D8U, 0x2U, 0x401F8464U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x401F81D8U, 0x3U, 0x401F859CU, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_LPUART4_RX 0x401F81D8U, 0x4U, 0x401F8540U, 0x0U, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x401F81D8U, 0x5U, 0, 0, 0x401F83C8U +#define IOMUXC_GPIO_SD_B1_01_SAI3_TX_DATA 0x401F81D8U, 0x8U, 0, 0, 0x401F83C8U + +#define IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x401F81DCU, 0x0U, 0x401F85ECU, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01 0x401F81DCU, 0x1U, 0x401F84BCU, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA03 0x401F81DCU, 0x2U, 0x401F8474U, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x401F81DCU, 0x3U, 0x401F85A0U, 0x0U, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x401F81DCU, 0x4U, 0, 0, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x401F81DCU, 0x5U, 0, 0, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x401F81DCU, 0x6U, 0, 0, 0x401F83CCU +#define IOMUXC_GPIO_SD_B1_02_SAI3_TX_SYNC 0x401F81DCU, 0x8U, 0x401F8784U, 0x1U, 0x401F83CCU + +#define IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x401F81E0U, 0x0U, 0x401F85E8U, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00 0x401F81E0U, 0x1U, 0x401F84B8U, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB03 0x401F81E0U, 0x2U, 0x401F8484U, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x401F81E0U, 0x3U, 0x401F858CU, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x401F81E0U, 0x4U, 0x401F844CU, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x401F81E0U, 0x5U, 0, 0, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x401F81E0U, 0x6U, 0x401F83FCU, 0x0U, 0x401F83D0U +#define IOMUXC_GPIO_SD_B1_03_SAI3_TX_BCLK 0x401F81E0U, 0x8U, 0x401F8780U, 0x1U, 0x401F83D0U + +#define IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x401F81E4U, 0x0U, 0x401F85DCU, 0x0U, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK 0x401F81E4U, 0x1U, 0, 0, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x401F81E4U, 0x2U, 0x401F84CCU, 0x0U, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x401F81E4U, 0x3U, 0x401F85A4U, 0x0U, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_FLEXSPIA_SS1_B 0x401F81E4U, 0x4U, 0, 0, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x401F81E4U, 0x5U, 0, 0, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x401F81E4U, 0x6U, 0, 0, 0x401F83D4U +#define IOMUXC_GPIO_SD_B1_04_SAI3_MCLK 0x401F81E4U, 0x8U, 0x401F8770U, 0x1U, 0x401F83D4U + +#define IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x401F81E8U, 0x0U, 0x401F85E4U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS 0x401F81E8U, 0x1U, 0x401F84A4U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x401F81E8U, 0x2U, 0x401F84D0U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x401F81E8U, 0x3U, 0x401F8590U, 0x0U, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_FLEXSPIB_SS0_B 0x401F81E8U, 0x4U, 0, 0, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x401F81E8U, 0x5U, 0, 0, 0x401F83D8U +#define IOMUXC_GPIO_SD_B1_05_SAI3_RX_SYNC 0x401F81E8U, 0x8U, 0x401F877CU, 0x1U, 0x401F83D8U + +#define IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x401F81ECU, 0x0U, 0, 0, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B 0x401F81ECU, 0x1U, 0, 0, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x401F81ECU, 0x2U, 0, 0, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x401F81ECU, 0x3U, 0x401F8594U, 0x0U, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x401F81ECU, 0x4U, 0x401F84FCU, 0x0U, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x401F81ECU, 0x5U, 0, 0, 0x401F83DCU +#define IOMUXC_GPIO_SD_B1_06_SAI3_RX_BCLK 0x401F81ECU, 0x8U, 0x401F8774U, 0x1U, 0x401F83DCU + +#define IOMUXC_GPIO_SD_B1_07_SEMC_CSX01 0x401F81F0U, 0x0U, 0, 0, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK 0x401F81F0U, 0x1U, 0x401F84C8U, 0x0U, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x401F81F0U, 0x2U, 0, 0, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x401F81F0U, 0x3U, 0, 0, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x401F81F0U, 0x4U, 0x401F8500U, 0x0U, 0x401F83E0U +#define IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x401F81F0U, 0x5U, 0, 0, 0x401F83E0U + +#define IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x401F81F4U, 0x0U, 0x401F85F8U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00 0x401F81F4U, 0x1U, 0x401F84A8U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_LPUART7_TX 0x401F81F4U, 0x2U, 0x401F855CU, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK 0x401F81F4U, 0x3U, 0x401F85A8U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0 0x401F81F4U, 0x4U, 0x401F8508U, 0x0U, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x401F81F4U, 0x5U, 0, 0, 0x401F83E4U +#define IOMUXC_GPIO_SD_B1_08_SEMC_CSX02 0x401F81F4U, 0x6U, 0, 0, 0x401F83E4U + +#define IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x401F81F8U, 0x0U, 0x401F85FCU, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01 0x401F81F8U, 0x1U, 0x401F84ACU, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_LPUART7_RX 0x401F81F8U, 0x2U, 0x401F8558U, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x401F81F8U, 0x3U, 0x401F85ACU, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x401F81F8U, 0x4U, 0x401F8504U, 0x0U, 0x401F83E8U +#define IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x401F81F8U, 0x5U, 0, 0, 0x401F83E8U + +#define IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x401F81FCU, 0x0U, 0x401F8600U, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02 0x401F81FCU, 0x1U, 0x401F84B0U, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_LPUART2_RX 0x401F81FCU, 0x2U, 0x401F852CU, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x401F81FCU, 0x3U, 0x401F84D8U, 0x0U, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x401F81FCU, 0x4U, 0, 0, 0x401F83ECU +#define IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x401F81FCU, 0x5U, 0, 0, 0x401F83ECU + +#define IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x401F8200U, 0x0U, 0x401F8604U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03 0x401F8200U, 0x1U, 0x401F84B4U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_LPUART2_TX 0x401F8200U, 0x2U, 0x401F8530U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x401F8200U, 0x3U, 0x401F84D4U, 0x0U, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8200U, 0x4U, 0, 0, 0x401F83F0U +#define IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x401F8200U, 0x5U, 0, 0, 0x401F83F0U + +#define IOMUXC_GPIO_SPI_B0_00 0x401F865CU, 0, 0, 0, 0x401F86B4U + +#define IOMUXC_GPIO_SPI_B0_01_FLEXSPI2_B_SCLK 0x401F8660U, 0x0U, 0x401F8754U, 0x1U, 0x401F86B8U + +#define IOMUXC_GPIO_SPI_B0_02_FLEXSPI2_A_DATA00 0x401F8664U, 0x0U, 0x401F8730U, 0x2U, 0x401F86BCU + +#define IOMUXC_GPIO_SPI_B0_03_FLEXSPI2_B_DATA02 0x401F8668U, 0x0U, 0x401F8748U, 0x1U, 0x401F86C0U + +#define IOMUXC_GPIO_SPI_B0_04_FLEXSPI2_B_DATA03 0x401F866CU, 0x0U, 0x401F874CU, 0x1U, 0x401F86C4U + +#define IOMUXC_GPIO_SPI_B0_05_FLEXSPI2_A_SS0_B 0x401F8670U, 0x0U, 0, 0, 0x401F86C8U + +#define IOMUXC_GPIO_SPI_B0_06_FLEXSPI2_A_DATA02 0x401F8674U, 0x0U, 0x401F8738U, 0x2U, 0x401F86CCU + +#define IOMUXC_GPIO_SPI_B0_07_FLEXSPI2_B_DATA01 0x401F8678U, 0x0U, 0x401F8744U, 0x1U, 0x401F86D0U + +#define IOMUXC_GPIO_SPI_B0_08_FLEXSPI2_A_SCLK 0x401F867CU, 0x0U, 0x401F8750U, 0x2U, 0x401F86D4U + +#define IOMUXC_GPIO_SPI_B0_09_FLEXSPI2_A_DQS 0x401F8680U, 0x0U, 0x401F872CU, 0x2U, 0x401F86D8U + +#define IOMUXC_GPIO_SPI_B0_10_FLEXSPI2_A_DATA03 0x401F8684U, 0x0U, 0x401F873CU, 0x2U, 0x401F86DCU + +#define IOMUXC_GPIO_SPI_B0_11_FLEXSPI2_B_DATA00 0x401F8688U, 0x0U, 0x401F8740U, 0x1U, 0x401F86E0U + +#define IOMUXC_GPIO_SPI_B0_12_FLEXSPI2_A_DATA01 0x401F868CU, 0x0U, 0x401F8734U, 0x2U, 0x401F86E4U + +#define IOMUXC_GPIO_SPI_B0_13 0x401F8690U, 0, 0, 0, 0x401F86E8U + +#define IOMUXC_GPIO_SPI_B1_00_FLEXSPI2_A_DQS 0x401F8694U, 0x0U, 0x401F872CU, 0x0U, 0x401F86ECU + +#define IOMUXC_GPIO_SPI_B1_01_FLEXSPI2_A_DATA03 0x401F8698U, 0x0U, 0x401F873CU, 0x0U, 0x401F86F0U + +#define IOMUXC_GPIO_SPI_B1_02_FLEXSPI2_A_DATA02 0x401F869CU, 0x0U, 0x401F8738U, 0x0U, 0x401F86F4U + +#define IOMUXC_GPIO_SPI_B1_03_FLEXSPI2_A_DATA01 0x401F86A0U, 0x0U, 0x401F8734U, 0x0U, 0x401F86F8U + +#define IOMUXC_GPIO_SPI_B1_04_FLEXSPI2_A_DATA00 0x401F86A4U, 0x0U, 0x401F8730U, 0x0U, 0x401F86FCU + +#define IOMUXC_GPIO_SPI_B1_05_FLEXSPI2_A_SCLK 0x401F86A8U, 0x0U, 0x401F8750U, 0x0U, 0x401F8700U + +#define IOMUXC_GPIO_SPI_B1_06_FLEXSPI2_A_SS0_B 0x401F86ACU, 0x0U, 0, 0, 0x401F8704U + +#define IOMUXC_GPIO_SPI_B1_07 0x401F86B0U, 0, 0, 0, 0x401F8708U + +#define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U) +#define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U) + +typedef enum _iomuxc_gpr_mode +{ + kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK, + kIOMUXC_GPR_ENET1RefClkMode = IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK, + kIOMUXC_GPR_ENET2RefClkMode = IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, + kIOMUXC_GPR_USBExposureMode = IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK, + kIOMUXC_GPR_ENET1TxClkOutputDir = IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK, + kIOMUXC_GPR_ENET2TxClkOutputDir = IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK, + kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK, + kIOMUXC_GPR_SAI2MClkOutputDir = IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK, + kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK, + kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK, + kIOMUXC_GPR_ENETIpgClkOn = IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK, + kIOMUXC_GPR_AHBClockEnable = IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK, +} iomuxc_gpr_mode_t; + +typedef enum _iomuxc_gpr_saimclk +{ + kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT, + kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT, + kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT, +} iomuxc_gpr_saimclk_t; + +typedef enum _iomuxc_mqs_pwm_oversample_rate +{ + kIOMUXC_MqsPwmOverSampleRate32 = 0, /* MQS PWM over sampling rate 32. */ + kIOMUXC_MqsPwmOverSampleRate64 = 1 /* MQS PWM over sampling rate 64. */ +} iomuxc_mqs_pwm_oversample_rate_t; + +/*@}*/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the PTA6 as the lpuart0_tx: + * @code + * IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0); + * @endcode + * + * This is an example to set the PTA0 as GPIOA0: + * @code + * IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0); + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param inputOnfield Software input on field. + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister) + { + *((volatile uint32_t *)inputRegister) = inputDaisy; + } +} + +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS: + * @code + * IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U)) + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param configValue The pin config value. + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} + +/*! + * @brief Sets IOMUXC general configuration for some mode. + * + * @param base The IOMUXC GPR base address. + * @param mode The mode for setting. the mode is the logical OR of "iomuxc_gpr_mode" + * @param enable True enable false disable. + */ +static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable) +{ + mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK + | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK + | IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK + | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK + | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK); + + if (enable) + { + base->GPR1 |= mode; + } + else + { + base->GPR1 &= ~mode; + } +} + +/*! + * @brief Sets IOMUXC general configuration for SAI MCLK selection. + * + * @param base The IOMUXC GPR base address. + * @param mclk The SAI MCLK. + * @param clkSrc The clock source. Take refer to register setting details for the clock source in RM. + */ +static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gpr_saimclk_t mclk, uint8_t clkSrc) +{ + uint32_t gpr; + + if (mclk > kIOMUXC_GPR_SAI1MClk2Sel) + { + gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK << mclk); + base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr; + } + else + { + gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_LOWBITMASK << mclk); + base->GPR1 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr; + } +} + +/*! + * @brief Enters or exit MQS software reset. + * + * @param base The IOMUXC GPR base address. + * @param enable Enter or exit MQS software reset. + */ +static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enable) +{ + if (enable) + { + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + } + else + { + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; + } +} + + +/*! + * @brief Enables or disables MQS. + * + * @param base The IOMUXC GPR base address. + * @param enable Enable or disable the MQS. + */ +static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable) +{ + if (enable) + { + base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; + } + else + { + base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; + } +} + +/*! + * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk. + * + * @param base The IOMUXC GPR base address. + * @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t". + * @param divider The divider ratio control for mclk from hmclk. mclk freq = 1 /(divider + 1) * hmclk freq. + */ + +static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider) +{ + uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK); + + base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ + diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_kpp.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_kpp.c new file mode 100644 index 0000000000..a7c8b3475f --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_kpp.c @@ -0,0 +1,202 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_kpp.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.kpp" +#endif + +#define KPP_KEYPAD_SCAN_TIMES (3U) +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to SEMC clocks for each instance. */ +static const clock_ip_name_t s_kppClock[FSL_FEATURE_SOC_KPP_COUNT] = KPP_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to SEMC bases for each instance. */ +static KPP_Type *const s_kppBases[] = KPP_BASE_PTRS; + +/*! @brief Pointers to KPP IRQ number for each instance. */ +static const IRQn_Type s_kppIrqs[] = KPP_IRQS; +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t KPP_GetInstance(KPP_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_kppBases); instance++) + { + if (s_kppBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_kppBases)); + + return instance; +} +static void KPP_Mdelay(uint64_t tickets) +{ + while (tickets--) + { + __NOP(); + } +} + +/*! + * brief KPP initialize. + * This function ungates the KPP clock and initializes KPP. + * This function must be called before calling any other KPP driver functions. + * + * param base KPP peripheral base address. + * param configure The KPP configuration structure pointer. + */ +void KPP_Init(KPP_Type *base, kpp_config_t *configure) +{ + assert(configure); + + uint32_t instance = KPP_GetInstance(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Un-gate sdram controller clock. */ + CLOCK_EnableClock(s_kppClock[KPP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Clear all. */ + base->KPSR &= ~(KPP_KPSR_KRIE_MASK | KPP_KPSR_KDIE_MASK); + + /* Enable the keypad row and set the column strobe output to open drain. */ + base->KPCR = KPP_KPCR_KRE(configure->activeRow); + base->KPDR = KPP_KPDR_KCD((uint8_t) ~(configure->activeColumn)); + base->KPCR |= KPP_KPCR_KCO(configure->activeColumn); + + /* Set the input direction for row and output direction for column. */ + base->KDDR = KPP_KDDR_KCDD(configure->activeColumn) | KPP_KDDR_KRDD((uint8_t) ~(configure->activeRow)); + + /* Clear the status flag and enable the interrupt. */ + base->KPSR = KPP_KPSR_KPKR_MASK | KPP_KPSR_KPKD_MASK | KPP_KPSR_KDSC_MASK | configure->interrupt; + + if (configure->interrupt) + { + /* Enable at the Interrupt */ + EnableIRQ(s_kppIrqs[instance]); + } +} + +/*! + * brief Deinitializes the KPP module and gates the clock. + * This function gates the KPP clock. As a result, the KPP + * module doesn't work after calling this function. + * + * param base KPP peripheral base address. + */ +void KPP_Deinit(KPP_Type *base) +{ + /* Disable interrupts and disable all rows. */ + base->KPSR &= ~(KPP_KPSR_KRIE_MASK | KPP_KPSR_KDIE_MASK); + base->KPCR = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable KPP clock. */ + CLOCK_DisableClock(s_kppClock[KPP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Keypad press scanning. + * + * This function will scanning all columns and rows. so + * all scanning data will be stored in the data pointer. + * + * param base KPP peripheral base address. + * param data KPP key press scanning data. The data buffer should be prepared with + * length at least equal to KPP_KEYPAD_COLUMNNUM_MAX * KPP_KEYPAD_ROWNUM_MAX. + * the data pointer is recommended to be a array like uint8_t data[KPP_KEYPAD_COLUMNNUM_MAX]. + * for example the data[2] = 4, that means in column 1 row 2 has a key press event. + */ +void KPP_keyPressScanning(KPP_Type *base, uint8_t *data, uint32_t clockSrc_Hz) +{ + assert(data); + + uint16_t kppKCO = base->KPCR & KPP_KPCR_KCO_MASK; + uint8_t columIndex = 0; + uint8_t activeColumn = (base->KPCR & KPP_KPCR_KCO_MASK) >> KPP_KPCR_KCO_SHIFT; + uint8_t times; + uint8_t rowData[KPP_KEYPAD_SCAN_TIMES][KPP_KEYPAD_COLUMNNUM_MAX]; + bool press = false; + uint8_t column; + + /* Initialize row data to zero. */ + memset(&rowData[0][0], 0, sizeof(rowData)); + + /* Scanning. */ + /* Configure the column data to 1 according to column numbers. */ + base->KPDR = KPP_KPDR_KCD_MASK; + /* Configure column to totem pole for quick discharge of keypad capacitance. */ + base->KPCR &= (uint16_t)(((uint16_t)~kppKCO) | KPP_KPCR_KRE_MASK); + /* Recover. */ + base->KPCR |= kppKCO; + /* Three times scanning. */ + for (times = 0; times < KPP_KEYPAD_SCAN_TIMES; times++) + { + for (columIndex = 0; columIndex < KPP_KEYPAD_COLUMNNUM_MAX; columIndex++) + { + column = activeColumn & (1U << columIndex); + if (column) + { + /* Set the single column line to 0. */ + base->KPDR = KPP_KPDR_KCD(~(uint16_t)column); + /* Take 100us delays. */ + KPP_Mdelay(clockSrc_Hz / 10000000); + /* Read row data. */ + rowData[times][columIndex] = ~(base->KPDR & KPP_KPDR_KRD_MASK); + } + else + { + /* Read row data. */ + rowData[times][columIndex] = 0; + } + } + } + + /* Return all columns to 0 in preparation for standby mode. */ + base->KPDR &= ~KPP_KPDR_KCD_MASK; + + /* Check if three time scan data is the same. */ + for (columIndex = 0; columIndex < KPP_KEYPAD_COLUMNNUM_MAX; columIndex++) + { + if ((uint8_t)(rowData[0][columIndex] & rowData[1][columIndex]) & rowData[2][columIndex]) + { + press = true; + } + } + + if (press) + { + memcpy((void *)data, &rowData[0][0], sizeof(rowData[0])); + } + else + { + memset((void *)data, 0, sizeof(rowData[0])); + } +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_kpp.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_kpp.h new file mode 100644 index 0000000000..e462a38f63 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_kpp.h @@ -0,0 +1,179 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_KPP_H_ +#define _FSL_KPP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup kpp + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief KPP driver version 2.0.0. */ +#define FSL_KPP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#define KPP_KEYPAD_COLUMNNUM_MAX (8U) +#define KPP_KEYPAD_ROWNUM_MAX (8U) + +/*! @brief List of interrupts supported by the peripheral. This + * enumeration uses one-bot encoding to allow a logical OR of multiple + * members. Members usually map to interrupt enable bits in one or more + * peripheral registers. + */ +typedef enum _kpp_interrupt_enable +{ + kKPP_keyDepressInterrupt = KPP_KPSR_KDIE_MASK, /*!< Keypad depress interrupt source */ + kKPP_keyReleaseInterrupt = KPP_KPSR_KRIE_MASK /*!< Keypad release interrupt source */ +} kpp_interrupt_enable_t; + +/*! @brief Lists of KPP synchronize chain operation. */ +typedef enum _kpp_sync_operation +{ + kKPP_ClearKeyDepressSyncChain = KPP_KPSR_KDSC_MASK, /*!< Keypad depress interrupt status. */ + kKPP_SetKeyReleasesSyncChain = KPP_KPSR_KRSS_MASK, /*!< Keypad release interrupt status. */ +} kpp_sync_operation_t; + +/*! @brief Lists of KPP status. */ +typedef struct _kpp_config +{ + uint8_t activeRow; /*!< The row number: bit 7 ~ 0 represents the row 7 ~ 0. */ + uint8_t activeColumn; /*!< The column number: bit 7 ~ 0 represents the column 7 ~ 0. */ + uint16_t interrupt; /*!< KPP interrupt source. A logical OR of "kpp_interrupt_enable_t". */ +} kpp_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and De-initialization + * @{ + */ + +/*! + * @brief KPP initialize. + * This function ungates the KPP clock and initializes KPP. + * This function must be called before calling any other KPP driver functions. + * + * @param base KPP peripheral base address. + * @param configure The KPP configuration structure pointer. + */ +void KPP_Init(KPP_Type *base, kpp_config_t *configure); + +/*! + * @brief Deinitializes the KPP module and gates the clock. + * This function gates the KPP clock. As a result, the KPP + * module doesn't work after calling this function. + * + * @param base KPP peripheral base address. + */ +void KPP_Deinit(KPP_Type *base); + +/* @} */ + +/*! + * @name KPP Basic Operation + * @{ + */ + +/*! + * @brief Enable the interrupt. + * + * @param base KPP peripheral base address. + * @param mask KPP interrupts to enable. This is a logical OR of the + * enumeration :: kpp_interrupt_enable_t. + */ +static inline void KPP_EnableInterrupts(KPP_Type *base, uint16_t mask) +{ + uint16_t data = base->KPSR & ~(KPP_KPSR_KPKR_MASK | KPP_KPSR_KPKD_MASK); + base->KPSR = data | mask; +} + +/*! + * @brief Disable the interrupt. + * + * @param base KPP peripheral base address. + * @param mask KPP interrupts to disable. This is a logical OR of the + * enumeration :: kpp_interrupt_enable_t. + */ +static inline void KPP_DisableInterrupts(KPP_Type *base, uint16_t mask) +{ + base->KPSR &= ~(mask | KPP_KPSR_KPKR_MASK | KPP_KPSR_KPKD_MASK); +} + +/*! + * @brief Gets the KPP interrupt event status. + * + * @param base KPP peripheral base address. + * @return The status of the KPP. Application can use the enum type in the "kpp_interrupt_enable_t" + * to get the right status of the related event. + */ +static inline uint16_t KPP_GetStatusFlag(KPP_Type *base) +{ + return (base->KPSR & (KPP_KPSR_KPKR_MASK | KPP_KPSR_KPKD_MASK)) << KPP_KPSR_KDIE_SHIFT; +} + +/*! + * @brief Clears KPP status flag. + * + * @param base KPP peripheral base address. + * @param mask KPP mask to be cleared. This is a logical OR of the + * enumeration :: kpp_interrupt_enable_t. + */ +static inline void KPP_ClearStatusFlag(KPP_Type *base, uint16_t mask) +{ + base->KPSR |= (uint16_t)((mask) >> KPP_KPSR_KDIE_SHIFT); +} + +/*! + * @brief Set KPP synchronization chain. + * + * @param base KPP peripheral base address. + * @param mask KPP mask to be cleared. This is a logical OR of the + * enumeration :: kpp_sync_operation_t. + */ +static inline void KPP_SetSynchronizeChain(KPP_Type *base, uint16_t mask) +{ + uint16_t data = base->KPSR & (KPP_KPSR_KRSS_MASK | KPP_KPSR_KDSC_MASK | KPP_KPSR_KRIE_MASK | KPP_KPSR_KDIE_MASK); + base->KPSR = data | mask; +} + +/*! + * @brief Keypad press scanning. + * + * This function will scanning all columns and rows. so + * all scanning data will be stored in the data pointer. + * + * @param base KPP peripheral base address. + * @param data KPP key press scanning data. The data buffer should be prepared with + * length at least equal to KPP_KEYPAD_COLUMNNUM_MAX * KPP_KEYPAD_ROWNUM_MAX. + * the data pointer is recommended to be a array like uint8_t data[KPP_KEYPAD_COLUMNNUM_MAX]. + * for example the data[2] = 4, that means in column 1 row 2 has a key press event. + */ +void KPP_keyPressScanning(KPP_Type *base, uint8_t *data, uint32_t clockSrc_Hz); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_KPP_H_*/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpi2c.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpi2c.c new file mode 100644 index 0000000000..67b81fde79 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpi2c.c @@ -0,0 +1,2245 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpi2c.h" +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpi2c" +#endif + +/*! @brief Common sets of flags used by the driver. */ +enum _lpi2c_flag_constants +{ + /*! All flags which are cleared by the driver upon starting a transfer. */ + kMasterClearFlags = kLPI2C_MasterEndOfPacketFlag | kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | + kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | kLPI2C_MasterPinLowTimeoutFlag | + kLPI2C_MasterDataMatchFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kMasterIrqFlags = kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterTxReadyFlag | kLPI2C_MasterRxReadyFlag | + kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | kLPI2C_MasterPinLowTimeoutFlag | + kLPI2C_MasterFifoErrFlag, + + /*! Errors to check for. */ + kMasterErrorFlags = kLPI2C_MasterNackDetectFlag | kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | + kLPI2C_MasterPinLowTimeoutFlag, + + /*! All flags which are cleared by the driver upon starting a transfer. */ + kSlaveClearFlags = kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveBitErrFlag | + kLPI2C_SlaveFifoErrFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kSlaveIrqFlags = kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | + kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag | + kLPI2C_SlaveTransmitAckFlag | kLPI2C_SlaveAddressValidFlag, + + /*! Errors to check for. */ + kSlaveErrorFlags = kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag, +}; + +/* ! @brief LPI2C master fifo commands. */ +enum _lpi2c_master_fifo_cmd +{ + kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */ + kRxDataCmd = LPI2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */ + kStopCmd = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */ + kStartCmd = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */ +}; + +/*! + * @brief Default watermark values. + * + * The default watermarks are set to zero. + */ +enum _lpi2c_default_watermarks +{ + kDefaultTxWatermark = 0, + kDefaultRxWatermark = 0, +}; + +/*! @brief States for the state machine used by transactional APIs. */ +enum _lpi2c_transfer_states +{ + kIdleState = 0, + kSendCommandState, + kIssueReadCommandState, + kTransferDataState, + kStopState, + kWaitForCompletionState, +}; + +/*! @brief Typedef for master interrupt handler. */ +typedef void (*lpi2c_master_isr_t)(LPI2C_Type *base, lpi2c_master_handle_t *handle); + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*lpi2c_slave_isr_t)(LPI2C_Type *base, lpi2c_slave_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +uint32_t LPI2C_GetInstance(LPI2C_Type *base); + +static uint32_t LPI2C_GetCyclesForWidth(uint32_t sourceClock_Hz, + uint32_t width_ns, + uint32_t maxCycles, + uint32_t prescaler); + +static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base); + +static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_handle_t *handle, bool *isDone); + +static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle); + +static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags); + +static void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map LPI2C instance number to base pointer. */ +static LPI2C_Type *const kLpi2cBases[] = LPI2C_BASE_PTRS; + +/*! @brief Array to map LPI2C instance number to IRQ number. */ +static IRQn_Type const kLpi2cIrqs[] = LPI2C_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map LPI2C instance number to clock gate enum. */ +static clock_ip_name_t const kLpi2cClocks[] = LPI2C_CLOCKS; + +#if defined(LPI2C_PERIPH_CLOCKS) +/*! @brief Array to map LPI2C instance number to pheripheral clock gate enum. */ +static const clock_ip_name_t kLpi2cPeriphClocks[] = LPI2C_PERIPH_CLOCKS; +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointer to master IRQ handler for each instance. */ +static lpi2c_master_isr_t s_lpi2cMasterIsr; + +/*! @brief Pointers to master handles for each instance. */ +static lpi2c_master_handle_t *s_lpi2cMasterHandle[ARRAY_SIZE(kLpi2cBases)]; + +/*! @brief Pointer to slave IRQ handler for each instance. */ +static lpi2c_slave_isr_t s_lpi2cSlaveIsr; + +/*! @brief Pointers to slave handles for each instance. */ +static lpi2c_slave_handle_t *s_lpi2cSlaveHandle[ARRAY_SIZE(kLpi2cBases)]; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * @brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * @param base The LPI2C peripheral base address. + * @return LPI2C instance number starting from 0. + */ +uint32_t LPI2C_GetInstance(LPI2C_Type *base) +{ + uint32_t instance; + for (instance = 0; instance < ARRAY_SIZE(kLpi2cBases); ++instance) + { + if (kLpi2cBases[instance] == base) + { + return instance; + } + } + + assert(false); + return 0; +} + +/*! + * @brief Computes a cycle count for a given time in nanoseconds. + * @param sourceClock_Hz LPI2C functional clock frequency in Hertz. + * @param width_ns Desired with in nanoseconds. + * @param maxCycles Maximum cycle count, determined by the number of bits wide the cycle count field is. + * @param prescaler LPI2C prescaler setting. Pass 1 if the prescaler should not be used, as for slave glitch widths. + */ +static uint32_t LPI2C_GetCyclesForWidth(uint32_t sourceClock_Hz, + uint32_t width_ns, + uint32_t maxCycles, + uint32_t prescaler) +{ + assert(sourceClock_Hz > 0); + assert(prescaler > 0); + + uint32_t busCycle_ns = 1000000 / (sourceClock_Hz / prescaler / 1000); + uint32_t cycles = 0; + + /* Search for the cycle count just below the desired glitch width. */ + while ((((cycles + 1) * busCycle_ns) < width_ns) && (cycles + 1 < maxCycles)) + { + ++cycles; + } + + /* If we end up with zero cycles, then set the filter to a single cycle unless the */ + /* bus clock is greater than 10x the desired glitch width. */ + if ((cycles == 0) && (busCycle_ns <= (width_ns * 10))) + { + cycles = 1; + } + + return cycles; +} + +/*! + * @brief Convert provided flags to status code, and clear any errors if present. + * @param base The LPI2C peripheral base address. + * @param status Current status flags value that will be checked. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_PinLowTimeout + * @retval #kStatus_LPI2C_ArbitrationLost + * @retval #kStatus_LPI2C_Nak + * @retval #kStatus_LPI2C_FifoError + */ +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check for error. These errors cause a stop to automatically be sent. We must */ + /* clear the errors before a new transfer can start. */ + status &= kMasterErrorFlags; + if (status) + { + /* Select the correct error code. Ordered by severity, with bus issues first. */ + if (status & kLPI2C_MasterPinLowTimeoutFlag) + { + result = kStatus_LPI2C_PinLowTimeout; + } + else if (status & kLPI2C_MasterArbitrationLostFlag) + { + result = kStatus_LPI2C_ArbitrationLost; + } + else if (status & kLPI2C_MasterNackDetectFlag) + { + result = kStatus_LPI2C_Nak; + } + else if (status & kLPI2C_MasterFifoErrFlag) + { + result = kStatus_LPI2C_FifoError; + } + else + { + assert(false); + } + + /* Clear the flags. */ + LPI2C_MasterClearStatusFlags(base, status); + + /* Reset fifos. These flags clear automatically. */ + base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + } + + return result; +} + +/*! + * @brief Wait until there is room in the tx fifo. + * @param base The LPI2C peripheral base address. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_PinLowTimeout + * @retval #kStatus_LPI2C_ArbitrationLost + * @retval #kStatus_LPI2C_Nak + * @retval #kStatus_LPI2C_FifoError + */ +static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base) +{ + uint32_t status; + size_t txCount; + size_t txFifoSize = FSL_FEATURE_LPI2C_FIFO_SIZEn(base); + +#if LPI2C_WAIT_TIMEOUT + uint32_t waitTimes = LPI2C_WAIT_TIMEOUT; +#endif + do + { + status_t result; + + /* Get the number of words in the tx fifo and compute empty slots. */ + LPI2C_MasterGetFifoCounts(base, NULL, &txCount); + txCount = txFifoSize - txCount; + + /* Check for error flags. */ + status = LPI2C_MasterGetStatusFlags(base); + result = LPI2C_MasterCheckAndClearError(base, status); + if (result) + { + return result; + } +#if LPI2C_WAIT_TIMEOUT + } while ((!txCount) && (--waitTimes)); + + if (waitTimes == 0) + { + return kStatus_LPI2C_Timeout; + } +#else + } while (!txCount); +#endif + + return kStatus_Success; +} + +/*! + * @brief Make sure the bus isn't already busy. + * + * A busy bus is allowed if we are the one driving it. + * + * @param base The LPI2C peripheral base address. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_Busy + */ +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_CheckForBusyBus(LPI2C_Type *base) +{ + uint32_t status = LPI2C_MasterGetStatusFlags(base); + if ((status & kLPI2C_MasterBusBusyFlag) && (!(status & kLPI2C_MasterBusyFlag))) + { + return kStatus_LPI2C_Busy; + } + + return kStatus_Success; +} + +/*! + * brief Provides a default configuration for the LPI2C master peripheral. + * + * This function provides the following default configuration for the LPI2C master peripheral: + * code + * masterConfig->enableMaster = true; + * masterConfig->debugEnable = false; + * masterConfig->ignoreAck = false; + * masterConfig->pinConfig = kLPI2C_2PinOpenDrain; + * masterConfig->baudRate_Hz = 100000U; + * masterConfig->busIdleTimeout_ns = 0; + * masterConfig->pinLowTimeout_ns = 0; + * masterConfig->sdaGlitchFilterWidth_ns = 0; + * masterConfig->sclGlitchFilterWidth_ns = 0; + * masterConfig->hostRequest.enable = false; + * masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; + * masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; + * endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with LPI2C_MasterInit(). + * + * param[out] masterConfig User provided configuration structure for default values. Refer to #lpi2c_master_config_t. + */ +void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig) +{ + /* Initializes the configure structure to zero. */ + memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->enableMaster = true; + masterConfig->debugEnable = false; + masterConfig->enableDoze = true; + masterConfig->ignoreAck = false; + masterConfig->pinConfig = kLPI2C_2PinOpenDrain; + masterConfig->baudRate_Hz = 100000U; + masterConfig->busIdleTimeout_ns = 0; + masterConfig->pinLowTimeout_ns = 0; + masterConfig->sdaGlitchFilterWidth_ns = 0; + masterConfig->sclGlitchFilterWidth_ns = 0; + masterConfig->hostRequest.enable = false; + masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; + masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; +} + +/*! + * brief Initializes the LPI2C master peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * param base The LPI2C peripheral base address. + * param masterConfig User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz) +{ + uint32_t prescaler; + uint32_t cycles; + uint32_t cfgr2; + uint32_t value; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPI2C_GetInstance(base); + + /* Ungate the clock. */ + CLOCK_EnableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Ungate the functional clock in initialize function. */ + CLOCK_EnableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset peripheral before configuring it. */ + LPI2C_MasterReset(base); + + /* Doze bit: 0 is enable, 1 is disable */ + base->MCR = LPI2C_MCR_DBGEN(masterConfig->debugEnable) | LPI2C_MCR_DOZEN(!(masterConfig->enableDoze)); + + /* host request */ + value = base->MCFGR0; + value &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK | LPI2C_MCFGR0_HRSEL_MASK)); + value |= LPI2C_MCFGR0_HREN(masterConfig->hostRequest.enable) | + LPI2C_MCFGR0_HRPOL(masterConfig->hostRequest.polarity) | + LPI2C_MCFGR0_HRSEL(masterConfig->hostRequest.source); + base->MCFGR0 = value; + + /* pin config and ignore ack */ + value = base->MCFGR1; + value &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK); + value |= LPI2C_MCFGR1_PINCFG(masterConfig->pinConfig); + value |= LPI2C_MCFGR1_IGNACK(masterConfig->ignoreAck); + base->MCFGR1 = value; + + LPI2C_MasterSetWatermarks(base, kDefaultTxWatermark, kDefaultRxWatermark); + + LPI2C_MasterSetBaudRate(base, sourceClock_Hz, masterConfig->baudRate_Hz); + + /* Configure glitch filters and bus idle and pin low timeouts. */ + prescaler = (base->MCFGR1 & LPI2C_MCFGR1_PRESCALE_MASK) >> LPI2C_MCFGR1_PRESCALE_SHIFT; + cfgr2 = base->MCFGR2; + if (masterConfig->busIdleTimeout_ns) + { + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->busIdleTimeout_ns, + (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler); + cfgr2 &= ~LPI2C_MCFGR2_BUSIDLE_MASK; + cfgr2 |= LPI2C_MCFGR2_BUSIDLE(cycles); + } + if (masterConfig->sdaGlitchFilterWidth_ns) + { + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->sdaGlitchFilterWidth_ns, + (LPI2C_MCFGR2_FILTSDA_MASK >> LPI2C_MCFGR2_FILTSDA_SHIFT), 1); + cfgr2 &= ~LPI2C_MCFGR2_FILTSDA_MASK; + cfgr2 |= LPI2C_MCFGR2_FILTSDA(cycles); + } + if (masterConfig->sclGlitchFilterWidth_ns) + { + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->sclGlitchFilterWidth_ns, + (LPI2C_MCFGR2_FILTSCL_MASK >> LPI2C_MCFGR2_FILTSCL_SHIFT), 1); + cfgr2 &= ~LPI2C_MCFGR2_FILTSCL_MASK; + cfgr2 |= LPI2C_MCFGR2_FILTSCL(cycles); + } + base->MCFGR2 = cfgr2; + if (masterConfig->pinLowTimeout_ns) + { + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->pinLowTimeout_ns / 256, + (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler); + base->MCFGR3 = (base->MCFGR3 & ~LPI2C_MCFGR3_PINLOW_MASK) | LPI2C_MCFGR3_PINLOW(cycles); + } + + LPI2C_MasterEnable(base, masterConfig->enableMaster); +} + +/*! + * brief Deinitializes the LPI2C master peripheral. + * + * This function disables the LPI2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The LPI2C peripheral base address. + */ +void LPI2C_MasterDeinit(LPI2C_Type *base) +{ + /* Restore to reset state. */ + LPI2C_MasterReset(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPI2C_GetInstance(base); + + /* Gate clock. */ + CLOCK_DisableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Gate the functional clock. */ + CLOCK_DisableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Configures LPI2C master data match feature. + * + * param base The LPI2C peripheral base address. + * param config Settings for the data match feature. + */ +void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *config) +{ + /* Disable master mode. */ + bool wasEnabled = (base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT; + LPI2C_MasterEnable(base, false); + + base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_MATCFG_MASK) | LPI2C_MCFGR1_MATCFG(config->matchMode); + base->MCFGR0 = (base->MCFGR0 & ~LPI2C_MCFGR0_RDMO_MASK) | LPI2C_MCFGR0_RDMO(config->rxDataMatchOnly); + base->MDMR = LPI2C_MDMR_MATCH0(config->match0) | LPI2C_MDMR_MATCH1(config->match1); + + /* Restore master mode. */ + if (wasEnabled) + { + LPI2C_MasterEnable(base, true); + } +} + +/*! + * brief Sets the I2C bus frequency for master transactions. + * + * The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * note Please note that the second parameter is the clock frequency of LPI2C module, the third + * parameter means user configured bus baudrate, this implementation is different from other I2C drivers + * which use baudrate configuration as second parameter and source clock frequency as third parameter. + * + * param base The LPI2C peripheral base address. + * param sourceClock_Hz LPI2C functional clock frequency in Hertz. + * param baudRate_Hz Requested bus frequency in Hertz. + */ +void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz) +{ + uint32_t prescale = 0; + uint32_t bestPre = 0; + uint32_t bestClkHi = 0; + uint32_t absError = 0; + uint32_t bestError = 0xffffffffu; + uint32_t value; + uint32_t clkHiCycle; + uint32_t computedRate; + int i; + bool wasEnabled; + + /* Disable master mode. */ + wasEnabled = (base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT; + LPI2C_MasterEnable(base, false); + + /* Baud rate = (sourceClock_Hz/2^prescale)/(CLKLO+1+CLKHI+1 + ROUNDDOWN((2+FILTSCL)/2^prescale) */ + /* Assume CLKLO = 2*CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2. */ + for (prescale = 1; (prescale <= 128) && (bestError != 0); prescale = 2 * prescale) + { + for (clkHiCycle = 1; clkHiCycle < 32; clkHiCycle++) + { + if (clkHiCycle == 1) + { + computedRate = (sourceClock_Hz / prescale) / (1 + 3 + 2 + 2 / prescale); + } + else + { + computedRate = (sourceClock_Hz / prescale) / (3 * clkHiCycle + 2 + 2 / prescale); + } + + absError = baudRate_Hz > computedRate ? baudRate_Hz - computedRate : computedRate - baudRate_Hz; + + if (absError < bestError) + { + bestPre = prescale; + bestClkHi = clkHiCycle; + bestError = absError; + + /* If the error is 0, then we can stop searching because we won't find a better match. */ + if (absError == 0) + { + break; + } + } + } + } + + /* Standard, fast, fast mode plus and ultra-fast transfers. */ + value = LPI2C_MCCR0_CLKHI(bestClkHi); + + if (bestClkHi < 2) + { + value |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | LPI2C_MCCR0_DATAVD(1); + } + else + { + value |= LPI2C_MCCR0_CLKLO(2 * bestClkHi) | LPI2C_MCCR0_SETHOLD(bestClkHi) | LPI2C_MCCR0_DATAVD(bestClkHi / 2); + } + + base->MCCR0 = value; + + for (i = 0; i < 8; i++) + { + if (bestPre == (1U << i)) + { + bestPre = i; + break; + } + } + base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_PRESCALE_MASK) | LPI2C_MCFGR1_PRESCALE(bestPre); + + /* Restore master mode. */ + if (wasEnabled) + { + LPI2C_MasterEnable(base, true); + } +} + +/*! + * brief Sends a START signal and slave address on the I2C bus. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * param base The LPI2C peripheral base address. + * param address 7-bit slave device address, in bits [6:0]. + * param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + */ +status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir) +{ + /* Return an error if the bus is already in use not by us. */ + status_t result = LPI2C_CheckForBusyBus(base); + if (result) + { + return result; + } + + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, kMasterClearFlags); + + /* Turn off auto-stop option. */ + base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; + + /* Wait until there is room in the fifo. */ + result = LPI2C_MasterWaitForTxReady(base); + if (result) + { + return result; + } + + /* Issue start command. */ + base->MTDR = kStartCmd | (((uint32_t)address << 1U) | (uint32_t)dir); + + return kStatus_Success; +} + +/*! + * brief Sends a STOP signal on the I2C bus. + * + * This function does not return until the STOP signal is seen on the bus, or an error occurs. + * + * param base The LPI2C peripheral base address. + * retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterStop(LPI2C_Type *base) +{ + /* Wait until there is room in the fifo. */ + status_t result = LPI2C_MasterWaitForTxReady(base); + if (result) + { + return result; + } + + /* Send the STOP signal */ + base->MTDR = kStopCmd; + +/* Wait for the stop detected flag to set, indicating the transfer has completed on the bus. */ +/* Also check for errors while waiting. */ +#if LPI2C_WAIT_TIMEOUT + uint32_t waitTimes = LPI2C_WAIT_TIMEOUT; +#endif + +#if LPI2C_WAIT_TIMEOUT + while ((result == kStatus_Success) && (--waitTimes)) +#else + while (result == kStatus_Success) +#endif + { + uint32_t status = LPI2C_MasterGetStatusFlags(base); + + /* Check for error flags. */ + result = LPI2C_MasterCheckAndClearError(base, status); + + /* Check if the stop was sent successfully. */ + if ((status & kLPI2C_MasterStopDetectFlag) && (status & kLPI2C_MasterTxReadyFlag)) + { + LPI2C_MasterClearStatusFlags(base, kLPI2C_MasterStopDetectFlag); + break; + } + } + +#if LPI2C_WAIT_TIMEOUT + if (waitTimes == 0) + { + return kStatus_LPI2C_Timeout; + } +#endif + + return result; +} + +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * retval #kStatus_Success Data was received successfully. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize) +{ + status_t result; + uint8_t *buf; + + assert(rxBuff); + + /* Handle empty read. */ + if (!rxSize) + { + return kStatus_Success; + } + + /* Wait until there is room in the command fifo. */ + result = LPI2C_MasterWaitForTxReady(base); + if (result) + { + return result; + } + + /* Issue command to receive data. */ + base->MTDR = kRxDataCmd | LPI2C_MTDR_DATA(rxSize - 1); + +#if LPI2C_WAIT_TIMEOUT + uint32_t waitTimes = LPI2C_WAIT_TIMEOUT; +#endif + + /* Receive data */ + buf = (uint8_t *)rxBuff; + while (rxSize--) + { + /* Read LPI2C receive fifo register. The register includes a flag to indicate whether */ + /* the FIFO is empty, so we can both get the data and check if we need to keep reading */ + /* using a single register read. */ + uint32_t value; + do + { + /* Check for errors. */ + result = LPI2C_MasterCheckAndClearError(base, LPI2C_MasterGetStatusFlags(base)); + if (result) + { + return result; + } + + value = base->MRDR; +#if LPI2C_WAIT_TIMEOUT + } while ((value & LPI2C_MRDR_RXEMPTY_MASK) && (--waitTimes)); + if (waitTimes == 0) + { + return kStatus_LPI2C_Timeout; + } +#else + } while (value & LPI2C_MRDR_RXEMPTY_MASK); +#endif + + *buf++ = value & LPI2C_MRDR_DATA_MASK; + } + + return kStatus_Success; +} + +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_LPI2C_Nak. + * + * param base The LPI2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * retval #kStatus_Success Data was sent successfully. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or over run. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize) +{ + uint8_t *buf = (uint8_t *)txBuff; + + assert(txBuff); + + /* Send data buffer */ + while (txSize--) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + status_t result = LPI2C_MasterWaitForTxReady(base); + if (result) + { + return result; + } + + /* Write byte into LPI2C master data register. */ + base->MTDR = *buf++; + } + + return kStatus_Success; +} + +/*! + * brief Performs a master polling transfer on the I2C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to error happens during transfer. + * + * param base The LPI2C peripheral base address. + * param transfer Pointer to the transfer structure. + * retval #kStatus_Success Data was received successfully. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer) +{ + status_t result = kStatus_Success; + uint16_t commandBuffer[7]; + uint32_t cmdCount = 0; + + assert(transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + /* Return an error if the bus is already in use not by us. */ + result = LPI2C_CheckForBusyBus(base); + if (result) + { + return result; + } + + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, kMasterClearFlags); + + /* Turn off auto-stop option. */ + base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; + + lpi2c_direction_t direction = transfer->subaddressSize ? kLPI2C_Write : transfer->direction; + if (!(transfer->flags & kLPI2C_TransferNoStartFlag)) + { + commandBuffer[cmdCount++] = + (uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)transfer->slaveAddress << 1U) | (uint16_t)direction); + } + + /* Subaddress, MSB first. */ + if (transfer->subaddressSize) + { + uint32_t subaddressRemaining = transfer->subaddressSize; + while (subaddressRemaining--) + { + uint8_t subaddressByte = (transfer->subaddress >> (8 * subaddressRemaining)) & 0xff; + commandBuffer[cmdCount++] = subaddressByte; + } + } + + /* Reads need special handling. */ + if ((transfer->dataSize) && (transfer->direction == kLPI2C_Read)) + { + /* Need to send repeated start if switching directions to read. */ + if (direction == kLPI2C_Write) + { + commandBuffer[cmdCount++] = + (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)transfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); + } + } + + /* Send command buffer */ + uint32_t index = 0; + while (cmdCount--) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + result = LPI2C_MasterWaitForTxReady(base); + if (result) + { + return result; + } + + /* Write byte into LPI2C master data register. */ + base->MTDR = commandBuffer[index]; + index++; + } + + /* Transmit data. */ + if ((transfer->direction == kLPI2C_Write) && (transfer->dataSize > 0)) + { + /* Send Data. */ + result = LPI2C_MasterSend(base, transfer->data, transfer->dataSize); + } + + /* Receive Data. */ + if ((transfer->direction == kLPI2C_Read) && (transfer->dataSize > 0)) + { + result = LPI2C_MasterReceive(base, transfer->data, transfer->dataSize); + } + + if (result) + { + return result; + } + + if ((transfer->flags & kLPI2C_TransferNoStopFlag) == 0) + { + result = LPI2C_MasterStop(base); + } + + return result; +} + +/*! + * brief Creates a new handle for the LPI2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called. + * + * + * note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * + * param base The LPI2C peripheral base address. + * param[out] handle Pointer to the LPI2C master driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_callback_t callback, + void *userData) +{ + uint32_t instance; + + assert(handle); + + /* Clear out the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = LPI2C_GetInstance(base); + + /* Save base and instance. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_lpi2cMasterHandle[instance] = handle; + + /* Set irq handler. */ + s_lpi2cMasterIsr = LPI2C_MasterTransferHandleIRQ; + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); + + /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. + In some cases the LPI2C IRQ is configured through INTMUX, user needs to enable + INTMUX IRQ in application code. */ + EnableIRQ(kLpi2cIrqs[instance]); +} + +/*! + * @brief Execute states until FIFOs are exhausted. + * @param handle Master nonblocking driver handle. + * @param[out] isDone Set to true if the transfer has completed. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_PinLowTimeout + * @retval #kStatus_LPI2C_ArbitrationLost + * @retval #kStatus_LPI2C_Nak + * @retval #kStatus_LPI2C_FifoError + */ +static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_handle_t *handle, bool *isDone) +{ + uint32_t status; + status_t result = kStatus_Success; + lpi2c_master_transfer_t *xfer; + size_t txCount; + size_t rxCount; + size_t txFifoSize = FSL_FEATURE_LPI2C_FIFO_SIZEn(base); + bool state_complete = false; + + /* Set default isDone return value. */ + *isDone = false; + + /* Check for errors. */ + status = LPI2C_MasterGetStatusFlags(base); + result = LPI2C_MasterCheckAndClearError(base, status); + if (result) + { + return result; + } + + /* Get pointer to private data. */ + xfer = &handle->transfer; + + /* Get fifo counts and compute room in tx fifo. */ + LPI2C_MasterGetFifoCounts(base, &rxCount, &txCount); + txCount = txFifoSize - txCount; + + while (!state_complete) + { + /* Execute the state. */ + switch (handle->state) + { + case kSendCommandState: + { + /* Make sure there is room in the tx fifo for the next command. */ + if (!txCount--) + { + state_complete = true; + break; + } + + /* Issue command. buf is a uint8_t* pointing at the uint16 command array. */ + base->MTDR = *(uint16_t *)handle->buf; + handle->buf += sizeof(uint16_t); + + /* Count down until all commands are sent. */ + if (--handle->remainingBytes == 0) + { + /* Choose next state and set up buffer pointer and count. */ + if (xfer->dataSize) + { + /* Either a send or receive transfer is next. */ + handle->state = kTransferDataState; + handle->buf = (uint8_t *)xfer->data; + handle->remainingBytes = xfer->dataSize; + if (xfer->direction == kLPI2C_Read) + { + /* Disable TX interrupt */ + LPI2C_MasterDisableInterrupts(base, kLPI2C_MasterTxReadyFlag); + } + } + else + { + /* No transfer, so move to stop state. */ + handle->state = kStopState; + } + } + break; + } + + case kIssueReadCommandState: + /* Make sure there is room in the tx fifo for the read command. */ + if (!txCount--) + { + state_complete = true; + break; + } + + base->MTDR = kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1); + + /* Move to transfer state. */ + handle->state = kTransferDataState; + if (xfer->direction == kLPI2C_Read) + { + /* Disable TX interrupt */ + LPI2C_MasterDisableInterrupts(base, kLPI2C_MasterTxReadyFlag); + } + break; + + case kTransferDataState: + if (xfer->direction == kLPI2C_Write) + { + /* Make sure there is room in the tx fifo. */ + if (!txCount--) + { + state_complete = true; + break; + } + + /* Put byte to send in fifo. */ + base->MTDR = *(handle->buf)++; + } + else + { + /* XXX handle receive sizes > 256, use kIssueReadCommandState */ + /* Make sure there is data in the rx fifo. */ + if (!rxCount--) + { + state_complete = true; + break; + } + + /* Read byte from fifo. */ + *(handle->buf)++ = base->MRDR & LPI2C_MRDR_DATA_MASK; + } + + /* Move to stop when the transfer is done. */ + if (--handle->remainingBytes == 0) + { + if (xfer->direction == kLPI2C_Write) + { + state_complete = true; + } + handle->state = kStopState; + } + break; + + case kStopState: + /* Only issue a stop transition if the caller requested it. */ + if ((xfer->flags & kLPI2C_TransferNoStopFlag) == 0) + { + /* Make sure there is room in the tx fifo for the stop command. */ + if (!txCount--) + { + state_complete = true; + break; + } + + base->MTDR = kStopCmd; + } + else + { + /* Caller doesn't want to send a stop, so we're done now. */ + *isDone = true; + state_complete = true; + break; + } + handle->state = kWaitForCompletionState; + break; + + case kWaitForCompletionState: + /* We stay in this state until the stop state is detected. */ + if (status & kLPI2C_MasterStopDetectFlag) + { + *isDone = true; + } + state_complete = true; + break; + default: + assert(false); + break; + } + } + return result; +} + +/*! + * @brief Prepares the transfer state machine and fills in the command buffer. + * @param handle Master nonblocking driver handle. + */ +static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle) +{ + lpi2c_master_transfer_t *xfer = &handle->transfer; + + /* Handle no start option. */ + if (xfer->flags & kLPI2C_TransferNoStartFlag) + { + if (xfer->direction == kLPI2C_Read) + { + /* Need to issue read command first. */ + handle->state = kIssueReadCommandState; + } + else + { + /* Start immediately in the data transfer state. */ + handle->state = kTransferDataState; + } + + handle->buf = (uint8_t *)xfer->data; + handle->remainingBytes = xfer->dataSize; + } + else + { + uint16_t *cmd = (uint16_t *)&handle->commandBuffer; + uint32_t cmdCount = 0; + + /* Initial direction depends on whether a subaddress was provided, and of course the actual */ + /* data transfer direction. */ + lpi2c_direction_t direction = xfer->subaddressSize ? kLPI2C_Write : xfer->direction; + + /* Start command. */ + cmd[cmdCount++] = + (uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)direction); + + /* Subaddress, MSB first. */ + if (xfer->subaddressSize) + { + uint32_t subaddressRemaining = xfer->subaddressSize; + while (subaddressRemaining--) + { + uint8_t subaddressByte = (xfer->subaddress >> (8 * subaddressRemaining)) & 0xff; + cmd[cmdCount++] = subaddressByte; + } + } + + /* Reads need special handling. */ + if ((xfer->dataSize) && (xfer->direction == kLPI2C_Read)) + { + /* Need to send repeated start if switching directions to read. */ + if (direction == kLPI2C_Write) + { + cmd[cmdCount++] = (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); + } + + /* Read command. */ + cmd[cmdCount++] = kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1); + } + + /* Set up state machine for transferring the commands. */ + handle->state = kSendCommandState; + handle->remainingBytes = cmdCount; + handle->buf = (uint8_t *)&handle->commandBuffer; + } +} + +/*! + * brief Performs a non-blocking transaction on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param transfer The pointer to the transfer descriptor. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_t *transfer) +{ + status_t result; + + assert(handle); + assert(transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + /* Return busy if another transaction is in progress. */ + if (handle->state != kIdleState) + { + return kStatus_LPI2C_Busy; + } + + /* Return an error if the bus is already in use not by us. */ + result = LPI2C_CheckForBusyBus(base); + if (result) + { + return result; + } + + /* Disable LPI2C IRQ sources while we configure stuff. */ + LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); + + /* Save transfer into handle. */ + handle->transfer = *transfer; + + /* Generate commands to send. */ + LPI2C_InitTransferStateMachine(handle); + + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, kMasterClearFlags); + + /* Turn off auto-stop option. */ + base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; + + /* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + LPI2C_MasterEnableInterrupts(base, kMasterIrqFlags); + + return result; +} + +/*! + * brief Returns number of bytes transferred so far. + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param[out] count Number of bytes transferred so far by the non-blocking transaction. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + uint8_t state; + uint16_t remainingBytes; + uint32_t dataSize; + + /* Cache some fields with IRQs disabled. This ensures all field values */ + /* are synchronized with each other during an ongoing transfer. */ + uint32_t irqs = LPI2C_MasterGetEnabledInterrupts(base); + LPI2C_MasterDisableInterrupts(base, irqs); + state = handle->state; + remainingBytes = handle->remainingBytes; + dataSize = handle->transfer.dataSize; + LPI2C_MasterEnableInterrupts(base, irqs); + + /* Get transfer count based on current transfer state. */ + switch (state) + { + case kIdleState: + case kSendCommandState: + case kIssueReadCommandState: /* XXX return correct value for this state when >256 reads are supported */ + *count = 0; + break; + + case kTransferDataState: + *count = dataSize - remainingBytes; + break; + + case kStopState: + case kWaitForCompletionState: + default: + *count = dataSize; + break; + } + + return kStatus_Success; +} + +/*! + * brief Terminates a non-blocking LPI2C master transmission early. + * + * note It is not safe to call this function from an IRQ handler that has a higher priority than the + * LPI2C peripheral's IRQ priority. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * retval #kStatus_Success A transaction was successfully aborted. + * retval #kStatus_LPI2C_Idle There is not a non-blocking transaction currently in progress. + */ +void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle) +{ + if (handle->state != kIdleState) + { + /* Disable internal IRQ enables. */ + LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); + + /* Reset fifos. */ + base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + + /* Send a stop command to finalize the transfer. */ + base->MTDR = kStopCmd; + + /* Reset handle. */ + handle->state = kIdleState; + } +} + +/*! + * brief Reusable routine to handle master interrupts. + * note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + */ +void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, lpi2c_master_handle_t *handle) +{ + bool isDone; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (!handle) + { + return; + } + + if (handle->state == kIdleState) + { + return; + } + + result = LPI2C_RunTransferStateMachine(base, handle, &isDone); + + if (isDone || (result != kStatus_Success)) + { + /* XXX need to handle data that may be in rx fifo below watermark level? */ + + /* XXX handle error, terminate xfer */ + + /* Disable internal IRQ enables. */ + LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); + + /* Set handle to idle state. */ + handle->state = kIdleState; + + /* Invoke callback. */ + if (handle->completionCallback) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } +} + +/*! + * brief Provides a default configuration for the LPI2C slave peripheral. + * + * This function provides the following default configuration for the LPI2C slave peripheral: + * code + * slaveConfig->enableSlave = true; + * slaveConfig->address0 = 0U; + * slaveConfig->address1 = 0U; + * slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; + * slaveConfig->filterDozeEnable = true; + * slaveConfig->filterEnable = true; + * slaveConfig->enableGeneralCall = false; + * slaveConfig->sclStall.enableAck = false; + * slaveConfig->sclStall.enableTx = true; + * slaveConfig->sclStall.enableRx = true; + * slaveConfig->sclStall.enableAddress = true; + * slaveConfig->ignoreAck = false; + * slaveConfig->enableReceivedAddressRead = false; + * slaveConfig->sdaGlitchFilterWidth_ns = 0; + * slaveConfig->sclGlitchFilterWidth_ns = 0; + * slaveConfig->dataValidDelay_ns = 0; + * slaveConfig->clockHoldTime_ns = 0; + * endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the a + * address0 member of the configuration structure with the desired slave address. + * + * param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #lpi2c_slave_config_t. + */ +void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig) +{ + /* Initializes the configure structure to zero. */ + memset(slaveConfig, 0, sizeof(*slaveConfig)); + + slaveConfig->enableSlave = true; + slaveConfig->address0 = 0U; + slaveConfig->address1 = 0U; + slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; + slaveConfig->filterDozeEnable = true; + slaveConfig->filterEnable = true; + slaveConfig->enableGeneralCall = false; + slaveConfig->sclStall.enableAck = false; + slaveConfig->sclStall.enableTx = true; + slaveConfig->sclStall.enableRx = true; + slaveConfig->sclStall.enableAddress = false; + slaveConfig->ignoreAck = false; + slaveConfig->enableReceivedAddressRead = false; + slaveConfig->sdaGlitchFilterWidth_ns = 0; /* TODO determine default width values */ + slaveConfig->sclGlitchFilterWidth_ns = 0; + slaveConfig->dataValidDelay_ns = 0; + slaveConfig->clockHoldTime_ns = 0; +} + +/*! + * brief Initializes the LPI2C slave peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user + * provided configuration. + * + * param base The LPI2C peripheral base address. + * param slaveConfig User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, + * data valid delay, and clock hold time. + */ +void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPI2C_GetInstance(base); + + /* Ungate the clock. */ + CLOCK_EnableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Ungate the functional clock in initialize function. */ + CLOCK_EnableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Restore to reset conditions. */ + LPI2C_SlaveReset(base); + + /* Configure peripheral. */ + base->SAMR = LPI2C_SAMR_ADDR0(slaveConfig->address0) | LPI2C_SAMR_ADDR1(slaveConfig->address1); + + base->SCFGR1 = + LPI2C_SCFGR1_ADDRCFG(slaveConfig->addressMatchMode) | LPI2C_SCFGR1_IGNACK(slaveConfig->ignoreAck) | + LPI2C_SCFGR1_RXCFG(slaveConfig->enableReceivedAddressRead) | LPI2C_SCFGR1_GCEN(slaveConfig->enableGeneralCall) | + LPI2C_SCFGR1_ACKSTALL(slaveConfig->sclStall.enableAck) | LPI2C_SCFGR1_TXDSTALL(slaveConfig->sclStall.enableTx) | + LPI2C_SCFGR1_RXSTALL(slaveConfig->sclStall.enableRx) | + LPI2C_SCFGR1_ADRSTALL(slaveConfig->sclStall.enableAddress); + + base->SCFGR2 = + LPI2C_SCFGR2_FILTSDA(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->sdaGlitchFilterWidth_ns, + (LPI2C_SCFGR2_FILTSDA_MASK >> LPI2C_SCFGR2_FILTSDA_SHIFT), 1)) | + LPI2C_SCFGR2_FILTSCL(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->sclGlitchFilterWidth_ns, + (LPI2C_SCFGR2_FILTSCL_MASK >> LPI2C_SCFGR2_FILTSCL_SHIFT), 1)) | + LPI2C_SCFGR2_DATAVD(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->dataValidDelay_ns, + (LPI2C_SCFGR2_DATAVD_MASK >> LPI2C_SCFGR2_DATAVD_SHIFT), 1)) | + LPI2C_SCFGR2_CLKHOLD(LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->clockHoldTime_ns, + (LPI2C_SCFGR2_CLKHOLD_MASK >> LPI2C_SCFGR2_CLKHOLD_SHIFT), 1)); + + /* Save SCR to last so we don't enable slave until it is configured */ + base->SCR = LPI2C_SCR_FILTDZ(slaveConfig->filterDozeEnable) | LPI2C_SCR_FILTEN(slaveConfig->filterEnable) | + LPI2C_SCR_SEN(slaveConfig->enableSlave); +} + +/*! + * brief Deinitializes the LPI2C slave peripheral. + * + * This function disables the LPI2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The LPI2C peripheral base address. + */ +void LPI2C_SlaveDeinit(LPI2C_Type *base) +{ + LPI2C_SlaveReset(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPI2C_GetInstance(base); + + /* Gate the clock. */ + CLOCK_DisableClock(kLpi2cClocks[instance]); + +#if defined(LPI2C_PERIPH_CLOCKS) + /* Gate the functional clock. */ + CLOCK_DisableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Convert provided flags to status code, and clear any errors if present. + * @param base The LPI2C peripheral base address. + * @param status Current status flags value that will be checked. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_BitError + * @retval #kStatus_LPI2C_FifoError + */ +static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags) +{ + status_t result = kStatus_Success; + + flags &= kSlaveErrorFlags; + if (flags) + { + if (flags & kLPI2C_SlaveBitErrFlag) + { + result = kStatus_LPI2C_BitError; + } + else if (flags & kLPI2C_SlaveFifoErrFlag) + { + result = kStatus_LPI2C_FifoError; + } + else + { + assert(false); + } + + /* Clear the errors. */ + LPI2C_SlaveClearStatusFlags(base, flags); + } + + return result; +} + +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * param[out] actualTxSize + * return Error or success status returned by API. + */ +status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize) +{ + uint8_t *buf = (uint8_t *)txBuff; + size_t remaining = txSize; + + assert(txBuff); + +#if LPI2C_WAIT_TIMEOUT + uint32_t waitTimes = LPI2C_WAIT_TIMEOUT; +#endif + + /* Clear stop flag. */ + LPI2C_SlaveClearStatusFlags(base, kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag); + + while (remaining) + { + uint32_t flags; + status_t result; + + /* Wait until we can transmit. */ + do + { + /* Check for errors */ + flags = LPI2C_SlaveGetStatusFlags(base); + result = LPI2C_SlaveCheckAndClearError(base, flags); + if (result) + { + if (actualTxSize) + { + *actualTxSize = txSize - remaining; + } + return result; + } +#if LPI2C_WAIT_TIMEOUT + } while ( + (!(flags & (kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))) && + (--waitTimes)); + if (waitTimes == 0) + { + return kStatus_LPI2C_Timeout; + } +#else + } while ( + !(flags & (kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))); +#endif + + /* Send a byte. */ + if (flags & kLPI2C_SlaveTxReadyFlag) + { + base->STDR = *buf++; + --remaining; + } + + /* Exit loop if we see a stop or restart in transfer*/ + if ((flags & (kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag)) && (remaining != 0U)) + { + LPI2C_SlaveClearStatusFlags(base, kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag); + break; + } + } + + if (actualTxSize) + { + *actualTxSize = txSize - remaining; + } + + return kStatus_Success; +} + +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * param[out] actualRxSize + * return Error or success status returned by API. + */ +status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize) +{ + uint8_t *buf = (uint8_t *)rxBuff; + size_t remaining = rxSize; + + assert(rxBuff); + +#if LPI2C_WAIT_TIMEOUT + uint32_t waitTimes = LPI2C_WAIT_TIMEOUT; +#endif + + /* Clear stop flag. */ + LPI2C_SlaveClearStatusFlags(base, kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag); + + while (remaining) + { + uint32_t flags; + status_t result; + + /* Wait until we can receive. */ + do + { + /* Check for errors */ + flags = LPI2C_SlaveGetStatusFlags(base); + result = LPI2C_SlaveCheckAndClearError(base, flags); + if (result) + { + if (actualRxSize) + { + *actualRxSize = rxSize - remaining; + } + return result; + } +#if LPI2C_WAIT_TIMEOUT + } while ( + (!(flags & (kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))) && + (--waitTimes)); + if (waitTimes == 0) + { + return kStatus_LPI2C_Timeout; + } +#else + } while ( + !(flags & (kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag))); +#endif + + /* Receive a byte. */ + if (flags & kLPI2C_SlaveRxReadyFlag) + { + *buf++ = base->SRDR & LPI2C_SRDR_DATA_MASK; + --remaining; + } + + /* Exit loop if we see a stop or restart */ + if ((flags & (kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag)) && (remaining != 0U)) + { + LPI2C_SlaveClearStatusFlags(base, kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveRepeatedStartDetectFlag); + break; + } + } + + if (actualRxSize) + { + *actualRxSize = rxSize - remaining; + } + + return kStatus_Success; +} + +/*! + * brief Creates a new handle for the LPI2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called. + * + * note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + + * param base The LPI2C peripheral base address. + * param[out] handle Pointer to the LPI2C slave driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, + lpi2c_slave_handle_t *handle, + lpi2c_slave_transfer_callback_t callback, + void *userData) +{ + uint32_t instance; + + assert(handle); + + /* Clear out the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = LPI2C_GetInstance(base); + + /* Save base and instance. */ + handle->callback = callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_lpi2cSlaveHandle[instance] = handle; + + /* Set irq handler. */ + s_lpi2cSlaveIsr = LPI2C_SlaveTransferHandleIRQ; + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + LPI2C_SlaveDisableInterrupts(base, kSlaveIrqFlags); + EnableIRQ(kLpi2cIrqs[instance]); + + /* Nack by default. */ + base->STAR = LPI2C_STAR_TXNACK_MASK; +} + +/*! + * brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kLPI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kLPI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + * param eventMask Bit mask formed by OR'ing together #lpi2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kLPI2C_SlaveAllEvents to enable all events. + * + * retval #kStatus_Success Slave transfers were successfully started. + * retval #kStatus_LPI2C_Busy Slave transfers have already been started on this handle. + */ +status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask) +{ + uint32_t status; + + assert(handle); + + /* Return busy if another transaction is in progress. */ + if (handle->isBusy) + { + return kStatus_LPI2C_Busy; + } + + /* Return an error if the bus is already in use not by us. */ + status = LPI2C_SlaveGetStatusFlags(base); + if ((status & kLPI2C_SlaveBusBusyFlag) && (!(status & kLPI2C_SlaveBusyFlag))) + { + return kStatus_LPI2C_Busy; + } + + /* Disable LPI2C IRQ sources while we configure stuff. */ + LPI2C_SlaveDisableInterrupts(base, kSlaveIrqFlags); + + /* Clear transfer in handle. */ + memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Record that we're busy. */ + handle->isBusy = true; + + /* Set up event mask. tx and rx are always enabled. */ + handle->eventMask = eventMask | kLPI2C_SlaveTransmitEvent | kLPI2C_SlaveReceiveEvent; + + /* Ack by default. */ + base->STAR = 0; + + /* Clear all flags. */ + LPI2C_SlaveClearStatusFlags(base, kSlaveClearFlags); + + /* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + LPI2C_SlaveEnableInterrupts(base, kSlaveIrqFlags); + + return kStatus_Success; +} + +/*! + * brief Gets the slave transfer status during a non-blocking transfer. + * param base The LPI2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure. + * param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not + * required. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress + */ +status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + *count = handle->transferredCount; + + return kStatus_Success; +} + +/*! + * brief Aborts the slave non-blocking transfers. + * note This API could be called at any time to stop slave for handling the bus events. + * param base The LPI2C peripheral base address. + * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + * retval #kStatus_Success + * retval #kStatus_LPI2C_Idle + */ +void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle) +{ + assert(handle); + + /* Return idle if no transaction is in progress. */ + if (handle->isBusy) + { + /* Disable LPI2C IRQ sources. */ + LPI2C_SlaveDisableInterrupts(base, kSlaveIrqFlags); + + /* Nack by default. */ + base->STAR = LPI2C_STAR_TXNACK_MASK; + + /* Reset transfer info. */ + memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* We're no longer busy. */ + handle->isBusy = false; + } +} + +/*! + * brief Reusable routine to handle slave interrupts. + * note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * param base The LPI2C peripheral base address. + * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + */ +void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle) +{ + uint32_t flags; + lpi2c_slave_transfer_t *xfer; + + /* Check for a valid handle in case of a spurious interrupt. */ + if (!handle) + { + return; + } + + xfer = &handle->transfer; + + /* Get status flags. */ + flags = LPI2C_SlaveGetStatusFlags(base); + + if (flags & (kLPI2C_SlaveBitErrFlag | kLPI2C_SlaveFifoErrFlag)) + { + xfer->event = kLPI2C_SlaveCompletionEvent; + xfer->completionStatus = LPI2C_SlaveCheckAndClearError(base, flags); + + if ((handle->eventMask & kLPI2C_SlaveCompletionEvent) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + return; + } + if (flags & (kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag)) + { + xfer->event = (flags & kLPI2C_SlaveRepeatedStartDetectFlag) ? kLPI2C_SlaveRepeatedStartEvent : + kLPI2C_SlaveCompletionEvent; + xfer->receivedAddress = 0; + xfer->completionStatus = kStatus_Success; + xfer->transferredCount = handle->transferredCount; + + if (xfer->event == kLPI2C_SlaveCompletionEvent) + { + handle->isBusy = false; + } + + if (handle->wasTransmit) + { + /* Subtract one from the transmit count to offset the fact that LPI2C asserts the */ + /* tx flag before it sees the nack from the master-receiver, thus causing one more */ + /* count that the master actually receives. */ + --xfer->transferredCount; + handle->wasTransmit = false; + } + + /* Clear the flag. */ + LPI2C_SlaveClearStatusFlags(base, flags & (kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag)); + + /* Revert to sending an Ack by default, in case we sent a Nack for receive. */ + base->STAR = 0; + + if ((handle->eventMask & xfer->event) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clean up transfer info on completion, after the callback has been invoked. */ + memset(&handle->transfer, 0, sizeof(handle->transfer)); + } + if (flags & kLPI2C_SlaveAddressValidFlag) + { + xfer->event = kLPI2C_SlaveAddressMatchEvent; + xfer->receivedAddress = base->SASR & LPI2C_SASR_RADDR_MASK; + + /* Update handle status to busy because slave is addressed. */ + handle->isBusy = true; + if ((handle->eventMask & kLPI2C_SlaveAddressMatchEvent) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + if (flags & kLPI2C_SlaveTransmitAckFlag) + { + xfer->event = kLPI2C_SlaveTransmitAckEvent; + + if ((handle->eventMask & kLPI2C_SlaveTransmitAckEvent) && (handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + + /* Handle transmit and receive. */ + if (flags & kLPI2C_SlaveTxReadyFlag) + { + handle->wasTransmit = true; + + /* If we're out of data, invoke callback to get more. */ + if ((!xfer->data) || (!xfer->dataSize)) + { + xfer->event = kLPI2C_SlaveTransmitEvent; + if (handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + handle->transferredCount = 0; + } + + /* Transmit a byte. */ + if ((xfer->data) && (xfer->dataSize)) + { + base->STDR = *xfer->data++; + --xfer->dataSize; + ++handle->transferredCount; + } + } + if (flags & kLPI2C_SlaveRxReadyFlag) + { + /* If we're out of room in the buffer, invoke callback to get another. */ + if ((!xfer->data) || (!xfer->dataSize)) + { + xfer->event = kLPI2C_SlaveReceiveEvent; + if (handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + handle->transferredCount = 0; + } + + /* Receive a byte. */ + if ((xfer->data) && (xfer->dataSize)) + { + *xfer->data++ = base->SRDR; + --xfer->dataSize; + ++handle->transferredCount; + } + else + { + /* We don't have any room to receive more data, so send a nack. */ + base->STAR = LPI2C_STAR_TXNACK_MASK; + } + } +} + +/*! + * @brief Shared IRQ handler that can call both master and slave ISRs. + * + * The master and slave ISRs are called through function pointers in order to decouple + * this code from the ISR functions. Without this, the linker would always pull in both + * ISRs and every function they call, even if only the functional API was used. + * + * @param base The LPI2C peripheral base address. + * @param instance The LPI2C peripheral instance number. + */ +static void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance) +{ + /* Check for master IRQ. */ + if ((base->MCR & LPI2C_MCR_MEN_MASK) && s_lpi2cMasterIsr) + { + /* Master mode. */ + s_lpi2cMasterIsr(base, s_lpi2cMasterHandle[instance]); + } + + /* Check for slave IRQ. */ + if ((base->SCR & LPI2C_SCR_SEN_MASK) && s_lpi2cSlaveIsr) + { + /* Slave mode. */ + s_lpi2cSlaveIsr(base, s_lpi2cSlaveHandle[instance]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#if defined(LPI2C0) +/* Implementation of LPI2C0 handler named in startup code. */ +void LPI2C0_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C0, 0); +} +#endif + +#if defined(LPI2C1) +/* Implementation of LPI2C1 handler named in startup code. */ +void LPI2C1_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C1, 1); +} +#endif + +#if defined(LPI2C2) +/* Implementation of LPI2C2 handler named in startup code. */ +void LPI2C2_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C2, 2); +} +#endif + +#if defined(LPI2C3) +/* Implementation of LPI2C3 handler named in startup code. */ +void LPI2C3_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C3, 3); +} +#endif + +#if defined(LPI2C4) +/* Implementation of LPI2C4 handler named in startup code. */ +void LPI2C4_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C4, 4); +} +#endif + +#if defined(CM4_0__LPI2C) +/* Implementation of CM4_0__LPI2C handler named in startup code. */ +void M4_0_LPI2C_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(CM4_0__LPI2C, LPI2C_GetInstance(CM4_0__LPI2C)); +} +#endif + +#if defined(CM4__LPI2C) +/* Implementation of CM4__LPI2C handler named in startup code. */ +void M4_LPI2C_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(CM4__LPI2C, LPI2C_GetInstance(CM4__LPI2C)); +} +#endif + +#if defined(CM4_1__LPI2C) +/* Implementation of CM4_1__LPI2C handler named in startup code. */ +void M4_1_LPI2C_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(CM4_1__LPI2C, LPI2C_GetInstance(CM4_1__LPI2C)); +} +#endif + +#if defined(DMA__LPI2C0) +/* Implementation of DMA__LPI2C0 handler named in startup code. */ +void DMA_I2C0_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(DMA__LPI2C0, LPI2C_GetInstance(DMA__LPI2C0)); +} +#endif + +#if defined(DMA__LPI2C1) +/* Implementation of DMA__LPI2C1 handler named in startup code. */ +void DMA_I2C1_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(DMA__LPI2C1, LPI2C_GetInstance(DMA__LPI2C1)); +} +#endif + +#if defined(DMA__LPI2C2) +/* Implementation of DMA__LPI2C2 handler named in startup code. */ +void DMA_I2C2_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(DMA__LPI2C2, LPI2C_GetInstance(DMA__LPI2C2)); +} +#endif + +#if defined(DMA__LPI2C3) +/* Implementation of DMA__LPI2C3 handler named in startup code. */ +void DMA_I2C3_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(DMA__LPI2C3, LPI2C_GetInstance(DMA__LPI2C3)); +} +#endif + +#if defined(DMA__LPI2C4) +/* Implementation of DMA__LPI2C3 handler named in startup code. */ +void DMA_I2C4_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(DMA__LPI2C4, LPI2C_GetInstance(DMA__LPI2C4)); +} +#endif + +#if defined(ADMA__LPI2C0) +/* Implementation of DMA__LPI2C0 handler named in startup code. */ +void ADMA_I2C0_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C0, LPI2C_GetInstance(ADMA__LPI2C0)); +} +#endif + +#if defined(ADMA__LPI2C1) +/* Implementation of DMA__LPI2C1 handler named in startup code. */ +void ADMA_I2C1_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C1, LPI2C_GetInstance(ADMA__LPI2C1)); +} +#endif + +#if defined(ADMA__LPI2C2) +/* Implementation of DMA__LPI2C2 handler named in startup code. */ +void ADMA_I2C2_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C2, LPI2C_GetInstance(ADMA__LPI2C2)); +} +#endif + +#if defined(ADMA__LPI2C3) +/* Implementation of DMA__LPI2C3 handler named in startup code. */ +void ADMA_I2C3_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C3, LPI2C_GetInstance(ADMA__LPI2C3)); +} +#endif + +#if defined(ADMA__LPI2C4) +/* Implementation of DMA__LPI2C3 handler named in startup code. */ +void ADMA_I2C4_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C4, LPI2C_GetInstance(ADMA__LPI2C4)); +} +#endif diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpi2c.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpi2c.h new file mode 100644 index 0000000000..41f83369b7 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpi2c.h @@ -0,0 +1,1266 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_LPI2C_H_ +#define _FSL_LPI2C_H_ + +#include +#include "fsl_device_registers.h" +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup lpi2c + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPI2C driver version 2.1.9. */ +#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) +/*@}*/ + +/*! @brief Timeout times for waiting flag. */ +#ifndef LPI2C_WAIT_TIMEOUT +#define LPI2C_WAIT_TIMEOUT 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief LPI2C status return codes. */ +enum _lpi2c_status +{ + kStatus_LPI2C_Busy = MAKE_STATUS(kStatusGroup_LPI2C, 0), /*!< The master is already performing a transfer. */ + kStatus_LPI2C_Idle = MAKE_STATUS(kStatusGroup_LPI2C, 1), /*!< The slave driver is idle. */ + kStatus_LPI2C_Nak = MAKE_STATUS(kStatusGroup_LPI2C, 2), /*!< The slave device sent a NAK in response to a byte. */ + kStatus_LPI2C_FifoError = MAKE_STATUS(kStatusGroup_LPI2C, 3), /*!< FIFO under run or overrun. */ + kStatus_LPI2C_BitError = MAKE_STATUS(kStatusGroup_LPI2C, 4), /*!< Transferred bit was not seen on the bus. */ + kStatus_LPI2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_LPI2C, 5), /*!< Arbitration lost error. */ + kStatus_LPI2C_PinLowTimeout = + MAKE_STATUS(kStatusGroup_LPI2C, 6), /*!< SCL or SDA were held low longer than the timeout. */ + kStatus_LPI2C_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_LPI2C, 7), /*!< Attempt to abort a transfer when one is not in progress. */ + kStatus_LPI2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_LPI2C, 8), /*!< DMA request failed. */ + kStatus_LPI2C_Timeout = MAKE_STATUS(kStatusGroup_LPI2C, 9), /*!< Timeout poling status flags. */ +}; + +/*! @} */ + +/*! + * @addtogroup lpi2c_master_driver + * @{ + */ + +/*! + * @brief LPI2C master peripheral flags. + * + * The following status register flags can be cleared: + * - #kLPI2C_MasterEndOfPacketFlag + * - #kLPI2C_MasterStopDetectFlag + * - #kLPI2C_MasterNackDetectFlag + * - #kLPI2C_MasterArbitrationLostFlag + * - #kLPI2C_MasterFifoErrFlag + * - #kLPI2C_MasterPinLowTimeoutFlag + * - #kLPI2C_MasterDataMatchFlag + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _lpi2c_master_flags +{ + kLPI2C_MasterTxReadyFlag = LPI2C_MSR_TDF_MASK, /*!< Transmit data flag */ + kLPI2C_MasterRxReadyFlag = LPI2C_MSR_RDF_MASK, /*!< Receive data flag */ + kLPI2C_MasterEndOfPacketFlag = LPI2C_MSR_EPF_MASK, /*!< End Packet flag */ + kLPI2C_MasterStopDetectFlag = LPI2C_MSR_SDF_MASK, /*!< Stop detect flag */ + kLPI2C_MasterNackDetectFlag = LPI2C_MSR_NDF_MASK, /*!< NACK detect flag */ + kLPI2C_MasterArbitrationLostFlag = LPI2C_MSR_ALF_MASK, /*!< Arbitration lost flag */ + kLPI2C_MasterFifoErrFlag = LPI2C_MSR_FEF_MASK, /*!< FIFO error flag */ + kLPI2C_MasterPinLowTimeoutFlag = LPI2C_MSR_PLTF_MASK, /*!< Pin low timeout flag */ + kLPI2C_MasterDataMatchFlag = LPI2C_MSR_DMF_MASK, /*!< Data match flag */ + kLPI2C_MasterBusyFlag = LPI2C_MSR_MBF_MASK, /*!< Master busy flag */ + kLPI2C_MasterBusBusyFlag = LPI2C_MSR_BBF_MASK /*!< Bus busy flag */ +}; + +/*! @brief Direction of master and slave transfers. */ +typedef enum _lpi2c_direction +{ + kLPI2C_Write = 0U, /*!< Master transmit. */ + kLPI2C_Read = 1U /*!< Master receive. */ +} lpi2c_direction_t; + +/*! @brief LPI2C pin configuration. */ +typedef enum _lpi2c_master_pin_config +{ + kLPI2C_2PinOpenDrain = 0x0U, /*!< LPI2C Configured for 2-pin open drain mode */ + kLPI2C_2PinOutputOnly = 0x1U, /*!< LPI2C Configured for 2-pin output only mode (ultra-fast mode) */ + kLPI2C_2PinPushPull = 0x2U, /*!< LPI2C Configured for 2-pin push-pull mode */ + kLPI2C_4PinPushPull = 0x3U, /*!< LPI2C Configured for 4-pin push-pull mode */ + kLPI2C_2PinOpenDrainWithSeparateSlave = + 0x4U, /*!< LPI2C Configured for 2-pin open drain mode with separate LPI2C slave */ + kLPI2C_2PinOutputOnlyWithSeparateSlave = + 0x5U, /*!< LPI2C Configured for 2-pin output only mode(ultra-fast mode) with separate LPI2C slave */ + kLPI2C_2PinPushPullWithSeparateSlave = + 0x6U, /*!< LPI2C Configured for 2-pin push-pull mode with separate LPI2C slave */ + kLPI2C_4PinPushPullWithInvertedOutput = 0x7U /*!< LPI2C Configured for 4-pin push-pull mode(inverted outputs) */ +} lpi2c_master_pin_config_t; + +/*! @brief LPI2C master host request selection. */ +typedef enum _lpi2c_host_request_source +{ + kLPI2C_HostRequestExternalPin = 0x0U, /*!< Select the LPI2C_HREQ pin as the host request input */ + kLPI2C_HostRequestInputTrigger = 0x1U, /*!< Select the input trigger as the host request input */ +} lpi2c_host_request_source_t; + +/*! @brief LPI2C master host request pin polarity configuration. */ +typedef enum _lpi2c_host_request_polarity +{ + kLPI2C_HostRequestPinActiveLow = 0x0U, /*!< Configure the LPI2C_HREQ pin active low */ + kLPI2C_HostRequestPinActiveHigh = 0x1U /*!< Configure the LPI2C_HREQ pin active high */ +} lpi2c_host_request_polarity_t; + +/*! + * @brief Structure with settings to initialize the LPI2C master module. + * + * This structure holds configuration settings for the LPI2C peripheral. To initialize this + * structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _lpi2c_master_config +{ + bool enableMaster; /*!< Whether to enable master mode. */ + bool enableDoze; /*!< Whether master is enabled in doze mode. */ + bool debugEnable; /*!< Enable transfers to continue when halted in debug mode. */ + bool ignoreAck; /*!< Whether to ignore ACK/NACK. */ + lpi2c_master_pin_config_t pinConfig; /*!< The pin configuration option. */ + uint32_t baudRate_Hz; /*!< Desired baud rate in Hertz. */ + uint32_t busIdleTimeout_ns; /*!< Bus idle timeout in nanoseconds. Set to 0 to disable. */ + uint32_t pinLowTimeout_ns; /*!< Pin low timeout in nanoseconds. Set to 0 to disable. */ + uint8_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SDA pin. Set to 0 to disable. */ + uint8_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SCL pin. Set to 0 to disable. */ + struct + { + bool enable; /*!< Enable host request. */ + lpi2c_host_request_source_t source; /*!< Host request source. */ + lpi2c_host_request_polarity_t polarity; /*!< Host request pin polarity. */ + } hostRequest; /*!< Host request options. */ +} lpi2c_master_config_t; + +/*! @brief LPI2C master data match configuration modes. */ +typedef enum _lpi2c_data_match_config_mode +{ + kLPI2C_MatchDisabled = 0x0U, /*!< LPI2C Match Disabled */ + kLPI2C_1stWordEqualsM0OrM1 = 0x2U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0 OR MATCH1 */ + kLPI2C_AnyWordEqualsM0OrM1 = 0x3U, /*!< LPI2C Match Enabled and any data word equals MATCH0 OR MATCH1 */ + kLPI2C_1stWordEqualsM0And2ndWordEqualsM1 = + 0x4U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0, 2nd data equals MATCH1 */ + kLPI2C_AnyWordEqualsM0AndNextWordEqualsM1 = + 0x5U, /*!< LPI2C Match Enabled and any data word equals MATCH0, next data equals MATCH1 */ + kLPI2C_1stWordAndM1EqualsM0AndM1 = + 0x6U, /*!< LPI2C Match Enabled and 1st data word and MATCH0 equals MATCH0 and MATCH1 */ + kLPI2C_AnyWordAndM1EqualsM0AndM1 = + 0x7U /*!< LPI2C Match Enabled and any data word and MATCH0 equals MATCH0 and MATCH1 */ +} lpi2c_data_match_config_mode_t; + +/*! @brief LPI2C master data match configuration structure. */ +typedef struct _lpi2c_match_config +{ + lpi2c_data_match_config_mode_t matchMode; /*!< Data match configuration setting. */ + bool rxDataMatchOnly; /*!< When set to true, received data is ignored until a successful match. */ + uint32_t match0; /*!< Match value 0. */ + uint32_t match1; /*!< Match value 1. */ +} lpi2c_data_match_config_t; + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _lpi2c_master_transfer lpi2c_master_transfer_t; +typedef struct _lpi2c_master_handle lpi2c_master_handle_t; + +/*! + * @brief Master completion callback function pointer type. + * + * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use + * in the call to LPI2C_MasterTransferCreateHandle(). + * + * @param base The LPI2C peripheral base address. + * @param completionStatus Either #kStatus_Success or an error code describing how the transfer completed. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_master_transfer_callback_t)(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! + * @brief Transfer option flags. + * + * @note These enumerations are intended to be OR'd together to form a bit mask of options for + * the #_lpi2c_master_transfer::flags field. + */ +enum _lpi2c_master_transfer_flags +{ + kLPI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kLPI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ + kLPI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ + kLPI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ +}; + +/*! + * @brief Non-blocking transfer descriptor structure. + * + * This structure is used to pass transaction parameters to the LPI2C_MasterTransferNonBlocking() API. + */ +struct _lpi2c_master_transfer +{ + uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_lpi2c_master_transfer_flags for + available options. Set to 0 or #kLPI2C_TransferDefaultFlag for normal transfers. */ + uint16_t slaveAddress; /*!< The 7-bit slave address. */ + lpi2c_direction_t direction; /*!< Either #kLPI2C_Read or #kLPI2C_Write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ + void *data; /*!< Pointer to data to transfer. */ + size_t dataSize; /*!< Number of bytes to transfer. */ +}; + +/*! + * @brief Driver handle for master non-blocking APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_master_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint16_t remainingBytes; /*!< Remaining byte count in current state. */ + uint8_t *buf; /*!< Buffer pointer for current state. */ + uint16_t commandBuffer[7]; /*!< LPI2C command sequence. */ + lpi2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + lpi2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ +}; + +/*! @} */ + +/*! + * @addtogroup lpi2c_slave_driver + * @{ + */ + +/*! + * @brief LPI2C slave peripheral flags. + * + * The following status register flags can be cleared: + * - #kLPI2C_SlaveRepeatedStartDetectFlag + * - #kLPI2C_SlaveStopDetectFlag + * - #kLPI2C_SlaveBitErrFlag + * - #kLPI2C_SlaveFifoErrFlag + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @note These enumerations are meant to be OR'd together to form a bit mask. + */ +enum _lpi2c_slave_flags +{ + kLPI2C_SlaveTxReadyFlag = LPI2C_SSR_TDF_MASK, /*!< Transmit data flag */ + kLPI2C_SlaveRxReadyFlag = LPI2C_SSR_RDF_MASK, /*!< Receive data flag */ + kLPI2C_SlaveAddressValidFlag = LPI2C_SSR_AVF_MASK, /*!< Address valid flag */ + kLPI2C_SlaveTransmitAckFlag = LPI2C_SSR_TAF_MASK, /*!< Transmit ACK flag */ + kLPI2C_SlaveRepeatedStartDetectFlag = LPI2C_SSR_RSF_MASK, /*!< Repeated start detect flag */ + kLPI2C_SlaveStopDetectFlag = LPI2C_SSR_SDF_MASK, /*!< Stop detect flag */ + kLPI2C_SlaveBitErrFlag = LPI2C_SSR_BEF_MASK, /*!< Bit error flag */ + kLPI2C_SlaveFifoErrFlag = LPI2C_SSR_FEF_MASK, /*!< FIFO error flag */ + kLPI2C_SlaveAddressMatch0Flag = LPI2C_SSR_AM0F_MASK, /*!< Address match 0 flag */ + kLPI2C_SlaveAddressMatch1Flag = LPI2C_SSR_AM1F_MASK, /*!< Address match 1 flag */ + kLPI2C_SlaveGeneralCallFlag = LPI2C_SSR_GCF_MASK, /*!< General call flag */ + kLPI2C_SlaveBusyFlag = LPI2C_SSR_SBF_MASK, /*!< Master busy flag */ + kLPI2C_SlaveBusBusyFlag = LPI2C_SSR_BBF_MASK, /*!< Bus busy flag */ +}; + +/*! @brief LPI2C slave address match options. */ +typedef enum _lpi2c_slave_address_match +{ + kLPI2C_MatchAddress0 = 0U, /*!< Match only address 0. */ + kLPI2C_MatchAddress0OrAddress1 = 2U, /*!< Match either address 0 or address 1. */ + kLPI2C_MatchAddress0ThroughAddress1 = 6U, /*!< Match a range of slave addresses from address 0 through address 1. */ +} lpi2c_slave_address_match_t; + +/*! + * @brief Structure with settings to initialize the LPI2C slave module. + * + * This structure holds configuration settings for the LPI2C slave peripheral. To initialize this + * structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _lpi2c_slave_config +{ + bool enableSlave; /*!< Enable slave mode. */ + uint8_t address0; /*!< Slave's 7-bit address. */ + uint8_t address1; /*!< Alternate slave 7-bit address. */ + lpi2c_slave_address_match_t addressMatchMode; /*!< Address matching options. */ + bool filterDozeEnable; /*!< Enable digital glitch filter in doze mode. */ + bool filterEnable; /*!< Enable digital glitch filter. */ + bool enableGeneralCall; /*!< Enable general call address matching. */ + struct + { + bool enableAck; /*!< Enables SCL clock stretching during slave-transmit address byte(s) + and slave-receiver address and data byte(s) to allow software to + write the Transmit ACK Register before the ACK or NACK is transmitted. + Clock stretching occurs when transmitting the 9th bit. When + enableAckSCLStall is enabled, there is no need to set either + enableRxDataSCLStall or enableAddressSCLStall. */ + bool enableTx; /*!< Enables SCL clock stretching when the transmit data flag is set + during a slave-transmit transfer. */ + bool enableRx; /*!< Enables SCL clock stretching when receive data flag is set during + a slave-receive transfer. */ + bool enableAddress; /*!< Enables SCL clock stretching when the address valid flag is asserted. */ + } sclStall; + bool ignoreAck; /*!< Continue transfers after a NACK is detected. */ + bool enableReceivedAddressRead; /*!< Enable reading the address received address as the first byte of data. */ + uint32_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SDA signal. */ + uint32_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SCL signal. */ + uint32_t dataValidDelay_ns; /*!< Width in nanoseconds of the data valid delay. */ + uint32_t clockHoldTime_ns; /*!< Width in nanoseconds of the clock hold time. */ +} lpi2c_slave_config_t; + +/*! + * @brief Set of events sent to the callback for non blocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _lpi2c_slave_transfer_event +{ + kLPI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kLPI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit + (slave-transmitter role). */ + kLPI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kLPI2C_SlaveTransmitAckEvent = 0x08U, /*!< Callback needs to either transmit an ACK or NACK. */ + kLPI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */ + kLPI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected, completing the transfer. */ + + /*! Bit mask of all available events. */ + kLPI2C_SlaveAllEvents = kLPI2C_SlaveAddressMatchEvent | kLPI2C_SlaveTransmitEvent | kLPI2C_SlaveReceiveEvent | + kLPI2C_SlaveTransmitAckEvent | kLPI2C_SlaveRepeatedStartEvent | kLPI2C_SlaveCompletionEvent, +} lpi2c_slave_transfer_event_t; + +/*! @brief LPI2C slave transfer structure */ +typedef struct _lpi2c_slave_transfer +{ + lpi2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ + uint8_t receivedAddress; /*!< Matching address send by master. */ + uint8_t *data; /*!< Transfer buffer */ + size_t dataSize; /*!< Transfer size */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kLPI2C_SlaveCompletionEvent. */ + size_t transferredCount; /*!< Number of bytes actually transferred since start or last repeated start. */ +} lpi2c_slave_transfer_t; + +/* Forward declaration. */ +typedef struct _lpi2c_slave_handle lpi2c_slave_handle_t; + +/*! + * @brief Slave event callback function pointer type. + * + * This callback is used only for the slave non-blocking transfer API. To install a callback, + * use the LPI2C_SlaveSetCallback() function after you have created a handle. + * + * @param base Base address for the LPI2C instance on which the event occurred. + * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_slave_transfer_callback_t)(LPI2C_Type *base, lpi2c_slave_transfer_t *transfer, void *userData); + +/*! + * @brief LPI2C slave handle structure. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_slave_handle +{ + lpi2c_slave_transfer_t transfer; /*!< LPI2C slave transfer copy. */ + bool isBusy; /*!< Whether transfer is busy. */ + bool wasTransmit; /*!< Whether the last transfer was a transmit. */ + uint32_t eventMask; /*!< Mask of enabled events. */ + uint32_t transferredCount; /*!< Count of bytes transferred. */ + lpi2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup lpi2c_master_driver + * @{ + */ + +/*! @name Initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the LPI2C master peripheral. + * + * This function provides the following default configuration for the LPI2C master peripheral: + * @code + * masterConfig->enableMaster = true; + * masterConfig->debugEnable = false; + * masterConfig->ignoreAck = false; + * masterConfig->pinConfig = kLPI2C_2PinOpenDrain; + * masterConfig->baudRate_Hz = 100000U; + * masterConfig->busIdleTimeout_ns = 0; + * masterConfig->pinLowTimeout_ns = 0; + * masterConfig->sdaGlitchFilterWidth_ns = 0; + * masterConfig->sclGlitchFilterWidth_ns = 0; + * masterConfig->hostRequest.enable = false; + * masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; + * masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with LPI2C_MasterInit(). + * + * @param[out] masterConfig User provided configuration structure for default values. Refer to #lpi2c_master_config_t. + */ +void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig); + +/*! + * @brief Initializes the LPI2C master peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * @param base The LPI2C peripheral base address. + * @param masterConfig User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * @param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz); + +/*! + * @brief Deinitializes the LPI2C master peripheral. + * + * This function disables the LPI2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +void LPI2C_MasterDeinit(LPI2C_Type *base); + +/*! + * @brief Configures LPI2C master data match feature. + * + * @param base The LPI2C peripheral base address. + * @param config Settings for the data match feature. + */ +void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *config); + +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status); + +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_CheckForBusyBus(LPI2C_Type *base); + +/*! + * @brief Performs a software reset. + * + * Restores the LPI2C master peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +static inline void LPI2C_MasterReset(LPI2C_Type *base) +{ + base->MCR = LPI2C_MCR_RST_MASK; + base->MCR = 0; +} + +/*! + * @brief Enables or disables the LPI2C module as master. + * + * @param base The LPI2C peripheral base address. + * @param enable Pass true to enable or false to disable the specified LPI2C as master. + */ +static inline void LPI2C_MasterEnable(LPI2C_Type *base, bool enable) +{ + base->MCR = (base->MCR & ~LPI2C_MCR_MEN_MASK) | LPI2C_MCR_MEN(enable); +} + +/*@}*/ + +/*! @name Status */ +/*@{*/ + +/*! + * @brief Gets the LPI2C master status flags. + * + * A bit mask with the state of all LPI2C master status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _lpi2c_master_flags + */ +static inline uint32_t LPI2C_MasterGetStatusFlags(LPI2C_Type *base) +{ + return base->MSR; +} + +/*! + * @brief Clears the LPI2C master status flag state. + * + * The following status register flags can be cleared: + * - #kLPI2C_MasterEndOfPacketFlag + * - #kLPI2C_MasterStopDetectFlag + * - #kLPI2C_MasterNackDetectFlag + * - #kLPI2C_MasterArbitrationLostFlag + * - #kLPI2C_MasterFifoErrFlag + * - #kLPI2C_MasterPinLowTimeoutFlag + * - #kLPI2C_MasterDataMatchFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The LPI2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_lpi2c_master_flags enumerators OR'd together. You may pass the result of a previous call to + * LPI2C_MasterGetStatusFlags(). + * @see _lpi2c_master_flags. + */ +static inline void LPI2C_MasterClearStatusFlags(LPI2C_Type *base, uint32_t statusMask) +{ + base->MSR = statusMask; +} + +/*@}*/ + +/*! @name Interrupts */ +/*@{*/ + +/*! + * @brief Enables the LPI2C master interrupt requests. + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_lpi2c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_MasterEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->MIER |= interruptMask; +} + +/*! + * @brief Disables the LPI2C master interrupt requests. + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_lpi2c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_MasterDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->MIER &= ~interruptMask; +} + +/*! + * @brief Returns the set of currently enabled LPI2C master interrupt requests. + * + * @param base The LPI2C peripheral base address. + * @return A bitmask composed of #_lpi2c_master_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t LPI2C_MasterGetEnabledInterrupts(LPI2C_Type *base) +{ + return base->MIER; +} + +/*@}*/ + +/*! @name DMA control */ +/*@{*/ + +/*! + * @brief Enables or disables LPI2C master DMA requests. + * + * @param base The LPI2C peripheral base address. + * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable. + * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable. + */ +static inline void LPI2C_MasterEnableDMA(LPI2C_Type *base, bool enableTx, bool enableRx) +{ + base->MDER = LPI2C_MDER_TDDE(enableTx) | LPI2C_MDER_RDDE(enableRx); +} + +/*! + * @brief Gets LPI2C master transmit data register address for DMA transfer. + * + * @param base The LPI2C peripheral base address. + * @return The LPI2C Master Transmit Data Register address. + */ +static inline uint32_t LPI2C_MasterGetTxFifoAddress(LPI2C_Type *base) +{ + return (uint32_t)&base->MTDR; +} + +/*! + * @brief Gets LPI2C master receive data register address for DMA transfer. + * + * @param base The LPI2C peripheral base address. + * @return The LPI2C Master Receive Data Register address. + */ +static inline uint32_t LPI2C_MasterGetRxFifoAddress(LPI2C_Type *base) +{ + return (uint32_t)&base->MRDR; +} + +/*@}*/ + +/*! @name FIFO control */ +/*@{*/ + +/*! + * @brief Sets the watermarks for LPI2C master FIFOs. + * + * @param base The LPI2C peripheral base address. + * @param txWords Transmit FIFO watermark value in words. The #kLPI2C_MasterTxReadyFlag flag is set whenever + * the number of words in the transmit FIFO is equal or less than @a txWords. Writing a value equal or + * greater than the FIFO size is truncated. + * @param rxWords Receive FIFO watermark value in words. The #kLPI2C_MasterRxReadyFlag flag is set whenever + * the number of words in the receive FIFO is greater than @a rxWords. Writing a value equal or greater + * than the FIFO size is truncated. + */ +static inline void LPI2C_MasterSetWatermarks(LPI2C_Type *base, size_t txWords, size_t rxWords) +{ + base->MFCR = LPI2C_MFCR_TXWATER(txWords) | LPI2C_MFCR_RXWATER(rxWords); +} + +/*! + * @brief Gets the current number of words in the LPI2C master FIFOs. + * + * @param base The LPI2C peripheral base address. + * @param[out] txCount Pointer through which the current number of words in the transmit FIFO is returned. + * Pass NULL if this value is not required. + * @param[out] rxCount Pointer through which the current number of words in the receive FIFO is returned. + * Pass NULL if this value is not required. + */ +static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount, size_t *txCount) +{ + if (txCount) + { + *txCount = (base->MFSR & LPI2C_MFSR_TXCOUNT_MASK) >> LPI2C_MFSR_TXCOUNT_SHIFT; + } + if (rxCount) + { + *rxCount = (base->MFSR & LPI2C_MFSR_RXCOUNT_MASK) >> LPI2C_MFSR_RXCOUNT_SHIFT; + } +} + +/*@}*/ + +/*! @name Bus operations */ +/*@{*/ + +/*! + * @brief Sets the I2C bus frequency for master transactions. + * + * The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * @note Please note that the second parameter is the clock frequency of LPI2C module, the third + * parameter means user configured bus baudrate, this implementation is different from other I2C drivers + * which use baudrate configuration as second parameter and source clock frequency as third parameter. + * + * @param base The LPI2C peripheral base address. + * @param sourceClock_Hz LPI2C functional clock frequency in Hertz. + * @param baudRate_Hz Requested bus frequency in Hertz. + */ +void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz); + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the master mode to be enabled. + * + * @param base The LPI2C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool LPI2C_MasterGetBusIdleState(LPI2C_Type *base) +{ + return (base->MSR & LPI2C_MSR_BBF_MASK) >> LPI2C_MSR_BBF_SHIFT; +} + +/*! + * @brief Sends a START signal and slave address on the I2C bus. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the @a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * @param base The LPI2C peripheral base address. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + */ +status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir); + +/*! + * @brief Sends a repeated START signal and slave address on the I2C bus. + * + * This function is used to send a Repeated START signal when a transfer is already in progress. Like + * LPI2C_MasterStart(), it also sends the specified 7-bit address. + * + * @note This function exists primarily to maintain compatible APIs between LPI2C and I2C drivers, + * as well as to better document the intent of code that uses these APIs. + * + * @param base The LPI2C peripheral base address. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + */ +static inline status_t LPI2C_MasterRepeatedStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir) +{ + return LPI2C_MasterStart(base, address, dir); +} + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_LPI2C_Nak. + * + * @param base The LPI2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @retval #kStatus_Success Data was sent successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or over run. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @retval #kStatus_Success Data was received successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * This function does not return until the STOP signal is seen on the bus, or an error occurs. + * + * @param base The LPI2C peripheral base address. + * @retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterStop(LPI2C_Type *base); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to error happens during transfer. + * + * @param base The LPI2C peripheral base address. + * @param transfer Pointer to the transfer structure. + * @retval #kStatus_Success Data was received successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer); + +/*@}*/ + +/*! @name Non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the LPI2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called. + * + * + * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * + * @param base The LPI2C peripheral base address. + * @param[out] handle Pointer to the LPI2C master driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking transaction on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param transfer The pointer to the transfer descriptor. + * @retval #kStatus_Success The transaction was started successfully. + * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_t *transfer); + +/*! + * @brief Returns number of bytes transferred so far. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval #kStatus_Success + * @retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking LPI2C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * LPI2C peripheral's IRQ priority. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @retval #kStatus_Success A transaction was successfully aborted. + * @retval #kStatus_LPI2C_Idle There is not a non-blocking transaction currently in progress. + */ +void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle); + +/*@}*/ + +/*! @name IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle master interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + */ +void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, lpi2c_master_handle_t *handle); + +/*@}*/ + +/*! @} */ + +/*! + * @addtogroup lpi2c_slave_driver + * @{ + */ + +/*! @name Slave initialization and deinitialization */ +/*@{*/ + +/*! + * @brief Provides a default configuration for the LPI2C slave peripheral. + * + * This function provides the following default configuration for the LPI2C slave peripheral: + * @code + * slaveConfig->enableSlave = true; + * slaveConfig->address0 = 0U; + * slaveConfig->address1 = 0U; + * slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; + * slaveConfig->filterDozeEnable = true; + * slaveConfig->filterEnable = true; + * slaveConfig->enableGeneralCall = false; + * slaveConfig->sclStall.enableAck = false; + * slaveConfig->sclStall.enableTx = true; + * slaveConfig->sclStall.enableRx = true; + * slaveConfig->sclStall.enableAddress = true; + * slaveConfig->ignoreAck = false; + * slaveConfig->enableReceivedAddressRead = false; + * slaveConfig->sdaGlitchFilterWidth_ns = 0; + * slaveConfig->sclGlitchFilterWidth_ns = 0; + * slaveConfig->dataValidDelay_ns = 0; + * slaveConfig->clockHoldTime_ns = 0; + * @endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the @a + * address0 member of the configuration structure with the desired slave address. + * + * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #lpi2c_slave_config_t. + */ +void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig); + +/*! + * @brief Initializes the LPI2C slave peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user + * provided configuration. + * + * @param base The LPI2C peripheral base address. + * @param slaveConfig User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * @param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, + * data valid delay, and clock hold time. + */ +void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz); + +/*! + * @brief Deinitializes the LPI2C slave peripheral. + * + * This function disables the LPI2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +void LPI2C_SlaveDeinit(LPI2C_Type *base); + +/*! + * @brief Performs a software reset of the LPI2C slave peripheral. + * + * @param base The LPI2C peripheral base address. + */ +static inline void LPI2C_SlaveReset(LPI2C_Type *base) +{ + base->SCR = LPI2C_SCR_RST_MASK; + base->SCR = 0; +} + +/*! + * @brief Enables or disables the LPI2C module as slave. + * + * @param base The LPI2C peripheral base address. + * @param enable Pass true to enable or false to disable the specified LPI2C as slave. + */ +static inline void LPI2C_SlaveEnable(LPI2C_Type *base, bool enable) +{ + base->SCR = (base->SCR & ~LPI2C_SCR_SEN_MASK) | LPI2C_SCR_SEN(enable); +} + +/*@}*/ + +/*! @name Slave status */ +/*@{*/ + +/*! + * @brief Gets the LPI2C slave status flags. + * + * A bit mask with the state of all LPI2C slave status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _lpi2c_slave_flags + */ +static inline uint32_t LPI2C_SlaveGetStatusFlags(LPI2C_Type *base) +{ + return base->SSR; +} + +/*! + * @brief Clears the LPI2C status flag state. + * + * The following status register flags can be cleared: + * - #kLPI2C_SlaveRepeatedStartDetectFlag + * - #kLPI2C_SlaveStopDetectFlag + * - #kLPI2C_SlaveBitErrFlag + * - #kLPI2C_SlaveFifoErrFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The LPI2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_lpi2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to + * LPI2C_SlaveGetStatusFlags(). + * @see _lpi2c_slave_flags. + */ +static inline void LPI2C_SlaveClearStatusFlags(LPI2C_Type *base, uint32_t statusMask) +{ + base->SSR = statusMask; +} + +/*@}*/ + +/*! @name Slave interrupts */ +/*@{*/ + +/*! + * @brief Enables the LPI2C slave interrupt requests. + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_lpi2c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_SlaveEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->SIER |= interruptMask; +} + +/*! + * @brief Disables the LPI2C slave interrupt requests. + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_lpi2c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_SlaveDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->SIER &= ~interruptMask; +} + +/*! + * @brief Returns the set of currently enabled LPI2C slave interrupt requests. + * @param base The LPI2C peripheral base address. + * @return A bitmask composed of #_lpi2c_slave_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(LPI2C_Type *base) +{ + return base->SIER; +} + +/*@}*/ + +/*! @name Slave DMA control */ +/*@{*/ + +/*! + * @brief Enables or disables the LPI2C slave peripheral DMA requests. + * + * @param base The LPI2C peripheral base address. + * @param enableAddressValid Enable flag for the address valid DMA request. Pass true for enable, false for disable. + * The address valid DMA request is shared with the receive data DMA request. + * @param enableRx Enable flag for the receive data DMA request. Pass true for enable, false for disable. + * @param enableTx Enable flag for the transmit data DMA request. Pass true for enable, false for disable. + */ +static inline void LPI2C_SlaveEnableDMA(LPI2C_Type *base, bool enableAddressValid, bool enableRx, bool enableTx) +{ + base->SDER = (base->SDER & ~(LPI2C_SDER_AVDE_MASK | LPI2C_SDER_RDDE_MASK | LPI2C_SDER_TDDE_MASK)) | + LPI2C_SDER_AVDE(enableAddressValid) | LPI2C_SDER_RDDE(enableRx) | LPI2C_SDER_TDDE(enableTx); +} + +/*@}*/ + +/*! @name Slave bus operations */ +/*@{*/ + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the slave mode to be enabled. + * + * @param base The LPI2C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool LPI2C_SlaveGetBusIdleState(LPI2C_Type *base) +{ + return (base->SSR & LPI2C_SSR_BBF_MASK) >> LPI2C_SSR_BBF_SHIFT; +} + +/*! + * @brief Transmits either an ACK or NAK on the I2C bus in response to a byte from the master. + * + * Use this function to send an ACK or NAK when the #kLPI2C_SlaveTransmitAckFlag is asserted. This + * only happens if you enable the sclStall.enableAck field of the ::lpi2c_slave_config_t configuration + * structure used to initialize the slave peripheral. + * + * @param base The LPI2C peripheral base address. + * @param ackOrNack Pass true for an ACK or false for a NAK. + */ +static inline void LPI2C_SlaveTransmitAck(LPI2C_Type *base, bool ackOrNack) +{ + base->STAR = LPI2C_STAR_TXNACK(!ackOrNack); +} + +/*! + * @brief Returns the slave address sent by the I2C master. + * + * This function should only be called if the #kLPI2C_SlaveAddressValidFlag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return The 8-bit address matched by the LPI2C slave. Bit 0 contains the R/w direction bit, and + * the 7-bit slave address is in the upper 7 bits. + */ +static inline uint32_t LPI2C_SlaveGetReceivedAddress(LPI2C_Type *base) +{ + return base->SASR & LPI2C_SASR_RADDR_MASK; +} + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param[out] actualTxSize + * @return Error or success status returned by API. + */ +status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @param[out] actualRxSize + * @return Error or success status returned by API. + */ +status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize); + +/*@}*/ + +/*! @name Slave non-blocking */ +/*@{*/ + +/*! + * @brief Creates a new handle for the LPI2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called. + * + * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + + * @param base The LPI2C peripheral base address. + * @param[out] handle Pointer to the LPI2C slave driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, + lpi2c_slave_handle_t *handle, + lpi2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kLPI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kLPI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #lpi2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kLPI2C_SlaveAllEvents to enable all events. + * + * @retval #kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_LPI2C_Busy Slave transfers have already been started on this handle. + */ +status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Gets the slave transfer status during a non-blocking transfer. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure. + * @param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not + * required. + * @retval #kStatus_Success + * @retval #kStatus_NoTransferInProgress + */ +status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count); + +/*! + * @brief Aborts the slave non-blocking transfers. + * @note This API could be called at any time to stop slave for handling the bus events. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_Idle + */ +void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle); + +/*@}*/ + +/*! @name Slave IRQ handler */ +/*@{*/ + +/*! + * @brief Reusable routine to handle slave interrupts. + * @note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + */ +void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle); + +/*@}*/ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_LPI2C_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpi2c_edma.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpi2c_edma.c new file mode 100644 index 0000000000..e8de4a1c89 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpi2c_edma.c @@ -0,0 +1,510 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpi2c_edma.h" +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpi2c_edma" +#endif + +/* @brief Mask to align an address to 32 bytes. */ +#define ALIGN_32_MASK (0x1fU) + +/*! @brief Common sets of flags used by the driver. */ +enum _lpi2c_flag_constants +{ + /*! All flags which are cleared by the driver upon starting a transfer. */ + kMasterClearFlags = kLPI2C_MasterEndOfPacketFlag | kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | + kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | kLPI2C_MasterPinLowTimeoutFlag | + kLPI2C_MasterDataMatchFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kMasterIrqFlags = kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterTxReadyFlag | kLPI2C_MasterRxReadyFlag | + kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | kLPI2C_MasterPinLowTimeoutFlag | + kLPI2C_MasterFifoErrFlag, + + /*! Errors to check for. */ + kMasterErrorFlags = kLPI2C_MasterNackDetectFlag | kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | + kLPI2C_MasterPinLowTimeoutFlag, + + /*! All flags which are cleared by the driver upon starting a transfer. */ + kSlaveClearFlags = kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveBitErrFlag | + kLPI2C_SlaveFifoErrFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kSlaveIrqFlags = kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | + kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag | + kLPI2C_SlaveTransmitAckFlag | kLPI2C_SlaveAddressValidFlag, + + /*! Errors to check for. */ + kSlaveErrorFlags = kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag, +}; + +/* ! @brief LPI2C master fifo commands. */ +enum _lpi2c_master_fifo_cmd +{ + kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */ + kRxDataCmd = LPI2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */ + kStopCmd = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */ + kStartCmd = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */ +}; + +/*! @brief States for the state machine used by transactional APIs. */ +enum _lpi2c_transfer_states +{ + kIdleState = 0, + kSendCommandState, + kIssueReadCommandState, + kTransferDataState, + kStopState, + kWaitForCompletionState, +}; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*lpi2c_isr_t)(LPI2C_Type *base, void *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle); + +static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, bool isTransferDone, uint32_t tcds); + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Create a new handle for the LPI2C master DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called. + * + * For devices where the LPI2C send and receive DMA requests are OR'd together, the a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * param base The LPI2C peripheral base address. + * param[out] handle Pointer to the LPI2C master driver handle. + * param rxDmaHandle Handle for the eDMA receive channel. Created by the user prior to calling this function. + * param txDmaHandle Handle for the eDMA transmit channel. Created by the user prior to calling this function. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle, + lpi2c_master_edma_transfer_callback_t callback, + void *userData) +{ + assert(handle); + assert(rxDmaHandle); + assert(txDmaHandle); + + /* Clear out the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set up the handle. For combined rx/tx DMA requests, the tx channel handle is set to the rx handle */ + /* in order to make the transfer API code simpler. */ + handle->base = base; + handle->completionCallback = callback; + handle->userData = userData; + handle->rx = rxDmaHandle; + handle->tx = FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) ? txDmaHandle : rxDmaHandle; + + /* Set DMA channel completion callbacks. */ + EDMA_SetCallback(handle->rx, LPI2C_MasterEDMACallback, handle); + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + EDMA_SetCallback(handle->tx, LPI2C_MasterEDMACallback, handle); + } +} + +/*! + * @brief Prepares the command buffer with the sequence of commands needed to send the requested transaction. + * @param handle Master DMA driver handle. + * @return Number of command words. + */ +static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle) +{ + lpi2c_master_transfer_t *xfer = &handle->transfer; + uint16_t *cmd = (uint16_t *)&handle->commandBuffer; + uint32_t cmdCount = 0; + + /* Handle no start option. */ + if (xfer->flags & kLPI2C_TransferNoStartFlag) + { + if (xfer->direction == kLPI2C_Read) + { + /* Need to issue read command first. */ + cmd[cmdCount++] = kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1); + } + } + else + { + /* + * Initial direction depends on whether a subaddress was provided, and of course the actual + * data transfer direction. + */ + lpi2c_direction_t direction = xfer->subaddressSize ? kLPI2C_Write : xfer->direction; + + /* Start command. */ + cmd[cmdCount++] = + (uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)direction); + + /* Subaddress, MSB first. */ + if (xfer->subaddressSize) + { + uint32_t subaddressRemaining = xfer->subaddressSize; + while (subaddressRemaining--) + { + uint8_t subaddressByte = (xfer->subaddress >> (8 * subaddressRemaining)) & 0xff; + cmd[cmdCount++] = subaddressByte; + } + } + + /* Reads need special handling because we have to issue a read command and maybe a repeated start. */ + if ((xfer->dataSize) && (xfer->direction == kLPI2C_Read)) + { + /* Need to send repeated start if switching directions to read. */ + if (direction == kLPI2C_Write) + { + cmd[cmdCount++] = (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); + } + + /* Read command. */ + cmd[cmdCount++] = kRxDataCmd | LPI2C_MTDR_DATA(xfer->dataSize - 1); + } + } + + return cmdCount; +} + +/*! + * brief Performs a non-blocking DMA-based transaction on the I2C bus. + * + * The callback specified when the a handle was created is invoked when the transaction has + * completed. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param transfer The pointer to the transfer descriptor. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + lpi2c_master_transfer_t *transfer) +{ + status_t result; + + assert(handle); + assert(transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + /* Return busy if another transaction is in progress. */ + if (handle->isBusy) + { + return kStatus_LPI2C_Busy; + } + + /* Return an error if the bus is already in use not by us. */ + result = LPI2C_CheckForBusyBus(base); + if (result) + { + return result; + } + + /* We're now busy. */ + handle->isBusy = true; + + /* Disable LPI2C IRQ and DMA sources while we configure stuff. */ + LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags); + LPI2C_MasterEnableDMA(base, false, false); + + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, kMasterClearFlags); + + /* Save transfer into handle. */ + handle->transfer = *transfer; + + /* Generate commands to send. */ + uint32_t commandCount = LPI2C_GenerateCommands(handle); + + /* If the user is transmitting no data with no start or stop, then just go ahead and invoke the callback. */ + if ((!commandCount) && (transfer->dataSize == 0)) + { + if (handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_Success, handle->userData); + } + return kStatus_Success; + } + + /* Reset DMA channels. */ + EDMA_ResetChannel(handle->rx->base, handle->rx->channel); + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + EDMA_ResetChannel(handle->tx->base, handle->tx->channel); + } + + /* Get a 32-byte aligned TCD pointer. */ + edma_tcd_t *tcd = (edma_tcd_t *)((uint32_t)(&handle->tcds[1]) & (~ALIGN_32_MASK)); + + bool hasSendData = (transfer->direction == kLPI2C_Write) && (transfer->dataSize); + bool hasReceiveData = (transfer->direction == kLPI2C_Read) && (transfer->dataSize); + + edma_transfer_config_t transferConfig; + edma_tcd_t *linkTcd = NULL; + + /* Set up data transmit. */ + if (hasSendData) + { + transferConfig.srcAddr = (uint32_t)transfer->data; + transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base); + transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.srcOffset = sizeof(uint8_t); + transferConfig.destOffset = 0; + transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to fill fifo */ + transferConfig.majorLoopCounts = transfer->dataSize; + + /* Store the initially configured eDMA minor byte transfer count into the LPI2C handle */ + handle->nbytes = transferConfig.minorLoopBytes; + + if (commandCount) + { + /* Create a software TCD, which will be chained after the commands. */ + EDMA_TcdReset(tcd); + EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL); + EDMA_TcdEnableInterrupts(tcd, kEDMA_MajorInterruptEnable); + linkTcd = tcd; + } + else + { + /* User is only transmitting data with no required commands, so this transfer can stand alone. */ + EDMA_SetTransferConfig(handle->tx->base, handle->tx->channel, &transferConfig, NULL); + EDMA_EnableChannelInterrupts(handle->tx->base, handle->tx->channel, kEDMA_MajorInterruptEnable); + } + } + else if (hasReceiveData) + { + /* Set up data receive. */ + transferConfig.srcAddr = (uint32_t)LPI2C_MasterGetRxFifoAddress(base); + transferConfig.destAddr = (uint32_t)transfer->data; + transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.srcOffset = 0; + transferConfig.destOffset = sizeof(uint8_t); + transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to empty fifo */ + transferConfig.majorLoopCounts = transfer->dataSize; + + /* Store the initially configured eDMA minor byte transfer count into the LPI2C handle */ + handle->nbytes = transferConfig.minorLoopBytes; + + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) || (!commandCount)) + { + /* We can put this receive transfer on its own DMA channel. */ + EDMA_SetTransferConfig(handle->rx->base, handle->rx->channel, &transferConfig, NULL); + EDMA_EnableChannelInterrupts(handle->rx->base, handle->rx->channel, kEDMA_MajorInterruptEnable); + } + else + { + /* For shared rx/tx DMA requests when there are commands, create a software TCD which will be */ + /* chained onto the commands transfer, notice that in this situation assume tx/rx uses same channel */ + EDMA_TcdReset(tcd); + EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL); + EDMA_TcdEnableInterrupts(tcd, kEDMA_MajorInterruptEnable); + linkTcd = tcd; + } + } + else + { + /* No data to send */ + } + + /* Set up commands transfer. */ + if (commandCount) + { + transferConfig.srcAddr = (uint32_t)handle->commandBuffer; + transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base); + transferConfig.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfig.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfig.srcOffset = sizeof(uint16_t); + transferConfig.destOffset = 0; + transferConfig.minorLoopBytes = sizeof(uint16_t); /* TODO optimize to fill fifo */ + transferConfig.majorLoopCounts = commandCount; + + EDMA_SetTransferConfig(handle->tx->base, handle->tx->channel, &transferConfig, linkTcd); + } + + /* Start DMA transfer. */ + if (hasReceiveData || !FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + EDMA_StartTransfer(handle->rx); + } + + if (hasReceiveData && !FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + EDMA_EnableChannelInterrupts(handle->tx->base, handle->tx->channel, kEDMA_MajorInterruptEnable); + } + + if ((hasSendData || commandCount) && FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + EDMA_StartTransfer(handle->tx); + } + + /* Enable DMA in both directions. This actually kicks of the transfer. */ + LPI2C_MasterEnableDMA(base, true, true); + + return result; +} + +/*! + * brief Returns number of bytes transferred so far. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param[out] count Number of bytes transferred so far by the non-blocking transaction. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress There is not a DMA transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + uint32_t remaining = handle->transfer.dataSize; + + /* If the DMA is still on a commands transfer that chains to the actual data transfer, */ + /* we do nothing and return the number of transferred bytes as zero. */ + if (EDMA_GetNextTCDAddress(handle->tx) == 0) + { + if (handle->transfer.direction == kLPI2C_Write) + { + remaining = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->tx->base, handle->tx->channel); + } + else + { + remaining = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->rx->base, handle->rx->channel); + } + } + + *count = handle->transfer.dataSize - remaining; + + return kStatus_Success; +} + +/*! + * brief Terminates a non-blocking LPI2C master transmission early. + * + * note It is not safe to call this function from an IRQ handler that has a higher priority than the + * eDMA peripheral's IRQ priority. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * retval #kStatus_Success A transaction was successfully aborted. + * retval #kStatus_LPI2C_Idle There is not a DMA transaction currently in progress. + */ +status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle) +{ + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + return kStatus_LPI2C_Idle; + } + + /* Terminate DMA transfers. */ + EDMA_AbortTransfer(handle->rx); + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + EDMA_AbortTransfer(handle->tx); + } + + /* Reset fifos. */ + base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + + /* Send a stop command to finalize the transfer. */ + base->MTDR = kStopCmd; + + /* Reset handle. */ + handle->isBusy = false; + + return kStatus_Success; +} + +/*! + * @brief DMA completion callback. + * @param dmaHandle DMA channel handle for the channel that completed. + * @param userData User data associated with the channel handle. For this callback, the user data is the + * LPI2C DMA driver handle. + * @param isTransferDone Whether the DMA transfer has completed. + * @param tcds Number of TCDs that completed. + */ +static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, bool isTransferDone, uint32_t tcds) +{ + lpi2c_master_edma_handle_t *handle = (lpi2c_master_edma_handle_t *)userData; + bool hasReceiveData; + + if (!handle) + { + return; + } + + hasReceiveData = (handle->transfer.direction == kLPI2C_Read) && (handle->transfer.dataSize); + + if (hasReceiveData && !FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base)) + { + if (EDMA_GetNextTCDAddress(handle->tx) != 0) + { + LPI2C_MasterEnableDMA(handle->base, false, true); + } + } + + /* Check for errors. */ + status_t result = LPI2C_MasterCheckAndClearError(handle->base, LPI2C_MasterGetStatusFlags(handle->base)); + + /* Done with this transaction. */ + handle->isBusy = false; + + if (!(handle->transfer.flags & kLPI2C_TransferNoStopFlag)) + { + /* Send a stop command to finalize the transfer. */ + handle->base->MTDR = kStopCmd; + } + + /* Invoke callback. */ + if (handle->completionCallback) + { + handle->completionCallback(handle->base, handle, result, handle->userData); + } +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpi2c_edma.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpi2c_edma.h new file mode 100644 index 0000000000..30d528e555 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpi2c_edma.h @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_LPI2C_EDMA_H_ +#define _FSL_LPI2C_EDMA_H_ + +#include "fsl_lpi2c.h" +#include "fsl_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPI2C EDMA driver version 2.1.5. */ +#define FSL_LPI2C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 5)) +/*@}*/ + +/*! + * @addtogroup lpi2c_master_edma_driver + * @{ + */ + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _lpi2c_master_edma_handle lpi2c_master_edma_handle_t; + +/*! + * @brief Master DMA completion callback function pointer type. + * + * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use + * in the call to LPI2C_MasterCreateEDMAHandle(). + * + * @param base The LPI2C peripheral base address. + * @param handle Handle associated with the completed transfer. + * @param completionStatus Either #kStatus_Success or an error code describing how the transfer completed. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_master_edma_transfer_callback_t)(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! + * @brief Driver handle for master DMA APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_master_edma_handle +{ + LPI2C_Type *base; /*!< LPI2C base pointer. */ + bool isBusy; /*!< Transfer state machine current state. */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + uint16_t commandBuffer[7]; /*!< LPI2C command sequence. */ + lpi2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + lpi2c_master_edma_transfer_callback_t completionCallback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ + edma_handle_t *rx; /*!< Handle for receive DMA channel. */ + edma_handle_t *tx; /*!< Handle for transmit DMA channel. */ + edma_tcd_t tcds[2]; /*!< Software TCD. Two are allocated to provide enough room to align to 32-bytes. */ +}; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup lpi2c_master_edma_driver + * @{ + */ + +/*! @name Master DMA */ +/*@{*/ + +/*! + * @brief Create a new handle for the LPI2C master DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called. + * + * For devices where the LPI2C send and receive DMA requests are OR'd together, the @a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * @param base The LPI2C peripheral base address. + * @param[out] handle Pointer to the LPI2C master driver handle. + * @param rxDmaHandle Handle for the eDMA receive channel. Created by the user prior to calling this function. + * @param txDmaHandle Handle for the eDMA transmit channel. Created by the user prior to calling this function. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle, + lpi2c_master_edma_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking DMA-based transaction on the I2C bus. + * + * The callback specified when the @a handle was created is invoked when the transaction has + * completed. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param transfer The pointer to the transfer descriptor. + * @retval #kStatus_Success The transaction was started successfully. + * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + lpi2c_master_transfer_t *transfer); + +/*! + * @brief Returns number of bytes transferred so far. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval #kStatus_Success + * @retval #kStatus_NoTransferInProgress There is not a DMA transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking LPI2C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * eDMA peripheral's IRQ priority. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @retval #kStatus_Success A transaction was successfully aborted. + * @retval #kStatus_LPI2C_Idle There is not a DMA transaction currently in progress. + */ +status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle); + +/*@}*/ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_LPI2C_EDMA_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpspi.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpspi.c new file mode 100644 index 0000000000..dbfbe38c98 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpspi.c @@ -0,0 +1,2099 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpspi.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpspi" +#endif + +/*! + * @brief Default watermark values. + * + * The default watermarks are set to zero. + */ +enum _lpspi_default_watermarks +{ + kLpspiDefaultTxWatermark = 0, + kLpspiDefaultRxWatermark = 0, +}; + +/*! @brief Typedef for master interrupt handler. */ +typedef void (*lpspi_master_isr_t)(LPSPI_Type *base, lpspi_master_handle_t *handle); + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*lpspi_slave_isr_t)(LPSPI_Type *base, lpspi_slave_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get instance number for LPSPI module. + * + * @param base LPSPI peripheral base address. + * @return Return the value of LPSPI instance. + */ +uint32_t LPSPI_GetInstance(LPSPI_Type *base); + +/*! + * @brief Configures the LPSPI peripheral chip select polarity. + * + * This function takes in the desired peripheral chip select (Pcs) and it's corresponding desired polarity and + * configures the Pcs signal to operate with the desired characteristic. + * + * @param base LPSPI peripheral address. + * @param pcs The particular peripheral chip select (parameter value is of type lpspi_which_pcs_t) for which we wish to + * apply the active high or active low characteristic. + * @param activeLowOrHigh The setting for either "active high, inactive low (0)" or "active low, inactive high(1)" of + * type lpspi_pcs_polarity_config_t. + */ +static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base, + lpspi_which_pcs_t pcs, + lpspi_pcs_polarity_config_t activeLowOrHigh); + +/*! + * @brief Combine the write data for 1 byte to 4 bytes. + * This is not a public API. + */ +static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint32_t bytesEachWrite, bool isByteSwap); + +/*! + * @brief Separate the read data for 1 byte to 4 bytes. + * This is not a public API. + */ +static void LPSPI_SeparateReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap); + +/*! + * @brief Master fill up the TX FIFO with data. + * This is not a public API. + */ +static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_handle_t *handle); + +/*! + * @brief Master finish up a transfer. + * It would call back if there is callback function and set the state to idle. + * This is not a public API. + */ +static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t *handle); + +/*! + * @brief Slave fill up the TX FIFO with data. + * This is not a public API. + */ +static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle_t *handle); + +/*! + * @brief Slave finish up a transfer. + * It would call back if there is callback function and set the state to idle. + * This is not a public API. + */ +static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *handle); + +/*! + * @brief LPSPI common interrupt handler. + * + * @param handle pointer to s_lpspiHandle which stores the transfer state. + */ +static void LPSPI_CommonIRQHandler(LPSPI_Type *base, void *param); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/ +static const uint8_t s_baudratePrescaler[] = {1, 2, 4, 8, 16, 32, 64, 128}; + +/*! @brief Pointers to lpspi bases for each instance. */ +static LPSPI_Type *const s_lpspiBases[] = LPSPI_BASE_PTRS; + +/*! @brief Pointers to lpspi IRQ number for each instance. */ +static const IRQn_Type s_lpspiIRQ[] = LPSPI_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to lpspi clocks for each instance. */ +static const clock_ip_name_t s_lpspiClocks[] = LPSPI_CLOCKS; + +#if defined(LPSPI_PERIPH_CLOCKS) +static const clock_ip_name_t s_LpspiPeriphClocks[] = LPSPI_PERIPH_CLOCKS; +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to lpspi handles for each instance. */ +static void *s_lpspiHandle[ARRAY_SIZE(s_lpspiBases)] = {NULL}; + +/*! @brief Pointer to master IRQ handler for each instance. */ +static lpspi_master_isr_t s_lpspiMasterIsr; +/*! @brief Pointer to slave IRQ handler for each instance. */ +static lpspi_slave_isr_t s_lpspiSlaveIsr; +/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/ +volatile uint8_t g_lpspiDummyData[ARRAY_SIZE(s_lpspiBases)] = {0}; +/********************************************************************************************************************** + * Code + *********************************************************************************************************************/ +uint32_t LPSPI_GetInstance(LPSPI_Type *base) +{ + uint8_t instance = 0; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_lpspiBases); instance++) + { + if (s_lpspiBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_lpspiBases)); + + return instance; +} + +/*! + * brief Set up the dummy data. + * + * param base LPSPI peripheral address. + * param dummyData Data to be transferred when tx buffer is NULL. + * Note: + * This API has no effect when LPSPI in slave interrupt mode, because driver + * will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit + * FIFO and output pin is tristated. + */ +void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData) +{ + uint32_t instance = LPSPI_GetInstance(base); + g_lpspiDummyData[instance] = dummyData; +} + +/*! + * brief Initializes the LPSPI master. + * + * param base LPSPI peripheral address. + * param masterConfig Pointer to structure lpspi_master_config_t. + * param srcClock_Hz Module source input clock in Hertz + */ +void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(masterConfig); + + uint32_t tcrPrescaleValue = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPSPI_GetInstance(base); + /* Enable LPSPI clock */ + CLOCK_EnableClock(s_lpspiClocks[instance]); + +#if defined(LPSPI_PERIPH_CLOCKS) + CLOCK_EnableClock(s_LpspiPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Set LPSPI to master */ + LPSPI_SetMasterSlaveMode(base, kLPSPI_Master); + + /* Set specific PCS to active high or low */ + LPSPI_SetOnePcsPolarity(base, masterConfig->whichPcs, masterConfig->pcsActiveHighOrLow); + + /* Set Configuration Register 1 related setting.*/ + base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOSTALL_MASK)) | + LPSPI_CFGR1_OUTCFG(masterConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(masterConfig->pinCfg) | + LPSPI_CFGR1_NOSTALL(0); + + /* Set baudrate and delay times*/ + LPSPI_MasterSetBaudRate(base, masterConfig->baudRate, srcClock_Hz, &tcrPrescaleValue); + + /* Set default watermarks */ + LPSPI_SetFifoWatermarks(base, kLpspiDefaultTxWatermark, kLpspiDefaultRxWatermark); + + /* Set Transmit Command Register*/ + base->TCR = LPSPI_TCR_CPOL(masterConfig->cpol) | LPSPI_TCR_CPHA(masterConfig->cpha) | + LPSPI_TCR_LSBF(masterConfig->direction) | LPSPI_TCR_FRAMESZ(masterConfig->bitsPerFrame - 1) | + LPSPI_TCR_PRESCALE(tcrPrescaleValue) | LPSPI_TCR_PCS(masterConfig->whichPcs); + + LPSPI_Enable(base, true); + + LPSPI_MasterSetDelayTimes(base, masterConfig->pcsToSckDelayInNanoSec, kLPSPI_PcsToSck, srcClock_Hz); + LPSPI_MasterSetDelayTimes(base, masterConfig->lastSckToPcsDelayInNanoSec, kLPSPI_LastSckToPcs, srcClock_Hz); + LPSPI_MasterSetDelayTimes(base, masterConfig->betweenTransferDelayInNanoSec, kLPSPI_BetweenTransfer, srcClock_Hz); + + LPSPI_SetDummyData(base, LPSPI_DUMMY_DATA); +} + +/*! + * brief Sets the lpspi_master_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_MasterInit(). + * The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified + * before calling the LPSPI_MasterInit(). + * Example: + * code + * lpspi_master_config_t masterConfig; + * LPSPI_MasterGetDefaultConfig(&masterConfig); + * endcode + * param masterConfig pointer to lpspi_master_config_t structure + */ +void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig) +{ + assert(masterConfig); + + /* Initializes the configure structure to zero. */ + memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->baudRate = 500000; + masterConfig->bitsPerFrame = 8; + masterConfig->cpol = kLPSPI_ClockPolarityActiveHigh; + masterConfig->cpha = kLPSPI_ClockPhaseFirstEdge; + masterConfig->direction = kLPSPI_MsbFirst; + + masterConfig->pcsToSckDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; + masterConfig->lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; + masterConfig->betweenTransferDelayInNanoSec = 1000000000 / masterConfig->baudRate * 2; + + masterConfig->whichPcs = kLPSPI_Pcs0; + masterConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; + + masterConfig->pinCfg = kLPSPI_SdiInSdoOut; + masterConfig->dataOutConfig = kLpspiDataOutRetained; +} + +/*! + * brief LPSPI slave configuration. + * + * param base LPSPI peripheral address. + * param slaveConfig Pointer to a structure lpspi_slave_config_t. + */ +void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPSPI_GetInstance(base); + /* Enable LPSPI clock */ + CLOCK_EnableClock(s_lpspiClocks[instance]); + +#if defined(LPSPI_PERIPH_CLOCKS) + CLOCK_EnableClock(s_LpspiPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + LPSPI_SetMasterSlaveMode(base, kLPSPI_Slave); + + LPSPI_SetOnePcsPolarity(base, slaveConfig->whichPcs, slaveConfig->pcsActiveHighOrLow); + + base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK)) | + LPSPI_CFGR1_OUTCFG(slaveConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(slaveConfig->pinCfg); + + LPSPI_SetFifoWatermarks(base, kLpspiDefaultTxWatermark, kLpspiDefaultRxWatermark); + + base->TCR = LPSPI_TCR_CPOL(slaveConfig->cpol) | LPSPI_TCR_CPHA(slaveConfig->cpha) | + LPSPI_TCR_LSBF(slaveConfig->direction) | LPSPI_TCR_FRAMESZ(slaveConfig->bitsPerFrame - 1); + + /* This operation will set the dummy data for edma transfer, no effect in interrupt way. */ + LPSPI_SetDummyData(base, LPSPI_DUMMY_DATA); + + LPSPI_Enable(base, true); +} + +/*! + * brief Sets the lpspi_slave_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_SlaveInit(). + * The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified + * before calling the LPSPI_SlaveInit(). + * Example: + * code + * lpspi_slave_config_t slaveConfig; + * LPSPI_SlaveGetDefaultConfig(&slaveConfig); + * endcode + * param slaveConfig pointer to lpspi_slave_config_t structure. + */ +void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig) +{ + assert(slaveConfig); + + /* Initializes the configure structure to zero. */ + memset(slaveConfig, 0, sizeof(*slaveConfig)); + + slaveConfig->bitsPerFrame = 8; /*!< Bits per frame, minimum 8, maximum 4096.*/ + slaveConfig->cpol = kLPSPI_ClockPolarityActiveHigh; /*!< Clock polarity. */ + slaveConfig->cpha = kLPSPI_ClockPhaseFirstEdge; /*!< Clock phase. */ + slaveConfig->direction = kLPSPI_MsbFirst; /*!< MSB or LSB data shift direction. */ + + slaveConfig->whichPcs = kLPSPI_Pcs0; /*!< Desired Peripheral Chip Select (pcs) */ + slaveConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; /*!< Desired PCS active high or low */ + + slaveConfig->pinCfg = kLPSPI_SdiInSdoOut; + slaveConfig->dataOutConfig = kLpspiDataOutRetained; +} + +/*! + * brief Restores the LPSPI peripheral to reset state. Note that this function + * sets all registers to reset state. As a result, the LPSPI module can't work after calling + * this API. + * param base LPSPI peripheral address. + */ +void LPSPI_Reset(LPSPI_Type *base) +{ + /* Reset all internal logic and registers, except the Control Register. Remains set until cleared by software.*/ + base->CR |= LPSPI_CR_RST_MASK; + + /* Software reset doesn't reset the CR, so manual reset the FIFOs */ + base->CR |= LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK; + + /* Master logic is not reset and module is disabled.*/ + base->CR = 0x00U; +} + +/*! + * brief De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock. + * param base LPSPI peripheral address. + */ +void LPSPI_Deinit(LPSPI_Type *base) +{ + /* Reset to default value */ + LPSPI_Reset(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPSPI_GetInstance(base); + /* Enable LPSPI clock */ + CLOCK_DisableClock(s_lpspiClocks[instance]); + +#if defined(LPSPI_PERIPH_CLOCKS) + CLOCK_DisableClock(s_LpspiPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base, + lpspi_which_pcs_t pcs, + lpspi_pcs_polarity_config_t activeLowOrHigh) +{ + uint32_t cfgr1Value = 0; + /* Clear the PCS polarity bit */ + cfgr1Value = base->CFGR1 & ~(1U << (LPSPI_CFGR1_PCSPOL_SHIFT + pcs)); + + /* Configure the PCS polarity bit according to the activeLowOrHigh setting */ + base->CFGR1 = cfgr1Value | ((uint32_t)activeLowOrHigh << (LPSPI_CFGR1_PCSPOL_SHIFT + pcs)); +} + +/*! + * brief Sets the LPSPI baud rate in bits per second. + * + * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest + * possible baud rate without exceeding the desired baud rate and returns the + * calculated baud rate in bits-per-second. It requires the caller to provide + * the frequency of the module source clock (in Hertz). Note that the baud rate + * does not go into effect until the Transmit Control Register (TCR) is programmed + * with the prescale value. Hence, this function returns the prescale tcrPrescaleValue + * parameter for later programming in the TCR. The higher level + * peripheral driver should alert the user of an out of range baud rate input. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * param base LPSPI peripheral address. + * param baudRate_Bps The desired baud rate in bits per second. + * param srcClock_Hz Module source input clock in Hertz. + * param tcrPrescaleValue The TCR prescale value needed to program the TCR. + * return The actual calculated baud rate. This function may also return a "0" if the + * LPSPI is not configured for master mode or if the LPSPI module is not disabled. + */ + +uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, + uint32_t baudRate_Bps, + uint32_t srcClock_Hz, + uint32_t *tcrPrescaleValue) +{ + assert(tcrPrescaleValue); + + /* For master mode configuration only, if slave mode detected, return 0. + * Also, the LPSPI module needs to be disabled first, if enabled, return 0 + */ + if ((!LPSPI_IsMaster(base)) || (base->CR & LPSPI_CR_MEN_MASK)) + { + return 0; + } + + uint32_t prescaler, bestPrescaler; + uint32_t scaler, bestScaler; + uint32_t realBaudrate, bestBaudrate; + uint32_t diff, min_diff; + uint32_t desiredBaudrate = baudRate_Bps; + + /* find combination of prescaler and scaler resulting in baudrate closest to the + * requested value + */ + min_diff = 0xFFFFFFFFU; + + /* Set to maximum divisor value bit settings so that if baud rate passed in is less + * than the minimum possible baud rate, then the SPI will be configured to the lowest + * possible baud rate + */ + bestPrescaler = 7; + bestScaler = 255; + + bestBaudrate = 0; /* required to avoid compilation warning */ + + /* In all for loops, if min_diff = 0, the exit for loop*/ + for (prescaler = 0; (prescaler < 8) && min_diff; prescaler++) + { + for (scaler = 0; (scaler < 256) && min_diff; scaler++) + { + realBaudrate = (srcClock_Hz / (s_baudratePrescaler[prescaler] * (scaler + 2U))); + + /* calculate the baud rate difference based on the conditional statement + * that states that the calculated baud rate must not exceed the desired baud rate + */ + if (desiredBaudrate >= realBaudrate) + { + diff = desiredBaudrate - realBaudrate; + if (min_diff > diff) + { + /* a better match found */ + min_diff = diff; + bestPrescaler = prescaler; + bestScaler = scaler; + bestBaudrate = realBaudrate; + } + } + } + } + + /* Write the best baud rate scalar to the CCR. + * Note, no need to check for error since we've already checked to make sure the module is + * disabled and in master mode. Also, there is a limit on the maximum divider so we will not + * exceed this. + */ + base->CCR = (base->CCR & ~LPSPI_CCR_SCKDIV_MASK) | LPSPI_CCR_SCKDIV(bestScaler); + + /* return the best prescaler value for user to use later */ + *tcrPrescaleValue = bestPrescaler; + + /* return the actual calculated baud rate */ + return bestBaudrate; +} + +/*! + * brief Manually configures a specific LPSPI delay parameter (module must be disabled to + * change the delay values). + * + * This function configures the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay along with the delay value. + * This allows the user to directly set the delay values if they have + * pre-calculated them or if they simply wish to manually increment the value. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * param base LPSPI peripheral address. + * param scaler The 8-bit delay value 0x00 to 0xFF (255). + * param whichDelay The desired delay to configure, must be of type lpspi_delay_type_t. + */ +void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay) +{ + /*These settings are only relevant in master mode */ + switch (whichDelay) + { + case kLPSPI_PcsToSck: + base->CCR = (base->CCR & (~LPSPI_CCR_PCSSCK_MASK)) | LPSPI_CCR_PCSSCK(scaler); + + break; + case kLPSPI_LastSckToPcs: + base->CCR = (base->CCR & (~LPSPI_CCR_SCKPCS_MASK)) | LPSPI_CCR_SCKPCS(scaler); + + break; + case kLPSPI_BetweenTransfer: + base->CCR = (base->CCR & (~LPSPI_CCR_DBT_MASK)) | LPSPI_CCR_DBT(scaler); + + break; + default: + assert(false); + break; + } +} + +/*! + * brief Calculates the delay based on the desired delay input in nanoseconds (module must be + * disabled to change the delay values). + * + * This function calculates the values for the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay and the desired delay value in + * nano-seconds. The function calculates the value needed for the desired delay parameter + * and returns the actual calculated delay because an exact delay match may not be possible. In this + * case, the closest match is calculated without going below the desired delay value input. + * It is possible to input a very large delay value that exceeds the capability of the part, in + * which case the maximum supported delay is returned. It is up to the higher level + * peripheral driver to alert the user of an out of range delay input. + * + * Note that the LPSPI module must be configured for master mode before configuring this. And note that + * the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler). + * + * param base LPSPI peripheral address. + * param delayTimeInNanoSec The desired delay value in nano-seconds. + * param whichDelay The desired delay to configuration, which must be of type lpspi_delay_type_t. + * param srcClock_Hz Module source input clock in Hertz. + * return actual Calculated delay value in nano-seconds. + */ +uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, + uint32_t delayTimeInNanoSec, + lpspi_delay_type_t whichDelay, + uint32_t srcClock_Hz) +{ + uint64_t realDelay, bestDelay; + uint32_t scaler, bestScaler; + uint32_t diff, min_diff; + uint64_t initialDelayNanoSec; + uint32_t clockDividedPrescaler; + + /* For delay between transfer, an additional scaler value is needed */ + uint32_t additionalScaler = 0; + + /*As the RM note, the LPSPI baud rate clock is itself divided by the PRESCALE setting, which can vary between + * transfers.*/ + clockDividedPrescaler = + srcClock_Hz / s_baudratePrescaler[(base->TCR & LPSPI_TCR_PRESCALE_MASK) >> LPSPI_TCR_PRESCALE_SHIFT]; + + /* Find combination of prescaler and scaler resulting in the delay closest to the requested value.*/ + min_diff = 0xFFFFFFFFU; + + /* Initialize scaler to max value to generate the max delay */ + bestScaler = 0xFFU; + + /* Calculate the initial (min) delay and maximum possible delay based on the specific delay as + * the delay divisors are slightly different based on which delay we are configuring. + */ + if (whichDelay == kLPSPI_BetweenTransfer) + { + /* First calculate the initial, default delay, note min delay is 2 clock cycles. Due to large size of + calculated values (uint64_t), we need to break up the calculation into several steps to ensure + accurate calculated results + */ + initialDelayNanoSec = 1000000000U; + initialDelayNanoSec *= 2U; + initialDelayNanoSec /= clockDividedPrescaler; + + /* Calculate the maximum delay */ + bestDelay = 1000000000U; + bestDelay *= 257U; /* based on DBT+2, or 255 + 2 */ + bestDelay /= clockDividedPrescaler; + + additionalScaler = 1U; + } + else + { + /* First calculate the initial, default delay, min delay is 1 clock cycle. Due to large size of calculated + values (uint64_t), we need to break up the calculation into several steps to ensure accurate calculated + results. + */ + initialDelayNanoSec = 1000000000U; + initialDelayNanoSec /= clockDividedPrescaler; + + /* Calculate the maximum delay */ + bestDelay = 1000000000U; + bestDelay *= 256U; /* based on SCKPCS+1 or PCSSCK+1, or 255 + 1 */ + bestDelay /= clockDividedPrescaler; + + additionalScaler = 0; + } + + /* If the initial, default delay is already greater than the desired delay, then + * set the delay to their initial value (0) and return the delay. In other words, + * there is no way to decrease the delay value further. + */ + if (initialDelayNanoSec >= delayTimeInNanoSec) + { + LPSPI_MasterSetDelayScaler(base, 0, whichDelay); + return initialDelayNanoSec; + } + + /* If min_diff = 0, the exit for loop */ + for (scaler = 0; (scaler < 256U) && min_diff; scaler++) + { + /* Calculate the real delay value as we cycle through the scaler values. + Due to large size of calculated values (uint64_t), we need to break up the + calculation into several steps to ensure accurate calculated results + */ + realDelay = 1000000000U; + realDelay *= (scaler + 1 + additionalScaler); + realDelay /= clockDividedPrescaler; + + /* calculate the delay difference based on the conditional statement + * that states that the calculated delay must not be less then the desired delay + */ + if (realDelay >= delayTimeInNanoSec) + { + diff = realDelay - delayTimeInNanoSec; + if (min_diff > diff) + { + /* a better match found */ + min_diff = diff; + bestScaler = scaler; + bestDelay = realDelay; + } + } + } + + /* write the best scaler value for the delay */ + LPSPI_MasterSetDelayScaler(base, bestScaler, whichDelay); + + /* return the actual calculated delay value (in ns) */ + return bestDelay; +} + +/*Transactional APIs -- Master*/ + +/*! + * brief Initializes the LPSPI master handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + + * param base LPSPI peripheral address. + * param handle LPSPI handle pointer to lpspi_master_handle_t. + * param callback DSPI callback. + * param userData callback function parameter. + */ +void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, + lpspi_master_handle_t *handle, + lpspi_master_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + s_lpspiHandle[LPSPI_GetInstance(base)] = handle; + + /* Set irq handler. */ + s_lpspiMasterIsr = LPSPI_MasterTransferHandleIRQ; + + handle->callback = callback; + handle->userData = userData; +} + +/*! + * brief Check the argument for transfer . + * + * param transfer the transfer struct to be used. + * param bitPerFrame The bit size of one frame. + * param bytePerFrame The byte size of one frame. + * return Return true for right and false for wrong. + */ +bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame) +{ + assert(transfer); + + /* If the transfer count is zero, then return immediately.*/ + if (transfer->dataSize == 0) + { + return false; + } + + /* If both send buffer and receive buffer is null */ + if ((!(transfer->txData)) && (!(transfer->rxData))) + { + return false; + } + + /*The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4 . + *For bytesPerFrame greater than 4 situation: + *the transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4 , + *otherwise , the transfer data size can be integer multiples of bytesPerFrame. + */ + if (bytesPerFrame <= 4) + { + if ((transfer->dataSize % bytesPerFrame) != 0) + { + return false; + } + } + else + { + if ((bytesPerFrame % 4U) != 0) + { + if (transfer->dataSize != bytesPerFrame) + { + return false; + } + } + else + { + if ((transfer->dataSize % bytesPerFrame) != 0) + { + return false; + } + } + } + + return true; +} + +/*! + * brief LPSPI master transfer data using a polling method. + * + * This function transfers data using a polling method. This is a blocking function, which does not return until all + * transfers have been + * completed. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral address. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer) +{ + assert(transfer); + + uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; + uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; + uint32_t temp = 0U; + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; + + if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) + { + return kStatus_InvalidArgument; + } + + /* Check that LPSPI is not busy.*/ + if (LPSPI_GetStatusFlags(base) & kLPSPI_ModuleBusyFlag) + { + return kStatus_LPSPI_Busy; + } + + uint8_t *txData = transfer->txData; + uint8_t *rxData = transfer->rxData; + uint32_t txRemainingByteCount = transfer->dataSize; + uint32_t rxRemainingByteCount = transfer->dataSize; + + uint8_t bytesEachWrite; + uint8_t bytesEachRead; + + uint32_t readData = 0; + uint32_t wordToSend = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + + /*The TX and RX FIFO sizes are always the same*/ + uint32_t fifoSize = LPSPI_GetRxFifoSize(base); + + uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; + + bool isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous); + bool isRxMask = false; + bool isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); + + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); + + if (!rxData) + { + isRxMask = true; + } + + LPSPI_Enable(base, false); + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ + temp = base->CFGR1; + temp &= LPSPI_CFGR1_PINCFG_MASK; + if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) + { + if (!txData) + { + base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; + } + /* The 3-wire mode can't send and receive data at the same time. */ + if ((txData) && (rxData)) + { + return kStatus_InvalidArgument; + } + } + LPSPI_Enable(base, true); + + base->TCR = + (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_CONT(isPcsContinuous) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(isRxMask) | LPSPI_TCR_PCS(whichPcs); + + if (bytesPerFrame <= 4) + { + bytesEachWrite = bytesPerFrame; + bytesEachRead = bytesPerFrame; + } + else + { + bytesEachWrite = 4; + bytesEachRead = 4; + } + + /*Write the TX data until txRemainingByteCount is equal to 0 */ + while (txRemainingByteCount > 0) + { + if (txRemainingByteCount < bytesEachWrite) + { + bytesEachWrite = txRemainingByteCount; + } + + /*Wait until TX FIFO is not full*/ + while (LPSPI_GetTxFifoCount(base) == fifoSize) + { + } + + if (txData) + { + wordToSend = LPSPI_CombineWriteData(txData, bytesEachWrite, isByteSwap); + txData += bytesEachWrite; + } + + LPSPI_WriteData(base, wordToSend); + txRemainingByteCount -= bytesEachWrite; + + /*Check whether there is RX data in RX FIFO . Read out the RX data so that the RX FIFO would not overrun.*/ + if (rxData) + { + while (LPSPI_GetRxFifoCount(base)) + { + readData = LPSPI_ReadData(base); + if (rxRemainingByteCount < bytesEachRead) + { + bytesEachRead = rxRemainingByteCount; + } + + LPSPI_SeparateReadData(rxData, readData, bytesEachRead, isByteSwap); + rxData += bytesEachRead; + + rxRemainingByteCount -= bytesEachRead; + } + } + } + + /* After write all the data in TX FIFO , should write the TCR_CONTC to 0 to de-assert the PCS. Note that TCR + * register also use the TX FIFO. + */ + while ((LPSPI_GetTxFifoCount(base) == fifoSize)) + { + } + base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); + + /*Read out the RX data in FIFO*/ + if (rxData) + { + while (rxRemainingByteCount > 0) + { + while (LPSPI_GetRxFifoCount(base)) + { + readData = LPSPI_ReadData(base); + + if (rxRemainingByteCount < bytesEachRead) + { + bytesEachRead = rxRemainingByteCount; + } + + LPSPI_SeparateReadData(rxData, readData, bytesEachRead, isByteSwap); + rxData += bytesEachRead; + + rxRemainingByteCount -= bytesEachRead; + } + } + } + else + { + /* If no RX buffer, then transfer is not complete until transfer complete flag sets */ + while (!(LPSPI_GetStatusFlags(base) & kLPSPI_TransferCompleteFlag)) + { + } + } + + return kStatus_Success; +} + +/*! + * brief LPSPI master transfer data using an interrupt method. + * + * This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data + * is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle); + assert(transfer); + + uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; + uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; + uint32_t temp = 0U; + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; + + if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + + handle->state = kLPSPI_Busy; + + bool isRxMask = false; + + uint8_t txWatermark; + + uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; + + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + + handle->writeTcrInIsr = false; + + handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + + handle->txBuffIfNull = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + + handle->isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous); + handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); + + /*Set the RX and TX watermarks to reduce the ISR times.*/ + if (handle->fifoSize > 1) + { + txWatermark = 1; + handle->rxWatermark = handle->fifoSize - 2; + } + else + { + txWatermark = 0; + handle->rxWatermark = 0; + } + + LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark); + + LPSPI_Enable(base, false); + /*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ + temp = base->CFGR1; + temp &= LPSPI_CFGR1_PINCFG_MASK; + if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) + { + if (!handle->txData) + { + base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; + } + /* The 3-wire mode can't send and receive data at the same time. */ + if ((handle->txData) && (handle->rxData)) + { + return kStatus_InvalidArgument; + } + } + LPSPI_Enable(base, true); + + /*Flush FIFO , clear status , disable all the inerrupts.*/ + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); + + /* If there is not rxData , can mask the receive data (receive data is not stored in receive FIFO). + * For master transfer , we'd better not masked the transmit data in TCR since the transfer flow is hard to + * controlled by software.*/ + if (handle->rxData == NULL) + { + isRxMask = true; + handle->rxRemainingByteCount = 0; + } + + base->TCR = + (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_CONT(handle->isPcsContinuous) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(isRxMask) | + LPSPI_TCR_PCS(whichPcs); + + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame <= 4) + { + handle->bytesEachWrite = bytesPerFrame; + handle->bytesEachRead = bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4; + handle->bytesEachRead = 4; + } + + /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , + * and you should also enable the INTMUX interupt in your application. + */ + EnableIRQ(s_lpspiIRQ[LPSPI_GetInstance(base)]); + + /*TCR is also shared the FIFO , so wait for TCR written.*/ + while (LPSPI_GetTxFifoCount(base) != 0) + { + } + /*Fill up the TX data in FIFO */ + LPSPI_MasterTransferFillUpTxFifo(base, handle); + + /* Since SPI is a synchronous interface, we only need to enable the RX interrupt if there is RX data. + * The IRQ handler will get the status of RX and TX interrupt flags. + */ + if (handle->rxData) + { + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there + *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + if ((handle->readRegRemainingTimes) <= handle->rxWatermark) + { + base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(handle->readRegRemainingTimes - 1); + } + + LPSPI_EnableInterrupts(base, kLPSPI_RxInterruptEnable); + } + else + { + LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable); + } + + return kStatus_Success; +} + +static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_handle_t *handle) +{ + assert(handle); + + uint32_t wordToSend = 0; + + /* Make sure the difference in remaining TX and RX byte counts does not exceed FIFO depth + * and that the number of TX FIFO entries does not exceed the FIFO depth. + * But no need to make the protection if there is no rxData. + */ + while ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize)) && + (((handle->readRegRemainingTimes - handle->writeRegRemainingTimes) < handle->fifoSize) || + (handle->rxData == NULL))) + { + if (handle->txRemainingByteCount < handle->bytesEachWrite) + { + handle->bytesEachWrite = handle->txRemainingByteCount; + } + + if (handle->txData) + { + wordToSend = LPSPI_CombineWriteData(handle->txData, handle->bytesEachWrite, handle->isByteSwap); + handle->txData += handle->bytesEachWrite; + } + else + { + wordToSend = handle->txBuffIfNull; + } + + /*Write the word to TX register*/ + LPSPI_WriteData(base, wordToSend); + + /*Decrease the write TX register times.*/ + --handle->writeRegRemainingTimes; + + /*Decrease the remaining TX byte count.*/ + handle->txRemainingByteCount -= handle->bytesEachWrite; + + if (handle->txRemainingByteCount == 0) + { + /* If PCS is continuous, update TCR to de-assert PCS */ + if (handle->isPcsContinuous) + { + /* Only write to the TCR if the FIFO has room */ + if ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize))) + { + base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); + handle->writeTcrInIsr = false; + } + /* Else, set a global flag to tell the ISR to do write to the TCR */ + else + { + handle->writeTcrInIsr = true; + } + } + break; + } + } +} + +static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t *handle) +{ + assert(handle); + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); + + handle->state = kLPSPI_Idle; + + if (handle->callback) + { + handle->callback(base, handle, kStatus_Success, handle->userData); + } +} + +/*! + * brief Gets the master transfer remaining bytes. + * + * This function gets the master transfer remaining bytes. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * return status of status_t. + */ +status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + if (handle->rxData) + { + remainingByte = handle->rxRemainingByteCount; + } + else + { + remainingByte = handle->txRemainingByteCount; + } + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} + +/*! + * brief LPSPI master abort transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle) +{ + assert(handle); + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); + + LPSPI_Reset(base); + + handle->state = kLPSPI_Idle; + handle->txRemainingByteCount = 0; + handle->rxRemainingByteCount = 0; +} + +/*! + * brief LPSPI Master IRQ handler function. + * + * This function processes the LPSPI transmit and receive IRQ. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle) +{ + assert(handle); + + uint32_t readData; + + if (handle->rxData != NULL) + { + if (handle->rxRemainingByteCount) + { + /* First, disable the interrupts to avoid potentially triggering another interrupt + * while reading out the RX FIFO as more data may be coming into the RX FIFO. We'll + * re-enable the interrupts based on the LPSPI state after reading out the FIFO. + */ + LPSPI_DisableInterrupts(base, kLPSPI_RxInterruptEnable); + + while ((LPSPI_GetRxFifoCount(base)) && (handle->rxRemainingByteCount)) + { + /*Read out the data*/ + readData = LPSPI_ReadData(base); + + /*Decrease the read RX register times.*/ + --handle->readRegRemainingTimes; + + if (handle->rxRemainingByteCount < handle->bytesEachRead) + { + handle->bytesEachRead = handle->rxRemainingByteCount; + } + + LPSPI_SeparateReadData(handle->rxData, readData, handle->bytesEachRead, handle->isByteSwap); + handle->rxData += handle->bytesEachRead; + + /*Decrease the remaining RX byte count.*/ + handle->rxRemainingByteCount -= handle->bytesEachRead; + } + + /* Re-enable the interrupts only if rxCount indicates there is more data to receive, + * else we may get a spurious interrupt. + * */ + if (handle->rxRemainingByteCount) + { + /* Set the TDF and RDF interrupt enables simultaneously to avoid race conditions */ + LPSPI_EnableInterrupts(base, kLPSPI_RxInterruptEnable); + } + } + + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there + *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + if ((handle->readRegRemainingTimes) <= (handle->rxWatermark)) + { + base->FCR = + (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | + LPSPI_FCR_RXWATER((handle->readRegRemainingTimes > 1) ? (handle->readRegRemainingTimes - 1U) : (0U)); + } + } + + if (handle->txRemainingByteCount) + { + LPSPI_MasterTransferFillUpTxFifo(base, handle); + } + else + { + if ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize))) + { + if ((handle->isPcsContinuous) && (handle->writeTcrInIsr)) + { + base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); + handle->writeTcrInIsr = false; + } + } + } + + if ((handle->txRemainingByteCount == 0) && (handle->rxRemainingByteCount == 0) && (!handle->writeTcrInIsr)) + { + /* If no RX buffer, then transfer is not complete until transfer complete flag sets */ + if (handle->rxData == NULL) + { + if (LPSPI_GetStatusFlags(base) & kLPSPI_TransferCompleteFlag) + { + /* Complete the transfer and disable the interrupts */ + LPSPI_MasterTransferComplete(base, handle); + } + else + { + LPSPI_EnableInterrupts(base, kLPSPI_TransferCompleteInterruptEnable); + LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable); + } + } + else + { + /* Complete the transfer and disable the interrupts */ + LPSPI_MasterTransferComplete(base, handle); + } + } +} + +/*Transactional APIs -- Slave*/ +/*! + * brief Initializes the LPSPI slave handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * param base LPSPI peripheral address. + * param handle LPSPI handle pointer to lpspi_slave_handle_t. + * param callback DSPI callback. + * param userData callback function parameter. + */ +void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, + lpspi_slave_handle_t *handle, + lpspi_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + s_lpspiHandle[LPSPI_GetInstance(base)] = handle; + + /* Set irq handler. */ + s_lpspiSlaveIsr = LPSPI_SlaveTransferHandleIRQ; + + handle->callback = callback; + handle->userData = userData; +} + +/*! + * brief LPSPI slave transfer data using an interrupt method. + * + * This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data + * is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle); + assert(transfer); + + uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; + uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; + uint32_t temp = 0U; + + if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + handle->state = kLPSPI_Busy; + + bool isRxMask = false; + bool isTxMask = false; + + uint32_t whichPcs = (transfer->configFlags & LPSPI_SLAVE_PCS_MASK) >> LPSPI_SLAVE_PCS_SHIFT; + + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + + handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + + handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_SlaveByteSwap); + + /*Set the RX and TX watermarks to reduce the ISR times.*/ + uint8_t txWatermark; + if (handle->fifoSize > 1) + { + txWatermark = 1; + handle->rxWatermark = handle->fifoSize - 2; + } + else + { + txWatermark = 0; + handle->rxWatermark = 0; + } + LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark); + + /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ + temp = base->CFGR1; + temp &= LPSPI_CFGR1_PINCFG_MASK; + if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) + { + if (!handle->txData) + { + LPSPI_Enable(base, false); + base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; + LPSPI_Enable(base, true); + } + /* The 3-wire mode can't send and receive data at the same time. */ + if ((handle->txData) && (handle->rxData)) + { + return kStatus_InvalidArgument; + } + } + + /*Flush FIFO , clear status , disable all the inerrupts.*/ + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); + + /*If there is not rxData , can mask the receive data (receive data is not stored in receive FIFO).*/ + if (handle->rxData == NULL) + { + isRxMask = true; + handle->rxRemainingByteCount = 0; + } + + /*If there is not txData , can mask the transmit data (no data is loaded from transmit FIFO and output pin + * is tristated). + */ + if (handle->txData == NULL) + { + isTxMask = true; + handle->txRemainingByteCount = 0; + } + + base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | + LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_CONT(0) | LPSPI_TCR_CONTC(0) | LPSPI_TCR_RXMSK(isRxMask) | LPSPI_TCR_TXMSK(isTxMask) | + LPSPI_TCR_PCS(whichPcs); + + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame <= 4) + { + handle->bytesEachWrite = bytesPerFrame; + handle->bytesEachRead = bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4; + handle->bytesEachRead = 4; + } + + /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , + * and you should also enable the INTMUX interupt in your application. + */ + EnableIRQ(s_lpspiIRQ[LPSPI_GetInstance(base)]); + + /*TCR is also shared the FIFO , so wait for TCR written.*/ + while (LPSPI_GetTxFifoCount(base) != 0) + { + } + + /*Fill up the TX data in FIFO */ + if (handle->txData) + { + LPSPI_SlaveTransferFillUpTxFifo(base, handle); + } + + /* Since SPI is a synchronous interface, we only need to enable the RX interrupt if there is RX data. + * The IRQ handler will get the status of RX and TX interrupt flags. + */ + if (handle->rxData) + { + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there + *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + if ((handle->readRegRemainingTimes) <= handle->rxWatermark) + { + base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(handle->readRegRemainingTimes - 1); + } + + LPSPI_EnableInterrupts(base, kLPSPI_RxInterruptEnable); + } + else + { + LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable); + } + + if (handle->rxData) + { + /* RX FIFO overflow request enable */ + LPSPI_EnableInterrupts(base, kLPSPI_ReceiveErrorInterruptEnable); + } + if (handle->txData) + { + /* TX FIFO underflow request enable */ + LPSPI_EnableInterrupts(base, kLPSPI_TransmitErrorInterruptEnable); + } + + return kStatus_Success; +} + +static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle_t *handle) +{ + assert(handle); + + uint32_t wordToSend = 0; + + while (LPSPI_GetTxFifoCount(base) < (handle->fifoSize)) + { + if (handle->txRemainingByteCount < handle->bytesEachWrite) + { + handle->bytesEachWrite = handle->txRemainingByteCount; + } + + wordToSend = LPSPI_CombineWriteData(handle->txData, handle->bytesEachWrite, handle->isByteSwap); + handle->txData += handle->bytesEachWrite; + + /*Decrease the remaining TX byte count.*/ + handle->txRemainingByteCount -= handle->bytesEachWrite; + + /*Write the word to TX register*/ + LPSPI_WriteData(base, wordToSend); + + if (handle->txRemainingByteCount == 0) + { + break; + } + } +} + +static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *handle) +{ + assert(handle); + + status_t status = 0; + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); + + if (handle->state == kLPSPI_Error) + { + status = kStatus_LPSPI_Error; + } + else + { + status = kStatus_Success; + } + + handle->state = kLPSPI_Idle; + + if (handle->callback) + { + handle->callback(base, handle, status, handle->userData); + } +} + +/*! + * brief Gets the slave transfer remaining bytes. + * + * This function gets the slave transfer remaining bytes. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * return status of status_t. + */ +status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + if (handle->rxData) + { + remainingByte = handle->rxRemainingByteCount; + } + else + { + remainingByte = handle->txRemainingByteCount; + } + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} + +/*! + * brief LPSPI slave aborts a transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle) +{ + assert(handle); + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable); + + LPSPI_Reset(base); + + handle->state = kLPSPI_Idle; + handle->txRemainingByteCount = 0; + handle->rxRemainingByteCount = 0; +} + +/*! + * brief LPSPI Slave IRQ handler function. + * + * This function processes the LPSPI transmit and receives an IRQ. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle) +{ + assert(handle); + + uint32_t readData; /* variable to store word read from RX FIFO */ + uint32_t wordToSend; /* variable to store word to write to TX FIFO */ + + if (handle->rxData != NULL) + { + if (handle->rxRemainingByteCount > 0) + { + while (LPSPI_GetRxFifoCount(base)) + { + /*Read out the data*/ + readData = LPSPI_ReadData(base); + + /*Decrease the read RX register times.*/ + --handle->readRegRemainingTimes; + + if (handle->rxRemainingByteCount < handle->bytesEachRead) + { + handle->bytesEachRead = handle->rxRemainingByteCount; + } + + LPSPI_SeparateReadData(handle->rxData, readData, handle->bytesEachRead, handle->isByteSwap); + handle->rxData += handle->bytesEachRead; + + /*Decrease the remaining RX byte count.*/ + handle->rxRemainingByteCount -= handle->bytesEachRead; + + if ((handle->txRemainingByteCount > 0) && (handle->txData != NULL)) + { + if (handle->txRemainingByteCount < handle->bytesEachWrite) + { + handle->bytesEachWrite = handle->txRemainingByteCount; + } + + wordToSend = LPSPI_CombineWriteData(handle->txData, handle->bytesEachWrite, handle->isByteSwap); + handle->txData += handle->bytesEachWrite; + + /*Decrease the remaining TX byte count.*/ + handle->txRemainingByteCount -= handle->bytesEachWrite; + + /*Write the word to TX register*/ + LPSPI_WriteData(base, wordToSend); + } + + if (handle->rxRemainingByteCount == 0) + { + break; + } + } + } + + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there + *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + if ((handle->readRegRemainingTimes) <= (handle->rxWatermark)) + { + base->FCR = + (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | + LPSPI_FCR_RXWATER((handle->readRegRemainingTimes > 1) ? (handle->readRegRemainingTimes - 1U) : (0U)); + } + } + else if ((handle->txRemainingByteCount) && (handle->txData != NULL)) + { + LPSPI_SlaveTransferFillUpTxFifo(base, handle); + } + else + { + __NOP(); + } + + if ((handle->txRemainingByteCount == 0) && (handle->rxRemainingByteCount == 0)) + { + /* If no RX buffer, then transfer is not complete until transfer complete flag sets and the TX FIFO empty*/ + if (handle->rxData == NULL) + { + if ((LPSPI_GetStatusFlags(base) & kLPSPI_FrameCompleteFlag) && (LPSPI_GetTxFifoCount(base) == 0)) + { + /* Complete the transfer and disable the interrupts */ + LPSPI_SlaveTransferComplete(base, handle); + } + else + { + LPSPI_ClearStatusFlags(base, kLPSPI_FrameCompleteFlag); + LPSPI_EnableInterrupts(base, kLPSPI_FrameCompleteInterruptEnable); + LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable); + } + } + else + { + /* Complete the transfer and disable the interrupts */ + LPSPI_SlaveTransferComplete(base, handle); + } + } + + /* Catch tx fifo underflow conditions, service only if tx under flow interrupt enabled */ + if ((LPSPI_GetStatusFlags(base) & kLPSPI_TransmitErrorFlag) && (base->IER & LPSPI_IER_TEIE_MASK)) + { + LPSPI_ClearStatusFlags(base, kLPSPI_TransmitErrorFlag); + /* Change state to error and clear flag */ + if (handle->txData) + { + handle->state = kLPSPI_Error; + } + handle->errorCount++; + } + /* Catch rx fifo overflow conditions, service only if rx over flow interrupt enabled */ + if ((LPSPI_GetStatusFlags(base) & kLPSPI_ReceiveErrorFlag) && (base->IER & LPSPI_IER_REIE_MASK)) + { + LPSPI_ClearStatusFlags(base, kLPSPI_ReceiveErrorFlag); + /* Change state to error and clear flag */ + if (handle->txData) + { + handle->state = kLPSPI_Error; + } + handle->errorCount++; + } +} + +static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint32_t bytesEachWrite, bool isByteSwap) +{ + assert(txData); + + uint32_t wordToSend = 0; + + switch (bytesEachWrite) + { + case 1: + wordToSend = *txData; + ++txData; + break; + + case 2: + if (!isByteSwap) + { + wordToSend = *txData; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + } + else + { + wordToSend = (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= *txData; + ++txData; + } + + break; + + case 3: + if (!isByteSwap) + { + wordToSend = *txData; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= (unsigned)(*txData) << 16U; + ++txData; + } + else + { + wordToSend = (unsigned)(*txData) << 16U; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= *txData; + ++txData; + } + break; + + case 4: + if (!isByteSwap) + { + wordToSend = *txData; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= (unsigned)(*txData) << 16U; + ++txData; + wordToSend |= (unsigned)(*txData) << 24U; + ++txData; + } + else + { + wordToSend = (unsigned)(*txData) << 24U; + ++txData; + wordToSend |= (unsigned)(*txData) << 16U; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= *txData; + ++txData; + } + break; + + default: + assert(false); + break; + } + return wordToSend; +} + +static void LPSPI_SeparateReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap) +{ + assert(rxData); + + switch (bytesEachRead) + { + case 1: + *rxData = readData; + ++rxData; + break; + + case 2: + if (!isByteSwap) + { + *rxData = readData; + ++rxData; + *rxData = readData >> 8; + ++rxData; + } + else + { + *rxData = readData >> 8; + ++rxData; + *rxData = readData; + ++rxData; + } + break; + + case 3: + if (!isByteSwap) + { + *rxData = readData; + ++rxData; + *rxData = readData >> 8; + ++rxData; + *rxData = readData >> 16; + ++rxData; + } + else + { + *rxData = readData >> 16; + ++rxData; + *rxData = readData >> 8; + ++rxData; + *rxData = readData; + ++rxData; + } + break; + + case 4: + if (!isByteSwap) + { + *rxData = readData; + ++rxData; + *rxData = readData >> 8; + ++rxData; + *rxData = readData >> 16; + ++rxData; + *rxData = readData >> 24; + ++rxData; + } + else + { + *rxData = readData >> 24; + ++rxData; + *rxData = readData >> 16; + ++rxData; + *rxData = readData >> 8; + ++rxData; + *rxData = readData; + ++rxData; + } + break; + + default: + assert(false); + break; + } +} + +static void LPSPI_CommonIRQHandler(LPSPI_Type *base, void *param) +{ + if (LPSPI_IsMaster(base)) + { + s_lpspiMasterIsr(base, (lpspi_master_handle_t *)param); + } + else + { + s_lpspiSlaveIsr(base, (lpspi_slave_handle_t *)param); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#if defined(LPSPI0) +void LPSPI0_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[0]); + LPSPI_CommonIRQHandler(LPSPI0, s_lpspiHandle[0]); +} +#endif + +#if defined(LPSPI1) +void LPSPI1_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[1]); + LPSPI_CommonIRQHandler(LPSPI1, s_lpspiHandle[1]); +} +#endif + +#if defined(LPSPI2) +void LPSPI2_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[2]); + LPSPI_CommonIRQHandler(LPSPI2, s_lpspiHandle[2]); +} +#endif + +#if defined(LPSPI3) +void LPSPI3_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[3]); + LPSPI_CommonIRQHandler(LPSPI3, s_lpspiHandle[3]); +} +#endif + +#if defined(LPSPI4) +void LPSPI4_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[4]); + LPSPI_CommonIRQHandler(LPSPI4, s_lpspiHandle[4]); +} +#endif + +#if defined(LPSPI5) +void LPSPI5_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[5]); + LPSPI_CommonIRQHandler(LPSPI5, s_lpspiHandle[5]); +} +#endif + +#if defined(DMA__LPSPI0) +void DMA_SPI0_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI0)]); + LPSPI_CommonIRQHandler(DMA__LPSPI0, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI0)]); +} +#endif + +#if defined(DMA__LPSPI1) +void DMA_SPI1_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI1)]); + LPSPI_CommonIRQHandler(DMA__LPSPI1, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI1)]); +} +#endif +#if defined(DMA__LPSPI2) +void DMA_SPI2_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI2)]); + LPSPI_CommonIRQHandler(DMA__LPSPI2, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI2)]); +} +#endif + +#if defined(DMA__LPSPI3) +void DMA_SPI3_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI3)]); + LPSPI_CommonIRQHandler(DMA__LPSPI3, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI3)]); +} +#endif + +#if defined(ADMA__LPSPI0) +void ADMA_SPI0_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI0)]); + LPSPI_CommonIRQHandler(ADMA__LPSPI0, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI0)]); +} +#endif + +#if defined(ADMA__LPSPI1) +void ADMA_SPI1_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI1)]); + LPSPI_CommonIRQHandler(ADMA__LPSPI1, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI1)]); +} +#endif +#if defined(ADMA__LPSPI2) +void ADMA_SPI2_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI2)]); + LPSPI_CommonIRQHandler(ADMA__LPSPI2, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI2)]); +} +#endif + +#if defined(ADMA__LPSPI3) +void ADMA_SPI3_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI3)]); + LPSPI_CommonIRQHandler(ADMA__LPSPI3, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI3)]); +} +#endif diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpspi.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpspi.h new file mode 100644 index 0000000000..40236798d1 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpspi.h @@ -0,0 +1,1109 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_LPSPI_H_ +#define _FSL_LPSPI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpspi_driver + * @{ + */ + +/********************************************************************************************************************** + * Definitions + *********************************************************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPSPI driver version 2.0.3. */ +#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*@}*/ + +#ifndef LPSPI_DUMMY_DATA +/*! @brief LPSPI dummy data if no Tx data.*/ +#define LPSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for tx if there is not txData. */ +#endif + +/*! @brief Global variable for dummy data value setting. */ +extern volatile uint8_t g_lpspiDummyData[]; + +/*! @brief Status for the LPSPI driver.*/ +enum _lpspi_status +{ + kStatus_LPSPI_Busy = MAKE_STATUS(kStatusGroup_LPSPI, 0), /*!< LPSPI transfer is busy.*/ + kStatus_LPSPI_Error = MAKE_STATUS(kStatusGroup_LPSPI, 1), /*!< LPSPI driver error. */ + kStatus_LPSPI_Idle = MAKE_STATUS(kStatusGroup_LPSPI, 2), /*!< LPSPI is idle.*/ + kStatus_LPSPI_OutOfRange = MAKE_STATUS(kStatusGroup_LPSPI, 3) /*!< LPSPI transfer out Of range. */ +}; + +/*! @brief LPSPI status flags in SPIx_SR register.*/ +enum _lpspi_flags +{ + kLPSPI_TxDataRequestFlag = LPSPI_SR_TDF_MASK, /*!< Transmit data flag */ + kLPSPI_RxDataReadyFlag = LPSPI_SR_RDF_MASK, /*!< Receive data flag */ + kLPSPI_WordCompleteFlag = LPSPI_SR_WCF_MASK, /*!< Word Complete flag */ + kLPSPI_FrameCompleteFlag = LPSPI_SR_FCF_MASK, /*!< Frame Complete flag */ + kLPSPI_TransferCompleteFlag = LPSPI_SR_TCF_MASK, /*!< Transfer Complete flag */ + kLPSPI_TransmitErrorFlag = LPSPI_SR_TEF_MASK, /*!< Transmit Error flag (FIFO underrun) */ + kLPSPI_ReceiveErrorFlag = LPSPI_SR_REF_MASK, /*!< Receive Error flag (FIFO overrun) */ + kLPSPI_DataMatchFlag = LPSPI_SR_DMF_MASK, /*!< Data Match flag */ + kLPSPI_ModuleBusyFlag = LPSPI_SR_MBF_MASK, /*!< Module Busy flag */ + kLPSPI_AllStatusFlag = (LPSPI_SR_TDF_MASK | LPSPI_SR_RDF_MASK | LPSPI_SR_WCF_MASK | LPSPI_SR_FCF_MASK | + LPSPI_SR_TCF_MASK | LPSPI_SR_TEF_MASK | LPSPI_SR_REF_MASK | LPSPI_SR_DMF_MASK | + LPSPI_SR_MBF_MASK) /*!< Used for clearing all w1c status flags */ +}; + +/*! @brief LPSPI interrupt source.*/ +enum _lpspi_interrupt_enable +{ + kLPSPI_TxInterruptEnable = LPSPI_IER_TDIE_MASK, /*!< Transmit data interrupt enable */ + kLPSPI_RxInterruptEnable = LPSPI_IER_RDIE_MASK, /*!< Receive data interrupt enable */ + kLPSPI_WordCompleteInterruptEnable = LPSPI_IER_WCIE_MASK, /*!< Word complete interrupt enable */ + kLPSPI_FrameCompleteInterruptEnable = LPSPI_IER_FCIE_MASK, /*!< Frame complete interrupt enable */ + kLPSPI_TransferCompleteInterruptEnable = LPSPI_IER_TCIE_MASK, /*!< Transfer complete interrupt enable */ + kLPSPI_TransmitErrorInterruptEnable = LPSPI_IER_TEIE_MASK, /*!< Transmit error interrupt enable(FIFO underrun)*/ + kLPSPI_ReceiveErrorInterruptEnable = LPSPI_IER_REIE_MASK, /*!< Receive Error interrupt enable (FIFO overrun) */ + kLPSPI_DataMatchInterruptEnable = LPSPI_IER_DMIE_MASK, /*!< Data Match interrupt enable */ + kLPSPI_AllInterruptEnable = + (LPSPI_IER_TDIE_MASK | LPSPI_IER_RDIE_MASK | LPSPI_IER_WCIE_MASK | LPSPI_IER_FCIE_MASK | LPSPI_IER_TCIE_MASK | + LPSPI_IER_TEIE_MASK | LPSPI_IER_REIE_MASK | LPSPI_IER_DMIE_MASK) /*!< All above interrupts enable.*/ +}; + +/*! @brief LPSPI DMA source.*/ +enum _lpspi_dma_enable +{ + kLPSPI_TxDmaEnable = LPSPI_DER_TDDE_MASK, /*!< Transmit data DMA enable */ + kLPSPI_RxDmaEnable = LPSPI_DER_RDDE_MASK /*!< Receive data DMA enable */ +}; + +/*! @brief LPSPI master or slave mode configuration.*/ +typedef enum _lpspi_master_slave_mode +{ + kLPSPI_Master = 1U, /*!< LPSPI peripheral operates in master mode.*/ + kLPSPI_Slave = 0U /*!< LPSPI peripheral operates in slave mode.*/ +} lpspi_master_slave_mode_t; + +/*! @brief LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).*/ +typedef enum _lpspi_which_pcs_config +{ + kLPSPI_Pcs0 = 0U, /*!< PCS[0] */ + kLPSPI_Pcs1 = 1U, /*!< PCS[1] */ + kLPSPI_Pcs2 = 2U, /*!< PCS[2] */ + kLPSPI_Pcs3 = 3U /*!< PCS[3] */ +} lpspi_which_pcs_t; + +/*! @brief LPSPI Peripheral Chip Select (PCS) Polarity configuration.*/ +typedef enum _lpspi_pcs_polarity_config +{ + kLPSPI_PcsActiveHigh = 1U, /*!< PCS Active High (idles low) */ + kLPSPI_PcsActiveLow = 0U /*!< PCS Active Low (idles high) */ +} lpspi_pcs_polarity_config_t; + +/*! @brief LPSPI Peripheral Chip Select (PCS) Polarity.*/ +enum _lpspi_pcs_polarity +{ + kLPSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */ + kLPSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */ + kLPSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */ + kLPSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */ + kLPSPI_PcsAllActiveLow = 0xFU /*!< Pcs0 to Pcs5 Active Low (idles high). */ +}; + +/*! @brief LPSPI clock polarity configuration.*/ +typedef enum _lpspi_clock_polarity +{ + kLPSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high LPSPI clock (idles low)*/ + kLPSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low LPSPI clock (idles high)*/ +} lpspi_clock_polarity_t; + +/*! @brief LPSPI clock phase configuration.*/ +typedef enum _lpspi_clock_phase +{ + kLPSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the + following edge.*/ + kLPSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the + following edge.*/ +} lpspi_clock_phase_t; + +/*! @brief LPSPI data shifter direction options.*/ +typedef enum _lpspi_shift_direction +{ + kLPSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/ + kLPSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit.*/ +} lpspi_shift_direction_t; + +/*! @brief LPSPI Host Request select configuration. */ +typedef enum _lpspi_host_request_select +{ + kLPSPI_HostReqExtPin = 0U, /*!< Host Request is an ext pin. */ + kLPSPI_HostReqInternalTrigger = 1U /*!< Host Request is an internal trigger. */ +} lpspi_host_request_select_t; + +/*! @brief LPSPI Match configuration options. */ +typedef enum _lpspi_match_config +{ + kLPSI_MatchDisabled = 0x0U, /*!< LPSPI Match Disabled. */ + kLPSI_1stWordEqualsM0orM1 = 0x2U, /*!< LPSPI Match Enabled. */ + kLPSI_AnyWordEqualsM0orM1 = 0x3U, /*!< LPSPI Match Enabled. */ + kLPSI_1stWordEqualsM0and2ndWordEqualsM1 = 0x4U, /*!< LPSPI Match Enabled. */ + kLPSI_AnyWordEqualsM0andNxtWordEqualsM1 = 0x5U, /*!< LPSPI Match Enabled. */ + kLPSI_1stWordAndM1EqualsM0andM1 = 0x6U, /*!< LPSPI Match Enabled. */ + kLPSI_AnyWordAndM1EqualsM0andM1 = 0x7U, /*!< LPSPI Match Enabled. */ +} lpspi_match_config_t; + +/*! @brief LPSPI pin (SDO and SDI) configuration. */ +typedef enum _lpspi_pin_config +{ + kLPSPI_SdiInSdoOut = 0U, /*!< LPSPI SDI input, SDO output. */ + kLPSPI_SdiInSdiOut = 1U, /*!< LPSPI SDI input, SDI output. */ + kLPSPI_SdoInSdoOut = 2U, /*!< LPSPI SDO input, SDO output. */ + kLPSPI_SdoInSdiOut = 3U /*!< LPSPI SDO input, SDI output. */ +} lpspi_pin_config_t; + +/*! @brief LPSPI data output configuration. */ +typedef enum _lpspi_data_out_config +{ + kLpspiDataOutRetained = 0U, /*!< Data out retains last value when chip select is de-asserted */ + kLpspiDataOutTristate = 1U /*!< Data out is tristated when chip select is de-asserted */ +} lpspi_data_out_config_t; + +/*! @brief LPSPI transfer width configuration. */ +typedef enum _lpspi_transfer_width +{ + kLPSPI_SingleBitXfer = 0U, /*!< 1-bit shift at a time, data out on SDO, in on SDI (normal mode) */ + kLPSPI_TwoBitXfer = 1U, /*!< 2-bits shift out on SDO/SDI and in on SDO/SDI */ + kLPSPI_FourBitXfer = 2U /*!< 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */ +} lpspi_transfer_width_t; + +/*! @brief LPSPI delay type selection.*/ +typedef enum _lpspi_delay_type +{ + kLPSPI_PcsToSck = 1U, /*!< PCS-to-SCK delay. */ + kLPSPI_LastSckToPcs, /*!< Last SCK edge to PCS delay. */ + kLPSPI_BetweenTransfer /*!< Delay between transfers. */ +} lpspi_delay_type_t; + +#define LPSPI_MASTER_PCS_SHIFT (4U) /*!< LPSPI master PCS shift macro , internal used. */ +#define LPSPI_MASTER_PCS_MASK (0xF0U) /*!< LPSPI master PCS shift macro , internal used. */ + +/*! @brief Use this enumeration for LPSPI master transfer configFlags. */ +enum _lpspi_transfer_config_flag_for_master +{ + kLPSPI_MasterPcs0 = 0U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS0 signal */ + kLPSPI_MasterPcs1 = 1U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS1 signal */ + kLPSPI_MasterPcs2 = 2U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS2 signal */ + kLPSPI_MasterPcs3 = 3U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS3 signal */ + + kLPSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous */ + + kLPSPI_MasterByteSwap = + 1U << 22 /*!< Is master swap the byte. + * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set + * lpspi_shift_direction_t to MSB). + * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used + * or not, the waveform is 1 2 3 4 5 6 7 8. + * 2. If you set bitPerFrame = 16 : + * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. + * 3. If you set bitPerFrame = 32 : + * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. + */ +}; + +#define LPSPI_SLAVE_PCS_SHIFT (4U) /*!< LPSPI slave PCS shift macro , internal used. */ +#define LPSPI_SLAVE_PCS_MASK (0xF0U) /*!< LPSPI slave PCS shift macro , internal used. */ + +/*! @brief Use this enumeration for LPSPI slave transfer configFlags. */ +enum _lpspi_transfer_config_flag_for_slave +{ + kLPSPI_SlavePcs0 = 0U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS0 signal */ + kLPSPI_SlavePcs1 = 1U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS1 signal */ + kLPSPI_SlavePcs2 = 2U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS2 signal */ + kLPSPI_SlavePcs3 = 3U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS3 signal */ + + kLPSPI_SlaveByteSwap = + 1U << 22 /*!< Is slave swap the byte. + * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set + * lpspi_shift_direction_t to MSB). + * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used + * or not, the waveform is 1 2 3 4 5 6 7 8. + * 2. If you set bitPerFrame = 16 : + * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. + * 3. If you set bitPerFrame = 32 : + * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. + */ +}; + +/*! @brief LPSPI transfer state, which is used for LPSPI transactional API state machine. */ +enum _lpspi_transfer_state +{ + kLPSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */ + kLPSPI_Busy, /*!< Transfer queue is not finished. */ + kLPSPI_Error /*!< Transfer error. */ +}; + +/*! @brief LPSPI master configuration structure.*/ +typedef struct _lpspi_master_config +{ + uint32_t baudRate; /*!< Baud Rate for LPSPI. */ + uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/ + lpspi_clock_polarity_t cpol; /*!< Clock polarity. */ + lpspi_clock_phase_t cpha; /*!< Clock phase. */ + lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ + + uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay. + It sets the boundary value if out of range.*/ + uint32_t lastSckToPcsDelayInNanoSec; /*!< Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum + delay. It sets the boundary value if out of range.*/ + uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time with nanoseconds, setting to 0 sets the + minimum delay. It sets the boundary value if out of range.*/ + + lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (PCS). */ + lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */ + + lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data + *during single bit transfers.*/ + + lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated + * between accesses (LPSPI_PCS is negated). */ +} lpspi_master_config_t; + +/*! @brief LPSPI slave configuration structure.*/ +typedef struct _lpspi_slave_config +{ + uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/ + lpspi_clock_polarity_t cpol; /*!< Clock polarity. */ + lpspi_clock_phase_t cpha; /*!< Clock phase. */ + lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ + + lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (pcs) */ + lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */ + + lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data + *during single bit transfers.*/ + + lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated + * between accesses (LPSPI_PCS is negated). */ +} lpspi_slave_config_t; + +/*! + * @brief Forward declaration of the _lpspi_master_handle typedefs. + */ +typedef struct _lpspi_master_handle lpspi_master_handle_t; + +/*! + * @brief Forward declaration of the _lpspi_slave_handle typedefs. + */ +typedef struct _lpspi_slave_handle lpspi_slave_handle_t; + +/*! + * @brief Master completion callback function pointer type. + * + * @param base LPSPI peripheral address. + * @param handle Pointer to the handle for the LPSPI master. + * @param status Success or error code describing whether the transfer is completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base, + lpspi_master_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief Slave completion callback function pointer type. + * + * @param base LPSPI peripheral address. + * @param handle Pointer to the handle for the LPSPI slave. + * @param status Success or error code describing whether the transfer is completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base, + lpspi_slave_handle_t *handle, + status_t status, + void *userData); + +/*! @brief LPSPI master/slave transfer structure.*/ +typedef struct _lpspi_transfer +{ + uint8_t *txData; /*!< Send buffer. */ + uint8_t *rxData; /*!< Receive buffer. */ + volatile size_t dataSize; /*!< Transfer bytes. */ + + uint32_t configFlags; /*!< Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if + the transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the + transfer is used for slave.*/ +} lpspi_transfer_t; + +/*! @brief LPSPI master transfer handle structure used for transactional API. */ +struct _lpspi_master_handle +{ + volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */ + volatile bool writeTcrInIsr; /*!< A flag that whether should write TCR in ISR. */ + + volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ + + volatile uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile uint8_t rxWatermark; /*!< Rx watermark. */ + + volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ + volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ + + volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ + volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ + + uint32_t totalByteCount; /*!< Number of transfer bytes*/ + + uint32_t txBuffIfNull; /*!< Used if the txData is NULL. */ + + volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ + + lpspi_master_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ +}; + +/*! @brief LPSPI slave transfer handle structure used for transactional API. */ +struct _lpspi_slave_handle +{ + volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ + + volatile uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile uint8_t rxWatermark; /*!< Rx watermark. */ + + volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ + volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + + volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ + + volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ + volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ + + uint32_t totalByteCount; /*!< Number of transfer bytes*/ + + volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ + + volatile uint32_t errorCount; /*!< Error count for slave transfer.*/ + + lpspi_slave_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ +}; + +/********************************************************************************************************************** + * API + *********************************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the LPSPI master. + * + * @param base LPSPI peripheral address. + * @param masterConfig Pointer to structure lpspi_master_config_t. + * @param srcClock_Hz Module source input clock in Hertz + */ +void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Sets the lpspi_master_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_MasterInit(). + * The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified + * before calling the LPSPI_MasterInit(). + * Example: + * @code + * lpspi_master_config_t masterConfig; + * LPSPI_MasterGetDefaultConfig(&masterConfig); + * @endcode + * @param masterConfig pointer to lpspi_master_config_t structure + */ +void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig); + +/*! + * @brief LPSPI slave configuration. + * + * @param base LPSPI peripheral address. + * @param slaveConfig Pointer to a structure lpspi_slave_config_t. + */ +void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig); + +/*! + * @brief Sets the lpspi_slave_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_SlaveInit(). + * The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified + * before calling the LPSPI_SlaveInit(). + * Example: + * @code + * lpspi_slave_config_t slaveConfig; + * LPSPI_SlaveGetDefaultConfig(&slaveConfig); + * @endcode + * @param slaveConfig pointer to lpspi_slave_config_t structure. + */ +void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig); + +/*! + * @brief De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock. + * @param base LPSPI peripheral address. + */ +void LPSPI_Deinit(LPSPI_Type *base); + +/*! + * @brief Restores the LPSPI peripheral to reset state. Note that this function + * sets all registers to reset state. As a result, the LPSPI module can't work after calling + * this API. + * @param base LPSPI peripheral address. + */ +void LPSPI_Reset(LPSPI_Type *base); + +/*! + * @brief Enables the LPSPI peripheral and sets the MCR MDIS to 0. + * + * @param base LPSPI peripheral address. + * @param enable Pass true to enable module, false to disable module. + */ +static inline void LPSPI_Enable(LPSPI_Type *base, bool enable) +{ + if (enable) + { + base->CR |= LPSPI_CR_MEN_MASK; + } + else + { + base->CR &= ~LPSPI_CR_MEN_MASK; + } +} + +/*! + *@} + */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the LPSPI status flag state. + * @param base LPSPI peripheral address. + * @return The LPSPI status(in SR register). + */ +static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base) +{ + return (base->SR); +} + +/*! + * @brief Gets the LPSPI Tx FIFO size. + * @param base LPSPI peripheral address. + * @return The LPSPI Tx FIFO size. + */ +static inline uint32_t LPSPI_GetTxFifoSize(LPSPI_Type *base) +{ + return (1U << ((base->PARAM & LPSPI_PARAM_TXFIFO_MASK) >> LPSPI_PARAM_TXFIFO_SHIFT)); +} + +/*! + * @brief Gets the LPSPI Rx FIFO size. + * @param base LPSPI peripheral address. + * @return The LPSPI Rx FIFO size. + */ +static inline uint32_t LPSPI_GetRxFifoSize(LPSPI_Type *base) +{ + return (1U << ((base->PARAM & LPSPI_PARAM_RXFIFO_MASK) >> LPSPI_PARAM_RXFIFO_SHIFT)); +} + +/*! + * @brief Gets the LPSPI Tx FIFO count. + * @param base LPSPI peripheral address. + * @return The number of words in the transmit FIFO. + */ +static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base) +{ + return ((base->FSR & LPSPI_FSR_TXCOUNT_MASK) >> LPSPI_FSR_TXCOUNT_SHIFT); +} + +/*! + * @brief Gets the LPSPI Rx FIFO count. + * @param base LPSPI peripheral address. + * @return The number of words in the receive FIFO. + */ +static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base) +{ + return ((base->FSR & LPSPI_FSR_RXCOUNT_MASK) >> LPSPI_FSR_RXCOUNT_SHIFT); +} + +/*! + * @brief Clears the LPSPI status flag. + * + * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the + * desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags. + * Example usage: + * @code + * LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag); + * @endcode + * + * @param base LPSPI peripheral address. + * @param statusFlags The status flag used from type _lpspi_flags. + */ +static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags) +{ + base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/ +} + +/*! + *@} + */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the LPSPI interrupts. + * + * This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask. + * Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request. + * + * @code + * LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable ); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable. + */ +static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask) +{ + base->IER |= mask; +} + +/*! + * @brief Disables the LPSPI interrupts. + * + * @code + * LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable ); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable. + */ +static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask) +{ + base->IER &= ~mask; +} + +/*! + *@} + */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables the LPSPI DMA request. + * + * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. + * @code + * LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_dma_enable. + */ +static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask) +{ + base->DER |= mask; +} + +/*! + * @brief Disables the LPSPI DMA request. + * + * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. + * @code + * SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_dma_enable. + */ +static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask) +{ + base->DER &= ~mask; +} + +/*! + * @brief Gets the LPSPI Transmit Data Register address for a DMA operation. + * + * This function gets the LPSPI Transmit Data Register address because this value is needed + * for the DMA operation. + * This function can be used for either master or slave mode. + * + * @param base LPSPI peripheral address. + * @return The LPSPI Transmit Data Register address. + */ +static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base) +{ + return (uint32_t) & (base->TDR); +} + +/*! + * @brief Gets the LPSPI Receive Data Register address for a DMA operation. + * + * This function gets the LPSPI Receive Data Register address because this value is needed + * for the DMA operation. + * This function can be used for either master or slave mode. + * + * @param base LPSPI peripheral address. + * @return The LPSPI Receive Data Register address. + */ +static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base) +{ + return (uint32_t) & (base->RDR); +} + +/*! + *@} + */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Check the argument for transfer . + * + * @param transfer the transfer struct to be used. + * @param bitPerFrame The bit size of one frame. + * @param bytePerFrame The byte size of one frame. + * @return Return true for right and false for wrong. + */ +bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame); + +/*! + * @brief Configures the LPSPI for either master or slave. + * + * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0). + * + * @param base LPSPI peripheral address. + * @param mode Mode setting (master or slave) of type lpspi_master_slave_mode_t. + */ +static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode) +{ + base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode); +} + +/*! + * @brief Returns whether the LPSPI module is in master mode. + * + * @param base LPSPI peripheral address. + * @return Returns true if the module is in master mode or false if the module is in slave mode. + */ +static inline bool LPSPI_IsMaster(LPSPI_Type *base) +{ + return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK); +} + +/*! + * @brief Flushes the LPSPI FIFOs. + * + * @param base LPSPI peripheral address. + * @param flushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO. + * @param flushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO. + */ +static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo) +{ + base->CR |= ((uint32_t)flushTxFifo << LPSPI_CR_RTF_SHIFT) | ((uint32_t)flushRxFifo << LPSPI_CR_RRF_SHIFT); +} + +/*! + * @brief Sets the transmit and receive FIFO watermark values. + * + * This function allows the user to set the receive and transmit FIFO watermarks. The function + * does not compare the watermark settings to the FIFO size. The FIFO watermark should not be + * equal to or greater than the FIFO size. It is up to the higher level driver to make this check. + * + * @param base LPSPI peripheral address. + * @param txWater The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. + * @param rxWater The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. + */ +static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater) +{ + base->FCR = LPSPI_FCR_TXWATER(txWater) | LPSPI_FCR_RXWATER(rxWater); +} + +/*! + * @brief Configures all LPSPI peripheral chip select polarities simultaneously. + * + * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0). + * + * This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of + * PCS is device-specific. + * @code + * LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The PCS polarity mask; Use the enum _lpspi_pcs_polarity. + */ +static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask) +{ + base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask); +} + +/*! + * @brief Configures the frame size. + * + * The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal + * to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word + * size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not + * divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported. + * + * Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although + * the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command + * register + * should only be changed if the LPSPI is idle. + * + * Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That + * means the TCR register should be written to when the Tx FIFO is not full. + * + * @param base LPSPI peripheral address. + * @param frameSize The frame size in number of bits. + */ +static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize) +{ + base->TCR = (base->TCR & ~LPSPI_TCR_FRAMESZ_MASK) | LPSPI_TCR_FRAMESZ(frameSize - 1); +} + +/*! + * @brief Sets the LPSPI baud rate in bits per second. + * + * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest + * possible baud rate without exceeding the desired baud rate and returns the + * calculated baud rate in bits-per-second. It requires the caller to provide + * the frequency of the module source clock (in Hertz). Note that the baud rate + * does not go into effect until the Transmit Control Register (TCR) is programmed + * with the prescale value. Hence, this function returns the prescale tcrPrescaleValue + * parameter for later programming in the TCR. The higher level + * peripheral driver should alert the user of an out of range baud rate input. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * @param base LPSPI peripheral address. + * @param baudRate_Bps The desired baud rate in bits per second. + * @param srcClock_Hz Module source input clock in Hertz. + * @param tcrPrescaleValue The TCR prescale value needed to program the TCR. + * @return The actual calculated baud rate. This function may also return a "0" if the + * LPSPI is not configured for master mode or if the LPSPI module is not disabled. + */ + +uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, + uint32_t baudRate_Bps, + uint32_t srcClock_Hz, + uint32_t *tcrPrescaleValue); + +/*! + * @brief Manually configures a specific LPSPI delay parameter (module must be disabled to + * change the delay values). + * + * This function configures the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay along with the delay value. + * This allows the user to directly set the delay values if they have + * pre-calculated them or if they simply wish to manually increment the value. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * @param base LPSPI peripheral address. + * @param scaler The 8-bit delay value 0x00 to 0xFF (255). + * @param whichDelay The desired delay to configure, must be of type lpspi_delay_type_t. + */ +void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay); + +/*! + * @brief Calculates the delay based on the desired delay input in nanoseconds (module must be + * disabled to change the delay values). + * + * This function calculates the values for the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay and the desired delay value in + * nano-seconds. The function calculates the value needed for the desired delay parameter + * and returns the actual calculated delay because an exact delay match may not be possible. In this + * case, the closest match is calculated without going below the desired delay value input. + * It is possible to input a very large delay value that exceeds the capability of the part, in + * which case the maximum supported delay is returned. It is up to the higher level + * peripheral driver to alert the user of an out of range delay input. + * + * Note that the LPSPI module must be configured for master mode before configuring this. And note that + * the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler). + * + * @param base LPSPI peripheral address. + * @param delayTimeInNanoSec The desired delay value in nano-seconds. + * @param whichDelay The desired delay to configuration, which must be of type lpspi_delay_type_t. + * @param srcClock_Hz Module source input clock in Hertz. + * @return actual Calculated delay value in nano-seconds. + */ +uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, + uint32_t delayTimeInNanoSec, + lpspi_delay_type_t whichDelay, + uint32_t srcClock_Hz); + +/*! + * @brief Writes data into the transmit data buffer. + * + * This function writes data passed in by the user to the Transmit Data Register (TDR). + * The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits, + * the user has to manage sending the data one 32-bit word at a time. + * Any writes to the TDR result in an immediate push to the transmit FIFO. + * This function can be used for either master or slave modes. + * + * @param base LPSPI peripheral address. + * @param data The data word to be sent. + */ +static inline void LPSPI_WriteData(LPSPI_Type *base, uint32_t data) +{ + base->TDR = data; +} + +/*! + * @brief Reads data from the data buffer. + * + * This function reads the data from the Receive Data Register (RDR). + * This function can be used for either master or slave mode. + * + * @param base LPSPI peripheral address. + * @return The data read from the data buffer. + */ +static inline uint32_t LPSPI_ReadData(LPSPI_Type *base) +{ + return (base->RDR); +} + +/*! + * @brief Set up the dummy data. + * + * @param base LPSPI peripheral address. + * @param dummyData Data to be transferred when tx buffer is NULL. + * Note: + * This API has no effect when LPSPI in slave interrupt mode, because driver + * will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit + * FIFO and output pin is tristated. + */ +void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData); + +/*! + *@} + */ + +/*! + * @name Transactional + * @{ + */ +/*Transactional APIs*/ + +/*! + * @brief Initializes the LPSPI master handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + + * @param base LPSPI peripheral address. + * @param handle LPSPI handle pointer to lpspi_master_handle_t. + * @param callback DSPI callback. + * @param userData callback function parameter. + */ +void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, + lpspi_master_handle_t *handle, + lpspi_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief LPSPI master transfer data using a polling method. + * + * This function transfers data using a polling method. This is a blocking function, which does not return until all + * transfers have been + * completed. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * @param base LPSPI peripheral address. + * @param transfer pointer to lpspi_transfer_t structure. + * @return status of status_t. + */ +status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer); + +/*! + * @brief LPSPI master transfer data using an interrupt method. + * + * This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data + * is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * @param transfer pointer to lpspi_transfer_t structure. + * @return status of status_t. + */ +status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer); + +/*! + * @brief Gets the master transfer remaining bytes. + * + * This function gets the master transfer remaining bytes. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @return status of status_t. + */ +status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count); + +/*! + * @brief LPSPI master abort transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle); + +/*! + * @brief LPSPI Master IRQ handler function. + * + * This function processes the LPSPI transmit and receive IRQ. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle); + +/*! + * @brief Initializes the LPSPI slave handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * @param base LPSPI peripheral address. + * @param handle LPSPI handle pointer to lpspi_slave_handle_t. + * @param callback DSPI callback. + * @param userData callback function parameter. + */ +void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, + lpspi_slave_handle_t *handle, + lpspi_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief LPSPI slave transfer data using an interrupt method. + * + * This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data + * is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * @param transfer pointer to lpspi_transfer_t structure. + * @return status of status_t. + */ +status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer); + +/*! + * @brief Gets the slave transfer remaining bytes. + * + * This function gets the slave transfer remaining bytes. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @return status of status_t. + */ +status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count); + +/*! + * @brief LPSPI slave aborts a transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle); + +/*! + * @brief LPSPI Slave IRQ handler function. + * + * This function processes the LPSPI transmit and receives an IRQ. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle); + +/*! + *@} + */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + /*! + *@} + */ + +#endif /*_FSL_LPSPI_H_*/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpspi_edma.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpspi_edma.c new file mode 100644 index 0000000000..a26599bd21 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpspi_edma.c @@ -0,0 +1,1171 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpspi_edma.h" + +/*********************************************************************************************************************** + * Definitions + ***********************************************************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpspi_edma" +#endif + +/*! + * @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private. + */ +typedef struct _lpspi_master_edma_private_handle +{ + LPSPI_Type *base; /*!< LPSPI peripheral base address. */ + lpspi_master_edma_handle_t *handle; /*!< lpspi_master_edma_handle_t handle */ +} lpspi_master_edma_private_handle_t; + +/*! + * @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private. + */ +typedef struct _lpspi_slave_edma_private_handle +{ + LPSPI_Type *base; /*!< LPSPI peripheral base address. */ + lpspi_slave_edma_handle_t *handle; /*!< lpspi_slave_edma_handle_t handle */ +} lpspi_slave_edma_private_handle_t; + +/*********************************************************************************************************************** + * Prototypes + ***********************************************************************************************************************/ + +/*! + * @brief Get instance number for LPSPI module. + * + * @param base LPSPI peripheral base address. + * @return Return the value of LPSPI instance. + */ +static uint32_t LPSPI_GetInstance(LPSPI_Type *base); + +/*! + * @brief EDMA_LpspiMasterCallback after the LPSPI master transfer completed by using EDMA. + * This is not a public API. + */ +static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds); + +/*! + * @brief EDMA_LpspiSlaveCallback after the LPSPI slave transfer completed by using EDMA. + * This is not a public API. + */ +static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds); + +static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap); + +/*********************************************************************************************************************** + * Variables + ***********************************************************************************************************************/ +/*! @brief Pointers to lpspi bases for each instance. */ +static LPSPI_Type *const s_lpspiBases[] = LPSPI_BASE_PTRS; + +/*! @brief Pointers to lpspi edma handles for each instance. */ +static lpspi_master_edma_private_handle_t s_lpspiMasterEdmaPrivateHandle[ARRAY_SIZE(s_lpspiBases)]; +static lpspi_slave_edma_private_handle_t s_lpspiSlaveEdmaPrivateHandle[ARRAY_SIZE(s_lpspiBases)]; + +/*********************************************************************************************************************** + * Code + ***********************************************************************************************************************/ + +static uint32_t LPSPI_GetInstance(LPSPI_Type *base) +{ + uint8_t instance = 0; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_lpspiBases); instance++) + { + if (s_lpspiBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_lpspiBases)); + + return instance; +} + +static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap) +{ + assert(rxData); + + switch (bytesEachRead) + { + case 1: + if (!isByteSwap) + { + *rxData = readData; + ++rxData; + } + else + { + *rxData = readData >> 24; + ++rxData; + } + break; + + case 2: + if (!isByteSwap) + { + *rxData = readData; + ++rxData; + *rxData = readData >> 8; + ++rxData; + } + else + { + *rxData = readData >> 16; + ++rxData; + *rxData = readData >> 24; + ++rxData; + } + break; + + case 4: + + *rxData = readData; + ++rxData; + *rxData = readData >> 8; + ++rxData; + *rxData = readData >> 16; + ++rxData; + *rxData = readData >> 24; + ++rxData; + + break; + + default: + assert(false); + break; + } +} + +/*! + * brief Initializes the LPSPI master eDMA handle. + * + * This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * Note that the LPSPI eDMA has a separated (Rx and Rx as two sources) or shared (Rx and Tx are the same source) DMA + * request source. + * (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and + * Tx DMAMUX source for edmaIntermediaryToTxRegHandle. + * (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle. + * + * param base LPSPI peripheral base address. + * param handle LPSPI handle pointer to lpspi_master_edma_handle_t. + * param callback LPSPI callback. + * param userData callback function parameter. + * param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t. + * param edmaTxDataToTxRegHandle edmaTxDataToTxRegHandle pointer to edma_handle_t. + */ +void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base, + lpspi_master_edma_handle_t *handle, + lpspi_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaRxRegToRxDataHandle, + edma_handle_t *edmaTxDataToTxRegHandle) +{ + assert(handle); + assert(edmaRxRegToRxDataHandle); + assert(edmaTxDataToTxRegHandle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + uint32_t instance = LPSPI_GetInstance(base); + + s_lpspiMasterEdmaPrivateHandle[instance].base = base; + s_lpspiMasterEdmaPrivateHandle[instance].handle = handle; + + handle->callback = callback; + handle->userData = userData; + + handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; + handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; +} + +/*! + * brief LPSPI master transfer data using eDMA. + * + * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data + * is transferred, the callback function is called. + * + * Note: + * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle); + assert(transfer); + + uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; + uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; + uint32_t temp = 0U; + + if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) + { + return kStatus_InvalidArgument; + } + + /*And since the dma transfer can not support 3 bytes .*/ + if ((bytesPerFrame % 4U) == 3) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + + handle->state = kLPSPI_Busy; + + uint32_t instance = LPSPI_GetInstance(base); + uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base); + uint32_t txAddr = LPSPI_GetTxRegisterAddress(base); + + uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; + + /*Because DMA is fast enough , so set the RX and TX watermarks to 0 .*/ + uint8_t txWatermark = 0; + uint8_t rxWatermark = 0; + + /*Used for byte swap*/ + uint32_t dif = 0; + + uint8_t bytesLastWrite = 0; + + bool isThereExtraTxBytes = false; + + uint8_t dummyData = g_lpspiDummyData[instance]; + + edma_transfer_config_t transferConfigRx; + edma_transfer_config_t transferConfigTx; + + edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); + edma_tcd_t *softwareTCD_pcsContinuous = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[2]) & (~0x1FU)); + + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + + handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + + handle->txBuffIfNull = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + + handle->isPcsContinuous = (bool)(transfer->configFlags & kLPSPI_MasterPcsContinuous); + handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); + + LPSPI_SetFifoWatermarks(base, txWatermark, rxWatermark); + + /*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ + LPSPI_Enable(base, false); + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ + temp = base->CFGR1; + temp &= LPSPI_CFGR1_PINCFG_MASK; + if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) + { + if (!handle->txData) + { + base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; + } + /* The 3-wire mode can't send and receive data at the same time. */ + if ((handle->txData) && (handle->rxData)) + { + return kStatus_InvalidArgument; + } + } + + LPSPI_Enable(base, true); + + /*Flush FIFO , clear status , disable all the inerrupts.*/ + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); + + /* For DMA transfer , we'd better not masked the transmit data and receive data in TCR since the transfer flow is + * hard to controlled by software. + */ + base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_CONT(handle->isPcsContinuous) | LPSPI_TCR_CONTC(0U) | LPSPI_TCR_BYSW(handle->isByteSwap) | + LPSPI_TCR_PCS(whichPcs); + + isThereExtraTxBytes = false; + handle->isThereExtraRxBytes = false; + + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame <= 4) + { + handle->bytesEachWrite = bytesPerFrame; + handle->bytesEachRead = bytesPerFrame; + + handle->bytesLastRead = bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4; + handle->bytesEachRead = 4; + + handle->bytesLastRead = 4; + + if ((transfer->dataSize % 4) != 0) + { + bytesLastWrite = transfer->dataSize % 4; + handle->bytesLastRead = bytesLastWrite; + + isThereExtraTxBytes = true; + + --handle->writeRegRemainingTimes; + + --handle->readRegRemainingTimes; + handle->isThereExtraRxBytes = true; + } + } + + LPSPI_DisableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); + + EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_LpspiMasterCallback, + &s_lpspiMasterEdmaPrivateHandle[instance]); + + /*Rx*/ + EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + if (handle->rxData) + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]); + transferConfigRx.destOffset = 1; + } + else + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull); + transferConfigRx.destOffset = 0; + } + transferConfigRx.destTransferSize = kEDMA_TransferSize1Bytes; + + dif = 0; + switch (handle->bytesEachRead) + { + case (1U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + dif = 3; + } + break; + + case (2U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfigRx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + dif = 2; + } + break; + + case (4U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigRx.minorLoopBytes = 4; + break; + + default: + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigRx.srcAddr = (uint32_t)rxAddr + dif; + transferConfigRx.srcOffset = 0; + + transferConfigRx.majorLoopCounts = handle->readRegRemainingTimes; + + /* Store the initially configured eDMA minor byte transfer count into the LPSPI handle */ + handle->nbytes = transferConfigRx.minorLoopBytes; + + EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &transferConfigRx, NULL); + EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + kEDMA_MajorInterruptEnable); + + /*Tx*/ + EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); + + if (isThereExtraTxBytes) + { + if (handle->txData) + { + transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]); + transferConfigTx.srcOffset = 1; + } + else + { + transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigTx.srcOffset = 0; + } + + transferConfigTx.destOffset = 0; + + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + + dif = 0; + switch (bytesLastWrite) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + dif = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + dif = 2; + } + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + dif; + transferConfigTx.majorLoopCounts = 1; + + EDMA_TcdReset(softwareTCD_extraBytes); + + if (handle->isPcsContinuous) + { + EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, softwareTCD_pcsContinuous); + } + else + { + EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL); + } + } + + if (handle->isPcsContinuous) + { + handle->transmitCommand = base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK); + + transferConfigTx.srcAddr = (uint32_t) & (handle->transmitCommand); + transferConfigTx.srcOffset = 0; + + transferConfigTx.destAddr = (uint32_t) & (base->TCR); + transferConfigTx.destOffset = 0; + + transferConfigTx.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.minorLoopBytes = 4; + transferConfigTx.majorLoopCounts = 1; + + EDMA_TcdReset(softwareTCD_pcsContinuous); + EDMA_TcdSetTransferConfig(softwareTCD_pcsContinuous, &transferConfigTx, NULL); + } + + if (handle->txData) + { + transferConfigTx.srcAddr = (uint32_t)(handle->txData); + transferConfigTx.srcOffset = 1; + } + else + { + transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigTx.srcOffset = 0; + } + + transferConfigTx.destOffset = 0; + + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + + dif = 0; + switch (handle->bytesEachRead) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + dif = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + + if (handle->isByteSwap) + { + dif = 2; + } + break; + + case (4U): + transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.minorLoopBytes = 4; + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + dif; + + transferConfigTx.majorLoopCounts = handle->writeRegRemainingTimes; + + if (isThereExtraTxBytes) + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, softwareTCD_extraBytes); + } + else if (handle->isPcsContinuous) + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, softwareTCD_pcsContinuous); + } + else + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, NULL); + } + + EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle); + EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); + + LPSPI_EnableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); + + return kStatus_Success; +} + +static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds) +{ + assert(edmaHandle); + assert(g_lpspiEdmaPrivateHandle); + + uint32_t readData; + + lpspi_master_edma_private_handle_t *lpspiEdmaPrivateHandle; + + lpspiEdmaPrivateHandle = (lpspi_master_edma_private_handle_t *)g_lpspiEdmaPrivateHandle; + + LPSPI_DisableDMA(lpspiEdmaPrivateHandle->base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); + + if (lpspiEdmaPrivateHandle->handle->isThereExtraRxBytes) + { + while (LPSPI_GetRxFifoCount(lpspiEdmaPrivateHandle->base) == 0) + { + } + readData = LPSPI_ReadData(lpspiEdmaPrivateHandle->base); + + if (lpspiEdmaPrivateHandle->handle->rxData) + { + LPSPI_SeparateEdmaReadData( + &(lpspiEdmaPrivateHandle->handle->rxData[lpspiEdmaPrivateHandle->handle->rxRemainingByteCount - + lpspiEdmaPrivateHandle->handle->bytesLastRead]), + readData, lpspiEdmaPrivateHandle->handle->bytesLastRead, lpspiEdmaPrivateHandle->handle->isByteSwap); + } + } + + lpspiEdmaPrivateHandle->handle->state = kLPSPI_Idle; + + if (lpspiEdmaPrivateHandle->handle->callback) + { + lpspiEdmaPrivateHandle->handle->callback(lpspiEdmaPrivateHandle->base, lpspiEdmaPrivateHandle->handle, + kStatus_Success, lpspiEdmaPrivateHandle->handle->userData); + } +} + +/*! + * brief LPSPI master aborts a transfer which is using eDMA. + * + * This function aborts a transfer which is using eDMA. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferAbortEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle) +{ + assert(handle); + + LPSPI_DisableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); + + EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle); + + handle->state = kLPSPI_Idle; +} + +/*! + * brief Gets the master eDMA transfer remaining bytes. + * + * This function gets the master eDMA transfer remaining bytes. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the EDMA transaction. + * return status of status_t. + */ +status_t LPSPI_MasterTransferGetCountEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + remainingByte = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, + handle->edmaRxRegToRxDataHandle->channel); + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} + +/*! + * brief Initializes the LPSPI slave eDMA handle. + * + * This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * Note that LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx as the same source) DMA request + * source. + * + * (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and + * Tx DMAMUX source for edmaTxDataToTxRegHandle. + * (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle . + * + * param base LPSPI peripheral base address. + * param handle LPSPI handle pointer to lpspi_slave_edma_handle_t. + * param callback LPSPI callback. + * param userData callback function parameter. + * param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t. + * param edmaTxDataToTxRegHandle edmaTxDataToTxRegHandle pointer to edma_handle_t. + */ +void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base, + lpspi_slave_edma_handle_t *handle, + lpspi_slave_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaRxRegToRxDataHandle, + edma_handle_t *edmaTxDataToTxRegHandle) +{ + assert(handle); + assert(edmaRxRegToRxDataHandle); + assert(edmaTxDataToTxRegHandle); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + uint32_t instance = LPSPI_GetInstance(base); + + s_lpspiSlaveEdmaPrivateHandle[instance].base = base; + s_lpspiSlaveEdmaPrivateHandle[instance].handle = handle; + + handle->callback = callback; + handle->userData = userData; + + handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; + handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; +} + +/*! + * brief LPSPI slave transfers data using eDMA. + * + * This function transfers data using eDMA. This is a non-blocking function, which return right away. When all data + * is transferred, the callback function is called. + * + * Note: + * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle); + assert(transfer); + + uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1; + uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8; + uint32_t temp = 0U; + + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; + + if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame)) + { + return kStatus_InvalidArgument; + } + + /*And since the dma transfer can not support 3 bytes .*/ + if ((bytesPerFrame % 4U) == 3) + { + return kStatus_InvalidArgument; + } + + /* Check that we're not busy.*/ + if (handle->state == kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + + handle->state = kLPSPI_Busy; + + uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base); + uint32_t txAddr = LPSPI_GetTxRegisterAddress(base); + + edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); + + uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; + + /*Because DMA is fast enough , so set the RX and TX watermarks to 0 .*/ + uint8_t txWatermark = 0; + uint8_t rxWatermark = 0; + + /*Used for byte swap*/ + uint32_t dif = 0; + + uint8_t bytesLastWrite = 0; + + uint32_t instance = LPSPI_GetInstance(base); + + edma_transfer_config_t transferConfigRx; + edma_transfer_config_t transferConfigTx; + + bool isThereExtraTxBytes = false; + + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + + handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3) / 4); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + + handle->txBuffIfNull = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + + handle->isByteSwap = (bool)(transfer->configFlags & kLPSPI_MasterByteSwap); + + LPSPI_SetFifoWatermarks(base, txWatermark, rxWatermark); + + /*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ + LPSPI_Enable(base, false); + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ + temp = base->CFGR1; + temp &= LPSPI_CFGR1_PINCFG_MASK; + if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) + { + if (!handle->txData) + { + base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; + } + /* The 3-wire mode can't send and receive data at the same time. */ + if ((handle->txData) && (handle->rxData)) + { + return kStatus_InvalidArgument; + } + } + + LPSPI_Enable(base, true); + + /*Flush FIFO , clear status , disable all the inerrupts.*/ + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(base, kLPSPI_AllInterruptEnable); + + /* For DMA transfer , we'd better not masked the transmit data and receive data in TCR since the transfer flow is + * hard to controlled by software. + */ + base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK)) | + LPSPI_TCR_CONTC(0U) | LPSPI_TCR_BYSW(handle->isByteSwap) | LPSPI_TCR_PCS(whichPcs); + + isThereExtraTxBytes = false; + handle->isThereExtraRxBytes = false; + + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame <= 4) + { + handle->bytesEachWrite = bytesPerFrame; + handle->bytesEachRead = bytesPerFrame; + + handle->bytesLastRead = bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4; + handle->bytesEachRead = 4; + + handle->bytesLastRead = 4; + + if ((transfer->dataSize % 4) != 0) + { + bytesLastWrite = transfer->dataSize % 4; + handle->bytesLastRead = bytesLastWrite; + + isThereExtraTxBytes = true; + --handle->writeRegRemainingTimes; + + handle->isThereExtraRxBytes = true; + --handle->readRegRemainingTimes; + } + } + + LPSPI_DisableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); + + EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_LpspiSlaveCallback, + &s_lpspiSlaveEdmaPrivateHandle[instance]); + + /*Rx*/ + if (handle->readRegRemainingTimes > 0) + { + EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + if (handle->rxData) + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]); + transferConfigRx.destOffset = 1; + } + else + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull); + transferConfigRx.destOffset = 0; + } + transferConfigRx.destTransferSize = kEDMA_TransferSize1Bytes; + + dif = 0; + switch (handle->bytesEachRead) + { + case (1U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + dif = 3; + } + break; + + case (2U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfigRx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + dif = 2; + } + break; + + case (4U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigRx.minorLoopBytes = 4; + break; + + default: + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigRx.srcAddr = (uint32_t)rxAddr + dif; + transferConfigRx.srcOffset = 0; + + transferConfigRx.majorLoopCounts = handle->readRegRemainingTimes; + + /* Store the initially configured eDMA minor byte transfer count into the DSPI handle */ + handle->nbytes = transferConfigRx.minorLoopBytes; + + EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &transferConfigRx, NULL); + EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + kEDMA_MajorInterruptEnable); + } + + /*Tx*/ + EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); + + if (isThereExtraTxBytes) + { + if (handle->txData) + { + transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]); + transferConfigTx.srcOffset = 1; + } + else + { + transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigTx.srcOffset = 0; + } + + transferConfigTx.destOffset = 0; + + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + + dif = 0; + switch (bytesLastWrite) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + dif = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + dif = 2; + } + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + dif; + transferConfigTx.majorLoopCounts = 1; + + EDMA_TcdReset(softwareTCD_extraBytes); + + EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL); + } + + if (handle->txData) + { + transferConfigTx.srcAddr = (uint32_t)(handle->txData); + transferConfigTx.srcOffset = 1; + } + else + { + transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigTx.srcOffset = 0; + } + + transferConfigTx.destOffset = 0; + + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + + dif = 0; + switch (handle->bytesEachRead) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + dif = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + + if (handle->isByteSwap) + { + dif = 2; + } + break; + + case (4U): + transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.minorLoopBytes = 4; + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + dif; + + transferConfigTx.majorLoopCounts = handle->writeRegRemainingTimes; + + if (isThereExtraTxBytes) + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, softwareTCD_extraBytes); + } + else + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, NULL); + } + + EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle); + EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); + + LPSPI_EnableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); + + return kStatus_Success; +} + +static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds) +{ + assert(edmaHandle); + assert(g_lpspiEdmaPrivateHandle); + + uint32_t readData; + + lpspi_slave_edma_private_handle_t *lpspiEdmaPrivateHandle; + + lpspiEdmaPrivateHandle = (lpspi_slave_edma_private_handle_t *)g_lpspiEdmaPrivateHandle; + + LPSPI_DisableDMA(lpspiEdmaPrivateHandle->base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); + + if (lpspiEdmaPrivateHandle->handle->isThereExtraRxBytes) + { + while (LPSPI_GetRxFifoCount(lpspiEdmaPrivateHandle->base) == 0) + { + } + readData = LPSPI_ReadData(lpspiEdmaPrivateHandle->base); + + if (lpspiEdmaPrivateHandle->handle->rxData) + { + LPSPI_SeparateEdmaReadData( + &(lpspiEdmaPrivateHandle->handle->rxData[lpspiEdmaPrivateHandle->handle->rxRemainingByteCount - + lpspiEdmaPrivateHandle->handle->bytesLastRead]), + readData, lpspiEdmaPrivateHandle->handle->bytesLastRead, lpspiEdmaPrivateHandle->handle->isByteSwap); + } + } + + lpspiEdmaPrivateHandle->handle->state = kLPSPI_Idle; + + if (lpspiEdmaPrivateHandle->handle->callback) + { + lpspiEdmaPrivateHandle->handle->callback(lpspiEdmaPrivateHandle->base, lpspiEdmaPrivateHandle->handle, + kStatus_Success, lpspiEdmaPrivateHandle->handle->userData); + } +} + +/*! + * brief LPSPI slave aborts a transfer which is using eDMA. + * + * This function aborts a transfer which is using eDMA. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferAbortEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle) +{ + assert(handle); + + LPSPI_DisableDMA(base, kLPSPI_RxDmaEnable | kLPSPI_TxDmaEnable); + + EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle); + + handle->state = kLPSPI_Idle; +} + +/*! + * brief Gets the slave eDMA transfer remaining bytes. + * + * This function gets the slave eDMA transfer remaining bytes. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the eDMA transaction. + * return status of status_t. + */ +status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + if (!count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + remainingByte = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, + handle->edmaRxRegToRxDataHandle->channel); + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpspi_edma.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpspi_edma.h new file mode 100644 index 0000000000..a2f9ef55e0 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpspi_edma.h @@ -0,0 +1,302 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_LPSPI_EDMA_H_ +#define _FSL_LPSPI_EDMA_H_ + +#include "fsl_lpspi.h" +#include "fsl_edma.h" + +/*! + * @addtogroup lpspi_edma_driver + * @{ + */ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief LPSPI EDMA driver version 2.0.2. */ +#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! + * @brief Forward declaration of the _lpspi_master_edma_handle typedefs. + */ +typedef struct _lpspi_master_edma_handle lpspi_master_edma_handle_t; + +/*! + * @brief Forward declaration of the _lpspi_slave_edma_handle typedefs. + */ +typedef struct _lpspi_slave_edma_handle lpspi_slave_edma_handle_t; + +/*! + * @brief Completion callback function pointer type. + * + * @param base LPSPI peripheral base address. + * @param handle Pointer to the handle for the LPSPI master. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_master_edma_transfer_callback_t)(LPSPI_Type *base, + lpspi_master_edma_handle_t *handle, + status_t status, + void *userData); +/*! + * @brief Completion callback function pointer type. + * + * @param base LPSPI peripheral base address. + * @param handle Pointer to the handle for the LPSPI slave. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_slave_edma_transfer_callback_t)(LPSPI_Type *base, + lpspi_slave_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief LPSPI master eDMA transfer handle structure used for transactional API. */ +struct _lpspi_master_edma_handle +{ + volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */ + + volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ + + volatile uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile uint8_t rxWatermark; /*!< Rx watermark. */ + + volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ + volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ + + volatile uint8_t bytesLastRead; /*!< Bytes for last read RDR. */ + volatile uint8_t isThereExtraRxBytes; /*!< Is there extra RX byte. */ + + uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ + + volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ + volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ + + uint32_t totalByteCount; /*!< Number of transfer bytes*/ + + uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/ + uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/ + + uint32_t transmitCommand; /*!< Used to write TCR for DMA purpose.*/ + + volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ + + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + + lpspi_master_edma_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ + + edma_handle_t *edmaRxRegToRxDataHandle; /*!rxRingBufferSize; + uint16_t tmpRxRingBufferTail = handle->rxRingBufferTail; + uint16_t tmpRxRingBufferHead = handle->rxRingBufferHead; + + if (tmpRxRingBufferTail > tmpRxRingBufferHead) + { + size = ((size_t)tmpRxRingBufferHead + tmpRxRingBufferSize - (size_t)tmpRxRingBufferTail); + } + else + { + size = ((size_t)tmpRxRingBufferHead - (size_t)tmpRxRingBufferTail); + } + + return size; +} + +static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + bool full; + + if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + return full; +} + +static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->DATA = data[i]; + } +} + +static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = + ((ctrl & LPUART_CTRL_M7_MASK) || ((!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); +#endif + + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (isSevenDataBits) + { + data[i] = (base->DATA & 0x7F); + } + else + { + data[i] = base->DATA; + } +#else + data[i] = (uint8_t)(base->DATA); +#endif + } +} + +/*! + * brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. + * + * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the LPUART. + * code + * lpuart_config_t lpuartConfig; + * lpuartConfig.baudRate_Bps = 115200U; + * lpuartConfig.parityMode = kLPUART_ParityDisabled; + * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig.isMsb = false; + * lpuartConfig.stopBitCount = kLPUART_OneStopBit; + * lpuartConfig.txFifoWatermark = 0; + * lpuartConfig.rxFifoWatermark = 1; + * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); + * endcode + * + * param base LPUART peripheral base address. + * param config Pointer to a user-defined configuration structure. + * param srcClock_Hz LPUART clock source frequency in HZ. + * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success LPUART initialize succeed + */ +status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz) +{ + assert(NULL != config); + assert(0U < config->baudRate_Bps); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->txFifoWatermark); + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) >= config->rxFifoWatermark); +#endif + + uint32_t temp; + uint16_t sbr, sbrTemp; + uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff; + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = config->baudRate_Bps; + osr = 0; + sbr = 0; + for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (uint16_t)((srcClock_Hz / (config->baudRate_Bps * osrTemp))); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0U) + { + sbrTemp = 1U; + } + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = (srcClock_Hz / (osrTemp * sbrTemp)); + + tempDiff = calculatedBaud - config->baudRate_Bps; + + /* Select the better value between srb and (sbr + 1) */ + if (tempDiff > (config->baudRate_Bps - (srcClock_Hz / (osrTemp * ((uint32_t)sbrTemp + 1U))))) + { + tempDiff = config->baudRate_Bps - (srcClock_Hz / (osrTemp * ((uint32_t)sbrTemp + 1U))); + sbrTemp++; + } + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff > ((config->baudRate_Bps / 100U) * 3U)) + { + /* Unacceptable baud rate difference of more than 3%*/ + return kStatus_LPUART_BaudrateNotSupport; + } + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPUART_GetInstance(base); + + /* Enable lpuart clock */ + CLOCK_EnableClock(s_lpuartClock[instance]); +#if defined(LPUART_PERIPH_CLOCKS) + CLOCK_EnableClock(s_lpuartPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL + /*Reset all internal logic and registers, except the Global Register */ + LPUART_SoftwareReset(base); +#else + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); +#endif + + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + if ((osr > 3U) && (osr < 8U)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR(osr - 1U); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + + /* Set bit count and parity mode. */ + base->BAUD &= ~LPUART_BAUD_M10_MASK; + + temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK | + LPUART_CTRL_IDLECFG_MASK); + + temp |= + (uint8_t)config->parityMode | LPUART_CTRL_IDLECFG(config->rxIdleConfig) | LPUART_CTRL_ILT(config->rxIdleType); + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (kLPUART_SevenDataBits == config->dataBitsCount) + { + if (kLPUART_ParityDisabled != config->parityMode) + { + temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */ + } + else + { + temp |= LPUART_CTRL_M7_MASK; + } + } + else +#endif + { + if (kLPUART_ParityDisabled != config->parityMode) + { + temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */ + } + } + + base->CTRL = temp; + +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + /* set stop bit per char */ + temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK; + base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Set tx/rx WATER watermark + Note: + Take care of the RX FIFO, RX interrupt request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + RX interrupt because the water mark is 2. + */ + base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16U) | config->txFifoWatermark); + + /* Enable tx/rx FIFO */ + base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK); + + /* Flush FIFO */ + base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK); +#endif + + /* Clear all status flags */ + temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_LBKDIF_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + /* Set the CTS configuration/TX CTS source. */ + base->MODIR |= LPUART_MODIR_TXCTSC(config->txCtsConfig) | LPUART_MODIR_TXCTSSRC(config->txCtsSource); + if (true == config->enableRxRTS) + { + /* Enable the receiver RTS(request-to-send) function. */ + base->MODIR |= LPUART_MODIR_RXRTSE_MASK; + } + if (true == config->enableTxCTS) + { + /* Enable the CTS(clear-to-send) function. */ + base->MODIR |= LPUART_MODIR_TXCTSE_MASK; + } +#endif + + /* Set data bits order. */ + if (true == config->isMsb) + { + temp |= LPUART_STAT_MSBF_MASK; + } + else + { + temp &= ~LPUART_STAT_MSBF_MASK; + } + + base->STAT |= temp; + + /* Enable TX/RX base on configure structure. */ + temp = base->CTRL; + if (true == config->enableTx) + { + temp |= LPUART_CTRL_TE_MASK; + } + + if (true == config->enableRx) + { + temp |= LPUART_CTRL_RE_MASK; + } + + base->CTRL = temp; + + return kStatus_Success; +} +/*! + * brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * param base LPUART peripheral base address. + */ +void LPUART_Deinit(LPUART_Type *base) +{ + uint32_t temp; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Wait tx FIFO send out*/ + while (0U != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT)) + { + } +#endif + /* Wait last char shift out */ + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) + { + } + + /* Clear all status flags */ + temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_LBKDIF_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + + base->STAT |= temp; + + /* Disable the module. */ + base->CTRL = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = LPUART_GetInstance(base); + + /* Disable lpuart clock */ + CLOCK_DisableClock(s_lpuartClock[instance]); + +#if defined(LPUART_PERIPH_CLOCKS) + CLOCK_DisableClock(s_lpuartPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig->isMsb = false; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; + * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * param config Pointer to a configuration structure. + */ +void LPUART_GetDefaultConfig(lpuart_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->baudRate_Bps = 115200U; + config->parityMode = kLPUART_ParityDisabled; + config->dataBitsCount = kLPUART_EightDataBits; + config->isMsb = false; +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + config->stopBitCount = kLPUART_OneStopBit; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + config->txFifoWatermark = 0; + config->rxFifoWatermark = 0; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + config->enableRxRTS = false; + config->enableTxCTS = false; + config->txCtsConfig = kLPUART_CtsSampleAtStart; + config->txCtsSource = kLPUART_CtsSourcePin; +#endif + config->rxIdleType = kLPUART_IdleTypeStartBit; + config->rxIdleConfig = kLPUART_IdleCharacter1; + config->enableTx = false; + config->enableRx = false; +} + +/*! + * brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * endcode + * + * param base LPUART peripheral base address. + * param baudRate_Bps LPUART baudrate to be set. + * param srcClock_Hz LPUART clock source frequency in HZ. + * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. + * retval kStatus_Success Set baudrate succeeded. + */ +status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + assert(0U < baudRate_Bps); + + uint32_t temp, oldCtrl; + uint16_t sbr, sbrTemp; + uint32_t osr, osrTemp, tempDiff, calculatedBaud, baudDiff; + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = baudRate_Bps; + osr = 0; + sbr = 0; + for (osrTemp = 4u; osrTemp <= 32u; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (uint16_t)(srcClock_Hz / (baudRate_Bps * osrTemp)); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0u) + { + sbrTemp = 1u; + } + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = (uint16_t)((srcClock_Hz / (osrTemp * sbrTemp))); + + tempDiff = calculatedBaud - baudRate_Bps; + + /* Select the better value between srb and (sbr + 1) */ + if (tempDiff > (baudRate_Bps - (srcClock_Hz / (osrTemp * ((uint32_t)sbrTemp + 1u))))) + { + tempDiff = baudRate_Bps - (srcClock_Hz / (osrTemp * ((uint32_t)sbrTemp + 1u))); + sbrTemp++; + } + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff < (uint32_t)((baudRate_Bps / 100u) * 3u)) + { + /* Store CTRL before disable Tx and Rx */ + oldCtrl = base->CTRL; + + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); + + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + if ((osr > 3u) && (osr < 8u)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR(osr - 1u); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + + /* Restore CTRL. */ + base->CTRL = oldCtrl; + + return kStatus_Success; + } + else + { + /* Unacceptable baud rate difference of more than 3%*/ + return kStatus_LPUART_BaudrateNotSupport; + } +} + +/*! + * brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * endcode + * + * param base LPUART peripheral base address. + * param mask The interrupts to enable. Logical OR of ref _uart_interrupt_enable. + */ +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) +{ + base->BAUD |= ((mask << 8U) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) | + ((mask << 8U) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); +#endif + mask &= 0xFFFFFF00U; + base->CTRL |= mask; +} + +/*! + * brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * endcode + * + * param base LPUART peripheral base address. + * param mask The interrupts to disable. Logical OR of ref _lpuart_interrupt_enable. + */ +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) +{ + base->BAUD &= ~((mask << 8U) & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) & + ~((mask << 8U) & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); +#endif + mask &= 0xFFFFFF00U; + base->CTRL &= ~mask; +} + +/*! + * brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * endcode + * + * param base LPUART peripheral base address. + * return LPUART interrupt flags which are logical OR of the enumerators in ref _lpuart_interrupt_enable. + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base) +{ + uint32_t temp; + temp = (base->BAUD & (LPUART_BAUD_LBKDIE_MASK | LPUART_BAUD_RXEDGIE_MASK)) >> 8U; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp |= (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)) >> 8U; +#endif + temp |= (uint32_t)(base->CTRL & 0xFF0C000u); + + return temp; +} + +/*! + * brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the ref _lpuart_flags. + * For example, to check whether the TX is empty: + * code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * endcode + * + * param base LPUART peripheral base address. + * return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ +uint32_t LPUART_GetStatusFlags(LPUART_Type *base) +{ + uint32_t temp; + temp = base->STAT; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp |= (base->FIFO & + (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >> + 16U; +#endif + return temp; +} + +/*! + * brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * param base LPUART peripheral base address. + * param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * return 0 succeed, others failed. + * retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * retval kStatus_Success Status in the mask are cleared. + */ +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask) +{ + uint32_t temp; + status_t status; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp = (uint32_t)base->FIFO; + temp &= (uint32_t)(~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)); + temp |= (mask << 16U) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK); + base->FIFO = temp; +#endif + temp = (uint32_t)base->STAT; +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp &= (uint32_t)(~(LPUART_STAT_LBKDIF_MASK)); + temp |= mask & LPUART_STAT_LBKDIF_MASK; +#endif + temp &= (uint32_t)(~(LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK)); + temp |= mask & (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp &= (uint32_t)(~(LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK)); + temp |= mask & (LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK); +#endif + base->STAT = temp; + /* If some flags still pending. */ + if (0U != (mask & LPUART_GetStatusFlags(base))) + { + /* Some flags can only clear or set by the hardware itself, these flags are: kLPUART_TxDataRegEmptyFlag, + kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, kLPUART_RxActiveFlag, + kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + kLPUART_TxFifoEmptyFlag, kLPUART_RxFifoEmptyFlag. */ + status = kStatus_LPUART_FlagCannotClearManually; /* flags can not clear manually */ + } + else + { + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Writes to the transmitter register using a blocking method. + * + * This function polls the transmitter register, waits for the register to be empty or for TX FIFO to have + * room, and writes data to the transmitter buffer. + * + * note This function does not check whether all data has been sent out to the bus. + * Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is + * finished. + * + * param base LPUART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + */ +void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + assert(NULL != data); + + const uint8_t *dataAddress = data; + size_t transferSize = length; + + /* This API can only ensure that the data is written into the data buffer but can't + ensure all data in the data buffer are sent into the transmit shift buffer. */ + while (0U != transferSize) + { + while (0U == (base->STAT & LPUART_STAT_TDRE_MASK)) + { + } + base->DATA = *(dataAddress); + dataAddress++; + transferSize--; + } +} + +/*! + * brief Reads the receiver data register using a blocking method. + * + * This function polls the receiver register, waits for the receiver register full or receiver FIFO + * has data, and reads data from the TX register. + * + * param base LPUART peripheral base address. + * param data Start address of the buffer to store the received data. + * param length Size of the buffer. + * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + assert(NULL != data); + + uint32_t statusFlag; + uint8_t *dataAddress = data; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = + ((ctrl & LPUART_CTRL_M7_MASK) || ((!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); +#endif + + while (0U != (length--)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) +#else + while (0U == (base->STAT & LPUART_STAT_RDRF_MASK)) +#endif + { + statusFlag = LPUART_GetStatusFlags(base); + + if ((uint32_t)kLPUART_RxOverrunFlag == (statusFlag & (uint32_t)kLPUART_RxOverrunFlag)) + { + return ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ? + (kStatus_LPUART_RxHardwareOverrun) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if ((uint32_t)kLPUART_NoiseErrorFlag == (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag)) + { + return ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ? + (kStatus_LPUART_NoiseError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if ((uint32_t)kLPUART_FramingErrorFlag == (statusFlag & (uint32_t)kLPUART_FramingErrorFlag)) + { + return ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ? + (kStatus_LPUART_FramingError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if ((uint32_t)kLPUART_ParityErrorFlag == (statusFlag & (uint32_t)kLPUART_ParityErrorFlag)) + { + return ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ? + (kStatus_LPUART_ParityError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + } +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (isSevenDataBits) + { + *(dataAddress) = (uint8_t)(base->DATA & 0x7F); + dataAddress++; + } + else + { + *(dataAddress) = (uint8_t)base->DATA; + dataAddress++; + } +#else + *(dataAddress) = (uint8_t)base->DATA; + dataAddress++; +#endif + } + + return kStatus_Success; +} + +/*! + * brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as p ringBuffer. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param callback Callback function. + * param userData User data. + */ +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData) +{ + assert(NULL != handle); + + uint32_t instance; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = + ((ctrl & LPUART_CTRL_M7_MASK) || ((!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); +#endif + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(lpuart_handle_t)); + + /* Set the TX/RX state. */ + handle->rxState = (uint8_t)kLPUART_RxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + /* Initial seven data bits flag */ + handle->isSevenDataBits = isSevenDataBits; +#endif + + /* Get instance from peripheral base address. */ + instance = LPUART_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_lpuartHandle[instance] = handle; + + s_lpuartIsr = LPUART_TransferHandleIRQ; + +/* Enable interrupt in NVIC. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + (void)EnableIRQ(s_lpuartRxIRQ[instance]); + (void)EnableIRQ(s_lpuartTxIRQ[instance]); +#else + (void)EnableIRQ(s_lpuartIRQ[instance]); +#endif +} + +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize size of the ring buffer. + */ +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize) +{ + assert(NULL != handle); + assert(NULL != ringBuffer); + + /* Setup the ring buffer address */ + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Enable the interrupt to accept the data when user need the ring buffer. */ + LPUART_EnableInterrupts( + base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable); +} + +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + if (handle->rxState == (uint8_t)kLPUART_RxIdle) + { + LPUART_DisableInterrupts( + base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the ref kStatus_LPUART_TxIdle as status parameter. + * + * note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART transfer structure, see #lpuart_transfer_t. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); + + status_t status; + + /* Return error if current TX busy. */ + if ((uint8_t)kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = (uint8_t)kLPUART_TxBusy; + + /* Enable transmitter interrupt. */ + LPUART_EnableInterrupts(base, (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are not sent out. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + LPUART_DisableInterrupts( + base, (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable | (uint32_t)kLPUART_TransmissionCompleteInterruptEnable); + + handle->txDataSize = 0; + handle->txState = (uint8_t)kLPUART_TxIdle; +} + +/*! + * brief Gets the number of bytes that have been written to the LPUART transmitter register. + * + * This function gets the number of bytes that have been written to LPUART TX + * register by an interrupt method. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if ((uint8_t)kLPUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - handle->txDataSize; + + return kStatus_Success; +} + +/*! + * brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART transfer structure, see #uart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into the transmit queue. + * retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes) +{ + assert(NULL != handle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); + + uint32_t i; + status_t status; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to lpuart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to lpuart handle, receive data + to this empty space and trigger callback when finished. */ + + if ((uint8_t)kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0; + + /* If RX ring buffer is used. */ + if (NULL != handle->rxRingBuffer) + { + /* Disable LPUART RX IRQ, protect ring buffer. */ + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle); + + if (0U != bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->data[bytesCurrentReceived] = handle->rxRingBuffer[handle->rxRingBufferTail]; + bytesCurrentReceived++; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (0U != bytesToReceive) + { + /* No data in ring buffer, save the request to LPUART handle. */ + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = (uint8_t)kLPUART_RxBusy; + } + /* Enable LPUART RX IRQ if previously enabled. */ + LPUART_EnableInterrupts(base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable); + + /* Call user callback since all data are received. */ + if (0U == bytesToReceive) + { + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = (uint8_t)kLPUART_RxBusy; + + /* Enable RX interrupt. */ + LPUART_EnableInterrupts(base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | + (uint32_t)kLPUART_RxOverrunInterruptEnable | + (uint32_t)kLPUART_IdleLineInterruptEnable); + } + + /* Return the how many bytes have read. */ + if (NULL != receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (NULL == handle->rxRingBuffer) + { + /* Disable RX interrupt. */ + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | + (uint32_t)kLPUART_RxOverrunInterruptEnable | + (uint32_t)kLPUART_IdleLineInterruptEnable); + } + + handle->rxDataSize = 0U; + handle->rxState = (uint8_t)kLPUART_RxIdle; +} + +/*! + * brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if ((uint8_t)kLPUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +/*! + * brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + uint8_t count; + uint8_t tempCount; + uint32_t status = LPUART_GetStatusFlags(base); + uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(base); + + /* If RX overrun. */ + if ((uint32_t)kLPUART_RxOverrunFlag == ((uint32_t)kLPUART_RxOverrunFlag & status)) + { + /* Clear overrun flag, otherwise the RX does not work. */ + base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); + + /* Trigger callback. */ + if (NULL != (handle->callback)) + { + handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData); + } + } + + /* If IDLE flag is set and the IDLE interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) && + (0U != ((uint32_t)kLPUART_IdleLineInterruptEnable & enabledInterrupts))) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); + + while ((0U != handle->rxDataSize) && (0U != count)) + { + tempCount = (uint8_t)MIN(handle->rxDataSize, count); + + /* Using non block API to read the data from the registers. */ + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData += tempCount; + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If rxDataSize is 0, disable idle line interrupt.*/ + if (0U == (handle->rxDataSize)) + { + handle->rxState = (uint8_t)kLPUART_RxIdle; + + LPUART_DisableInterrupts( + base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable); + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } +#endif + /* Clear IDLE flag.*/ + base->STAT |= LPUART_STAT_IDLE_MASK; + + /* If rxDataSize is 0, disable idle line interrupt.*/ + if (0U != (handle->rxDataSize)) + { + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_IdleLineInterruptEnable); + } + /* If callback is not NULL and rxDataSize is not 0. */ + if ((0U != handle->rxDataSize) && (NULL != handle->callback)) + { + handle->callback(base, handle, kStatus_LPUART_IdleLineDetected, handle->userData); + } + } + /* Receive data register full */ + if ((0U != ((uint32_t)kLPUART_RxDataRegFullFlag & status)) && + (0U != ((uint32_t)kLPUART_RxDataRegFullInterruptEnable & enabledInterrupts))) + { +/* Get the size that can be stored into buffer for this interrupt. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); +#else + count = 1; +#endif + + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + while ((0U != handle->rxDataSize) && (0U != count)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = (uint8_t)MIN(handle->rxDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to read the data from the registers. */ + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData += tempCount; + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (0U == handle->rxDataSize) + { + handle->rxState = (uint8_t)kLPUART_RxIdle; + + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (NULL != handle->rxRingBuffer) + { + while (0U != count--) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overridden. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + +/* Read data. */ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (handle->isSevenDataBits) + { + handle->rxRingBuffer[handle->rxRingBufferHead] = (base->DATA & 0x7F); + } + else + { + handle->rxRingBuffer[handle->rxRingBufferHead] = base->DATA; + } +#else + uint16_t tpmRxRingBufferHead = handle->rxRingBufferHead; + uint32_t tpmData = base->DATA; + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData; +#endif + + /* Increase handle->rxRingBufferHead. */ + if (((uint32_t)handle->rxRingBufferHead + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If no receive requst pending, stop RX interrupt. */ + else if (0U == handle->rxDataSize) + { + LPUART_DisableInterrupts( + base, (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable); + } + else + { + } + } + + /* Send data register empty and the interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_TxDataRegEmptyFlag & status)) && + (0U != ((uint32_t)kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts))) + { +/* Get the bytes that available at this moment. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) - + (uint8_t)((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +#else + count = 1; +#endif + + while ((0U != handle->txDataSize) && (0U != count)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = (uint8_t)MIN(handle->txDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to write the data to the registers. */ + LPUART_WriteNonBlocking(base, handle->txData, tempCount); + handle->txData += tempCount; + handle->txDataSize -= tempCount; + count -= tempCount; + + /* If all the data are written to data register, notify user with the callback, then TX finished. */ + if (0U == handle->txDataSize) + { + handle->txState = (uint8_t)kLPUART_TxIdle; + + /* Disable TX register empty interrupt. */ + base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK); + + /* Trigger callback. */ + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); + } + } + } + } +} + +/*! + * brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle) +{ + /* To be implemented by User. */ +} +#if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART0_LPUART1_RX_DriverIRQHandler(void) +{ + uint32_t stat = 0U; + uint32_t ctrl = 0U; + + if (CLOCK_isEnabledClock(s_lpuartClock[0])) + { + stat = LPUART0->STAT; + ctrl = LPUART0->CTRL; + if ((LPUART_STAT_OR_MASK & stat) || ((LPUART_STAT_RDRF_MASK & stat) && (LPUART_CTRL_RIE_MASK & ctrl))) + { + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); + } + } + if (CLOCK_isEnabledClock(s_lpuartClock[1])) + { + stat = LPUART1->STAT; + ctrl = LPUART1->CTRL; + if ((LPUART_STAT_OR_MASK & stat) || ((LPUART_STAT_RDRF_MASK & stat) && (LPUART_CTRL_RIE_MASK & ctrl))) + { + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); + } + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART0_LPUART1_TX_DriverIRQHandler(void) +{ + uint32_t stat = 0U; + uint32_t ctrl = 0U; + + if (CLOCK_isEnabledClock(s_lpuartClock[0])) + { + stat = LPUART0->STAT; + ctrl = LPUART0->CTRL; + if ((LPUART_STAT_OR_MASK & stat) || ((stat & LPUART_STAT_TDRE_MASK) && (ctrl & LPUART_CTRL_TIE_MASK))) + { + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); + } + } + if (CLOCK_isEnabledClock(s_lpuartClock[1])) + { + stat = LPUART1->STAT; + ctrl = LPUART1->CTRL; + if ((LPUART_STAT_OR_MASK & stat) || ((stat & LPUART_STAT_TDRE_MASK) && (ctrl & LPUART_CTRL_TIE_MASK))) + { + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); + } + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART0_LPUART1_DriverIRQHandler(void) +{ + uint32_t stat = 0U; + uint32_t ctrl = 0U; + + if (CLOCK_isEnabledClock(s_lpuartClock[0])) + { + stat = LPUART0->STAT; + ctrl = LPUART0->CTRL; + if ((0U != (LPUART_STAT_OR_MASK & stat)) || + ((0U != (LPUART_STAT_RDRF_MASK & stat)) && (0U != (LPUART_CTRL_RIE_MASK & ctrl))) || + ((0U != (stat & LPUART_STAT_TDRE_MASK)) && (0U != (ctrl & LPUART_CTRL_TIE_MASK)))) + { + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); + } + } + if (CLOCK_isEnabledClock(s_lpuartClock[1])) + { + stat = LPUART1->STAT; + ctrl = LPUART1->CTRL; + if ((0U != (LPUART_STAT_OR_MASK & stat)) || + ((0U != (LPUART_STAT_RDRF_MASK & stat)) && (0U != (LPUART_CTRL_RIE_MASK & ctrl))) || + ((0U != (stat & LPUART_STAT_TDRE_MASK)) && (0U != (ctrl & LPUART_CTRL_TIE_MASK)))) + { + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); + } + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif + +#if defined(LPUART0) +#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART0_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART0_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART0_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif +#endif + +#if defined(LPUART1) +#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART1_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART1_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART1_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif +#endif + +#if defined(LPUART2) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART2_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART2, s_lpuartHandle[2]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART2_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART2, s_lpuartHandle[2]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART2_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART2, s_lpuartHandle[2]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif + +#if defined(LPUART3) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART3_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART3, s_lpuartHandle[3]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART3_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART3, s_lpuartHandle[3]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART3_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART3, s_lpuartHandle[3]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif + +#if defined(LPUART4) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART4_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART4, s_lpuartHandle[4]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART4_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART4, s_lpuartHandle[4]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART4_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART4, s_lpuartHandle[4]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif + +#if defined(LPUART5) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART5_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART5, s_lpuartHandle[5]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART5_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART5, s_lpuartHandle[5]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART5_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART5, s_lpuartHandle[5]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif + +#if defined(LPUART6) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART6_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART6, s_lpuartHandle[6]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART6_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART6, s_lpuartHandle[6]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART6_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART6, s_lpuartHandle[6]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif + +#if defined(LPUART7) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART7_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART7, s_lpuartHandle[7]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART7_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART7, s_lpuartHandle[7]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART7_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART7, s_lpuartHandle[7]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif + +#if defined(LPUART8) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART8_TX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART8, s_lpuartHandle[8]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +void LPUART8_RX_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART8, s_lpuartHandle[8]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#else +void LPUART8_DriverIRQHandler(void) +{ + s_lpuartIsr(LPUART8, s_lpuartHandle[8]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif + +#if defined(CM4_0__LPUART) +void M4_0_LPUART_DriverIRQHandler(void) +{ + s_lpuartIsr(CM4_0__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_0__LPUART)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CM4_1__LPUART) +void M4_1_LPUART_DriverIRQHandler(void) +{ + s_lpuartIsr(CM4_1__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_1__LPUART)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CM4__LPUART) +void M4_LPUART_DriverIRQHandler(void) +{ + s_lpuartIsr(CM4__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4__LPUART)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(DMA__LPUART0) +void DMA_UART0_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(DMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART0)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(DMA__LPUART1) +void DMA_UART1_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(DMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART1)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(DMA__LPUART2) +void DMA_UART2_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(DMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART2)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(DMA__LPUART3) +void DMA_UART3_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(DMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART3)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(DMA__LPUART4) +void DMA_UART4_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(DMA__LPUART4, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART4)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__LPUART0) +void ADMA_UART0_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(ADMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART0)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__LPUART1) +void ADMA_UART1_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(ADMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART1)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__LPUART2) +void ADMA_UART2_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(ADMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART2)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(ADMA__LPUART3) +void ADMA_UART3_INT_DriverIRQHandler(void) +{ + s_lpuartIsr(ADMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART3)]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpuart.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpuart.h new file mode 100644 index 0000000000..ddfa6f6d6b --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpuart.h @@ -0,0 +1,854 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_LPUART_H_ +#define _FSL_LPUART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpuart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPUART driver version 2.2.7. */ +#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 7)) +/*@}*/ + +/*! @brief Error codes for the LPUART driver. */ +enum _lpuart_status +{ + kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */ + kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */ + kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */ + kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */ + kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */ + kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */ + kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */ + kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */ + kStatus_LPUART_RxRingBufferOverrun = + MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */ + kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */ + kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */ + kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */ + kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */ + kStatus_LPUART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */ + kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */ +}; + +/*! @brief LPUART parity mode. */ +typedef enum _lpuart_parity_mode +{ + kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} lpuart_parity_mode_t; + +/*! @brief LPUART data bits count. */ +typedef enum _lpuart_data_bits +{ + kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */ +#endif +} lpuart_data_bits_t; + +/*! @brief LPUART stop bit count. */ +typedef enum _lpuart_stop_bit_count +{ + kLPUART_OneStopBit = 0U, /*!< One stop bit */ + kLPUART_TwoStopBit = 1U, /*!< Two stop bits */ +} lpuart_stop_bit_count_t; + +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT +/*! @brief LPUART transmit CTS source. */ +typedef enum _lpuart_transmit_cts_source +{ + kLPUART_CtsSourcePin = 0U, /*!< CTS resource is the LPUART_CTS pin. */ + kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */ +} lpuart_transmit_cts_source_t; + +/*! @brief LPUART transmit CTS configure. */ +typedef enum _lpuart_transmit_cts_config +{ + kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */ + kLPUART_CtsSampleAtIdle = 1U, /*!< CTS input is sampled when the transmitter is idle */ +} lpuart_transmit_cts_config_t; +#endif + +/*! @brief LPUART idle flag type defines when the receiver starts counting. */ +typedef enum _lpuart_idle_type_select +{ + kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */ + kLPUART_IdleTypeStopBit = 1U, /*!< Start counting after a stop bit. */ +} lpuart_idle_type_select_t; + +/*! @brief LPUART idle detected configuration. + * This structure defines the number of idle characters that must be received before + * the IDLE flag is set. + */ +typedef enum _lpuart_idle_config +{ + kLPUART_IdleCharacter1 = 0U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter2 = 1U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter4 = 2U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter8 = 3U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter16 = 4U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter32 = 5U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter64 = 6U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */ +} lpuart_idle_config_t; + +/*! + * @brief LPUART interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all LPUART interrupt configurations. + */ +enum _lpuart_interrupt_enable +{ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8), /*!< LIN break detect. */ +#endif + kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8), /*!< Receive Active Edge. */ + kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. */ + kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. */ + kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. */ + kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. */ + kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. */ + kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. */ + kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. */ + kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK >> 8), /*!< Transmit FIFO Overflow. */ + kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK >> 8), /*!< Receive FIFO Underflow. */ +#endif +}; + +/*! + * @brief LPUART status flags. + * + * This provides constants for the LPUART status flags for use in the LPUART functions. + */ +enum _lpuart_flags +{ + kLPUART_TxDataRegEmptyFlag = + (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty */ + kLPUART_TransmissionCompleteFlag = + (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete */ + kLPUART_RxDataRegFullFlag = + (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive data buffer is full */ + kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected */ + kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is + read from receive register */ + kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these + samples differ, noise flag sets */ + kLPUART_FramingErrorFlag = + (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */ + kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection */ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakFlag = (int)(LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break + char detected and LIN circuit enabled */ +#endif + kLPUART_RxActiveEdgeFlag = + (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active edge detected */ + kLPUART_RxActiveFlag = + (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */ +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + kLPUART_DataMatch1Flag = LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1*/ + kLPUART_DataMatch2Flag = LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2*/ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS + kLPUART_NoiseErrorInRxDataRegFlag = + (LPUART_DATA_NOISY_MASK >> 10), /*!< NOISY bit, sets if noise detected in current data word */ + kLPUART_ParityErrorInRxDataRegFlag = + (LPUART_DATA_PARITYE_MASK >> 10), /*!< PARITY bit, sets if noise detected in current data word */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoEmptyFlag = (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty */ + kLPUART_RxFifoEmptyFlag = (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty */ + kLPUART_TxFifoOverflowFlag = + (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred */ + kLPUART_RxFifoUnderflowFlag = + (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred */ +#endif +}; + +/*! @brief LPUART configuration structure. */ +typedef struct _lpuart_config +{ + uint32_t baudRate_Bps; /*!< LPUART baud rate */ + lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */ + bool isMsb; /*!< Data bits order, LSB (default), MSB */ +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + uint8_t txFifoWatermark; /*!< TX FIFO watermark */ + uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + bool enableRxRTS; /*!< RX RTS enable */ + bool enableTxCTS; /*!< TX CTS enable */ + lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */ + lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */ +#endif + lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */ + lpuart_idle_config_t rxIdleConfig; /*!< RX IDLE configuration. */ + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ +} lpuart_config_t; + +/*! @brief LPUART transfer structure. */ +typedef struct _lpuart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} lpuart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_handle lpuart_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData); + +/*! @brief LPUART handle structure. */ +struct _lpuart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + lpuart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state. */ + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + bool isSevenDataBits; /*!< Seven data bits flag. */ +#endif +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Resets the LPUART using software. + * + * This function resets all internal logic and registers except the Global Register. + * Remains set until cleared by software. + * + * @param base LPUART peripheral base address. + */ +static inline void LPUART_SoftwareReset(LPUART_Type *base) +{ + base->GLOBAL |= LPUART_GLOBAL_RST_MASK; + base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; +} +/* @} */ +#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. + * + * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the LPUART. + * @code + * lpuart_config_t lpuartConfig; + * lpuartConfig.baudRate_Bps = 115200U; + * lpuartConfig.parityMode = kLPUART_ParityDisabled; + * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig.isMsb = false; + * lpuartConfig.stopBitCount = kLPUART_OneStopBit; + * lpuartConfig.txFifoWatermark = 0; + * lpuartConfig.rxFifoWatermark = 1; + * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param config Pointer to a user-defined configuration structure. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success LPUART initialize succeed + */ +status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * @param base LPUART peripheral base address. + */ +void LPUART_Deinit(LPUART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig->isMsb = false; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; + * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * @param config Pointer to a configuration structure. + */ +void LPUART_GetDefaultConfig(lpuart_config_t *config); + +/*! + * @brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * @code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param baudRate_Bps LPUART baudrate to be set. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. + * @retval kStatus_Success Set baudrate succeeded. + */ +status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators @ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _lpuart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ +uint32_t LPUART_GetStatusFlags(LPUART_Type *base); + +/*! + * @brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorInRxDataRegFlag, kLPUART_ParityErrorInRxDataRegFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * @param base LPUART peripheral base address. + * @param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * @return 0 succeed, others failed. + * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * @retval kStatus_Success Status in the mask are cleared. + */ +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask); + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * @code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable. + */ +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable. + */ +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in @ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * @code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable. + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base); + +#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE +/*! + * @brief Gets the LPUART data register address. + * + * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA. + * + * @param base LPUART peripheral base address. + * @return LPUART data register addresses which are used both by the transmitter and receiver. + */ +static inline uint32_t LPUART_GetDataRegisterAddress(LPUART_Type *base) +{ + return (uint32_t) & (base->DATA); +} + +/*! + * @brief Enables or disables the LPUART transmitter DMA request. + * + * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_TDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_TDMAE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver DMA. + * + * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_RDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_RDMAE_MASK; + } +} + +/* @} */ +#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Get the LPUART instance from peripheral base address. + * + * @param base LPUART peripheral base address. + * @return LPUART instance. + */ +uint32_t LPUART_GetInstance(LPUART_Type *base); + +/*! + * @brief Enables or disables the LPUART transmitter. + * + * This function enables or disables the LPUART transmitter. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_TE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_TE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver. + * + * This function enables or disables the LPUART receiver. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_RE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_RE_MASK; + } +} + +/*! + * @brief Writes to the transmitter register. + * + * This function writes data to the transmitter register directly. The upper layer must + * ensure that the TX register is empty or that the TX FIFO has room before calling this function. + * + * @param base LPUART peripheral base address. + * @param data Data write to the TX register. + */ +static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data) +{ + base->DATA = data; +} + +/*! + * @brief Reads the receiver register. + * + * This function reads data from the receiver register directly. The upper layer must + * ensure that the receiver register is full or that the RX FIFO has data before calling this function. + * + * @param base LPUART peripheral base address. + * @return Data read from data register. + */ +static inline uint8_t LPUART_ReadByte(LPUART_Type *base) +{ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = + ((ctrl & LPUART_CTRL_M7_MASK) || + ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK))); + + if (isSevenDataBits) + { + return (base->DATA & 0x7F); + } + else + { + return base->DATA; + } +#else + return (uint8_t)(base->DATA); +#endif +} + +/*! + * @brief Writes to the transmitter register using a blocking method. + * + * This function polls the transmitter register, waits for the register to be empty or for TX FIFO to have + * room, and writes data to the transmitter buffer. + * + * @note This function does not check whether all data has been sent out to the bus. + * Before disabling the transmitter, check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is + * finished. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + */ +void LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Reads the receiver data register using a blocking method. + * + * This function polls the receiver register, waits for the receiver register full or receiver FIFO + * has data, and reads data from the TX register. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * @retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as @p ringBuffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData); +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the @ref kStatus_LPUART_TxIdle as status parameter. + * + * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see #lpuart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle LPUART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are not sent out. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been written to the LPUART transmitter register. + * + * This function gets the number of bytes that have been written to LPUART TX + * register by an interrupt method. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter @ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see #uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into the transmit queue. + * @retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferHandleIRQ(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_LPUART_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpuart_edma.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpuart_edma.c new file mode 100644 index 0000000000..5e7561399c --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpuart_edma.c @@ -0,0 +1,439 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpuart_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpuart_edma" +#endif + +/*base, lpuartPrivateHandle->handle); + + if (NULL != lpuartPrivateHandle->handle->callback) + { + lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, + kStatus_LPUART_TxIdle, lpuartPrivateHandle->handle->userData); + } + } +} + +static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + assert(NULL != param); + + lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param; + + /* Avoid warning for unused parameters. */ + handle = handle; + tcds = tcds; + + if (transferDone) + { + /* Disable transfer. */ + LPUART_TransferAbortReceiveEDMA(lpuartPrivateHandle->base, lpuartPrivateHandle->handle); + + if (NULL != lpuartPrivateHandle->handle->callback) + { + lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, + kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData); + } + } +} + +/*! + * brief Initializes the LPUART handle which is used in transactional functions. + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + * param callback Callback function. + * param userData User data. + * param txEdmaHandle User requested DMA handle for TX DMA transfer. + * param rxEdmaHandle User requested DMA handle for RX DMA transfer. + */ +void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, + lpuart_edma_handle_t *handle, + lpuart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle) +{ + assert(NULL != handle); + + uint32_t instance = LPUART_GetInstance(base); + + s_lpuartEdmaPrivateHandle[instance].base = base; + s_lpuartEdmaPrivateHandle[instance].handle = handle; + + (void)memset(handle, 0, sizeof(*handle)); + + handle->rxState = (uint8_t)kLPUART_RxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; + + handle->rxEdmaHandle = rxEdmaHandle; + handle->txEdmaHandle = txEdmaHandle; + + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Note: + Take care of the RX FIFO, EDMA request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + EDMA transfer because the water mark is 2. + */ + if (NULL != rxEdmaHandle) + { + base->WATER &= (~LPUART_WATER_RXWATER_MASK); + } +#endif + + /* Configure TX. */ + if (NULL != txEdmaHandle) + { + EDMA_SetCallback(handle->txEdmaHandle, LPUART_SendEDMACallback, &s_lpuartEdmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (NULL != rxEdmaHandle) + { + EDMA_SetCallback(handle->rxEdmaHandle, LPUART_ReceiveEDMACallback, &s_lpuartEdmaPrivateHandle[instance]); + } +} + +/*! + * brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_LPUART_TxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); + + edma_transfer_config_t xferConfig; + status_t status; + + /* If previous TX not finished. */ + if ((uint8_t)kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + handle->txState = (uint8_t)kLPUART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), + (void *)(uint32_t *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), sizeof(uint8_t), + xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ + handle->nbytes = (uint8_t)sizeof(uint8_t); + + /* Submit transfer. */ + if (kStatus_Success != + EDMA_SubmitTransfer(handle->txEdmaHandle, (const edma_transfer_config_t *)(uint32_t)&xferConfig)) + { + return kStatus_Fail; + } + EDMA_StartTransfer(handle->txEdmaHandle); + + /* Enable LPUART TX EDMA. */ + LPUART_EnableTxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Receives data using eDMA. + * + * This function receives data using eDMA. This is non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + * param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t. + * retval kStatus_Success if succeed, others fail. + * retval kStatus_LPUART_RxBusy Previous transfer ongoing. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); + + edma_transfer_config_t xferConfig; + status_t status; + + /* If previous RX not finished. */ + if ((uint8_t)kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + handle->rxState = (uint8_t)kLPUART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, (void *)(uint32_t *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), + xfer->data, sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ + handle->nbytes = (uint8_t)sizeof(uint8_t); + + /* Submit transfer. */ + if (kStatus_Success != + EDMA_SubmitTransfer(handle->rxEdmaHandle, (const edma_transfer_config_t *)(uint32_t)&xferConfig)) + { + return kStatus_Fail; + } + EDMA_StartTransfer(handle->rxEdmaHandle); + + /* Enable LPUART RX EDMA. */ + LPUART_EnableRxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the sent data using eDMA. + * + * This function aborts the sent data using eDMA. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + + /* Disable LPUART TX EDMA. */ + LPUART_EnableTxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->txEdmaHandle); + + handle->txState = (uint8_t)kLPUART_TxIdle; +} + +/*! + * brief Aborts the received data using eDMA. + * + * This function aborts the received data using eDMA. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + + /* Disable LPUART RX EDMA. */ + LPUART_EnableRxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->rxEdmaHandle); + + handle->rxState = (uint8_t)kLPUART_RxIdle; +} + +/*! + * brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + assert(NULL != count); + + if ((uint8_t)kLPUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - + ((uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel)); + + return kStatus_Success; +} + +/*! + * brief Gets the number of bytes written to the LPUART TX register. + * + * This function gets the number of bytes written to the LPUART TX + * register by DMA. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + assert(NULL != count); + + if ((uint8_t)kLPUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - + ((uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel)); + + return kStatus_Success; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpuart_edma.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpuart_edma.h new file mode 100644 index 0000000000..53ac71036b --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_lpuart_edma.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_LPUART_EDMA_H_ +#define _FSL_LPUART_EDMA_H_ + +#include "fsl_lpuart.h" +#include "fsl_edma.h" + +/*! + * @addtogroup lpuart_edma_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPUART EDMA driver version 2.2.7. */ +#define FSL_LPUART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 7)) +/*@}*/ + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_edma_handle lpuart_edma_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base, + lpuart_edma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief LPUART eDMA handle + */ +struct _lpuart_edma_handle +{ + lpuart_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ + edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ + + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle which is used in transactional functions. + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + * @param callback Callback function. + * @param userData User data. + * @param txEdmaHandle User requested DMA handle for TX DMA transfer. + * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. + */ +void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, + lpuart_edma_handle_t *handle, + lpuart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle); + +/*! + * @brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_LPUART_TxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Receives data using eDMA. + * + * This function receives data using eDMA. This is non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + * @param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others fail. + * @retval kStatus_LPUART_RxBusy Previous transfer ongoing. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data using eDMA. + * + * This function aborts the sent data using eDMA. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); + +/*! + * @brief Aborts the received data using eDMA. + * + * This function aborts the received data using eDMA. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); + +/*! + * @brief Gets the number of bytes written to the LPUART TX register. + * + * This function gets the number of bytes written to the LPUART TX + * register by DMA. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); + +/*! + * @brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_LPUART_EDMA_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_ocotp.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_ocotp.c new file mode 100644 index 0000000000..9ac6f0056b --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_ocotp.c @@ -0,0 +1,263 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_ocotp.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ocotp" +#endif + +/* Wait time should be not less than 150ns . */ +#define OCOTP_TIMING_WAIT_NS (uint64_t)150 +/* Relex time should be not less than 100ns . */ +#define OCOTP_TIMING_RELEX_NS (uint64_t)100 +/* Program time should be rang from 9000ns~11000ns. */ +#define OCOTP_TIMING_PROGRAM_NS (uint64_t)10000 +/* Read time should be less than 40ns. */ +#define OCOTP_TIMING_READ_NS (uint64_t)40 + +/* Unlock key is 0x3E77. */ +#define OCOTP_WRITE_UNLOCK_KEY (0x3E77) +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Set read timing configuration. + * + * @param base OCOTP peripheral base addess. + * @param timingConfig configuration of timing. + */ +static void OCOTP_SetReadTiming(OCOTP_Type *base, ocotp_timing_t timingConfig); + +/*! + * @brief Set write timing configuration. + * + * @param base OCOTP peripheral base addess. + * @param timingConfig configuration of timing. + */ +static void OCOTP_SetWriteTiming(OCOTP_Type *base, ocotp_timing_t timingConfig); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Timing configuration for OCOTP controller. */ +ocotp_timing_t s_timingConfig; + +/******************************************************************************* + * Code + *******************************************************************************/ +/* Reload the shadow register. */ +void OCOTP_ReloadShadowRegister(OCOTP_Type *base) +{ + assert(NULL != base); + + /* Make sure the OCOTP is ready, Overlapped accesses are not supported by the controller. */ + while (OCOTP_CheckBusyStatus(base)) + { + } + + /* Clear access error status bit. */ + OCOTP_ClearErrorStatus(base); + + /* Set the read timing. */ + OCOTP_SetReadTiming(base, s_timingConfig); + + /* Wait for the OCOTP controller not busy. */ + while (OCOTP_CheckBusyStatus(base)) + { + } + + /* Set reload bit. */ + base->CTRL_SET = OCOTP_CTRL_RELOAD_SHADOWS(1); + + /* Wait for the OCOTP controller not busy. */ + while (OCOTP_CheckBusyStatus(base)) + { + } + /* Wait for shadow register reload complete. this bit will be auto clear by OCOTP once operation is complete. */ + while (OCOTP_CTRL_RELOAD_SHADOWS_MASK == (base->CTRL & OCOTP_CTRL_RELOAD_SHADOWS_MASK)) + { + } +} + +static void OCOTP_SetReadTiming(OCOTP_Type *base, ocotp_timing_t timingConfig) +{ + uint32_t timingValue = base->TIMING; + + timingValue &= ~(OCOTP_TIMING_RELAX_MASK | OCOTP_TIMING_STROBE_READ_MASK | OCOTP_TIMING_WAIT_MASK); + timingValue |= OCOTP_TIMING_RELAX(timingConfig.relax) | OCOTP_TIMING_STROBE_READ(timingConfig.strobe_read) | + OCOTP_TIMING_WAIT(timingConfig.wait); + base->TIMING = timingValue; +} + +static void OCOTP_SetWriteTiming(OCOTP_Type *base, ocotp_timing_t timingConfig) +{ + uint32_t timingValue = base->TIMING; + + timingValue &= ~(OCOTP_TIMING_RELAX_MASK | OCOTP_TIMING_STROBE_PROG_MASK | OCOTP_TIMING_WAIT_MASK); + timingValue |= OCOTP_TIMING_RELAX(timingConfig.relax) | OCOTP_TIMING_STROBE_PROG(timingConfig.strobe_prog) | + OCOTP_TIMING_WAIT(timingConfig.wait); + + base->TIMING = timingValue; +} + +/* Initializes OCOTP controller. */ +void OCOTP_Init(OCOTP_Type *base, uint32_t srcClock_Hz) +{ + assert(NULL != base); + assert(0UL != srcClock_Hz); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable OCOTP clock */ + CLOCK_EnableClock(kCLOCK_Ocotp); +#endif + + /* tWait time shoule be higher than OCOTP_TIMING_WAIT_NS. */ + s_timingConfig.wait = (OCOTP_TIMING_WAIT_NS * srcClock_Hz + 1000000000) / 1000000000 - 1; + + /* tRelax time shoule be higher than OCOTP_TIMING_RELEX_NS. */ + s_timingConfig.relax = (OCOTP_TIMING_RELEX_NS * srcClock_Hz + 1000000000) / 1000000000 - 1; + + /* tStrobe_prog time should be close to OCOTP_TIMING_PROGRAM_NS, only add half of 1000000000. */ + s_timingConfig.strobe_prog = + (OCOTP_TIMING_PROGRAM_NS * srcClock_Hz + 500000000) / 1000000000 + 2 * (s_timingConfig.relax + 1) - 1; + + /* tStrobe_read time should be higher than OCOTP_TIMING_READ_NS. */ + s_timingConfig.strobe_read = + (OCOTP_TIMING_READ_NS * srcClock_Hz + 1000000000) / 1000000000 + 2 * (s_timingConfig.relax + 1) - 1; +} + +/* De-init OCOTP controller. */ +void OCOTP_Deinit(OCOTP_Type *base) +{ + assert(NULL != base); + + s_timingConfig.wait = 0UL; + s_timingConfig.relax = 0UL; + s_timingConfig.strobe_prog = 0UL; + s_timingConfig.strobe_read = 0UL; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable OCOTP clock */ + CLOCK_DisableClock(kCLOCK_Ocotp); +#endif +} + +/* Read the fuse shadow register. */ +uint32_t OCOTP_ReadFuseShadowRegister(OCOTP_Type *base, uint32_t address) +{ + assert(NULL != base); + + /* Make sure the OCOTP is ready, Overlapped accesses are not supported by the controller. */ + while (OCOTP_CheckBusyStatus(base)) + { + } + + /* If ERROR bit was set, clear access error status bit. */ + if (OCOTP_CheckErrorStatus(base)) + { + OCOTP_ClearErrorStatus(base); + } + + /* Set the read timing. */ + OCOTP_SetReadTiming(base, s_timingConfig); + + /* Wait for busy bit is cleared. */ + while (OCOTP_CheckBusyStatus(base)) + { + } + + /* Clear access error status bit. */ + if (OCOTP_CheckErrorStatus(base)) + { + OCOTP_ClearErrorStatus(base); + } + + /* Write requested address to register. */ + base->CTRL_CLR = OCOTP_CTRL_CLR_ADDR_MASK; + base->CTRL_SET = OCOTP_CTRL_SET_ADDR(address); + + /* Set OCOTP auto read enable. */ + base->READ_CTRL = OCOTP_READ_CTRL_READ_FUSE_MASK; + + /* Wait for busy bit is cleared, and no error occurred on controller. */ + while (OCOTP_CheckBusyStatus(base)) + { + } + + /* If ERROR bit was set, this may be mean that the accsee to the register was wrong. */ + if (OCOTP_CheckErrorStatus(base)) + { + /* Clear access error status bit. */ + OCOTP_ClearErrorStatus(base); + } + + /* Read the fuse data. */ + return (base->READ_FUSE_DATA); +} + +/* Write the fuse shadow register. */ +status_t OCOTP_WriteFuseShadowRegister(OCOTP_Type *base, uint32_t address, uint32_t data) +{ + assert(NULL != base); + + /* Make sure the OCOTP is ready, Overlapped accesses are not supported by the controller. */ + while (OCOTP_CheckBusyStatus(base)) + { + } + + /* Clear access error status bit. */ + if (OCOTP_CheckErrorStatus(base)) + { + OCOTP_ClearErrorStatus(base); + } + + /* Set write timing for OCOTP controller. */ + OCOTP_SetWriteTiming(base, s_timingConfig); + + /* Wait for busy bit is cleared. */ + while (OCOTP_CheckBusyStatus(base)) + { + } + + /* Clear access error status bit. */ + if (OCOTP_CheckErrorStatus(base)) + { + OCOTP_ClearErrorStatus(base); + } + + /* Write requested address and unlock key to register. */ + base->CTRL_CLR = OCOTP_CTRL_CLR_ADDR_MASK | OCOTP_CTRL_WR_UNLOCK_MASK; + base->CTRL_SET = OCOTP_CTRL_SET_ADDR(address) | OCOTP_CTRL_WR_UNLOCK(OCOTP_WRITE_UNLOCK_KEY); + + /* Write data to register. */ + base->DATA = data; + + /* Wait for busy bit is cleared, and no error occurred on controller. */ + while (OCOTP_CheckBusyStatus(base)) + { + } + + /* If ERROR bit was set, this may be mean that the accsee to the register was wrong. */ + if (OCOTP_CheckErrorStatus(base)) + { + /* Clear access error status bit. */ + OCOTP_ClearErrorStatus(base); + + return kStatus_OCOTP_AccessError; + } + + /* Reload the fuse register. */ + OCOTP_ReloadShadowRegister(base); + + return kStatus_Success; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_ocotp.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_ocotp.h new file mode 100644 index 0000000000..d962187337 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_ocotp.h @@ -0,0 +1,153 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_OCOTP_H_ +#define _FSL_OCOTP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ocotp + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief OCOTP driver version 2.0.0 */ +#define FSL_OCOTP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! @brief Error codes for the OCOTP driver. */ +enum _ocotp_status +{ + kStatus_OCOTP_AccessError = MAKE_STATUS(kStatusGroup_SDK_OCOTP, 0), /*!< eFuse and shadow register access error. */ + kStatus_OCOTP_CrcFail = MAKE_STATUS(kStatusGroup_SDK_OCOTP, 1), /*!< CRC check failed. */ +}; + +/*! @brief OCOTP timing structure. + * Note that, these value are used for calcalating the read/write timings. + * And the values should statisfy below rules: + * + * Tsp_rd=(WAIT+1)/ipg_clk_freq should be >= 150ns; + * Tsp_pgm=(RELAX+1)/ipg_clk_freq should be >= 100ns; + * Trd = ((STROBE_READ+1)- 2*(RELAX_READ+1)) /ipg_clk_freq, + * The Trd is required to be larger than 40 ns. + * Tpgm = ((STROBE_PROG+1)- 2*(RELAX_PROG+1)) /ipg_clk_freq; + * The Tpgm should be configured within the range of 9000 ns < Tpgm < 11000 ns; + */ +typedef struct _ocotp_timing +{ + uint32_t wait; /*!< Wait time value to fill in the TIMING register. */ + uint32_t relax; /*!< Relax time value to fill in the TIMING register. */ + uint32_t strobe_prog; /*!< Storbe program time value to fill in the TIMING register. */ + uint32_t strobe_read; /*!< Storbe read time value to fill in the TIMING register. */ +} ocotp_timing_t; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes OCOTP controller. + * + * @param base OCOTP peripheral base address. + * @param srcClock_Hz source clock frequency in unit of Hz. + */ +void OCOTP_Init(OCOTP_Type *base, uint32_t srcClock_Hz); + +/*! + * @brief De-initializes OCOTP controller. + * + * @retval kStatus_Success upon successful execution, error status otherwise. + */ +void OCOTP_Deinit(OCOTP_Type *base); + +/*! + * @brief Checking the BUSY bit in CTRL register. + * Checking this BUSY bit will help confirm if the OCOTP controller is ready for access. + * + * @param base OCOTP peripheral base address. + * @retval true for bit set and false for cleared. + */ +static inline bool OCOTP_CheckBusyStatus(OCOTP_Type *base) +{ + return ((OCOTP_CTRL_BUSY_MASK == (base->CTRL & OCOTP_CTRL_BUSY_MASK)) ? (true) : (false)); +} + +/*! + * @brief Checking the ERROR bit in CTRL register. + * + * @param base OCOTP peripheral base address. + * @retval true for bit set and false for cleared. + */ +static inline bool OCOTP_CheckErrorStatus(OCOTP_Type *base) +{ + return ((OCOTP_CTRL_ERROR_MASK == (base->CTRL & OCOTP_CTRL_ERROR_MASK)) ? (true) : (false)); +} + +/*! + * @brief Clear the error bit if this bit is set. + * + * @param base OCOTP peripheral base address. + */ +static inline void OCOTP_ClearErrorStatus(OCOTP_Type *base) +{ + base->CTRL_CLR = OCOTP_CTRL_CLR_ERROR_MASK; +} + +/*! + * @brief Reload the shadow register. + * This function will help reload the shadow register without reseting the OCOTP module. + * Please make sure the OCOTP has been initialized before calling this API. + * + * @param base OCOTP peripheral base addess. + */ +void OCOTP_ReloadShadowRegister(OCOTP_Type *base); + +/*! + * @brief Read the fuse shadow register with the fuse addess. + * + * @param base OCOTP peripheral base address. + * @param address the fuse address to be read from. + */ +uint32_t OCOTP_ReadFuseShadowRegister(OCOTP_Type *base, uint32_t address); + +/*! + * @brief Write the fuse shadow register with the fuse addess and data. + * Please make sure the wrtie address is not locked while calling this API. + * + * @param base OCOTP peripheral base address. + * @param address the fuse address to be written. + * @param data the value will be writen to fuse address. + * @retval write status, kStatus_Success for success and kStatus_Fail for failed. + */ +status_t OCOTP_WriteFuseShadowRegister(OCOTP_Type *base, uint32_t address, uint32_t data); + +/*! + * @brief Get the OCOTP controller version from the register. + * + * @param base OCOTP peripheral base address. + * @retval return the version value. + */ +static inline uint32_t OCOTP_GetVersion(OCOTP_Type *base) +{ + return (base->VERSION); +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_OCOTP_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_os_abstraction.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_os_abstraction.h new file mode 100644 index 0000000000..379bde9c2c --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_os_abstraction.h @@ -0,0 +1,812 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_OS_ABSTRACTION_H_ +#define _FSL_OS_ABSTRACTION_H_ + +#include "fsl_common.h" +#include "fsl_os_abstraction_config.h" +#include "generic_list.h" + +/*! + * @addtogroup osa_adapter + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Type for the Task Priority*/ +typedef uint16_t osa_task_priority_t; +/*! @brief Type for a task handler */ +typedef void *osa_task_handle_t; +/*! @brief Type for the parameter to be passed to the task at its creation */ +typedef void *osa_task_param_t; +/*! @brief Type for task pointer. Task prototype declaration */ +typedef void (*osa_task_ptr_t)(osa_task_param_t task_param); +/*! @brief Type for the semaphore handler */ +typedef void *osa_semaphore_handle_t; +/*! @brief Type for the mutex handler */ +typedef void *osa_mutex_handle_t; +/*! @brief Type for the event handler */ +typedef void *osa_event_handle_t; +/*! @brief Type for an event flags group, bit 32 is reserved. */ +typedef uint32_t osa_event_flags_t; +/*! @brief Message definition. */ +typedef void *osa_msg_handle_t; +/*! @brief Type for the message queue handler */ +typedef void *osa_msgq_handle_t; +/*! @brief Type for the Timer handler */ +typedef void *osa_timer_handle_t; +/*! @brief Type for the Timer callback function pointer. */ +typedef void (*osa_timer_fct_ptr_t)(void const *argument); +/*! @brief Thread Definition structure contains startup information of a thread.*/ +typedef struct osa_task_def_tag +{ + osa_task_ptr_t pthread; /*!< start address of thread function*/ + uint32_t tpriority; /*!< initial thread priority*/ + uint32_t instances; /*!< maximum number of instances of that thread function*/ + uint32_t stacksize; /*!< stack size requirements in bytes; 0 is default stack size*/ + uint32_t *tstack; /*!< stack pointer*/ + void *tlink; /*!< link pointer*/ + uint8_t *tname; /*!< name pointer*/ + uint8_t useFloat; /*!< is use float*/ +} osa_task_def_t; +/*! @brief Thread Link Definition structure .*/ +typedef struct osa_thread_link_tag +{ + uint8_t link[12]; /*!< link*/ + osa_task_handle_t osThreadId; /*!< thread id*/ + osa_task_def_t *osThreadDefHandle; /*!< pointer of thread define handle*/ + uint32_t *osThreadStackHandle; /*!< pointer of thread stack handle*/ +} osa_thread_link_t, *osa_thread_link_handle_t; + +/*! @brief Definition structure contains timer parameters.*/ +typedef struct osa_time_def_tag +{ + osa_timer_fct_ptr_t pfCallback; /* < start address of a timer function */ + void *argument; /* < argument of a timer function */ +} osa_time_def_t; + +/*! @brief Type for the timer definition*/ +typedef enum _osa_timer +{ + KOSA_TimerOnce = 0, /*!< one-shot timer*/ + KOSA_TimerPeriodic = 1 /*!< repeating timer*/ +} osa_timer_t; + +/*! @brief Defines the return status of OSA's functions */ +typedef enum _osa_status +{ + KOSA_StatusSuccess = kStatus_Success, /*!< Success */ + KOSA_StatusError = MAKE_STATUS(kStatusGroup_OSA, 1), /*!< Failed */ + KOSA_StatusTimeout = MAKE_STATUS(kStatusGroup_OSA, 2), /*!< Timeout occurs while waiting */ + KOSA_StatusIdle = MAKE_STATUS(kStatusGroup_OSA, 3), /*!< Used for bare metal only, the wait object is not ready + and timeout still not occur */ +} osa_status_t; + +#ifdef USE_RTOS +#undef USE_RTOS +#endif + +#define USE_RTOS (1) +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#define OSA_TASK_HANDLE_SIZE (12U) +#else +#define OSA_TASK_HANDLE_SIZE (16U) +#endif +#define OSA_EVENT_HANDLE_SIZE (8U) +#define OSA_SEM_HANDLE_SIZE (4U) +#define OSA_MUTEX_HANDLE_SIZE (4U) +#define OSA_MSGQ_HANDLE_SIZE (4U) +#define OSA_MSG_HANDLE_SIZE (0U) + +/*! @brief Priority setting for OSA. */ +#ifndef OSA_PRIORITY_IDLE +#define OSA_PRIORITY_IDLE (6) +#endif + +#ifndef OSA_PRIORITY_LOW +#define OSA_PRIORITY_LOW (5) +#endif + +#ifndef OSA_PRIORITY_BELOW_NORMAL +#define OSA_PRIORITY_BELOW_NORMAL (4) +#endif + +#ifndef OSA_PRIORITY_NORMAL +#define OSA_PRIORITY_NORMAL (3) +#endif + +#ifndef OSA_PRIORITY_ABOVE_NORMAL +#define OSA_PRIORITY_ABOVE_NORMAL (2) +#endif + +#ifndef OSA_PRIORITY_HIGH +#define OSA_PRIORITY_HIGH (1) +#endif + +#ifndef OSA_PRIORITY_REAL_TIME +#define OSA_PRIORITY_REAL_TIME (0) +#endif + +#ifndef OSA_TASK_PRIORITY_MAX +#define OSA_TASK_PRIORITY_MAX (0) +#endif + +#ifndef OSA_TASK_PRIORITY_MIN +#define OSA_TASK_PRIORITY_MIN (15) +#endif + +#define SIZE_IN_UINT32_UNITS(size) (((size) + sizeof(uint32_t) - 1) / sizeof(uint32_t)) + +/*! @brief Constant to pass as timeout value in order to wait indefinitely. */ +#define osaWaitForever_c ((uint32_t)(-1)) +#define osaEventFlagsAll_c ((osa_event_flags_t)(0x00FFFFFF)) +#define osThreadStackArray(name) osThread_##name##_stack +#define osThreadStackDef(name, stacksize, instances) \ + uint32_t osThreadStackArray(name)[SIZE_IN_UINT32_UNITS(stacksize) * (instances)]; + +/* ==== Thread Management ==== */ + +/* Create a Thread Definition with function, priority, and stack requirements. + * \param name name of the thread function. + * \param priority initial priority of the thread function. + * \param instances number of possible thread instances. + * \param stackSz stack size (in bytes) requirements for the thread function. + * \param useFloat + */ +#if defined(FSL_RTOS_MQX) +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ + osa_thread_link_t osThreadLink_##name[instances] = {0}; \ + osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \ + (name), (priority), (instances), (stackSz), osThreadStackArray(name), osThreadLink_##name, \ + (uint8_t *)#name, (useFloat)} +#elif defined(FSL_RTOS_UCOSII) +#if gTaskMultipleInstancesManagement_c +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ + osa_thread_link_t osThreadLink_##name[instances] = {0}; \ + osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \ + (name), (priority), (instances), (stackSz), osThreadStackArray(name), osThreadLink_##name, \ + (uint8_t *)#name, (useFloat)} +#else +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ + osThreadStackDef(name, stackSz, instances) osa_task_def_t os_thread_def_##name = { \ + (name), (priority), (instances), (stackSz), osThreadStackArray(name), NULL, (uint8_t *)#name, (useFloat)} +#endif +#else +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ + osa_task_def_t os_thread_def_##name = {(name), (priority), (instances), (stackSz), \ + NULL, NULL, (uint8_t *)#name, (useFloat)} +#endif +/* Access a Thread defintion. + * \param name name of the thread definition object. + */ +#define OSA_TASK(name) &os_thread_def_##name + +#define OSA_TASK_PROTO(name) externosa_task_def_t os_thread_def_##name +/* ==== Timer Management ==== + * Define a Timer object. + * \param name name of the timer object. + * \param function name of the timer call back function. + */ + +#define OSA_TIMER_DEF(name, function) osa_time_def_t os_timer_def_##name = {(function), NULL} + +/* Access a Timer definition. + * \param name name of the timer object. + */ +#define OSA_TIMER(name) &os_timer_def_##name + +/* ==== Buffer Definition ==== */ + +/*! + * @brief Defines the semaphore handle + * + * This macro is used to define a 4 byte aligned semaphore handle. + * Then use "(osa_semaphore_handle_t)name" to get the semaphore handle. + * + * The macro should be global and could be optional. You could also define semaphore handle by yourself. + * + * This is an example, + * @code + * OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle); + * @endcode + * + * @param name The name string of the semaphore handle. + */ +#define OSA_SEMAPHORE_HANDLE_DEFINE(name) \ + uint32_t name[(OSA_SEM_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] + +/*! + * @brief Defines the mutex handle + * + * This macro is used to define a 4 byte aligned mutex handle. + * Then use "(osa_mutex_handle_t)name" to get the mutex handle. + * + * The macro should be global and could be optional. You could also define mutex handle by yourself. + * + * This is an example, + * @code + * OSA_MUTEX_HANDLE_DEFINE(mutexHandle); + * @endcode + * + * @param name The name string of the mutex handle. + */ +#define OSA_MUTEX_HANDLE_DEFINE(name) uint32_t name[(OSA_MUTEX_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] + +/*! + * @brief Defines the event handle + * + * This macro is used to define a 4 byte aligned event handle. + * Then use "(osa_event_handle_t)name" to get the event handle. + * + * The macro should be global and could be optional. You could also define event handle by yourself. + * + * This is an example, + * @code + * OSA_EVENT_HANDLE_DEFINE(eventHandle); + * @endcode + * + * @param name The name string of the event handle. + */ +#define OSA_EVENT_HANDLE_DEFINE(name) uint32_t name[(OSA_EVENT_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] + +/*! + * @brief Defines the message queue handle + * + * This macro is used to define a 4 byte aligned message queue handle. + * Then use "(osa_msgq_handle_t)name" to get the message queue handle. + * + * The macro should be global and could be optional. You could also define message queue handle by yourself. + * + * This is an example, + * @code + * OSA_MSGQ_HANDLE_DEFINE(msgqHandle, 3, sizeof(msgStruct)); + * @endcode + * + * @param name The name string of the message queue handle. + * @param numberOfMsgs Number of messages. + * @param msgSize Message size. + * + */ + +/*< Macro For FREE_RTOS*/ +#define OSA_MSGQ_HANDLE_DEFINE(name, numberOfMsgs, msgSize) \ + uint32_t name[(OSA_MSGQ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] + +/*! + * @brief Defines the TASK handle + * + * This macro is used to define a 4 byte aligned TASK handle. + * Then use "(osa_task_handle_t)name" to get the TASK handle. + * + * The macro should be global and could be optional. You could also define TASK handle by yourself. + * + * This is an example, + * @code + * OSA_TASK_HANDLE_DEFINE(taskHandle); + * @endcode + * + * @param name The name string of the TASK handle. + */ +#define OSA_TASK_HANDLE_DEFINE(name) uint32_t name[(OSA_TASK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t)] + +#include "fsl_os_abstraction_rtthread.h" + +extern const uint8_t gUseRtos_c; + +/* + * alloc the temporary memory to store the status + */ +#define OSA_SR_ALLOC() uint32_t osaCurrentSr; +/* + * Enter critical mode + */ +#define OSA_ENTER_CRITICAL() OSA_EnterCritical(&osaCurrentSr) +/* + * Exit critical mode and retore the previous mode + */ +#define OSA_EXIT_CRITICAL() OSA_ExitCritical(osaCurrentSr) + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Reserves the requested amount of memory in bytes. + * + * The function is used to reserve the requested amount of memory in bytes and initializes it to 0. + * + * @param length Amount of bytes to reserve. + * + * @return Pointer to the reserved memory. NULL if memory can't be allocated. + */ +void *OSA_MemoryAllocate(uint32_t length); + +/*! + * @brief Frees the memory previously reserved. + * + * The function is used to free the memory block previously reserved. + * + * @param p Pointer to the start of the memory block previously reserved. + * + */ +void OSA_MemoryFree(void *p); + +/*! + * @brief Enter critical with nesting mode. + * + * @param sr Store current status and return to caller. + */ +void OSA_EnterCritical(uint32_t *sr); + +/*! + * @brief Exit critical with nesting mode. + * + * @param sr Previous status to restore. + */ +void OSA_ExitCritical(uint32_t sr); + +/*! + * @name Task management + * @{ + */ + +/*! + * @brief Creates a task. + * + * This function is used to create task based on the resources defined + * by the macro OSA_TASK_DEFINE. + * + * Example below shows how to use this API to create the task handle. + * @code + * OSA_TASK_HANDLE_DEFINE(taskHandle); + * OSA_TASK_DEFINE( Job1, OSA_PRIORITY_HIGH, 1, 800, 0); + * OSA_TaskCreate((osa_task_handle_t)taskHandle, OSA_TASK(Job1), (osa_task_param_t)NULL); + * @endcode + * + * @param taskHandle Pointer to a memory space of size OSA_TASK_HANDLE_SIZE allocated by the caller, task handle. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #OSA_TASK_HANDLE_DEFINE(taskHandle); + * or + * uint32_t taskHandle[((OSA_TASK_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param thread_def pointer to theosa_task_def_t structure which defines the task. + * @param task_param Pointer to be passed to the task when it is created. + * @retval KOSA_StatusSuccess The task is successfully created. + * @retval KOSA_StatusError The task can not be created. + */ +#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, osa_task_def_t *thread_def, osa_task_param_t task_param); +#endif /* FSL_OSA_TASK_ENABLE */ + +/*! + * @brief Gets the handler of active task. + * + * @return Handler to current active task. + */ +#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_task_handle_t OSA_TaskGetCurrentHandle(void); +#endif /* FSL_OSA_TASK_ENABLE */ + +/*! + * @brief Puts the active task to the end of scheduler's queue. + * + * When a task calls this function, it gives up the CPU and puts itself to the + * end of a task ready list. + * + * @retval KOSA_StatusSuccess The function is called successfully. + * @retval KOSA_StatusError Error occurs with this function. + */ +#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskYield(void); +#endif /* FSL_OSA_TASK_ENABLE */ + +/*! + * @brief Gets the priority of a task. + * + * @param taskHandle The handler of the task whose priority is received. + * + * @return Task's priority. + */ +#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_task_priority_t OSA_TaskGetPriority(osa_task_handle_t taskHandle); +#endif /* FSL_OSA_TASK_ENABLE */ + +/*! + * @brief Sets the priority of a task. + * + * @param taskHandle The handler of the task whose priority is set. + * @param taskPriority The priority to set. + * + * @retval KOSA_StatusSuccess Task's priority is set successfully. + * @retval KOSA_StatusError Task's priority can not be set. + */ +#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority_t taskPriority); +#endif /* FSL_OSA_TASK_ENABLE */ + +/*! + * @brief Destroys a previously created task. + * + * @param taskHandle The handler of the task to destroy. + * + * @retval KOSA_StatusSuccess The task was successfully destroyed. + * @retval KOSA_StatusError Task destruction failed or invalid parameter. + */ +#if ((defined(FSL_OSA_TASK_ENABLE)) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskDestroy(osa_task_handle_t taskHandle); +#endif /* FSL_OSA_TASK_ENABLE */ + +/*! + * @brief Creates a semaphore with a given value. + * + * This function creates a semaphore and sets the value to the parameter + * initValue. + * + * Example below shows how to use this API to create the semaphore handle. + * @code + * OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle); + * OSA_SemaphoreCreate((osa_semaphore_handle_t)semaphoreHandle, 0xff); + * @endcode + * + * @param semaphoreHandle Pointer to a memory space of size OSA_SEM_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #OSA_SEMAPHORE_HANDLE_DEFINE(semaphoreHandle); + * or + * uint32_t semaphoreHandle[((OSA_SEM_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param initValue Initial value the semaphore will be set to. + * + * @retval KOSA_StatusSuccess the new semaphore if the semaphore is created successfully. + * @retval KOSA_StatusError if the semaphore can not be created. + */ +osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_t initValue); + +/*! + * @brief Destroys a previously created semaphore. + * + * @param semaphoreHandle The semaphore handle. + * The macro SEMAPHORE_HANDLE_BUFFER_GET is used to get the semaphore buffer pointer, + * and should not be used before the macro SEMAPHORE_HANDLE_BUFFER_DEFINE is used. + * + * @retval KOSA_StatusSuccess The semaphore is successfully destroyed. + * @retval KOSA_StatusError The semaphore can not be destroyed. + */ +osa_status_t OSA_SemaphoreDestroy(osa_semaphore_handle_t semaphoreHandle); + +/*! + * @brief Pending a semaphore with timeout. + * + * This function checks the semaphore's counting value. If it is positive, + * decreases it and returns KOSA_StatusSuccess. Otherwise, a timeout is used + * to wait. + * + * @param semaphoreHandle The semaphore handle. + * @param millisec The maximum number of milliseconds to wait if semaphore is not + * positive. Pass osaWaitForever_c to wait indefinitely, pass 0 + * will return KOSA_StatusTimeout immediately. + * + * @retval KOSA_StatusSuccess The semaphore is received. + * @retval KOSA_StatusTimeout The semaphore is not received within the specified 'timeout'. + * @retval KOSA_StatusError An incorrect parameter was passed. + */ +osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t millisec); + +/*! + * @brief Signals for someone waiting on the semaphore to wake up. + * + * Wakes up one task that is waiting on the semaphore. If no task is waiting, increases + * the semaphore's counting value. + * + * @param semaphoreHandle The semaphore handle to signal. + * + * @retval KOSA_StatusSuccess The semaphore is successfully signaled. + * @retval KOSA_StatusError The object can not be signaled or invalid parameter. + * + */ +osa_status_t OSA_SemaphorePost(osa_semaphore_handle_t semaphoreHandle); + +/*! + * @brief Create an unlocked mutex. + * + * This function creates a non-recursive mutex and sets it to unlocked status. + * + * Example below shows how to use this API to create the mutex handle. + * @code + * OSA_MUTEX_HANDLE_DEFINE(mutexHandle); + * OSA_MutexCreate((osa_mutex_handle_t)mutexHandle); + * @endcode + * + * @param mutexHandle Pointer to a memory space of size OSA_MUTEX_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #OSA_MUTEX_HANDLE_DEFINE(mutexHandle); + * or + * uint32_t mutexHandle[((OSA_MUTEX_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @retval KOSA_StatusSuccess the new mutex if the mutex is created successfully. + * @retval KOSA_StatusError if the mutex can not be created. + */ +osa_status_t OSA_MutexCreate(osa_mutex_handle_t mutexHandle); + +/*! + * @brief Waits for a mutex and locks it. + * + * This function checks the mutex's status. If it is unlocked, locks it and returns the + * KOSA_StatusSuccess. Otherwise, waits for a timeout in milliseconds to lock. + * + * @param mutexHandle The mutex handle. + * @param millisec The maximum number of milliseconds to wait for the mutex. + * If the mutex is locked, Pass the value osaWaitForever_c will + * wait indefinitely, pass 0 will return KOSA_StatusTimeout + * immediately. + * + * @retval KOSA_StatusSuccess The mutex is locked successfully. + * @retval KOSA_StatusTimeout Timeout occurred. + * @retval KOSA_StatusError Incorrect parameter was passed. + * + * @note This is non-recursive mutex, a task can not try to lock the mutex it has locked. + */ +osa_status_t OSA_MutexLock(osa_mutex_handle_t mutexHandle, uint32_t millisec); + +/*! + * @brief Unlocks a previously locked mutex. + * + * @param mutexHandle The mutex handle. + * + * @retval KOSA_StatusSuccess The mutex is successfully unlocked. + * @retval KOSA_StatusError The mutex can not be unlocked or invalid parameter. + */ +osa_status_t OSA_MutexUnlock(osa_mutex_handle_t mutexHandle); + +/*! + * @brief Destroys a previously created mutex. + * + * @param mutexHandle The mutex handle. + * + * @retval KOSA_StatusSuccess The mutex is successfully destroyed. + * @retval KOSA_StatusError The mutex can not be destroyed. + * + */ +osa_status_t OSA_MutexDestroy(osa_mutex_handle_t mutexHandle); + +/*! + * @brief Initializes an event object with all flags cleared. + * + * This function creates an event object and set its clear mode. If autoClear + * is 1, when a task gets the event flags, these flags will be + * cleared automatically. Otherwise these flags must + * be cleared manually. + * + * Example below shows how to use this API to create the event handle. + * @code + * OSA_EVENT_HANDLE_DEFINE(eventHandle); + * OSA_EventCreate((osa_event_handle_t)eventHandle, 0); + * @endcode + * + * @param eventHandle Pointer to a memory space of size OSA_EVENT_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #OSA_EVENT_HANDLE_DEFINE(eventHandle); + * or + * uint32_t eventHandle[((OSA_EVENT_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param autoClear 1 The event is auto-clear. + * 0 The event manual-clear + * @retval KOSA_StatusSuccess the new event if the event is created successfully. + * @retval KOSA_StatusError if the event can not be created. + */ +osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear); + +/*! + * @brief Sets one or more event flags. + * + * Sets specified flags of an event object. + * + * @param eventHandle The event handle. + * @param flagsToSet Flags to be set. + * + * @retval KOSA_StatusSuccess The flags were successfully set. + * @retval KOSA_StatusError An incorrect parameter was passed. + */ +osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flagsToSet); + +/*! + * @brief Clears one or more flags. + * + * Clears specified flags of an event object. + * + * @param eventHandle The event handle. + * @param flagsToClear Flags to be clear. + * + * @retval KOSA_StatusSuccess The flags were successfully cleared. + * @retval KOSA_StatusError An incorrect parameter was passed. + */ +osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t flagsToClear); + +/*! + * @brief Get event's flags. + * + * Get specified flags of an event object. + * + * @param eventHandle The event handle. + * The macro EVENT_HANDLE_BUFFER_GET is used to get the event buffer pointer, + * and should not be used before the macro EVENT_HANDLE_BUFFER_DEFINE is used. + * @param flagsMask The flags user want to get are specified by this parameter. + * @param pFlagsOfEvent The event flags are obtained by this parameter. + * + * @retval KOSA_StatusSuccess The event flags were successfully got. + * @retval KOSA_StatusError An incorrect parameter was passed. + */ +osa_status_t OSA_EventGet(osa_event_handle_t eventHandle, + osa_event_flags_t flagsMask, + osa_event_flags_t *pFlagsOfEvent); + +/*! + * @brief Waits for specified event flags to be set. + * + * This function waits for a combination of flags to be set in an event object. + * Applications can wait for any/all bits to be set. Also this function could + * obtain the flags who wakeup the waiting task. + * + * @param eventHandle The event handle. + * @param flagsToWait Flags that to wait. + * @param waitAll Wait all flags or any flag to be set. + * @param millisec The maximum number of milliseconds to wait for the event. + * If the wait condition is not met, pass osaWaitForever_c will + * wait indefinitely, pass 0 will return KOSA_StatusTimeout + * immediately. + * @param pSetFlags Flags that wakeup the waiting task are obtained by this parameter. + * + * @retval KOSA_StatusSuccess The wait condition met and function returns successfully. + * @retval KOSA_StatusTimeout Has not met wait condition within timeout. + * @retval KOSA_StatusError An incorrect parameter was passed. + * + * @note Please pay attention to the flags bit width, FreeRTOS uses the most + * significant 8 bis as control bits, so do not wait these bits while using + * FreeRTOS. + * + */ +osa_status_t OSA_EventWait(osa_event_handle_t eventHandle, + osa_event_flags_t flagsToWait, + uint8_t waitAll, + uint32_t millisec, + osa_event_flags_t *pSetFlags); + +/*! + * @brief Destroys a previously created event object. + * + * @param eventHandle The event handle. + * + * @retval KOSA_StatusSuccess The event is successfully destroyed. + * @retval KOSA_StatusError Event destruction failed. + */ +osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle); + +/*! + * @brief Initializes a message queue. + * + * This function allocates memory for and initializes a message queue. Message queue elements are hardcoded as void*. + * + * Example below shows how to use this API to create the massage queue handle. + * @code + * OSA_MSGQ_HANDLE_DEFINE(msgqHandle); + * OSA_MsgQCreate((osa_msgq_handle_t)msgqHandle, 5U, sizeof(msg)); + * @endcode + * + * @param msgqHandle Pointer to a memory space of size #(OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize) on bare-matel + * and #(OSA_MSGQ_HANDLE_SIZE) on FreeRTOS allocated by the caller, message queue handle. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #OSA_MSGQ_HANDLE_DEFINE(msgqHandle); + * or + * For bm: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + msgNo*msgSize + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * For freertos: uint32_t msgqHandle[((OSA_MSGQ_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param msgNo :number of messages the message queue should accommodate. + * @param msgSize :size of a single message structure. + * + * @retval KOSA_StatusSuccess Message queue successfully Create. + * @retval KOSA_StatusError Message queue create failure. + */ +osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32_t msgSize); + +/*! + * @brief Puts a message at the end of the queue. + * + * This function puts a message to the end of the message queue. If the queue + * is full, this function returns the KOSA_StatusError; + * + * @param msgqHandle Message Queue handler. + * @param pMessage Pointer to the message to be put into the queue. + * + * @retval KOSA_StatusSuccess Message successfully put into the queue. + * @retval KOSA_StatusError The queue was full or an invalid parameter was passed. + */ +osa_status_t OSA_MsgQPut(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage); + +/*! + * @brief Reads and remove a message at the head of the queue. + * + * This function gets a message from the head of the message queue. If the + * queue is empty, timeout is used to wait. + * + * @param msgqHandle Message Queue handler. + * @param pMessage Pointer to a memory to save the message. + * @param millisec The number of milliseconds to wait for a message. If the + * queue is empty, pass osaWaitForever_c will wait indefinitely, + * pass 0 will return KOSA_StatusTimeout immediately. + * + * @retval KOSA_StatusSuccess Message successfully obtained from the queue. + * @retval KOSA_StatusTimeout The queue remains empty after timeout. + * @retval KOSA_StatusError Invalid parameter. + */ +osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage, uint32_t millisec); + +/*! + * @brief Destroys a previously created queue. + * + * @param msgqHandle Message Queue handler. + * + * @retval KOSA_StatusSuccess The queue was successfully destroyed. + * @retval KOSA_StatusError Message queue destruction failed. + */ +osa_status_t OSA_MsgQDestroy(osa_msgq_handle_t msgqHandle); + +/*! + * @brief Enable all interrupts. + */ +void OSA_InterruptEnable(void); + +/*! + * @brief Disable all interrupts. + */ +void OSA_InterruptDisable(void); + +/*! + * @brief Enable all interrupts using PRIMASK. + */ +void OSA_EnableIRQGlobal(void); + +/*! + * @brief Disable all interrupts using PRIMASK. + */ +void OSA_DisableIRQGlobal(void); + +/*! + * @brief Delays execution for a number of milliseconds. + * + * @param millisec The time in milliseconds to wait. + */ +void OSA_TimeDelay(uint32_t millisec); + +/*! + * @brief This function gets current time in milliseconds. + * + * @retval current time in milliseconds + */ +uint32_t OSA_TimeGetMsec(void); + +/*! + * @brief Installs the interrupt handler. + * + * @param IRQNumber IRQ number of the interrupt. + * @param handler The interrupt handler to install. + */ +void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void)); + +/*! @}*/ +#ifdef __cplusplus +} +#endif +/*! @}*/ +#endif diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_os_abstraction_config.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_os_abstraction_config.h new file mode 100644 index 0000000000..234cf972bc --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_os_abstraction_config.h @@ -0,0 +1,36 @@ +/*! + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_OS_ABSTRACTION_CONFIG_H_ +#define _FSL_OS_ABSTRACTION_CONFIG_H_ + +#ifndef gMainThreadStackSize_c +#define gMainThreadStackSize_c 1024 +#endif + +#ifndef gMainThreadPriority_c +#define gMainThreadPriority_c 1 +#endif + +#ifndef gTaskMultipleInstancesManagement_c +#define gTaskMultipleInstancesManagement_c 0 +#endif + +/*! @brief Definition to determine whether enable OSA's TASK module. */ +#ifndef OSA_USED +#ifndef FSL_OSA_TASK_ENABLE +#define FSL_OSA_TASK_ENABLE 0U +#endif +#else +#if defined(FSL_OSA_TASK_ENABLE) +#undef FSL_OSA_TASK_ENABLE +#endif +#define FSL_OSA_TASK_ENABLE 1U +#endif /* OSA_USED */ + +#endif /* _FSL_OS_ABSTRACTION_CONFIG_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_os_abstraction_rtthread.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_os_abstraction_rtthread.c new file mode 100644 index 0000000000..524744c251 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_os_abstraction_rtthread.c @@ -0,0 +1,917 @@ +/*! ********************************************************************************* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2019 NXP + * All rights reserved. + * + * + * This is the source file for the OS Abstraction layer for freertos. + * + * SPDX-License-Identifier: BSD-3-Clause + ********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Include +************************************************************************************* +********************************************************************************** */ +#include "fsl_common.h" +#include "fsl_os_abstraction.h" +#include "fsl_os_abstraction_rtthread.h" +#include +#include "generic_list.h" + +/*! ********************************************************************************* +************************************************************************************* +* Private macros +************************************************************************************* +********************************************************************************** */ + +/* Weak function. */ +#if defined(__GNUC__) +#define __WEAK_FUNC __attribute__((weak)) +#elif defined(__ICCARM__) +#define __WEAK_FUNC __weak +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +#define __WEAK_FUNC __attribute__((weak)) +#endif + +#define millisecToTicks(millisec) (((millisec)*configTICK_RATE_HZ + 999U) / 1000U) + +#ifdef DEBUG_ASSERT +#define OS_ASSERT(condition) \ + if (!(condition)) \ + while (1) \ + ; +#else +#define OS_ASSERT(condition) (void)(condition); +#endif + +/*! @brief Converts milliseconds to ticks*/ +#define MSEC_TO_TICK(msec) \ + (((uint32_t)(msec) + 500uL / (uint32_t)configTICK_RATE_HZ) * (uint32_t)configTICK_RATE_HZ / 1000uL) +#define TICKS_TO_MSEC(tick) ((uint32_t)((uint64_t)(tick)*1000uL / (uint64_t)configTICK_RATE_HZ)) +/************************************************************************************ +************************************************************************************* +* Private type definitions +************************************************************************************* +************************************************************************************/ +typedef struct osa_freertos_task +{ + list_element_t link; + rt_thread_t taskHandle; +} osa_freertos_task_t; + +typedef struct _osa_event_struct +{ + rt_event_t handle; /* The event handle */ + uint8_t autoClear; /*!< Auto clear or manual clear */ +} osa_event_struct_t; + +/*! @brief State structure for bm osa manager. */ +typedef struct _osa_state +{ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) + list_label_t taskList; + OSA_TASK_HANDLE_DEFINE(mainTaskHandle); +#endif + uint32_t basePriority; + int32_t basePriorityNesting; + uint32_t interruptDisableCount; +} osa_state_t; + +/*! ********************************************************************************* +************************************************************************************* +* Private prototypes +************************************************************************************* +********************************************************************************** */ +__WEAK_FUNC void main_task(void const *argument); +__WEAK_FUNC void main_task(void const *argument) +{ +} + +void startup_task(void *argument); + +/*! ********************************************************************************* +************************************************************************************* +* Public memory declarations +************************************************************************************* +********************************************************************************** */ +const uint8_t gUseRtos_c = USE_RTOS; // USE_RTOS = 0 for BareMetal and 1 for OS + +static osa_state_t s_osaState = {0}; +/*! ********************************************************************************* +************************************************************************************* +* Private memory declarations +************************************************************************************* +********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Public functions +************************************************************************************* +********************************************************************************** */ +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MemoryAllocate + * Description : Reserves the requested amount of memory in bytes. + * + *END**************************************************************************/ +void *OSA_MemoryAllocate(uint32_t length) +{ + void *p = rt_malloc(length); + + if (RT_NULL != p) + { + rt_memset(p, 0, length); + } + + return p; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MemoryFree + * Description : Frees the memory previously reserved. + * + *END**************************************************************************/ +void OSA_MemoryFree(void *p) +{ + rt_free(p); +} + +void OSA_EnterCritical(uint32_t *sr) +{ + if (rt_thread_self() != RT_NULL) + rt_enter_critical(); +} + +void OSA_ExitCritical(uint32_t sr) +{ + if (rt_thread_self() != RT_NULL) + rt_exit_critical(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : startup_task + * Description : Wrapper over main_task.. + * + *END**************************************************************************/ +void startup_task(void *argument) +{ + main_task(argument); +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskGetCurrentHandle + * Description : This function is used to get current active task's handler. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_task_handle_t OSA_TaskGetCurrentHandle(void) +{ + list_element_handle_t list_element; + osa_freertos_task_t *ptask; + + list_element = LIST_GetHead(&s_osaState.taskList); + while (NULL != list_element) + { + ptask = (osa_freertos_task_t *)(void *)list_element; + if (ptask->taskHandle == xTaskGetCurrentTaskHandle()) + { + return (osa_task_handle_t)ptask; + } + list_element = LIST_GetNext(list_element); + } + return NULL; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskYield + * Description : When a task calls this function, it will give up CPU and put + * itself to the tail of ready list. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskYield(void) +{ + taskYIELD(); + return KOSA_StatusSuccess; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskGetPriority + * Description : This function returns task's priority by task handler. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_task_priority_t OSA_TaskGetPriority(osa_task_handle_t taskHandle) +{ + assert(taskHandle); + osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle; + return (osa_task_priority_t)(PRIORITY_RTOS_TO_OSA(uxTaskPriorityGet(ptask->taskHandle))); +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskSetPriority + * Description : This function sets task's priority by task handler. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority_t taskPriority) +{ + assert(taskHandle); + osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle; + vTaskPrioritySet((task_handler_t)ptask->taskHandle, PRIORITY_OSA_TO_RTOS(taskPriority)); + return KOSA_StatusSuccess; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskCreate + * Description : This function is used to create a task and make it ready. + * Param[in] : threadDef - Definition of the thread. + * task_param - Parameter to pass to the new thread. + * Return Thread handle of the new thread, or NULL if failed. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, osa_task_def_t *thread_def, osa_task_param_t task_param) +{ + assert(sizeof(osa_freertos_task_t) == OSA_TASK_HANDLE_SIZE); + assert(taskHandle); + TaskHandle_t pxCreatedTask; + osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle; + + if (xTaskCreate((TaskFunction_t)thread_def->pthread, /* pointer to the task */ + (char const *)thread_def->tname, /* task name for kernel awareness debugging */ + (configSTACK_DEPTH_TYPE)thread_def->stacksize / sizeof(portSTACK_TYPE), /* task stack size */ + (task_param_t)task_param, /* optional task startup argument */ + PRIORITY_OSA_TO_RTOS(thread_def->tpriority), /* initial priority */ + &pxCreatedTask /* optional task handle to create */ + ) == pdPASS) + { + ptask->taskHandle = pxCreatedTask; + OSA_InterruptDisable(); + (void)LIST_AddTail(&s_osaState.taskList, (list_element_handle_t) & (ptask->link)); + OSA_InterruptEnable(); + return KOSA_StatusSuccess; + } + return KOSA_StatusError; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TaskDestroy + * Description : This function destroy a task. + * Param[in] :taskHandle - Thread handle. + * Return KOSA_StatusSuccess if the task is destroied, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) +osa_status_t OSA_TaskDestroy(osa_task_handle_t taskHandle) +{ + assert(taskHandle); + osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle; + osa_status_t status; + uint16_t oldPriority; + /*Change priority to avoid context switches*/ + oldPriority = OSA_TaskGetPriority(OSA_TaskGetCurrentHandle()); + (void)OSA_TaskSetPriority(OSA_TaskGetCurrentHandle(), OSA_PRIORITY_REAL_TIME); +#if INCLUDE_vTaskDelete /* vTaskDelete() enabled */ + vTaskDelete((task_handler_t)ptask->taskHandle); + status = KOSA_StatusSuccess; +#else + status = KOSA_StatusError; /* vTaskDelete() not available */ +#endif + (void)OSA_TaskSetPriority(OSA_TaskGetCurrentHandle(), oldPriority); + OSA_InterruptDisable(); + (void)LIST_RemoveElement(taskHandle); + OSA_InterruptEnable(); + return status; +} +#endif + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TimeDelay + * Description : This function is used to suspend the active thread for the given number of milliseconds. + * + *END**************************************************************************/ +void OSA_TimeDelay(uint32_t millisec) +{ + rt_thread_mdelay(millisec); +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_TimeGetMsec + * Description : This function gets current time in milliseconds. + * + *END**************************************************************************/ +uint32_t OSA_TimeGetMsec(void) +{ + return rt_tick_get_millisecond(); +} +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphoreCreate + * Description : This function is used to create a semaphore. + * Return : Semaphore handle of the new semaphore, or NULL if failed. + * + *END**************************************************************************/ +osa_status_t OSA_SemaphoreCreate(osa_semaphore_handle_t semaphoreHandle, uint32_t initValue) +{ + assert(sizeof(osa_semaphore_handle_t) == OSA_SEM_HANDLE_SIZE); + assert(semaphoreHandle); + + union + { + rt_sem_t sem; + uint32_t semhandle; + } xSemaHandle; + + xSemaHandle.sem = rt_sem_create("osa_sem", initValue, RT_IPC_FLAG_PRIO); + if (NULL != xSemaHandle.sem) + { + *(uint32_t *)semaphoreHandle = xSemaHandle.semhandle; + return KOSA_StatusSuccess; + } + return KOSA_StatusError; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphoreDestroy + * Description : This function is used to destroy a semaphore. + * Return : KOSA_StatusSuccess if the semaphore is destroyed successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_SemaphoreDestroy(osa_semaphore_handle_t semaphoreHandle) +{ + assert(semaphoreHandle); + rt_sem_t sem = (rt_sem_t)(void *)(uint32_t *)(*(uint32_t *)semaphoreHandle); + + rt_sem_delete(sem); + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphoreWait + * Description : This function checks the semaphore's counting value, if it is + * positive, decreases it and returns KOSA_StatusSuccess, otherwise, timeout + * will be used for wait. The parameter timeout indicates how long should wait + * in milliseconds. Pass osaWaitForever_c to wait indefinitely, pass 0 will + * return KOSA_StatusTimeout immediately if semaphore is not positive. + * This function returns KOSA_StatusSuccess if the semaphore is received, returns + * KOSA_StatusTimeout if the semaphore is not received within the specified + * 'timeout', returns KOSA_StatusError if any errors occur during waiting. + * + *END**************************************************************************/ +osa_status_t OSA_SemaphoreWait(osa_semaphore_handle_t semaphoreHandle, uint32_t millisec) +{ + int32_t timeoutTicks; + assert(semaphoreHandle); + rt_sem_t sem = (rt_sem_t)(void *)(uint32_t *)(*(uint32_t *)semaphoreHandle); + + /* Convert timeout from millisecond to tick. */ + if (millisec == osaWaitForever_c) + { + timeoutTicks = RT_WAITING_FOREVER; + } + else + { + timeoutTicks = rt_tick_from_millisecond(millisec); + } + + if (RT_EOK != rt_sem_take(sem, timeoutTicks)) + { + return KOSA_StatusTimeout; /* timeout */ + } + else + { + return KOSA_StatusSuccess; /* semaphore taken */ + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_SemaphorePost + * Description : This function is used to wake up one task that wating on the + * semaphore. If no task is waiting, increase the semaphore. The function returns + * KOSA_StatusSuccess if the semaphre is post successfully, otherwise returns + * KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_SemaphorePost(osa_semaphore_handle_t semaphoreHandle) +{ + assert(semaphoreHandle); + rt_sem_t sem = (rt_sem_t)(void *)(uint32_t *)(*(uint32_t *)semaphoreHandle); + rt_sem_release(sem); + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexCreate + * Description : This function is used to create a mutex. + * Return : Mutex handle of the new mutex, or NULL if failed. + * + *END**************************************************************************/ +osa_status_t OSA_MutexCreate(osa_mutex_handle_t mutexHandle) +{ + assert(sizeof(osa_mutex_handle_t) == OSA_MUTEX_HANDLE_SIZE); + assert(mutexHandle); + + union + { + rt_mutex_t mutex; + uint32_t pmutexHandle; + } xMutexHandle; + + xMutexHandle.mutex = rt_mutex_create("osa_mutex", RT_IPC_FLAG_PRIO); + if (RT_NULL != xMutexHandle.mutex) + { + *(uint32_t *)mutexHandle = xMutexHandle.pmutexHandle; + return KOSA_StatusSuccess; + } + return KOSA_StatusError; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexLock + * Description : This function checks the mutex's status, if it is unlocked, + * lock it and returns KOSA_StatusSuccess, otherwise, wait for the mutex. + * This function returns KOSA_StatusSuccess if the mutex is obtained, returns + * KOSA_StatusError if any errors occur during waiting. If the mutex has been + * locked, pass 0 as timeout will return KOSA_StatusTimeout immediately. + * + *END**************************************************************************/ +osa_status_t OSA_MutexLock(osa_mutex_handle_t mutexHandle, uint32_t millisec) +{ + assert(mutexHandle); + int32_t timeoutTicks; + rt_mutex_t mutex = (rt_mutex_t)(void *)(uint32_t *)(*(uint32_t *)mutexHandle); + + /* Convert timeout from millisecond to tick. */ + if (millisec == osaWaitForever_c) + { + timeoutTicks = RT_WAITING_FOREVER; + } + else + { + timeoutTicks = rt_tick_from_millisecond(millisec); + } + + if (RT_EOK != rt_mutex_take(mutex, timeoutTicks)) + { + return KOSA_StatusTimeout; /* timeout */ + } + else + { + return KOSA_StatusSuccess; /* semaphore taken */ + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexUnlock + * Description : This function is used to unlock a mutex. + * + *END**************************************************************************/ +osa_status_t OSA_MutexUnlock(osa_mutex_handle_t mutexHandle) +{ + assert(mutexHandle); + rt_mutex_t mutex = (rt_mutex_t)(void *)(uint32_t *)(*(uint32_t *)mutexHandle); + rt_mutex_release(mutex); + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MutexDestroy + * Description : This function is used to destroy a mutex. + * Return : KOSA_StatusSuccess if the lock object is destroyed successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_MutexDestroy(osa_mutex_handle_t mutexHandle) +{ + assert(mutexHandle); + rt_mutex_t mutex = (rt_mutex_t)(void *)(uint32_t *)(*(uint32_t *)mutexHandle); + + rt_mutex_delete(mutex); + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventCreate + * Description : This function is used to create a event object. + * Return : Event handle of the new event, or NULL if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventCreate(osa_event_handle_t eventHandle, uint8_t autoClear) +{ + assert(eventHandle); + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + + pEventStruct->handle = rt_event_create("osa_event", RT_IPC_FLAG_PRIO); + if (RT_NULL != pEventStruct->handle) + { + pEventStruct->autoClear = autoClear; + } + else + { + return KOSA_StatusError; + } + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventSet + * Description : Set one or more event flags of an event object. + * Return : KOSA_StatusSuccess if set successfully, KOSA_StatusError if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventSet(osa_event_handle_t eventHandle, osa_event_flags_t flagsToSet) +{ + rt_err_t result; + assert(eventHandle); + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + + if (RT_NULL == pEventStruct->handle) + { + return KOSA_StatusError; + } + + rt_event_send(pEventStruct->handle, (rt_uint32_t)flagsToSet); + + (void)result; + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventClear + * Description : Clear one or more event flags of an event object. + * Return :KOSA_StatusSuccess if clear successfully, KOSA_StatusError if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventClear(osa_event_handle_t eventHandle, osa_event_flags_t flagsToClear) +{ + assert(eventHandle); + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + + if (RT_NULL == pEventStruct->handle) + { + return KOSA_StatusError; + } + + rt_uint32_t recved; + rt_event_recv(pEventStruct->handle, (rt_uint32_t)flagsToClear, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, 0, &recved); + + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventGet + * Description : This function is used to get event's flags that specified by prameter + * flagsMask, and the flags (user specified) are obatianed by parameter pFlagsOfEvent. So + * you should pass the parameter 0xffffffff to specify you want to check all. + * Return :KOSA_StatusSuccess if event flags were successfully got, KOSA_StatusError if failed. + * + *END**************************************************************************/ +osa_status_t OSA_EventGet(osa_event_handle_t eventHandle, osa_event_flags_t flagsMask, osa_event_flags_t *pFlagsOfEvent) +{ + assert(eventHandle); + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + rt_uint32_t eventFlags; + + if (RT_NULL == pEventStruct->handle) + { + return KOSA_StatusError; + } + + if (RT_NULL == pFlagsOfEvent) + { + return KOSA_StatusError; + } + + if (RT_EOK != rt_event_recv(pEventStruct->handle, (rt_uint32_t)flagsMask, RT_EVENT_FLAG_OR, 0, &eventFlags)) + { + eventFlags = 0; + } + + *pFlagsOfEvent = (osa_event_flags_t)eventFlags & flagsMask; + + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventWait + * Description : This function checks the event's status, if it meets the wait + * condition, return KOSA_StatusSuccess, otherwise, timeout will be used for + * wait. The parameter timeout indicates how long should wait in milliseconds. + * Pass osaWaitForever_c to wait indefinitely, pass 0 will return the value + * KOSA_StatusTimeout immediately if wait condition is not met. The event flags + * will be cleared if the event is auto clear mode. Flags that wakeup waiting + * task could be obtained from the parameter setFlags. + * This function returns KOSA_StatusSuccess if wait condition is met, returns + * KOSA_StatusTimeout if wait condition is not met within the specified + * 'timeout', returns KOSA_StatusError if any errors occur during waiting. + * + *END**************************************************************************/ +osa_status_t OSA_EventWait(osa_event_handle_t eventHandle, + osa_event_flags_t flagsToWait, + uint8_t waitAll, + uint32_t millisec, + osa_event_flags_t *pSetFlags) +{ + assert(eventHandle); + rt_uint8_t option = 0; + rt_int32_t timeoutTicks; + rt_uint32_t flagsSave; + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + + /* Clean FreeRTOS cotrol flags */ + flagsToWait = flagsToWait & 0x00FFFFFFU; + if (RT_NULL == pEventStruct->handle) + { + return KOSA_StatusError; + } + + /* Convert timeout from millisecond to tick. */ + if (millisec == osaWaitForever_c) + { + timeoutTicks = RT_WAITING_FOREVER; + } + else + { + timeoutTicks = rt_tick_from_millisecond(millisec); + } + + if (pEventStruct->autoClear != 0U) + { + option |= RT_EVENT_FLAG_CLEAR; + } + option |= waitAll ? RT_EVENT_FLAG_AND : RT_EVENT_FLAG_OR; + + rt_err_t status = rt_event_recv(pEventStruct->handle, (rt_uint32_t)flagsToWait, option, timeoutTicks, &flagsSave); + + flagsSave &= (rt_uint32_t)flagsToWait; + if (RT_NULL != pSetFlags) + { + *pSetFlags = (osa_event_flags_t)flagsSave; + } + + if (RT_EOK != status) + { + return KOSA_StatusTimeout; + } + else + { + return KOSA_StatusSuccess; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EventDestroy + * Description : This function is used to destroy a event object. Return + * KOSA_StatusSuccess if the event object is destroyed successfully, otherwise + * return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_EventDestroy(osa_event_handle_t eventHandle) +{ + assert(eventHandle); + osa_event_struct_t *pEventStruct = (osa_event_struct_t *)eventHandle; + + if (RT_NULL == pEventStruct->handle) + { + return KOSA_StatusError; + } + rt_event_delete(pEventStruct->handle); + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQCreate + * Description : This function is used to create a message queue. + * Return : the handle to the message queue if create successfully, otherwise + * return NULL. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQCreate(osa_msgq_handle_t msgqHandle, uint32_t msgNo, uint32_t msgSize) +{ + assert(sizeof(osa_msgq_handle_t) == OSA_MSGQ_HANDLE_SIZE); + assert(msgqHandle); + + union + { + rt_mq_t msgq; + uint32_t pmsgqHandle; + } xMsgqHandle; + + /* Create the message queue where the number and size is specified by msgNo and msgSize */ + xMsgqHandle.msgq = rt_mq_create("osa_mq", msgSize, msgNo, RT_IPC_FLAG_PRIO); + if (RT_NULL != xMsgqHandle.msgq) + { + *(uint32_t *)msgqHandle = xMsgqHandle.pmsgqHandle; + return KOSA_StatusSuccess; + } + return KOSA_StatusError; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQPut + * Description : This function is used to put a message to a message queue. + * Return : KOSA_StatusSuccess if the message is put successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQPut(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage) +{ + assert(msgqHandle); + rt_mq_t handler = (rt_mq_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle); + + if (RT_EOK == rt_mq_send(handler, pMessage, handler->msg_size)) + { + return KOSA_StatusSuccess; + } + else + { + return KOSA_StatusError; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQGet + * Description : This function checks the queue's status, if it is not empty, + * get message from it and return KOSA_StatusSuccess, otherwise, timeout will + * be used for wait. The parameter timeout indicates how long should wait in + * milliseconds. Pass osaWaitForever_c to wait indefinitely, pass 0 will return + * KOSA_StatusTimeout immediately if queue is empty. + * This function returns KOSA_StatusSuccess if message is got successfully, + * returns KOSA_StatusTimeout if message queue is empty within the specified + * 'timeout', returns KOSA_StatusError if any errors occur during waiting. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage, uint32_t millisec) +{ + osa_status_t osaStatus; + assert(msgqHandle); + rt_mq_t handler = (rt_mq_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle); + + int32_t timeoutTicks; + + if (millisec == osaWaitForever_c) + { + timeoutTicks = RT_WAITING_FOREVER; + } + else + { + timeoutTicks = rt_tick_from_millisecond(millisec); + } + if (RT_EOK != rt_mq_recv(handler, pMessage, handler->msg_size, timeoutTicks)) + { + osaStatus = KOSA_StatusTimeout; /* not able to send it to the queue? */ + } + else + { + osaStatus = KOSA_StatusSuccess; + } + return osaStatus; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_MsgQDestroy + * Description : This function is used to destroy the message queue. + * Return : KOSA_StatusSuccess if the message queue is destroyed successfully, otherwise return KOSA_StatusError. + * + *END**************************************************************************/ +osa_status_t OSA_MsgQDestroy(osa_msgq_handle_t msgqHandle) +{ + assert(msgqHandle); + rt_mq_t handler = (rt_mq_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle); + + rt_mq_delete(handler); + return KOSA_StatusSuccess; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InterruptEnable + * Description : self explanatory. + * + *END**************************************************************************/ +void OSA_InterruptEnable(void) +{ + rt_exit_critical(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InterruptDisable + * Description : self explanatory. + * + *END**************************************************************************/ +void OSA_InterruptDisable(void) +{ + rt_enter_critical(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_EnableIRQGlobal + * Description : enable interrupts using PRIMASK register. + * + *END**************************************************************************/ +void OSA_EnableIRQGlobal(void) +{ + if (s_osaState.interruptDisableCount > 0U) + { + s_osaState.interruptDisableCount--; + + if (0U == s_osaState.interruptDisableCount) + { + __enable_irq(); + } + /* call core API to enable the global interrupt*/ + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_DisableIRQGlobal + * Description : disable interrupts using PRIMASK register. + * + *END**************************************************************************/ +void OSA_DisableIRQGlobal(void) +{ + /* call core API to disable the global interrupt*/ + __disable_irq(); + + /* update counter*/ + s_osaState.interruptDisableCount++; +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InstallIntHandler + * Description : This function is used to install interrupt handler. + * + *END**************************************************************************/ +void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void)) +{ +#if defined(__IAR_SYSTEMS_ICC__) + _Pragma("diag_suppress = Pm138") +#endif +#if defined(ENABLE_RAM_VECTOR_TABLE) + (void) InstallIRQHandler((IRQn_Type)IRQNumber, (uint32_t) * (uint32_t *)&handler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#if defined(__IAR_SYSTEMS_ICC__) + _Pragma("diag_remark = PM138") +#endif +} + +/*!********************************************************************************* +************************************************************************************* +* Private functions +************************************************************************************* +********************************************************************************** */ +#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U)) + +static OSA_TASK_DEFINE(startup_task, gMainThreadPriority_c, 1, gMainThreadStackSize_c, 0); + +int main(void) +{ + extern void BOARD_InitHardware(void); + /* Initialize MCU clock */ + BOARD_InitHardware(); + LIST_Init((&s_osaState.taskList), 0); + + s_osaState.basePriorityNesting = 0; + s_osaState.interruptDisableCount = 0; + (void)OSA_TaskCreate((osa_task_handle_t)s_osaState.mainTaskHandle, OSA_TASK(startup_task), NULL); + + vTaskStartScheduler(); + return 0; +} +#endif /* FSL_OSA_TASK_ENABLE */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_os_abstraction_rtthread.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_os_abstraction_rtthread.h new file mode 100644 index 0000000000..40bd24271a --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_os_abstraction_rtthread.h @@ -0,0 +1,130 @@ +/*! ********************************************************************************* + * Copyright (c) 2013-2014, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * ile + * + * SPDX-License-Identifier: BSD-3-Clause + ********************************************************************************** */ +#if !defined(__FSL_OS_ABSTRACTION_RTTHREAD_H__) +#define __FSL_OS_ABSTRACTION_RTTHREAD_H__ + +#if defined(__IAR_SYSTEMS_ICC__) +/** + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + */ +// http://supp.iar.com/Support/?note=24725 + +#define MISRAC_DISABLE \ + _Pragma( \ + "diag_suppress= \ + Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\ + Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\ + Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\ + Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\ + Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\ + Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\ + Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\ + Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\ + Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\ + Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\ + Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\ + Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\ + Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\ + Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\ + Pm155") + +#define MISRAC_ENABLE \ + _Pragma( \ + "diag_default= \ + Pm001,Pm002,Pm003,Pm004,Pm005,Pm006,Pm007,Pm008,Pm009,Pm010,Pm011,\ + Pm012,Pm013,Pm014,Pm015,Pm016,Pm017,Pm018,Pm019,Pm020,Pm021,Pm022,\ + Pm023,Pm024,Pm025,Pm026,Pm027,Pm028,Pm029,Pm030,Pm031,Pm032,Pm033,\ + Pm034,Pm035,Pm036,Pm037,Pm038,Pm039,Pm040,Pm041,Pm042,Pm043,Pm044,\ + Pm045,Pm046,Pm047,Pm048,Pm049,Pm050,Pm051,Pm052,Pm053,Pm054,Pm055,\ + Pm056,Pm057,Pm058,Pm059,Pm060,Pm061,Pm062,Pm063,Pm064,Pm065,Pm066,\ + Pm067,Pm068,Pm069,Pm070,Pm071,Pm072,Pm073,Pm074,Pm075,Pm076,Pm077,\ + Pm078,Pm079,Pm080,Pm081,Pm082,Pm083,Pm084,Pm085,Pm086,Pm087,Pm088,\ + Pm089,Pm090,Pm091,Pm092,Pm093,Pm094,Pm095,Pm096,Pm097,Pm098,Pm099,\ + Pm100,Pm101,Pm102,Pm103,Pm104,Pm105,Pm106,Pm107,Pm108,Pm109,Pm110,\ + Pm111,Pm112,Pm113,Pm114,Pm115,Pm116,Pm117,Pm118,Pm119,Pm120,Pm121,\ + Pm122,Pm123,Pm124,Pm125,Pm126,Pm127,Pm128,Pm129,Pm130,Pm131,Pm132,\ + Pm133,Pm134,Pm135,Pm136,Pm137,Pm138,Pm139,Pm140,Pm141,Pm142,Pm143,\ + Pm144,Pm145,Pm146,Pm147,Pm148,Pm149,Pm150,Pm151,Pm152,Pm153,Pm154,\ + Pm155") +#else +/* Empty MISRA C macros for other toolchains. */ +#define MISRAC_DISABLE +#define MISRAC_ENABLE +#endif + +MISRAC_DISABLE +#include +MISRAC_ENABLE + +/*! + * @addtogroup os_abstraction_free_rtos + * @{ + */ + +/******************************************************************************* + * Declarations + ******************************************************************************/ +/*! @brief Type for a task handler, returned by the OSA_TaskCreate function. */ +typedef rt_thread_t task_handler_t; + +/*! @brief Type for a task stack.*/ +typedef rt_uint32_t task_stack_t; + +/*! @brief Type for task parameter */ +typedef void *task_param_t; + +/*! @brief Type for an event flags object.*/ +typedef rt_uint32_t event_flags_t; + +/*! @brief Constant to pass as timeout value in order to wait indefinitely. */ +#define OSA_WAIT_FOREVER 0xFFFFFFFFU + +/*! @brief OSA's time range in millisecond, OSA time wraps if exceeds this value. */ +#define FSL_OSA_TIME_RANGE 0xFFFFFFFFU + +/*! @brief The default interrupt handler installed in vector table. */ +#define OSA_DEFAULT_INT_HANDLER ((osa_int_handler_t)(&DefaultISR)) + +extern void DefaultISR(void); + +/*! + * @name Thread management + * @{ + */ + +/*! + * @brief To provide unified task piority for upper layer, OSA layer makes conversion. + */ +#define PRIORITY_OSA_TO_RTOS(osa_prio) ((UBaseType_t)configMAX_PRIORITIES - (osa_prio)-2U) +#define PRIORITY_RTOS_TO_OSA(rtos_prio) ((UBaseType_t)configMAX_PRIORITIES - (rtos_prio)-2U) + +/* @}*/ + +/*! + * @name Message queues + * @{ + */ + +/*! + * @brief This macro statically reserves the memory required for the queue. + * + * @param name Identifier for the memory region. + * @param number Number of elements in the queue. + * @param size Size of every elements in words. + */ +#define MSG_QUEUE_DECLARE(name, number, size) msg_queue_t *name = NULL + +/* @}*/ + +/*! @}*/ +/*! @}*/ +/*! @}*/ + +#endif // __FSL_OS_ABSTRACTION_RTTHREAD_H__ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_pit.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_pit.c new file mode 100644 index 0000000000..2d15e76865 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_pit.c @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_pit.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pit" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address to be used to gate or ungate the module clock + * + * @param base PIT peripheral base address + * + * @return The PIT instance + */ +static uint32_t PIT_GetInstance(PIT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to PIT bases for each instance. */ +static PIT_Type *const s_pitBases[] = PIT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to PIT clocks for each instance. */ +static const clock_ip_name_t s_pitClocks[] = PIT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t PIT_GetInstance(PIT_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_pitBases); instance++) + { + if (s_pitBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_pitBases)); + + return instance; +} + +/*! + * brief Ungates the PIT clock, enables the PIT module, and configures the peripheral for basic operations. + * + * note This API should be called at the beginning of the application using the PIT driver. + * + * param base PIT peripheral base address + * param config Pointer to the user's PIT config structure + */ +void PIT_Init(PIT_Type *base, const pit_config_t *config) +{ + assert(NULL != config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the PIT clock*/ + CLOCK_EnableClock(s_pitClocks[PIT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_PIT_HAS_MDIS) && FSL_FEATURE_PIT_HAS_MDIS + /* Enable PIT timers */ + base->MCR &= ~PIT_MCR_MDIS_MASK; +#endif + +#if defined(FSL_FEATURE_PIT_TIMER_COUNT) && (FSL_FEATURE_PIT_TIMER_COUNT) + /* Clear the timer enable bit for all channels to make sure the channel's timer is disabled. */ + for (uint8_t i = 0U; i < (uint32_t)FSL_FEATURE_PIT_TIMER_COUNT; i++) + { + base->CHANNEL[i].TCTRL &= ~PIT_TCTRL_TEN_MASK; + } +#endif /* FSL_FEATURE_PIT_TIMER_COUNT */ + + /* Config timer operation when in debug mode */ + if (true == config->enableRunInDebug) + { + base->MCR &= ~PIT_MCR_FRZ_MASK; + } + else + { + base->MCR |= PIT_MCR_FRZ_MASK; + } +} + +/*! + * brief Gates the PIT clock and disables the PIT module. + * + * param base PIT peripheral base address + */ +void PIT_Deinit(PIT_Type *base) +{ +#if defined(FSL_FEATURE_PIT_HAS_MDIS) && FSL_FEATURE_PIT_HAS_MDIS + /* Disable PIT timers */ + base->MCR |= PIT_MCR_MDIS_MASK; +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the PIT clock*/ + CLOCK_DisableClock(s_pitClocks[PIT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER + +/*! + * brief Reads the current lifetime counter value. + * + * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together. + * Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer. + * The period of lifetime timer is equal to the "period of timer 0 * period of timer 1". + * For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit + * has the value of timer 0. + * + * param base PIT peripheral base address + * + * return Current lifetime timer value + */ +uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base) +{ + uint32_t valueH = 0U; + uint32_t valueL = 0U; + + /* LTMR64H should be read before LTMR64L */ + valueH = base->LTMR64H; + valueL = base->LTMR64L; + + return (((uint64_t)valueH << 32U) + (uint64_t)(valueL)); +} + +#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_pit.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_pit.h new file mode 100644 index 0000000000..1de4984358 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_pit.h @@ -0,0 +1,332 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_PIT_H_ +#define _FSL_PIT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pit + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief PIT Driver Version 2.0.2 */ +#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! + * @brief List of PIT channels + * @note Actual number of available channels is SoC dependent + */ +typedef enum _pit_chnl +{ + kPIT_Chnl_0 = 0U, /*!< PIT channel number 0*/ + kPIT_Chnl_1, /*!< PIT channel number 1 */ + kPIT_Chnl_2, /*!< PIT channel number 2 */ + kPIT_Chnl_3, /*!< PIT channel number 3 */ +} pit_chnl_t; + +/*! @brief List of PIT interrupts */ +typedef enum _pit_interrupt_enable +{ + kPIT_TimerInterruptEnable = PIT_TCTRL_TIE_MASK, /*!< Timer interrupt enable*/ +} pit_interrupt_enable_t; + +/*! @brief List of PIT status flags */ +typedef enum _pit_status_flags +{ + kPIT_TimerFlag = PIT_TFLG_TIF_MASK, /*!< Timer flag */ +} pit_status_flags_t; + +/*! + * @brief PIT configuration structure + * + * This structure holds the configuration settings for the PIT peripheral. To initialize this + * structure to reasonable defaults, call the PIT_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _pit_config +{ + bool enableRunInDebug; /*!< true: Timers run in debug mode; false: Timers stop in debug mode */ +} pit_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the PIT clock, enables the PIT module, and configures the peripheral for basic operations. + * + * @note This API should be called at the beginning of the application using the PIT driver. + * + * @param base PIT peripheral base address + * @param config Pointer to the user's PIT config structure + */ +void PIT_Init(PIT_Type *base, const pit_config_t *config); + +/*! + * @brief Gates the PIT clock and disables the PIT module. + * + * @param base PIT peripheral base address + */ +void PIT_Deinit(PIT_Type *base); + +/*! + * @brief Fills in the PIT configuration structure with the default settings. + * + * The default values are as follows. + * @code + * config->enableRunInDebug = false; + * @endcode + * @param config Pointer to the configuration structure. + */ +static inline void PIT_GetDefaultConfig(pit_config_t *config) +{ + assert(NULL != config); + + /* Timers are stopped in Debug mode */ + config->enableRunInDebug = false; +} + +#if defined(FSL_FEATURE_PIT_HAS_CHAIN_MODE) && FSL_FEATURE_PIT_HAS_CHAIN_MODE + +/*! + * @brief Enables or disables chaining a timer with the previous timer. + * + * When a timer has a chain mode enabled, it only counts after the previous + * timer has expired. If the timer n-1 has counted down to 0, counter n + * decrements the value by one. Each timer is 32-bits, which allows the developers + * to chain timers together and form a longer timer (64-bits and larger). The first timer + * (timer 0) can't be chained to any other timer. + * + * @param base PIT peripheral base address + * @param channel Timer channel number which is chained with the previous timer + * @param enable Enable or disable chain. + * true: Current timer is chained with the previous timer. + * false: Timer doesn't chain with other timers. + */ +static inline void PIT_SetTimerChainMode(PIT_Type *base, pit_chnl_t channel, bool enable) +{ + if (enable) + { + base->CHANNEL[channel].TCTRL |= PIT_TCTRL_CHN_MASK; + } + else + { + base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_CHN_MASK; + } +} + +#endif /* FSL_FEATURE_PIT_HAS_CHAIN_MODE */ + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected PIT interrupts. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pit_interrupt_enable_t + */ +static inline void PIT_EnableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask) +{ + base->CHANNEL[channel].TCTRL |= mask; +} + +/*! + * @brief Disables the selected PIT interrupts. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::pit_interrupt_enable_t + */ +static inline void PIT_DisableInterrupts(PIT_Type *base, pit_chnl_t channel, uint32_t mask) +{ + base->CHANNEL[channel].TCTRL &= ~mask; +} + +/*! + * @brief Gets the enabled PIT interrupts. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::pit_interrupt_enable_t + */ +static inline uint32_t PIT_GetEnabledInterrupts(PIT_Type *base, pit_chnl_t channel) +{ + return (base->CHANNEL[channel].TCTRL & PIT_TCTRL_TIE_MASK); +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the PIT status flags. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::pit_status_flags_t + */ +static inline uint32_t PIT_GetStatusFlags(PIT_Type *base, pit_chnl_t channel) +{ + return (base->CHANNEL[channel].TFLG & PIT_TFLG_TIF_MASK); +} + +/*! + * @brief Clears the PIT status flags. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::pit_status_flags_t + */ +static inline void PIT_ClearStatusFlags(PIT_Type *base, pit_chnl_t channel, uint32_t mask) +{ + base->CHANNEL[channel].TFLG = mask; +} + +/*! @}*/ + +/*! + * @name Read and Write the timer period + * @{ + */ + +/*! + * @brief Sets the timer period in units of count. + * + * Timers begin counting from the value set by this function until it reaches 0, + * then it generates an interrupt and load this register value again. + * Writing a new value to this register does not restart the timer. Instead, the value + * is loaded after the timer expires. + * + * @note Users can call the utility macros provided in fsl_common.h to convert to ticks. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * @param count Timer period in units of ticks + */ +static inline void PIT_SetTimerPeriod(PIT_Type *base, pit_chnl_t channel, uint32_t count) +{ + base->CHANNEL[channel].LDVAL = count; +} + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec. + * + * @param base PIT peripheral base address + * @param channel Timer channel number + * + * @return Current timer counting value in ticks + */ +static inline uint32_t PIT_GetCurrentTimerCount(PIT_Type *base, pit_chnl_t channel) +{ + return base->CHANNEL[channel].CVAL; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the timer counting. + * + * After calling this function, timers load period value, count down to 0 and + * then load the respective start value again. Each time a timer reaches 0, + * it generates a trigger pulse and sets the timeout interrupt flag. + * + * @param base PIT peripheral base address + * @param channel Timer channel number. + */ +static inline void PIT_StartTimer(PIT_Type *base, pit_chnl_t channel) +{ + base->CHANNEL[channel].TCTRL |= PIT_TCTRL_TEN_MASK; +} + +/*! + * @brief Stops the timer counting. + * + * This function stops every timer counting. Timers reload their periods + * respectively after the next time they call the PIT_DRV_StartTimer. + * + * @param base PIT peripheral base address + * @param channel Timer channel number. + */ +static inline void PIT_StopTimer(PIT_Type *base, pit_chnl_t channel) +{ + base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_TEN_MASK; +} + +/*! @}*/ + +#if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER + +/*! + * @brief Reads the current lifetime counter value. + * + * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together. + * Timer 0 and 1 are chained by calling the PIT_SetTimerChainMode before using this timer. + * The period of lifetime timer is equal to the "period of timer 0 * period of timer 1". + * For the 64-bit value, the higher 32-bit has the value of timer 1, and the lower 32-bit + * has the value of timer 0. + * + * @param base PIT peripheral base address + * + * @return Current lifetime timer value + */ +uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base); + +#endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PIT_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_pmu.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_pmu.c new file mode 100644 index 0000000000..f3e0571f0d --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_pmu.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_pmu.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pmu" +#endif + +/*! + * name Status. + * { + */ + +uint32_t PMU_GetStatusFlags(PMU_Type *base) +{ + uint32_t ret = 0U; + + /* For 1P1. */ + if (PMU_REG_1P1_OK_VDD1P1_MASK == (PMU_REG_1P1_OK_VDD1P1_MASK & base->REG_1P1)) + { + ret |= kPMU_1P1RegulatorOutputOK; + } + if (PMU_REG_1P1_BO_VDD1P1_MASK == (PMU_REG_1P1_BO_VDD1P1_MASK & base->REG_1P1)) + { + ret |= kPMU_1P1BrownoutOnOutput; + } + + /* For 3P0. */ + if (PMU_REG_3P0_OK_VDD3P0_MASK == (PMU_REG_3P0_OK_VDD3P0_MASK & base->REG_3P0)) + { + ret |= kPMU_3P0RegulatorOutputOK; + } + if (PMU_REG_3P0_BO_VDD3P0_MASK == (PMU_REG_3P0_BO_VDD3P0_MASK & base->REG_3P0)) + { + ret |= kPMU_3P0BrownoutOnOutput; + } + + /* For 2P5. */ + if (PMU_REG_2P5_OK_VDD2P5_MASK == (PMU_REG_2P5_OK_VDD2P5_MASK & base->REG_2P5)) + { + ret |= kPMU_2P5RegulatorOutputOK; + } + if (PMU_REG_2P5_BO_VDD2P5_MASK == (PMU_REG_2P5_BO_VDD2P5_MASK & base->REG_2P5)) + { + ret |= kPMU_2P5BrownoutOnOutput; + } + + return ret; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_pmu.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_pmu.h new file mode 100644 index 0000000000..6d9639d22e --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_pmu.h @@ -0,0 +1,671 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_PMU_H_ +#define _FSL_PMU_H_ + +#include "fsl_common.h" + +/*! @addtogroup pmu */ +/*! @{ */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief PMU driver version */ +#define FSL_PMU_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + /*@}*/ + +/*! + * @brief Status flags. + */ +enum _pmu_status_flags +{ + kPMU_1P1RegulatorOutputOK = (1U << 0U), /*!< Status bit that signals when the 1p1 regulator output + is ok. 1 = regulator output > brownout target. */ + kPMU_1P1BrownoutOnOutput = (1U << 1U), /*!< Status bit that signals when a 1p1 brownout is detected + on the regulator output. */ + kPMU_3P0RegulatorOutputOK = (1U << 2U), /*!< Status bit that signals when the 3p0 regulator output + is ok. 1 = regulator output > brownout target. */ + kPMU_3P0BrownoutOnOutput = (1U << 3U), /*!< Status bit that signals when a 3p0 brownout is detected + on the regulator output. */ + kPMU_2P5RegulatorOutputOK = (1U << 4U), /*!< Status bit that signals when the 2p5 regulator output + is ok. 1 = regulator output > brownout target. */ + kPMU_2P5BrownoutOnOutput = (1U << 5U), /*!< Status bit that signals when a 2p5 brownout is detected + on the regulator output. */ +}; + +/*! + * @brief The source for the reference voltage of the weak 1P1 regulator. + */ +typedef enum _pmu_1p1_weak_reference_source +{ + kPMU_1P1WeakReferenceSourceAlt0 = 0U, /*!< Weak-linreg output tracks low-power-bandgap voltage. */ + kPMU_1P1WeakReferenceSourceAlt1 = 1U, /*!< Weak-linreg output tracks VDD_SOC_CAP voltage. */ +} pmu_1p1_weak_reference_source_t; + +/*! + * @brief Input voltage source for LDO_3P0 from USB VBus. + */ +typedef enum _pmu_3p0_vbus_voltage_source +{ + kPMU_3P0VBusVoltageSourceAlt0 = 0U, /*!< USB_OTG1_VBUS - Utilize VBUS OTG1 for power. */ + kPMU_3P0VBusVoltageSourceAlt1 = 1U, /*!< USB_OTG2_VBUS - Utilize VBUS OTG2 for power. */ +} pmu_3p0_vbus_voltage_source_t; + +/*! + * @brief Regulator voltage ramp rate. + */ +typedef enum _pmu_core_reg_voltage_ramp_rate +{ + kPMU_CoreRegVoltageRampRateFast = 0U, /*!< Fast. */ + kPMU_CoreRegVoltageRampRateMediumFast = 1U, /*!< Medium Fast. */ + kPMU_CoreRegVoltageRampRateMediumSlow = 2U, /*!< Medium Slow. */ + kPMU_CoreRegVoltageRampRateSlow = 0U, /*!< Slow. */ +} pmu_core_reg_voltage_ramp_rate_t; + +#if defined(FSL_FEATURE_PMU_HAS_LOWPWR_CTRL) && FSL_FEATURE_PMU_HAS_LOWPWR_CTRL +/*! + * @brief Mask values of power gate. + */ +enum _pmu_power_gate +{ + kPMU_PowerGateDisplay = PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK, /*!< Display power gate control. */ + kPMU_PowerGateDisplayLogic = PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK, /*!< Display logic power gate control. */ + kPMU_PowerGateL2 = PMU_LOWPWR_CTRL_L2_PWRGATE_MASK, /*!< L2 power gate control. */ + kPMU_PowerGateL1 = PMU_LOWPWR_CTRL_L1_PWRGATE_MASK, /*!< L1 power gate control. */ + kPMU_PowerGateRefTopIBias = PMU_LOWPWR_CTRL_REFTOP_IBIAS_OFF_MASK, /*!< Low power reftop ibias disable. */ +}; +#endif /* FSL_FEATURE_PMU_HAS_LOWPWR_CTRL. */ + +/*! + * @brief Bandgap select. + */ +typedef enum _pmu_power_bandgap +{ + kPMU_NormalPowerBandgap = 0U, /*!< Normal power bandgap. */ + kPMU_LowPowerBandgap = 1U, /*!< Low power bandgap. */ +} pmu_power_bandgap_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @name Status. + * @{ + */ + +/*! + * @brief Get PMU status flags. + * + * @param base PMU peripheral base address. + * @return PMU status flags.It indicate if regulator output of 1P1,3P0 and 2P5 is ok + * and brownout output of 1P1,3P0 and 2P5 is detected. + */ +uint32_t PMU_GetStatusFlags(PMU_Type *base); + +/*@}*/ + +/*! + * @name 1P1 Regular + * @{ + */ + +/*! + * @brief Selects the source for the reference voltage of the weak 1P1 regulator. + * + * @param base PMU peripheral base address. + * @param option The option for reference voltage source, see to #pmu_1p1_weak_reference_source_t. + */ +static inline void PMU_1P1SetWeakReferenceSource(PMU_Type *base, pmu_1p1_weak_reference_source_t option) +{ + base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_SELREF_WEAK_LINREG_MASK) | PMU_REG_1P1_SELREF_WEAK_LINREG(option); +} + +/*! + * @brief Enables the weak 1P1 regulator. + * + * This regulator can be used when the main 1P1 regulator is disabled, under low-power conditions. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_1P1EnableWeakRegulator(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_1P1 |= PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK; + } + else + { + base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_WEAK_LINREG_MASK; + } +} + +/*! + * @brief Adjust the 1P1 regulator output voltage. + * + * Each LSB is worth 25mV. Programming examples are detailed below. Other output target voltages + * may be interpolated from these examples. Choices must be in this range: + * - 0x1b(1.375V) >= output_trg >= 0x04(0.8V) + * - 0x04 : 0.8V + * - 0x10 : 1.1V (typical) + * - 0x1b : 1.375V + * NOTE: There may be reduced chip functionality or reliability at the extremes of the programming range. + * + * @param base PMU peripheral base address. + * @param value Setting value for the output. + */ +static inline void PMU_1P1SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value) +{ + base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_OUTPUT_TRG_MASK) | PMU_REG_1P1_OUTPUT_TRG(value); +} + +/*! + * @brief Adjust the 1P1 regulator brownout offset voltage. + * + * Control bits to adjust the regulator brownout offset voltage in 25mV steps. The reset + * brown-offset is 175mV below the programmed target code. + * Brownout target = OUTPUT_TRG - BO_OFFSET. + * Some steps may be irrelevant because of input supply limitations or load operation. + * + * @param base PMU peripheral base address. + * @param value Setting value for the brownout offset. The available range is in 3-bit. + */ +static inline void PMU_1P1SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value) +{ + base->REG_1P1 = (base->REG_1P1 & ~PMU_REG_1P1_BO_OFFSET_MASK) | PMU_REG_1P1_BO_OFFSET(value); +} + +/*! + * @brief Enable the pull-down circuitry in the regulator. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_1P1EnablePullDown(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_1P1 |= PMU_REG_1P1_ENABLE_PULLDOWN_MASK; + } + else + { + base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_PULLDOWN_MASK; + } +} + +/*! + * @brief Enable the current-limit circuitry in the regulator. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_1P1EnableCurrentLimit(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_1P1 |= PMU_REG_1P1_ENABLE_ILIMIT_MASK; + } + else + { + base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_ILIMIT_MASK; + } +} + +/*! + * @brief Enable the brownout circuitry in the regulator. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_1P1EnableBrownout(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_1P1 |= PMU_REG_1P1_ENABLE_BO_MASK; + } + else + { + base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_BO_MASK; + } +} + +/*! + * @brief Enable the regulator output. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_1P1EnableOutput(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_1P1 |= PMU_REG_1P1_ENABLE_LINREG_MASK; + } + else + { + base->REG_1P1 &= ~PMU_REG_1P1_ENABLE_LINREG_MASK; + } +} + +/*@}*/ + +/*! + * @name 3P0 Regular + * @{ + */ + +/*! + * @brief Adjust the 3P0 regulator output voltage. + * + * Each LSB is worth 25mV. Programming examples are detailed below. Other output target voltages + * may be interpolated from these examples. Choices must be in this range: + * - 0x00(2.625V) >= output_trg >= 0x1f(3.4V) + * - 0x00 : 2.625V + * - 0x0f : 3.0V (typical) + * - 0x1f : 3.4V + * + * @param base PMU peripheral base address. + * @param value Setting value for the output. + */ +static inline void PMU_3P0SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value) +{ + base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_OUTPUT_TRG_MASK) | PMU_REG_3P0_OUTPUT_TRG(value); +} + +/*! + * @brief Select input voltage source for LDO_3P0. + * + * Select input voltage source for LDO_3P0 from either USB_OTG1_VBUS or USB_OTG2_VBUS. If only + * one of the two VBUS voltages is present, it is automatically selected. + * + * @param base PMU peripheral base address. + * @param option User-defined input voltage source for LDO_3P0. + */ +static inline void PMU_3P0SetVBusVoltageSource(PMU_Type *base, pmu_3p0_vbus_voltage_source_t option) +{ + base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_VBUS_SEL_MASK) | PMU_REG_3P0_VBUS_SEL(option); +} + +/*! + * @brief Adjust the 3P0 regulator brownout offset voltage. + * + * Control bits to adjust the 3P0 regulator brownout offset voltage in 25mV steps. The reset + * brown-offset is 175mV below the programmed target code. + * Brownout target = OUTPUT_TRG - BO_OFFSET. + * Some steps may be irrelevant because of input supply limitations or load operation. + * + * @param base PMU peripheral base address. + * @param value Setting value for the brownout offset. The available range is in 3-bit. + */ +static inline void PMU_3P0SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value) +{ + base->REG_3P0 = (base->REG_3P0 & ~PMU_REG_3P0_BO_OFFSET_MASK) | PMU_REG_3P0_BO_OFFSET(value); +} + +/*! + * @brief Enable the current-limit circuitry in the 3P0 regulator. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_3P0EnableCurrentLimit(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_3P0 |= PMU_REG_3P0_ENABLE_ILIMIT_MASK; + } + else + { + base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_ILIMIT_MASK; + } +} + +/*! + * @brief Enable the brownout circuitry in the 3P0 regulator. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_3P0EnableBrownout(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_3P0 |= PMU_REG_3P0_ENABLE_BO_MASK; + } + else + { + base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_BO_MASK; + } +} + +/*! + * @brief Enable the 3P0 regulator output. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_3P0EnableOutput(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_3P0 |= PMU_REG_3P0_ENABLE_LINREG_MASK; + } + else + { + base->REG_3P0 &= ~PMU_REG_3P0_ENABLE_LINREG_MASK; + } +} + +/* @} */ + +/*! + * @name 2P5 Regulator + * @{ + */ + +/*! + * @brief Enables the weak 2P5 regulator. + * + * This low power regulator is used when the main 2P5 regulator is disabled + * to keep the 2.5V output roughly at 2.5V. Scales directly with the value of VDDHIGH_IN. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_2P5EnableWeakRegulator(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_2P5 |= PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK; + } + else + { + base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_WEAK_LINREG_MASK; + } +} + +/*! + * @brief Adjust the 1P1 regulator output voltage. + * + * Each LSB is worth 25mV. Programming examples are detailed below. Other output target voltages + * may be interpolated from these examples. Choices must be in this range: + * - 0x00(2.1V) >= output_trg >= 0x1f(2.875V) + * - 0x00 : 2.1V + * - 0x10 : 2.5V (typical) + * - 0x1f : 2.875V + * NOTE: There may be reduced chip functionality or reliability at the extremes of the programming range. + * + * @param base PMU peripheral base address. + * @param value Setting value for the output. + */ +static inline void PMU_2P5SetRegulatorOutputVoltage(PMU_Type *base, uint32_t value) +{ + base->REG_2P5 = (base->REG_2P5 & ~PMU_REG_2P5_OUTPUT_TRG_MASK) | PMU_REG_2P5_OUTPUT_TRG(value); +} + +/*! + * @brief Adjust the 2P5 regulator brownout offset voltage. + * + * Adjust the regulator brownout offset voltage in 25mV steps. The reset + * brown-offset is 175mV below the programmed target code. + * Brownout target = OUTPUT_TRG - BO_OFFSET. + * Some steps may be irrelevant because of input supply limitations or load operation. + * + * @param base PMU peripheral base address. + * @param value Setting value for the brownout offset. The available range is in 3-bit. + */ +static inline void PMU_2P5SetBrownoutOffsetVoltage(PMU_Type *base, uint32_t value) +{ + base->REG_2P5 = (base->REG_2P5 & ~PMU_REG_2P5_BO_OFFSET_MASK) | PMU_REG_2P5_BO_OFFSET(value); +} + +/*! + * @brief Enable the pull-down circuitry in the 2P5 regulator. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_2P5EnablePullDown(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_2P5 |= PMU_REG_2P5_ENABLE_PULLDOWN_MASK; + } + else + { + base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_PULLDOWN_MASK; + } +} + +/*! + * @brief Enable the pull-down circuitry in the 2P5 regulator. + * @deprecated Do not use this function. It has been superceded by @ref PMU_2P5EnablePullDown. + */ +static inline void PMU_2P1EnablePullDown(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_2P5 |= PMU_REG_2P5_ENABLE_PULLDOWN_MASK; + } + else + { + base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_PULLDOWN_MASK; + } +} + +/*! + * @brief Enable the current-limit circuitry in the 2P5 regulator. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_2P5EnableCurrentLimit(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_2P5 |= PMU_REG_2P5_ENABLE_ILIMIT_MASK; + } + else + { + base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_ILIMIT_MASK; + } +} + +/*! + * @brief Enable the brownout circuitry in the 2P5 regulator. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_2P5nableBrownout(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_2P5 |= PMU_REG_2P5_ENABLE_BO_MASK; + } + else + { + base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_BO_MASK; + } +} + +/*! + * @brief Enable the 2P5 regulator output. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_2P5EnableOutput(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_2P5 |= PMU_REG_2P5_ENABLE_LINREG_MASK; + } + else + { + base->REG_2P5 &= ~PMU_REG_2P5_ENABLE_LINREG_MASK; + } +} + +/* @} */ + +/*! + * @name Core Regulator + * @{ + */ + +/*! + * @brief Increase the gate drive on power gating FETs. + * + * If set, increases the gate drive on power gating FETs to reduce leakage in the off state. + * Care must be taken to apply this bit only when the input supply voltage to the power FET + * is less than 1.1V. + * NOTE: This bit should only be used in low-power modes where the external input supply voltage + * is nominally 0.9V. + * + * @param base PMU peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void PMU_CoreEnableIncreaseGateDrive(PMU_Type *base, bool enable) +{ + if (enable) + { + base->REG_CORE |= PMU_REG_CORE_FET_ODRIVE_MASK; + } + else + { + base->REG_CORE &= ~PMU_REG_CORE_FET_ODRIVE_MASK; + } +} + +/*! + * @brief Set the CORE regulator voltage ramp rate. + * + * @param base PMU peripheral base address. + * @param option User-defined option for voltage ramp rate, see to #pmu_core_reg_voltage_ramp_rate_t. + */ +static inline void PMU_CoreSetRegulatorVoltageRampRate(PMU_Type *base, pmu_core_reg_voltage_ramp_rate_t option) +{ + base->REG_CORE = (base->REG_CORE & ~PMU_REG_CORE_RAMP_RATE_MASK) | PMU_REG_CORE_RAMP_RATE(option); +} + +/*! + * @brief Define the target voltage for the SOC power domain. + * + * Define the target voltage for the SOC power domain. Single-bit increments reflect 25mV core + * voltage steps. Some steps may not be relevant because of input supply limitations or load operation. + * - 0x00 : Power gated off. + * - 0x01 : Target core voltage = 0.725V + * - 0x02 : Target core voltage = 0.750V + * - ... + * - 0x10 : Target core voltage = 1.100V + * - ... + * - 0x1e : Target core voltage = 1.450V + * - 0x1F : Power FET switched full on. No regulation. + * NOTE: This register is capable of programming an over-voltage condition on the device. Consult the + * datasheet Operating Ranges table for the allowed voltages. + * + * @param base PMU peripheral base address. + * @param value Setting value for target voltage. 5-bit available + */ +static inline void PMU_CoreSetSOCDomainVoltage(PMU_Type *base, uint32_t value) +{ + base->REG_CORE = (base->REG_CORE & ~PMU_REG_CORE_REG2_TARG_MASK) | PMU_REG_CORE_REG2_TARG(value); +} + +/*! + * @brief Define the target voltage for the ARM Core power domain. + * + * Define the target voltage for the ARM Core power domain. Single-bit increments reflect 25mV core + * voltage steps. Some steps may not be relevant because of input supply limitations or load operation. + * - 0x00 : Power gated off. + * - 0x01 : Target core voltage = 0.725V + * - 0x02 : Target core voltage = 0.750V + * - ... + * - 0x10 : Target core voltage = 1.100V + * - ... + * - 0x1e : Target core voltage = 1.450V + * - 0x1F : Power FET switched full on. No regulation. + * NOTE: This register is capable of programming an over-voltage condition on the device. Consult the + * datasheet Operating Ranges table for the allowed voltages. + * + * @param base PMU peripheral base address. + * @param value Setting value for target voltage. 5-bit available + */ +static inline void PMU_CoreSetARMCoreDomainVoltage(PMU_Type *base, uint32_t value) +{ + base->REG_CORE = (base->REG_CORE & ~PMU_REG_CORE_REG0_TARG_MASK) | PMU_REG_CORE_REG0_TARG(value); +} + +/* @} */ + +#if defined(FSL_FEATURE_PMU_HAS_LOWPWR_CTRL) && FSL_FEATURE_PMU_HAS_LOWPWR_CTRL +/*! + * @name Power Gate Controller & other + * @{ + */ + +/*! + * @brief Gate the power to modules. + * + * @param base PMU peripheral base address. + * @param gates Mask value for the module to be gated. See to #_pmu_power_gate. + */ +static inline void PMU_GatePower(PMU_Type *base, uint32_t gates) +{ + base->LOWPWR_CTRL_SET = gates; +} + +/*! + * @brief Ungate the power to modules. + * + * @param base PMU peripheral base address. + * @param gates Mask value for the module to be gated. See to #_pmu_power_gate. + */ +static inline void PMU_UngatePower(PMU_Type *base, uint32_t gates) +{ + base->LOWPWR_CTRL_CLR = gates; +} + +/*! + * @brief Enable the low power bandgap. + * + * @param base PMU peripheral base address. + * @param enable Enable the low power bandgap or use the normal power bandgap. + * @ + */ +static inline void PMU_EnableLowPowerBandgap(PMU_Type *base, bool enable) +{ + if (enable) + { + base->LOWPWR_CTRL_SET = PMU_LOWPWR_CTRL_LPBG_SEL_MASK; /* Use the low power bandgap. */ + } + else + { + base->LOWPWR_CTRL_CLR = PMU_LOWPWR_CTRL_LPBG_SEL_MASK; /* Use the normal power bandgap. */ + } +} +#endif /* FSL_FEATURE_PMU_HAS_LOWPWR_CTRL. */ +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* _FSL_PMU_H_*/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_pwm.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_pwm.c new file mode 100644 index 0000000000..ebb9d283dd --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_pwm.c @@ -0,0 +1,813 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_pwm.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pwm" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance from the base address + * + * @param base PWM peripheral base address + * + * @return The PWM module instance + */ +static uint32_t PWM_GetInstance(PWM_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to PWM bases for each instance. */ +static PWM_Type *const s_pwmBases[] = PWM_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to PWM clocks for each PWM submodule. */ +static const clock_ip_name_t s_pwmClocks[][FSL_FEATURE_PWM_SUBMODULE_COUNT] = PWM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t PWM_GetInstance(PWM_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_pwmBases); instance++) + { + if (s_pwmBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_pwmBases)); + + return instance; +} + +/*! + * brief Ungates the PWM submodule clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the PWM driver. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param config Pointer to user's PWM config structure. + * + * return kStatus_Success means success; else failed. + */ +status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config) +{ + assert(config); + + uint16_t reg; + + /* Source clock for submodule 0 cannot be itself */ + if ((config->clockSource == kPWM_Submodule0Clock) && (subModule == kPWM_Module_0)) + { + return kStatus_Fail; + } + + /* Reload source select clock for submodule 0 cannot be master reload */ + if ((config->reloadSelect == kPWM_MasterReload) && (subModule == kPWM_Module_0)) + { + return kStatus_Fail; + } + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the PWM submodule clock*/ + CLOCK_EnableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Clear the fault status flags */ + base->FSTS |= PWM_FSTS_FFLAG_MASK; + + reg = base->SM[subModule].CTRL2; + + /* Setup the submodule clock-source, control source of the INIT signal, + * source of the force output signal, operation in debug & wait modes and reload source select + */ + reg &= ~(PWM_CTRL2_CLK_SEL_MASK | PWM_CTRL2_FORCE_SEL_MASK | PWM_CTRL2_INIT_SEL_MASK | PWM_CTRL2_INDEP_MASK | + PWM_CTRL2_WAITEN_MASK | PWM_CTRL2_DBGEN_MASK | PWM_CTRL2_RELOAD_SEL_MASK); + reg |= (PWM_CTRL2_CLK_SEL(config->clockSource) | PWM_CTRL2_FORCE_SEL(config->forceTrigger) | + PWM_CTRL2_INIT_SEL(config->initializationControl) | PWM_CTRL2_DBGEN(config->enableDebugMode) | + PWM_CTRL2_WAITEN(config->enableWait) | PWM_CTRL2_RELOAD_SEL(config->reloadSelect)); + + /* Setup PWM A & B to be independent or a complementary-pair */ + switch (config->pairOperation) + { + case kPWM_Independent: + reg |= PWM_CTRL2_INDEP_MASK; + break; + case kPWM_ComplementaryPwmA: + base->MCTRL &= ~(1U << (PWM_MCTRL_IPOL_SHIFT + subModule)); + break; + case kPWM_ComplementaryPwmB: + base->MCTRL |= (1U << (PWM_MCTRL_IPOL_SHIFT + subModule)); + break; + default: + break; + } + base->SM[subModule].CTRL2 = reg; + + reg = base->SM[subModule].CTRL; + + /* Setup the clock prescale, load mode and frequency */ + reg &= ~(PWM_CTRL_PRSC_MASK | PWM_CTRL_LDFQ_MASK | PWM_CTRL_LDMOD_MASK); + reg |= (PWM_CTRL_PRSC(config->prescale) | PWM_CTRL_LDFQ(config->reloadFrequency)); + + /* Setup register reload logic */ + switch (config->reloadLogic) + { + case kPWM_ReloadImmediate: + reg |= PWM_CTRL_LDMOD_MASK; + break; + case kPWM_ReloadPwmHalfCycle: + reg |= PWM_CTRL_HALF_MASK; + reg &= ~PWM_CTRL_FULL_MASK; + break; + case kPWM_ReloadPwmFullCycle: + reg &= ~PWM_CTRL_HALF_MASK; + reg |= PWM_CTRL_FULL_MASK; + break; + case kPWM_ReloadPwmHalfAndFullCycle: + reg |= PWM_CTRL_HALF_MASK; + reg |= PWM_CTRL_FULL_MASK; + break; + default: + break; + } + base->SM[subModule].CTRL = reg; + + /* Setup the fault filter */ + if (base->FFILT & PWM_FFILT_FILT_PER_MASK) + { + /* When changing values for fault period from a non-zero value, first write a value of 0 + * to clear the filter + */ + base->FFILT &= ~(PWM_FFILT_FILT_PER_MASK); + } + + base->FFILT = (PWM_FFILT_FILT_CNT(config->faultFilterCount) | PWM_FFILT_FILT_PER(config->faultFilterPeriod)); + + /* Issue a Force trigger event when configured to trigger locally */ + if (config->forceTrigger == kPWM_Force_Local) + { + base->SM[subModule].CTRL2 |= PWM_CTRL2_FORCE(1U); + } + + return kStatus_Success; +} + +/*! + * brief Gate the PWM submodule clock + * + * param base PWM peripheral base address + * param subModule PWM submodule to deinitialize + */ +void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule) +{ + /* Stop the submodule */ + base->MCTRL &= ~(1U << (PWM_MCTRL_RUN_SHIFT + subModule)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the PWM submodule clock*/ + CLOCK_DisableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Fill in the PWM config struct with the default settings + * + * The default values are: + * code + * config->enableDebugMode = false; + * config->enableWait = false; + * config->reloadSelect = kPWM_LocalReload; + * config->faultFilterCount = 0; + * config->faultFilterPeriod = 0; + * config->clockSource = kPWM_BusClock; + * config->prescale = kPWM_Prescale_Divide_1; + * config->initializationControl = kPWM_Initialize_LocalSync; + * config->forceTrigger = kPWM_Force_Local; + * config->reloadFrequency = kPWM_LoadEveryOportunity; + * config->reloadLogic = kPWM_ReloadImmediate; + * config->pairOperation = kPWM_Independent; + * endcode + * param config Pointer to user's PWM config structure. + */ +void PWM_GetDefaultConfig(pwm_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + /* PWM is paused in debug mode */ + config->enableDebugMode = false; + /* PWM is paused in wait mode */ + config->enableWait = false; + /* PWM module uses the local reload signal to reload registers */ + config->reloadSelect = kPWM_LocalReload; + /* Fault filter count is set to 0 */ + config->faultFilterCount = 0; + /* Fault filter period is set to 0 which disables the fault filter */ + config->faultFilterPeriod = 0; + /* Use the IP Bus clock as source clock for the PWM submodule */ + config->clockSource = kPWM_BusClock; + /* Clock source prescale is set to divide by 1*/ + config->prescale = kPWM_Prescale_Divide_1; + /* Local sync causes initialization */ + config->initializationControl = kPWM_Initialize_LocalSync; + /* The local force signal, CTRL2[FORCE], from the submodule is used to force updates */ + config->forceTrigger = kPWM_Force_Local; + /* PWM reload frequency, reload opportunity is PWM half cycle or full cycle. + * This field is not used in Immediate reload mode + */ + config->reloadFrequency = kPWM_LoadEveryOportunity; + /* Buffered-registers get loaded with new values as soon as LDOK bit is set */ + config->reloadLogic = kPWM_ReloadImmediate; + /* PWM A & PWM B operate as 2 independent channels */ + config->pairOperation = kPWM_Independent; +} + +/*! + * brief Sets up the PWM signals for a PWM submodule. + * + * The function initializes the submodule according to the parameters passed in by the user. The function + * also sets up the value compare registers to match the PWM signal requirements. + * If the dead time insertion logic is enabled, the pulse period is reduced by the + * dead time period specified by the user. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param chnlParams Array of PWM channel parameters to configure the channel(s) + * param numOfChnls Number of channels to configure, this should be the size of the array passed in. + * Array size should not be more than 2 as each submodule has 2 pins to output PWM + * param mode PWM operation mode, options available in enumeration ::pwm_mode_t + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz PWM main counter clock in Hz. + * + * return Returns kStatusFail if there was error setting up the signal; kStatusSuccess otherwise + */ +status_t PWM_SetupPwm(PWM_Type *base, + pwm_submodule_t subModule, + const pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz) +{ + assert(chnlParams); + assert(pwmFreq_Hz); + assert(numOfChnls); + assert(srcClock_Hz); + + uint32_t pwmClock; + uint16_t pulseCnt = 0, pwmHighPulse = 0; + int16_t modulo = 0; + uint8_t i, polarityShift = 0, outputEnableShift = 0; + + if (numOfChnls > 2) + { + /* Each submodule has 2 signals; PWM A & PWM B */ + return kStatus_Fail; + } + + /* Divide the clock by the prescale value */ + pwmClock = (srcClock_Hz / (1U << ((base->SM[subModule].CTRL & PWM_CTRL_PRSC_MASK) >> PWM_CTRL_PRSC_SHIFT))); + pulseCnt = (pwmClock / pwmFreq_Hz); + + /* Setup each PWM channel */ + for (i = 0; i < numOfChnls; i++) + { + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * chnlParams->dutyCyclePercent) / 100; + + /* Setup the different match registers to generate the PWM signal */ + switch (mode) + { + case kPWM_SignedCenterAligned: + /* Setup the PWM period for a signed center aligned signal */ + modulo = pulseCnt >> 1; + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = (-modulo); + /* Indicates the center value */ + base->SM[subModule].VAL0 = 0; + /* Indicates the end of the PWM period */ + base->SM[subModule].VAL1 = modulo; + + /* Setup the PWM dutycycle */ + if (chnlParams->pwmChannel == kPWM_PwmA) + { + base->SM[subModule].VAL2 = (-(pwmHighPulse / 2)); + base->SM[subModule].VAL3 = (pwmHighPulse / 2); + } + else + { + base->SM[subModule].VAL4 = (-(pwmHighPulse / 2)); + base->SM[subModule].VAL5 = (pwmHighPulse / 2); + } + break; + case kPWM_CenterAligned: + /* Setup the PWM period for an unsigned center aligned signal */ + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = 0; + /* Indicates the center value */ + base->SM[subModule].VAL0 = (pulseCnt / 2); + /* Indicates the end of the PWM period */ + base->SM[subModule].VAL1 = pulseCnt; + + /* Setup the PWM dutycycle */ + if (chnlParams->pwmChannel == kPWM_PwmA) + { + base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2); + base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2); + } + else + { + base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2); + base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2); + } + break; + case kPWM_SignedEdgeAligned: + /* Setup the PWM period for a signed edge aligned signal */ + modulo = pulseCnt >> 1; + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = (-modulo); + /* Indicates the center value */ + base->SM[subModule].VAL0 = 0; + /* Indicates the end of the PWM period */ + base->SM[subModule].VAL1 = modulo; + + /* Setup the PWM dutycycle */ + if (chnlParams->pwmChannel == kPWM_PwmA) + { + base->SM[subModule].VAL2 = (-modulo); + base->SM[subModule].VAL3 = (-modulo + pwmHighPulse); + } + else + { + base->SM[subModule].VAL4 = (-modulo); + base->SM[subModule].VAL5 = (-modulo + pwmHighPulse); + } + break; + case kPWM_EdgeAligned: + /* Setup the PWM period for a unsigned edge aligned signal */ + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = 0; + /* Indicates the center value */ + base->SM[subModule].VAL0 = (pulseCnt / 2); + /* Indicates the end of the PWM period */ + base->SM[subModule].VAL1 = pulseCnt; + + /* Setup the PWM dutycycle */ + if (chnlParams->pwmChannel == kPWM_PwmA) + { + base->SM[subModule].VAL2 = 0; + base->SM[subModule].VAL3 = pwmHighPulse; + } + else + { + base->SM[subModule].VAL4 = 0; + base->SM[subModule].VAL5 = pwmHighPulse; + } + break; + default: + break; + } + /* Setup register shift values based on the channel being configured. + * Also setup the deadtime value + */ + if (chnlParams->pwmChannel == kPWM_PwmA) + { + polarityShift = PWM_OCTRL_POLA_SHIFT; + outputEnableShift = PWM_OUTEN_PWMA_EN_SHIFT; + base->SM[subModule].DTCNT0 = PWM_DTCNT0_DTCNT0(chnlParams->deadtimeValue); + } + else + { + polarityShift = PWM_OCTRL_POLB_SHIFT; + outputEnableShift = PWM_OUTEN_PWMB_EN_SHIFT; + base->SM[subModule].DTCNT1 = PWM_DTCNT1_DTCNT1(chnlParams->deadtimeValue); + } + + /* Setup signal active level */ + if (chnlParams->level == kPWM_HighTrue) + { + base->SM[subModule].OCTRL &= ~(1U << polarityShift); + } + else + { + base->SM[subModule].OCTRL |= (1U << polarityShift); + } + /* Enable PWM output */ + base->OUTEN |= (1U << (outputEnableShift + subModule)); + + /* Get the next channel parameters */ + chnlParams++; + } + + return kStatus_Success; +} + +/*! + * brief Updates the PWM signal's dutycycle. + * + * The function updates the PWM dutycyle to the new value that is passed in. + * If the dead time insertion logic is enabled then the pulse period is reduced by the + * dead time period specified by the user. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmSignal Signal (PWM A or PWM B) to update + * param currPwmMode The current PWM mode set during PWM setup + * param dutyCyclePercent New PWM pulse width, value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + */ +void PWM_UpdatePwmDutycycle(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t currPwmMode, + uint8_t dutyCyclePercent) +{ + assert(dutyCyclePercent <= 100); + assert(pwmSignal < 2); + uint16_t pulseCnt = 0, pwmHighPulse = 0; + int16_t modulo = 0; + + switch (currPwmMode) + { + case kPWM_SignedCenterAligned: + modulo = base->SM[subModule].VAL1; + pulseCnt = modulo * 2; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100; + + /* Setup the PWM dutycycle */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = (-(pwmHighPulse / 2)); + base->SM[subModule].VAL3 = (pwmHighPulse / 2); + } + else + { + base->SM[subModule].VAL4 = (-(pwmHighPulse / 2)); + base->SM[subModule].VAL5 = (pwmHighPulse / 2); + } + break; + case kPWM_CenterAligned: + pulseCnt = base->SM[subModule].VAL1; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100; + + /* Setup the PWM dutycycle */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2); + base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2); + } + else + { + base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2); + base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2); + } + break; + case kPWM_SignedEdgeAligned: + modulo = base->SM[subModule].VAL1; + pulseCnt = modulo * 2; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100; + + /* Setup the PWM dutycycle */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = (-modulo); + base->SM[subModule].VAL3 = (-modulo + pwmHighPulse); + } + else + { + base->SM[subModule].VAL4 = (-modulo); + base->SM[subModule].VAL5 = (-modulo + pwmHighPulse); + } + break; + case kPWM_EdgeAligned: + pulseCnt = base->SM[subModule].VAL1; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCyclePercent) / 100; + + /* Setup the PWM dutycycle */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = 0; + base->SM[subModule].VAL3 = pwmHighPulse; + } + else + { + base->SM[subModule].VAL4 = 0; + base->SM[subModule].VAL5 = pwmHighPulse; + } + break; + default: + break; + } +} + +/*! + * brief Sets up the PWM input capture + * + * Each PWM submodule has 3 pins that can be configured for use as input capture pins. This function + * sets up the capture parameters for each pin and enables the pin for input capture operation. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmChannel Channel in the submodule to setup + * param inputCaptureParams Parameters passed in to set up the input pin + */ +void PWM_SetupInputCapture(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + const pwm_input_capture_param_t *inputCaptureParams) +{ + uint32_t reg = 0; + switch (pwmChannel) + { + case kPWM_PwmA: + /* Setup the capture paramters for PWM A pin */ + reg = (PWM_CAPTCTRLA_INP_SELA(inputCaptureParams->captureInputSel) | + PWM_CAPTCTRLA_EDGA0(inputCaptureParams->edge0) | PWM_CAPTCTRLA_EDGA1(inputCaptureParams->edge1) | + PWM_CAPTCTRLA_ONESHOTA(inputCaptureParams->enableOneShotCapture) | + PWM_CAPTCTRLA_CFAWM(inputCaptureParams->fifoWatermark)); + /* Enable the edge counter if using the output edge counter */ + if (inputCaptureParams->captureInputSel) + { + reg |= PWM_CAPTCTRLA_EDGCNTA_EN_MASK; + } + /* Enable input capture operation */ + reg |= PWM_CAPTCTRLA_ARMA_MASK; + + base->SM[subModule].CAPTCTRLA = reg; + + /* Setup the compare value when using the edge counter as source */ + base->SM[subModule].CAPTCOMPA = PWM_CAPTCOMPA_EDGCMPA(inputCaptureParams->edgeCompareValue); + /* Setup PWM A pin for input capture */ + base->OUTEN &= ~(1U << (PWM_OUTEN_PWMA_EN_SHIFT + subModule)); + + break; + case kPWM_PwmB: + /* Setup the capture paramters for PWM B pin */ + reg = (PWM_CAPTCTRLB_INP_SELB(inputCaptureParams->captureInputSel) | + PWM_CAPTCTRLB_EDGB0(inputCaptureParams->edge0) | PWM_CAPTCTRLB_EDGB1(inputCaptureParams->edge1) | + PWM_CAPTCTRLB_ONESHOTB(inputCaptureParams->enableOneShotCapture) | + PWM_CAPTCTRLB_CFBWM(inputCaptureParams->fifoWatermark)); + /* Enable the edge counter if using the output edge counter */ + if (inputCaptureParams->captureInputSel) + { + reg |= PWM_CAPTCTRLB_EDGCNTB_EN_MASK; + } + /* Enable input capture operation */ + reg |= PWM_CAPTCTRLB_ARMB_MASK; + + base->SM[subModule].CAPTCTRLB = reg; + + /* Setup the compare value when using the edge counter as source */ + base->SM[subModule].CAPTCOMPB = PWM_CAPTCOMPB_EDGCMPB(inputCaptureParams->edgeCompareValue); + /* Setup PWM B pin for input capture */ + base->OUTEN &= ~(1U << (PWM_OUTEN_PWMB_EN_SHIFT + subModule)); + break; + case kPWM_PwmX: + reg = (PWM_CAPTCTRLX_INP_SELX(inputCaptureParams->captureInputSel) | + PWM_CAPTCTRLX_EDGX0(inputCaptureParams->edge0) | PWM_CAPTCTRLX_EDGX1(inputCaptureParams->edge1) | + PWM_CAPTCTRLX_ONESHOTX(inputCaptureParams->enableOneShotCapture) | + PWM_CAPTCTRLX_CFXWM(inputCaptureParams->fifoWatermark)); + /* Enable the edge counter if using the output edge counter */ + if (inputCaptureParams->captureInputSel) + { + reg |= PWM_CAPTCTRLX_EDGCNTX_EN_MASK; + } + /* Enable input capture operation */ + reg |= PWM_CAPTCTRLX_ARMX_MASK; + + base->SM[subModule].CAPTCTRLX = reg; + + /* Setup the compare value when using the edge counter as source */ + base->SM[subModule].CAPTCOMPX = PWM_CAPTCOMPX_EDGCMPX(inputCaptureParams->edgeCompareValue); + /* Setup PWM X pin for input capture */ + base->OUTEN &= ~(1U << (PWM_OUTEN_PWMX_EN_SHIFT + subModule)); + break; + default: + break; + } +} + +/*! + * brief Sets up the PWM fault protection. + * + * PWM has 4 fault inputs. + * + * param base PWM peripheral base address + * param faultNum PWM fault to configure. + * param faultParams Pointer to the PWM fault config structure + */ +void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams) +{ + assert(faultParams); + uint16_t reg; + + reg = base->FCTRL; + /* Set the faults level-settting */ + if (faultParams->faultLevel) + { + reg |= (1U << (PWM_FCTRL_FLVL_SHIFT + faultNum)); + } + else + { + reg &= ~(1U << (PWM_FCTRL_FLVL_SHIFT + faultNum)); + } + /* Set the fault clearing mode */ + if (faultParams->faultClearingMode) + { + /* Use manual fault clearing */ + reg &= ~(1U << (PWM_FCTRL_FAUTO_SHIFT + faultNum)); + if (faultParams->faultClearingMode == kPWM_ManualSafety) + { + /* Use manual fault clearing with safety mode enabled */ + reg |= (1U << (PWM_FCTRL_FSAFE_SHIFT + faultNum)); + } + else + { + /* Use manual fault clearing with safety mode disabled */ + reg &= ~(1U << (PWM_FCTRL_FSAFE_SHIFT + faultNum)); + } + } + else + { + /* Use automatic fault clearing */ + reg |= (1U << (PWM_FCTRL_FAUTO_SHIFT + faultNum)); + } + base->FCTRL = reg; + + /* Set the combinational path option */ + if (faultParams->enableCombinationalPath) + { + /* Combinational path from the fault input to the PWM output is available */ + base->FCTRL2 &= ~(1U << faultNum); + } + else + { + /* No combinational path available, only fault filter & latch signal can disable PWM output */ + base->FCTRL2 |= (1U << faultNum); + } + + /* Initially clear both recovery modes */ + reg = base->FSTS; + reg &= ~((1U << (PWM_FSTS_FFULL_SHIFT + faultNum)) | (1U << (PWM_FSTS_FHALF_SHIFT + faultNum))); + /* Setup fault recovery */ + switch (faultParams->recoverMode) + { + case kPWM_NoRecovery: + break; + case kPWM_RecoverHalfCycle: + reg |= (1U << (PWM_FSTS_FHALF_SHIFT + faultNum)); + break; + case kPWM_RecoverFullCycle: + reg |= (1U << (PWM_FSTS_FFULL_SHIFT + faultNum)); + break; + case kPWM_RecoverHalfAndFullCycle: + reg |= (1U << (PWM_FSTS_FHALF_SHIFT + faultNum)); + reg |= (1U << (PWM_FSTS_FFULL_SHIFT + faultNum)); + break; + default: + break; + } + base->FSTS = reg; +} + +/*! + * brief Selects the signal to output on a PWM pin when a FORCE_OUT signal is asserted. + * + * The user specifies which channel to configure by supplying the submodule number and whether + * to modify PWM A or PWM B within that submodule. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmChannel Channel to configure + * param mode Signal to output when a FORCE_OUT is triggered + */ +void PWM_SetupForceSignal(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_force_signal_t mode) + +{ + uint16_t shift; + uint16_t reg; + + /* DTSRCSEL register has 4 bits per submodule; 2 bits for PWM A and 2 bits for PWM B */ + shift = subModule * 4 + pwmChannel * 2; + + /* Setup the signal to be passed upon occurrence of a FORCE_OUT signal */ + reg = base->DTSRCSEL; + reg &= ~(0x3U << shift); + reg |= (uint16_t)((uint16_t)mode << shift); + base->DTSRCSEL = reg; +} + +/*! + * brief Enables the selected PWM interrupts + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) +{ + /* Upper 16 bits are for related to the submodule */ + base->SM[subModule].INTEN |= (mask & 0xFFFFU); + /* Fault related interrupts */ + base->FCTRL |= ((mask >> 16U) & PWM_FCTRL_FIE_MASK); +} + +/*! + * brief Disables the selected PWM interrupts + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) +{ + base->SM[subModule].INTEN &= ~(mask & 0xFFFF); + base->FCTRL &= ~((mask >> 16U) & PWM_FCTRL_FIE_MASK); +} + +/*! + * brief Gets the enabled PWM interrupts + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * + * return The enabled interrupts. This is the logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule) +{ + uint32_t enabledInterrupts; + + enabledInterrupts = base->SM[subModule].INTEN; + enabledInterrupts |= ((uint32_t)(base->FCTRL & PWM_FCTRL_FIE_MASK) << 16U); + return enabledInterrupts; +} + +/*! + * brief Gets the PWM status flags + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * + * return The status flags. This is the logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule) +{ + uint32_t statusFlags; + + statusFlags = base->SM[subModule].STS; + statusFlags |= ((uint32_t)(base->FSTS & PWM_FSTS_FFLAG_MASK) << 16U); + + return statusFlags; +} + +/*! + * brief Clears the PWM status flags + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) +{ + uint16_t reg; + + base->SM[subModule].STS = (mask & 0xFFFFU); + reg = base->FSTS; + /* Clear the fault flags and set only the ones we wish to clear as the fault flags are cleared + * by writing a login one + */ + reg &= ~(PWM_FSTS_FFLAG_MASK); + reg |= ((mask >> 16U) & PWM_FSTS_FFLAG_MASK); + base->FSTS = reg; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_pwm.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_pwm.h new file mode 100644 index 0000000000..29e78a2be1 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_pwm.h @@ -0,0 +1,669 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_PWM_H_ +#define _FSL_PWM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pwm_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! Number of bits per submodule for software output control */ +#define PWM_SUBMODULE_SWCONTROL_WIDTH 2 + +/*! @brief List of PWM submodules */ +typedef enum _pwm_submodule +{ + kPWM_Module_0 = 0U, /*!< Submodule 0 */ + kPWM_Module_1, /*!< Submodule 1 */ + kPWM_Module_2, /*!< Submodule 2 */ + kPWM_Module_3 /*!< Submodule 3 */ +} pwm_submodule_t; + +/*! @brief List of PWM channels in each module */ +typedef enum _pwm_channels +{ + kPWM_PwmB = 0U, + kPWM_PwmA, + kPWM_PwmX +} pwm_channels_t; + +/*! @brief List of PWM value registers */ +typedef enum _pwm_value_register +{ + kPWM_ValueRegister_0 = 0U, /*!< PWM Value0 register */ + kPWM_ValueRegister_1, /*!< PWM Value1 register */ + kPWM_ValueRegister_2, /*!< PWM Value2 register */ + kPWM_ValueRegister_3, /*!< PWM Value3 register */ + kPWM_ValueRegister_4, /*!< PWM Value4 register */ + kPWM_ValueRegister_5 /*!< PWM Value5 register */ +} pwm_value_register_t; + +/*! @brief PWM clock source selection.*/ +typedef enum _pwm_clock_source +{ + kPWM_BusClock = 0U, /*!< The IPBus clock is used as the clock */ + kPWM_ExternalClock, /*!< EXT_CLK is used as the clock */ + kPWM_Submodule0Clock /*!< Clock of the submodule 0 (AUX_CLK) is used as the source clock */ +} pwm_clock_source_t; + +/*! @brief PWM prescaler factor selection for clock source*/ +typedef enum _pwm_clock_prescale +{ + kPWM_Prescale_Divide_1 = 0U, /*!< PWM clock frequency = fclk/1 */ + kPWM_Prescale_Divide_2, /*!< PWM clock frequency = fclk/2 */ + kPWM_Prescale_Divide_4, /*!< PWM clock frequency = fclk/4 */ + kPWM_Prescale_Divide_8, /*!< PWM clock frequency = fclk/8 */ + kPWM_Prescale_Divide_16, /*!< PWM clock frequency = fclk/16 */ + kPWM_Prescale_Divide_32, /*!< PWM clock frequency = fclk/32 */ + kPWM_Prescale_Divide_64, /*!< PWM clock frequency = fclk/64 */ + kPWM_Prescale_Divide_128 /*!< PWM clock frequency = fclk/128 */ +} pwm_clock_prescale_t; + +/*! @brief Options that can trigger a PWM FORCE_OUT */ +typedef enum _pwm_force_output_trigger +{ + kPWM_Force_Local = 0U, /*!< The local force signal, CTRL2[FORCE], from the submodule is used to force updates */ + kPWM_Force_Master, /*!< The master force signal from submodule 0 is used to force updates */ + kPWM_Force_LocalReload, /*!< The local reload signal from this submodule is used to force updates without regard to + the state of LDOK */ + kPWM_Force_MasterReload, /*!< The master reload signal from submodule 0 is used to force updates if LDOK is set */ + kPWM_Force_LocalSync, /*!< The local sync signal from this submodule is used to force updates */ + kPWM_Force_MasterSync, /*!< The master sync signal from submodule0 is used to force updates */ + kPWM_Force_External, /*!< The external force signal, EXT_FORCE, from outside the PWM module causes updates */ + kPWM_Force_ExternalSync /*!< The external sync signal, EXT_SYNC, from outside the PWM module causes updates */ +} pwm_force_output_trigger_t; + +/*! @brief PWM counter initialization options */ +typedef enum _pwm_init_source +{ + kPWM_Initialize_LocalSync = 0U, /*!< Local sync causes initialization */ + kPWM_Initialize_MasterReload, /*!< Master reload from submodule 0 causes initialization */ + kPWM_Initialize_MasterSync, /*!< Master sync from submodule 0 causes initialization */ + kPWM_Initialize_ExtSync /*!< EXT_SYNC causes initialization */ +} pwm_init_source_t; + +/*! @brief PWM load frequency selection */ +typedef enum _pwm_load_frequency +{ + kPWM_LoadEveryOportunity = 0U, /*!< Every PWM opportunity */ + kPWM_LoadEvery2Oportunity, /*!< Every 2 PWM opportunities */ + kPWM_LoadEvery3Oportunity, /*!< Every 3 PWM opportunities */ + kPWM_LoadEvery4Oportunity, /*!< Every 4 PWM opportunities */ + kPWM_LoadEvery5Oportunity, /*!< Every 5 PWM opportunities */ + kPWM_LoadEvery6Oportunity, /*!< Every 6 PWM opportunities */ + kPWM_LoadEvery7Oportunity, /*!< Every 7 PWM opportunities */ + kPWM_LoadEvery8Oportunity, /*!< Every 8 PWM opportunities */ + kPWM_LoadEvery9Oportunity, /*!< Every 9 PWM opportunities */ + kPWM_LoadEvery10Oportunity, /*!< Every 10 PWM opportunities */ + kPWM_LoadEvery11Oportunity, /*!< Every 11 PWM opportunities */ + kPWM_LoadEvery12Oportunity, /*!< Every 12 PWM opportunities */ + kPWM_LoadEvery13Oportunity, /*!< Every 13 PWM opportunities */ + kPWM_LoadEvery14Oportunity, /*!< Every 14 PWM opportunities */ + kPWM_LoadEvery15Oportunity, /*!< Every 15 PWM opportunities */ + kPWM_LoadEvery16Oportunity /*!< Every 16 PWM opportunities */ +} pwm_load_frequency_t; + +/*! @brief List of PWM fault selections */ +typedef enum _pwm_fault_input +{ + kPWM_Fault_0 = 0U, /*!< Fault 0 input pin */ + kPWM_Fault_1, /*!< Fault 1 input pin */ + kPWM_Fault_2, /*!< Fault 2 input pin */ + kPWM_Fault_3 /*!< Fault 3 input pin */ +} pwm_fault_input_t; + +/*! @brief PWM capture edge select */ +typedef enum _pwm_input_capture_edge +{ + kPWM_Disable = 0U, /*!< Disabled */ + kPWM_FallingEdge, /*!< Capture on falling edge only */ + kPWM_RisingEdge, /*!< Capture on rising edge only */ + kPWM_RiseAndFallEdge /*!< Capture on rising or falling edge */ +} pwm_input_capture_edge_t; + +/*! @brief PWM output options when a FORCE_OUT signal is asserted */ +typedef enum _pwm_force_signal +{ + kPWM_UsePwm = 0U, /*!< Generated PWM signal is used by the deadtime logic.*/ + kPWM_InvertedPwm, /*!< Inverted PWM signal is used by the deadtime logic.*/ + kPWM_SoftwareControl, /*!< Software controlled value is used by the deadtime logic. */ + kPWM_UseExternal /*!< PWM_EXTA signal is used by the deadtime logic. */ +} pwm_force_signal_t; + +/*! @brief Options available for the PWM A & B pair operation */ +typedef enum _pwm_chnl_pair_operation +{ + kPWM_Independent = 0U, /*!< PWM A & PWM B operate as 2 independent channels */ + kPWM_ComplementaryPwmA, /*!< PWM A & PWM B are complementary channels, PWM A generates the signal */ + kPWM_ComplementaryPwmB /*!< PWM A & PWM B are complementary channels, PWM B generates the signal */ +} pwm_chnl_pair_operation_t; + +/*! @brief Options available on how to load the buffered-registers with new values */ +typedef enum _pwm_register_reload +{ + kPWM_ReloadImmediate = 0U, /*!< Buffered-registers get loaded with new values as soon as LDOK bit is set */ + kPWM_ReloadPwmHalfCycle, /*!< Registers loaded on a PWM half cycle */ + kPWM_ReloadPwmFullCycle, /*!< Registers loaded on a PWM full cycle */ + kPWM_ReloadPwmHalfAndFullCycle /*!< Registers loaded on a PWM half & full cycle */ +} pwm_register_reload_t; + +/*! @brief Options available on how to re-enable the PWM output when recovering from a fault */ +typedef enum _pwm_fault_recovery_mode +{ + kPWM_NoRecovery = 0U, /*!< PWM output will stay inactive */ + kPWM_RecoverHalfCycle, /*!< PWM output re-enabled at the first half cycle */ + kPWM_RecoverFullCycle, /*!< PWM output re-enabled at the first full cycle */ + kPWM_RecoverHalfAndFullCycle /*!< PWM output re-enabled at the first half or full cycle */ +} pwm_fault_recovery_mode_t; + +/*! @brief List of PWM interrupt options */ +typedef enum _pwm_interrupt_enable +{ + kPWM_CompareVal0InterruptEnable = (1U << 0), /*!< PWM VAL0 compare interrupt */ + kPWM_CompareVal1InterruptEnable = (1U << 1), /*!< PWM VAL1 compare interrupt */ + kPWM_CompareVal2InterruptEnable = (1U << 2), /*!< PWM VAL2 compare interrupt */ + kPWM_CompareVal3InterruptEnable = (1U << 3), /*!< PWM VAL3 compare interrupt */ + kPWM_CompareVal4InterruptEnable = (1U << 4), /*!< PWM VAL4 compare interrupt */ + kPWM_CompareVal5InterruptEnable = (1U << 5), /*!< PWM VAL5 compare interrupt */ + kPWM_CaptureX0InterruptEnable = (1U << 6), /*!< PWM capture X0 interrupt */ + kPWM_CaptureX1InterruptEnable = (1U << 7), /*!< PWM capture X1 interrupt */ + kPWM_CaptureB0InterruptEnable = (1U << 8), /*!< PWM capture B0 interrupt */ + kPWM_CaptureB1InterruptEnable = (1U << 9), /*!< PWM capture B1 interrupt */ + kPWM_CaptureA0InterruptEnable = (1U << 10), /*!< PWM capture A0 interrupt */ + kPWM_CaptureA1InterruptEnable = (1U << 11), /*!< PWM capture A1 interrupt */ + kPWM_ReloadInterruptEnable = (1U << 12), /*!< PWM reload interrupt */ + kPWM_ReloadErrorInterruptEnable = (1U << 13), /*!< PWM reload error interrupt */ + kPWM_Fault0InterruptEnable = (1U << 16), /*!< PWM fault 0 interrupt */ + kPWM_Fault1InterruptEnable = (1U << 17), /*!< PWM fault 1 interrupt */ + kPWM_Fault2InterruptEnable = (1U << 18), /*!< PWM fault 2 interrupt */ + kPWM_Fault3InterruptEnable = (1U << 19) /*!< PWM fault 3 interrupt */ +} pwm_interrupt_enable_t; + +/*! @brief List of PWM status flags */ +typedef enum _pwm_status_flags +{ + kPWM_CompareVal0Flag = (1U << 0), /*!< PWM VAL0 compare flag */ + kPWM_CompareVal1Flag = (1U << 1), /*!< PWM VAL1 compare flag */ + kPWM_CompareVal2Flag = (1U << 2), /*!< PWM VAL2 compare flag */ + kPWM_CompareVal3Flag = (1U << 3), /*!< PWM VAL3 compare flag */ + kPWM_CompareVal4Flag = (1U << 4), /*!< PWM VAL4 compare flag */ + kPWM_CompareVal5Flag = (1U << 5), /*!< PWM VAL5 compare flag */ + kPWM_CaptureX0Flag = (1U << 6), /*!< PWM capture X0 flag */ + kPWM_CaptureX1Flag = (1U << 7), /*!< PWM capture X1 flag */ + kPWM_CaptureB0Flag = (1U << 8), /*!< PWM capture B0 flag */ + kPWM_CaptureB1Flag = (1U << 9), /*!< PWM capture B1 flag */ + kPWM_CaptureA0Flag = (1U << 10), /*!< PWM capture A0 flag */ + kPWM_CaptureA1Flag = (1U << 11), /*!< PWM capture A1 flag */ + kPWM_ReloadFlag = (1U << 12), /*!< PWM reload flag */ + kPWM_ReloadErrorFlag = (1U << 13), /*!< PWM reload error flag */ + kPWM_RegUpdatedFlag = (1U << 14), /*!< PWM registers updated flag */ + kPWM_Fault0Flag = (1U << 16), /*!< PWM fault 0 flag */ + kPWM_Fault1Flag = (1U << 17), /*!< PWM fault 1 flag */ + kPWM_Fault2Flag = (1U << 18), /*!< PWM fault 2 flag */ + kPWM_Fault3Flag = (1U << 19) /*!< PWM fault 3 flag */ +} pwm_status_flags_t; + +/*! @brief PWM operation mode */ +typedef enum _pwm_mode +{ + kPWM_SignedCenterAligned = 0U, /*!< Signed center-aligned */ + kPWM_CenterAligned, /*!< Unsigned cente-aligned */ + kPWM_SignedEdgeAligned, /*!< Signed edge-aligned */ + kPWM_EdgeAligned /*!< Unsigned edge-aligned */ +} pwm_mode_t; + +/*! @brief PWM output pulse mode, high-true or low-true */ +typedef enum _pwm_level_select +{ + kPWM_HighTrue = 0U, /*!< High level represents "on" or "active" state */ + kPWM_LowTrue /*!< Low level represents "on" or "active" state */ +} pwm_level_select_t; + +/*! @brief PWM reload source select */ +typedef enum _pwm_reload_source_select +{ + kPWM_LocalReload = 0U, /*!< The local reload signal is used to reload registers */ + kPWM_MasterReload /*!< The master reload signal (from submodule 0) is used to reload */ +} pwm_reload_source_select_t; + +/*! @brief PWM fault clearing options */ +typedef enum _pwm_fault_clear +{ + kPWM_Automatic = 0U, /*!< Automatic fault clearing */ + kPWM_ManualNormal, /*!< Manual fault clearing with no fault safety mode */ + kPWM_ManualSafety /*!< Manual fault clearing with fault safety mode */ +} pwm_fault_clear_t; + +/*! @brief Options for submodule master control operation */ +typedef enum _pwm_module_control +{ + kPWM_Control_Module_0 = (1U << 0), /*!< Control submodule 0's start/stop,buffer reload operation */ + kPWM_Control_Module_1 = (1U << 1), /*!< Control submodule 1's start/stop,buffer reload operation */ + kPWM_Control_Module_2 = (1U << 2), /*!< Control submodule 2's start/stop,buffer reload operation */ + kPWM_Control_Module_3 = (1U << 3) /*!< Control submodule 3's start/stop,buffer reload operation */ +} pwm_module_control_t; + +/*! @brief Structure for the user to define the PWM signal characteristics */ +typedef struct _pwm_signal_param +{ + pwm_channels_t pwmChannel; /*!< PWM channel being configured; PWM A or PWM B */ + uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 + 0=inactive signal(0% duty cycle)... + 100=always active signal (100% duty cycle)*/ + pwm_level_select_t level; /*!< PWM output active level select */ + uint16_t deadtimeValue; /*!< The deadtime value; only used if channel pair is operating in complementary mode */ +} pwm_signal_param_t; + +/*! + * @brief PWM config structure + * + * This structure holds the configuration settings for the PWM peripheral. To initialize this + * structure to reasonable defaults, call the PWM_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _pwm_config +{ + bool enableDebugMode; /*!< true: PWM continues to run in debug mode; + false: PWM is paused in debug mode */ + bool enableWait; /*!< true: PWM continues to run in WAIT mode; + false: PWM is paused in WAIT mode */ + uint8_t faultFilterCount; /*!< Fault filter count */ + uint8_t faultFilterPeriod; /*!< Fault filter period;value of 0 will bypass the filter */ + pwm_init_source_t initializationControl; /*!< Option to initialize the counter */ + pwm_clock_source_t clockSource; /*!< Clock source for the counter */ + pwm_clock_prescale_t prescale; /*!< Pre-scaler to divide down the clock */ + pwm_chnl_pair_operation_t pairOperation; /*!< Channel pair in indepedent or complementary mode */ + pwm_register_reload_t reloadLogic; /*!< PWM Reload logic setup */ + pwm_reload_source_select_t reloadSelect; /*!< Reload source select */ + pwm_load_frequency_t reloadFrequency; /*!< Specifies when to reload, used when user's choice + is not immediate reload */ + pwm_force_output_trigger_t forceTrigger; /*!< Specify which signal will trigger a FORCE_OUT */ +} pwm_config_t; + +/*! @brief Structure is used to hold the parameters to configure a PWM fault */ +typedef struct _pwm_fault_param +{ + pwm_fault_clear_t faultClearingMode; /*!< Fault clearing mode to use */ + bool faultLevel; /*!< true: Logic 1 indicates fault; + false: Logic 0 indicates fault */ + bool enableCombinationalPath; /*!< true: Combinational Path from fault input is enabled; + false: No combination path is available */ + pwm_fault_recovery_mode_t recoverMode; /*!< Specify when to re-enable the PWM output */ +} pwm_fault_param_t; + +/*! + * @brief Structure is used to hold parameters to configure the capture capability of a signal pin + */ +typedef struct _pwm_input_capture_param +{ + bool captureInputSel; /*!< true: Use the edge counter signal as source + false: Use the raw input signal from the pin as source */ + uint8_t edgeCompareValue; /*!< Compare value, used only if edge counter is used as source */ + pwm_input_capture_edge_t edge0; /*!< Specify which edge causes a capture for input circuitry 0 */ + pwm_input_capture_edge_t edge1; /*!< Specify which edge causes a capture for input circuitry 1 */ + bool enableOneShotCapture; /*!< true: Use one-shot capture mode; + false: Use free-running capture mode */ + uint8_t fifoWatermark; /*!< Watermark level for capture FIFO. The capture flags in + the status register will set if the word count in the FIFO + is greater than this watermark level */ +} pwm_input_capture_param_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the PWM submodule clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the PWM driver. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param config Pointer to user's PWM config structure. + * + * @return kStatus_Success means success; else failed. + */ +status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config); + +/*! + * @brief Gate the PWM submodule clock + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to deinitialize + */ +void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule); + +/*! + * @brief Fill in the PWM config struct with the default settings + * + * The default values are: + * @code + * config->enableDebugMode = false; + * config->enableWait = false; + * config->reloadSelect = kPWM_LocalReload; + * config->faultFilterCount = 0; + * config->faultFilterPeriod = 0; + * config->clockSource = kPWM_BusClock; + * config->prescale = kPWM_Prescale_Divide_1; + * config->initializationControl = kPWM_Initialize_LocalSync; + * config->forceTrigger = kPWM_Force_Local; + * config->reloadFrequency = kPWM_LoadEveryOportunity; + * config->reloadLogic = kPWM_ReloadImmediate; + * config->pairOperation = kPWM_Independent; + * @endcode + * @param config Pointer to user's PWM config structure. + */ +void PWM_GetDefaultConfig(pwm_config_t *config); + +/*! @}*/ + +/*! + * @name Module PWM output + * @{ + */ +/*! + * @brief Sets up the PWM signals for a PWM submodule. + * + * The function initializes the submodule according to the parameters passed in by the user. The function + * also sets up the value compare registers to match the PWM signal requirements. + * If the dead time insertion logic is enabled, the pulse period is reduced by the + * dead time period specified by the user. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param chnlParams Array of PWM channel parameters to configure the channel(s) + * @param numOfChnls Number of channels to configure, this should be the size of the array passed in. + * Array size should not be more than 2 as each submodule has 2 pins to output PWM + * @param mode PWM operation mode, options available in enumeration ::pwm_mode_t + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz PWM main counter clock in Hz. + * + * @return Returns kStatusFail if there was error setting up the signal; kStatusSuccess otherwise + */ +status_t PWM_SetupPwm(PWM_Type *base, + pwm_submodule_t subModule, + const pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz); + +/*! + * @brief Updates the PWM signal's dutycycle. + * + * The function updates the PWM dutycyle to the new value that is passed in. + * If the dead time insertion logic is enabled then the pulse period is reduced by the + * dead time period specified by the user. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmSignal Signal (PWM A or PWM B) to update + * @param currPwmMode The current PWM mode set during PWM setup + * @param dutyCyclePercent New PWM pulse width, value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + */ +void PWM_UpdatePwmDutycycle(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t currPwmMode, + uint8_t dutyCyclePercent); + +/*! @}*/ + +/*! + * @brief Sets up the PWM input capture + * + * Each PWM submodule has 3 pins that can be configured for use as input capture pins. This function + * sets up the capture parameters for each pin and enables the pin for input capture operation. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel Channel in the submodule to setup + * @param inputCaptureParams Parameters passed in to set up the input pin + */ +void PWM_SetupInputCapture(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + const pwm_input_capture_param_t *inputCaptureParams); + +/*! + * @brief Sets up the PWM fault protection. + * + * PWM has 4 fault inputs. + * + * @param base PWM peripheral base address + * @param faultNum PWM fault to configure. + * @param faultParams Pointer to the PWM fault config structure + */ +void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams); + +/*! + * @brief Selects the signal to output on a PWM pin when a FORCE_OUT signal is asserted. + * + * The user specifies which channel to configure by supplying the submodule number and whether + * to modify PWM A or PWM B within that submodule. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel Channel to configure + * @param mode Signal to output when a FORCE_OUT is triggered + */ +void PWM_SetupForceSignal(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + pwm_force_signal_t mode); + +/*! + * @name Interrupts Interface + * @{ + */ + +/*! + * @brief Enables the selected PWM interrupts + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); + +/*! + * @brief Disables the selected PWM interrupts + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); + +/*! + * @brief Gets the enabled PWM interrupts + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule); + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the PWM status flags + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule); + +/*! + * @brief Clears the PWM status flags + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the PWM counter for a single or multiple submodules. + * + * Sets the Run bit which enables the clocks to the PWM submodule. This function can start multiple + * submodules at the same time. + * + * @param base PWM peripheral base address + * @param subModulesToStart PWM submodules to start. This is a logical OR of members of the + * enumeration ::pwm_module_control_t + */ +static inline void PWM_StartTimer(PWM_Type *base, uint8_t subModulesToStart) +{ + base->MCTRL |= PWM_MCTRL_RUN(subModulesToStart); +} + +/*! + * @brief Stops the PWM counter for a single or multiple submodules. + * + * Clears the Run bit which resets the submodule's counter. This function can stop multiple + * submodules at the same time. + * + * @param base PWM peripheral base address + * @param subModulesToStop PWM submodules to stop. This is a logical OR of members of the + * enumeration ::pwm_module_control_t + */ +static inline void PWM_StopTimer(PWM_Type *base, uint8_t subModulesToStop) +{ + base->MCTRL &= ~(PWM_MCTRL_RUN(subModulesToStop)); +} + +/*! @}*/ + +/*! + * @brief Enables or disables the PWM output trigger. + * + * This function allows the user to enable or disable the PWM trigger. The PWM has 2 triggers. Trigger 0 + * is activated when the counter matches VAL 0, VAL 2, or VAL 4 register. Trigger 1 is activated + * when the counter matches VAL 1, VAL 3, or VAL 5 register. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param valueRegister Value register that will activate the trigger + * @param activate true: Enable the trigger; false: Disable the trigger + */ +static inline void PWM_OutputTriggerEnable(PWM_Type *base, + pwm_submodule_t subModule, + pwm_value_register_t valueRegister, + bool activate) +{ + if (activate) + { + base->SM[subModule].TCTRL |= (1U << valueRegister); + } + else + { + base->SM[subModule].TCTRL &= ~(1U << valueRegister); + } +} + +/*! + * @brief Sets the software control output for a pin to high or low. + * + * The user specifies which channel to modify by supplying the submodule number and whether + * to modify PWM A or PWM B within that submodule. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel Channel to configure + * @param value true: Supply a logic 1, false: Supply a logic 0. + */ +static inline void PWM_SetupSwCtrlOut(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool value) +{ + if (value) + { + base->SWCOUT |= (1U << ((subModule * PWM_SUBMODULE_SWCONTROL_WIDTH) + pwmChannel)); + } + else + { + base->SWCOUT &= ~(1U << ((subModule * PWM_SUBMODULE_SWCONTROL_WIDTH) + pwmChannel)); + } +} + +/*! + * @brief Sets or clears the PWM LDOK bit on a single or multiple submodules + * + * Set LDOK bit to load buffered values into CTRL[PRSC] and the INIT, FRACVAL and VAL registers. The + * values are loaded immediately if kPWM_ReloadImmediate option was choosen during config. Else the + * values are loaded at the next PWM reload point. + * This function can issue the load command to multiple submodules at the same time. + * + * @param base PWM peripheral base address + * @param subModulesToUpdate PWM submodules to update with buffered values. This is a logical OR of + * members of the enumeration ::pwm_module_control_t + * @param value true: Set LDOK bit for the submodule list; false: Clear LDOK bit + */ +static inline void PWM_SetPwmLdok(PWM_Type *base, uint8_t subModulesToUpdate, bool value) +{ + if (value) + { + base->MCTRL |= PWM_MCTRL_LDOK(subModulesToUpdate); + } + else + { + base->MCTRL |= PWM_MCTRL_CLDOK(subModulesToUpdate); + } +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PWM_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_qtmr.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_qtmr.c new file mode 100644 index 0000000000..88294a994f --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_qtmr.c @@ -0,0 +1,592 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_qtmr.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.qtmr" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address to be used to gate or ungate the module clock + * + * @param base Quad Timer peripheral base address + * + * @return The Quad Timer instance + */ +static uint32_t QTMR_GetInstance(TMR_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to Quad Timer bases for each instance. */ +static TMR_Type *const s_qtmrBases[] = TMR_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to Quad Timer clocks for each instance. */ +static const clock_ip_name_t s_qtmrClocks[] = TMR_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t QTMR_GetInstance(TMR_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_qtmrBases); instance++) + { + if (s_qtmrBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_qtmrBases)); + + return instance; +} + +/*! + * brief Ungates the Quad Timer clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the Quad Timer driver. + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * param config Pointer to user's Quad Timer config structure + */ +void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_config_t *config) +{ + assert(config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the module clock */ + CLOCK_EnableClock(s_qtmrClocks[QTMR_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Setup the counter sources */ + base->CHANNEL[channel].CTRL = (TMR_CTRL_PCS(config->primarySource) | TMR_CTRL_SCS(config->secondarySource)); + + /* Setup the master mode operation */ + base->CHANNEL[channel].SCTRL = + (TMR_SCTRL_EEOF(config->enableExternalForce) | TMR_SCTRL_MSTR(config->enableMasterMode)); + + /* Setup debug mode */ + base->CHANNEL[channel].CSCTRL = TMR_CSCTRL_DBG_EN(config->debugMode); + + base->CHANNEL[channel].FILT &= ~(TMR_FILT_FILT_CNT_MASK | TMR_FILT_FILT_PER_MASK); + /* Setup input filter */ + base->CHANNEL[channel].FILT = + (TMR_FILT_FILT_CNT(config->faultFilterCount) | TMR_FILT_FILT_PER(config->faultFilterPeriod)); +} + +/*! + * brief Stops the counter and gates the Quad Timer clock + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + */ +void QTMR_Deinit(TMR_Type *base, qtmr_channel_selection_t channel) +{ + /* Stop the counter */ + base->CHANNEL[channel].CTRL &= ~TMR_CTRL_CM_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the module clock */ + CLOCK_DisableClock(s_qtmrClocks[QTMR_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Fill in the Quad Timer config struct with the default settings + * + * The default values are: + * code + * config->debugMode = kQTMR_RunNormalInDebug; + * config->enableExternalForce = false; + * config->enableMasterMode = false; + * config->faultFilterCount = 0; + * config->faultFilterPeriod = 0; + * config->primarySource = kQTMR_ClockDivide_2; + * config->secondarySource = kQTMR_Counter0InputPin; + * endcode + * param config Pointer to user's Quad Timer config structure. + */ +void QTMR_GetDefaultConfig(qtmr_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + /* Halt counter during debug mode */ + config->debugMode = kQTMR_RunNormalInDebug; + /* Another counter cannot force state of OFLAG signal */ + config->enableExternalForce = false; + /* Compare function's output from this counter is not broadcast to other counters */ + config->enableMasterMode = false; + /* Fault filter count is set to 0 */ + config->faultFilterCount = 0; + /* Fault filter period is set to 0 which disables the fault filter */ + config->faultFilterPeriod = 0; + /* Primary count source is IP bus clock divide by 2 */ + config->primarySource = kQTMR_ClockDivide_2; + /* Secondary count source is counter 0 input pin */ + config->secondarySource = kQTMR_Counter0InputPin; +} + +/*! + * brief Sets up Quad timer module for PWM signal output. + * + * The function initializes the timer module according to the parameters passed in by the user. The + * function also sets up the value compare registers to match the PWM signal requirements. + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * param pwmFreqHz PWM signal frequency in Hz + * param dutyCyclePercent PWM pulse width, value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + * param outputPolarity true: invert polarity of the output signal, false: no inversion + * param srcClock_Hz Main counter clock in Hz. + * + * return Returns an error if there was error setting up the signal. + */ +status_t QTMR_SetupPwm(TMR_Type *base, + qtmr_channel_selection_t channel, + uint32_t pwmFreqHz, + uint8_t dutyCyclePercent, + bool outputPolarity, + uint32_t srcClock_Hz) +{ + uint32_t periodCount, highCount, lowCount, reg; + + if (dutyCyclePercent > 100) + { + /* Invalid dutycycle */ + return kStatus_Fail; + } + + /* Set OFLAG pin for output mode and force out a low on the pin */ + base->CHANNEL[channel].SCTRL |= (TMR_SCTRL_FORCE_MASK | TMR_SCTRL_OEN_MASK); + + /* Counter values to generate a PWM signal */ + periodCount = (srcClock_Hz / pwmFreqHz); + highCount = (periodCount * dutyCyclePercent) / 100; + lowCount = periodCount - highCount; + + /* Setup the compare registers for PWM output */ + base->CHANNEL[channel].COMP1 = lowCount; + base->CHANNEL[channel].COMP2 = highCount; + + /* Setup the pre-load registers for PWM output */ + base->CHANNEL[channel].CMPLD1 = lowCount; + base->CHANNEL[channel].CMPLD2 = highCount; + + reg = base->CHANNEL[channel].CSCTRL; + /* Setup the compare load control for COMP1 and COMP2. + * Load COMP1 when CSCTRL[TCF2] is asserted, load COMP2 when CSCTRL[TCF1] is asserted + */ + reg &= ~(TMR_CSCTRL_CL1_MASK | TMR_CSCTRL_CL2_MASK); + reg |= (TMR_CSCTRL_CL1(kQTMR_LoadOnComp2) | TMR_CSCTRL_CL2(kQTMR_LoadOnComp1)); + base->CHANNEL[channel].CSCTRL = reg; + + if (outputPolarity) + { + /* Invert the polarity */ + base->CHANNEL[channel].SCTRL |= TMR_SCTRL_OPS_MASK; + } + else + { + /* True polarity, no inversion */ + base->CHANNEL[channel].SCTRL &= ~TMR_SCTRL_OPS_MASK; + } + + reg = base->CHANNEL[channel].CTRL; + reg &= ~(TMR_CTRL_OUTMODE_MASK); + /* Count until compare value is reached and re-initialize the counter, toggle OFLAG output + * using alternating compare register + */ + reg |= (TMR_CTRL_LENGTH_MASK | TMR_CTRL_OUTMODE(kQTMR_ToggleOnAltCompareReg)); + base->CHANNEL[channel].CTRL = reg; + + return kStatus_Success; +} + +/*! + * brief Allows the user to count the source clock cycles until a capture event arrives. + * + * The count is stored in the capture register. + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * param capturePin Pin through which we receive the input signal to trigger the capture + * param inputPolarity true: invert polarity of the input signal, false: no inversion + * param reloadOnCapture true: reload the counter when an input capture occurs, false: no reload + * param captureMode Specifies which edge of the input signal triggers a capture + */ +void QTMR_SetupInputCapture(TMR_Type *base, + qtmr_channel_selection_t channel, + qtmr_input_source_t capturePin, + bool inputPolarity, + bool reloadOnCapture, + qtmr_input_capture_edge_t captureMode) +{ + uint16_t reg; + + /* Clear the prior value for the input source for capture */ + reg = base->CHANNEL[channel].CTRL & (~TMR_CTRL_SCS_MASK); + + /* Set the new input source */ + reg |= TMR_CTRL_SCS(capturePin); + base->CHANNEL[channel].CTRL = reg; + + /* Clear the prior values for input polarity, capture mode. Set the external pin as input */ + reg = base->CHANNEL[channel].SCTRL & (~(TMR_SCTRL_IPS_MASK | TMR_SCTRL_CAPTURE_MODE_MASK | TMR_SCTRL_OEN_MASK)); + /* Set the new values */ + reg |= (TMR_SCTRL_IPS(inputPolarity) | TMR_SCTRL_CAPTURE_MODE(captureMode)); + base->CHANNEL[channel].SCTRL = reg; + + /* Setup if counter should reload when a capture occurs */ + if (reloadOnCapture) + { + base->CHANNEL[channel].CSCTRL |= TMR_CSCTRL_ROC_MASK; + } + else + { + base->CHANNEL[channel].CSCTRL &= ~TMR_CSCTRL_ROC_MASK; + } +} + +/*! + * brief Enables the selected Quad Timer interrupts + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::qtmr_interrupt_enable_t + */ +void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) +{ + uint16_t reg; + + reg = base->CHANNEL[channel].SCTRL; + /* Compare interrupt */ + if (mask & kQTMR_CompareInterruptEnable) + { + reg |= TMR_SCTRL_TCFIE_MASK; + } + /* Overflow interrupt */ + if (mask & kQTMR_OverflowInterruptEnable) + { + reg |= TMR_SCTRL_TOFIE_MASK; + } + /* Input edge interrupt */ + if (mask & kQTMR_EdgeInterruptEnable) + { + /* Restriction: Do not set both SCTRL[IEFIE] and DMA[IEFDE] */ + base->CHANNEL[channel].DMA &= ~TMR_DMA_IEFDE_MASK; + reg |= TMR_SCTRL_IEFIE_MASK; + } + base->CHANNEL[channel].SCTRL = reg; + + reg = base->CHANNEL[channel].CSCTRL; + /* Compare 1 interrupt */ + if (mask & kQTMR_Compare1InterruptEnable) + { + reg |= TMR_CSCTRL_TCF1EN_MASK; + } + /* Compare 2 interrupt */ + if (mask & kQTMR_Compare2InterruptEnable) + { + reg |= TMR_CSCTRL_TCF2EN_MASK; + } + base->CHANNEL[channel].CSCTRL = reg; +} + +/*! + * brief Disables the selected Quad Timer interrupts + * + * param base Quad Timer peripheral base addres + * param channel Quad Timer channel number + * param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::qtmr_interrupt_enable_t + */ +void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) +{ + uint16_t reg; + + reg = base->CHANNEL[channel].SCTRL; + /* Compare interrupt */ + if (mask & kQTMR_CompareInterruptEnable) + { + reg &= ~TMR_SCTRL_TCFIE_MASK; + } + /* Overflow interrupt */ + if (mask & kQTMR_OverflowInterruptEnable) + { + reg &= ~TMR_SCTRL_TOFIE_MASK; + } + /* Input edge interrupt */ + if (mask & kQTMR_EdgeInterruptEnable) + { + reg &= ~TMR_SCTRL_IEFIE_MASK; + } + base->CHANNEL[channel].SCTRL = reg; + + reg = base->CHANNEL[channel].CSCTRL; + /* Compare 1 interrupt */ + if (mask & kQTMR_Compare1InterruptEnable) + { + reg &= ~TMR_CSCTRL_TCF1EN_MASK; + } + /* Compare 2 interrupt */ + if (mask & kQTMR_Compare2InterruptEnable) + { + reg &= ~TMR_CSCTRL_TCF2EN_MASK; + } + base->CHANNEL[channel].CSCTRL = reg; +} + +/*! + * brief Gets the enabled Quad Timer interrupts + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * + * return The enabled interrupts. This is the logical OR of members of the + * enumeration ::qtmr_interrupt_enable_t + */ +uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t channel) +{ + uint32_t enabledInterrupts = 0; + uint16_t reg; + + reg = base->CHANNEL[channel].SCTRL; + /* Compare interrupt */ + if (reg & TMR_SCTRL_TCFIE_MASK) + { + enabledInterrupts |= kQTMR_CompareFlag; + } + /* Overflow interrupt */ + if (reg & TMR_SCTRL_TOFIE_MASK) + { + enabledInterrupts |= kQTMR_OverflowInterruptEnable; + } + /* Input edge interrupt */ + if (reg & TMR_SCTRL_IEFIE_MASK) + { + enabledInterrupts |= kQTMR_EdgeInterruptEnable; + } + + reg = base->CHANNEL[channel].CSCTRL; + /* Compare 1 interrupt */ + if (reg & TMR_CSCTRL_TCF1EN_MASK) + { + enabledInterrupts |= kQTMR_Compare1InterruptEnable; + } + /* Compare 2 interrupt */ + if (reg & TMR_CSCTRL_TCF2EN_MASK) + { + enabledInterrupts |= kQTMR_Compare2InterruptEnable; + } + + return enabledInterrupts; +} + +/*! + * brief Gets the Quad Timer status flags + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * + * return The status flags. This is the logical OR of members of the + * enumeration ::qtmr_status_flags_t + */ +uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel) +{ + uint32_t statusFlags = 0; + uint16_t reg; + + reg = base->CHANNEL[channel].SCTRL; + /* Timer compare flag */ + if (reg & TMR_SCTRL_TCF_MASK) + { + statusFlags |= kQTMR_CompareFlag; + } + /* Timer overflow flag */ + if (reg & TMR_SCTRL_TOF_MASK) + { + statusFlags |= kQTMR_OverflowFlag; + } + /* Input edge flag */ + if (reg & TMR_SCTRL_IEF_MASK) + { + statusFlags |= kQTMR_EdgeFlag; + } + + reg = base->CHANNEL[channel].CSCTRL; + /* Compare 1 flag */ + if (reg & TMR_CSCTRL_TCF1_MASK) + { + statusFlags |= kQTMR_Compare1Flag; + } + /* Compare 2 flag */ + if (reg & TMR_CSCTRL_TCF2_MASK) + { + statusFlags |= kQTMR_Compare2Flag; + } + + return statusFlags; +} + +/*! + * brief Clears the Quad Timer status flags. + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::qtmr_status_flags_t + */ +void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) +{ + uint16_t reg; + + reg = base->CHANNEL[channel].SCTRL; + /* Timer compare flag */ + if (mask & kQTMR_CompareFlag) + { + reg &= ~TMR_SCTRL_TCF_MASK; + } + /* Timer overflow flag */ + if (mask & kQTMR_OverflowFlag) + { + reg &= ~TMR_SCTRL_TOF_MASK; + } + /* Input edge flag */ + if (mask & kQTMR_EdgeFlag) + { + reg &= ~TMR_SCTRL_IEF_MASK; + } + base->CHANNEL[channel].SCTRL = reg; + + reg = base->CHANNEL[channel].CSCTRL; + /* Compare 1 flag */ + if (mask & kQTMR_Compare1Flag) + { + reg &= ~TMR_CSCTRL_TCF1_MASK; + } + /* Compare 2 flag */ + if (mask & kQTMR_Compare2Flag) + { + reg &= ~TMR_CSCTRL_TCF2_MASK; + } + base->CHANNEL[channel].CSCTRL = reg; +} + +/*! + * brief Sets the timer period in ticks. + * + * Timers counts from initial value till it equals the count value set here. The counter + * will then reinitialize to the value specified in the Load register. + * + * note + * 1. This function will write the time period in ticks to COMP1 or COMP2 register + * depending on the count direction + * 2. User can call the utility macros provided in fsl_common.h to convert to ticks + * 3. This function supports cases, providing only primary source clock without secondary source clock. + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * param ticks Timer period in units of ticks + */ +void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks) +{ + /* Set the length bit to reinitialize the counters on a match */ + base->CHANNEL[channel].CTRL |= TMR_CTRL_LENGTH_MASK; + + if (base->CHANNEL[channel].CTRL & TMR_CTRL_DIR_MASK) + { + /* Counting down */ + base->CHANNEL[channel].COMP2 = ticks; + } + else + { + /* Counting up */ + base->CHANNEL[channel].COMP1 = ticks; + } +} + +/*! + * brief Enable the Quad Timer DMA. + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * param mask The DMA to enable. This is a logical OR of members of the + * enumeration ::qtmr_dma_enable_t + */ +void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) +{ + uint16_t reg; + + reg = base->CHANNEL[channel].DMA; + /* Input Edge Flag DMA Enable */ + if (mask & kQTMR_InputEdgeFlagDmaEnable) + { + /* Restriction: Do not set both DMA[IEFDE] and SCTRL[IEFIE] */ + base->CHANNEL[channel].SCTRL &= ~TMR_SCTRL_IEFIE_MASK; + reg |= TMR_DMA_IEFDE_MASK; + } + /* Comparator Preload Register 1 DMA Enable */ + if (mask & kQTMR_ComparatorPreload1DmaEnable) + { + reg |= TMR_DMA_CMPLD1DE_MASK; + } + /* Comparator Preload Register 2 DMA Enable */ + if (mask & kQTMR_ComparatorPreload2DmaEnable) + { + reg |= TMR_DMA_CMPLD2DE_MASK; + } + base->CHANNEL[channel].DMA = reg; +} + +/*! + * brief Disable the Quad Timer DMA. + * + * param base Quad Timer peripheral base address + * param channel Quad Timer channel number + * param mask The DMA to enable. This is a logical OR of members of the + * enumeration ::qtmr_dma_enable_t + */ +void QTMR_DisableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask) +{ + uint16_t reg; + + reg = base->CHANNEL[channel].DMA; + /* Input Edge Flag DMA Enable */ + if (mask & kQTMR_InputEdgeFlagDmaEnable) + { + reg &= ~TMR_DMA_IEFDE_MASK; + } + /* Comparator Preload Register 1 DMA Enable */ + if (mask & kQTMR_ComparatorPreload1DmaEnable) + { + reg &= ~TMR_DMA_CMPLD1DE_MASK; + } + /* Comparator Preload Register 2 DMA Enable */ + if (mask & kQTMR_ComparatorPreload2DmaEnable) + { + reg &= ~TMR_DMA_CMPLD2DE_MASK; + } + base->CHANNEL[channel].DMA = reg; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_qtmr.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_qtmr.h new file mode 100644 index 0000000000..26d1204ebb --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_qtmr.h @@ -0,0 +1,438 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_QTMR_H_ +#define _FSL_QTMR_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup qtmr + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_QTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief Quad Timer primary clock source selection*/ +typedef enum _qtmr_primary_count_source +{ + kQTMR_ClockCounter0InputPin = 0, /*!< Use counter 0 input pin */ + kQTMR_ClockCounter1InputPin, /*!< Use counter 1 input pin */ + kQTMR_ClockCounter2InputPin, /*!< Use counter 2 input pin */ + kQTMR_ClockCounter3InputPin, /*!< Use counter 3 input pin */ + kQTMR_ClockCounter0Output, /*!< Use counter 0 output */ + kQTMR_ClockCounter1Output, /*!< Use counter 1 output */ + kQTMR_ClockCounter2Output, /*!< Use counter 2 output */ + kQTMR_ClockCounter3Output, /*!< Use counter 3 output */ + kQTMR_ClockDivide_1, /*!< IP bus clock divide by 1 prescaler */ + kQTMR_ClockDivide_2, /*!< IP bus clock divide by 2 prescaler */ + kQTMR_ClockDivide_4, /*!< IP bus clock divide by 4 prescaler */ + kQTMR_ClockDivide_8, /*!< IP bus clock divide by 8 prescaler */ + kQTMR_ClockDivide_16, /*!< IP bus clock divide by 16 prescaler */ + kQTMR_ClockDivide_32, /*!< IP bus clock divide by 32 prescaler */ + kQTMR_ClockDivide_64, /*!< IP bus clock divide by 64 prescaler */ + kQTMR_ClockDivide_128 /*!< IP bus clock divide by 128 prescaler */ +} qtmr_primary_count_source_t; + +/*! @brief Quad Timer input sources selection*/ +typedef enum _qtmr_input_source +{ + kQTMR_Counter0InputPin = 0, /*!< Use counter 0 input pin */ + kQTMR_Counter1InputPin, /*!< Use counter 1 input pin */ + kQTMR_Counter2InputPin, /*!< Use counter 2 input pin */ + kQTMR_Counter3InputPin /*!< Use counter 3 input pin */ +} qtmr_input_source_t; + +/*! @brief Quad Timer counting mode selection */ +typedef enum _qtmr_counting_mode +{ + kQTMR_NoOperation = 0, /*!< No operation */ + kQTMR_PriSrcRiseEdge, /*!< Count rising edges or primary source */ + kQTMR_PriSrcRiseAndFallEdge, /*!< Count rising and falling edges of primary source */ + kQTMR_PriSrcRiseEdgeSecInpHigh, /*!< Count rise edges of pri SRC while sec inp high active */ + kQTMR_QuadCountMode, /*!< Quadrature count mode, uses pri and sec sources */ + kQTMR_PriSrcRiseEdgeSecDir, /*!< Count rising edges of pri SRC; sec SRC specifies dir */ + kQTMR_SecSrcTrigPriCnt, /*!< Edge of sec SRC trigger primary count until compare*/ + kQTMR_CascadeCount /*!< Cascaded count mode (up/down) */ +} qtmr_counting_mode_t; + +/*! @brief Quad Timer output mode selection*/ +typedef enum _qtmr_output_mode +{ + kQTMR_AssertWhenCountActive = 0, /*!< Assert OFLAG while counter is active*/ + kQTMR_ClearOnCompare, /*!< Clear OFLAG on successful compare */ + kQTMR_SetOnCompare, /*!< Set OFLAG on successful compare */ + kQTMR_ToggleOnCompare, /*!< Toggle OFLAG on successful compare */ + kQTMR_ToggleOnAltCompareReg, /*!< Toggle OFLAG using alternating compare registers */ + kQTMR_SetOnCompareClearOnSecSrcInp, /*!< Set OFLAG on compare, clear on sec SRC input edge */ + kQTMR_SetOnCompareClearOnCountRoll, /*!< Set OFLAG on compare, clear on counter rollover */ + kQTMR_EnableGateClock /*!< Enable gated clock output while count is active */ +} qtmr_output_mode_t; + +/*! @brief Quad Timer input capture edge mode, rising edge, or falling edge */ +typedef enum _qtmr_input_capture_edge +{ + kQTMR_NoCapture = 0, /*!< Capture is disabled */ + kQTMR_RisingEdge, /*!< Capture on rising edge (IPS=0) or falling edge (IPS=1)*/ + kQTMR_FallingEdge, /*!< Capture on falling edge (IPS=0) or rising edge (IPS=1)*/ + kQTMR_RisingAndFallingEdge /*!< Capture on both edges */ +} qtmr_input_capture_edge_t; + +/*! @brief Quad Timer input capture edge mode, rising edge, or falling edge */ +typedef enum _qtmr_preload_control +{ + kQTMR_NoPreload = 0, /*!< Never preload */ + kQTMR_LoadOnComp1, /*!< Load upon successful compare with value in COMP1 */ + kQTMR_LoadOnComp2 /*!< Load upon successful compare with value in COMP2*/ +} qtmr_preload_control_t; + +/*! @brief List of Quad Timer run options when in Debug mode */ +typedef enum _qtmr_debug_action +{ + kQTMR_RunNormalInDebug = 0U, /*!< Continue with normal operation */ + kQTMR_HaltCounter, /*!< Halt counter */ + kQTMR_ForceOutToZero, /*!< Force output to logic 0 */ + kQTMR_HaltCountForceOutZero /*!< Halt counter and force output to logic 0 */ +} qtmr_debug_action_t; + +/*! @brief List of Quad Timer interrupts */ +typedef enum _qtmr_interrupt_enable +{ + kQTMR_CompareInterruptEnable = (1U << 0), /*!< Compare interrupt.*/ + kQTMR_Compare1InterruptEnable = (1U << 1), /*!< Compare 1 interrupt.*/ + kQTMR_Compare2InterruptEnable = (1U << 2), /*!< Compare 2 interrupt.*/ + kQTMR_OverflowInterruptEnable = (1U << 3), /*!< Timer overflow interrupt.*/ + kQTMR_EdgeInterruptEnable = (1U << 4) /*!< Input edge interrupt.*/ +} qtmr_interrupt_enable_t; + +/*! @brief List of Quad Timer flags */ +typedef enum _qtmr_status_flags +{ + kQTMR_CompareFlag = (1U << 0), /*!< Compare flag */ + kQTMR_Compare1Flag = (1U << 1), /*!< Compare 1 flag */ + kQTMR_Compare2Flag = (1U << 2), /*!< Compare 2 flag */ + kQTMR_OverflowFlag = (1U << 3), /*!< Timer overflow flag */ + kQTMR_EdgeFlag = (1U << 4) /*!< Input edge flag */ +} qtmr_status_flags_t; + +/*! @brief List of channel selection */ +typedef enum _qtmr_channel_selection +{ + kQTMR_Channel_0 = 0U, /*!< TMR Channel 0 */ + kQTMR_Channel_1, /*!< TMR Channel 1 */ + kQTMR_Channel_2, /*!< TMR Channel 2 */ + kQTMR_Channel_3, /*!< TMR Channel 3 */ +} qtmr_channel_selection_t; + +/*! @brief List of Quad Timer DMA enable */ +typedef enum _qtmr_dma_enable +{ + kQTMR_InputEdgeFlagDmaEnable = (1U << 0), /*!< Input Edge Flag DMA Enable.*/ + kQTMR_ComparatorPreload1DmaEnable = (1U << 1), /*!< Comparator Preload Register 1 DMA Enable.*/ + kQTMR_ComparatorPreload2DmaEnable = (1U << 2), /*!< Comparator Preload Register 2 DMA Enable.*/ +} qtmr_dma_enable_t; + +/*! + * @brief Quad Timer config structure + * + * This structure holds the configuration settings for the Quad Timer peripheral. To initialize this + * structure to reasonable defaults, call the QTMR_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _qtmr_config +{ + qtmr_primary_count_source_t primarySource; /*!< Specify the primary count source */ + qtmr_input_source_t secondarySource; /*!< Specify the secondary count source */ + bool enableMasterMode; /*!< true: Broadcast compare function output to other counters; + false no broadcast */ + bool enableExternalForce; /*!< true: Compare from another counter force state of OFLAG signal + false: OFLAG controlled by local counter */ + uint8_t faultFilterCount; /*!< Fault filter count */ + uint8_t faultFilterPeriod; /*!< Fault filter period;value of 0 will bypass the filter */ + qtmr_debug_action_t debugMode; /*!< Operation in Debug mode */ +} qtmr_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the Quad Timer clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the Quad Timer driver. + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param config Pointer to user's Quad Timer config structure + */ +void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_config_t *config); + +/*! + * @brief Stops the counter and gates the Quad Timer clock + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + */ +void QTMR_Deinit(TMR_Type *base, qtmr_channel_selection_t channel); + +/*! + * @brief Fill in the Quad Timer config struct with the default settings + * + * The default values are: + * @code + * config->debugMode = kQTMR_RunNormalInDebug; + * config->enableExternalForce = false; + * config->enableMasterMode = false; + * config->faultFilterCount = 0; + * config->faultFilterPeriod = 0; + * config->primarySource = kQTMR_ClockDivide_2; + * config->secondarySource = kQTMR_Counter0InputPin; + * @endcode + * @param config Pointer to user's Quad Timer config structure. + */ +void QTMR_GetDefaultConfig(qtmr_config_t *config); + +/*! @}*/ + +/*! + * @brief Sets up Quad timer module for PWM signal output. + * + * The function initializes the timer module according to the parameters passed in by the user. The + * function also sets up the value compare registers to match the PWM signal requirements. + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param pwmFreqHz PWM signal frequency in Hz + * @param dutyCyclePercent PWM pulse width, value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + * @param outputPolarity true: invert polarity of the output signal, false: no inversion + * @param srcClock_Hz Main counter clock in Hz. + * + * @return Returns an error if there was error setting up the signal. + */ +status_t QTMR_SetupPwm(TMR_Type *base, + qtmr_channel_selection_t channel, + uint32_t pwmFreqHz, + uint8_t dutyCyclePercent, + bool outputPolarity, + uint32_t srcClock_Hz); + +/*! + * @brief Allows the user to count the source clock cycles until a capture event arrives. + * + * The count is stored in the capture register. + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param capturePin Pin through which we receive the input signal to trigger the capture + * @param inputPolarity true: invert polarity of the input signal, false: no inversion + * @param reloadOnCapture true: reload the counter when an input capture occurs, false: no reload + * @param captureMode Specifies which edge of the input signal triggers a capture + */ +void QTMR_SetupInputCapture(TMR_Type *base, + qtmr_channel_selection_t channel, + qtmr_input_source_t capturePin, + bool inputPolarity, + bool reloadOnCapture, + qtmr_input_capture_edge_t captureMode); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected Quad Timer interrupts + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::qtmr_interrupt_enable_t + */ +void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask); + +/*! + * @brief Disables the selected Quad Timer interrupts + * + * @param base Quad Timer peripheral base addres + * @param channel Quad Timer channel number + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::qtmr_interrupt_enable_t + */ +void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask); + +/*! + * @brief Gets the enabled Quad Timer interrupts + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::qtmr_interrupt_enable_t + */ +uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t channel); + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the Quad Timer status flags + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::qtmr_status_flags_t + */ +uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel); + +/*! + * @brief Clears the Quad Timer status flags. + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::qtmr_status_flags_t + */ +void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask); + +/*! @}*/ + +/*! + * @name Read and Write the timer period + * @{ + */ + +/*! + * @brief Sets the timer period in ticks. + * + * Timers counts from initial value till it equals the count value set here. The counter + * will then reinitialize to the value specified in the Load register. + * + * @note + * 1. This function will write the time period in ticks to COMP1 or COMP2 register + * depending on the count direction + * 2. User can call the utility macros provided in fsl_common.h to convert to ticks + * 3. This function supports cases, providing only primary source clock without secondary source clock. + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param ticks Timer period in units of ticks + */ +void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks); + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * + * @return Current counter value in ticks + */ +static inline uint16_t QTMR_GetCurrentTimerCount(TMR_Type *base, qtmr_channel_selection_t channel) +{ + return base->CHANNEL[channel].CNTR; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the Quad Timer counter. + * + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param clockSource Quad Timer clock source + */ +static inline void QTMR_StartTimer(TMR_Type *base, qtmr_channel_selection_t channel, qtmr_counting_mode_t clockSource) +{ + uint16_t reg = base->CHANNEL[channel].CTRL; + + reg &= ~(TMR_CTRL_CM_MASK); + reg |= TMR_CTRL_CM(clockSource); + base->CHANNEL[channel].CTRL = reg; +} + +/*! + * @brief Stops the Quad Timer counter. + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + */ +static inline void QTMR_StopTimer(TMR_Type *base, qtmr_channel_selection_t channel) +{ + base->CHANNEL[channel].CTRL &= ~TMR_CTRL_CM_MASK; +} + +/*! @}*/ + +/*! + * @name Enable and Disable the Quad Timer DMA + * @{ + */ + +/*! + * @brief Enable the Quad Timer DMA. + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param mask The DMA to enable. This is a logical OR of members of the + * enumeration ::qtmr_dma_enable_t + */ +void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask); + +/*! + * @brief Disable the Quad Timer DMA. + * + * @param base Quad Timer peripheral base address + * @param channel Quad Timer channel number + * @param mask The DMA to enable. This is a logical OR of members of the + * enumeration ::qtmr_dma_enable_t + */ +void QTMR_DisableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_QTMR_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_rtwdog.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_rtwdog.c new file mode 100644 index 0000000000..9a32bd8064 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_rtwdog.c @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_rtwdog.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.rtwdog" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Clears the RTWDOG flag. + * + * This function clears the RTWDOG status flag. + * + * Example to clear an interrupt flag: + * code + * RTWDOG_ClearStatusFlags(wdog_base,kRTWDOG_InterruptFlag); + * endcode + * param base RTWDOG peripheral base address. + * param mask The status flags to clear. + * The parameter can be any combination of the following values: + * arg kRTWDOG_InterruptFlag + */ +void RTWDOG_ClearStatusFlags(RTWDOG_Type *base, uint32_t mask) +{ + if (mask & kRTWDOG_InterruptFlag) + { + base->CS |= RTWDOG_CS_FLG_MASK; + } +} + +/*! + * brief Initializes the RTWDOG configuration structure. + * + * This function initializes the RTWDOG configuration structure to default values. The default + * values are: + * code + * rtwdogConfig->enableRtwdog = true; + * rtwdogConfig->clockSource = kRTWDOG_ClockSource1; + * rtwdogConfig->prescaler = kRTWDOG_ClockPrescalerDivide1; + * rtwdogConfig->workMode.enableWait = true; + * rtwdogConfig->workMode.enableStop = false; + * rtwdogConfig->workMode.enableDebug = false; + * rtwdogConfig->testMode = kRTWDOG_TestModeDisabled; + * rtwdogConfig->enableUpdate = true; + * rtwdogConfig->enableInterrupt = false; + * rtwdogConfig->enableWindowMode = false; + * rtwdogConfig->windowValue = 0U; + * rtwdogConfig->timeoutValue = 0xFFFFU; + * endcode + * + * param config Pointer to the RTWDOG configuration structure. + * see rtwdog_config_t + */ +void RTWDOG_GetDefaultConfig(rtwdog_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->enableRtwdog = true; + config->clockSource = kRTWDOG_ClockSource1; + config->prescaler = kRTWDOG_ClockPrescalerDivide1; + config->workMode.enableWait = true; + config->workMode.enableStop = false; + config->workMode.enableDebug = false; + config->testMode = kRTWDOG_TestModeDisabled; + config->enableUpdate = true; + config->enableInterrupt = false; + config->enableWindowMode = false; + config->windowValue = 0U; + config->timeoutValue = 0xFFFFU; +} + +/*! + * brief Initializes the RTWDOG module. + * + * This function initializes the RTWDOG. + * To reconfigure the RTWDOG without forcing a reset first, enableUpdate must be set to true + * in the configuration. + * + * Example: + * code + * rtwdog_config_t config; + * RTWDOG_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * config.enableUpdate = true; + * RTWDOG_Init(wdog_base,&config); + * endcode + * + * param base RTWDOG peripheral base address. + * param config The configuration of the RTWDOG. + */ +void RTWDOG_Init(RTWDOG_Type *base, const rtwdog_config_t *config) +{ + assert(config); + + uint32_t value = 0U; + uint32_t primaskValue = 0U; + + value = RTWDOG_CS_EN(config->enableRtwdog) | RTWDOG_CS_CLK(config->clockSource) | + RTWDOG_CS_INT(config->enableInterrupt) | RTWDOG_CS_WIN(config->enableWindowMode) | + RTWDOG_CS_UPDATE(config->enableUpdate) | RTWDOG_CS_DBG(config->workMode.enableDebug) | + RTWDOG_CS_STOP(config->workMode.enableStop) | RTWDOG_CS_WAIT(config->workMode.enableWait) | + RTWDOG_CS_PRES(config->prescaler) | RTWDOG_CS_CMD32EN(true) | RTWDOG_CS_TST(config->testMode); + + /* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence + * and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */ + primaskValue = DisableGlobalIRQ(); + RTWDOG_Unlock(base); + base->WIN = config->windowValue; + base->TOVAL = config->timeoutValue; + base->CS = value; + while ((base->CS & RTWDOG_CS_RCS_MASK) == 0) + { + } + EnableGlobalIRQ(primaskValue); +} + +/*! + * brief De-initializes the RTWDOG module. + * + * This function shuts down the RTWDOG. + * Ensure that the WDOG_CS.UPDATE is 1, which means that the register update is enabled. + * + * param base RTWDOG peripheral base address. + */ +void RTWDOG_Deinit(RTWDOG_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupts */ + primaskValue = DisableGlobalIRQ(); + RTWDOG_Unlock(base); + RTWDOG_Disable(base); + EnableGlobalIRQ(primaskValue); +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_rtwdog.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_rtwdog.h new file mode 100644 index 0000000000..b1a708fc80 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_rtwdog.h @@ -0,0 +1,420 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_RTWDOG_H_ +#define _FSL_RTWDOG_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup rtwdog + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ +/*! @name Unlock sequence */ +/*@{*/ +#define WDOG_FIRST_WORD_OF_UNLOCK (RTWDOG_UPDATE_KEY & 0xFFFFU) /*!< First word of unlock sequence */ +#define WDOG_SECOND_WORD_OF_UNLOCK ((RTWDOG_UPDATE_KEY >> 16U) & 0xFFFFU) /*!< Second word of unlock sequence */ +/*@}*/ + +/*! @name Refresh sequence */ +/*@{*/ +#define WDOG_FIRST_WORD_OF_REFRESH (RTWDOG_REFRESH_KEY & 0xFFFFU) /*!< First word of refresh sequence */ +#define WDOG_SECOND_WORD_OF_REFRESH ((RTWDOG_REFRESH_KEY >> 16U) & 0xFFFFU) /*!< Second word of refresh sequence */ +/*@}*/ +/*! @name Driver version */ +/*@{*/ +/*! @brief RTWDOG driver version 2.1.0. */ +#define FSL_RTWDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief Describes RTWDOG clock source. */ +typedef enum _rtwdog_clock_source +{ + kRTWDOG_ClockSource0 = 0U, /*!< Clock source 0 */ + kRTWDOG_ClockSource1 = 1U, /*!< Clock source 1 */ + kRTWDOG_ClockSource2 = 2U, /*!< Clock source 2 */ + kRTWDOG_ClockSource3 = 3U, /*!< Clock source 3 */ +} rtwdog_clock_source_t; + +/*! @brief Describes the selection of the clock prescaler. */ +typedef enum _rtwdog_clock_prescaler +{ + kRTWDOG_ClockPrescalerDivide1 = 0x0U, /*!< Divided by 1 */ + kRTWDOG_ClockPrescalerDivide256 = 0x1U, /*!< Divided by 256 */ +} rtwdog_clock_prescaler_t; + +/*! @brief Defines RTWDOG work mode. */ +typedef struct _rtwdog_work_mode +{ + bool enableWait; /*!< Enables or disables RTWDOG in wait mode */ + bool enableStop; /*!< Enables or disables RTWDOG in stop mode */ + bool enableDebug; /*!< Enables or disables RTWDOG in debug mode */ +} rtwdog_work_mode_t; + +/*! @brief Describes RTWDOG test mode. */ +typedef enum _rtwdog_test_mode +{ + kRTWDOG_TestModeDisabled = 0U, /*!< Test Mode disabled */ + kRTWDOG_UserModeEnabled = 1U, /*!< User Mode enabled */ + kRTWDOG_LowByteTest = 2U, /*!< Test Mode enabled, only low byte is used */ + kRTWDOG_HighByteTest = 3U, /*!< Test Mode enabled, only high byte is used */ +} rtwdog_test_mode_t; + +/*! @brief Describes RTWDOG configuration structure. */ +typedef struct _rtwdog_config +{ + bool enableRtwdog; /*!< Enables or disables RTWDOG */ + rtwdog_clock_source_t clockSource; /*!< Clock source select */ + rtwdog_clock_prescaler_t prescaler; /*!< Clock prescaler value */ + rtwdog_work_mode_t workMode; /*!< Configures RTWDOG work mode in debug stop and wait mode */ + rtwdog_test_mode_t testMode; /*!< Configures RTWDOG test mode */ + bool enableUpdate; /*!< Update write-once register enable */ + bool enableInterrupt; /*!< Enables or disables RTWDOG interrupt */ + bool enableWindowMode; /*!< Enables or disables RTWDOG window mode */ + uint16_t windowValue; /*!< Window value */ + uint16_t timeoutValue; /*!< Timeout value */ +} rtwdog_config_t; + +/*! + * @brief RTWDOG interrupt configuration structure. + * + * This structure contains the settings for all of the RTWDOG interrupt configurations. + */ +enum _rtwdog_interrupt_enable_t +{ + kRTWDOG_InterruptEnable = RTWDOG_CS_INT_MASK, /*!< Interrupt is generated before forcing a reset */ +}; + +/*! + * @brief RTWDOG status flags. + * + * This structure contains the RTWDOG status flags for use in the RTWDOG functions. + */ +enum _rtwdog_status_flags_t +{ + kRTWDOG_RunningFlag = RTWDOG_CS_EN_MASK, /*!< Running flag, set when RTWDOG is enabled */ + kRTWDOG_InterruptFlag = RTWDOG_CS_FLG_MASK, /*!< Interrupt flag, set when interrupt occurs */ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name RTWDOG Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes the RTWDOG configuration structure. + * + * This function initializes the RTWDOG configuration structure to default values. The default + * values are: + * @code + * rtwdogConfig->enableRtwdog = true; + * rtwdogConfig->clockSource = kRTWDOG_ClockSource1; + * rtwdogConfig->prescaler = kRTWDOG_ClockPrescalerDivide1; + * rtwdogConfig->workMode.enableWait = true; + * rtwdogConfig->workMode.enableStop = false; + * rtwdogConfig->workMode.enableDebug = false; + * rtwdogConfig->testMode = kRTWDOG_TestModeDisabled; + * rtwdogConfig->enableUpdate = true; + * rtwdogConfig->enableInterrupt = false; + * rtwdogConfig->enableWindowMode = false; + * rtwdogConfig->windowValue = 0U; + * rtwdogConfig->timeoutValue = 0xFFFFU; + * @endcode + * + * @param config Pointer to the RTWDOG configuration structure. + * @see rtwdog_config_t + */ +void RTWDOG_GetDefaultConfig(rtwdog_config_t *config); + +/*! + * @brief Initializes the RTWDOG module. + * + * This function initializes the RTWDOG. + * To reconfigure the RTWDOG without forcing a reset first, enableUpdate must be set to true + * in the configuration. + * + * Example: + * @code + * rtwdog_config_t config; + * RTWDOG_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * config.enableUpdate = true; + * RTWDOG_Init(wdog_base,&config); + * @endcode + * + * @param base RTWDOG peripheral base address. + * @param config The configuration of the RTWDOG. + */ +AT_QUICKACCESS_SECTION_CODE(void RTWDOG_Init(RTWDOG_Type *base, const rtwdog_config_t *config)); + +/*! + * @brief De-initializes the RTWDOG module. + * + * This function shuts down the RTWDOG. + * Ensure that the WDOG_CS.UPDATE is 1, which means that the register update is enabled. + * + * @param base RTWDOG peripheral base address. + */ +void RTWDOG_Deinit(RTWDOG_Type *base); + +/* @} */ + +/*! + * @name RTWDOG functional Operation + * @{ + */ + +/*! + * @brief Enables the RTWDOG module. + * + * This function writes a value into the WDOG_CS register to enable the RTWDOG. + * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and + * this register has not been written in this WCT while the function is called. + * + * @param base RTWDOG peripheral base address. + */ +static inline void RTWDOG_Enable(RTWDOG_Type *base) +{ + base->CS |= RTWDOG_CS_EN_MASK; +} + +/*! + * @brief Disables the RTWDOG module. + * + * This function writes a value into the WDOG_CS register to disable the RTWDOG. + * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and + * this register has not been written in this WCT while the function is called. + * + * @param base RTWDOG peripheral base address + */ +static inline void RTWDOG_Disable(RTWDOG_Type *base) +{ + base->CS &= ~RTWDOG_CS_EN_MASK; +} + +/*! + * @brief Enables the RTWDOG interrupt. + * + * This function writes a value into the WDOG_CS register to enable the RTWDOG interrupt. + * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and + * this register has not been written in this WCT while the function is called. + * + * @param base RTWDOG peripheral base address. + * @param mask The interrupts to enable. + * The parameter can be a combination of the following source if defined: + * @arg kRTWDOG_InterruptEnable + */ +static inline void RTWDOG_EnableInterrupts(RTWDOG_Type *base, uint32_t mask) +{ + base->CS |= mask; +} + +/*! + * @brief Disables the RTWDOG interrupt. + * + * This function writes a value into the WDOG_CS register to disable the RTWDOG interrupt. + * The WDOG_CS register is a write-once register. Ensure that the WCT window is still open and + * this register has not been written in this WCT while the function is called. + * + * @param base RTWDOG peripheral base address. + * @param mask The interrupts to disabled. + * The parameter can be a combination of the following source if defined: + * @arg kRTWDOG_InterruptEnable + */ +static inline void RTWDOG_DisableInterrupts(RTWDOG_Type *base, uint32_t mask) +{ + base->CS &= ~mask; +} + +/*! + * @brief Gets the RTWDOG all status flags. + * + * This function gets all status flags. + * + * Example to get the running flag: + * @code + * uint32_t status; + * status = RTWDOG_GetStatusFlags(wdog_base) & kRTWDOG_RunningFlag; + * @endcode + * @param base RTWDOG peripheral base address + * @return State of the status flag: asserted (true) or not-asserted (false). @see _rtwdog_status_flags_t + * - true: related status flag has been set. + * - false: related status flag is not set. + */ +static inline uint32_t RTWDOG_GetStatusFlags(RTWDOG_Type *base) +{ + return (base->CS & (RTWDOG_CS_EN_MASK | RTWDOG_CS_FLG_MASK)); +} + +/*! + * @brief Enables/disables the window mode. + * + * @param base RTWDOG peripheral base address. + * @param enable Enables(true) or disables(false) the feature. + */ +static inline void RTWDOG_EnableWindowMode(RTWDOG_Type *base, bool enable) +{ + if (enable) + { + base->CS |= RTWDOG_CS_WIN_MASK; + } + else + { + base->CS &= ~RTWDOG_CS_WIN_MASK; + } +} + +/*! + * @brief Converts raw count value to millisecond. + * + * Note that if the clock frequency is too high the timeout period can be less than 1 ms. + * In this case this api will return 0 value. + * + * @param base RTWDOG peripheral base address. + * @param count Raw count value. + # @param clockFreqInHz The frequency of the clock source RTWDOG uses. + */ +static inline uint32_t RTWDOG_CountToMesec(RTWDOG_Type *base, uint32_t count, uint32_t clockFreqInHz) +{ + if ((base->CS & RTWDOG_CS_PRES_MASK) >> RTWDOG_CS_PRES_SHIFT) + { + clockFreqInHz /= 256; + } + return count * 1000U / clockFreqInHz; +} + +/*! + * @brief Clears the RTWDOG flag. + * + * This function clears the RTWDOG status flag. + * + * Example to clear an interrupt flag: + * @code + * RTWDOG_ClearStatusFlags(wdog_base,kRTWDOG_InterruptFlag); + * @endcode + * @param base RTWDOG peripheral base address. + * @param mask The status flags to clear. + * The parameter can be any combination of the following values: + * @arg kRTWDOG_InterruptFlag + */ +void RTWDOG_ClearStatusFlags(RTWDOG_Type *base, uint32_t mask); + +/*! + * @brief Sets the RTWDOG timeout value. + * + * This function writes a timeout value into the WDOG_TOVAL register. + * The WDOG_TOVAL register is a write-once register. Ensure that the WCT window is still open and + * this register has not been written in this WCT while the function is called. + * + * @param base RTWDOG peripheral base address + * @param timeoutCount RTWDOG timeout value, count of RTWDOG clock ticks. + */ +static inline void RTWDOG_SetTimeoutValue(RTWDOG_Type *base, uint16_t timeoutCount) +{ + base->TOVAL = timeoutCount; +} + +/*! + * @brief Sets the RTWDOG window value. + * + * This function writes a window value into the WDOG_WIN register. + * The WDOG_WIN register is a write-once register. Ensure that the WCT window is still open and + * this register has not been written in this WCT while the function is called. + * + * @param base RTWDOG peripheral base address. + * @param windowValue RTWDOG window value. + */ +static inline void RTWDOG_SetWindowValue(RTWDOG_Type *base, uint16_t windowValue) +{ + base->WIN = windowValue; +} + +/*! + * @brief Unlocks the RTWDOG register written. + * + * This function unlocks the RTWDOG register written. + * + * Before starting the unlock sequence and following the configuration, disable the global interrupts. + * Otherwise, an interrupt could effectively invalidate the unlock sequence and the WCT may expire. + * After the configuration finishes, re-enable the global interrupts. + * + * @param base RTWDOG peripheral base address + */ +static inline void RTWDOG_Unlock(RTWDOG_Type *base) +{ + if ((base->CS) & RTWDOG_CS_CMD32EN_MASK) + { + base->CNT = RTWDOG_UPDATE_KEY; + } + else + { + base->CNT = WDOG_FIRST_WORD_OF_UNLOCK; + base->CNT = WDOG_SECOND_WORD_OF_UNLOCK; + } + while ((base->CS & RTWDOG_CS_ULK_MASK) == 0) + { + } +} + +/*! + * @brief Refreshes the RTWDOG timer. + * + * This function feeds the RTWDOG. + * This function should be called before the Watchdog timer is in timeout. Otherwise, a reset is asserted. + * + * @param base RTWDOG peripheral base address + */ +static inline void RTWDOG_Refresh(RTWDOG_Type *base) +{ + uint32_t primaskValue = 0U; + primaskValue = DisableGlobalIRQ(); + if ((base->CS) & RTWDOG_CS_CMD32EN_MASK) + { + base->CNT = RTWDOG_REFRESH_KEY; + } + else + { + base->CNT = WDOG_FIRST_WORD_OF_REFRESH; + base->CNT = WDOG_SECOND_WORD_OF_REFRESH; + } + EnableGlobalIRQ(primaskValue); +} + +/*! + * @brief Gets the RTWDOG counter value. + * + * This function gets the RTWDOG counter value. + * + * @param base RTWDOG peripheral base address. + * @return Current RTWDOG counter value. + */ +static inline uint16_t RTWDOG_GetCounterValue(RTWDOG_Type *base) +{ + return base->CNT; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_RTWDOG_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_sai.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_sai.c new file mode 100644 index 0000000000..9bf4c59ba2 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_sai.c @@ -0,0 +1,3837 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sai.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sai" +#endif + +/******************************************************************************* + * Definitations + ******************************************************************************/ +enum _sai_transfer_state +{ + kSAI_Busy = 0x0U, /*!< SAI is busy */ + kSAI_Idle, /*!< Transfer is done. */ + kSAI_Error /*!< Transfer error occurred. */ +}; + +/*! @brief Typedef for sai tx interrupt handler. */ +typedef void (*sai_tx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + +/*! @brief Typedef for sai rx interrupt handler. */ +typedef void (*sai_rx_isr_t)(I2S_Type *base, sai_handle_t *saiHandle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if ((defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV) && (FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV))) + +/*! + * @brief Set the master clock divider. + * + * This API will compute the master clock divider according to master clock frequency and master + * clock source clock source frequency. + * + * @param base SAI base pointer. + * @param mclk_Hz Mater clock frequency in Hz. + * @param mclkSrcClock_Hz Master clock source frequency in Hz. + */ +static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz); +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + +/*! + * @brief Get the instance number for SAI. + * + * @param base SAI base pointer. + */ +static uint32_t SAI_GetInstance(I2S_Type *base); + +/*! + * @brief sends a piece of data in non-blocking way. + * + * @param base SAI base pointer + * @param channel start channel number. + * @param channelMask enabled channels mask. + * @param endChannel end channel numbers. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +static void SAI_WriteNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint32_t bitWidth, + uint8_t *buffer, + uint32_t size); + +/*! + * @brief Receive a piece of data in non-blocking way. + * + * @param base SAI base pointer + * @param channel start channel number. + * @param channelMask enabled channels mask. + * @param endChannel end channel numbers. + * @param bitWidth How many bits in a audio word, usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +static void SAI_ReadNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint32_t bitWidth, + uint8_t *buffer, + uint32_t size); + +/*! + * @brief Get classic I2S mode configurations. + * + * @param config transceiver configurations + * @param bitWidth audio data bitWidth. + * @param mode audio data channel + * @param saiChannelMask channel mask value to enable + */ +static void SAI_GetCommonConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Base pointer array */ +static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; +/*!@brief SAI handle pointer */ +static sai_handle_t *s_saiHandle[ARRAY_SIZE(s_saiBases)][2]; +/* IRQ number array */ +static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS; +static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Clock name array */ +static const clock_ip_name_t s_saiClock[] = SAI_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_tx_isr_t s_saiTxIsr; +/*! @brief Pointer to tx IRQ handler for each instance. */ +static sai_rx_isr_t s_saiRxIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +#if ((defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV) && (FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV))) +static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t mclkSrcClock_Hz) +{ + assert(mclk_Hz <= mclkSrcClock_Hz); + + uint32_t sourceFreq = mclkSrcClock_Hz / 100U; /*In order to prevent overflow */ + uint32_t targetFreq = mclk_Hz / 100U; /*In order to prevent overflow */ + +#if FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV + uint32_t postDivider = sourceFreq / targetFreq; + + /* if source equal to target, then disable divider */ + if (postDivider == 1U) + { + base->MCR &= ~I2S_MCR_DIVEN_MASK; + } + else + { + base->MCR = (base->MCR & (~I2S_MCR_DIV_MASK)) | I2S_MCR_DIV(postDivider / 2U - 1U) | I2S_MCR_DIVEN_MASK; + } +#endif +#if FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER + uint16_t fract, divide; + uint32_t remaind = 0; + uint32_t current_remainder = 0xFFFFFFFFU; + uint16_t current_fract = 0; + uint16_t current_divide = 0; + uint32_t mul_freq = 0; + uint32_t max_fract = 256; + + /* Compute the max fract number */ + max_fract = targetFreq * 4096 / sourceFreq + 1; + if (max_fract > 256) + { + max_fract = 256; + } + + /* Looking for the closet frequency */ + for (fract = 1; fract < max_fract; fract++) + { + mul_freq = sourceFreq * fract; + remaind = mul_freq % targetFreq; + divide = mul_freq / targetFreq; + + /* Find the exactly frequency */ + if (remaind == 0) + { + current_fract = fract; + current_divide = mul_freq / targetFreq; + break; + } + + /* Closer to next one, set the closest to next data */ + if (remaind > mclk_Hz / 2) + { + remaind = targetFreq - remaind; + divide += 1; + } + + /* Update the closest div and fract */ + if (remaind < current_remainder) + { + current_fract = fract; + current_divide = divide; + current_remainder = remaind; + } + } + + /* Fill the computed fract and divider to registers */ + base->MDR = I2S_MDR_DIVIDE(current_divide - 1) | I2S_MDR_FRACT(current_fract - 1); + + /* Waiting for the divider updated */ + while (base->MCR & I2S_MCR_DUF_MASK) + { + } +#endif +} +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + +static uint32_t SAI_GetInstance(I2S_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_saiBases); instance++) + { + if (s_saiBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_saiBases)); + + return instance; +} + +static void SAI_WriteNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint32_t bitWidth, + uint8_t *buffer, + uint32_t size) +{ + uint32_t i = 0; + uint8_t j = 0, m = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + uint32_t temp = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + for (j = channel; j <= endChannel; j++) + { + if ((1U << j) & channelMask) + { + for (m = 0; m < bytesPerWord; m++) + { + temp = (uint32_t)(*buffer); + data |= (temp << (8U * m)); + buffer++; + } + base->TDR[j] = data; + data = 0; + } + } + } +} + +static void SAI_ReadNonBlocking(I2S_Type *base, + uint32_t channel, + uint32_t channelMask, + uint32_t endChannel, + uint32_t bitWidth, + uint8_t *buffer, + uint32_t size) +{ + uint32_t i = 0; + uint8_t j = 0, m = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t data = 0; + + for (i = 0; i < size / bytesPerWord; i++) + { + for (j = channel; j <= endChannel; j++) + { + if ((1U << j) & channelMask) + { + data = base->RDR[j]; + for (m = 0; m < bytesPerWord; m++) + { + *buffer = (data >> (8U * m)) & 0xFF; + buffer++; + } + } + } + } +} + +static void SAI_GetCommonConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + + memset(config, 0U, sizeof(sai_transceiver_t)); + + config->channelMask = saiChannelMask; + /* sync mode default configurations */ + config->syncMode = kSAI_ModeAsync; + + /* master mode default */ + config->masterSlave = kSAI_Master; + + /* bit default configurations */ + config->bitClock.bclkSrcSwap = false; + config->bitClock.bclkInputDelay = false; + config->bitClock.bclkPolarity = kSAI_SampleOnRisingEdge; + config->bitClock.bclkSource = kSAI_BclkSourceMclkDiv; + + /* frame sync default configurations */ + config->frameSync.frameSyncWidth = bitWidth; + config->frameSync.frameSyncEarly = true; +#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND + config->frameSync.frameSyncGenerateOnDemand = false; +#endif + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveLow; + + /* serial data default configurations */ +#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE + config->serialData.dataMode = kSAI_DataPinStateOutputZero; +#endif + config->serialData.dataOrder = kSAI_DataMSB; + config->serialData.dataWord0Length = bitWidth; + config->serialData.dataWordLength = bitWidth; + config->serialData.dataWordNLength = bitWidth; + config->serialData.dataFirstBitShifted = bitWidth; + config->serialData.dataWordNum = 2U; + config->serialData.dataMaskedWord = mode; + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* fifo configurations */ + config->fifo.fifoWatermark = FSL_FEATURE_SAI_FIFO_COUNT / 2U; +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + config->fifo.fifoContinueOneError = true; +#endif +} + +/*! + * brief Initializes the SAI Tx peripheral. + * + * deprecated Do not use this function. It has been superceded by @ref SAI_Init + * + * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_TxGetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAIM module can cause a hard fault + * because the clock is not enabled. + * + * param base SAI base pointer + * param config SAI configuration structure. + */ +void SAI_TxInit(I2S_Type *base, const sai_config_t *config) +{ + uint32_t val = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the SAI clock */ + CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + /* Master clock source setting */ + val = (base->MCR & ~I2S_MCR_MICS_MASK); + base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); +#endif + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + + SAI_TxReset(base); + + /* Configure audio protocol */ + switch (config->protocol) + { + case kSAI_BusLeftJustified: + base->TCR2 |= I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusRightJustified: + base->TCR2 |= I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusI2S: + base->TCR2 |= I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(31U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(1U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusPCMA: + base->TCR2 &= ~I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(1U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + case kSAI_BusPCMB: + base->TCR2 &= ~I2S_TCR2_BCP_MASK; + base->TCR3 &= ~I2S_TCR3_WDFL_MASK; + base->TCR4 = I2S_TCR4_MF(1U) | I2S_TCR4_SYWD(0U) | I2S_TCR4_FSE(0U) | I2S_TCR4_FSP(0U) | I2S_TCR4_FRSZ(1U); + break; + + default: + break; + } + + /* Set master or slave */ + if (config->masterSlave == kSAI_Master) + { + base->TCR2 |= I2S_TCR2_BCD_MASK; + base->TCR4 |= I2S_TCR4_FSD_MASK; + + /* Bit clock source setting */ + val = base->TCR2 & (~I2S_TCR2_MSEL_MASK); + base->TCR2 = (val | I2S_TCR2_MSEL(config->bclkSource)); + } + else + { + base->TCR2 &= ~I2S_TCR2_BCD_MASK; + base->TCR4 &= ~I2S_TCR4_FSD_MASK; + } + + /* Set Sync mode */ + switch (config->syncMode) + { + case kSAI_ModeAsync: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + break; + case kSAI_ModeSync: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(1U)); + /* If sync with Rx, should set Rx to async mode */ + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + break; +#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) + case kSAI_ModeSyncWithOtherTx: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(2U)); + break; + case kSAI_ModeSyncWithOtherRx: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(3U)); + break; +#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ + default: + break; + } + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + SAI_TxSetFIFOErrorContinue(base, true); +#endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */ +} + +/*! + * brief Initializes the SAI Rx peripheral. + * + * deprecated Do not use this function. It has been superceded by @ref SAI_Init + * + * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_RxGetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAI module can cause a hard fault + * because the clock is not enabled. + * + * param base SAI base pointer + * param config SAI configuration structure. + */ +void SAI_RxInit(I2S_Type *base, const sai_config_t *config) +{ + uint32_t val = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable SAI clock first. */ + CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + /* Master clock source setting */ + val = (base->MCR & ~I2S_MCR_MICS_MASK); + base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); +#endif + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + + SAI_RxReset(base); + + /* Configure audio protocol */ + switch (config->protocol) + { + case kSAI_BusLeftJustified: + base->RCR2 |= I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusRightJustified: + base->RCR2 |= I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusI2S: + base->RCR2 |= I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(31U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(1U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusPCMA: + base->RCR2 &= ~I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(1U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + case kSAI_BusPCMB: + base->RCR2 &= ~I2S_RCR2_BCP_MASK; + base->RCR3 &= ~I2S_RCR3_WDFL_MASK; + base->RCR4 = I2S_RCR4_MF(1U) | I2S_RCR4_SYWD(0U) | I2S_RCR4_FSE(0U) | I2S_RCR4_FSP(0U) | I2S_RCR4_FRSZ(1U); + break; + + default: + break; + } + + /* Set master or slave */ + if (config->masterSlave == kSAI_Master) + { + base->RCR2 |= I2S_RCR2_BCD_MASK; + base->RCR4 |= I2S_RCR4_FSD_MASK; + + /* Bit clock source setting */ + val = base->RCR2 & (~I2S_RCR2_MSEL_MASK); + base->RCR2 = (val | I2S_RCR2_MSEL(config->bclkSource)); + } + else + { + base->RCR2 &= ~I2S_RCR2_BCD_MASK; + base->RCR4 &= ~I2S_RCR4_FSD_MASK; + } + + /* Set Sync mode */ + switch (config->syncMode) + { + case kSAI_ModeAsync: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + break; + case kSAI_ModeSync: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(1U)); + /* If sync with Tx, should set Tx to async mode */ + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + break; +#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) + case kSAI_ModeSyncWithOtherTx: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(2U)); + break; + case kSAI_ModeSyncWithOtherRx: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(3U)); + break; +#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ + default: + break; + } + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + SAI_RxSetFIFOErrorContinue(base, true); +#endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */ +} + +/*! + * brief Initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_Init is called to enable the clock. + * + * param base SAI base pointer + */ +void SAI_Init(I2S_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the SAI clock */ + CLOCK_EnableClock(s_saiClock[SAI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief De-initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit + * or SAI_RxInit is called to enable the clock. + * + * param base SAI base pointer + */ +void SAI_Deinit(I2S_Type *base) +{ + SAI_TxEnable(base, false); + SAI_RxEnable(base, false); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_saiClock[SAI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Sets the SAI Tx configuration structure to default values. + * + * deprecated Do not use this function. It has been superceded by @ref + * SAI_GetClassicI2SConfig/SAI_GetLeftJustifiedConfig/SAI_GetRightJustifiedConfig/SAI_GetDSPConfig/SAI_GetTDMConfig + * + * This API initializes the configuration structure for use in SAI_TxConfig(). + * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified + * before calling SAI_TxConfig(). + * This is an example. + code + sai_config_t config; + SAI_TxGetDefaultConfig(&config); + endcode + * + * param config pointer to master configuration structure + */ +void SAI_TxGetDefaultConfig(sai_config_t *config) +{ + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->bclkSource = kSAI_BclkSourceMclkDiv; + config->masterSlave = kSAI_Master; +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + config->mclkOutputEnable = true; +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + config->mclkSource = kSAI_MclkSourceSysclk; +#endif +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + config->protocol = kSAI_BusI2S; + config->syncMode = kSAI_ModeAsync; +} + +/*! + * brief Sets the SAI Rx configuration structure to default values. + * + * deprecated Do not use this function. It has been superceded by @ref + * SAI_GetClassicI2SConfig/SAI_GetLeftJustifiedConfig/SAI_GetRightJustifiedConfig/SAI_GetDSPConfig/SAI_GetTDMConfig + * + * This API initializes the configuration structure for use in SAI_RxConfig(). + * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified + * before calling SAI_RxConfig(). + * This is an example. + code + sai_config_t config; + SAI_RxGetDefaultConfig(&config); + endcode + * + * param config pointer to master configuration structure + */ +void SAI_RxGetDefaultConfig(sai_config_t *config) +{ + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->bclkSource = kSAI_BclkSourceMclkDiv; + config->masterSlave = kSAI_Master; +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + config->mclkOutputEnable = true; +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + config->mclkSource = kSAI_MclkSourceSysclk; +#endif +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + config->protocol = kSAI_BusI2S; + config->syncMode = kSAI_ModeSync; +} + +/*! + * brief Resets the SAI Tx. + * + * This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit. + * + * param base SAI base pointer + */ +void SAI_TxReset(I2S_Type *base) +{ + /* Set the software reset and FIFO reset to clear internal state */ + base->TCSR = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK; + + /* Clear software reset bit, this should be done by software */ + base->TCSR &= ~I2S_TCSR_SR_MASK; + + /* Reset all Tx register values */ + base->TCR2 = 0; + base->TCR3 = 0; + base->TCR4 = 0; + base->TCR5 = 0; + base->TMR = 0; +} + +/*! + * brief Resets the SAI Rx. + * + * This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit. + * + * param base SAI base pointer + */ +void SAI_RxReset(I2S_Type *base) +{ + /* Set the software reset and FIFO reset to clear internal state */ + base->RCSR = I2S_RCSR_SR_MASK | I2S_RCSR_FR_MASK; + + /* Clear software reset bit, this should be done by software */ + base->RCSR &= ~I2S_RCSR_SR_MASK; + + /* Reset all Rx register values */ + base->RCR2 = 0; + base->RCR3 = 0; + base->RCR4 = 0; + base->RCR5 = 0; + base->RMR = 0; +} + +/*! + * brief Enables/disables the SAI Tx. + * + * param base SAI base pointer + * param enable True means enable SAI Tx, false means disable. + */ +void SAI_TxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + /* If clock is sync with Rx, should enable RE bit. */ + if (((base->TCR2 & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT) == 0x1U) + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK); + } + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK); + /* Also need to clear the FIFO error flag before start */ + SAI_TxClearStatusFlags(base, kSAI_FIFOErrorFlag); + } + else + { + /* If RE not sync with TE, than disable TE, otherwise, shall not disable TE */ + if (((base->RCR2 & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT) != 0x1U) + { + /* Should not close RE even sync with Rx */ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~I2S_TCSR_TE_MASK)); + } + } +} + +/*! + * brief Enables/disables the SAI Rx. + * + * param base SAI base pointer + * param enable True means enable SAI Rx, false means disable. + */ +void SAI_RxEnable(I2S_Type *base, bool enable) +{ + if (enable) + { + /* If clock is sync with Tx, should enable TE bit. */ + if (((base->RCR2 & I2S_RCR2_SYNC_MASK) >> I2S_RCR2_SYNC_SHIFT) == 0x1U) + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | I2S_TCSR_TE_MASK); + } + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | I2S_RCSR_RE_MASK); + /* Also need to clear the FIFO error flag before start */ + SAI_RxClearStatusFlags(base, kSAI_FIFOErrorFlag); + } + else + { + /* While TX is not sync with RX, close RX */ + if (((base->TCR2 & I2S_TCR2_SYNC_MASK) >> I2S_TCR2_SYNC_SHIFT) != 0x1U) + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~I2S_RCSR_RE_MASK)); + } + } +} + +/*! + * brief Do software reset or FIFO reset . + * + * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. + * Software reset means clear the Tx internal logic, including the bit clock, frame count etc. But software + * reset will not clear any configuration registers like TCR1~TCR5. + * This function will also clear all the error flags such as FIFO error, sync error etc. + * + * param base SAI base pointer + * param type Reset type, FIFO reset or software reset + */ +void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type) +{ + base->TCSR |= (uint32_t)type; + + /* Clear the software reset */ + base->TCSR &= ~I2S_TCSR_SR_MASK; +} + +/*! + * brief Do software reset or FIFO reset . + * + * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. + * Software reset means clear the Rx internal logic, including the bit clock, frame count etc. But software + * reset will not clear any configuration registers like RCR1~RCR5. + * This function will also clear all the error flags such as FIFO error, sync error etc. + * + * param base SAI base pointer + * param type Reset type, FIFO reset or software reset + */ +void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type) +{ + base->RCSR |= (uint32_t)type; + + /* Clear the software reset */ + base->RCSR &= ~I2S_RCSR_SR_MASK; +} + +/*! + * brief Set the Tx channel FIFO enable mask. + * + * param base SAI base pointer + * param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, + * 3 means both channel 0 and channel 1 enabled. + */ +void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask) +{ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; + base->TCR3 |= I2S_TCR3_TCE(mask); +} + +/*! + * brief Set the Rx channel FIFO enable mask. + * + * param base SAI base pointer + * param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, + * 3 means both channel 0 and channel 1 enabled. + */ +void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask) +{ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; + base->RCR3 |= I2S_RCR3_RCE(mask); +} + +/*! + * brief Set the Tx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order) +{ + uint32_t val = (base->TCR4) & (~I2S_TCR4_MF_MASK); + + val |= I2S_TCR4_MF(order); + base->TCR4 = val; +} + +/*! + * brief Set the Rx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order) +{ + uint32_t val = (base->RCR4) & (~I2S_RCR4_MF_MASK); + + val |= I2S_RCR4_MF(order); + base->RCR4 = val; +} + +/*! + * brief Set the Tx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->TCR2) & (~I2S_TCR2_BCP_MASK); + + val |= I2S_TCR2_BCP(polarity); + base->TCR2 = val; +} + +/*! + * brief Set the Rx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->RCR2) & (~I2S_RCR2_BCP_MASK); + + val |= I2S_RCR2_BCP(polarity); + base->RCR2 = val; +} + +/*! + * brief Set the Tx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->TCR4) & (~I2S_TCR4_FSP_MASK); + + val |= I2S_TCR4_FSP(polarity); + base->TCR4 = val; +} + +/*! + * brief Set the Rx data order. + * + * param base SAI base pointer + * param order Data order MSB or LSB + */ +void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity) +{ + uint32_t val = (base->RCR4) & (~I2S_RCR4_FSP_MASK); + + val |= I2S_RCR4_FSP(polarity); + base->RCR4 = val; +} + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +/*! + * brief Set Tx FIFO packing feature. + * + * param base SAI base pointer. + * param pack FIFO pack type. It is element of sai_fifo_packing_t. + */ +void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) +{ + uint32_t val = base->TCR4; + + val &= ~I2S_TCR4_FPACK_MASK; + val |= I2S_TCR4_FPACK(pack); + base->TCR4 = val; +} + +/*! + * brief Set Rx FIFO packing feature. + * + * param base SAI base pointer. + * param pack FIFO pack type. It is element of sai_fifo_packing_t. + */ +void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack) +{ + uint32_t val = base->RCR4; + + val &= ~I2S_RCR4_FPACK_MASK; + val |= I2S_RCR4_FPACK(pack); + base->RCR4 = val; +} +#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ + +/*! + * brief Transmitter bit clock rate configurations. + * + * param base SAI base pointer. + * param sourceClockHz, bit clock source frequency. + * param sampleRate audio data sample rate. + * param bitWidth, audio data bitWidth. + * param channelNumbers, audio channel numbers. + */ +void SAI_TxSetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers) +{ + uint32_t tcr2 = base->TCR2; + uint32_t bitClockDiv = 0; + uint32_t bitClockFreq = sampleRate * bitWidth * channelNumbers; + + assert(sourceClockHz >= bitClockFreq); + + tcr2 &= ~I2S_TCR2_DIV_MASK; + /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ + bitClockDiv = sourceClockHz / bitClockFreq; + /* for the condition where the source clock is smaller than target bclk */ + if (bitClockDiv == 0U) + { + bitClockDiv++; + } + /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ + if ((sourceClockHz / bitClockDiv) > bitClockFreq) + { + bitClockDiv++; + } + +#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) + /* if bclk same with MCLK, bypass the divider */ + if (bitClockDiv == 1U) + { + tcr2 |= I2S_TCR2_BYP_MASK; + } + else +#endif + { + tcr2 |= I2S_TCR2_DIV(bitClockDiv / 2U - 1U); + } + + base->TCR2 = tcr2; +} + +/*! + * brief Receiver bit clock rate configurations. + * + * param base SAI base pointer. + * param sourceClockHz, bit clock source frequency. + * param sampleRate audio data sample rate. + * param bitWidth, audio data bitWidth. + * param channelNumbers, audio channel numbers. + */ +void SAI_RxSetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers) +{ + uint32_t rcr2 = base->RCR2; + uint32_t bitClockDiv = 0; + uint32_t bitClockFreq = sampleRate * bitWidth * channelNumbers; + + assert(sourceClockHz >= bitClockFreq); + + rcr2 &= ~I2S_RCR2_DIV_MASK; + /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ + bitClockDiv = sourceClockHz / bitClockFreq; + /* for the condition where the source clock is smaller than target bclk */ + if (bitClockDiv == 0U) + { + bitClockDiv++; + } + /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ + if ((sourceClockHz / bitClockDiv) > bitClockFreq) + { + bitClockDiv++; + } + +#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) + /* if bclk same with MCLK, bypass the divider */ + if (bitClockDiv == 1U) + { + rcr2 |= I2S_RCR2_BYP_MASK; + } + else +#endif + { + rcr2 |= I2S_RCR2_DIV(bitClockDiv / 2U - 1U); + } + + base->RCR2 = rcr2; +} + +/*! + * brief Transmitter Bit clock configurations. + * + * param base SAI base pointer. + * param masterSlave master or slave. + * param config bit clock other configurations, can be NULL in slave mode. + */ +void SAI_TxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config) +{ + uint32_t tcr2 = base->TCR2; + + if ((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Master_FrameSync_Slave)) + { + assert(config != NULL); + + tcr2 &= ~(I2S_TCR2_BCD_MASK | I2S_TCR2_BCP_MASK | I2S_TCR2_BCI_MASK | I2S_TCR2_BCS_MASK | I2S_TCR2_MSEL_MASK); + tcr2 |= I2S_TCR2_BCD(1U) | I2S_TCR2_BCP(config->bclkPolarity) | I2S_TCR2_BCI(config->bclkInputDelay) | + I2S_TCR2_BCS(config->bclkSrcSwap) | I2S_TCR2_MSEL(config->bclkSource); + } + else + { + tcr2 &= ~(I2S_TCR2_BCD_MASK); + } + + base->TCR2 = tcr2; +} + +/*! + * brief Receiver Bit clock configurations. + * + * param base SAI base pointer. + * param masterSlave master or slave. + * param config bit clock other configurations, can be NULL in slave mode. + */ +void SAI_RxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config) +{ + uint32_t rcr2 = base->RCR2; + + if ((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Master_FrameSync_Slave)) + { + assert(config != NULL); + + rcr2 &= ~(I2S_RCR2_BCD_MASK | I2S_RCR2_BCP_MASK | I2S_RCR2_BCI_MASK | I2S_RCR2_BCS_MASK | I2S_RCR2_MSEL_MASK); + rcr2 |= I2S_RCR2_BCD(1U) | I2S_RCR2_BCP(config->bclkPolarity) | I2S_RCR2_BCI(config->bclkInputDelay) | + I2S_RCR2_BCS(config->bclkSrcSwap) | I2S_RCR2_MSEL(config->bclkSource); + } + else + { + rcr2 &= ~(I2S_RCR2_BCD_MASK); + } + + base->RCR2 = rcr2; +} + +#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) +/*! + * brief Master clock configurations. + * + * param base SAI base pointer. + * param config master clock configurations. + */ +void SAI_SetMasterClockConfig(I2S_Type *base, sai_master_clock_t *config) +{ + assert(config != NULL); + +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + uint32_t val = 0; +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + /* Master clock source setting */ + val = (base->MCR & ~I2S_MCR_MICS_MASK); + base->MCR = (val | I2S_MCR_MICS(config->mclkSource)); +#endif + + /* Configure Master clock output enable */ + val = (base->MCR & ~I2S_MCR_MOE_MASK); + base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable)); +#endif /* FSL_FEATURE_SAI_HAS_MCR */ + +#if ((defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV) && (FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV))) + /* Check if master clock divider enabled, then set master clock divider */ + if (config->mclkOutputEnable) + { + SAI_SetMasterClockDivider(base, config->mclkHz, config->mclkSourceClkHz); + } +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ +} +#endif + +/*! + * brief SAI transmitter fifo configurations. + * + * param base SAI base pointer. + * param config fifo configurations. + */ +void SAI_TxSetFifoConfig(I2S_Type *base, sai_fifo_t *config) +{ + assert(config != NULL); +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + assert(config->fifoWatermark <= (I2S_TCR1_TFW_MASK >> I2S_TCR1_TFW_SHIFT)); +#endif + + uint32_t tcr4 = base->TCR4; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE + tcr4 &= ~I2S_TCR4_FCOMB_MASK; + tcr4 |= I2S_TCR4_FCOMB(config->fifoCombine); +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + tcr4 &= ~I2S_TCR4_FCONT_MASK; + /* ERR05144: not set FCONT = 1 when TMR > 0, the transmit shift register may not load correctly that will cause TX + * not work */ + if (base->TMR == 0U) + { + tcr4 |= I2S_TCR4_FCONT(config->fifoContinueOneError); + } +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING + tcr4 &= ~I2S_TCR4_FPACK_MASK; + tcr4 |= I2S_TCR4_FPACK(config->fifoPacking); +#endif + + base->TCR4 = tcr4; + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + base->TCR1 = (base->TCR1 & (~I2S_TCR1_TFW_MASK)) | I2S_TCR1_TFW(config->fifoWatermark); +#endif +} + +/*! + * brief SAI receiver fifo configurations. + * + * param base SAI base pointer. + * param config fifo configurations. + */ +void SAI_RxSetFifoConfig(I2S_Type *base, sai_fifo_t *config) +{ + assert(config != NULL); +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + assert(config->fifoWatermark <= (I2S_TCR1_TFW_MASK >> I2S_TCR1_TFW_SHIFT)); +#endif + uint32_t rcr4 = base->RCR4; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE + rcr4 &= ~I2S_RCR4_FCOMB_MASK; + rcr4 |= I2S_RCR4_FCOMB(config->fifoCombine); +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + rcr4 &= ~I2S_RCR4_FCONT_MASK; + rcr4 |= I2S_RCR4_FCONT(config->fifoContinueOneError); +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING + rcr4 &= ~I2S_RCR4_FPACK_MASK; + rcr4 |= I2S_RCR4_FPACK(config->fifoPacking); +#endif + + base->RCR4 = rcr4; + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + base->RCR1 = (base->RCR1 & (~I2S_RCR1_RFW_MASK)) | I2S_RCR1_RFW(config->fifoWatermark); +#endif +} + +/*! + * brief SAI transmitter Frame sync configurations. + * + * param base SAI base pointer. + * param masterSlave master or slave. + * param config frame sync configurations, can be NULL in slave mode. + */ +void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config) +{ + uint32_t tcr4 = base->TCR4; + + if ((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Slave_FrameSync_Master)) + { + assert(config != NULL); + assert((config->frameSyncWidth - 1U) <= (I2S_TCR4_SYWD_MASK >> I2S_TCR4_SYWD_SHIFT)); + + tcr4 &= ~(I2S_TCR4_FSE_MASK | I2S_TCR4_FSP_MASK | I2S_TCR4_FSD_MASK | I2S_TCR4_SYWD_MASK); + +#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND + tcr4 &= ~I2S_TCR4_ONDEM_MASK; + tcr4 |= I2S_TCR4_ONDEM(config->frameSyncGenerateOnDemand); +#endif + + tcr4 |= I2S_TCR4_FSE(config->frameSyncEarly) | I2S_TCR4_FSP(config->frameSyncPolarity) | I2S_TCR4_FSD(1U) | + I2S_TCR4_SYWD(config->frameSyncWidth - 1U); + } + else + { + tcr4 &= ~I2S_TCR4_FSD_MASK; + } + + base->TCR4 = tcr4; +} + +/*! + * brief SAI receiver Frame sync configurations. + * + * param base SAI base pointer. + * param masterSlave master or slave. + * param config frame sync configurations, can be NULL in slave mode. + */ +void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config) +{ + uint32_t rcr4 = base->RCR4; + + if ((masterSlave == kSAI_Master) || (masterSlave == kSAI_Bclk_Slave_FrameSync_Master)) + { + assert(config != NULL); + assert((config->frameSyncWidth - 1U) <= (I2S_RCR4_SYWD_MASK >> I2S_RCR4_SYWD_SHIFT)); + + rcr4 &= ~(I2S_RCR4_FSE_MASK | I2S_RCR4_FSP_MASK | I2S_RCR4_FSD_MASK | I2S_RCR4_SYWD_MASK); + +#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND + rcr4 &= ~I2S_RCR4_ONDEM_MASK; + rcr4 |= I2S_RCR4_ONDEM(config->frameSyncGenerateOnDemand); +#endif + + rcr4 |= I2S_RCR4_FSE(config->frameSyncEarly) | I2S_RCR4_FSP(config->frameSyncPolarity) | I2S_RCR4_FSD(1U) | + I2S_RCR4_SYWD(config->frameSyncWidth - 1U); + } + else + { + rcr4 &= ~I2S_RCR4_FSD_MASK; + } + + base->RCR4 = rcr4; +} + +/*! + * brief SAI transmitter Serial data configurations. + * + * param base SAI base pointer. + * param config serial data configurations. + */ +void SAI_TxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config) +{ + assert(config != NULL); + + uint32_t tcr4 = base->TCR4; + + base->TCR5 = I2S_TCR5_WNW(config->dataWordNLength - 1U) | I2S_TCR5_W0W(config->dataWord0Length - 1U) | + I2S_TCR5_FBT(config->dataFirstBitShifted - 1U); + base->TMR = config->dataMaskedWord; +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + /* ERR05144: not set FCONT = 1 when TMR > 0, the transmit shift register may not load correctly that will cause TX + * not work */ + if (config->dataMaskedWord > 0U) + { + tcr4 &= ~I2S_TCR4_FCONT_MASK; + } +#endif + tcr4 &= ~(I2S_TCR4_FRSZ_MASK | I2S_TCR4_MF_MASK); + tcr4 |= I2S_TCR4_FRSZ(config->dataWordNum - 1U) | I2S_TCR4_MF(config->dataOrder); + +#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE + tcr4 &= ~I2S_TCR4_CHMOD_MASK; + tcr4 |= I2S_TCR4_CHMOD(config->dataMode); +#endif + + base->TCR4 = tcr4; +} + +/*! + * @brief SAI receiver Serial data configurations. + * + * @param base SAI base pointer. + * @param config serial data configurations. + */ +void SAI_RxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config) +{ + assert(config != NULL); + + uint32_t rcr4 = base->RCR4; + + base->RCR5 = I2S_RCR5_WNW(config->dataWordNLength - 1U) | I2S_RCR5_W0W(config->dataWord0Length - 1U) | + I2S_RCR5_FBT(config->dataFirstBitShifted - 1U); + base->RMR = config->dataMaskedWord; + + rcr4 &= ~(I2S_RCR4_FRSZ_MASK | I2S_RCR4_MF_MASK); + rcr4 |= I2S_RCR4_FRSZ(config->dataWordNum - 1u) | I2S_RCR4_MF(config->dataOrder); + + base->RCR4 = rcr4; +} + +/*! + * brief SAI transmitter configurations. + * + * param base SAI base pointer. + * param config transmitter configurations. + */ +void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config) +{ + assert(config != NULL); + assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); + + uint32_t val = 0U, i = 0U; + uint32_t channelNums = 0U; + /* reset transmitter */ + SAI_TxReset(base); + + /* if channel mask is not set, then format->channel must be set, + use it to get channel mask value */ + if (config->channelMask == 0U) + { + config->channelMask = 1U << config->startChannel; + } + + for (i = 0U; i < FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (((uint32_t)1 << i) & config->channelMask) + { + /* get start channel number when channelNums = 0 only */ + if (channelNums == 0U) + { + config->startChannel = i; + } + channelNums++; + config->endChannel = i; + } + } + assert(channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); + config->channelNums = channelNums; +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + /* make sure combine mode disabled while multipe channel is used */ + if (config->channelNums > 1U) + { + base->TCR4 &= ~I2S_TCR4_FCOMB_MASK; + } +#endif + + /* Set data channel */ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; + base->TCR3 |= I2S_TCR3_TCE(config->channelMask); + + /* Set Sync mode */ + switch (config->syncMode) + { + case kSAI_ModeAsync: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + break; + case kSAI_ModeSync: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(1U)); + /* If sync with Rx, should set Rx to async mode */ + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + break; +#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) + case kSAI_ModeSyncWithOtherTx: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(2U)); + break; + case kSAI_ModeSyncWithOtherRx: + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(3U)); + break; +#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ + default: + break; + } + + /* bit clock configurations */ + SAI_TxSetBitclockConfig(base, config->masterSlave, &config->bitClock); + /* serial data configurations */ + SAI_TxSetSerialDataConfig(base, &config->serialData); + /* frame sync configurations */ + SAI_TxSetFrameSyncConfig(base, config->masterSlave, &config->frameSync); + /* fifo configurations */ + SAI_TxSetFifoConfig(base, &config->fifo); +} + +/*! + * brief SAI transmitter transfer configurations. + * + * This function initializes the TX, include bit clock, frame sync, master clock, serial data and fifo configurations. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param config tranmitter configurations. + */ +void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config) +{ + assert(handle != NULL); + assert(config != NULL); + + handle->bitWidth = config->frameSync.frameSyncWidth; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->watermark = config->fifo.fifoWatermark; +#endif + + /* transmitter configurations */ + SAI_TxSetConfig(base, config); + + handle->channel = config->startChannel; + /* used for multi channel */ + handle->channelMask = config->channelMask; + handle->channelNums = config->channelNums; + handle->endChannel = config->endChannel; +} + +/*! + * brief SAI receiver configurations. + * + * param base SAI base pointer. + * param config transmitter configurations. + */ +void SAI_RxSetConfig(I2S_Type *base, sai_transceiver_t *config) +{ + assert(config != NULL); + assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); + + uint32_t val = 0U, i = 0U; + uint32_t channelNums = 0U; + + /* reset receiver */ + SAI_RxReset(base); + + /* if channel mask is not set, then format->channel must be set, + use it to get channel mask value */ + if (config->channelMask == 0U) + { + config->channelMask = 1U << config->startChannel; + } + + for (i = 0U; i < FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (((uint32_t)1 << i) & config->channelMask) + { + /* get start channel number when channelNums = 0 only */ + if (channelNums == 0U) + { + config->startChannel = i; + } + channelNums++; + config->endChannel = i; + } + } + assert(channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); + config->channelNums = channelNums; +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + /* make sure combine mode disabled while multipe channel is used */ + if (config->channelNums > 1U) + { + base->RCR4 &= ~I2S_RCR4_FCOMB_MASK; + } +#endif + + /* Set data channel */ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; + base->RCR3 |= I2S_RCR3_RCE(config->channelMask); + + /* Set Sync mode */ + switch (config->syncMode) + { + case kSAI_ModeAsync: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(0U)); + break; + case kSAI_ModeSync: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(1U)); + /* If sync with Tx, should set Tx to async mode */ + val = base->TCR2; + val &= ~I2S_TCR2_SYNC_MASK; + base->TCR2 = (val | I2S_TCR2_SYNC(0U)); + break; +#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) + case kSAI_ModeSyncWithOtherTx: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(2U)); + break; + case kSAI_ModeSyncWithOtherRx: + val = base->RCR2; + val &= ~I2S_RCR2_SYNC_MASK; + base->RCR2 = (val | I2S_RCR2_SYNC(3U)); + break; +#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ + default: + break; + } + + /* bit clock configurations */ + SAI_RxSetBitclockConfig(base, config->masterSlave, &config->bitClock); + /* serial data configurations */ + SAI_RxSetSerialDataConfig(base, &config->serialData); + /* frame sync configurations */ + SAI_RxSetFrameSyncConfig(base, config->masterSlave, &config->frameSync); + /* fifo configurations */ + SAI_RxSetFifoConfig(base, &config->fifo); +} + +/*! + * brief SAI receiver transfer configurations. + * + * This function initializes the TX, include bit clock, frame sync, master clock, serial data and fifo configurations. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param config tranmitter configurations. + */ +void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config) +{ + assert(handle != NULL); + assert(config != NULL); + + handle->bitWidth = config->frameSync.frameSyncWidth; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->watermark = config->fifo.fifoWatermark; +#endif + + /* receiver configurations */ + SAI_RxSetConfig(base, config); + + handle->channel = config->startChannel; + /* used for multi channel */ + handle->channelMask = config->channelMask; + handle->channelNums = config->channelNums; + handle->endChannel = config->endChannel; +} + +/*! + * brief Get classic I2S mode configurations. + * + * param config transceiver configurations. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask channel mask value to enable. + */ +void SAI_GetClassicI2SConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask); +} + +/*! + * brief Get left justified mode configurations. + * + * param config transceiver configurations. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask channel mask value to enable. + */ +void SAI_GetLeftJustifiedConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + + SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask); + + config->frameSync.frameSyncEarly = false; + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh; +} + +/*! + * brief Get right justified mode configurations. + * + * param config transceiver configurations. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask channel mask value to enable. + */ +void SAI_GetRightJustifiedConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + + SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask); + + config->frameSync.frameSyncEarly = false; + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh; +} + +/*! + * brief Get DSP mode configurations. + * + * param config transceiver configurations. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask channel mask value to enable. + */ +void SAI_GetDSPConfig(sai_transceiver_t *config, + sai_frame_sync_len_t frameSyncWidth, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + + SAI_GetCommonConfig(config, bitWidth, mode, saiChannelMask); + + /* frame sync default configurations */ + switch (frameSyncWidth) + { + case kSAI_FrameSyncLenOneBitClk: + config->frameSync.frameSyncWidth = 1U; + break; + default: + assert(false); + } + config->frameSync.frameSyncEarly = false; + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh; +} + +/*! + * brief Get TDM mode configurations. + * + * param config transceiver configurations. + * param bitWidth audio data bitWidth. + * param mode audio data channel. + * param saiChannelMask channel mask value to enable. + */ +void SAI_GetTDMConfig(sai_transceiver_t *config, + sai_frame_sync_len_t frameSyncWidth, + sai_word_width_t bitWidth, + uint32_t dataWordNum, + uint32_t saiChannelMask) +{ + assert(NULL != config); + assert(saiChannelMask != 0U); + assert(dataWordNum <= 32U); + + SAI_GetCommonConfig(config, bitWidth, kSAI_Stereo, saiChannelMask); + + /* frame sync default configurations */ + switch (frameSyncWidth) + { + case kSAI_FrameSyncLenOneBitClk: + config->frameSync.frameSyncWidth = 1U; + break; + case kSAI_FrameSyncLenPerWordWidth: + break; + default: + assert(false); + } + config->frameSync.frameSyncEarly = false; + config->frameSync.frameSyncPolarity = kSAI_PolarityActiveHigh; + config->serialData.dataWordNum = dataWordNum; +} + +/*! + * brief Configures the SAI Tx audio format. + * + * deprecated Do not use this function. It has been superceded by @ref SAI_TxSetConfig + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * param base SAI base pointer. + * param format Pointer to the SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master + * clock, this value should equal the masterClockHz. + */ +void SAI_TxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); + + uint32_t bclk = 0; + uint32_t val = 0; + uint32_t i = 0U; + uint32_t divider = 0U, channelNums = 0U; + + if (format->isFrameSyncCompact) + { + bclk = format->sampleRate_Hz * format->bitWidth * (format->stereo == kSAI_Stereo ? 2U : 1U); + val = (base->TCR4 & (~I2S_TCR4_SYWD_MASK)); + val |= I2S_TCR4_SYWD(format->bitWidth - 1U); + base->TCR4 = val; + } + else + { + bclk = format->sampleRate_Hz * 32U * 2U; + } + +/* Compute the mclk */ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + /* Check if master clock divider enabled, then set master clock divider */ + if (base->MCR & I2S_MCR_MOE_MASK) + { + SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); + } +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + + /* Set bclk if needed */ + if (base->TCR2 & I2S_TCR2_BCD_MASK) + { + base->TCR2 &= ~I2S_TCR2_DIV_MASK; + /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ + divider = bclkSourceClockHz / bclk; + /* for the condition where the source clock is smaller than target bclk */ + if (divider == 0U) + { + divider++; + } + /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ + if ((bclkSourceClockHz / divider) > bclk) + { + divider++; + } + +#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) + /* if bclk same with MCLK, bypass the divider */ + if (divider == 1U) + { + base->TCR2 |= I2S_TCR2_BYP_MASK; + } + else +#endif + { + base->TCR2 |= I2S_TCR2_DIV(divider / 2U - 1U); + } + } + + /* Set bitWidth */ + val = (format->isFrameSyncCompact) ? (format->bitWidth - 1) : 31U; + if (format->protocol == kSAI_BusRightJustified) + { + base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(val); + } + else + { + if (base->TCR4 & I2S_TCR4_MF_MASK) + { + base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(format->bitWidth - 1); + } + else + { + base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(0); + } + } + + /* Set mono or stereo */ + base->TMR = (uint32_t)format->stereo; + + /* if channel mask is not set, then format->channel must be set, + use it to get channel mask value */ + if (format->channelMask == 0U) + { + format->channelMask = 1U << format->channel; + } + + /* if channel nums is not set, calculate it here according to channelMask*/ + for (i = 0U; i < FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (((uint32_t)1 << i) & format->channelMask) + { + /* geet start channel number when channelNums = 0 only */ + if (channelNums == 0U) + { + format->channel = i; + } + channelNums++; + format->endChannel = i; + } + } + format->channelNums = channelNums; + assert(format->channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + /* make sure combine mode disabled while multipe channel is used */ + if (format->channelNums > 1U) + { + base->TCR4 &= ~I2S_TCR4_FCOMB_MASK; + } +#endif + + /* Set data channel */ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; + base->TCR3 |= I2S_TCR3_TCE(format->channelMask); + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Set watermark */ + base->TCR1 = format->watermark; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +/*! + * brief Configures the SAI Rx audio format. + * + * deprecated Do not use this function. It has been superceded by @ref SAI_RxSetConfig + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * param base SAI base pointer. + * param format Pointer to the SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master + * clock, this value should equal the masterClockHz. + */ +void SAI_RxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); + + uint32_t bclk = 0; + uint32_t val = 0; + uint32_t i = 0U; + uint32_t divider = 0U, channelNums = 0U; + + if (format->isFrameSyncCompact) + { + bclk = format->sampleRate_Hz * format->bitWidth * (format->stereo == kSAI_Stereo ? 2U : 1U); + val = (base->RCR4 & (~I2S_RCR4_SYWD_MASK)); + val |= I2S_RCR4_SYWD(format->bitWidth - 1U); + base->RCR4 = val; + } + else + { + bclk = format->sampleRate_Hz * 32U * 2U; + } + +/* Compute the mclk */ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + /* Check if master clock divider enabled */ + if (base->MCR & I2S_MCR_MOE_MASK) + { + SAI_SetMasterClockDivider(base, format->masterClockHz, mclkSourceClockHz); + } +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ + + /* Set bclk if needed */ + if (base->RCR2 & I2S_RCR2_BCD_MASK) + { + base->RCR2 &= ~I2S_RCR2_DIV_MASK; + /* need to check the divided bclk, if bigger than target, then divider need to re-calculate. */ + divider = bclkSourceClockHz / bclk; + /* for the condition where the source clock is smaller than target bclk */ + if (divider == 0U) + { + divider++; + } + /* recheck the divider if properly or not, to make sure output blck not bigger than target*/ + if ((bclkSourceClockHz / divider) > bclk) + { + divider++; + } +#if defined(FSL_FEATURE_SAI_HAS_BCLK_BYPASS) && (FSL_FEATURE_SAI_HAS_BCLK_BYPASS) + /* if bclk same with MCLK, bypass the divider */ + if (divider == 1U) + { + base->RCR2 |= I2S_RCR2_BYP_MASK; + } + else +#endif + { + base->RCR2 |= I2S_RCR2_DIV(divider / 2U - 1U); + } + } + + /* Set bitWidth */ + val = (format->isFrameSyncCompact) ? (format->bitWidth - 1) : 31U; + if (format->protocol == kSAI_BusRightJustified) + { + base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(val); + } + else + { + if (base->RCR4 & I2S_RCR4_MF_MASK) + { + base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(format->bitWidth - 1); + } + else + { + base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(0); + } + } + + /* Set mono or stereo */ + base->RMR = (uint32_t)format->stereo; + + /* if channel mask is not set, then format->channel must be set, + use it to get channel mask value */ + if (format->channelMask == 0U) + { + format->channelMask = 1U << format->channel; + } + + /* if channel nums is not set, calculate it here according to channelMask*/ + for (i = 0U; i < FSL_FEATURE_SAI_CHANNEL_COUNTn(base); i++) + { + if (((uint32_t)1 << i) & format->channelMask) + { + /* geet start channel number when channelNums = 0 only */ + if (channelNums == 0U) + { + format->channel = i; + } + channelNums++; + format->endChannel = i; + } + } + format->channelNums = channelNums; + assert(format->channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && (FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) + /* make sure combine mode disabled while multipe channel is used */ + if (format->channelNums > 1U) + { + base->RCR4 &= ~I2S_RCR4_FCOMB_MASK; + } +#endif + + /* Set data channel */ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; + /* enable all the channel */ + base->RCR3 |= I2S_RCR3_RCE(format->channelMask); + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Set watermark */ + base->RCR1 = format->watermark; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +/*! + * brief Sends data using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be written. + * param size Bytes to be written. + */ +void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint8_t bytesPerWord = bitWidth / 8U; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + bytesPerWord = (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - base->TCR1) * bytesPerWord); +#endif + + while (i < size) + { + /* Wait until it can write data */ + while (!(base->TCSR & I2S_TCSR_FWF_MASK)) + { + } + + SAI_WriteNonBlocking(base, channel, 1U << channel, channel, bitWidth, buffer, bytesPerWord); + buffer += bytesPerWord; + i += bytesPerWord; + } + + /* Wait until the last data is sent */ + while (!(base->TCSR & I2S_TCSR_FWF_MASK)) + { + } +} + +/*! + * brief Sends data to multi channel using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param channelMask channel mask. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be written. + * param size Bytes to be written. + */ +void SAI_WriteMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); + + uint32_t i = 0, j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t channelNums = 0U, endChannel = 0U; + +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + bytesPerWord = (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - base->TCR1) * bytesPerWord); +#endif + + for (i = 0U; (i < FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); i++) + { + if ((1U << i) & (channelMask)) + { + channelNums++; + endChannel = i; + } + } + + assert(channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); + bytesPerWord *= channelNums; + + while (j < size) + { + /* Wait until it can write data */ + while (!(base->TCSR & I2S_TCSR_FWF_MASK)) + { + } + + SAI_WriteNonBlocking(base, channel, channelMask, endChannel, bitWidth, buffer, bytesPerWord); + buffer += bytesPerWord; + j += bytesPerWord; + } + + /* Wait until the last data is sent */ + while (!(base->TCSR & I2S_TCSR_FWF_MASK)) + { + } +} + +/*! + * brief Receives multi channel data using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param channelMask channel mask. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be read. + * param size Bytes to be read. + */ +void SAI_ReadMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + assert(FSL_FEATURE_SAI_CHANNEL_COUNTn(base) != -1); + + uint32_t i = 0, j = 0; + uint8_t bytesPerWord = bitWidth / 8U; + uint32_t channelNums = 0U, endChannel = 0U; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + bytesPerWord = (size_t)(base->RCR1 * bytesPerWord); +#endif + for (i = 0U; (i < FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); i++) + { + if ((1U << i) & (channelMask)) + { + channelNums++; + endChannel = i; + } + } + + assert(channelNums <= FSL_FEATURE_SAI_CHANNEL_COUNTn(base)); + bytesPerWord *= channelNums; + + while (j < size) + { + /* Wait until data is received */ + while (!(base->RCSR & I2S_RCSR_FWF_MASK)) + { + } + + SAI_ReadNonBlocking(base, channel, channelMask, endChannel, bitWidth, buffer, bytesPerWord); + buffer += bytesPerWord; + j += bytesPerWord; + } +} + +/*! + * brief Receives data using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SAI base pointer. + * param channel Data channel used. + * param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * param buffer Pointer to the data to be read. + * param size Bytes to be read. + */ +void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size) +{ + uint32_t i = 0; + uint8_t bytesPerWord = bitWidth / 8U; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + bytesPerWord = (size_t)(base->RCR1 * bytesPerWord); +#endif + + while (i < size) + { + /* Wait until data is received */ + while (!(base->RCSR & I2S_RCSR_FWF_MASK)) + { + } + + SAI_ReadNonBlocking(base, channel, 1U << channel, channel, bitWidth, buffer, bytesPerWord); + buffer += bytesPerWord; + i += bytesPerWord; + } +} + +/*! + * brief Initializes the SAI Tx handle. + * + * This function initializes the Tx handle for the SAI Tx transactional APIs. Call + * this function once to get the handle initialized. + * + * param base SAI base pointer + * param handle SAI handle pointer. + * param callback Pointer to the user callback function. + * param userData User parameter passed to the callback function + */ +void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) +{ + assert(handle); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + s_saiHandle[SAI_GetInstance(base)][0] = handle; + + handle->callback = callback; + handle->userData = userData; + handle->base = base; + + /* Set the isr pointer */ + s_saiTxIsr = SAI_TransferTxHandleIRQ; + + /* Enable Tx irq */ + EnableIRQ(s_saiTxIRQ[SAI_GetInstance(base)]); +} + +/*! + * brief Initializes the SAI Rx handle. + * + * This function initializes the Rx handle for the SAI Rx transactional APIs. Call + * this function once to get the handle initialized. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param callback Pointer to the user callback function. + * param userData User parameter passed to the callback function. + */ +void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData) +{ + assert(handle); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + s_saiHandle[SAI_GetInstance(base)][1] = handle; + + handle->callback = callback; + handle->userData = userData; + handle->base = base; + + /* Set the isr pointer */ + s_saiRxIsr = SAI_TransferRxHandleIRQ; + + /* Enable Rx irq */ + EnableIRQ(s_saiRxIRQ[SAI_GetInstance(base)]); +} + +/*! + * brief Configures the SAI Tx audio format. + * + * deprecated Do not use this function. It has been superceded by @ref SAI_TxSetTransferConfig + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param format Pointer to the SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master + * clock, this value should equal the masterClockHz in format. + * return Status of this function. Return value is the status_t. + */ +status_t SAI_TransferTxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle); + + if ((bclkSourceClockHz < format->sampleRate_Hz) +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + || (mclkSourceClockHz < format->sampleRate_Hz) +#endif + ) + { + return kStatus_InvalidArgument; + } + + /* Copy format to handle */ + handle->bitWidth = format->bitWidth; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->watermark = format->watermark; +#endif + + SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + handle->channel = format->channel; + /* used for multi channel */ + handle->channelMask = format->channelMask; + handle->channelNums = format->channelNums; + handle->endChannel = format->endChannel; + + return kStatus_Success; +} + +/*! + * brief Configures the SAI Rx audio format. + * + * deprecated Do not use this function. It has been superceded by @ref SAI_RxSetTransferConfig + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * param base SAI base pointer. + * param handle SAI handle pointer. + * param format Pointer to the SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master + * clock, this value should equal the masterClockHz in format. + * return Status of this function. Return value is one of status_t. + */ +status_t SAI_TransferRxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle); + + if ((bclkSourceClockHz < format->sampleRate_Hz) +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + || (mclkSourceClockHz < format->sampleRate_Hz) +#endif + ) + { + return kStatus_InvalidArgument; + } + + /* Copy format to handle */ + handle->bitWidth = format->bitWidth; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->watermark = format->watermark; +#endif + + SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + handle->channel = format->channel; + /* used for multi channel */ + handle->channelMask = format->channelMask; + handle->channelNums = format->channelNums; + handle->endChannel = format->endChannel; + + return kStatus_Success; +} + +/*! + * brief Performs an interrupt non-blocking send transfer on SAI. + * + * note This API returns immediately after the transfer initiates. + * Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param xfer Pointer to the sai_transfer_t structure. + * retval kStatus_Success Successfully started the data receive. + * retval kStatus_SAI_TxBusy Previous receive still not finished. + * retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Add into queue */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Set the state to busy */ + handle->state = kSAI_Busy; + + /* Enable interrupt */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error*/ + SAI_TxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_TxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* Enable Tx transfer */ + SAI_TxEnable(base, true); + + return kStatus_Success; +} + +/*! + * brief Performs an interrupt non-blocking receive transfer on SAI. + * + * note This API returns immediately after the transfer initiates. + * Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * param base SAI base pointer + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param xfer Pointer to the sai_transfer_t structure. + * retval kStatus_Success Successfully started the data receive. + * retval kStatus_SAI_RxBusy Previous receive still not finished. + * retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Add into queue */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Set state to busy */ + handle->state = kSAI_Busy; + +/* Enable interrupt */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error*/ + SAI_RxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_RxEnableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* Enable Rx transfer */ + SAI_RxEnable(base, true); + + return kStatus_Success; +} + +/*! + * brief Gets a set byte count. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param count Bytes count sent. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->saiQueue[handle->queueDriver].dataSize); + } + + return status; +} + +/*! + * brief Gets a received byte count. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + * param count Bytes count received. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->saiQueue[handle->queueDriver].dataSize); + } + + return status; +} + +/*! + * brief Aborts the current send. + * + * note This API can be called any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + /* Stop Tx transfer and disable interrupt */ + SAI_TxEnable(base, false); +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error */ + SAI_TxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_TxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + handle->state = kSAI_Idle; + + /* Clear the queue */ + memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +/*! + * brief Aborts the current IRQ receive. + * + * note This API can be called when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base SAI base pointer + * param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + /* Stop Tx transfer and disable interrupt */ + SAI_RxEnable(base, false); +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + /* Use FIFO request interrupt and fifo error */ + SAI_RxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFORequestInterruptEnable); +#else + SAI_RxDisableInterrupts(base, kSAI_FIFOErrorInterruptEnable | kSAI_FIFOWarningInterruptEnable); +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + handle->state = kSAI_Idle; + + /* Clear the queue */ + memset(handle->saiQueue, 0, sizeof(sai_transfer_t) * SAI_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +/*! + * brief Terminate all SAI send. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortSend. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + /* Abort the current transfer */ + SAI_TransferAbortSend(base, handle); + + /* Clear all the internal information */ + memset(handle->saiQueue, 0U, sizeof(handle->saiQueue)); + memset(handle->transferSize, 0U, sizeof(handle->transferSize)); + handle->queueUser = 0U; + handle->queueDriver = 0U; +} + +/*! + * brief Terminate all SAI receive. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortReceive. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + /* Abort the current transfer */ + SAI_TransferAbortReceive(base, handle); + + /* Clear all the internal information */ + memset(handle->saiQueue, 0U, sizeof(handle->saiQueue)); + memset(handle->transferSize, 0U, sizeof(handle->transferSize)); + handle->queueUser = 0U; + handle->queueDriver = 0U; +} + +/*! + * brief Tx interrupt handler. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure. + */ +void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; + uint8_t dataSize = (handle->bitWidth / 8U) * handle->channelNums; + + /* Handle Error */ + if (base->TCSR & I2S_TCSR_FEF_MASK) + { + /* Clear FIFO error flag to continue transfer */ + SAI_TxClearStatusFlags(base, kSAI_FIFOErrorFlag); + + /* Reset FIFO for safety */ + SAI_TxSoftwareReset(base, kSAI_ResetTypeFIFO); + + /* Call the callback */ + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_TxError, handle->userData); + } + } + +/* Handle transfer */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if (base->TCSR & I2S_TCSR_FRF_MASK) + { + /* Judge if the data need to transmit is less than space */ + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), + (size_t)((FSL_FEATURE_SAI_FIFO_COUNT - handle->watermark) * dataSize)); + + /* Copy the data from sai buffer to FIFO */ + SAI_WriteNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); + + /* Update the internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#else + if (base->TCSR & I2S_TCSR_FWF_MASK) + { + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); + + SAI_WriteNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); + + /* Update internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* If finished a block, call the callback function */ + if (handle->saiQueue[handle->queueDriver].dataSize == 0U) + { + memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_TxIdle, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->saiQueue[handle->queueDriver].data == NULL) + { + SAI_TransferAbortSend(base, handle); + } +} + +/*! + * brief Tx interrupt handler. + * + * param base SAI base pointer. + * param handle Pointer to the sai_handle_t structure. + */ +void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle) +{ + assert(handle); + + uint8_t *buffer = handle->saiQueue[handle->queueDriver].data; + uint8_t dataSize = (handle->bitWidth / 8U) * handle->channelNums; + + /* Handle Error */ + if (base->RCSR & I2S_RCSR_FEF_MASK) + { + /* Clear FIFO error flag to continue transfer */ + SAI_RxClearStatusFlags(base, kSAI_FIFOErrorFlag); + + /* Reset FIFO for safety */ + SAI_RxSoftwareReset(base, kSAI_ResetTypeFIFO); + + /* Call the callback */ + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_RxError, handle->userData); + } + } + +/* Handle transfer */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if (base->RCSR & I2S_RCSR_FRF_MASK) + { + /* Judge if the data need to transmit is less than space */ + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), (handle->watermark * dataSize)); + + /* Copy the data from sai buffer to FIFO */ + SAI_ReadNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); + + /* Update the internal counter */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#else + if (base->RCSR & I2S_RCSR_FWF_MASK) + { + uint8_t size = MIN((handle->saiQueue[handle->queueDriver].dataSize), dataSize); + + SAI_ReadNonBlocking(base, handle->channel, handle->channelMask, handle->endChannel, handle->bitWidth, buffer, + size); + + /* Update internal state */ + handle->saiQueue[handle->queueDriver].dataSize -= size; + handle->saiQueue[handle->queueDriver].data += size; + } +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* If finished a block, call the callback function */ + if (handle->saiQueue[handle->queueDriver].dataSize == 0U) + { + memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SAI_RxIdle, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->saiQueue[handle->queueDriver].data == NULL) + { + SAI_TransferAbortReceive(base, handle); + } +} + +#if defined(I2S0) +void I2S0_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFORequestFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S0->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[0][1]) && ((I2S0->RCSR & kSAI_FIFOWarningFlag) || (I2S0->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S0->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(I2S0, s_saiHandle[0][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFORequestFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S0->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[0][0]) && ((I2S0->TCSR & kSAI_FIFOWarningFlag) || (I2S0->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S0->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(I2S0, s_saiHandle[0][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S0_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[0][0]); + s_saiTxIsr(I2S0, s_saiHandle[0][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S0_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[0][1]); + s_saiRxIsr(I2S0, s_saiHandle[0][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* I2S0*/ + +#if defined(I2S1) +void I2S1_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((I2S1->RCSR & kSAI_FIFORequestFlag) || (I2S1->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S1->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((I2S1->RCSR & kSAI_FIFOWarningFlag) || (I2S1->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S1->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(I2S1, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((I2S1->TCSR & kSAI_FIFORequestFlag) || (I2S1->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S1->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((I2S1->TCSR & kSAI_FIFOWarningFlag) || (I2S1->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S1->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(I2S1, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S1_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[1][0]); + s_saiTxIsr(I2S1, s_saiHandle[1][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S1_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[1][1]); + s_saiRxIsr(I2S1, s_saiHandle[1][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* I2S1*/ + +#if defined(I2S2) +void I2S2_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][1]) && ((I2S2->RCSR & kSAI_FIFORequestFlag) || (I2S2->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S2->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[2][1]) && ((I2S2->RCSR & kSAI_FIFOWarningFlag) || (I2S2->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S2->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(I2S2, s_saiHandle[2][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][0]) && ((I2S2->TCSR & kSAI_FIFORequestFlag) || (I2S2->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S2->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[2][0]) && ((I2S2->TCSR & kSAI_FIFOWarningFlag) || (I2S2->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S2->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(I2S2, s_saiHandle[2][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S2_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[2][0]); + s_saiTxIsr(I2S2, s_saiHandle[2][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S2_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[2][1]); + s_saiRxIsr(I2S2, s_saiHandle[2][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* I2S2*/ + +#if defined(I2S3) +void I2S3_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][1]) && ((I2S3->RCSR & kSAI_FIFORequestFlag) || (I2S3->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S3->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[3][1]) && ((I2S3->RCSR & kSAI_FIFOWarningFlag) || (I2S3->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S3->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(I2S3, s_saiHandle[3][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][0]) && ((I2S3->TCSR & kSAI_FIFORequestFlag) || (I2S3->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S3->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[3][0]) && ((I2S3->TCSR & kSAI_FIFOWarningFlag) || (I2S3->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S3->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(I2S3, s_saiHandle[3][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S3_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][0]); + s_saiTxIsr(I2S3, s_saiHandle[3][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S3_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][1]); + s_saiRxIsr(I2S3, s_saiHandle[3][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* I2S3*/ + +#if defined(I2S4) +void I2S4_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[4][1]) && ((I2S4->RCSR & kSAI_FIFORequestFlag) || (I2S4->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S4->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S4->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[4][1]) && ((I2S4->RCSR & kSAI_FIFOWarningFlag) || (I2S4->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S4->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S4->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(I2S4, s_saiHandle[4][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[4][0]) && ((I2S4->TCSR & kSAI_FIFORequestFlag) || (I2S4->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S4->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S4->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[4][0]) && ((I2S4->TCSR & kSAI_FIFOWarningFlag) || (I2S4->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S4->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S4->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(I2S4, s_saiHandle[4][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S4_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[4][0]); + s_saiTxIsr(I2S4, s_saiHandle[4][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S4_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[4][1]); + s_saiRxIsr(I2S4, s_saiHandle[4][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ) && (FSL_FEATURE_SAI_SAI5_SAI6_SHARE_IRQ) && defined(I2S5) && \ + defined(I2S6) +void I2S56_DriverIRQHandler(void) +{ + /* use index 5 to get handle when I2S5 & I2S6 share IRQ NUMBER */ + I2S_Type *base = s_saiHandle[5][1]->base; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[5][1]) && base && ((base->RCSR & kSAI_FIFORequestFlag) || (base->RCSR & kSAI_FIFOErrorFlag)) && + ((base->RCSR & kSAI_FIFORequestInterruptEnable) || (base->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[5][1]) && base && ((base->RCSR & kSAI_FIFOWarningFlag) || (base->RCSR & kSAI_FIFOErrorFlag)) && + ((base->RCSR & kSAI_FIFOWarningInterruptEnable) || (base->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(base, s_saiHandle[5][1]); + } + + base = s_saiHandle[5][0]->base; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[5][0]) && base && ((base->TCSR & kSAI_FIFORequestFlag) || (base->TCSR & kSAI_FIFOErrorFlag)) && + ((base->TCSR & kSAI_FIFORequestInterruptEnable) || (base->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[5][0]) && base && ((base->TCSR & kSAI_FIFOWarningFlag) || (base->TCSR & kSAI_FIFOErrorFlag)) && + ((base->TCSR & kSAI_FIFOWarningInterruptEnable) || (base->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(base, s_saiHandle[5][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S56_Tx_DriverIRQHandler(void) +{ + /* use index 5 to get handle when I2S5 & I2S6 share IRQ NUMBER */ + assert(s_saiHandle[5][0]); + s_saiTxIsr(s_saiHandle[5][0]->base, s_saiHandle[5][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S56_Rx_DriverIRQHandler(void) +{ + /* use index 5 to get handle when I2S5 & I2S6 share IRQ NUMBER */ + assert(s_saiHandle[5][1]); + s_saiRxIsr(s_saiHandle[5][1]->base, s_saiHandle[5][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#else + +#if defined(I2S5) +void I2S5_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[5][1]) && ((I2S5->RCSR & kSAI_FIFORequestFlag) || (I2S5->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S5->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S5->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[5][1]) && ((I2S5->RCSR & kSAI_FIFOWarningFlag) || (I2S5->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S5->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S5->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(I2S5, s_saiHandle[5][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[5][0]) && ((I2S5->TCSR & kSAI_FIFORequestFlag) || (I2S5->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S5->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S5->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[5][0]) && ((I2S5->TCSR & kSAI_FIFOWarningFlag) || (I2S5->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S5->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S5->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(I2S5, s_saiHandle[5][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S5_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[5][0]); + s_saiTxIsr(I2S5, s_saiHandle[5][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S5_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[5][1]); + s_saiRxIsr(I2S5, s_saiHandle[5][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(I2S6) +void I2S6_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[6][1]) && ((I2S6->RCSR & kSAI_FIFORequestFlag) || (I2S6->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S6->RCSR & kSAI_FIFORequestInterruptEnable) || (I2S6->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[6][1]) && ((I2S6->RCSR & kSAI_FIFOWarningFlag) || (I2S6->RCSR & kSAI_FIFOErrorFlag)) && + ((I2S6->RCSR & kSAI_FIFOWarningInterruptEnable) || (I2S6->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(I2S6, s_saiHandle[6][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[6][0]) && ((I2S6->TCSR & kSAI_FIFORequestFlag) || (I2S6->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S6->TCSR & kSAI_FIFORequestInterruptEnable) || (I2S6->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[6][0]) && ((I2S6->TCSR & kSAI_FIFOWarningFlag) || (I2S6->TCSR & kSAI_FIFOErrorFlag)) && + ((I2S6->TCSR & kSAI_FIFOWarningInterruptEnable) || (I2S6->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(I2S6, s_saiHandle[6][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S6_Tx_DriverIRQHandler(void) +{ + assert(s_saiHandle[6][0]); + s_saiTxIsr(I2S6, s_saiHandle[6][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void I2S6_Rx_DriverIRQHandler(void) +{ + assert(s_saiHandle[6][1]); + s_saiRxIsr(I2S6, s_saiHandle[6][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif +#endif + +#if defined(AUDIO__SAI0) +void AUDIO_SAI0_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][1]) && + ((AUDIO__SAI0->RCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI0->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI0->RCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[0][1]) && + ((AUDIO__SAI0->RCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI0->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI0->RCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(AUDIO__SAI0, s_saiHandle[0][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][0]) && + ((AUDIO__SAI0->TCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI0->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI0->TCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[0][0]) && + ((AUDIO__SAI0->TCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI0->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI0->TCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(AUDIO__SAI0, s_saiHandle[0][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* AUDIO__SAI0 */ + +#if defined(AUDIO__SAI1) +void AUDIO_SAI1_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && + ((AUDIO__SAI1->RCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI1->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI1->RCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && + ((AUDIO__SAI1->RCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI1->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI1->RCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(AUDIO__SAI1, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && + ((AUDIO__SAI1->TCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI1->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI1->TCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && + ((AUDIO__SAI1->TCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI1->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI1->TCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(AUDIO__SAI1, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* AUDIO__SAI1 */ + +#if defined(AUDIO__SAI2) +void AUDIO_SAI2_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][1]) && + ((AUDIO__SAI2->RCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI2->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI2->RCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[2][1]) && + ((AUDIO__SAI2->RCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI2->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI2->RCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(AUDIO__SAI2, s_saiHandle[2][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][0]) && + ((AUDIO__SAI2->TCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI2->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI2->TCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[2][0]) && + ((AUDIO__SAI2->TCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI2->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI2->TCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(AUDIO__SAI2, s_saiHandle[2][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* AUDIO__SAI2 */ + +#if defined(AUDIO__SAI3) +void AUDIO_SAI3_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][1]) && + ((AUDIO__SAI3->RCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI3->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI3->RCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[3][1]) && + ((AUDIO__SAI3->RCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI3->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI3->RCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(AUDIO__SAI3, s_saiHandle[3][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][0]) && + ((AUDIO__SAI3->TCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI3->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI3->TCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[3][0]) && + ((AUDIO__SAI3->TCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI3->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI3->TCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(AUDIO__SAI3, s_saiHandle[3][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(AUDIO__SAI6) +void AUDIO_SAI6_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[6][1]) && + ((AUDIO__SAI6->RCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI6->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI6->RCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI6->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[6][1]) && + ((AUDIO__SAI6->RCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI6->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI6->RCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI6->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(AUDIO__SAI6, s_saiHandle[6][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[6][0]) && + ((AUDIO__SAI6->TCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI6->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI6->TCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI6->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[6][0]) && + ((AUDIO__SAI6->TCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI6->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI6->TCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI6->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(AUDIO__SAI6, s_saiHandle[6][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* AUDIO__SAI6 */ + +#if defined(AUDIO__SAI7) +void AUDIO_SAI7_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[7][1]) && + ((AUDIO__SAI7->RCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI7->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI7->RCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI7->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[7][1]) && + ((AUDIO__SAI7->RCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI7->RCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI7->RCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI7->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(AUDIO__SAI7, s_saiHandle[7][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[7][0]) && + ((AUDIO__SAI7->TCSR & kSAI_FIFORequestFlag) || (AUDIO__SAI7->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI7->TCSR & kSAI_FIFORequestInterruptEnable) || (AUDIO__SAI7->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[7][0]) && + ((AUDIO__SAI7->TCSR & kSAI_FIFOWarningFlag) || (AUDIO__SAI7->TCSR & kSAI_FIFOErrorFlag)) && + ((AUDIO__SAI7->TCSR & kSAI_FIFOWarningInterruptEnable) || (AUDIO__SAI7->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(AUDIO__SAI7, s_saiHandle[7][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* AUDIO__SAI7 */ + +#if defined(ADMA__SAI0) +void ADMA_SAI0_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI0->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI0->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI0->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI0->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI0, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI0->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI0->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI0->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI0->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI0, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI0 */ + +#if defined(ADMA__SAI1) +void ADMA_SAI1_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI1->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI1->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI1->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI1->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI1, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI1->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI1->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI1->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI1->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI1, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI1 */ + +#if defined(ADMA__SAI2) +void ADMA_SAI2_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI2->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI2->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI2->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI2->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI2, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI2->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI2->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI2->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI2->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI2, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI2 */ + +#if defined(ADMA__SAI3) +void ADMA_SAI3_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI3->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI3->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI3->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI3->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI3, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI3->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI3->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI3->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI3->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI3, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI3 */ + +#if defined(ADMA__SAI4) +void ADMA_SAI4_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI4->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI4->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI4->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI4->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI4, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI4->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI4->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI4->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI4->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI4, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI4 */ + +#if defined(ADMA__SAI5) +void ADMA_SAI5_INT_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((ADMA__SAI5->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI5->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((ADMA__SAI5->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI5->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(ADMA__SAI5, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((ADMA__SAI5->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI5->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((ADMA__SAI5->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorFlag)) && + ((ADMA__SAI5->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(ADMA__SAI5, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* ADMA__SAI5 */ + +#if defined(SAI0) +void SAI0_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][1]) && ((SAI0->RCSR & kSAI_FIFORequestFlag) || (SAI0->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI0->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[0][1]) && ((SAI0->RCSR & kSAI_FIFOWarningFlag) || (SAI0->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI0->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI0->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(SAI0, s_saiHandle[0][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[0][0]) && ((SAI0->TCSR & kSAI_FIFORequestFlag) || (SAI0->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI0->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[0][0]) && ((SAI0->TCSR & kSAI_FIFOWarningFlag) || (SAI0->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI0->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI0->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(AUDIO__SAI0, s_saiHandle[0][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* SAI0 */ + +#if defined(SAI1) +void SAI1_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][1]) && ((SAI1->RCSR & kSAI_FIFORequestFlag) || (SAI1->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI1->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][1]) && ((SAI1->RCSR & kSAI_FIFOWarningFlag) || (SAI1->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI1->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI1->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(SAI1, s_saiHandle[1][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[1][0]) && ((SAI1->TCSR & kSAI_FIFORequestFlag) || (SAI1->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI1->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[1][0]) && ((SAI1->TCSR & kSAI_FIFOWarningFlag) || (SAI1->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI1->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI1->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(SAI1, s_saiHandle[1][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* SAI1 */ + +#if defined(SAI2) +void SAI2_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][1]) && ((SAI2->RCSR & kSAI_FIFORequestFlag) || (SAI2->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI2->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[2][1]) && ((SAI2->RCSR & kSAI_FIFOWarningFlag) || (SAI2->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI2->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI2->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(SAI2, s_saiHandle[2][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[2][0]) && ((SAI2->TCSR & kSAI_FIFORequestFlag) || (SAI2->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI2->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[2][0]) && ((SAI2->TCSR & kSAI_FIFOWarningFlag) || (SAI2->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI2->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI2->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(SAI2, s_saiHandle[2][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* SAI2 */ + +#if defined(SAI3) +void SAI3_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][1]) && ((SAI3->RCSR & kSAI_FIFORequestFlag) || (SAI3->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI3->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[3][1]) && ((SAI3->RCSR & kSAI_FIFOWarningFlag) || (SAI3->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI3->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI3->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(SAI3, s_saiHandle[3][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[3][0]) && ((SAI3->TCSR & kSAI_FIFORequestFlag) || (SAI3->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI3->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[3][0]) && ((SAI3->TCSR & kSAI_FIFOWarningFlag) || (SAI3->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI3->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI3->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(SAI3, s_saiHandle[3][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void SAI3_TX_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][0]); + s_saiTxIsr(SAI3, s_saiHandle[3][0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +void SAI3_RX_DriverIRQHandler(void) +{ + assert(s_saiHandle[3][1]); + s_saiRxIsr(SAI3, s_saiHandle[3][1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* SAI3 */ + +#if defined(SAI4) +void SAI4_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[4][1]) && ((SAI4->RCSR & kSAI_FIFORequestFlag) || (SAI4->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI4->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI4->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[4][1]) && ((SAI4->RCSR & kSAI_FIFOWarningFlag) || (SAI4->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI4->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI4->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(SAI4, s_saiHandle[4][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[4][0]) && ((SAI4->TCSR & kSAI_FIFORequestFlag) || (SAI4->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI4->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI4->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[4][0]) && ((SAI4->TCSR & kSAI_FIFOWarningFlag) || (SAI4->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI4->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI4->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(SAI4, s_saiHandle[4][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* SAI4 */ + +#if defined(SAI5) +void SAI5_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[5][1]) && ((SAI5->RCSR & kSAI_FIFORequestFlag) || (SAI5->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI5->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI5->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[5][1]) && ((SAI5->RCSR & kSAI_FIFOWarningFlag) || (SAI5->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI5->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI5->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(SAI5, s_saiHandle[5][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[5][0]) && ((SAI5->TCSR & kSAI_FIFORequestFlag) || (SAI5->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI5->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI5->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[5][0]) && ((SAI5->TCSR & kSAI_FIFOWarningFlag) || (SAI5->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI5->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI5->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(SAI5, s_saiHandle[5][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* SAI5 */ + +#if defined(SAI6) +void SAI6_DriverIRQHandler(void) +{ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[6][1]) && ((SAI6->RCSR & kSAI_FIFORequestFlag) || (SAI6->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI6->RCSR & kSAI_FIFORequestInterruptEnable) || (SAI6->RCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[6][1]) && ((SAI6->RCSR & kSAI_FIFOWarningFlag) || (SAI6->RCSR & kSAI_FIFOErrorFlag)) && + ((SAI6->RCSR & kSAI_FIFOWarningInterruptEnable) || (SAI6->RCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiRxIsr(SAI6, s_saiHandle[6][1]); + } +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + if ((s_saiHandle[6][0]) && ((SAI6->TCSR & kSAI_FIFORequestFlag) || (SAI6->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI6->TCSR & kSAI_FIFORequestInterruptEnable) || (SAI6->TCSR & kSAI_FIFOErrorInterruptEnable))) +#else + if ((s_saiHandle[6][0]) && ((SAI6->TCSR & kSAI_FIFOWarningFlag) || (SAI6->TCSR & kSAI_FIFOErrorFlag)) && + ((SAI6->TCSR & kSAI_FIFOWarningInterruptEnable) || (SAI6->TCSR & kSAI_FIFOErrorInterruptEnable))) +#endif + { + s_saiTxIsr(SAI6, s_saiHandle[6][0]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* SAI6 */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_sai.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_sai.h new file mode 100644 index 0000000000..6a9c8355f0 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_sai.h @@ -0,0 +1,1555 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SAI_H_ +#define _FSL_SAI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup sai_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1 */ +/*@}*/ + +/*! @brief SAI return status*/ +enum _sai_status_t +{ + kStatus_SAI_TxBusy = MAKE_STATUS(kStatusGroup_SAI, 0), /*!< SAI Tx is busy. */ + kStatus_SAI_RxBusy = MAKE_STATUS(kStatusGroup_SAI, 1), /*!< SAI Rx is busy. */ + kStatus_SAI_TxError = MAKE_STATUS(kStatusGroup_SAI, 2), /*!< SAI Tx FIFO error. */ + kStatus_SAI_RxError = MAKE_STATUS(kStatusGroup_SAI, 3), /*!< SAI Rx FIFO error. */ + kStatus_SAI_QueueFull = MAKE_STATUS(kStatusGroup_SAI, 4), /*!< SAI transfer queue is full. */ + kStatus_SAI_TxIdle = MAKE_STATUS(kStatusGroup_SAI, 5), /*!< SAI Tx is idle */ + kStatus_SAI_RxIdle = MAKE_STATUS(kStatusGroup_SAI, 6) /*!< SAI Rx is idle */ +}; + +/*< sai channel mask value, actual channel numbers is depend soc specific */ +enum _sai_channel_mask +{ + kSAI_Channel0Mask = 1 << 0U, /*!< channel 0 mask value */ + kSAI_Channel1Mask = 1 << 1U, /*!< channel 1 mask value */ + kSAI_Channel2Mask = 1 << 2U, /*!< channel 2 mask value */ + kSAI_Channel3Mask = 1 << 3U, /*!< channel 3 mask value */ + kSAI_Channel4Mask = 1 << 4U, /*!< channel 4 mask value */ + kSAI_Channel5Mask = 1 << 5U, /*!< channel 5 mask value */ + kSAI_Channel6Mask = 1 << 6U, /*!< channel 6 mask value */ + kSAI_Channel7Mask = 1 << 7U, /*!< channel 7 mask value */ +}; + +/*! @brief Define the SAI bus type */ +typedef enum _sai_protocol +{ + kSAI_BusLeftJustified = 0x0U, /*!< Uses left justified format.*/ + kSAI_BusRightJustified, /*!< Uses right justified format. */ + kSAI_BusI2S, /*!< Uses I2S format. */ + kSAI_BusPCMA, /*!< Uses I2S PCM A format.*/ + kSAI_BusPCMB /*!< Uses I2S PCM B format. */ +} sai_protocol_t; + +/*! @brief Master or slave mode */ +typedef enum _sai_master_slave +{ + kSAI_Master = 0x0U, /*!< Master mode include bclk and frame sync */ + kSAI_Slave = 0x1U, /*!< Slave mode include bclk and frame sync */ + kSAI_Bclk_Master_FrameSync_Slave = 0x2U, /*!< bclk in master mode, frame sync in slave mode */ + kSAI_Bclk_Slave_FrameSync_Master = 0x3U, /*!< bclk in slave mode, frame sync in master mode */ +} sai_master_slave_t; + +/*! @brief Mono or stereo audio format */ +typedef enum _sai_mono_stereo +{ + kSAI_Stereo = 0x0U, /*!< Stereo sound. */ + kSAI_MonoRight, /*!< Only Right channel have sound. */ + kSAI_MonoLeft /*!< Only left channel have sound. */ +} sai_mono_stereo_t; + +/*! @brief SAI data order, MSB or LSB */ +typedef enum _sai_data_order +{ + kSAI_DataLSB = 0x0U, /*!< LSB bit transferred first */ + kSAI_DataMSB /*!< MSB bit transferred first */ +} sai_data_order_t; + +/*! @brief SAI clock polarity, active high or low */ +typedef enum _sai_clock_polarity +{ + kSAI_PolarityActiveHigh = 0x0U, /*!< Drive outputs on rising edge */ + kSAI_PolarityActiveLow, /*!< Drive outputs on falling edge */ + kSAI_SampleOnFallingEdge = 0x0U, /*!< Sample inputs on falling edge */ + kSAI_SampleOnRisingEdge /*!< Sample inputs on rising edge */ +} sai_clock_polarity_t; + +/*! @brief Synchronous or asynchronous mode */ +typedef enum _sai_sync_mode +{ + kSAI_ModeAsync = 0x0U, /*!< Asynchronous mode */ + kSAI_ModeSync, /*!< Synchronous mode (with receiver or transmit) */ +#if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) + kSAI_ModeSyncWithOtherTx, /*!< Synchronous with another SAI transmit */ + kSAI_ModeSyncWithOtherRx /*!< Synchronous with another SAI receiver */ +#endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */ +} sai_sync_mode_t; + +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) +/*! @brief Mater clock source */ +typedef enum _sai_mclk_source +{ + kSAI_MclkSourceSysclk = 0x0U, /*!< Master clock from the system clock */ + kSAI_MclkSourceSelect1, /*!< Master clock from source 1 */ + kSAI_MclkSourceSelect2, /*!< Master clock from source 2 */ + kSAI_MclkSourceSelect3 /*!< Master clock from source 3 */ +} sai_mclk_source_t; +#endif + +/*! @brief Bit clock source */ +typedef enum _sai_bclk_source +{ + kSAI_BclkSourceBusclk = 0x0U, /*!< Bit clock using bus clock */ + /* General device bit source definition */ + kSAI_BclkSourceMclkOption1 = 0x1U, /*!< Bit clock MCLK option 1 */ + kSAI_BclkSourceMclkOption2 = 0x2U, /*!< Bit clock MCLK option2 */ + kSAI_BclkSourceMclkOption3 = 0x3U, /*!< Bit clock MCLK option3 */ + /* Kinetis device bit clock source definition */ + kSAI_BclkSourceMclkDiv = 0x1U, /*!< Bit clock using master clock divider */ + kSAI_BclkSourceOtherSai0 = 0x2U, /*!< Bit clock from other SAI device */ + kSAI_BclkSourceOtherSai1 = 0x3U /*!< Bit clock from other SAI device */ +} sai_bclk_source_t; + +/*! @brief The SAI interrupt enable flag */ +enum _sai_interrupt_enable_t +{ + kSAI_WordStartInterruptEnable = + I2S_TCSR_WSIE_MASK, /*!< Word start flag, means the first word in a frame detected */ + kSAI_SyncErrorInterruptEnable = I2S_TCSR_SEIE_MASK, /*!< Sync error flag, means the sync error is detected */ + kSAI_FIFOWarningInterruptEnable = I2S_TCSR_FWIE_MASK, /*!< FIFO warning flag, means the FIFO is empty */ + kSAI_FIFOErrorInterruptEnable = I2S_TCSR_FEIE_MASK, /*!< FIFO error flag */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + kSAI_FIFORequestInterruptEnable = I2S_TCSR_FRIE_MASK, /*!< FIFO request, means reached watermark */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +}; + +/*! @brief The DMA request sources */ +enum _sai_dma_enable_t +{ + kSAI_FIFOWarningDMAEnable = I2S_TCSR_FWDE_MASK, /*!< FIFO warning caused by the DMA request */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + kSAI_FIFORequestDMAEnable = I2S_TCSR_FRDE_MASK, /*!< FIFO request caused by the DMA request */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +}; + +/*! @brief The SAI status flag */ +enum _sai_flags +{ + kSAI_WordStartFlag = I2S_TCSR_WSF_MASK, /*!< Word start flag, means the first word in a frame detected */ + kSAI_SyncErrorFlag = I2S_TCSR_SEF_MASK, /*!< Sync error flag, means the sync error is detected */ + kSAI_FIFOErrorFlag = I2S_TCSR_FEF_MASK, /*!< FIFO error flag */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + kSAI_FIFORequestFlag = I2S_TCSR_FRF_MASK, /*!< FIFO request flag. */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + kSAI_FIFOWarningFlag = I2S_TCSR_FWF_MASK, /*!< FIFO warning flag */ +}; + +/*! @brief The reset type */ +typedef enum _sai_reset_type +{ + kSAI_ResetTypeSoftware = I2S_TCSR_SR_MASK, /*!< Software reset, reset the logic state */ + kSAI_ResetTypeFIFO = I2S_TCSR_FR_MASK, /*!< FIFO reset, reset the FIFO read and write pointer */ + kSAI_ResetAll = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK /*!< All reset. */ +} sai_reset_type_t; + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +/*! + * @brief The SAI packing mode + * The mode includes 8 bit and 16 bit packing. + */ +typedef enum _sai_fifo_packing +{ + kSAI_FifoPackingDisabled = 0x0U, /*!< Packing disabled */ + kSAI_FifoPacking8bit = 0x2U, /*!< 8 bit packing enabled */ + kSAI_FifoPacking16bit = 0x3U /*!< 16bit packing enabled */ +} sai_fifo_packing_t; +#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ + +/*! @brief SAI user configuration structure */ +typedef struct _sai_config +{ + sai_protocol_t protocol; /*!< Audio bus protocol in SAI */ + sai_sync_mode_t syncMode; /*!< SAI sync mode, control Tx/Rx clock sync */ +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + bool mclkOutputEnable; /*!< Master clock output enable, true means master clock divider enabled */ +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + sai_mclk_source_t mclkSource; /*!< Master Clock source */ +#endif /* FSL_FEATURE_SAI_HAS_MCR */ +#endif + sai_bclk_source_t bclkSource; /*!< Bit Clock source */ + sai_master_slave_t masterSlave; /*!< Master or slave */ +} sai_config_t; + +#ifndef SAI_XFER_QUEUE_SIZE +/*!@brief SAI transfer queue size, user can refine it according to use case. */ +#define SAI_XFER_QUEUE_SIZE (4) +#endif + +/*! @brief Audio sample rate */ +typedef enum _sai_sample_rate +{ + kSAI_SampleRate8KHz = 8000U, /*!< Sample rate 8000 Hz */ + kSAI_SampleRate11025Hz = 11025U, /*!< Sample rate 11025 Hz */ + kSAI_SampleRate12KHz = 12000U, /*!< Sample rate 12000 Hz */ + kSAI_SampleRate16KHz = 16000U, /*!< Sample rate 16000 Hz */ + kSAI_SampleRate22050Hz = 22050U, /*!< Sample rate 22050 Hz */ + kSAI_SampleRate24KHz = 24000U, /*!< Sample rate 24000 Hz */ + kSAI_SampleRate32KHz = 32000U, /*!< Sample rate 32000 Hz */ + kSAI_SampleRate44100Hz = 44100U, /*!< Sample rate 44100 Hz */ + kSAI_SampleRate48KHz = 48000U, /*!< Sample rate 48000 Hz */ + kSAI_SampleRate96KHz = 96000U, /*!< Sample rate 96000 Hz */ + kSAI_SampleRate192KHz = 192000U, /*!< Sample rate 192000 Hz */ + kSAI_SampleRate384KHz = 384000U, /*!< Sample rate 384000 Hz */ +} sai_sample_rate_t; + +/*! @brief Audio word width */ +typedef enum _sai_word_width +{ + kSAI_WordWidth8bits = 8U, /*!< Audio data width 8 bits */ + kSAI_WordWidth16bits = 16U, /*!< Audio data width 16 bits */ + kSAI_WordWidth24bits = 24U, /*!< Audio data width 24 bits */ + kSAI_WordWidth32bits = 32U /*!< Audio data width 32 bits */ +} sai_word_width_t; + +#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE +/*! @brief sai data pin state definition */ +typedef enum _sai_data_pin_state +{ + kSAI_DataPinStateTriState = + 0U, /*!< transmit data pins are tri-stated when slots are masked or channels are disabled */ + kSAI_DataPinStateOutputZero = 1U, /*!< transmit data pins are never tri-stated and will output zero when slots + are masked or channel disabled */ +} sai_data_pin_state_t; +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE +/*! @brief sai fifo combine mode definition */ +typedef enum _sai_fifo_combine +{ + kSAI_FifoCombineDisabled = 0U, /*!< sai fifo combine mode disabled */ + kSAI_FifoCombineModeEnabledOnRead, /*!< sai fifo combine mode enabled on FIFO reads */ + kSAI_FifoCombineModeEnabledOnWrite, /*!< sai fifo combine mode enabled on FIFO write */ + kSAI_FifoCombineModeEnabledOnReadWrite, /*!< sai fifo combined mode enabled on FIFO read/writes */ +} sai_fifo_combine_t; +#endif + +/*! @brief sai transceiver type */ +typedef enum _sai_transceiver_type +{ + kSAI_Transmitter = 0U, /*!< sai transmitter */ + kSAI_Receiver = 1U, /*!< sai receiver */ +} sai_transceiver_type_t; + +/*! @brief sai frame sync len */ +typedef enum _sai_frame_sync_len +{ + kSAI_FrameSyncLenOneBitClk = 0U, /*!< 1 bit clock frame sync len for DSP mode */ + kSAI_FrameSyncLenPerWordWidth = 1U, /*!< Frame sync length decided by word width */ +} sai_frame_sync_len_t; + +/*! @brief sai transfer format */ +typedef struct _sai_transfer_format +{ + uint32_t sampleRate_Hz; /*!< Sample rate of audio data */ + uint32_t bitWidth; /*!< Data length of audio data, usually 8/16/24/32 bits */ + sai_mono_stereo_t stereo; /*!< Mono or stereo */ +#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) + uint32_t masterClockHz; /*!< Master clock frequency in Hz */ +#endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + uint8_t watermark; /*!< Watermark value */ +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ + + /* for the multi channel usage, user can provide channelMask Oonly, then sai driver will handle + * other parameter carefully, such as + * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask + * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated. + * for the single channel usage, user can provide channel or channel mask only, such as, + * channel = 0 or channelMask = kSAI_Channel0Mask. + */ + uint8_t channel; /*!< Transfer start channel */ + uint8_t channelMask; /*!< enabled channel mask value, reference _sai_channel_mask */ + uint8_t endChannel; /*!< end channel number */ + uint8_t channelNums; /*!< Total enabled channel numbers */ + + sai_protocol_t protocol; /*!< Which audio protocol used */ + bool isFrameSyncCompact; /*!< True means Frame sync length is configurable according to bitWidth, false means frame + sync length is 64 times of bit clock. */ +} sai_transfer_format_t; + +#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) +/*! @brief master clock configurations */ +typedef struct _sai_master_clock +{ +#if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR) + bool mclkOutputEnable; /*!< master clock output enable */ +#if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS)) + sai_mclk_source_t mclkSource; /*!< Master Clock source */ +#endif +#endif + +#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) + uint32_t mclkHz; /*!< target mclk frequency */ + uint32_t mclkSourceClkHz; /*!< mclk source frequency*/ +#endif +} sai_master_clock_t; +#endif + +/*! @brief sai fifo configurations */ +typedef struct _sai_fifo +{ +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR + bool fifoContinueOneError; /*!< fifo continues when error occur */ +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_COMBINE + sai_fifo_combine_t fifoCombine; /*!< fifo combine mode */ +#endif + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING + sai_fifo_packing_t fifoPacking; /*!< fifo packing mode */ +#endif +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + uint8_t fifoWatermark; /*!< fifo watermark */ +#endif +} sai_fifo_t; + +/*! @brief sai bit clock configurations */ +typedef struct _sai_bit_clock +{ + bool bclkSrcSwap; /*!< bit clock source swap */ + bool bclkInputDelay; /*!< bit clock actually used by the transmitter is delayed by the pad output delay, + this has effect of decreasing the data input setup time, but increasing the data output valid + time .*/ + sai_clock_polarity_t bclkPolarity; /*!< bit clock polarity */ + sai_bclk_source_t bclkSource; /*!< bit Clock source */ +} sai_bit_clock_t; + +/*! @brief sai frame sync configurations */ +typedef struct _sai_frame_sync +{ + uint8_t frameSyncWidth; /*!< frame sync width in number of bit clocks */ + bool frameSyncEarly; /*!< TRUE is frame sync assert one bit before the first bit of frame + FALSE is frame sync assert with the first bit of the frame */ + +#if defined(FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND) && FSL_FEATURE_SAI_HAS_FRAME_SYNC_ON_DEMAND + bool frameSyncGenerateOnDemand; /*!< internal frame sync is generated when FIFO waring flag is clear */ +#endif + + sai_clock_polarity_t frameSyncPolarity; /*!< frame sync polarity */ + +} sai_frame_sync_t; + +/*! @brief sai serial data configurations */ +typedef struct _sai_serial_data +{ +#if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE + sai_data_pin_state_t dataMode; /*!< sai data pin state when slots masked or channel disabled */ +#endif + + sai_data_order_t dataOrder; /*!< configure whether the LSB or MSB is transmitted first */ + uint8_t dataWord0Length; /*!< configure the number of bits in the first word in each frame */ + uint8_t dataWordNLength; /*!< configure the number of bits in the each word in each frame, except the first word */ + uint8_t dataWordLength; /*!< used to record the data length for dma transfer */ + uint8_t + dataFirstBitShifted; /*!< Configure the bit index for the first bit transmitted for each word in the frame */ + uint8_t dataWordNum; /*!< configure the number of words in each frame */ + uint32_t dataMaskedWord; /*!< configure whether the transmit word is masked */ +} sai_serial_data_t; + +/*! @brief sai transceiver configurations */ +typedef struct _sai_transceiver +{ + sai_serial_data_t serialData; /*!< serial data configurations */ + sai_frame_sync_t frameSync; /*!< ws configurations */ + sai_bit_clock_t bitClock; /*!< bit clock configurations */ + sai_fifo_t fifo; /*!< fifo configurations */ + + sai_master_slave_t masterSlave; /*!< transceiver is master or slave */ + + sai_sync_mode_t syncMode; /*!< transceiver sync mode */ + + uint8_t startChannel; /*!< Transfer start channel */ + uint8_t channelMask; /*!< enabled channel mask value, reference _sai_channel_mask */ + uint8_t endChannel; /*!< end channel number */ + uint8_t channelNums; /*!< Total enabled channel numbers */ + +} sai_transceiver_t; + +/*! @brief SAI transfer structure */ +typedef struct _sai_transfer +{ + uint8_t *data; /*!< Data start address to transfer. */ + size_t dataSize; /*!< Transfer size. */ +} sai_transfer_t; + +typedef struct _sai_handle sai_handle_t; + +/*! @brief SAI transfer callback prototype */ +typedef void (*sai_transfer_callback_t)(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData); + +/*! @brief SAI handle structure */ +struct _sai_handle +{ + I2S_Type *base; /*!< base address */ + + uint32_t state; /*!< Transfer status */ + sai_transfer_callback_t callback; /*!< Callback function called at transfer event*/ + void *userData; /*!< Callback parameter passed to callback function*/ + uint8_t bitWidth; /*!< Bit width for transfer, 8/16/24/32 bits */ + + /* for the multi channel usage, user can provide channelMask Oonly, then sai driver will handle + * other parameter carefully, such as + * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask + * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated. + * for the single channel usage, user can provide channel or channel mask only, such as, + * channel = 0 or channelMask = kSAI_Channel0Mask. + */ + uint8_t channel; /*!< Transfer start channel */ + uint8_t channelMask; /*!< enabled channel mask value, refernece _sai_channel_mask */ + uint8_t endChannel; /*!< end channel number */ + uint8_t channelNums; /*!< Total enabled channel numbers */ + + sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ + size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + uint8_t watermark; /*!< Watermark value */ +#endif +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the SAI Tx peripheral. + * @deprecated Do not use this function. It has been superceded by @ref SAI_Init + * + * Ungates the SAI clock, resets the module, and configures SAI Tx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_TxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAIM module can cause a hard fault + * because the clock is not enabled. + * + * @param base SAI base pointer + * @param config SAI configuration structure. + */ +void SAI_TxInit(I2S_Type *base, const sai_config_t *config); + +/*! + * @brief Initializes the SAI Rx peripheral. + * @deprecated Do not use this function. It has been superceded by @ref SAI_Init + * + * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SAI_RxGetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the SAI driver. Otherwise, accessing the SAI module can cause a hard fault + * because the clock is not enabled. + * + * @param base SAI base pointer + * @param config SAI configuration structure. + */ +void SAI_RxInit(I2S_Type *base, const sai_config_t *config); + +/*! + * @brief Sets the SAI Tx configuration structure to default values. + * @deprecated Do not use this function. It has been superceded by @ref + * SAI_GetClassicI2SConfig/SAI_GetLeftJustifiedConfig/SAI_GetRightJustifiedConfig/SAI_GetDSPConfig/SAI_GetTDMConfig + * + * This API initializes the configuration structure for use in SAI_TxConfig(). + * The initialized structure can remain unchanged in SAI_TxConfig(), or it can be modified + * before calling SAI_TxConfig(). + * This is an example. + @code + sai_config_t config; + SAI_TxGetDefaultConfig(&config); + @endcode + * + * @param config pointer to master configuration structure + */ +void SAI_TxGetDefaultConfig(sai_config_t *config); + +/*! + * @brief Sets the SAI Rx configuration structure to default values. + * @deprecated Do not use this function. It has been superceded by @ref + * SAI_GetClassicI2SConfig/SAI_GetLeftJustifiedConfig/SAI_GetRightJustifiedConfig/SAI_GetDSPConfig/SAI_GetTDMConfig + * + * This API initializes the configuration structure for use in SAI_RxConfig(). + * The initialized structure can remain unchanged in SAI_RxConfig() or it can be modified + * before calling SAI_RxConfig(). + * This is an example. + @code + sai_config_t config; + SAI_RxGetDefaultConfig(&config); + @endcode + * + * @param config pointer to master configuration structure + */ +void SAI_RxGetDefaultConfig(sai_config_t *config); + +/*! + * @brief Initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_Init is called to enable the clock. + * + * @param base SAI base pointer. + */ +void SAI_Init(I2S_Type *base); + +/*! + * @brief De-initializes the SAI peripheral. + * + * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit + * or SAI_RxInit is called to enable the clock. + * + * @param base SAI base pointer. + */ +void SAI_Deinit(I2S_Type *base); + +/*! + * @brief Resets the SAI Tx. + * + * This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit. + * + * @param base SAI base pointer + */ +void SAI_TxReset(I2S_Type *base); + +/*! + * @brief Resets the SAI Rx. + * + * This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit. + * + * @param base SAI base pointer + */ +void SAI_RxReset(I2S_Type *base); + +/*! + * @brief Enables/disables the SAI Tx. + * + * @param base SAI base pointer. + * @param enable True means enable SAI Tx, false means disable. + */ +void SAI_TxEnable(I2S_Type *base, bool enable); + +/*! + * @brief Enables/disables the SAI Rx. + * + * @param base SAI base pointer. + * @param enable True means enable SAI Rx, false means disable. + */ +void SAI_RxEnable(I2S_Type *base, bool enable); + +/*! + * @brief Set Rx bit clock direction. + * + * Select bit clock direction, master or slave. + * + * @param base SAI base pointer. + * @param masterSlave reference sai_master_slave_t. + */ +static inline void SAI_TxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave) +{ + if (masterSlave == kSAI_Master) + { + base->TCR2 |= I2S_TCR2_BCD_MASK; + } + else + { + base->TCR2 &= ~I2S_TCR2_BCD_MASK; + } +} + +/*! + * @brief Set Rx bit clock direction. + * + * Select bit clock direction, master or slave. + * + * @param base SAI base pointer. + * @param masterSlave reference sai_master_slave_t. + */ +static inline void SAI_RxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave) +{ + if (masterSlave == kSAI_Master) + { + base->RCR2 |= I2S_RCR2_BCD_MASK; + } + else + { + base->RCR2 &= ~I2S_RCR2_BCD_MASK; + } +} + +/*! + * @brief Set Rx frame sync direction. + * + * Select frame sync direction, master or slave. + * + * @param base SAI base pointer. + * @param masterSlave reference sai_master_slave_t. + */ +static inline void SAI_RxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave) +{ + if (masterSlave == kSAI_Master) + { + base->RCR4 |= I2S_RCR4_FSD_MASK; + } + else + { + base->RCR4 &= ~I2S_RCR4_FSD_MASK; + } +} + +/*! + * @brief Set Tx frame sync direction. + * + * Select frame sync direction, master or slave. + * + * @param base SAI base pointer. + * @param masterSlave reference sai_master_slave_t. + */ +static inline void SAI_TxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave) +{ + if (masterSlave == kSAI_Master) + { + base->TCR4 |= I2S_TCR4_FSD_MASK; + } + else + { + base->TCR4 &= ~I2S_TCR4_FSD_MASK; + } +} + +/*! + * @brief Transmitter bit clock rate configurations. + * + * @param base SAI base pointer. + * @param sourceClockHz, bit clock source frequency. + * @param sampleRate audio data sample rate. + * @param bitWidth, audio data bitWidth. + * @param channelNumbers, audio channel numbers. + */ +void SAI_TxSetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers); + +/*! + * @brief Receiver bit clock rate configurations. + * + * @param base SAI base pointer. + * @param sourceClockHz, bit clock source frequency. + * @param sampleRate audio data sample rate. + * @param bitWidth, audio data bitWidth. + * @param channelNumbers, audio channel numbers. + */ +void SAI_RxSetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers); + +/*! + * @brief Transmitter Bit clock configurations. + * + * @param base SAI base pointer. + * @param masterSlave master or slave. + * @param config bit clock other configurations, can be NULL in slave mode. + */ +void SAI_TxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config); + +/*! + * @brief Receiver Bit clock configurations. + * + * @param base SAI base pointer. + * @param masterSlave master or slave. + * @param config bit clock other configurations, can be NULL in slave mode. + */ +void SAI_RxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config); + +#if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \ + (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) +/*! + * @brief Master clock configurations. + * + * @param base SAI base pointer. + * @param config master clock configurations. + */ +void SAI_SetMasterClockConfig(I2S_Type *base, sai_master_clock_t *config); +#endif + +/*! + * @brief SAI transmitter fifo configurations. + * + * @param base SAI base pointer. + * @param config fifo configurations. + */ +void SAI_TxSetFifoConfig(I2S_Type *base, sai_fifo_t *config); + +/*! + * @brief SAI receiver fifo configurations. + * + * @param base SAI base pointer. + * @param config fifo configurations. + */ +void SAI_RxSetFifoConfig(I2S_Type *base, sai_fifo_t *config); + +/*! + * @brief SAI transmitter Frame sync configurations. + * + * @param base SAI base pointer. + * @param masterSlave master or slave. + * @param config frame sync configurations, can be NULL in slave mode. + */ +void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config); + +/*! + * @brief SAI receiver Frame sync configurations. + * + * @param base SAI base pointer. + * @param masterSlave master or slave. + * @param config frame sync configurations, can be NULL in slave mode. + */ +void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config); + +/*! + * @brief SAI transmitter Serial data configurations. + * + * @param base SAI base pointer. + * @param config serial data configurations. + */ +void SAI_TxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config); + +/*! + * @brief SAI receiver Serial data configurations. + * + * @param base SAI base pointer. + * @param config serial data configurations. + */ +void SAI_RxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config); + +/*! + * @brief SAI transmitter configurations. + * + * @param base SAI base pointer. + * @param config transmitter configurations. + */ +void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config); + +/*! + * @brief SAI receiver configurations. + * + * @param base SAI base pointer. + * @param config receiver configurations. + */ +void SAI_RxSetConfig(I2S_Type *base, sai_transceiver_t *config); + +/*! + * @brief Get classic I2S mode configurations. + * + * @param config transceiver configurations. + * @param bitWidth audio data bitWidth. + * @param mode audio data channel. + * @param saiChannelMask mask value of the channel to be enable. + */ +void SAI_GetClassicI2SConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); + +/*! + * @brief Get left justified mode configurations. + * + * @param config transceiver configurations. + * @param bitWidth audio data bitWidth. + * @param mode audio data channel. + * @param saiChannelMask mask value of the channel to be enable. + */ +void SAI_GetLeftJustifiedConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); + +/*! + * @brief Get right justified mode configurations. + * + * @param config transceiver configurations. + * @param bitWidth audio data bitWidth. + * @param mode audio data channel. + * @param saiChannelMask mask value of the channel to be enable. + */ +void SAI_GetRightJustifiedConfig(sai_transceiver_t *config, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); + +/*! + * @brief Get TDM mode configurations. + * + * @param config transceiver configurations. + * @param frameSyncWidth length of frame sync. + * @param bitWidth audio data word width. + * @param dataWordNum word number in one frame. + * @param saiChannelMask mask value of the channel to be enable. + */ +void SAI_GetTDMConfig(sai_transceiver_t *config, + sai_frame_sync_len_t frameSyncWidth, + sai_word_width_t bitWidth, + uint32_t dataWordNum, + uint32_t saiChannelMask); + +/*! + * @brief Get DSP mode configurations. + * + * @param config transceiver configurations. + * @param frameSyncWidth length of frame sync. + * @param bitWidth audio data bitWidth. + * @param mode audio data channel. + * @param saiChannelMask mask value of the channel to enable. + */ +void SAI_GetDSPConfig(sai_transceiver_t *config, + sai_frame_sync_len_t frameSyncWidth, + sai_word_width_t bitWidth, + sai_mono_stereo_t mode, + uint32_t saiChannelMask); +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the SAI Tx status flag state. + * + * @param base SAI base pointer + * @return SAI Tx status flag value. Use the Status Mask to get the status value needed. + */ +static inline uint32_t SAI_TxGetStatusFlag(I2S_Type *base) +{ + return base->TCSR; +} + +/*! + * @brief Clears the SAI Tx status flag state. + * + * @param base SAI base pointer + * @param mask State mask. It can be a combination of the following source if defined: + * @arg kSAI_WordStartFlag + * @arg kSAI_SyncErrorFlag + * @arg kSAI_FIFOErrorFlag + */ +static inline void SAI_TxClearStatusFlags(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Gets the SAI Tx status flag state. + * + * @param base SAI base pointer + * @return SAI Rx status flag value. Use the Status Mask to get the status value needed. + */ +static inline uint32_t SAI_RxGetStatusFlag(I2S_Type *base) +{ + return base->RCSR; +} + +/*! + * @brief Clears the SAI Rx status flag state. + * + * @param base SAI base pointer + * @param mask State mask. It can be a combination of the following sources if defined. + * @arg kSAI_WordStartFlag + * @arg kSAI_SyncErrorFlag + * @arg kSAI_FIFOErrorFlag + */ +static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Do software reset or FIFO reset . + * + * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. + * Software reset means clear the Tx internal logic, including the bit clock, frame count etc. But software + * reset will not clear any configuration registers like TCR1~TCR5. + * This function will also clear all the error flags such as FIFO error, sync error etc. + * + * @param base SAI base pointer + * @param type Reset type, FIFO reset or software reset + */ +void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t type); + +/*! + * @brief Do software reset or FIFO reset . + * + * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0. + * Software reset means clear the Rx internal logic, including the bit clock, frame count etc. But software + * reset will not clear any configuration registers like RCR1~RCR5. + * This function will also clear all the error flags such as FIFO error, sync error etc. + * + * @param base SAI base pointer + * @param type Reset type, FIFO reset or software reset + */ +void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t type); + +/*! + * @brief Set the Tx channel FIFO enable mask. + * + * @param base SAI base pointer + * @param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, + * 3 means both channel 0 and channel 1 enabled. + */ +void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask); + +/*! + * @brief Set the Rx channel FIFO enable mask. + * + * @param base SAI base pointer + * @param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled, + * 3 means both channel 0 and channel 1 enabled. + */ +void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask); + +/*! + * @brief Set the Tx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order); + +/*! + * @brief Set the Rx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order); + +/*! + * @brief Set the Tx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +/*! + * @brief Set the Rx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +/*! + * @brief Set the Tx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +/*! + * @brief Set the Rx data order. + * + * @param base SAI base pointer + * @param order Data order MSB or LSB + */ +void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity); + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING +/*! + * @brief Set Tx FIFO packing feature. + * + * @param base SAI base pointer. + * @param pack FIFO pack type. It is element of sai_fifo_packing_t. + */ +void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack); + +/*! + * @brief Set Rx FIFO packing feature. + * + * @param base SAI base pointer. + * @param pack FIFO pack type. It is element of sai_fifo_packing_t. + */ +void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack); +#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */ + +#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR +/*! + * @brief Set Tx FIFO error continue. + * + * FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature + * not enabled, SAI will hang and users need to clear FEF flag in TCSR register. + * + * @param base SAI base pointer. + * @param isEnabled Is FIFO error continue enabled, true means enable, false means disable. + */ +static inline void SAI_TxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled) +{ + if (isEnabled) + { + base->TCR4 |= I2S_TCR4_FCONT_MASK; + } + else + { + base->TCR4 &= ~I2S_TCR4_FCONT_MASK; + } +} + +/*! + * @brief Set Rx FIFO error continue. + * + * FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature + * not enabled, SAI will hang and users need to clear FEF flag in RCSR register. + * + * @param base SAI base pointer. + * @param isEnabled Is FIFO error continue enabled, true means enable, false means disable. + */ +static inline void SAI_RxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled) +{ + if (isEnabled) + { + base->RCR4 |= I2S_RCR4_FCONT_MASK; + } + else + { + base->RCR4 &= ~I2S_RCR4_FCONT_MASK; + } +} +#endif + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the SAI Tx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_TxEnableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Enables the SAI Rx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_RxEnableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); +} + +/*! + * @brief Disables the SAI Tx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_TxDisableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask)); +} + +/*! + * @brief Disables the SAI Rx interrupt requests. + * + * @param base SAI base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_WordStartInterruptEnable + * @arg kSAI_SyncErrorInterruptEnable + * @arg kSAI_FIFOWarningInterruptEnable + * @arg kSAI_FIFORequestInterruptEnable + * @arg kSAI_FIFOErrorInterruptEnable + */ +static inline void SAI_RxDisableInterrupts(I2S_Type *base, uint32_t mask) +{ + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask)); +} + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables the SAI Tx DMA requests. + * @param base SAI base pointer + * @param mask DMA source + * The parameter can be combination of the following sources if defined. + * @arg kSAI_FIFOWarningDMAEnable + * @arg kSAI_FIFORequestDMAEnable + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void SAI_TxEnableDMA(I2S_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask); + } + else + { + base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask)); + } +} + +/*! + * @brief Enables/disables the SAI Rx DMA requests. + * @param base SAI base pointer + * @param mask DMA source + * The parameter can be a combination of the following sources if defined. + * @arg kSAI_FIFOWarningDMAEnable + * @arg kSAI_FIFORequestDMAEnable + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask); + } + else + { + base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask)); + } +} + +/*! + * @brief Gets the SAI Tx data register address. + * + * This API is used to provide a transfer address for the SAI DMA transfer configuration. + * + * @param base SAI base pointer. + * @param channel Which data channel used. + * @return data register address. + */ +static inline uint32_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) +{ + return (uint32_t)(&(base->TDR)[channel]); +} + +/*! + * @brief Gets the SAI Rx data register address. + * + * This API is used to provide a transfer address for the SAI DMA transfer configuration. + * + * @param base SAI base pointer. + * @param channel Which data channel used. + * @return data register address. + */ +static inline uint32_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel) +{ + return (uint32_t)(&(base->RDR)[channel]); +} + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Configures the SAI Tx audio format. + * @deprecated Do not use this function. It has been superceded by @ref SAI_TxSetConfig + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param format Pointer to the SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master + * clock, this value should equal the masterClockHz. + */ +void SAI_TxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Configures the SAI Rx audio format. + * @deprecated Do not use this function. It has been superceded by @ref SAI_RxSetConfig + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param format Pointer to the SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If the bit clock source is a master + * clock, this value should equal the masterClockHz. + */ +void SAI_RxSetFormat(I2S_Type *base, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Sends data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Sends data to multi channel using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param channelMask channel mask. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +void SAI_WriteMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Writes data into SAI FIFO. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param data Data needs to be written. + */ +static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data) +{ + base->TDR[channel] = data; +} + +/*! + * @brief Receives data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Receives multi channel data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @param channelMask channel mask. + * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +void SAI_ReadMultiChannelBlocking( + I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size); + +/*! + * @brief Reads data from the SAI FIFO. + * + * @param base SAI base pointer. + * @param channel Data channel used. + * @return Data in SAI FIFO. + */ +static inline uint32_t SAI_ReadData(I2S_Type *base, uint32_t channel) +{ + return base->RDR[channel]; +} + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the SAI Tx handle. + * + * This function initializes the Tx handle for the SAI Tx transactional APIs. Call + * this function once to get the handle initialized. + * + * @param base SAI base pointer + * @param handle SAI handle pointer. + * @param callback Pointer to the user callback function. + * @param userData User parameter passed to the callback function + */ +void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData); + +/*! + * @brief Initializes the SAI Rx handle. + * + * This function initializes the Rx handle for the SAI Rx transactional APIs. Call + * this function once to get the handle initialized. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param callback Pointer to the user callback function. + * @param userData User parameter passed to the callback function. + */ +void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData); + +/*! + * @brief SAI transmitter transfer configurations. + * + * This function initializes the Tx, include bit clock, frame sync, master clock, serial data and fifo + * configurations. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param config tranmitter configurations. + */ +void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config); + +/*! + * @brief SAI receiver transfer configurations. + * + * This function initializes the Rx, include bit clock, frame sync, master clock, serial data and fifo + * configurations. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param config receiver configurations. + */ +void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config); + +/*! + * @brief Configures the SAI Tx audio format. + * @deprecated Do not use this function. It has been superceded by @ref SAI_TxSetTransferConfig + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param format Pointer to the SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master + * clock, this value should equal the masterClockHz in format. + * @return Status of this function. Return value is the status_t. + */ +status_t SAI_TransferTxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Configures the SAI Rx audio format. + * @deprecated Do not use this function. It has been superceded by @ref SAI_RxSetTransferConfig + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SAI base pointer. + * @param handle SAI handle pointer. + * @param format Pointer to the SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is a master + * clock, this value should equal the masterClockHz in format. + * @return Status of this function. Return value is one of status_t. + */ +status_t SAI_TransferRxSetFormat(I2S_Type *base, + sai_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Performs an interrupt non-blocking send transfer on SAI. + * + * @note This API returns immediately after the transfer initiates. + * Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param xfer Pointer to the sai_transfer_t structure. + * @retval kStatus_Success Successfully started the data receive. + * @retval kStatus_SAI_TxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Performs an interrupt non-blocking receive transfer on SAI. + * + * @note This API returns immediately after the transfer initiates. + * Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer + * is finished. + * + * @param base SAI base pointer + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param xfer Pointer to the sai_transfer_t structure. + * @retval kStatus_Success Successfully started the data receive. + * @retval kStatus_SAI_RxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Gets a set byte count. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param count Bytes count sent. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count); + +/*! + * @brief Gets a received byte count. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + * @param count Bytes count received. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count); + +/*! + * @brief Aborts the current send. + * + * @note This API can be called any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Aborts the current IRQ receive. + * + * @note This API can be called when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base SAI base pointer + * @param handle Pointer to the sai_handle_t structure which stores the transfer state. + */ +void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Terminate all SAI send. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortSend. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Terminate all SAI receive. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortReceive. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Tx interrupt handler. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure. + */ +void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle); + +/*! + * @brief Tx interrupt handler. + * + * @param base SAI base pointer. + * @param handle Pointer to the sai_handle_t structure. + */ +void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + +/*! @} */ + +#endif /* _FSL_SAI_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_sai_edma.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_sai_edma.c new file mode 100644 index 0000000000..6fb16e06f2 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_sai_edma.c @@ -0,0 +1,692 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sai_edma.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.sai_edma" +#endif + +/******************************************************************************* + * Definitations + ******************************************************************************/ +/* Used for 32byte aligned */ +#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)(address) + 32) & ~0x1FU) + +static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS; + +/*handle; + + /* If finished a block, call the callback function */ + memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t)); + saiHandle->queueDriver = (saiHandle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (saiHandle->callback) + { + (saiHandle->callback)(privHandle->base, saiHandle, kStatus_SAI_TxIdle, saiHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (saiHandle->saiQueue[saiHandle->queueDriver].data == NULL) + { + /* Disable DMA enable bit */ + SAI_TxEnableDMA(privHandle->base, kSAI_FIFORequestDMAEnable, false); + EDMA_AbortTransfer(handle); + } +} + +static void SAI_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) +{ + sai_edma_private_handle_t *privHandle = (sai_edma_private_handle_t *)userData; + sai_edma_handle_t *saiHandle = privHandle->handle; + + /* If finished a block, call the callback function */ + memset(&saiHandle->saiQueue[saiHandle->queueDriver], 0, sizeof(sai_transfer_t)); + saiHandle->queueDriver = (saiHandle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + if (saiHandle->callback) + { + (saiHandle->callback)(privHandle->base, saiHandle, kStatus_SAI_RxIdle, saiHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (saiHandle->saiQueue[saiHandle->queueDriver].data == NULL) + { + /* Disable DMA enable bit */ + SAI_RxEnableDMA(privHandle->base, kSAI_FIFORequestDMAEnable, false); + EDMA_AbortTransfer(handle); + } +} + +/*! + * brief Initializes the SAI eDMA handle. + * + * This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs. + * Usually, for a specified SAI instance, call this API once to get the initialized handle. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param base SAI peripheral base address. + * param callback Pointer to user callback function. + * param userData User parameter passed to the callback function. + * param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ +void SAI_TransferTxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle) +{ + assert(handle && dmaHandle); + + uint32_t instance = SAI_GetInstance(base); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + /* Set sai base to handle */ + handle->dmaHandle = dmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set SAI state to idle */ + handle->state = kSAI_Idle; + + s_edmaPrivateHandle[instance][0].base = base; + s_edmaPrivateHandle[instance][0].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(dmaHandle, (edma_tcd_t *)(STCD_ADDR(handle->tcd)), SAI_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel */ + EDMA_SetCallback(dmaHandle, SAI_TxEDMACallback, &s_edmaPrivateHandle[instance][0]); +} + +/*! + * brief Initializes the SAI Rx eDMA handle. + * + * This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs. + * Usually, for a specified SAI instance, call this API once to get the initialized handle. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param base SAI peripheral base address. + * param callback Pointer to user callback function. + * param userData User parameter passed to the callback function. + * param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ +void SAI_TransferRxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle) +{ + assert(handle && dmaHandle); + + uint32_t instance = SAI_GetInstance(base); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + /* Set sai base to handle */ + handle->dmaHandle = dmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Set SAI state to idle */ + handle->state = kSAI_Idle; + + s_edmaPrivateHandle[instance][1].base = base; + s_edmaPrivateHandle[instance][1].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(dmaHandle, STCD_ADDR(handle->tcd), SAI_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel */ + EDMA_SetCallback(dmaHandle, SAI_RxEDMACallback, &s_edmaPrivateHandle[instance][1]); +} + +/*! + * brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param format Pointer to SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master + * clock, this value should equals to masterClockHz in format. + * retval kStatus_Success Audio format set successfully. + * retval kStatus_InvalidArgument The input argument is invalid. + */ +void SAI_TransferTxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle && format); + + /* Configure the audio format to SAI registers */ + SAI_TxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + /* Get the transfer size from format, this should be used in EDMA configuration */ + if (format->bitWidth == 24U) + { + handle->bytesPerFrame = 4U; + } + else + { + handle->bytesPerFrame = format->bitWidth / 8U; + } + + /* Update the data channel SAI used */ + handle->channel = format->channel; + + /* Clear the channel enable bits until do a send/receive */ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->count = FSL_FEATURE_SAI_FIFO_COUNT - format->watermark; +#else + handle->count = 1U; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +/*! + * @brief Configures the SAI Tx. + * + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param saiConfig sai configurations. + */ +void SAI_TransferTxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig) +{ + assert(handle && saiConfig); + + /* Configure the audio format to SAI registers */ + SAI_TxSetConfig(base, saiConfig); + + /* Get the transfer size from format, this should be used in EDMA configuration */ + if (saiConfig->serialData.dataWordLength == 24U) + { + handle->bytesPerFrame = 4U; + } + else + { + handle->bytesPerFrame = saiConfig->serialData.dataWordLength / 8U; + } + /* Update the data channel SAI used */ + handle->channel = saiConfig->startChannel; + + /* Clear the channel enable bits until do a send/receive */ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->count = FSL_FEATURE_SAI_FIFO_COUNT - saiConfig->fifo.fifoWatermark; +#else + handle->count = 1U; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +/*! + * brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param format Pointer to SAI audio data format structure. + * param mclkSourceClockHz SAI master clock source frequency in Hz. + * param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is the master + * clock, this value should equal to masterClockHz in format. + * retval kStatus_Success Audio format set successfully. + * retval kStatus_InvalidArgument The input argument is invalid. + */ +void SAI_TransferRxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz) +{ + assert(handle && format); + + /* Configure the audio format to SAI registers */ + SAI_RxSetFormat(base, format, mclkSourceClockHz, bclkSourceClockHz); + + /* Get the transfer size from format, this should be used in EDMA configuration */ + if (format->bitWidth == 24U) + { + handle->bytesPerFrame = 4U; + } + else + { + handle->bytesPerFrame = format->bitWidth / 8U; + } + + /* Update the data channel SAI used */ + handle->channel = format->channel; + + /* Clear the channel enable bits until do a send/receive */ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->count = format->watermark; +#else + handle->count = 1U; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +/*! + * @brief Configures the SAI Rx. + * + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param saiConfig sai configurations. + */ +void SAI_TransferRxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig) +{ + assert(handle && saiConfig); + + /* Configure the audio format to SAI registers */ + SAI_RxSetConfig(base, saiConfig); + + /* Get the transfer size from format, this should be used in EDMA configuration */ + if (saiConfig->serialData.dataWordLength == 24U) + { + handle->bytesPerFrame = 4U; + } + else + { + handle->bytesPerFrame = saiConfig->serialData.dataWordLength / 8U; + } + + /* Update the data channel SAI used */ + handle->channel = saiConfig->startChannel; + + /* Clear the channel enable bits until do a send/receive */ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; +#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1) + handle->count = saiConfig->fifo.fifoWatermark; +#else + handle->count = 1U; +#endif /* FSL_FEATURE_SAI_FIFO_COUNT */ +} + +/*! + * brief Performs a non-blocking SAI transfer using DMA. + * + * note This interface returns immediately after the transfer initiates. Call + * SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param xfer Pointer to the DMA transfer structure. + * retval kStatus_Success Start a SAI eDMA send successfully. + * retval kStatus_InvalidArgument The input argument is invalid. + * retval kStatus_TxBusy SAI is busy sending data. + */ +status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle && xfer); + + edma_transfer_config_t config = {0}; + uint32_t destAddr = SAI_TxGetDataRegisterAddress(base, handle->channel); + + /* Check if input parameter invalid */ + if ((xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Change the state of handle */ + handle->state = kSAI_Busy; + + /* Update the queue state */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, xfer->data, handle->bytesPerFrame, (void *)destAddr, handle->bytesPerFrame, + handle->count * handle->bytesPerFrame, xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Store the initially configured eDMA minor byte transfer count into the SAI handle */ + handle->nbytes = handle->count * handle->bytesPerFrame; + + EDMA_SubmitTransfer(handle->dmaHandle, &config); + + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, true); + + /* Enable SAI Tx clock */ + SAI_TxEnable(base, true); + + /* Enable the channel FIFO */ + base->TCR3 |= I2S_TCR3_TCE(1U << handle->channel); + + return kStatus_Success; +} + +/*! + * brief Performs a non-blocking SAI receive using eDMA. + * + * note This interface returns immediately after the transfer initiates. Call + * the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished. + * + * param base SAI base pointer + * param handle SAI eDMA handle pointer. + * param xfer Pointer to DMA transfer structure. + * retval kStatus_Success Start a SAI eDMA receive successfully. + * retval kStatus_InvalidArgument The input argument is invalid. + * retval kStatus_RxBusy SAI is busy receiving data. + */ +status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer) +{ + assert(handle && xfer); + + edma_transfer_config_t config = {0}; + uint32_t srcAddr = SAI_RxGetDataRegisterAddress(base, handle->channel); + + /* Check if input parameter invalid */ + if ((xfer->data == NULL) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + if (handle->saiQueue[handle->queueUser].data) + { + return kStatus_SAI_QueueFull; + } + + /* Change the state of handle */ + handle->state = kSAI_Busy; + + /* Update queue state */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->saiQueue[handle->queueUser].data = xfer->data; + handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame, + handle->count * handle->bytesPerFrame, xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Store the initially configured eDMA minor byte transfer count into the SAI handle */ + handle->nbytes = handle->count * handle->bytesPerFrame; + + EDMA_SubmitTransfer(handle->dmaHandle, &config); + + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaHandle); + + /* Enable DMA enable bit */ + SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, true); + + /* Enable the channel FIFO */ + base->RCR3 |= I2S_RCR3_RCE(1U << handle->channel); + + /* Enable SAI Rx clock */ + SAI_RxEnable(base, true); + + return kStatus_Success; +} + +/*! + * brief Aborts a SAI transfer using eDMA. + * + * This function only aborts the current transfer slots, the other transfer slots' information still kept + * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateSendEDMA. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ +void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable the channel FIFO */ + base->TCR3 &= ~I2S_TCR3_TCE_MASK; + + /* Disable DMA enable bit */ + SAI_TxEnableDMA(base, kSAI_FIFORequestDMAEnable, false); + + /* Disable Tx */ + SAI_TxEnable(base, false); + + /* Reset the FIFO pointer, at the same time clear all error flags if set */ + base->TCSR |= (I2S_TCSR_FR_MASK | I2S_TCSR_SR_MASK); + base->TCSR &= ~I2S_TCSR_SR_MASK; + + /* Handle the queue index */ + memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + + /* Set the handle state */ + handle->state = kSAI_Idle; +} + +/*! + * brief Aborts a SAI receive using eDMA. + * + * This function only aborts the current transfer slots, the other transfer slots' information still kept + * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateReceiveEDMA. + * + * param base SAI base pointer + * param handle SAI eDMA handle pointer. + */ +void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaHandle); + + /* Disable the channel FIFO */ + base->RCR3 &= ~I2S_RCR3_RCE_MASK; + + /* Disable DMA enable bit */ + SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, false); + + /* Disable Rx */ + SAI_RxEnable(base, false); + + /* Reset the FIFO pointer, at the same time clear all error flags if set */ + base->RCSR |= (I2S_RCSR_FR_MASK | I2S_RCSR_SR_MASK); + base->RCSR &= ~I2S_RCSR_SR_MASK; + + /* Handle the queue index */ + memset(&handle->saiQueue[handle->queueDriver], 0, sizeof(sai_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % SAI_XFER_QUEUE_SIZE; + + /* Set the handle state */ + handle->state = kSAI_Idle; +} + +/*! + * brief Terminate all SAI send. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortSendEDMA. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle) +{ + assert(handle); + + /* Abort the current transfer */ + SAI_TransferAbortSendEDMA(base, handle); + + /* Clear all the internal information */ + memset(handle->tcd, 0U, sizeof(handle->tcd)); + memset(handle->saiQueue, 0U, sizeof(handle->saiQueue)); + memset(handle->transferSize, 0U, sizeof(handle->transferSize)); + handle->queueUser = 0U; + handle->queueDriver = 0U; +} + +/*! + * brief Terminate all SAI receive. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortReceiveEDMA. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle) +{ + assert(handle); + + /* Abort the current transfer */ + SAI_TransferAbortReceiveEDMA(base, handle); + + /* Clear all the internal information */ + memset(handle->tcd, 0U, sizeof(handle->tcd)); + memset(handle->saiQueue, 0U, sizeof(handle->saiQueue)); + memset(handle->transferSize, 0U, sizeof(handle->transferSize)); + handle->queueUser = 0U; + handle->queueDriver = 0U; +} + +/*! + * brief Gets byte count sent by SAI. + * + * param base SAI base pointer. + * param handle SAI eDMA handle pointer. + * param count Bytes count sent by SAI. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel)); + } + + return status; +} + +/*! + * brief Gets byte count received by SAI. + * + * param base SAI base pointer + * param handle SAI eDMA handle pointer. + * param count Bytes count received by SAI. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSAI_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->dmaHandle->base, handle->dmaHandle->channel)); + } + + return status; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_sai_edma.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_sai_edma.h new file mode 100644 index 0000000000..71305fd448 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_sai_edma.h @@ -0,0 +1,262 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SAI_EDMA_H_ +#define _FSL_SAI_EDMA_H_ + +#include "fsl_edma.h" +#include "fsl_sai.h" + +/*! + * @addtogroup sai_edma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SAI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) /*!< Version 2.2.0 */ +/*@}*/ + +typedef struct _sai_edma_handle sai_edma_handle_t; + +/*! @brief SAI eDMA transfer callback function for finish and error */ +typedef void (*sai_edma_callback_t)(I2S_Type *base, sai_edma_handle_t *handle, status_t status, void *userData); + +/*! @brief SAI DMA transfer handle, users should not touch the content of the handle.*/ +struct _sai_edma_handle +{ + edma_handle_t *dmaHandle; /*!< DMA handler for SAI send */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + uint8_t bytesPerFrame; /*!< Bytes in a frame */ + uint8_t channel; /*!< Which data channel */ + uint8_t count; /*!< The transfer data count in a DMA request */ + uint32_t state; /*!< Internal state for SAI eDMA transfer */ + sai_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurs */ + void *userData; /*!< User callback parameter */ + uint8_t tcd[(SAI_XFER_QUEUE_SIZE + 1U) * sizeof(edma_tcd_t)]; /*!< TCD pool for eDMA transfer. */ + sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ + size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA Transactional + * @{ + */ + +/*! + * @brief Initializes the SAI eDMA handle. + * + * This function initializes the SAI master DMA handle, which can be used for other SAI master transactional APIs. + * Usually, for a specified SAI instance, call this API once to get the initialized handle. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param base SAI peripheral base address. + * @param callback Pointer to user callback function. + * @param userData User parameter passed to the callback function. + * @param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ +void SAI_TransferTxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle); + +/*! + * @brief Initializes the SAI Rx eDMA handle. + * + * This function initializes the SAI slave DMA handle, which can be used for other SAI master transactional APIs. + * Usually, for a specified SAI instance, call this API once to get the initialized handle. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param base SAI peripheral base address. + * @param callback Pointer to user callback function. + * @param userData User parameter passed to the callback function. + * @param dmaHandle eDMA handle pointer, this handle shall be static allocated by users. + */ +void SAI_TransferRxCreateHandleEDMA( + I2S_Type *base, sai_edma_handle_t *handle, sai_edma_callback_t callback, void *userData, edma_handle_t *dmaHandle); + +/*! + * @brief Configures the SAI Tx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param format Pointer to SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If bit clock source is master + * clock, this value should equals to masterClockHz in format. + * @retval kStatus_Success Audio format set successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + */ +void SAI_TransferTxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Configures the SAI Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. This function also sets the eDMA parameter according to formatting requirements. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param format Pointer to SAI audio data format structure. + * @param mclkSourceClockHz SAI master clock source frequency in Hz. + * @param bclkSourceClockHz SAI bit clock source frequency in Hz. If a bit clock source is the master + * clock, this value should equal to masterClockHz in format. + * @retval kStatus_Success Audio format set successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + */ +void SAI_TransferRxSetFormatEDMA(I2S_Type *base, + sai_edma_handle_t *handle, + sai_transfer_format_t *format, + uint32_t mclkSourceClockHz, + uint32_t bclkSourceClockHz); + +/*! + * @brief Configures the SAI Tx. + * + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param saiConfig sai configurations. + */ +void SAI_TransferTxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig); + +/*! + * @brief Configures the SAI Rx. + * + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param saiConfig sai configurations. + */ +void SAI_TransferRxSetConfigEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transceiver_t *saiConfig); + +/*! + * @brief Performs a non-blocking SAI transfer using DMA. + * + * @note This interface returns immediately after the transfer initiates. Call + * SAI_GetTransferStatus to poll the transfer status and check whether the SAI transfer is finished. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param xfer Pointer to the DMA transfer structure. + * @retval kStatus_Success Start a SAI eDMA send successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + * @retval kStatus_TxBusy SAI is busy sending data. + */ +status_t SAI_TransferSendEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SAI receive using eDMA. + * + * @note This interface returns immediately after the transfer initiates. Call + * the SAI_GetReceiveRemainingBytes to poll the transfer status and check whether the SAI transfer is finished. + * + * @param base SAI base pointer + * @param handle SAI eDMA handle pointer. + * @param xfer Pointer to DMA transfer structure. + * @retval kStatus_Success Start a SAI eDMA receive successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + * @retval kStatus_RxBusy SAI is busy receiving data. + */ +status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer); + +/*! + * @brief Terminate all SAI send. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortSendEDMA. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateSendEDMA(I2S_Type *base, sai_edma_handle_t *handle); + +/*! + * @brief Terminate all SAI receive. + * + * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the + * current transfer slot, please call SAI_TransferAbortReceiveEDMA. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferTerminateReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle); + +/*! + * @brief Aborts a SAI transfer using eDMA. + * + * This function only aborts the current transfer slots, the other transfer slots' information still kept + * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateSendEDMA. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferAbortSendEDMA(I2S_Type *base, sai_edma_handle_t *handle); + +/*! + * @brief Aborts a SAI receive using eDMA. + * + * This function only aborts the current transfer slots, the other transfer slots' information still kept + * in the handler. If users want to terminate all transfer slots, just call SAI_TransferTerminateReceiveEDMA. + * + * @param base SAI base pointer + * @param handle SAI eDMA handle pointer. + */ +void SAI_TransferAbortReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle); + +/*! + * @brief Gets byte count sent by SAI. + * + * @param base SAI base pointer. + * @param handle SAI eDMA handle pointer. + * @param count Bytes count sent by SAI. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SAI_TransferGetSendCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count); + +/*! + * @brief Gets byte count received by SAI. + * + * @param base SAI base pointer + * @param handle SAI eDMA handle pointer. + * @param count Bytes count received by SAI. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SAI_TransferGetReceiveCountEDMA(I2S_Type *base, sai_edma_handle_t *handle, size_t *count); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_semc.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_semc.c new file mode 100644 index 0000000000..68a517c3eb --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_semc.c @@ -0,0 +1,1066 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_semc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.semc" +#endif + +/*! @brief Define macros for SEMC driver. */ +#define SEMC_IPCOMMANDDATASIZEBYTEMAX (4U) +#define SEMC_IPCOMMANDMAGICKEY (0xA55A) +#define SEMC_IOCR_PINMUXBITWIDTH (0x3U) +#define SEMC_IOCR_NAND_CE (4U) +#define SEMC_IOCR_NOR_CE (5U) +#define SEMC_IOCR_NOR_CE_A8 (2U) +#define SEMC_IOCR_PSRAM_CE (6U) +#define SEMC_IOCR_PSRAM_CE_A8 (3U) +#define SEMC_IOCR_DBI_CSX (7U) +#define SEMC_IOCR_DBI_CSX_A8 (4U) +#define SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE (24U) +#define SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHMAX (28U) +#define SEMC_BMCR0_TYPICAL_WQOS (5U) +#define SEMC_BMCR0_TYPICAL_WAGE (8U) +#define SEMC_BMCR0_TYPICAL_WSH (0x40U) +#define SEMC_BMCR0_TYPICAL_WRWS (0x10U) +#define SEMC_BMCR1_TYPICAL_WQOS (5U) +#define SEMC_BMCR1_TYPICAL_WAGE (8U) +#define SEMC_BMCR1_TYPICAL_WPH (0x60U) +#define SEMC_BMCR1_TYPICAL_WBR (0x40U) +#define SEMC_BMCR1_TYPICAL_WRWS (0x24U) +#define SEMC_STARTADDRESS (0x80000000U) +#define SEMC_ENDADDRESS (0xDFFFFFFFU) +#define SEMC_BR_MEMSIZE_MIN (4) +#define SEMC_BR_MEMSIZE_OFFSET (2) +#define SEMC_BR_MEMSIZE_MAX (4 * 1024 * 1024) +#define SEMC_SDRAM_MODESETCAL_OFFSET (4) +#define SEMC_BR_REG_NUM (9) +#define SEMC_BYTE_NUMBIT (8) +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for SEMC module. + * + * @param base SEMC peripheral base address + */ +static uint32_t SEMC_GetInstance(SEMC_Type *base); + +/*! + * @brief Covert the input memory size to internal register set value. + * + * @param base SEMC peripheral base address + * @param size_kbytes SEMC memory size in unit of kbytes. + * @param sizeConverted SEMC converted memory size to 0 ~ 0x1F. + * @return Execution status. + */ +static status_t SEMC_CovertMemorySize(SEMC_Type *base, uint32_t size_kbytes, uint8_t *sizeConverted); + +/*! + * @brief Covert the external timing nanosecond to internal clock cycle. + * + * @param time_ns SEMC external time interval in unit of nanosecond. + * @param clkSrc_Hz SEMC clock source frequency. + * @return The changed internal clock cycle. + */ +static uint8_t SEMC_ConvertTiming(uint32_t time_ns, uint32_t clkSrc_Hz); + +/*! + * @brief Configure IP command. + * + * @param base SEMC peripheral base address. + * @param size_bytes SEMC IP command data size. + * @return Execution status. + */ +static status_t SEMC_ConfigureIPCommand(SEMC_Type *base, uint8_t size_bytes); + +/*! + * @brief Check if the IP command has finished. + * + * @param base SEMC peripheral base address. + * @return Execution status. + */ +static status_t SEMC_IsIPCommandDone(SEMC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to SEMC clocks for each instance. */ +static const clock_ip_name_t s_semcClock[FSL_FEATURE_SOC_SEMC_COUNT] = SEMC_CLOCKS; +static const clock_ip_name_t s_semcExtClock[FSL_FEATURE_SOC_SEMC_COUNT] = SEMC_EXSC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointers to SEMC bases for each instance. */ +static SEMC_Type *const s_semcBases[] = SEMC_BASE_PTRS; +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t SEMC_GetInstance(SEMC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_semcBases); instance++) + { + if (s_semcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_semcBases)); + + return instance; +} + +static status_t SEMC_CovertMemorySize(SEMC_Type *base, uint32_t size_kbytes, uint8_t *sizeConverted) +{ + assert(sizeConverted); + uint32_t memsize; + + if ((size_kbytes < SEMC_BR_MEMSIZE_MIN) || (size_kbytes > SEMC_BR_MEMSIZE_MAX)) + { + return kStatus_SEMC_InvalidMemorySize; + } + + *sizeConverted = 0; + memsize = size_kbytes / 8; + while (memsize) + { + memsize >>= 1; + (*sizeConverted)++; + } + return kStatus_Success; +} + +static uint8_t SEMC_ConvertTiming(uint32_t time_ns, uint32_t clkSrc_Hz) +{ + assert(clkSrc_Hz); + + uint8_t clockCycles = 0; + uint32_t tClk_us; + + clkSrc_Hz /= 1000000; + tClk_us = 1000000 / clkSrc_Hz; + + while (tClk_us * clockCycles < (time_ns * 1000)) + { + clockCycles++; + } + + return clockCycles; +} + +static status_t SEMC_ConfigureIPCommand(SEMC_Type *base, uint8_t size_bytes) +{ + if ((size_bytes > SEMC_IPCOMMANDDATASIZEBYTEMAX) || (!size_bytes)) + { + return kStatus_SEMC_InvalidIpcmdDataSize; + } + + /* Set data size. */ + /* Note: It is better to set data size as the device data port width when transfering + * device command data. but for device memory data transfer, it can be set freely. + * Note: If the data size is greater than data port width, for example, datsz = 4, data port = 16bit, + * then the 4-byte data transfer will be split into two 2-byte transfer, the slave address + * will be switched automatically according to connected device type*/ + base->IPCR1 = SEMC_IPCR1_DATSZ(size_bytes); + /* Clear data size. */ + base->IPCR2 = 0; + /* Set data size. */ + if (size_bytes < 4) + { + base->IPCR2 |= SEMC_IPCR2_BM3_MASK; + } + if (size_bytes < 3) + { + base->IPCR2 |= SEMC_IPCR2_BM2_MASK; + } + if (size_bytes < 2) + { + base->IPCR2 |= SEMC_IPCR2_BM1_MASK; + } + return kStatus_Success; +} + +static status_t SEMC_IsIPCommandDone(SEMC_Type *base) +{ + /* Poll status bit till command is done*/ + while (!(base->INTR & SEMC_INTR_IPCMDDONE_MASK)) + { + }; + + /* Clear status bit */ + base->INTR |= SEMC_INTR_IPCMDDONE_MASK; + + /* Check error status */ + if (base->INTR & SEMC_INTR_IPCMDERR_MASK) + { + base->INTR |= SEMC_INTR_IPCMDERR_MASK; + return kStatus_SEMC_IpCommandExecutionError; + } + + return kStatus_Success; +} + +/*! + * brief Gets the SEMC default basic configuration structure. + * + * The purpose of this API is to get the default SEMC + * configure structure for SEMC_Init(). User may use the initialized + * structure unchanged in SEMC_Init(), or modify some fields of the + * structure before calling SEMC_Init(). + * Example: + code + semc_config_t config; + SEMC_GetDefaultConfig(&config); + endcode + * param config The SEMC configuration structure pointer. + */ +void SEMC_GetDefaultConfig(semc_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + semc_queuea_weight_struct_t *queueaWeight = &(config->queueWeight.queueaWeight.queueaConfig); + semc_queueb_weight_struct_t *queuebWeight = &(config->queueWeight.queuebWeight.queuebConfig); + + /* Get default settings. */ + config->dqsMode = kSEMC_Loopbackinternal; + config->cmdTimeoutCycles = 0; + config->busTimeoutCycles = 0x1F; + + queueaWeight->qos = SEMC_BMCR0_TYPICAL_WQOS; + queueaWeight->aging = SEMC_BMCR0_TYPICAL_WAGE; + queueaWeight->slaveHitSwith = SEMC_BMCR0_TYPICAL_WSH; + queueaWeight->slaveHitNoswitch = SEMC_BMCR0_TYPICAL_WRWS; + queuebWeight->qos = SEMC_BMCR1_TYPICAL_WQOS; + queuebWeight->aging = SEMC_BMCR1_TYPICAL_WAGE; + queuebWeight->slaveHitSwith = SEMC_BMCR1_TYPICAL_WRWS; + queuebWeight->weightPagehit = SEMC_BMCR1_TYPICAL_WPH; + queuebWeight->bankRotation = SEMC_BMCR1_TYPICAL_WBR; +} + +/*! + * brief Initializes SEMC. + * This function ungates the SEMC clock and initializes SEMC. + * This function must be called before calling any other SEMC driver functions. + * + * param base SEMC peripheral base address. + * param configure The SEMC configuration structure pointer. + */ +void SEMC_Init(SEMC_Type *base, semc_config_t *configure) +{ + assert(configure); + + uint8_t index = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Un-gate sdram controller clock. */ + CLOCK_EnableClock(s_semcClock[SEMC_GetInstance(base)]); + CLOCK_EnableClock(s_semcExtClock[SEMC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Initialize all BR to zero due to the default base address set. */ + for (index = 0; index < SEMC_BR_REG_NUM; index++) + { + base->BR[index] = 0; + } + + /* Software reset for SEMC internal logical . */ + base->MCR = SEMC_MCR_SWRST_MASK; + while (base->MCR & SEMC_MCR_SWRST_MASK) + { + } + + /* Configure, disable module first. */ + base->MCR |= SEMC_MCR_MDIS_MASK | SEMC_MCR_BTO(configure->busTimeoutCycles) | + SEMC_MCR_CTO(configure->cmdTimeoutCycles) | SEMC_MCR_DQSMD(configure->dqsMode); + + /* Configure Queue 0/1 for AXI bus. */ + base->BMCR0 = (uint32_t)(configure->queueWeight.queueaWeight.queueaValue); + base->BMCR1 = (uint32_t)(configure->queueWeight.queuebWeight.queuebValue); + + /* Enable SEMC. */ + base->MCR &= ~SEMC_MCR_MDIS_MASK; +} + +/*! + * brief Deinitializes the SEMC module and gates the clock. + * This function gates the SEMC clock. As a result, the SEMC + * module doesn't work after calling this function. + * + * param base SEMC peripheral base address. + */ +void SEMC_Deinit(SEMC_Type *base) +{ + /* Disable module. Check there is no pending command before disable module. */ + while (!(base->STS0 & SEMC_STS0_IDLE_MASK)) + { + ; + } + + base->MCR |= SEMC_MCR_MDIS_MASK | SEMC_MCR_SWRST_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable SDRAM clock. */ + CLOCK_DisableClock(s_semcClock[SEMC_GetInstance(base)]); + CLOCK_DisableClock(s_semcExtClock[SEMC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Configures SDRAM controller in SEMC. + * + * param base SEMC peripheral base address. + * param cs The chip selection. + * param config The sdram configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + assert(clkSrc_Hz); + assert(config->refreshBurstLen); + + uint8_t memsize; + status_t result = kStatus_Success; + uint16_t prescale = config->tPrescalePeriod_Ns / 16 / (1000000000 / clkSrc_Hz); + uint16_t refresh; + uint16_t urgentRef; + uint16_t idle; + uint16_t mode; + + if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + if (config->csxPinMux == kSEMC_MUXA8) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + + if (prescale > 256) + { + return kStatus_SEMC_InvalidTimerSetting; + } + + refresh = config->refreshPeriod_nsPerRow / config->tPrescalePeriod_Ns; + urgentRef = config->refreshUrgThreshold / config->tPrescalePeriod_Ns; + idle = config->tIdleTimeout_Ns / config->tPrescalePeriod_Ns; + + uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->csxPinMux); + + /* Base control. */ + result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + + base->BR[cs] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + base->SDRAMCR0 = SEMC_SDRAMCR0_PS(config->portSize) | SEMC_SDRAMCR0_BL(config->burstLen) | + SEMC_SDRAMCR0_COL(config->columnAddrBitNum) | SEMC_SDRAMCR0_CL(config->casLatency); + /* IOMUX setting. */ + if (cs) + { + base->IOCR = iocReg | (cs << config->csxPinMux); + } + + base->IOCR &= ~SEMC_IOCR_MUX_A8_MASK; + + /* Timing setting. */ + base->SDRAMCR1 = SEMC_SDRAMCR1_PRE2ACT(SEMC_ConvertTiming(config->tPrecharge2Act_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_ACT2RW(SEMC_ConvertTiming(config->tAct2ReadWrite_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_RFRC(SEMC_ConvertTiming(config->tRefreshRecovery_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_WRC(SEMC_ConvertTiming(config->tWriteRecovery_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_CKEOFF(SEMC_ConvertTiming(config->tCkeOff_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR1_ACT2PRE(SEMC_ConvertTiming(config->tAct2Prechage_Ns, clkSrc_Hz) - 1); + base->SDRAMCR2 = + SEMC_SDRAMCR2_SRRC(SEMC_ConvertTiming(config->tSelfRefRecovery_Ns, clkSrc_Hz) - 1) | + SEMC_SDRAMCR2_REF2REF( + SEMC_ConvertTiming(config->tRefresh2Refresh_Ns, clkSrc_Hz)) | /* No Minus one to keep with RM */ + SEMC_SDRAMCR2_ACT2ACT(SEMC_ConvertTiming(config->tAct2Act_Ns, clkSrc_Hz)) | /* No Minus one to keep with RM */ + SEMC_SDRAMCR2_ITO(idle); + base->SDRAMCR3 = SEMC_SDRAMCR3_REBL(config->refreshBurstLen - 1) | + /* N * 16 * 1s / clkSrc_Hz = config->tPrescalePeriod_Ns */ + SEMC_SDRAMCR3_PRESCALE(prescale) | SEMC_SDRAMCR3_RT(refresh) | SEMC_SDRAMCR3_UT(urgentRef); + + SEMC->IPCR1 = 0x2; + SEMC->IPCR2 = 0; + + result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_Prechargeall, 0, NULL); + if (result != kStatus_Success) + { + return result; + } + result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_AutoRefresh, 0, NULL); + if (result != kStatus_Success) + { + return result; + } + result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_AutoRefresh, 0, NULL); + if (result != kStatus_Success) + { + return result; + } + /* Mode setting value. */ + mode = (uint16_t)config->burstLen | (uint16_t)(config->casLatency << SEMC_SDRAM_MODESETCAL_OFFSET); + result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_Modeset, mode, NULL); + if (result != kStatus_Success) + { + return result; + } + /* Enables refresh */ + base->SDRAMCR3 |= SEMC_SDRAMCR3_REN_MASK; + + return kStatus_Success; +} + +/*! + * brief Configures NAND controller in SEMC. + * + * param base SEMC peripheral base address. + * param config The nand configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + assert(config->timingConfig); + + uint8_t memsize; + status_t result; + + if ((config->axiAddress < SEMC_STARTADDRESS) || (config->axiAddress > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + if (config->cePinMux == kSEMC_MUXRDY) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + + uint32_t iocReg = base->IOCR & ~((SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux) | SEMC_IOCR_MUX_RDY_MASK); + + /* Base control. */ + if (config->rdyactivePolarity == kSEMC_RdyActivehigh) + { + base->MCR |= SEMC_MCR_WPOL1_MASK; + } + else + { + base->MCR &= ~SEMC_MCR_WPOL1_MASK; + } + result = SEMC_CovertMemorySize(base, config->axiMemsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[4] = (config->axiAddress & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + + result = SEMC_CovertMemorySize(base, config->ipgMemsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[8] = (config->ipgAddress & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + + /* IOMUX setting. */ + if (config->cePinMux) + { + base->IOCR = iocReg | (SEMC_IOCR_NAND_CE << config->cePinMux); + } + else + { + base->IOCR = iocReg | (1U << config->cePinMux); + } + + base->NANDCR0 = SEMC_NANDCR0_PS(config->portSize) | SEMC_NANDCR0_BL(config->burstLen) | + SEMC_NANDCR0_EDO(config->edoModeEnabled) | SEMC_NANDCR0_COL(config->columnAddrBitNum); + + /* Timing setting. */ + base->NANDCR1 = SEMC_NANDCR1_CES(SEMC_ConvertTiming(config->timingConfig->tCeSetup_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_CEH(SEMC_ConvertTiming(config->timingConfig->tCeHold_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_WEL(SEMC_ConvertTiming(config->timingConfig->tWeLow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_WEH(SEMC_ConvertTiming(config->timingConfig->tWeHigh_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_REL(SEMC_ConvertTiming(config->timingConfig->tReLow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_REH(SEMC_ConvertTiming(config->timingConfig->tReHigh_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_TA(SEMC_ConvertTiming(config->timingConfig->tTurnAround_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR1_CEITV(SEMC_ConvertTiming(config->timingConfig->tCeInterval_Ns, clkSrc_Hz) - 1); + base->NANDCR2 = SEMC_NANDCR2_TWHR(SEMC_ConvertTiming(config->timingConfig->tWehigh2Relow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TRHW(SEMC_ConvertTiming(config->timingConfig->tRehigh2Welow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TADL(SEMC_ConvertTiming(config->timingConfig->tAle2WriteStart_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TRR(SEMC_ConvertTiming(config->timingConfig->tReady2Relow_Ns, clkSrc_Hz) - 1) | + SEMC_NANDCR2_TWB(SEMC_ConvertTiming(config->timingConfig->tWehigh2Busy_Ns, clkSrc_Hz) - 1); + base->NANDCR3 = config->arrayAddrOption; + return kStatus_Success; +} + +/*! + * brief Configures NOR controller in SEMC. + * + * param base SEMC peripheral base address. + * param config The nor configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + + uint8_t memsize; + status_t result; + + if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux); + uint32_t muxCe = (config->cePinMux == kSEMC_MUXRDY) ? + SEMC_IOCR_NOR_CE - 1 : + ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_NOR_CE_A8 : SEMC_IOCR_NOR_CE); + + /* IOMUX setting. */ + base->IOCR = iocReg | (muxCe << config->cePinMux); + /* Address bit setting. */ + if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE) + { + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 1) + { + /* Address bit 24 (A24) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX0_MASK; + if (config->cePinMux == kSEMC_MUXCSX0) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 2) + { + /* Address bit 25 (A25) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX1_MASK; + if (config->cePinMux == kSEMC_MUXCSX1) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 3) + { + /* Address bit 26 (A26) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX2_MASK; + if (config->cePinMux == kSEMC_MUXCSX2) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 4) + { + if (config->addr27 == kSEMC_NORA27_MUXCSX3) + { + /* Address bit 27 (A27) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX3_MASK; + } + else if (config->addr27 == kSEMC_NORA27_MUXRDY) + { + base->IOCR |= SEMC_IOCR_MUX_RDY_MASK; + } + else + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + if (config->cePinMux == kSEMC_MUXCSX3) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHMAX) + { + return kStatus_SEMC_InvalidAddressPortWidth; + } + } + + /* Base control. */ + if (config->rdyactivePolarity == kSEMC_RdyActivehigh) + { + base->MCR |= SEMC_MCR_WPOL0_MASK; + } + else + { + base->MCR &= ~SEMC_MCR_WPOL0_MASK; + } + result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[5] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + base->NORCR0 = SEMC_NORCR0_PS(config->portSize) | SEMC_NORCR0_BL(config->burstLen) | + SEMC_NORCR0_AM(config->addrMode) | SEMC_NORCR0_ADVP(config->advActivePolarity) | + SEMC_NORCR0_COL(config->columnAddrBitNum); + + /* Timing setting. */ + base->NORCR1 = SEMC_NORCR1_CES(SEMC_ConvertTiming(config->tCeSetup_Ns, clkSrc_Hz)) | + SEMC_NORCR1_CEH(SEMC_ConvertTiming(config->tCeHold_Ns, clkSrc_Hz)) | + SEMC_NORCR1_AS(SEMC_ConvertTiming(config->tAddrSetup_Ns, clkSrc_Hz)) | + SEMC_NORCR1_AH(SEMC_ConvertTiming(config->tAddrHold_Ns, clkSrc_Hz)) | + SEMC_NORCR1_WEL(SEMC_ConvertTiming(config->tWeLow_Ns, clkSrc_Hz)) | + SEMC_NORCR1_WEH(SEMC_ConvertTiming(config->tWeHigh_Ns, clkSrc_Hz)) | + SEMC_NORCR1_REL(SEMC_ConvertTiming(config->tReLow_Ns, clkSrc_Hz)) | + SEMC_NORCR1_REH(SEMC_ConvertTiming(config->tReHigh_Ns, clkSrc_Hz)); + base->NORCR2 = +#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) + SEMC_NORCR2_WDS(SEMC_ConvertTiming(config->tWriteSetup_Ns, clkSrc_Hz)) | +#endif /* FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME */ +#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) + SEMC_NORCR2_WDH(SEMC_ConvertTiming(config->tWriteHold_Ns, clkSrc_Hz)) | +#endif /* FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME */ + SEMC_NORCR2_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz)) | + SEMC_NORCR2_AWDH(SEMC_ConvertTiming(config->tAddr2WriteHold_Ns, clkSrc_Hz) + 1) | + SEMC_NORCR2_LC(config->latencyCount) | SEMC_NORCR2_RD(config->readCycle) | + SEMC_NORCR2_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz)); + + return SEMC_ConfigureIPCommand(base, (config->portSize + 1)); +} + +/*! + * brief Configures SRAM controller in SEMC. + * + * param base SEMC peripheral base address. + * param config The sram configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + + uint8_t memsize; + status_t result = kStatus_Success; + + if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux); + uint32_t muxCe = (config->cePinMux == kSEMC_MUXRDY) ? + SEMC_IOCR_PSRAM_CE - 1 : + ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_PSRAM_CE_A8 : SEMC_IOCR_PSRAM_CE); + + /* IOMUX setting. */ + base->IOCR = iocReg | (muxCe << config->cePinMux); + /* Address bit setting. */ + if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE) + { + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 1) + { + /* Address bit 24 (A24) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX0_MASK; + if (config->cePinMux == kSEMC_MUXCSX0) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 2) + { + /* Address bit 25 (A25) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX1_MASK; + if (config->cePinMux == kSEMC_MUXCSX1) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 3) + { + /* Address bit 26 (A26) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX2_MASK; + if (config->cePinMux == kSEMC_MUXCSX2) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth >= SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHBASE + 4) + { + if (config->addr27 == kSEMC_NORA27_MUXCSX3) + { + /* Address bit 27 (A27) */ + base->IOCR &= (uint32_t)~SEMC_IOCR_MUX_CSX3_MASK; + } + else if (config->addr27 == kSEMC_NORA27_MUXRDY) + { + base->IOCR |= SEMC_IOCR_MUX_RDY_MASK; + } + else + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + + if (config->cePinMux == kSEMC_MUXCSX3) + { + return kStatus_SEMC_InvalidSwPinmuxSelection; + } + } + if (config->addrPortWidth > SEMC_NORFLASH_SRAM_ADDR_PORTWIDTHMAX) + { + return kStatus_SEMC_InvalidAddressPortWidth; + } + } + /* Base control. */ + result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[6] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + base->SRAMCR0 = SEMC_SRAMCR0_PS(config->portSize) | SEMC_SRAMCR0_BL(config->burstLen) | + SEMC_SRAMCR0_AM(config->addrMode) | SEMC_SRAMCR0_ADVP(config->advActivePolarity) | + SEMC_SRAMCR0_COL_MASK; + + /* Timing setting. */ + base->SRAMCR1 = SEMC_SRAMCR1_CES(SEMC_ConvertTiming(config->tCeSetup_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_CEH(SEMC_ConvertTiming(config->tCeHold_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_AS(SEMC_ConvertTiming(config->tAddrSetup_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_AH(SEMC_ConvertTiming(config->tAddrHold_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_WEL(SEMC_ConvertTiming(config->tWeLow_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_WEH(SEMC_ConvertTiming(config->tWeHigh_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_REL(SEMC_ConvertTiming(config->tReLow_Ns, clkSrc_Hz)) | + SEMC_SRAMCR1_REH(SEMC_ConvertTiming(config->tReHigh_Ns, clkSrc_Hz)); + + base->SRAMCR2 = SEMC_SRAMCR2_WDS(SEMC_ConvertTiming(config->tWriteSetup_Ns, clkSrc_Hz)) | + SEMC_SRAMCR2_WDH(SEMC_ConvertTiming(config->tWriteHold_Ns, clkSrc_Hz)) | + SEMC_SRAMCR2_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz)) | + SEMC_SRAMCR2_AWDH(SEMC_ConvertTiming(config->tAddr2WriteHold_Ns, clkSrc_Hz) + 1) | + SEMC_SRAMCR2_LC(config->latencyCount) | SEMC_SRAMCR2_RD(config->readCycle) | + SEMC_SRAMCR2_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz)); + + return result; +} + +/*! + * brief Configures DBI controller in SEMC. + * + * param base SEMC peripheral base address. + * param config The dbi configuration. + * param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz) +{ + assert(config); + + uint8_t memsize; + status_t result; + + if ((config->address < SEMC_STARTADDRESS) || (config->address > SEMC_ENDADDRESS)) + { + return kStatus_SEMC_InvalidBaseAddress; + } + + uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->csxPinMux); + uint32_t muxCsx = (config->csxPinMux == kSEMC_MUXRDY) ? + SEMC_IOCR_DBI_CSX - 1 : + ((config->csxPinMux == kSEMC_MUXA8) ? SEMC_IOCR_DBI_CSX_A8 : SEMC_IOCR_DBI_CSX); + + /* IOMUX setting. */ + base->IOCR = iocReg | (muxCsx << config->csxPinMux); + /* Base control. */ + result = SEMC_CovertMemorySize(base, config->memsize_kbytes, &memsize); + if (result != kStatus_Success) + { + return result; + } + base->BR[7] = (config->address & SEMC_BR_BA_MASK) | SEMC_BR_MS(memsize) | SEMC_BR_VLD_MASK; + base->DBICR0 = + SEMC_DBICR0_PS(config->portSize) | SEMC_DBICR0_BL(config->burstLen) | SEMC_DBICR0_COL(config->columnAddrBitNum); + + /* Timing setting. */ + base->DBICR1 = SEMC_DBICR1_CES(SEMC_ConvertTiming(config->tCsxSetup_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_CEH(SEMC_ConvertTiming(config->tCsxHold_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_WEL(SEMC_ConvertTiming(config->tWexLow_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_WEH(SEMC_ConvertTiming(config->tWexHigh_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_REL(SEMC_ConvertTiming(config->tRdxLow_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_REH(SEMC_ConvertTiming(config->tRdxHigh_Ns, clkSrc_Hz) - 1) | + SEMC_DBICR1_CEITV(SEMC_ConvertTiming(config->tCsxInterval_Ns, clkSrc_Hz) - 1); + return SEMC_ConfigureIPCommand(base, (config->portSize + 1)); +} + +/*! + * brief SEMC IP command access. + * + * param base SEMC peripheral base address. + * param type SEMC memory type. refer to "semc_mem_type_t" + * param address SEMC device address. + * param command SEMC IP command. + * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. + * For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t". + * For SRAM device, take refer to "semc_ipcmd_sram_t". + * For SDRAM device, take refer to "semc_ipcmd_sdram_t". + * param write Data for write access. + * param read Data pointer for read data out. + */ +status_t SEMC_SendIPCommand( + SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read) +{ + uint32_t cmdMode; + bool readCmd = 0; + bool writeCmd = 0; + status_t result; + + /* Clear status bit */ + base->INTR |= SEMC_INTR_IPCMDDONE_MASK; + /* Set address. */ + base->IPCR0 = address; + + /* Check command mode. */ + cmdMode = command & 0xFU; + switch (type) + { + case kSEMC_MemType_NAND: + readCmd = (cmdMode == kSEMC_NANDCM_CommandAddressRead) || (cmdMode == kSEMC_NANDCM_CommandRead) || + (cmdMode == kSEMC_NANDCM_Read); + writeCmd = (cmdMode == kSEMC_NANDCM_CommandAddressWrite) || (cmdMode == kSEMC_NANDCM_CommandWrite) || + (cmdMode == kSEMC_NANDCM_Write); + break; + case kSEMC_MemType_NOR: + case kSEMC_MemType_8080: + readCmd = (cmdMode == kSEMC_NORDBICM_Read); + writeCmd = (cmdMode == kSEMC_NORDBICM_Write); + break; + case kSEMC_MemType_SRAM: + readCmd = (cmdMode == kSEMC_SRAMCM_ArrayRead) || (cmdMode == kSEMC_SRAMCM_RegRead); + writeCmd = (cmdMode == kSEMC_SRAMCM_ArrayWrite) || (cmdMode == kSEMC_SRAMCM_RegWrite); + break; + case kSEMC_MemType_SDRAM: + readCmd = (cmdMode == kSEMC_SDRAMCM_Read); + writeCmd = (cmdMode == kSEMC_SDRAMCM_Write) || (cmdMode == kSEMC_SDRAMCM_Modeset); + break; + default: + break; + } + + if (writeCmd) + { + /* Set data. */ + base->IPTXDAT = write; + } + + /* Set command code. */ + base->IPCMD = command | SEMC_IPCMD_KEY(SEMC_IPCOMMANDMAGICKEY); + /* Wait for command done. */ + result = SEMC_IsIPCommandDone(base); + if (result != kStatus_Success) + { + return result; + } + + if (readCmd) + { + /* Get the read data */ + *read = base->IPRXDAT; + } + + return kStatus_Success; +} + +/*! + * brief SEMC NAND device memory write through IP command. + * + * param base SEMC peripheral base address. + * param address SEMC NAND device address. + * param data Data for write access. + * param size_bytes Data length. + */ +status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) +{ + assert(data); + + status_t result = kStatus_Success; + uint16_t ipCmd; + uint32_t tempData = 0; + + /* Write command built */ + ipCmd = SEMC_BuildNandIPCommand(0, kSEMC_NANDAM_ColumnRow, kSEMC_NANDCM_Write); + while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) + { + /* Configure IP command data size. */ + SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); + result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, *(uint32_t *)data, NULL); + if (result != kStatus_Success) + { + break; + } + + data += SEMC_IPCOMMANDDATASIZEBYTEMAX; + size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; + } + + if ((result == kStatus_Success) && size_bytes) + { + SEMC_ConfigureIPCommand(base, size_bytes); + + while (size_bytes) + { + tempData |= ((uint32_t) * (data + size_bytes - 1) << ((size_bytes - 1) * SEMC_BYTE_NUMBIT)); + size_bytes--; + } + + result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, tempData, NULL); + } + + return result; +} + +/*! + * brief SEMC NAND device memory read through IP command. + * + * param base SEMC peripheral base address. + * param address SEMC NAND device address. + * param data Data pointer for data read out. + * param size_bytes Data length. + */ +status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) +{ + assert(data); + + status_t result = kStatus_Success; + uint16_t ipCmd; + uint32_t tempData = 0; + + /* Configure IP command data size. */ + SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); + /* Read command built */ + ipCmd = SEMC_BuildNandIPCommand(0, kSEMC_NANDAM_ColumnRow, kSEMC_NANDCM_Read); + + while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) + { + result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, 0, (uint32_t *)data); + if (result != kStatus_Success) + { + break; + } + + data += SEMC_IPCOMMANDDATASIZEBYTEMAX; + size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; + } + + if ((result == kStatus_Success) && size_bytes) + { + SEMC_ConfigureIPCommand(base, size_bytes); + result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, 0, &tempData); + + while (size_bytes) + { + size_bytes--; + *(data + size_bytes) = (tempData >> (SEMC_BYTE_NUMBIT * size_bytes)) & 0xFFU; + } + } + + return result; +} + +/*! + * brief SEMC NOR device memory read through IP command. + * + * param base SEMC peripheral base address. + * param address SEMC NOR device address. + * param data Data pointer for data read out. + * param size_bytes Data length. + */ +status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) +{ + assert(data); + + uint32_t tempData = 0; + status_t result = kStatus_Success; + uint8_t dataSize = base->NORCR0 & SEMC_NORCR0_PS_MASK; + + /* Configure IP command data size. */ + SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); + + while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) + { + result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Read, 0, (uint32_t *)data); + if (result != kStatus_Success) + { + break; + } + + data += SEMC_IPCOMMANDDATASIZEBYTEMAX; + size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; + } + + if ((result == kStatus_Success) && size_bytes) + { + SEMC_ConfigureIPCommand(base, size_bytes); + result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Read, 0, &tempData); + while (size_bytes) + { + size_bytes--; + *(data + size_bytes) = (tempData >> (SEMC_BYTE_NUMBIT * size_bytes)) & 0xFFU; + } + } + + SEMC_ConfigureIPCommand(base, dataSize); + return result; +} + +/*! + * brief SEMC NOR device memory write through IP command. + * + * param base SEMC peripheral base address. + * param address SEMC NOR device address. + * param data Data for write access. + * param size_bytes Data length. + */ +status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes) +{ + assert(data); + + uint32_t tempData = 0; + status_t result = kStatus_Success; + uint8_t dataSize = base->NORCR0 & SEMC_NORCR0_PS_MASK; + + /* Write command built */ + while (size_bytes >= SEMC_IPCOMMANDDATASIZEBYTEMAX) + { + /* Configure IP command data size. */ + SEMC_ConfigureIPCommand(base, SEMC_IPCOMMANDDATASIZEBYTEMAX); + result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Write, *(uint32_t *)data, NULL); + if (result != kStatus_Success) + { + break; + } + size_bytes -= SEMC_IPCOMMANDDATASIZEBYTEMAX; + data += SEMC_IPCOMMANDDATASIZEBYTEMAX; + } + + if ((result == kStatus_Success) && size_bytes) + { + SEMC_ConfigureIPCommand(base, size_bytes); + + while (size_bytes) + { + tempData |= ((uint32_t) * (data + size_bytes - 1) << ((size_bytes - 1) * SEMC_BYTE_NUMBIT)); + size_bytes--; + } + + result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Write, tempData, NULL); + } + SEMC_ConfigureIPCommand(base, dataSize); + + return result; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_semc.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_semc.h new file mode 100644 index 0000000000..41ad2b2362 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_semc.h @@ -0,0 +1,830 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SEMC_H_ +#define _FSL_SEMC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup semc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SEMC driver version 2.0.4. */ +#define FSL_SEMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*@}*/ + +/*! @brief SEMC status. */ +enum _semc_status +{ + kStatus_SEMC_InvalidDeviceType = MAKE_STATUS(kStatusGroup_SEMC, 0), + kStatus_SEMC_IpCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 1), + kStatus_SEMC_AxiCommandExecutionError = MAKE_STATUS(kStatusGroup_SEMC, 2), + kStatus_SEMC_InvalidMemorySize = MAKE_STATUS(kStatusGroup_SEMC, 3), + kStatus_SEMC_InvalidIpcmdDataSize = MAKE_STATUS(kStatusGroup_SEMC, 4), + kStatus_SEMC_InvalidAddressPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 5), + kStatus_SEMC_InvalidDataPortWidth = MAKE_STATUS(kStatusGroup_SEMC, 6), + kStatus_SEMC_InvalidSwPinmuxSelection = MAKE_STATUS(kStatusGroup_SEMC, 7), + kStatus_SEMC_InvalidBurstLength = MAKE_STATUS(kStatusGroup_SEMC, 8), + kStatus_SEMC_InvalidColumnAddressBitWidth = MAKE_STATUS(kStatusGroup_SEMC, 9), + kStatus_SEMC_InvalidBaseAddress = MAKE_STATUS(kStatusGroup_SEMC, 10), + kStatus_SEMC_InvalidTimerSetting = MAKE_STATUS(kStatusGroup_SEMC, 11), +}; + +/*! @brief SEMC memory device type. */ +typedef enum _semc_mem_type +{ + kSEMC_MemType_SDRAM = 0, /*!< SDRAM */ + kSEMC_MemType_SRAM, /*!< SRAM */ + kSEMC_MemType_NOR, /*!< NOR */ + kSEMC_MemType_NAND, /*!< NAND */ + kSEMC_MemType_8080 /*!< 8080. */ +} semc_mem_type_t; + +/*! @brief SEMC WAIT/RDY polarity. */ +typedef enum _semc_waitready_polarity +{ + kSEMC_LowActive = 0, /*!< Low active. */ + kSEMC_HighActive, /*!< High active. */ +} semc_waitready_polarity_t; + +/*! @brief SEMC SDRAM Chip selection . */ +typedef enum _semc_sdram_cs +{ + kSEMC_SDRAM_CS0 = 0, /*!< SEMC SDRAM CS0. */ + kSEMC_SDRAM_CS1, /*!< SEMC SDRAM CS1. */ + kSEMC_SDRAM_CS2, /*!< SEMC SDRAM CS2. */ + kSEMC_SDRAM_CS3 /*!< SEMC SDRAM CS3. */ +} semc_sdram_cs_t; + +/*! @brief SEMC NAND device type. */ +typedef enum _semc_nand_access_type +{ + kSEMC_NAND_ACCESS_BY_AXI = 0, + kSEMC_NAND_ACCESS_BY_IPCMD, +} semc_nand_access_type_t; + +/*! @brief SEMC interrupts . */ +typedef enum _semc_interrupt_enable +{ + kSEMC_IPCmdDoneInterrupt = SEMC_INTEN_IPCMDDONEEN_MASK, /*!< Ip command done interrupt. */ + kSEMC_IPCmdErrInterrupt = SEMC_INTEN_IPCMDERREN_MASK, /*!< Ip command error interrupt. */ + kSEMC_AXICmdErrInterrupt = SEMC_INTEN_AXICMDERREN_MASK, /*!< AXI command error interrupt. */ + kSEMC_AXIBusErrInterrupt = SEMC_INTEN_AXIBUSERREN_MASK /*!< AXI bus error interrupt. */ +} semc_interrupt_enable_t; + +/*! @brief SEMC IP command data size in bytes. */ +typedef enum _semc_ipcmd_datasize +{ + kSEMC_IPcmdDataSize_1bytes = 1, /*!< The IP command data size 1 byte. */ + kSEMC_IPcmdDataSize_2bytes, /*!< The IP command data size 2 byte. */ + kSEMC_IPcmdDataSize_3bytes, /*!< The IP command data size 3 byte. */ + kSEMC_IPcmdDataSize_4bytes /*!< The IP command data size 4 byte. */ +} semc_ipcmd_datasize_t; + +/*! @brief SEMC auto-refresh timing. */ +typedef enum _semc_refresh_time +{ + kSEMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */ + kSEMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */ + kSEMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */ +} semc_refresh_time_t; + +/*! @brief CAS latency */ +typedef enum _semc_caslatency +{ + kSEMC_LatencyOne = 1, /*!< Latency 1. */ + kSEMC_LatencyTwo, /*!< Latency 2. */ + kSEMC_LatencyThree, /*!< Latency 3. */ +} semc_caslatency_t; + +/*! @brief SEMC sdram column address bit number. */ +typedef enum _semc_sdram_column_bit_num +{ + kSEMC_SdramColunm_12bit = 0x0U, /*!< 12 bit. */ + kSEMC_SdramColunm_11bit, /*!< 11 bit. */ + kSEMC_SdramColunm_10bit, /*!< 10 bit. */ + kSEMC_SdramColunm_9bit, /*!< 9 bit. */ +} semc_sdram_column_bit_num_t; + +/*! @brief SEMC sdram burst length. */ +typedef enum _semc_sdram_burst_len +{ + kSEMC_Sdram_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Sdram_BurstLen2, /*!< Burst length 2*/ + kSEMC_Sdram_BurstLen4, /*!< Burst length 4*/ + kSEMC_Sdram_BurstLen8 /*!< Burst length 8*/ +} sem_sdram_burst_len_t; + +/*! @brief SEMC nand column address bit number. */ +typedef enum _semc_nand_column_bit_num +{ + kSEMC_NandColum_16bit = 0x0U, /*!< 16 bit. */ + kSEMC_NandColum_15bit, /*!< 15 bit. */ + kSEMC_NandColum_14bit, /*!< 14 bit. */ + kSEMC_NandColum_13bit, /*!< 13 bit. */ + kSEMC_NandColum_12bit, /*!< 12 bit. */ + kSEMC_NandColum_11bit, /*!< 11 bit. */ + kSEMC_NandColum_10bit, /*!< 10 bit. */ + kSEMC_NandColum_9bit, /*!< 9 bit. */ +} semc_nand_column_bit_num_t; + +/*! @brief SEMC nand burst length. */ +typedef enum _semc_nand_burst_len +{ + kSEMC_Nand_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Nand_BurstLen2, /*!< Burst length 2*/ + kSEMC_Nand_BurstLen4, /*!< Burst length 4*/ + kSEMC_Nand_BurstLen8, /*!< Burst length 8*/ + kSEMC_Nand_BurstLen16, /*!< Burst length 16*/ + kSEMC_Nand_BurstLen32, /*!< Burst length 32*/ + kSEMC_Nand_BurstLen64 /*!< Burst length 64*/ +} sem_nand_burst_len_t; + +/*! @brief SEMC nor/sram column address bit number. */ +typedef enum _semc_norsram_column_bit_num +{ + kSEMC_NorColum_12bit = 0x0U, /*!< 12 bit. */ + kSEMC_NorColum_11bit, /*!< 11 bit. */ + kSEMC_NorColum_10bit, /*!< 10 bit. */ + kSEMC_NorColum_9bit, /*!< 9 bit. */ + kSEMC_NorColum_8bit, /*!< 8 bit. */ + kSEMC_NorColum_7bit, /*!< 7 bit. */ + kSEMC_NorColum_6bit, /*!< 6 bit. */ + kSEMC_NorColum_5bit, /*!< 5 bit. */ + kSEMC_NorColum_4bit, /*!< 4 bit. */ + kSEMC_NorColum_3bit, /*!< 3 bit. */ + kSEMC_NorColum_2bit /*!< 2 bit. */ +} semc_norsram_column_bit_num_t; + +/*! @brief SEMC nor/sram burst length. */ +typedef enum _semc_norsram_burst_len +{ + kSEMC_Nor_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Nor_BurstLen2, /*!< Burst length 2*/ + kSEMC_Nor_BurstLen4, /*!< Burst length 4*/ + kSEMC_Nor_BurstLen8, /*!< Burst length 8*/ + kSEMC_Nor_BurstLen16, /*!< Burst length 16*/ + kSEMC_Nor_BurstLen32, /*!< Burst length 32*/ + kSEMC_Nor_BurstLen64 /*!< Burst length 64*/ +} sem_norsram_burst_len_t; + +/*! @brief SEMC dbi column address bit number. */ +typedef enum _semc_dbi_column_bit_num +{ + kSEMC_Dbi_Colum_12bit = 0x0U, /*!< 12 bit. */ + kSEMC_Dbi_Colum_11bit, /*!< 11 bit. */ + kSEMC_Dbi_Colum_10bit, /*!< 10 bit. */ + kSEMC_Dbi_Colum_9bit, /*!< 9 bit. */ + kSEMC_Dbi_Colum_8bit, /*!< 8 bit. */ + kSEMC_Dbi_Colum_7bit, /*!< 7 bit. */ + kSEMC_Dbi_Colum_6bit, /*!< 6 bit. */ + kSEMC_Dbi_Colum_5bit, /*!< 5 bit. */ + kSEMC_Dbi_Colum_4bit, /*!< 4 bit. */ + kSEMC_Dbi_Colum_3bit, /*!< 3 bit. */ + kSEMC_Dbi_Colum_2bit /*!< 2 bit. */ +} semc_dbi_column_bit_num_t; + +/*! @brief SEMC dbi burst length. */ +typedef enum _semc_dbi_burst_len +{ + kSEMC_Dbi_BurstLen1 = 0, /*!< Burst length 1*/ + kSEMC_Dbi_BurstLen2, /*!< Burst length 2*/ + kSEMC_Dbi_Dbi_BurstLen4, /*!< Burst length 4*/ + kSEMC_Dbi_BurstLen8, /*!< Burst length 8*/ + kSEMC_Dbi_BurstLen16, /*!< Burst length 16*/ + kSEMC_Dbi_BurstLen32, /*!< Burst length 32*/ + kSEMC_Dbi_BurstLen64 /*!< Burst length 64*/ +} sem_dbi_burst_len_t; + +/*! @brief SEMC IOMUXC. */ +typedef enum _semc_iomux_pin +{ + kSEMC_MUXA8 = SEMC_IOCR_MUX_A8_SHIFT, /*!< MUX A8 pin. */ + kSEMC_MUXCSX0 = SEMC_IOCR_MUX_CSX0_SHIFT, /*!< MUX CSX0 pin */ + kSEMC_MUXCSX1 = SEMC_IOCR_MUX_CSX1_SHIFT, /*!< MUX CSX1 Pin.*/ + kSEMC_MUXCSX2 = SEMC_IOCR_MUX_CSX2_SHIFT, /*!< MUX CSX2 Pin. */ + kSEMC_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */ + kSEMC_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */ +} semc_iomux_pin; + +/*! @brief SEMC NOR/PSRAM Address bit 27 A27. */ +typedef enum _semc_iomux_nora27_pin +{ + kSEMC_MORA27_NONE = 0, /*!< No NOR/SRAM A27 pin. */ + kSEMC_NORA27_MUXCSX3 = SEMC_IOCR_MUX_CSX3_SHIFT, /*!< MUX CSX3 Pin. */ + kSEMC_NORA27_MUXRDY = SEMC_IOCR_MUX_RDY_SHIFT /*!< MUX RDY pin. */ +} semc_iomux_nora27_pin; + +/*! @brief SEMC port size. */ +typedef enum _semc_port_size +{ + kSEMC_PortSize8Bit = 0, /*!< 8-Bit port size. */ + kSEMC_PortSize16Bit /*!< 16-Bit port size. */ +} smec_port_size_t; + +/*! @brief SEMC address mode. */ +typedef enum _semc_addr_mode +{ + kSEMC_AddrDataMux = 0, /*!< SEMC address/data mux mode. */ + kSEMC_AdvAddrdataMux, /*!< Advanced address/data mux mode. */ + kSEMC_AddrDataNonMux /*!< Address/data non-mux mode. */ +} semc_addr_mode_t; + +/*! @brief SEMC DQS read strobe mode. */ +typedef enum _semc_dqs_mode +{ + kSEMC_Loopbackinternal = 0, /*!< Dummy read strobe loopbacked internally. */ + kSEMC_Loopbackdqspad, /*!< Dummy read strobe loopbacked from DQS pad. */ +} semc_dqs_mode_t; + +/*! @brief SEMC ADV signal active polarity. */ +typedef enum _semc_adv_polarity +{ + kSEMC_AdvActiveLow = 0, /*!< Adv active low. */ + kSEMC_AdvActivehigh, /*!< Adv active low. */ +} semc_adv_polarity_t; + +/*! @brief SEMC RDY signal active polarity. */ +typedef enum _semc_rdy_polarity +{ + kSEMC_RdyActiveLow = 0, /*!< Adv active low. */ + kSEMC_RdyActivehigh, /*!< Adv active low. */ +} semc_rdy_polarity_t; + +/*! @brief SEMC IP command for NAND: address mode. */ +typedef enum _semc_ipcmd_nand_addrmode +{ + kSEMC_NANDAM_ColumnRow = 0x0U, /*!< Address mode: column and row address(5Byte-CA0/CA1/RA0/RA1/RA2). */ + kSEMC_NANDAM_ColumnCA0, /*!< Address mode: column address only(1 Byte-CA0). */ + kSEMC_NANDAM_ColumnCA0CA1, /*!< Address mode: column address only(2 Byte-CA0/CA1). */ + kSEMC_NANDAM_RawRA0, /*!< Address mode: row address only(1 Byte-RA0). */ + kSEMC_NANDAM_RawRA0RA1, /*!< Address mode: row address only(2 Byte-RA0/RA1). */ + kSEMC_NANDAM_RawRA0RA1RA2 /*!< Address mode: row address only(3 Byte-RA0). */ +} semc_ipcmd_nand_addrmode_t; + +/*! @brief SEMC IP command for NAND： command mode. */ +typedef enum _semc_ipcmd_nand_cmdmode +{ + kSEMC_NANDCM_Command = 0x2U, /*!< command. */ + kSEMC_NANDCM_CommandHold, /*!< Command hold. */ + kSEMC_NANDCM_CommandAddress, /*!< Command address. */ + kSEMC_NANDCM_CommandAddressHold, /*!< Command address hold. */ + kSEMC_NANDCM_CommandAddressRead, /*!< Command address read. */ + kSEMC_NANDCM_CommandAddressWrite, /*!< Command address write. */ + kSEMC_NANDCM_CommandRead, /*!< Command read. */ + kSEMC_NANDCM_CommandWrite, /*!< Command write. */ + kSEMC_NANDCM_Read, /*!< Read. */ + kSEMC_NANDCM_Write /*!< Write. */ +} semc_ipcmd_nand_cmdmode_t; + +/*! @brief SEMC NAND address option. */ +typedef enum _semc_nand_address_option +{ + kSEMC_NandAddrOption_5byte_CA2RA3 = 0U, /*!< CA0+CA1+RA0+RA1+RA2 */ + kSEMC_NandAddrOption_4byte_CA2RA2 = 2U, /*!< CA0+CA1+RA0+RA1 */ + kSEMC_NandAddrOption_3byte_CA2RA1 = 4U, /*!< CA0+CA1+RA0 */ + kSEMC_NandAddrOption_4byte_CA1RA3 = 1U, /*!< CA0+RA0+RA1+RA2 */ + kSEMC_NandAddrOption_3byte_CA1RA2 = 3U, /*!< CA0+RA0+RA1 */ + kSEMC_NandAddrOption_2byte_CA1RA1 = 7U, /*!< CA0+RA0 */ +} semc_nand_address_option_t; + +/*! @brief SEMC IP command for NOR. */ +typedef enum _semc_ipcmd_nor_dbi +{ + kSEMC_NORDBICM_Read = 0x2U, /*!< NOR read. */ + kSEMC_NORDBICM_Write /*!< NOR write. */ +} semc_ipcmd_nor_dbi_t; + +/*! @brief SEMC IP command for SRAM. */ +typedef enum _semc_ipcmd_sram +{ + kSEMC_SRAMCM_ArrayRead = 0x2U, /*!< SRAM memory array read. */ + kSEMC_SRAMCM_ArrayWrite, /*!< SRAM memory array write. */ + kSEMC_SRAMCM_RegRead, /*!< SRAM memory register read. */ + kSEMC_SRAMCM_RegWrite /*!< SRAM memory register write. */ +} semc_ipcmd_sram_t; + +/*! @brief SEMC IP command for SDARM. */ +typedef enum _semc_ipcmd_sdram +{ + kSEMC_SDRAMCM_Read = 0x8U, /*!< SDRAM memory read. */ + kSEMC_SDRAMCM_Write, /*!< SDRAM memory write. */ + kSEMC_SDRAMCM_Modeset, /*!< SDRAM MODE SET. */ + kSEMC_SDRAMCM_Active, /*!< SDRAM active. */ + kSEMC_SDRAMCM_AutoRefresh, /*!< SDRAM auto-refresh. */ + kSEMC_SDRAMCM_SelfRefresh, /*!< SDRAM self-refresh. */ + kSEMC_SDRAMCM_Precharge, /*!< SDRAM precharge. */ + kSEMC_SDRAMCM_Prechargeall /*!< SDRAM precharge all. */ +} semc_ipcmd_sdram_t; + +/*! @brief SEMC SDRAM configuration structure. + * + * 1. The memory size in the configuration is in the unit of KB. So memsize_kbytes + * should be set as 2^2, 2^3, 2^4 .etc which is base 2KB exponential function. + * Take refer to BR0~BR3 register in RM for details. + * 2. The prescalePeriod_N16Cycle is in unit of 16 clock cycle. It is a exception for prescaleTimer_n16cycle = 0, + * it means the prescaler timer period is 256 * 16 clock cycles. For precalerIf precalerTimer_n16cycle not equal to 0, + * The prescaler timer period is prescalePeriod_N16Cycle * 16 clock cycles. + * idleTimeout_NprescalePeriod, refreshUrgThreshold_NprescalePeriod, refreshPeriod_NprescalePeriod are + * similar to prescalePeriod_N16Cycle. + * + */ +typedef struct _semc_sdram_config +{ + semc_iomux_pin csxPinMux; /*!< CS pin mux. The kSEMC_MUXA8 is not valid in sdram pin mux setting. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ + smec_port_size_t portSize; /*!< Port size. */ + sem_sdram_burst_len_t burstLen; /*!< Burst length. */ + semc_sdram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + semc_caslatency_t casLatency; /*!< CAS latency. */ + uint8_t tPrecharge2Act_Ns; /*!< Precharge to active wait time in unit of nanosecond. */ + uint8_t tAct2ReadWrite_Ns; /*!< Act to read/write wait time in unit of nanosecond. */ + uint8_t tRefreshRecovery_Ns; /*!< Refresh recovery time in unit of nanosecond. */ + uint8_t tWriteRecovery_Ns; /*!< write recovery time in unit of nanosecond. */ + uint8_t tCkeOff_Ns; /*!< CKE off minimum time in unit of nanosecond. */ + uint8_t tAct2Prechage_Ns; /*!< Active to precharge in unit of nanosecond. */ + uint8_t tSelfRefRecovery_Ns; /*!< Self refresh recovery time in unit of nanosecond. */ + uint8_t tRefresh2Refresh_Ns; /*!< Refresh to refresh wait time in unit of nanosecond. */ + uint8_t tAct2Act_Ns; /*!< Active to active wait time in unit of nanosecond. */ + uint32_t tPrescalePeriod_Ns; /*!< Prescaler timer period should not be larger than 256 * 16 * clock cycle. */ + uint32_t tIdleTimeout_Ns; /*!< Idle timeout in unit of prescale time period. */ + uint32_t refreshPeriod_nsPerRow; /*!< Refresh timer period like 64ms * 1000000/8192 . */ + uint32_t refreshUrgThreshold; /*!< Refresh urgent threshold. */ + uint8_t refreshBurstLen; /*!< Refresh burst length. */ +} semc_sdram_config_t; + +/*! @brief SEMC NAND device timing configuration structure. */ +typedef struct _semc_nand_timing_config +{ + uint8_t tCeSetup_Ns; /*!< CE setup time: tCS. */ + uint8_t tCeHold_Ns; /*!< CE hold time: tCH. */ + uint8_t tCeInterval_Ns; /*!< CE interval time:tCEITV. */ + uint8_t tWeLow_Ns; /*!< WE low time: tWP. */ + uint8_t tWeHigh_Ns; /*!< WE high time: tWH. */ + uint8_t tReLow_Ns; /*!< RE low time: tRP. */ + uint8_t tReHigh_Ns; /*!< RE high time: tREH. */ + uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode: tTA. */ + uint8_t tWehigh2Relow_Ns; /*!< WE# high to RE# wait time: tWHR. */ + uint8_t tRehigh2Welow_Ns; /*!< RE# high to WE# low wait time: tRHW. */ + uint8_t tAle2WriteStart_Ns; /*!< ALE to write start wait time: tADL. */ + uint8_t tReady2Relow_Ns; /*!< Ready to RE# low min wait time: tRR. */ + uint8_t tWehigh2Busy_Ns; /*!< WE# high to busy wait time: tWB. */ +} semc_nand_timing_config_t; + +/*! @brief SEMC NAND configuration structure. */ +typedef struct _semc_nand_config +{ + semc_iomux_pin cePinMux; /*!< The CE pin mux setting. The kSEMC_MUXRDY is not valid for CE pin setting. */ + uint32_t axiAddress; /*!< The base address for AXI nand. */ + uint32_t axiMemsize_kbytes; /*!< The memory size in unit of kbytes for AXI nand. */ + uint32_t ipgAddress; /*!< The base address for IPG nand . */ + uint32_t ipgMemsize_kbytes; /*!< The memory size in unit of kbytes for IPG nand. */ + semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */ + bool edoModeEnabled; /*!< EDO mode enabled. */ + semc_nand_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + semc_nand_address_option_t arrayAddrOption; /*!< Address option. */ + sem_nand_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + semc_nand_timing_config_t *timingConfig; /*!< SEMC nand timing configuration. */ +} semc_nand_config_t; + +/*! @brief SEMC NOR configuration structure. */ +typedef struct _semc_nor_config +{ + semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */ + semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ + uint8_t addrPortWidth; /*!< The address port width. */ + semc_rdy_polarity_t rdyactivePolarity; /*!< Wait ready polarity. */ + semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity. */ + semc_norsram_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + semc_addr_mode_t addrMode; /*!< Address mode. */ + sem_norsram_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + uint8_t tCeSetup_Ns; /*!< The CE setup time. */ + uint8_t tCeHold_Ns; /*!< The CE hold time. */ + uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */ + uint8_t tAddrSetup_Ns; /*!< The address setup time. */ + uint8_t tAddrHold_Ns; /*!< The address hold time. */ + uint8_t tWeLow_Ns; /*!< WE low time for async mode. */ + uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */ + uint8_t tReLow_Ns; /*!< RE low time for async mode. */ + uint8_t tReHigh_Ns; /*!< RE high time for async mode. */ + uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */ + uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */ +#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDS_TIME) + uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/ +#endif +#if defined(FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) && (FSL_FEATURE_SEMC_HAS_NOR_WDH_TIME) + uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */ +#endif + uint8_t latencyCount; /*!< Latency count for sync mode. */ + uint8_t readCycle; /*!< Read cycle time for sync mode. */ +} semc_nor_config_t; + +/*! @brief SEMC SRAM configuration structure. */ +typedef struct _semc_sram_config +{ + semc_iomux_pin cePinMux; /*!< The CE# pin mux setting. */ + semc_iomux_nora27_pin addr27; /*!< The Addr bit 27 pin mux setting. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of kbytes. */ + uint8_t addrPortWidth; /*!< The address port width. */ + semc_adv_polarity_t advActivePolarity; /*!< ADV# polarity 1: active high, 0: active low. */ + semc_addr_mode_t addrMode; /*!< Address mode. */ + sem_norsram_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + uint8_t tCeSetup_Ns; /*!< The CE setup time. */ + uint8_t tCeHold_Ns; /*!< The CE hold time. */ + uint8_t tCeInterval_Ns; /*!< CE interval minimum time. */ + uint8_t tAddrSetup_Ns; /*!< The address setup time. */ + uint8_t tAddrHold_Ns; /*!< The address hold time. */ + uint8_t tWeLow_Ns; /*!< WE low time for async mode. */ + uint8_t tWeHigh_Ns; /*!< WE high time for async mode. */ + uint8_t tReLow_Ns; /*!< RE low time for async mode. */ + uint8_t tReHigh_Ns; /*!< RE high time for async mode. */ + uint8_t tTurnAround_Ns; /*!< Turnaround time for async mode. */ + uint8_t tAddr2WriteHold_Ns; /*!< Address to write data hold time for async mode. */ + uint8_t tWriteSetup_Ns; /*!< Write data setup time for sync mode.*/ + uint8_t tWriteHold_Ns; /*!< Write hold time for sync mode. */ + uint8_t latencyCount; /*!< Latency count for sync mode. */ + uint8_t readCycle; /*!< Read cycle time for sync mode. */ +} semc_sram_config_t; + +/*! @brief SEMC DBI configuration structure. */ +typedef struct _semc_dbi_config +{ + semc_iomux_pin csxPinMux; /*!< The CE# pin mux. */ + uint32_t address; /*!< The base address. */ + uint32_t memsize_kbytes; /*!< The memory size in unit of 4kbytes. */ + semc_dbi_column_bit_num_t columnAddrBitNum; /*!< Column address bit number. */ + sem_dbi_burst_len_t burstLen; /*!< Burst length. */ + smec_port_size_t portSize; /*!< Port size. */ + uint8_t tCsxSetup_Ns; /*!< The CSX setup time. */ + uint8_t tCsxHold_Ns; /*!< The CSX hold time. */ + uint8_t tWexLow_Ns; /*!< WEX low time. */ + uint8_t tWexHigh_Ns; /*!< WEX high time. */ + uint8_t tRdxLow_Ns; /*!< RDX low time. */ + uint8_t tRdxHigh_Ns; /*!< RDX high time. */ + uint8_t tCsxInterval_Ns; /*!< Write data setup time.*/ +} semc_dbi_config_t; + +/*! @brief SEMC AXI queue a weight setting structure. */ +typedef struct _semc_queuea_weight_struct +{ + uint32_t qos : 4; /*!< weight of qos for queue 0 . */ + uint32_t aging : 4; /*!< weight of aging for queue 0.*/ + uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 0.*/ + uint32_t slaveHitNoswitch : 8; /*!< weight of read/write no switch for queue 0 .*/ +} semc_queuea_weight_struct_t; + +/*! @brief SEMC AXI queue a weight setting union. */ +typedef union _semc_queuea_weight +{ + semc_queuea_weight_struct_t queueaConfig; /*!< Structure configuration for queueA. */ + uint32_t queueaValue; /*!< Configuration value for queueA which could directly write to the reg. */ +} semc_queuea_weight_t; + +/*! @brief SEMC AXI queue b weight setting structure. */ +typedef struct _semc_queueb_weight_struct +{ + uint32_t qos : 4; /*!< weight of qos for queue 1. */ + uint32_t aging : 4; /*!< weight of aging for queue 1.*/ + uint32_t slaveHitSwith : 8; /*!< weight of read/write switch for queue 1.*/ + uint32_t weightPagehit : 8; /*!< weight of page hit for queue 1 only .*/ + uint32_t bankRotation : 8; /*!< weight of bank rotation for queue 1 only .*/ +} semc_queueb_weight_struct_t; + +/*! @brief SEMC AXI queue b weight setting union. */ +typedef union _semc_queueb_weight +{ + semc_queueb_weight_struct_t queuebConfig; /*!< Structure configuration for queueB. */ + uint32_t queuebValue; /*!< Configuration value for queueB which could directly write to the reg. */ +} semc_queueb_weight_t; + +/*! @brief SEMC AXI queue weight setting. */ +typedef struct _semc_axi_queueweight +{ + semc_queuea_weight_t queueaWeight; /*!< Weight settings for queue a. */ + semc_queueb_weight_t queuebWeight; /*!< Weight settings for queue b. */ +} semc_axi_queueweight_t; + +/*! + * @brief SEMC configuration structure. + * + * busTimeoutCycles: when busTimeoutCycles is zero, the bus timeout cycle is + * 255*1024. otherwise the bus timeout cycles is busTimeoutCycles*1024. + * cmdTimeoutCycles: is used for command execution timeout cycles. it's + * similar to the busTimeoutCycles. + */ +typedef struct _semc_config_t +{ + semc_dqs_mode_t dqsMode; /*!< Dummy read strobe mode: use enum in "semc_dqs_mode_t". */ + uint8_t cmdTimeoutCycles; /*!< Command execution timeout cycles. */ + uint8_t busTimeoutCycles; /*!< Bus timeout cycles. */ + semc_axi_queueweight_t queueWeight; /*!< AXI queue weight. */ +} semc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name SEMC Initialization and De-initialization + * @{ + */ + +/*! + * @brief Gets the SEMC default basic configuration structure. + * + * The purpose of this API is to get the default SEMC + * configure structure for SEMC_Init(). User may use the initialized + * structure unchanged in SEMC_Init(), or modify some fields of the + * structure before calling SEMC_Init(). + * Example: + @code + semc_config_t config; + SEMC_GetDefaultConfig(&config); + @endcode + * @param config The SEMC configuration structure pointer. + */ +void SEMC_GetDefaultConfig(semc_config_t *config); + +/*! + * @brief Initializes SEMC. + * This function ungates the SEMC clock and initializes SEMC. + * This function must be called before calling any other SEMC driver functions. + * + * @param base SEMC peripheral base address. + * @param configure The SEMC configuration structure pointer. + */ +void SEMC_Init(SEMC_Type *base, semc_config_t *configure); + +/*! + * @brief Deinitializes the SEMC module and gates the clock. + * + * This function gates the SEMC clock. As a result, the SEMC module doesn't work after + * calling this function, for some IDE, calling this API may cause the next downloading + * operation failed. so, please call this API cautiously. Additional, users can + * using "#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL (1)" to disable the clock control + * operation in drivers. + * + * @param base SEMC peripheral base address. + */ +void SEMC_Deinit(SEMC_Type *base); + +/* @} */ + +/*! + * @name SEMC Configuration Operation For Each Memory Type + * @{ + */ + +/*! + * @brief Configures SDRAM controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param cs The chip selection. + * @param config The sdram configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures NAND controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The nand configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures NOR controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The nor configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures SRAM controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The sram configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_t clkSrc_Hz); + +/*! + * @brief Configures DBI controller in SEMC. + * + * @param base SEMC peripheral base address. + * @param config The dbi configuration. + * @param clkSrc_Hz The SEMC clock frequency. + */ +status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t clkSrc_Hz); + +/* @} */ + +/*! + * @name SEMC Interrupt Operation + * @{ + */ + +/*! + * @brief Enables the SEMC interrupt. + * + * This function enables the SEMC interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t. + * For example, to enable the IP command done and error interrupt, do the following. + * @code + * SEMC_EnableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt); + * @endcode + * + * @param base SEMC peripheral base address. + * @param mask SEMC interrupts to enable. This is a logical OR of the + * enumeration :: semc_interrupt_enable_t. + */ +static inline void SEMC_EnableInterrupts(SEMC_Type *base, uint32_t mask) +{ + base->INTEN |= mask; +} + +/*! + * @brief Disables the SEMC interrupt. + * + * This function disables the SEMC interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref semc_interrupt_enable_t. + * For example, to disable the IP command done and error interrupt, do the following. + * @code + * SEMC_DisableInterrupts(ENET, kSEMC_IPCmdDoneInterrupt | kSEMC_IPCmdErrInterrupt); + * @endcode + * + * @param base SEMC peripheral base address. + * @param mask SEMC interrupts to disable. This is a logical OR of the + * enumeration :: semc_interrupt_enable_t. + */ +static inline void SEMC_DisableInterrupts(SEMC_Type *base, uint32_t mask) +{ + base->INTEN &= ~mask; +} + +/*! + * @brief Gets the SEMC status. + * + * This function gets the SEMC interrupts event status. + * User can use the a logical OR of enumeration member as a mask. + * See @ref semc_interrupt_enable_t. + * + * @param base SEMC peripheral base address. + * @return status flag, use status flag in semc_interrupt_enable_t to get the related status. + */ +static inline bool SEMC_GetStatusFlag(SEMC_Type *base) +{ + return base->INTR; +} + +/*! + * @brief Clears the SEMC status flag state. + * + * The following status register flags can be cleared SEMC interrupt status. + * + * @param base SEMC base pointer + * @param mask The status flag mask, a logical OR of enumeration member @ref semc_interrupt_enable_t. + */ +static inline void SEMC_ClearStatusFlags(SEMC_Type *base, uint32_t mask) +{ + base->INTR |= mask; +} + +/* @} */ + +/*! + * @name SEMC Memory Access Operation + * @{ + */ + +/*! + * @brief Check if SEMC is in idle. + * + * @param base SEMC peripheral base address. + * @return True SEMC is in idle, false is not in idle. + */ +static inline bool SEMC_IsInIdle(SEMC_Type *base) +{ + return (base->STS0 & SEMC_STS0_IDLE_MASK) ? true : false; +} + +/*! + * @brief SEMC IP command access. + * + * @param base SEMC peripheral base address. + * @param type SEMC memory type. refer to "semc_mem_type_t" + * @param address SEMC device address. + * @param command SEMC IP command. + * For NAND device, we should use the SEMC_BuildNandIPCommand to get the right nand command. + * For NOR/DBI device, take refer to "semc_ipcmd_nor_dbi_t". + * For SRAM device, take refer to "semc_ipcmd_sram_t". + * For SDRAM device, take refer to "semc_ipcmd_sdram_t". + * @param write Data for write access. + * @param read Data pointer for read data out. + */ +status_t SEMC_SendIPCommand( + SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read); + +/*! + * @brief Build SEMC IP command for NAND. + * + * This function build SEMC NAND IP command. The command is build of user command code, + * SEMC address mode and SEMC command mode. + * + * @param userCommand NAND device normal command. + * @param addrMode NAND address mode. Refer to "semc_ipcmd_nand_addrmode_t". + * @param cmdMode NAND command mode. Refer to "semc_ipcmd_nand_cmdmode_t". + */ +static inline uint16_t SEMC_BuildNandIPCommand(uint8_t userCommand, + semc_ipcmd_nand_addrmode_t addrMode, + semc_ipcmd_nand_cmdmode_t cmdMode) +{ + return (uint16_t)((uint16_t)userCommand << 8) | (uint16_t)(addrMode << 4) | ((uint8_t)cmdMode & 0x0Fu); +} + +/*! + * @brief Check if the NAND device is ready. + * + * @param base SEMC peripheral base address. + * @return True NAND is ready, false NAND is not ready. + */ +static inline bool SEMC_IsNandReady(SEMC_Type *base) +{ + return (base->STS0 & SEMC_STS0_NARDY_MASK) ? true : false; +} + +/*! + * @brief SEMC NAND device memory write through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NAND device address. + * @param data Data for write access. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/*! + * @brief SEMC NAND device memory read through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NAND device address. + * @param data Data pointer for data read out. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/*! + * @brief SEMC NOR device memory write through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NOR device address. + * @param data Data for write access. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/*! + * @brief SEMC NOR device memory read through IP command. + * + * @param base SEMC peripheral base address. + * @param address SEMC NOR device address. + * @param data Data pointer for data read out. + * @param size_bytes Data length. + */ +status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data, uint32_t size_bytes); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SEMC_H_*/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_snvs_hp.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_snvs_hp.c new file mode 100644 index 0000000000..c59e9fc035 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_snvs_hp.c @@ -0,0 +1,547 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2017, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_snvs_hp.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.snvs_hp" +#endif + +#define SECONDS_IN_A_DAY (86400U) +#define SECONDS_IN_A_HOUR (3600U) +#define SECONDS_IN_A_MINUTE (60U) +#define DAYS_IN_A_YEAR (365U) +#define YEAR_RANGE_START (1970U) +#define YEAR_RANGE_END (2099U) + +#if !(defined(SNVS_HPSR_PI_MASK)) +#define SNVS_HPSR_PI_MASK (0x2U) +#endif +#if !(defined(SNVS_HPSR_HPTA_MASK)) +#define SNVS_HPSR_HPTA_MASK (0x1U) +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Checks whether the date and time passed in is valid + * + * @param datetime Pointer to structure where the date and time details are stored + * + * @return Returns false if the date & time details are out of range; true if in range + */ +static bool SNVS_HP_CheckDatetimeFormat(const snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from datetime to seconds + * + * @param datetime Pointer to datetime structure where the date and time details are stored + * + * @return The result of the conversion in seconds + */ +static uint32_t SNVS_HP_ConvertDatetimeToSeconds(const snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Converts time data from seconds to a datetime structure + * + * @param seconds Seconds value that needs to be converted to datetime format + * @param datetime Pointer to the datetime structure where the result of the conversion is stored + */ +static void SNVS_HP_ConvertSecondsToDatetime(uint32_t seconds, snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Returns RTC time in seconds. + * + * This function is used internally to get actual RTC time in seconds. + * + * @param base SNVS peripheral base address + * + * @return RTC time in seconds + */ +static uint32_t SNVS_HP_RTC_GetSeconds(SNVS_Type *base); + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) +/*! + * @brief Get the SNVS instance from peripheral base address. + * + * @param base SNVS peripheral base address. + * + * @return SNVS instance. + */ +static uint32_t SNVS_HP_GetInstance(SNVS_Type *base); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) +/*! @brief Pointer to snvs_hp clock. */ +const clock_ip_name_t s_snvsHpClock[] = SNVS_HP_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static bool SNVS_HP_CheckDatetimeFormat(const snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Check year, month, hour, minute, seconds */ + if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || + (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) + { + /* If not correct then error*/ + return false; + } + + /* Adjust the days in February for a leap year */ + if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0)) + { + daysPerMonth[2] = 29U; + } + + /* Check the validity of the day */ + if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) + { + return false; + } + + return true; +} + +static uint32_t SNVS_HP_ConvertDatetimeToSeconds(const snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + /* Number of days from begin of the non Leap-year*/ + /* Number of days from begin of the non Leap-year*/ + uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; + uint32_t seconds; + + /* Compute number of days from 1970 till given year*/ + seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; + /* Add leap year days */ + seconds += ((datetime->year / 4) - (1970U / 4)); + /* Add number of days till given month*/ + seconds += monthDays[datetime->month]; + /* Add days in given month. We subtract the current day as it is + * represented in the hours, minutes and seconds field*/ + seconds += (datetime->day - 1); + /* For leap year if month less than or equal to Febraury, decrement day counter*/ + if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) + { + seconds--; + } + + seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + + (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; + + return seconds; +} + +static void SNVS_HP_ConvertSecondsToDatetime(uint32_t seconds, snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t x; + uint32_t secondsRemaining, days; + uint16_t daysInYear; + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Start with the seconds value that is passed in to be converted to date time format */ + secondsRemaining = seconds; + + /* Calcuate the number of days, we add 1 for the current day which is represented in the + * hours and seconds field + */ + days = secondsRemaining / SECONDS_IN_A_DAY + 1; + + /* Update seconds left*/ + secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; + + /* Calculate the datetime hour, minute and second fields */ + datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; + secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; + datetime->minute = secondsRemaining / 60U; + datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; + + /* Calculate year */ + daysInYear = DAYS_IN_A_YEAR; + datetime->year = YEAR_RANGE_START; + while (days > daysInYear) + { + /* Decrease day count by a year and increment year by 1 */ + days -= daysInYear; + datetime->year++; + + /* Adjust the number of days for a leap year */ + if (datetime->year & 3U) + { + daysInYear = DAYS_IN_A_YEAR; + } + else + { + daysInYear = DAYS_IN_A_YEAR + 1; + } + } + + /* Adjust the days in February for a leap year */ + if (!(datetime->year & 3U)) + { + daysPerMonth[2] = 29U; + } + + for (x = 1U; x <= 12U; x++) + { + if (days <= daysPerMonth[x]) + { + datetime->month = x; + break; + } + else + { + days -= daysPerMonth[x]; + } + } + + datetime->day = days; +} + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) +static uint32_t SNVS_HP_GetInstance(SNVS_Type *base) +{ + return 0U; +} +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! + * brief Initialize the SNVS. + * + * note This API should be called at the beginning of the application using the SNVS driver. + * + * param base SNVS peripheral base address + */ +void SNVS_HP_Init(SNVS_Type *base) +{ +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) + uint32_t instance = SNVS_HP_GetInstance(base); + CLOCK_EnableClock(s_snvsHpClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Deinitialize the SNVS. + * + * param base SNVS peripheral base address + */ +void SNVS_HP_Deinit(SNVS_Type *base) +{ +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) + uint32_t instance = SNVS_HP_GetInstance(base); + CLOCK_DisableClock(s_snvsHpClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Ungates the SNVS clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the SNVS driver. + * + * param base SNVS peripheral base address + * param config Pointer to the user's SNVS configuration structure. + */ +void SNVS_HP_RTC_Init(SNVS_Type *base, const snvs_hp_rtc_config_t *config) +{ + assert(config); + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) + uint32_t instance = SNVS_HP_GetInstance(base); + CLOCK_EnableClock(s_snvsHpClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + base->HPCOMR |= SNVS_HPCOMR_NPSWA_EN_MASK; + + base->HPCR = SNVS_HPCR_PI_FREQ(config->periodicInterruptFreq); + + if (config->rtcCalEnable) + { + base->HPCR |= SNVS_HPCR_HPCALB_VAL_MASK & (config->rtcCalValue << SNVS_HPCR_HPCALB_VAL_SHIFT); + base->HPCR |= SNVS_HPCR_HPCALB_EN_MASK; + } +} + +/*! + * brief Stops the RTC and SRTC timers. + * + * param base SNVS peripheral base address + */ +void SNVS_HP_RTC_Deinit(SNVS_Type *base) +{ + base->HPCR &= ~SNVS_HPCR_RTC_EN_MASK; + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_HP_CLOCKS)) + uint32_t instance = SNVS_HP_GetInstance(base); + CLOCK_DisableClock(s_snvsHpClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Fills in the SNVS config struct with the default settings. + * + * The default values are as follows. + * code + * config->rtccalenable = false; + * config->rtccalvalue = 0U; + * config->PIFreq = 0U; + * endcode + * param config Pointer to the user's SNVS configuration structure. + */ +void SNVS_HP_RTC_GetDefaultConfig(snvs_hp_rtc_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->rtcCalEnable = false; + config->rtcCalValue = 0U; + config->periodicInterruptFreq = 0U; +} + +static uint32_t SNVS_HP_RTC_GetSeconds(SNVS_Type *base) +{ + uint32_t seconds = 0; + uint32_t tmp = 0; + + /* Do consecutive reads until value is correct */ + do + { + seconds = tmp; + tmp = (base->HPRTCMR << 17U) | (base->HPRTCLR >> 15U); + } while (tmp != seconds); + + return seconds; +} + +/*! + * brief Sets the SNVS RTC date and time according to the given time structure. + * + * param base SNVS peripheral base address + * param datetime Pointer to the structure where the date and time details are stored. + * + * return kStatus_Success: Success in setting the time and starting the SNVS RTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ +status_t SNVS_HP_RTC_SetDatetime(SNVS_Type *base, const snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t seconds = 0U; + uint32_t tmp = base->HPCR; + + /* disable RTC */ + SNVS_HP_RTC_StopTimer(base); + + /* Return error if the time provided is not valid */ + if (!(SNVS_HP_CheckDatetimeFormat(datetime))) + { + return kStatus_InvalidArgument; + } + + /* Set time in seconds */ + seconds = SNVS_HP_ConvertDatetimeToSeconds(datetime); + + base->HPRTCMR = (uint32_t)(seconds >> 17U); + base->HPRTCLR = (uint32_t)(seconds << 15U); + + /* reenable RTC in case that it was enabled before */ + if (tmp & SNVS_HPCR_RTC_EN_MASK) + { + SNVS_HP_RTC_StartTimer(base); + } + + return kStatus_Success; +} + +/*! + * brief Gets the SNVS RTC time and stores it in the given time structure. + * + * param base SNVS peripheral base address + * param datetime Pointer to the structure where the date and time details are stored. + */ +void SNVS_HP_RTC_GetDatetime(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + SNVS_HP_ConvertSecondsToDatetime(SNVS_HP_RTC_GetSeconds(base), datetime); +} + +/*! + * brief Sets the SNVS RTC alarm time. + * + * The function sets the RTC alarm. It also checks whether the specified alarm time + * is greater than the present time. If not, the function does not set the alarm + * and returns an error. + * + * param base SNVS peripheral base address + * param alarmTime Pointer to the structure where the alarm time is stored. + * + * return kStatus_Success: success in setting the SNVS RTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed + */ +status_t SNVS_HP_RTC_SetAlarm(SNVS_Type *base, const snvs_hp_rtc_datetime_t *alarmTime) +{ + assert(alarmTime); + + uint32_t alarmSeconds = 0U; + uint32_t currSeconds = 0U; + uint32_t tmp = base->HPCR; + + /* Return error if the alarm time provided is not valid */ + if (!(SNVS_HP_CheckDatetimeFormat(alarmTime))) + { + return kStatus_InvalidArgument; + } + + alarmSeconds = SNVS_HP_ConvertDatetimeToSeconds(alarmTime); + currSeconds = SNVS_HP_RTC_GetSeconds(base); + + /* Return error if the alarm time has passed */ + if (alarmSeconds < currSeconds) + { + return kStatus_Fail; + } + + /* disable RTC alarm interrupt */ + base->HPCR &= ~SNVS_HPCR_HPTA_EN_MASK; + while (base->HPCR & SNVS_HPCR_HPTA_EN_MASK) + { + } + + /* Set alarm in seconds*/ + base->HPTAMR = (uint32_t)(alarmSeconds >> 17U); + base->HPTALR = (uint32_t)(alarmSeconds << 15U); + + /* reenable RTC alarm interrupt in case that it was enabled before */ + base->HPCR = tmp; + + return kStatus_Success; +} + +/*! + * brief Returns the SNVS RTC alarm time. + * + * param base SNVS peripheral base address + * param datetime Pointer to the structure where the alarm date and time details are stored. + */ +void SNVS_HP_RTC_GetAlarm(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t alarmSeconds = 0U; + + /* Get alarm in seconds */ + alarmSeconds = (base->HPTAMR << 17U) | (base->HPTALR >> 15U); + + SNVS_HP_ConvertSecondsToDatetime(alarmSeconds, datetime); +} + +#if (defined(FSL_FEATURE_SNVS_HAS_SRTC) && (FSL_FEATURE_SNVS_HAS_SRTC > 0)) +/*! + * brief The function synchronizes RTC counter value with SRTC. + * + * param base SNVS peripheral base address + */ +void SNVS_HP_RTC_TimeSynchronize(SNVS_Type *base) +{ + uint32_t tmp = base->HPCR; + + /* disable RTC */ + SNVS_HP_RTC_StopTimer(base); + + base->HPCR |= SNVS_HPCR_HP_TS_MASK; + + /* reenable RTC in case that it was enabled before */ + if (tmp & SNVS_HPCR_RTC_EN_MASK) + { + SNVS_HP_RTC_StartTimer(base); + } +} +#endif /* FSL_FEATURE_SNVS_HAS_SRTC */ + +/*! + * brief Gets the SNVS status flags. + * + * param base SNVS peripheral base address + * + * return The status flags. This is the logical OR of members of the + * enumeration ::snvs_status_flags_t + */ +uint32_t SNVS_HP_RTC_GetStatusFlags(SNVS_Type *base) +{ + uint32_t flags = 0U; + + if (base->HPSR & SNVS_HPSR_PI_MASK) + { + flags |= kSNVS_RTC_PeriodicInterruptFlag; + } + + if (base->HPSR & SNVS_HPSR_HPTA_MASK) + { + flags |= kSNVS_RTC_AlarmInterruptFlag; + } + + return flags; +} + +/*! + * brief Gets the enabled SNVS interrupts. + * + * param base SNVS peripheral base address + * + * return The enabled interrupts. This is the logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +uint32_t SNVS_HP_RTC_GetEnabledInterrupts(SNVS_Type *base) +{ + uint32_t val = 0U; + + if (base->HPCR & SNVS_HPCR_PI_EN_MASK) + { + val |= kSNVS_RTC_PeriodicInterrupt; + } + + if (base->HPCR & SNVS_HPCR_HPTA_EN_MASK) + { + val |= kSNVS_RTC_AlarmInterrupt; + } + + return val; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_snvs_hp.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_snvs_hp.h new file mode 100644 index 0000000000..0b86d09850 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_snvs_hp.h @@ -0,0 +1,612 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2017-2018, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SNVS_HP_H_ +#define _FSL_SNVS_HP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup snvs_hp + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SNVS_HP_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2 */ +/*@}*/ + +/*! @brief List of SNVS interrupts */ +typedef enum _snvs_hp_interrupts +{ + kSNVS_RTC_AlarmInterrupt = SNVS_HPCR_HPTA_EN_MASK, /*!< RTC time alarm */ + kSNVS_RTC_PeriodicInterrupt = SNVS_HPCR_PI_EN_MASK, /*!< RTC periodic interrupt */ +} snvs_hp_interrupts_t; + +/*! @brief List of SNVS flags */ +typedef enum _snvs_hp_status_flags +{ + kSNVS_RTC_AlarmInterruptFlag = SNVS_HPSR_HPTA_MASK, /*!< RTC time alarm flag */ + kSNVS_RTC_PeriodicInterruptFlag = SNVS_HPSR_PI_MASK, /*!< RTC periodic interrupt flag */ + kSNVS_ZMK_ZeroFlag = (int)SNVS_HPSR_ZMK_ZERO_MASK, /*!< The ZMK is zero */ + kSNVS_OTPMK_ZeroFlag = SNVS_HPSR_OTPMK_ZERO_MASK, /*!< The OTPMK is zero */ +} snvs_hp_status_flags_t; + +/*! @brief List of SNVS security violation flags */ +typedef enum _snvs_hp_sv_status_flags +{ + kSNVS_LP_ViolationFlag = SNVS_HPSVSR_SW_LPSV_MASK, /*!< Low Power section Security Violation */ + kSNVS_ZMK_EccFailFlag = SNVS_HPSVSR_ZMK_ECC_FAIL_MASK, /*!< Zeroizable Master Key Error Correcting Code Check + Failure */ + kSNVS_LP_SoftwareViolationFlag = SNVS_HPSVSR_SW_LPSV_MASK, /*!< LP Software Security Violation */ + kSNVS_FatalSoftwareViolationFlag = SNVS_HPSVSR_SW_FSV_MASK, /*!< Software Fatal Security Violation */ + kSNVS_SoftwareViolationFlag = SNVS_HPSVSR_SW_SV_MASK, /*!< Software Security Violation */ + kSNVS_Violation0Flag = SNVS_HPSVSR_SV0_MASK, /*!< Security Violation 0 */ + kSNVS_Violation1Flag = SNVS_HPSVSR_SV1_MASK, /*!< Security Violation 1 */ + kSNVS_Violation2Flag = SNVS_HPSVSR_SV2_MASK, /*!< Security Violation 2 */ + kSNVS_Violation3Flag = SNVS_HPSVSR_SV3_MASK, /*!< Security Violation 3 */ + kSNVS_Violation4Flag = SNVS_HPSVSR_SV4_MASK, /*!< Security Violation 4 */ + kSNVS_Violation5Flag = SNVS_HPSVSR_SV5_MASK, /*!< Security Violation 5 */ +} snvs_hp_sv_status_flags_t; + +/*! + * @brief Macro to make security violation flag + * + * Macro help to make security violation flag kSNVS_Violation0Flag to kSNVS_Violation5Flag, + * For example, SNVS_MAKE_HP_SV_FLAG(0) is kSNVS_Violation0Flag. + */ +#define SNVS_MAKE_HP_SV_FLAG(x) (1U << (SNVS_HPSVSR_SV0_SHIFT + (x))) + +/*! @brief Structure is used to hold the date and time */ +typedef struct _snvs_hp_rtc_datetime +{ + uint16_t year; /*!< Range from 1970 to 2099.*/ + uint8_t month; /*!< Range from 1 to 12.*/ + uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ + uint8_t hour; /*!< Range from 0 to 23.*/ + uint8_t minute; /*!< Range from 0 to 59.*/ + uint8_t second; /*!< Range from 0 to 59.*/ +} snvs_hp_rtc_datetime_t; + +/*! + * @brief SNVS config structure + * + * This structure holds the configuration settings for the SNVS peripheral. To initialize this + * structure to reasonable defaults, call the SNVS_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _snvs_hp_rtc_config +{ + bool rtcCalEnable; /*!< true: RTC calibration mechanism is enabled; + false:No calibration is used */ + uint32_t rtcCalValue; /*!< Defines signed calibration value for nonsecure RTC; + This is a 5-bit 2's complement value, range from -16 to +15 */ + uint32_t periodicInterruptFreq; /*!< Defines frequency of the periodic interrupt; + Range from 0 to 15 */ +} snvs_hp_rtc_config_t; + +typedef enum _snvs_hp_ssm_state +{ + kSNVS_SSMInit = 0x00, /*!< Init */ + kSNVS_SSMHardFail = 0x01, /*!< Hard Fail */ + kSNVS_SSMSoftFail = 0x03, /*!< Soft Fail */ + kSNVS_SSMInitInter = 0x08, /*!< Init Intermediate (transition state between Init and Check) */ + kSNVS_SSMCheck = 0x09, /*!< Check */ + kSNVS_SSMNonSecure = 0x0B, /*!< Non-Secure */ + kSNVS_SSMTrusted = 0x0D, /*!< Trusted */ + kSNVS_SSMSecure = 0x0F, /*!< Secure */ +} snvs_hp_ssm_state_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initialize the SNVS. + * + * @note This API should be called at the beginning of the application using the SNVS driver. + * + * @param base SNVS peripheral base address + */ +void SNVS_HP_Init(SNVS_Type *base); + +/*! + * @brief Deinitialize the SNVS. + * + * @param base SNVS peripheral base address + */ +void SNVS_HP_Deinit(SNVS_Type *base); + +/*! + * @brief Ungates the SNVS clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the SNVS driver. + * + * @param base SNVS peripheral base address + * @param config Pointer to the user's SNVS configuration structure. + */ +void SNVS_HP_RTC_Init(SNVS_Type *base, const snvs_hp_rtc_config_t *config); + +/*! + * @brief Stops the RTC and SRTC timers. + * + * @param base SNVS peripheral base address + */ +void SNVS_HP_RTC_Deinit(SNVS_Type *base); + +/*! + * @brief Fills in the SNVS config struct with the default settings. + * + * The default values are as follows. + * @code + * config->rtccalenable = false; + * config->rtccalvalue = 0U; + * config->PIFreq = 0U; + * @endcode + * @param config Pointer to the user's SNVS configuration structure. + */ +void SNVS_HP_RTC_GetDefaultConfig(snvs_hp_rtc_config_t *config); + +/*! @}*/ + +/*! + * @name Non secure RTC current Time & Alarm + * @{ + */ + +/*! + * @brief Sets the SNVS RTC date and time according to the given time structure. + * + * @param base SNVS peripheral base address + * @param datetime Pointer to the structure where the date and time details are stored. + * + * @return kStatus_Success: Success in setting the time and starting the SNVS RTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ +status_t SNVS_HP_RTC_SetDatetime(SNVS_Type *base, const snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Gets the SNVS RTC time and stores it in the given time structure. + * + * @param base SNVS peripheral base address + * @param datetime Pointer to the structure where the date and time details are stored. + */ +void SNVS_HP_RTC_GetDatetime(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime); + +/*! + * @brief Sets the SNVS RTC alarm time. + * + * The function sets the RTC alarm. It also checks whether the specified alarm time + * is greater than the present time. If not, the function does not set the alarm + * and returns an error. + * + * @param base SNVS peripheral base address + * @param alarmTime Pointer to the structure where the alarm time is stored. + * + * @return kStatus_Success: success in setting the SNVS RTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed + */ +status_t SNVS_HP_RTC_SetAlarm(SNVS_Type *base, const snvs_hp_rtc_datetime_t *alarmTime); + +/*! + * @brief Returns the SNVS RTC alarm time. + * + * @param base SNVS peripheral base address + * @param datetime Pointer to the structure where the alarm date and time details are stored. + */ +void SNVS_HP_RTC_GetAlarm(SNVS_Type *base, snvs_hp_rtc_datetime_t *datetime); + +#if (defined(FSL_FEATURE_SNVS_HAS_SRTC) && (FSL_FEATURE_SNVS_HAS_SRTC > 0)) +/*! + * @brief The function synchronizes RTC counter value with SRTC. + * + * @param base SNVS peripheral base address + */ +void SNVS_HP_RTC_TimeSynchronize(SNVS_Type *base); +#endif /* FSL_FEATURE_SNVS_HAS_SRTC */ + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected SNVS interrupts. + * + * @param base SNVS peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +static inline void SNVS_HP_RTC_EnableInterrupts(SNVS_Type *base, uint32_t mask) +{ + base->HPCR |= mask; +} + +/*! + * @brief Disables the selected SNVS interrupts. + * + * @param base SNVS peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +static inline void SNVS_HP_RTC_DisableInterrupts(SNVS_Type *base, uint32_t mask) +{ + base->HPCR &= ~mask; +} + +/*! + * @brief Gets the enabled SNVS interrupts. + * + * @param base SNVS peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +uint32_t SNVS_HP_RTC_GetEnabledInterrupts(SNVS_Type *base); + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the SNVS status flags. + * + * @param base SNVS peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::snvs_status_flags_t + */ +uint32_t SNVS_HP_RTC_GetStatusFlags(SNVS_Type *base); + +/*! + * @brief Clears the SNVS status flags. + * + * @param base SNVS peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::snvs_status_flags_t + */ +static inline void SNVS_HP_RTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask) +{ + base->HPSR |= mask; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the SNVS RTC time counter. + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_HP_RTC_StartTimer(SNVS_Type *base) +{ + base->HPCR |= SNVS_HPCR_RTC_EN_MASK; + while (!(base->HPCR & SNVS_HPCR_RTC_EN_MASK)) + { + } +} + +/*! + * @brief Stops the SNVS RTC time counter. + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_HP_RTC_StopTimer(SNVS_Type *base) +{ + base->HPCR &= ~SNVS_HPCR_RTC_EN_MASK; + while (base->HPCR & SNVS_HPCR_RTC_EN_MASK) + { + } +} + +/*! @}*/ + +/*! + * @brief Enable or disable master key selection. + * + * @param base SNVS peripheral base address + * @param enable Pass true to enable, false to disable. + */ +static inline void SNVS_HP_EnableMasterKeySelection(SNVS_Type *base, bool enable) +{ + if (enable) + { + base->HPCOMR |= SNVS_HPCOMR_MKS_EN_MASK; + } + else + { + base->HPCOMR &= (~SNVS_HPCOMR_MKS_EN_MASK); + } +} + +/*! + * @brief Trigger to program Zeroizable Master Key. + * + * @param base SNVS peripheral base address + * @param enable Pass true to enable, false to disable. + */ +static inline void SNVS_HP_ProgramZeroizableMasterKey(SNVS_Type *base) +{ + base->HPCOMR |= SNVS_HPCOMR_PROG_ZMK_MASK; +} + +/*! + * @brief Trigger SSM State Transition + * + * Trigger state transition of the system security monitor (SSM). It results only + * the following transitions of the SSM: + * - Check State -> Non-Secure (when Non-Secure Boot and not in Fab Configuration) + * - Check State --> Trusted (when Secure Boot or in Fab Configuration ) + * - Trusted State --> Secure + * - Secure State --> Trusted + * - Soft Fail --> Non-Secure + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_HP_ChangeSSMState(SNVS_Type *base) +{ + base->HPCOMR |= SNVS_HPCOMR_SSM_ST_MASK; +} + +/*! + * @brief Trigger Software Fatal Security Violation + * + * The result SSM state transition is: + * - Check State -> Soft Fail + * - Non-Secure State -> Soft Fail + * - Trusted State -> Soft Fail + * - Secure State -> Soft Fail + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_HP_SetSoftwareFatalSecurityViolation(SNVS_Type *base) +{ + base->HPCOMR |= SNVS_HPCOMR_SW_FSV_MASK; +} + +/*! + * @brief Trigger Software Security Violation + * + * The result SSM state transition is: + * - Check -> Non-Secure + * - Trusted -> Soft Fail + * - Secure -> Soft Fail + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_HP_SetSoftwareSecurityViolation(SNVS_Type *base) +{ + base->HPCOMR |= SNVS_HPCOMR_SW_SV_MASK; +} + +/*! + * @brief Get current SSM State + * + * @param base SNVS peripheral base address + * @return Current SSM state + */ +static inline snvs_hp_ssm_state_t SNVS_HP_GetSSMState(SNVS_Type *base) +{ + return (snvs_hp_ssm_state_t)((base->HPSR & SNVS_HPSR_SSM_STATE_MASK) >> SNVS_HPSR_SSM_STATE_SHIFT); +} + +/*! + * @brief Reset the SNVS LP section. + * + * Reset the LP section except SRTC and Time alarm. + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_HP_ResetLP(SNVS_Type *base) +{ + base->HPCOMR |= SNVS_HPCOMR_LP_SWR_MASK; +} + +/*! + * @name High Assurance Counter (HAC) + * @{ + */ + +/*! + * @brief Enable or disable the High Assurance Counter (HAC) + * + * @param base SNVS peripheral base address + * @param enable Pass true to enable, false to disable. + */ +static inline void SNVS_HP_EnableHighAssuranceCounter(SNVS_Type *base, bool enable) +{ + if (enable) + { + base->HPCOMR |= SNVS_HPCOMR_HAC_EN_MASK; + } + else + { + base->HPCOMR &= (~SNVS_HPCOMR_HAC_EN_MASK); + } +} + +/*! + * @brief Start or stop the High Assurance Counter (HAC) + * + * @param base SNVS peripheral base address + * @param start Pass true to start, false to stop. + */ +static inline void SNVS_HP_StartHighAssuranceCounter(SNVS_Type *base, bool start) +{ + if (start) + { + base->HPCOMR &= (~SNVS_HPCOMR_HAC_STOP_MASK); + } + else + { + base->HPCOMR |= SNVS_HPCOMR_HAC_STOP_MASK; + } +} + +/*! + * @brief Set the High Assurance Counter (HAC) initialize value. + * + * @param base SNVS peripheral base address + * @param value The initial value to set. + */ +static inline void SNVS_HP_SetHighAssuranceCounterInitialValue(SNVS_Type *base, uint32_t value) +{ + base->HPHACIVR = value; +} + +/*! + * @brief Load the High Assurance Counter (HAC) + * + * This function loads the HAC initialize value to counter register. + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_HP_LoadHighAssuranceCounter(SNVS_Type *base) +{ + base->HPCOMR |= SNVS_HPCOMR_HAC_LOAD_MASK; +} + +/*! + * @brief Get the current High Assurance Counter (HAC) value + * + * @param base SNVS peripheral base address + * @return HAC currnet value. + */ +static inline uint32_t SNVS_HP_GetHighAssuranceCounter(SNVS_Type *base) +{ + return base->HPHACR; +} + +/*! + * @brief Clear the High Assurance Counter (HAC) + * + * This function can be called in a functional or soft fail state. When the HAC + * is enabled: + * - If the HAC is cleared in the soft fail state, the SSM transitions to the + * hard fail state immediately; + * - If the HAC is cleared in functional state, the SSM will transition to + * hard fail immediately after transitioning to soft fail. + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_HP_ClearHighAssuranceCounter(SNVS_Type *base) +{ + base->HPCOMR |= SNVS_HPCOMR_HAC_CLEAR_MASK; +} + +/*! + * @brief Lock the High Assurance Counter (HAC) + * + * Once locked, the HAC initialize value could not be changed, the HAC enable + * status could not be changed. This could only be unlocked by system reset. + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_HP_LockHighAssuranceCounter(SNVS_Type *base) +{ + base->HPLR |= SNVS_HPLR_HAC_L_MASK; +} + +/*! @}*/ + +/*! + * @brief Get the SNVS HP status flags. + * + * The flags are returned as the OR'ed value of @ref snvs_hp_sgtatus_flags_t. + * + * @param base SNVS peripheral base address + * @return The OR'ed value of status flags. + */ +static inline uint32_t SNVS_HP_GetStatusFlags(SNVS_Type *base) +{ + return base->HPSR; +} + +/*! + * @brief Clear the SNVS HP status flags. + * + * The flags to clear are passed in as the OR'ed value of @ref snvs_hp_status_flags_t. + * Only these flags could be cleared using this API. + * - @ref kSNVS_RTC_PeriodicInterruptFlag + * - @ref kSNVS_RTC_AlarmInterruptFlag + * + * @param base SNVS peripheral base address + * @param mask OR'ed value of the flags to clear. + */ +static inline void SNVS_HP_ClearStatusFlags(SNVS_Type *base, uint32_t mask) +{ + base->HPSR = mask; +} + +/*! + * @brief Get the SNVS HP security violation status flags. + * + * The flags are returned as the OR'ed value of @ref snvs_hp_sv_status_flags_t. + * + * @param base SNVS peripheral base address + * @return The OR'ed value of security violation status flags. + */ +static inline uint32_t SNVS_HP_GetSecurityViolationStatusFlags(SNVS_Type *base) +{ + return base->HPSVSR; +} + +/*! + * @brief Clear the SNVS HP security violation status flags. + * + * The flags to clear are passed in as the OR'ed value of @ref snvs_hp_sv_status_flags_t. + * Only these flags could be cleared using this API. + * + * - @ref kSNVS_ZMK_EccFailFlag + * - @ref kSNVS_Violation0Flag + * - @ref kSNVS_Violation1Flag + * - @ref kSNVS_Violation2Flag + * - @ref kSNVS_Violation3Flag + * - @ref kSNVS_Violation4Flag + * - @ref kSNVS_Violation5Flag + * + * @param base SNVS peripheral base address + * @param mask OR'ed value of the flags to clear. + */ +static inline void SNVS_HP_ClearSecurityViolationStatusFlags(SNVS_Type *base, uint32_t mask) +{ + base->HPSVSR = mask; +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SNVS_HP_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_snvs_lp.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_snvs_lp.c new file mode 100644 index 0000000000..96f41cb054 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_snvs_lp.c @@ -0,0 +1,760 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2017, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_snvs_lp.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.snvs_lp" +#endif + +#define SECONDS_IN_A_DAY (86400U) +#define SECONDS_IN_A_HOUR (3600U) +#define SECONDS_IN_A_MINUTE (60U) +#define DAYS_IN_A_YEAR (365U) +#define YEAR_RANGE_START (1970U) +#define YEAR_RANGE_END (2099U) + +#define SNVS_DEFAULT_PGD_VALUE (0x41736166U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Checks whether the date and time passed in is valid + * + * @param datetime Pointer to structure where the date and time details are stored + * + * @return Returns false if the date & time details are out of range; true if in range + */ +static bool SNVS_LP_CheckDatetimeFormat(const snvs_lp_srtc_datetime_t *datetime); + +/*! + * @brief Converts time data from datetime to seconds + * + * @param datetime Pointer to datetime structure where the date and time details are stored + * + * @return The result of the conversion in seconds + */ +static uint32_t SNVS_LP_ConvertDatetimeToSeconds(const snvs_lp_srtc_datetime_t *datetime); + +/*! + * @brief Converts time data from seconds to a datetime structure + * + * @param seconds Seconds value that needs to be converted to datetime format + * @param datetime Pointer to the datetime structure where the result of the conversion is stored + */ +static void SNVS_LP_ConvertSecondsToDatetime(uint32_t seconds, snvs_lp_srtc_datetime_t *datetime); + +/*! + * @brief Returns SRTC time in seconds. + * + * This function is used internally to get actual SRTC time in seconds. + * + * @param base SNVS peripheral base address + * + * @return SRTC time in seconds + */ +static uint32_t SNVS_LP_SRTC_GetSeconds(SNVS_Type *base); + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_LP_CLOCKS)) +/*! + * @brief Get the SNVS instance from peripheral base address. + * + * @param base SNVS peripheral base address. + * + * @return SNVS instance. + */ +static uint32_t SNVS_LP_GetInstance(SNVS_Type *base); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_LP_CLOCKS)) +/*! @brief Pointer to snvs_lp clock. */ +const clock_ip_name_t s_snvsLpClock[] = SNVS_LP_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static bool SNVS_LP_CheckDatetimeFormat(const snvs_lp_srtc_datetime_t *datetime) +{ + assert(datetime); + + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Check year, month, hour, minute, seconds */ + if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) || + (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U)) + { + /* If not correct then error*/ + return false; + } + + /* Adjust the days in February for a leap year */ + if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0)) + { + daysPerMonth[2] = 29U; + } + + /* Check the validity of the day */ + if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U)) + { + return false; + } + + return true; +} + +static uint32_t SNVS_LP_ConvertDatetimeToSeconds(const snvs_lp_srtc_datetime_t *datetime) +{ + assert(datetime); + + /* Number of days from begin of the non Leap-year*/ + /* Number of days from begin of the non Leap-year*/ + uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U}; + uint32_t seconds; + + /* Compute number of days from 1970 till given year*/ + seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; + /* Add leap year days */ + seconds += ((datetime->year / 4) - (1970U / 4)); + /* Add number of days till given month*/ + seconds += monthDays[datetime->month]; + /* Add days in given month. We subtract the current day as it is + * represented in the hours, minutes and seconds field*/ + seconds += (datetime->day - 1); + /* For leap year if month less than or equal to Febraury, decrement day counter*/ + if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) + { + seconds--; + } + + seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) + + (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second; + + return seconds; +} + +static void SNVS_LP_ConvertSecondsToDatetime(uint32_t seconds, snvs_lp_srtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t x; + uint32_t secondsRemaining, days; + uint16_t daysInYear; + /* Table of days in a month for a non leap year. First entry in the table is not used, + * valid months start from 1 + */ + uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U}; + + /* Start with the seconds value that is passed in to be converted to date time format */ + secondsRemaining = seconds; + + /* Calcuate the number of days, we add 1 for the current day which is represented in the + * hours and seconds field + */ + days = secondsRemaining / SECONDS_IN_A_DAY + 1; + + /* Update seconds left*/ + secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; + + /* Calculate the datetime hour, minute and second fields */ + datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; + secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; + datetime->minute = secondsRemaining / 60U; + datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; + + /* Calculate year */ + daysInYear = DAYS_IN_A_YEAR; + datetime->year = YEAR_RANGE_START; + while (days > daysInYear) + { + /* Decrease day count by a year and increment year by 1 */ + days -= daysInYear; + datetime->year++; + + /* Adjust the number of days for a leap year */ + if (datetime->year & 3U) + { + daysInYear = DAYS_IN_A_YEAR; + } + else + { + daysInYear = DAYS_IN_A_YEAR + 1; + } + } + + /* Adjust the days in February for a leap year */ + if (!(datetime->year & 3U)) + { + daysPerMonth[2] = 29U; + } + + for (x = 1U; x <= 12U; x++) + { + if (days <= daysPerMonth[x]) + { + datetime->month = x; + break; + } + else + { + days -= daysPerMonth[x]; + } + } + + datetime->day = days; +} + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_LP_CLOCKS)) +static uint32_t SNVS_LP_GetInstance(SNVS_Type *base) +{ + return 0U; +} +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! + * brief Ungates the SNVS clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the SNVS driver. + * + * param base SNVS peripheral base address + * param config Pointer to the user's SNVS configuration structure. + */ +void SNVS_LP_Init(SNVS_Type *base) +{ +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_LP_CLOCKS)) + uint32_t instance = SNVS_LP_GetInstance(base); + CLOCK_EnableClock(s_snvsLpClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Power glitch detector: set the PGD value and clear the previous status. */ + base->LPPGDR = SNVS_DEFAULT_PGD_VALUE; + base->LPSR = SNVS_LPSR_PGD_MASK; +} + +/*! + * brief Deinit the SNVS LP section. + * + * param base SNVS peripheral base address + */ +void SNVS_LP_Deinit(SNVS_Type *base) +{ +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_LP_CLOCKS)) + uint32_t instance = SNVS_LP_GetInstance(base); + CLOCK_DisableClock(s_snvsLpClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Ungates the SNVS clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the SNVS driver. + * + * param base SNVS peripheral base address + * param config Pointer to the user's SNVS configuration structure. + */ +void SNVS_LP_SRTC_Init(SNVS_Type *base, const snvs_lp_srtc_config_t *config) +{ + assert(config); + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_LP_CLOCKS)) + uint32_t instance = SNVS_LP_GetInstance(base); + CLOCK_EnableClock(s_snvsLpClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + int pin; + + if (config->srtcCalEnable) + { + base->LPCR = SNVS_LPCR_LPCALB_VAL_MASK & (config->srtcCalValue << SNVS_LPCR_LPCALB_VAL_SHIFT); + base->LPCR |= SNVS_LPCR_LPCALB_EN_MASK; + } + + for (pin = kSNVS_ExternalTamper1; pin <= SNVS_LP_MAX_TAMPER; pin++) + { + SNVS_LP_DisableExternalTamper(SNVS, (snvs_lp_external_tamper_t)pin); + SNVS_LP_ClearExternalTamperStatus(SNVS, (snvs_lp_external_tamper_t)pin); + } +} + +/*! + * brief Stops the SRTC timer. + * + * param base SNVS peripheral base address + */ +void SNVS_LP_SRTC_Deinit(SNVS_Type *base) +{ + base->LPCR &= ~SNVS_LPCR_SRTC_ENV_MASK; + +#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && \ + defined(SNVS_LP_CLOCKS)) + uint32_t instance = SNVS_LP_GetInstance(base); + CLOCK_DisableClock(s_snvsLpClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Fills in the SNVS_LP config struct with the default settings. + * + * The default values are as follows. + * code + * config->srtccalenable = false; + * config->srtccalvalue = 0U; + * endcode + * param config Pointer to the user's SNVS configuration structure. + */ +void SNVS_LP_SRTC_GetDefaultConfig(snvs_lp_srtc_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->srtcCalEnable = false; + config->srtcCalValue = 0U; +} + +static uint32_t SNVS_LP_SRTC_GetSeconds(SNVS_Type *base) +{ + uint32_t seconds = 0; + uint32_t tmp = 0; + + /* Do consecutive reads until value is correct */ + do + { + seconds = tmp; + tmp = (base->LPSRTCMR << 17U) | (base->LPSRTCLR >> 15U); + } while (tmp != seconds); + + return seconds; +} + +/*! + * brief Sets the SNVS SRTC date and time according to the given time structure. + * + * param base SNVS peripheral base address + * param datetime Pointer to the structure where the date and time details are stored. + * + * return kStatus_Success: Success in setting the time and starting the SNVS SRTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ +status_t SNVS_LP_SRTC_SetDatetime(SNVS_Type *base, const snvs_lp_srtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t seconds = 0U; + uint32_t tmp = base->LPCR; + + /* disable RTC */ + SNVS_LP_SRTC_StopTimer(base); + + /* Return error if the time provided is not valid */ + if (!(SNVS_LP_CheckDatetimeFormat(datetime))) + { + return kStatus_InvalidArgument; + } + + /* Set time in seconds */ + seconds = SNVS_LP_ConvertDatetimeToSeconds(datetime); + + base->LPSRTCMR = (uint32_t)(seconds >> 17U); + base->LPSRTCLR = (uint32_t)(seconds << 15U); + + /* reenable SRTC in case that it was enabled before */ + if (tmp & SNVS_LPCR_SRTC_ENV_MASK) + { + SNVS_LP_SRTC_StartTimer(base); + } + + return kStatus_Success; +} + +/*! + * brief Gets the SNVS SRTC time and stores it in the given time structure. + * + * param base SNVS peripheral base address + * param datetime Pointer to the structure where the date and time details are stored. + */ +void SNVS_LP_SRTC_GetDatetime(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime) +{ + assert(datetime); + + SNVS_LP_ConvertSecondsToDatetime(SNVS_LP_SRTC_GetSeconds(base), datetime); +} + +/*! + * brief Sets the SNVS SRTC alarm time. + * + * The function sets the SRTC alarm. It also checks whether the specified alarm + * time is greater than the present time. If not, the function does not set the alarm + * and returns an error. + * Please note, that SRTC alarm has limited resolution because only 32 most + * significant bits of SRTC counter are compared to SRTC Alarm register. + * If the alarm time is beyond SRTC resolution, the function does not set the alarm + * and returns an error. + * + * param base SNVS peripheral base address + * param alarmTime Pointer to the structure where the alarm time is stored. + * + * return kStatus_Success: success in setting the SNVS SRTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed or is beyond resolution + */ +status_t SNVS_LP_SRTC_SetAlarm(SNVS_Type *base, const snvs_lp_srtc_datetime_t *alarmTime) +{ + assert(alarmTime); + + uint32_t alarmSeconds = 0U; + uint32_t currSeconds = 0U; + uint32_t tmp = base->LPCR; + + /* Return error if the alarm time provided is not valid */ + if (!(SNVS_LP_CheckDatetimeFormat(alarmTime))) + { + return kStatus_InvalidArgument; + } + + alarmSeconds = SNVS_LP_ConvertDatetimeToSeconds(alarmTime); + currSeconds = SNVS_LP_SRTC_GetSeconds(base); + + /* Return error if the alarm time has passed */ + if (alarmSeconds <= currSeconds) + { + return kStatus_Fail; + } + + /* disable SRTC alarm interrupt */ + base->LPCR &= ~SNVS_LPCR_LPTA_EN_MASK; + while (base->LPCR & SNVS_LPCR_LPTA_EN_MASK) + { + } + + /* Set alarm in seconds*/ + base->LPTAR = alarmSeconds; + + /* reenable SRTC alarm interrupt in case that it was enabled before */ + base->LPCR = tmp; + + return kStatus_Success; +} + +/*! + * brief Returns the SNVS SRTC alarm time. + * + * param base SNVS peripheral base address + * param datetime Pointer to the structure where the alarm date and time details are stored. + */ +void SNVS_LP_SRTC_GetAlarm(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime) +{ + assert(datetime); + + uint32_t alarmSeconds = 0U; + + /* Get alarm in seconds */ + alarmSeconds = base->LPTAR; + + SNVS_LP_ConvertSecondsToDatetime(alarmSeconds, datetime); +} + +/*! + * brief Gets the SNVS status flags. + * + * param base SNVS peripheral base address + * + * return The status flags. This is the logical OR of members of the + * enumeration ::snvs_status_flags_t + */ +uint32_t SNVS_LP_SRTC_GetStatusFlags(SNVS_Type *base) +{ + uint32_t flags = 0U; + + if (base->LPSR & SNVS_LPSR_LPTA_MASK) + { + flags |= kSNVS_SRTC_AlarmInterruptFlag; + } + + return flags; +} + +/*! + * brief Gets the enabled SNVS interrupts. + * + * param base SNVS peripheral base address + * + * return The enabled interrupts. This is the logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +uint32_t SNVS_LP_SRTC_GetEnabledInterrupts(SNVS_Type *base) +{ + uint32_t val = 0U; + + if (base->LPCR & SNVS_LPCR_LPTA_EN_MASK) + { + val |= kSNVS_SRTC_AlarmInterrupt; + } + + return val; +} + +/*! + * brief Enables the specified SNVS external tamper. + * + * param base SNVS peripheral base address + * param pin SNVS external tamper pin + * param polarity Polarity of external tamper + */ +void SNVS_LP_EnableExternalTamper(SNVS_Type *base, + snvs_lp_external_tamper_t pin, + snvs_lp_external_tamper_polarity_t polarity) +{ + switch (pin) + { + case (kSNVS_ExternalTamper1): + base->LPTDCR = (base->LPTDCR & ~(1U << SNVS_LPTDCR_ET1P_SHIFT)) | (polarity << SNVS_LPTDCR_ET1P_SHIFT); + base->LPTDCR |= SNVS_LPTDCR_ET1_EN_MASK; + break; +#if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1) + case (kSNVS_ExternalTamper2): + base->LPTDCR = (base->LPTDCR & ~(1U << SNVS_LPTDCR_ET2P_SHIFT)) | (polarity << SNVS_LPTDCR_ET2P_SHIFT); + base->LPTDCR |= SNVS_LPTDCR_ET2_EN_MASK; + break; + case (kSNVS_ExternalTamper3): + base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET3P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET3P_SHIFT); + base->LPTDC2R |= SNVS_LPTDC2R_ET3_EN_MASK; + break; + case (kSNVS_ExternalTamper4): + base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET4P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET4P_SHIFT); + base->LPTDC2R |= SNVS_LPTDC2R_ET4_EN_MASK; + break; + case (kSNVS_ExternalTamper5): + base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET5P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET5P_SHIFT); + base->LPTDC2R |= SNVS_LPTDC2R_ET5_EN_MASK; + break; + case (kSNVS_ExternalTamper6): + base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET6P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET6P_SHIFT); + base->LPTDC2R |= SNVS_LPTDC2R_ET6_EN_MASK; + break; + case (kSNVS_ExternalTamper7): + base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET7P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET7P_SHIFT); + base->LPTDC2R |= SNVS_LPTDC2R_ET7_EN_MASK; + break; + case (kSNVS_ExternalTamper8): + base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET8P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET8P_SHIFT); + base->LPTDC2R |= SNVS_LPTDC2R_ET8_EN_MASK; + break; + case (kSNVS_ExternalTamper9): + base->LPTDC2R = (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET9P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET9P_SHIFT); + base->LPTDC2R |= SNVS_LPTDC2R_ET9_EN_MASK; + break; + case (kSNVS_ExternalTamper10): + base->LPTDC2R = + (base->LPTDC2R & ~(1U << SNVS_LPTDC2R_ET10P_SHIFT)) | (polarity << SNVS_LPTDC2R_ET10P_SHIFT); + base->LPTDC2R |= SNVS_LPTDC2R_ET10_EN_MASK; + break; +#endif + default: + break; + } +} + +/*! + * brief Disables the specified SNVS external tamper. + * + * param base SNVS peripheral base address + * param pin SNVS external tamper pin + */ +void SNVS_LP_DisableExternalTamper(SNVS_Type *base, snvs_lp_external_tamper_t pin) +{ + switch (pin) + { + case (kSNVS_ExternalTamper1): + base->LPTDCR &= ~SNVS_LPTDCR_ET1_EN_MASK; + break; +#if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1) + case (kSNVS_ExternalTamper2): + base->LPTDCR &= ~SNVS_LPTDCR_ET2_EN_MASK; + break; + case (kSNVS_ExternalTamper3): + base->LPTDC2R &= ~SNVS_LPTDC2R_ET3_EN_MASK; + break; + case (kSNVS_ExternalTamper4): + base->LPTDC2R &= ~SNVS_LPTDC2R_ET4_EN_MASK; + break; + case (kSNVS_ExternalTamper5): + base->LPTDC2R &= ~SNVS_LPTDC2R_ET5_EN_MASK; + break; + case (kSNVS_ExternalTamper6): + base->LPTDC2R &= ~SNVS_LPTDC2R_ET6_EN_MASK; + break; + case (kSNVS_ExternalTamper7): + base->LPTDC2R &= ~SNVS_LPTDC2R_ET7_EN_MASK; + break; + case (kSNVS_ExternalTamper8): + base->LPTDC2R &= ~SNVS_LPTDC2R_ET8_EN_MASK; + break; + case (kSNVS_ExternalTamper9): + base->LPTDC2R &= ~SNVS_LPTDC2R_ET9_EN_MASK; + break; + case (kSNVS_ExternalTamper10): + base->LPTDC2R &= ~SNVS_LPTDC2R_ET10_EN_MASK; + break; +#endif + default: + break; + } +} + +/*! + * brief Returns status of the specified external tamper. + * + * param base SNVS peripheral base address + * param pin SNVS external tamper pin + * + * return The status flag. This is the enumeration ::snvs_external_tamper_status_t + */ +snvs_lp_external_tamper_status_t SNVS_LP_GetExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin) +{ + snvs_lp_external_tamper_status_t status = kSNVS_TamperNotDetected; + + switch (pin) + { + case (kSNVS_ExternalTamper1): + status = (base->LPSR & SNVS_LPSR_ET1D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; +#if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1) + case (kSNVS_ExternalTamper2): + status = (base->LPSR & SNVS_LPSR_ET2D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; + case (kSNVS_ExternalTamper3): + status = (base->LPTDSR & SNVS_LPTDSR_ET3D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; + case (kSNVS_ExternalTamper4): + status = (base->LPTDSR & SNVS_LPTDSR_ET4D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; + case (kSNVS_ExternalTamper5): + status = (base->LPTDSR & SNVS_LPTDSR_ET5D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; + case (kSNVS_ExternalTamper6): + status = (base->LPTDSR & SNVS_LPTDSR_ET6D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; + case (kSNVS_ExternalTamper7): + status = (base->LPTDSR & SNVS_LPTDSR_ET7D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; + case (kSNVS_ExternalTamper8): + status = (base->LPTDSR & SNVS_LPTDSR_ET8D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; + case (kSNVS_ExternalTamper9): + status = (base->LPTDSR & SNVS_LPTDSR_ET9D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; + case (kSNVS_ExternalTamper10): + status = (base->LPTDSR & SNVS_LPTDSR_ET10D_MASK) ? kSNVS_TamperDetected : kSNVS_TamperNotDetected; + break; +#endif + default: + break; + } + return status; +} + +/*! + * brief Clears status of the specified external tamper. + * + * param base SNVS peripheral base address + * param pin SNVS external tamper pin + */ +void SNVS_LP_ClearExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin) +{ + base->LPSR |= SNVS_LPSR_ET1D_MASK; + + switch (pin) + { + case (kSNVS_ExternalTamper1): + base->LPSR |= SNVS_LPSR_ET1D_MASK; + break; +#if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1) + case (kSNVS_ExternalTamper2): + base->LPSR |= SNVS_LPSR_ET2D_MASK; + break; + case (kSNVS_ExternalTamper3): + base->LPTDSR |= SNVS_LPTDSR_ET3D_MASK; + break; + case (kSNVS_ExternalTamper4): + base->LPTDSR |= SNVS_LPTDSR_ET4D_MASK; + break; + case (kSNVS_ExternalTamper5): + base->LPTDSR |= SNVS_LPTDSR_ET5D_MASK; + break; + case (kSNVS_ExternalTamper6): + base->LPTDSR |= SNVS_LPTDSR_ET6D_MASK; + break; + case (kSNVS_ExternalTamper7): + base->LPTDSR |= SNVS_LPTDSR_ET7D_MASK; + break; + case (kSNVS_ExternalTamper8): + base->LPTDSR |= SNVS_LPTDSR_ET8D_MASK; + break; + case (kSNVS_ExternalTamper9): + base->LPTDSR |= SNVS_LPTDSR_ET9D_MASK; + break; + case (kSNVS_ExternalTamper10): + base->LPTDSR |= SNVS_LPTDSR_ET10D_MASK; + break; +#endif + default: + break; + } +} + +/*! + * brief Get the current Monotonic Counter. + * + * param base SNVS peripheral base address + * return Current Monotonic Counter value. + */ +uint64_t SNVS_LP_GetMonotonicCounter(SNVS_Type *base) +{ + uint32_t mc_lsb, mc_msb; + + mc_msb = base->LPSMCMR; + mc_lsb = base->LPSMCLR; + + return ((uint64_t)mc_msb << 32UL) | (uint64_t)mc_lsb; +} + +/*! + * brief Write Zeroizable Master Key (ZMK) to the SNVS registers. + * + * param base SNVS peripheral base address + * param ZMKey The ZMK write to the SNVS register. + */ +void SNVS_LP_WriteZeroizableMasterKey(SNVS_Type *base, uint32_t ZMKey[SNVS_ZMK_REG_COUNT]) +{ + uint8_t i = 0; + + for (i = 0; i < SNVS_ZMK_REG_COUNT; i++) + { + base->LPZMKR[i] = ZMKey[i]; + } +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_snvs_lp.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_snvs_lp.h new file mode 100644 index 0000000000..7f012ccd8a --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_snvs_lp.h @@ -0,0 +1,542 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2017, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SNVS_LP_H_ +#define _FSL_SNVS_LP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup snvs_lp + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SNVS_LP_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */ +/*@}*/ + +#define SNVS_ZMK_REG_COUNT 8 /* 8 Zeroizable Master Key registers. */ + +/*! @brief List of SNVS_LP interrupts */ +typedef enum _snvs_lp_srtc_interrupts +{ + kSNVS_SRTC_AlarmInterrupt = SNVS_LPCR_LPTA_EN_MASK, /*!< SRTC time alarm.*/ +} snvs_lp_srtc_interrupts_t; + +/*! @brief List of SNVS_LP flags */ +typedef enum _snvs_lp_srtc_status_flags +{ + kSNVS_SRTC_AlarmInterruptFlag = SNVS_LPSR_LPTA_MASK, /*!< SRTC time alarm flag */ +} snvs_lp_srtc_status_flags_t; + +/*! @brief List of SNVS_LP external tampers */ +typedef enum _snvs_lp_external_tamper +{ + kSNVS_ExternalTamper1 = 1U, +#if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1) + kSNVS_ExternalTamper2 = 2U, + kSNVS_ExternalTamper3 = 3U, + kSNVS_ExternalTamper4 = 4U, + kSNVS_ExternalTamper5 = 5U, + kSNVS_ExternalTamper6 = 6U, + kSNVS_ExternalTamper7 = 7U, + kSNVS_ExternalTamper8 = 8U, + kSNVS_ExternalTamper9 = 9U, + kSNVS_ExternalTamper10 = 10U +#endif +} snvs_lp_external_tamper_t; + +/* define max possible tamper present */ +#if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 1) +#define SNVS_LP_MAX_TAMPER kSNVS_ExternalTamper10 +#else +#define SNVS_LP_MAX_TAMPER kSNVS_ExternalTamper1 +#endif + +/*! @brief List of SNVS_LP external tampers status */ +typedef enum _snvs_lp_external_tamper_status +{ + kSNVS_TamperNotDetected = 0U, + kSNVS_TamperDetected = 1U +} snvs_lp_external_tamper_status_t; + +/*! @brief SNVS_LP external tamper polarity */ +typedef enum _snvs_lp_external_tamper_polarity +{ + kSNVS_ExternalTamperActiveLow = 0U, + kSNVS_ExternalTamperActiveHigh = 1U +} snvs_lp_external_tamper_polarity_t; + +/*! @brief Structure is used to hold the date and time */ +typedef struct _snvs_lp_srtc_datetime +{ + uint16_t year; /*!< Range from 1970 to 2099.*/ + uint8_t month; /*!< Range from 1 to 12.*/ + uint8_t day; /*!< Range from 1 to 31 (depending on month).*/ + uint8_t hour; /*!< Range from 0 to 23.*/ + uint8_t minute; /*!< Range from 0 to 59.*/ + uint8_t second; /*!< Range from 0 to 59.*/ +} snvs_lp_srtc_datetime_t; + +/*! + * @brief SNVS_LP config structure + * + * This structure holds the configuration settings for the SNVS_LP peripheral. To initialize this + * structure to reasonable defaults, call the SNVS_LP_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _snvs_lp_srtc_config +{ + bool srtcCalEnable; /*!< true: SRTC calibration mechanism is enabled; + false: No calibration is used */ + uint32_t srtcCalValue; /*!< Defines signed calibration value for SRTC; + This is a 5-bit 2's complement value, range from -16 to +15 */ +} snvs_lp_srtc_config_t; + +/*! + * @brief SNVS_LP Zeroizable Master Key programming mode. + */ +typedef enum _snvs_lp_zmk_program_mode +{ + kSNVS_ZMKSoftwareProgram, /*!< Software programming mode. */ + kSNVS_ZMKHardwareProgram, /*!< Hardware programming mode. */ +} snvs_lp_zmk_program_mode_t; + +/*! + * @brief SNVS_LP Master Key mode. + */ +typedef enum _snvs_lp_master_key_mode +{ + kSNVS_OTPMK = 0, /*!< One Time Programmable Master Key. */ + kSNVS_ZMK = 2, /*!< Zeroizable Master Key. */ + kSNVS_CMK = 3, /*!< Combined Master Key, it is XOR of OPTMK and ZMK. */ +} snvs_lp_master_key_mode_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the SNVS clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the SNVS driver. + * + * @param base SNVS peripheral base address + * @param config Pointer to the user's SNVS configuration structure. + */ +void SNVS_LP_Init(SNVS_Type *base); + +/*! + * @brief Deinit the SNVS LP section. + * + * @param base SNVS peripheral base address + */ +void SNVS_LP_Deinit(SNVS_Type *base); + +/*! @}*/ + +/*! + * @brief Ungates the SNVS clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the SNVS driver. + * + * @param base SNVS peripheral base address + * @param config Pointer to the user's SNVS configuration structure. + */ +void SNVS_LP_SRTC_Init(SNVS_Type *base, const snvs_lp_srtc_config_t *config); + +/*! + * @brief Stops the SRTC timer. + * + * @param base SNVS peripheral base address + */ +void SNVS_LP_SRTC_Deinit(SNVS_Type *base); + +/*! + * @brief Fills in the SNVS_LP config struct with the default settings. + * + * The default values are as follows. + * @code + * config->srtccalenable = false; + * config->srtccalvalue = 0U; + * @endcode + * @param config Pointer to the user's SNVS configuration structure. + */ +void SNVS_LP_SRTC_GetDefaultConfig(snvs_lp_srtc_config_t *config); + +/*! + * @name Secure RTC (SRTC) current Time & Alarm + * @{ + */ + +/*! + * @brief Sets the SNVS SRTC date and time according to the given time structure. + * + * @param base SNVS peripheral base address + * @param datetime Pointer to the structure where the date and time details are stored. + * + * @return kStatus_Success: Success in setting the time and starting the SNVS SRTC + * kStatus_InvalidArgument: Error because the datetime format is incorrect + */ +status_t SNVS_LP_SRTC_SetDatetime(SNVS_Type *base, const snvs_lp_srtc_datetime_t *datetime); + +/*! + * @brief Gets the SNVS SRTC time and stores it in the given time structure. + * + * @param base SNVS peripheral base address + * @param datetime Pointer to the structure where the date and time details are stored. + */ +void SNVS_LP_SRTC_GetDatetime(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime); + +/*! + * @brief Sets the SNVS SRTC alarm time. + * + * The function sets the SRTC alarm. It also checks whether the specified alarm + * time is greater than the present time. If not, the function does not set the alarm + * and returns an error. + * Please note, that SRTC alarm has limited resolution because only 32 most + * significant bits of SRTC counter are compared to SRTC Alarm register. + * If the alarm time is beyond SRTC resolution, the function does not set the alarm + * and returns an error. + * + * @param base SNVS peripheral base address + * @param alarmTime Pointer to the structure where the alarm time is stored. + * + * @return kStatus_Success: success in setting the SNVS SRTC alarm + * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect + * kStatus_Fail: Error because the alarm time has already passed or is beyond resolution + */ +status_t SNVS_LP_SRTC_SetAlarm(SNVS_Type *base, const snvs_lp_srtc_datetime_t *alarmTime); + +/*! + * @brief Returns the SNVS SRTC alarm time. + * + * @param base SNVS peripheral base address + * @param datetime Pointer to the structure where the alarm date and time details are stored. + */ +void SNVS_LP_SRTC_GetAlarm(SNVS_Type *base, snvs_lp_srtc_datetime_t *datetime); + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected SNVS interrupts. + * + * @param base SNVS peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +static inline void SNVS_LP_SRTC_EnableInterrupts(SNVS_Type *base, uint32_t mask) +{ + base->LPCR |= mask; +} + +/*! + * @brief Disables the selected SNVS interrupts. + * + * @param base SNVS peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +static inline void SNVS_LP_SRTC_DisableInterrupts(SNVS_Type *base, uint32_t mask) +{ + base->LPCR &= ~mask; +} + +/*! + * @brief Gets the enabled SNVS interrupts. + * + * @param base SNVS peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::snvs_interrupt_enable_t + */ +uint32_t SNVS_LP_SRTC_GetEnabledInterrupts(SNVS_Type *base); + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the SNVS status flags. + * + * @param base SNVS peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::snvs_status_flags_t + */ +uint32_t SNVS_LP_SRTC_GetStatusFlags(SNVS_Type *base); + +/*! + * @brief Clears the SNVS status flags. + * + * @param base SNVS peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::snvs_status_flags_t + */ +static inline void SNVS_LP_SRTC_ClearStatusFlags(SNVS_Type *base, uint32_t mask) +{ + base->LPSR |= mask; +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the SNVS SRTC time counter. + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_LP_SRTC_StartTimer(SNVS_Type *base) +{ + base->LPCR |= SNVS_LPCR_SRTC_ENV_MASK; + while (!(base->LPCR & SNVS_LPCR_SRTC_ENV_MASK)) + { + } +} + +/*! + * @brief Stops the SNVS SRTC time counter. + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_LP_SRTC_StopTimer(SNVS_Type *base) +{ + base->LPCR &= ~SNVS_LPCR_SRTC_ENV_MASK; + while (base->LPCR & SNVS_LPCR_SRTC_ENV_MASK) + { + } +} + +/*! @}*/ + +/*! + * @name External tampering + * @{ + */ + +/*! + * @brief Enables the specified SNVS external tamper. + * + * @param base SNVS peripheral base address + * @param pin SNVS external tamper pin + * @param polarity Polarity of external tamper + */ +void SNVS_LP_EnableExternalTamper(SNVS_Type *base, + snvs_lp_external_tamper_t pin, + snvs_lp_external_tamper_polarity_t polarity); + +/*! + * @brief Disables the specified SNVS external tamper. + * + * @param base SNVS peripheral base address + * @param pin SNVS external tamper pin + */ +void SNVS_LP_DisableExternalTamper(SNVS_Type *base, snvs_lp_external_tamper_t pin); + +/*! + * @brief Returns status of the specified external tamper. + * + * @param base SNVS peripheral base address + * @param pin SNVS external tamper pin + * + * @return The status flag. This is the enumeration ::snvs_external_tamper_status_t + */ +snvs_lp_external_tamper_status_t SNVS_LP_GetExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin); + +/*! + * @brief Clears status of the specified external tamper. + * + * @param base SNVS peripheral base address + * @param pin SNVS external tamper pin + */ +void SNVS_LP_ClearExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin); + +/*! @}*/ + +/*! + * @name Monotonic Counter (MC) + * @{ + */ + +/*! + * @brief Enable or disable the Monotonic Counter. + * + * @param base SNVS peripheral base address + * @param enable Pass true to enable, false to disable. + */ +static inline void SNVS_LP_EnableMonotonicCounter(SNVS_Type *base, bool enable) +{ + if (enable) + { + base->LPCR |= SNVS_LPCR_MC_ENV_MASK; + } + else + { + base->LPCR &= (~SNVS_LPCR_MC_ENV_MASK); + } +} + +/*! + * @brief Get the current Monotonic Counter. + * + * @param base SNVS peripheral base address + * @return Current Monotonic Counter value. + */ +uint64_t SNVS_LP_GetMonotonicCounter(SNVS_Type *base); + +/*! + * @brief Increase the Monotonic Counter. + * + * Increase the Monotonic Counter by 1. + * + * @param base SNVS peripheral base address + */ +static inline void SNVS_LP_IncreaseMonotonicCounter(SNVS_Type *base) +{ + /* Write to the LPSMCLR or LPSMCLR, the counter increases. */ + *((volatile uint32_t *)(&(base->LPSMCLR))) = 0xFFFFFFFFU; +} + +/*! @}*/ + +/*! + * @name Zeroizable Master Key (ZMK) + * @{ + */ + +/*! + * @brief Write Zeroizable Master Key (ZMK) to the SNVS registers. + * + * @param base SNVS peripheral base address + * @param ZMKey The ZMK write to the SNVS register. + */ +void SNVS_LP_WriteZeroizableMasterKey(SNVS_Type *base, uint32_t ZMKey[SNVS_ZMK_REG_COUNT]); + +/*! + * @brief Set Zeroizable Master Key valid. + * + * This API could only be called when using software programming mode. After writing + * ZMK using @ref SNVS_LP_WriteZeroizableMasterKey, call this API to make the ZMK + * valid. + * + * @param base SNVS peripheral base address + * @param valid Pass true to set valid, false to set invalid. + */ +static inline void SNVS_LP_SetZeroizableMasterKeyValid(SNVS_Type *base, bool valid) +{ + if (valid) + { + base->LPMKCR |= SNVS_LPMKCR_ZMK_VAL_MASK; + } + else + { + base->LPMKCR &= (~SNVS_LPMKCR_ZMK_VAL_MASK); + } +} + +/*! + * @brief Get Zeroizable Master Key valid status. + * + * In hardware programming mode, call this API to check whether the ZMK is valid. + * + * @param base SNVS peripheral base address + * @return true if valid, false if invalid. + */ +static inline bool SNVS_LP_GetZeroizableMasterKeyValid(SNVS_Type *base) +{ + return (SNVS_LPMKCR_ZMK_VAL_MASK == (base->LPMKCR & SNVS_LPMKCR_ZMK_VAL_MASK)); +} + +/*! + * @brief Set Zeroizable Master Key programming mode. + * + * @param base SNVS peripheral base address + * @param mode ZMK programming mode. + */ +static inline void SNVS_LP_SetZeroizableMasterKeyProgramMode(SNVS_Type *base, snvs_lp_zmk_program_mode_t mode) +{ + if (kSNVS_ZMKSoftwareProgram == mode) + { + base->LPMKCR &= (~SNVS_LPMKCR_ZMK_HWP_MASK); + } + else + { + base->LPMKCR |= SNVS_LPMKCR_ZMK_HWP_MASK; + } +} + +/*! + * @brief Enable or disable Zeroizable Master Key ECC. + * + * @param base SNVS peripheral base address + * @param enable Pass true to enable, false to disable. + */ +static inline void SNVS_LP_EnableZeroizableMasterKeyECC(SNVS_Type *base, bool enable) +{ + if (enable) + { + base->LPMKCR |= SNVS_LPMKCR_ZMK_ECC_EN_MASK; + } + else + { + base->LPMKCR &= (~SNVS_LPMKCR_ZMK_ECC_EN_MASK); + } +} + +/*! + * @brief Set SNVS Master Key mode. + * + * @param base SNVS peripheral base address + * @param mode Master Key mode. + * @note When @ref kSNVS_ZMK or @ref kSNVS_CMK used, the SNVS_HP must be configured + * to enable the master key selection. + */ +static inline void SNVS_LP_SetMasterKeyMode(SNVS_Type *base, snvs_lp_master_key_mode_t mode) +{ + uint32_t lpmkcr = base->LPMKCR; + lpmkcr = (lpmkcr & (~SNVS_LPMKCR_MASTER_KEY_SEL_MASK)) | SNVS_LPMKCR_MASTER_KEY_SEL(mode); + base->LPMKCR = lpmkcr; +} + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_SNVS_LP_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_spdif.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_spdif.c new file mode 100644 index 0000000000..2431301b5e --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_spdif.c @@ -0,0 +1,831 @@ +/* + * Copyright 2017, NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_spdif.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.spdif" +#endif + +/******************************************************************************* + * Definitations + ******************************************************************************/ +enum _spdif_transfer_state +{ + kSPDIF_Busy = 0x0U, /*!< SPDIF is busy */ + kSPDIF_Idle, /*!< Transfer is done. */ + kSPDIF_Error /*!< Transfer error occurred. */ +}; + +/*! @brief Typedef for spdif tx interrupt handler. */ +typedef void (*spdif_isr_t)(SPDIF_Type *base, spdif_handle_t *handle); +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the instance number for SPDIF. + * + * @param base SPDIF base pointer. + */ +uint32_t SPDIF_GetInstance(SPDIF_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Base pointer array */ +static SPDIF_Type *const s_spdifBases[] = SPDIF_BASE_PTRS; +/*! @brief SPDIF handle pointer */ +spdif_handle_t *s_spdifHandle[ARRAY_SIZE(s_spdifBases)][2]; +/* IRQ number array */ +static const IRQn_Type s_spdifIRQ[] = SPDIF_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Clock name array */ +static const clock_ip_name_t s_spdifClock[] = SPDIF_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/*! @brief Pointer to IRQ handler for each instance. */ +static spdif_isr_t s_spdifTxIsr; +/*! @brief Pointer to IRQ handler for each instance. */ +static spdif_isr_t s_spdifRxIsr; +/*! @brief Used for spdif gain */ +static uint8_t s_spdif_gain[8] = {24U, 16U, 12U, 8U, 6U, 4U, 3U, 1U}; +static uint8_t s_spdif_tx_watermark[4] = {16, 12, 8, 4}; +static uint8_t s_spdif_rx_watermark[4] = {1, 4, 8, 16}; + +/******************************************************************************* + * Code + ******************************************************************************/ +uint32_t SPDIF_GetInstance(SPDIF_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_spdifBases); instance++) + { + if (s_spdifBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_spdifBases)); + + return instance; +} + +/*! + * brief Initializes the SPDIF peripheral. + * + * Ungates the SPDIF clock, resets the module, and configures SPDIF with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SPDIF_GetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the SPDIF driver. Otherwise, accessing the SPDIF module can cause a hard fault + * because the clock is not enabled. + * + * param base SPDIF base pointer + * param config SPDIF configuration structure. + */ +void SPDIF_Init(SPDIF_Type *base, const spdif_config_t *config) +{ + uint32_t val = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the SPDIF clock */ + CLOCK_EnableClock(s_spdifClock[SPDIF_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the internal logic */ + base->SCR |= SPDIF_SCR_SOFT_RESET_MASK; + + /* Waiting for reset finish */ + while (base->SCR & SPDIF_SCR_SOFT_RESET_MASK) + { + } + + /* Setting the SPDIF settings */ + base->SCR = SPDIF_SCR_RXFIFOFULL_SEL(config->rxFullSelect) | SPDIF_SCR_RXAUTOSYNC(config->isRxAutoSync) | + SPDIF_SCR_TXAUTOSYNC(config->isRxAutoSync) | SPDIF_SCR_TXFIFOEMPTY_SEL(config->txFullSelect) | + SPDIF_SCR_TXFIFO_CTRL(1U) | SPDIF_SCR_VALCTRL(config->validityConfig) | + SPDIF_SCR_TXSEL(config->txSource) | SPDIF_SCR_USRC_SEL(config->uChannelSrc); + + /* Set DPLL clock source */ + base->SRPC = SPDIF_SRPC_CLKSRC_SEL(config->DPLLClkSource) | SPDIF_SRPC_GAINSEL(config->gain); + + /* Set SPDIF tx clock source */ + val = base->STC & ~SPDIF_STC_TXCLK_SOURCE_MASK; + val |= SPDIF_STC_TXCLK_SOURCE(config->txClkSource); + base->STC = val; +} + +/*! + * brief De-initializes the SPDIF peripheral. + * + * This API gates the SPDIF clock. The SPDIF module can't operate unless SPDIF_Init is called to enable the clock. + * + * param base SPDIF base pointer + */ +void SPDIF_Deinit(SPDIF_Type *base) +{ + SPDIF_TxEnable(base, false); + SPDIF_RxEnable(base, false); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_spdifClock[SPDIF_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Sets the SPDIF configuration structure to default values. + * + * This API initializes the configuration structure for use in SPDIF_Init. + * The initialized structure can remain unchanged in SPDIF_Init, or it can be modified + * before calling SPDIF_Init. + * This is an example. + code + spdif_config_t config; + SPDIF_GetDefaultConfig(&config); + endcode + * + * param config pointer to master configuration structure + */ +void SPDIF_GetDefaultConfig(spdif_config_t *config) +{ + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->isTxAutoSync = true; + config->isRxAutoSync = true; + config->DPLLClkSource = 1; + config->txClkSource = 1; + config->rxFullSelect = kSPDIF_RxFull8Samples; + config->txFullSelect = kSPDIF_TxEmpty8Samples; + config->uChannelSrc = kSPDIF_UChannelFromTx; + config->txSource = kSPDIF_txNormal; + config->validityConfig = kSPDIF_validityFlagAlwaysClear; + config->gain = kSPDIF_GAIN_8; +} + +/*! + * brief Enables/disables the SPDIF Tx. + * + * param base SPDIF base pointer + * param enable True means enable SPDIF Tx, false means disable. + */ +void SPDIF_TxEnable(SPDIF_Type *base, bool enable) +{ + uint32_t val = 0; + + if (enable) + { + /* Open Tx FIFO */ + val = base->SCR & (~SPDIF_SCR_TXFIFO_CTRL_MASK); + val |= SPDIF_SCR_TXFIFO_CTRL(1U); + base->SCR = val; + /* Enable transfer clock */ + base->STC |= SPDIF_STC_TX_ALL_CLK_EN_MASK; + } + else + { + base->SCR &= ~(SPDIF_SCR_TXFIFO_CTRL_MASK | SPDIF_SCR_TXSEL_MASK); + /* Disable transfer clock */ + base->STC &= ~SPDIF_STC_TX_ALL_CLK_EN_MASK; + } +} + +/*! + * brief Configures the SPDIF Tx sample rate. + * + * The audio format can be changed at run-time. This function configures the sample rate. + * + * param base SPDIF base pointer. + * param sampleRate_Hz SPDIF sample rate frequency in Hz. + * param sourceClockFreq_Hz SPDIF tx clock source frequency in Hz. + */ +void SPDIF_TxSetSampleRate(SPDIF_Type *base, uint32_t sampleRate_Hz, uint32_t sourceClockFreq_Hz) +{ + uint32_t clkDiv = sourceClockFreq_Hz / (sampleRate_Hz * 64); + uint32_t mod = sourceClockFreq_Hz % (sampleRate_Hz * 64); + uint32_t val = 0; + uint8_t clockSource = (((base->STC) & SPDIF_STC_TXCLK_SOURCE_MASK) >> SPDIF_STC_TXCLK_SOURCE_SHIFT); + + /* Compute the nearest divider */ + if (mod > ((sampleRate_Hz * 64) / 2)) + { + clkDiv += 1U; + } + + /* If use divided systeme clock */ + if (clockSource == 5U) + { + if (clkDiv > 256) + { + val = base->STC & (~(SPDIF_STC_TXCLK_DF_MASK | SPDIF_STC_SYSCLK_DF_MASK)); + val |= SPDIF_STC_SYSCLK_DF(clkDiv / 128U - 1U) | SPDIF_STC_TXCLK_DF(127U); + base->STC = val; + } + else + { + val = base->STC & (~(SPDIF_STC_TXCLK_DF_MASK | SPDIF_STC_SYSCLK_DF_MASK)); + val |= SPDIF_STC_SYSCLK_DF(1U) | SPDIF_STC_TXCLK_DF(clkDiv - 1U); + base->STC = val; + } + } + else + { + /* Other clock only uses txclk div */ + val = base->STC & (~(SPDIF_STC_TXCLK_DF_MASK | SPDIF_STC_SYSCLK_DF_MASK)); + val |= SPDIF_STC_TXCLK_DF(clkDiv - 1U); + base->STC = val; + } +} + +/*! + * brief Configures the SPDIF Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * param base SPDIF base pointer. + * param clockSourceFreq_Hz SPDIF system clock frequency in hz. + */ +uint32_t SPDIF_GetRxSampleRate(SPDIF_Type *base, uint32_t clockSourceFreq_Hz) +{ + uint32_t gain = s_spdif_gain[((base->SRPC & SPDIF_SRPC_GAINSEL_MASK) >> SPDIF_SRPC_GAINSEL_SHIFT)]; + uint32_t measure = 0, sampleRate = 0; + uint64_t temp = 0; + + /* Wait the DPLL locked */ + while ((base->SRPC & SPDIF_SRPC_LOCK_MASK) == 0U) + { + } + + /* Get the measure value */ + measure = base->SRFM; + temp = (uint64_t)measure * (uint64_t)clockSourceFreq_Hz; + temp /= (uint64_t)(1024 * 1024 * 128 * gain); + sampleRate = (uint32_t)temp; + + return sampleRate; +} + +/*! + * brief Sends data using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SPDIF base pointer. + * param buffer Pointer to the data to be written. + * param size Bytes to be written. + */ +void SPDIF_WriteBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size) +{ + assert(buffer); + assert(size % 6U == 0U); + + uint32_t i = 0, j = 0, data = 0; + + while (i < size) + { + /* Wait until it can write data */ + while ((SPDIF_GetStatusFlag(base) & kSPDIF_TxFIFOEmpty) == 0U) + { + } + + /* Write left channel data */ + for (j = 0; j < 3U; j++) + { + data |= ((uint32_t)(*buffer) << (j * 8U)); + buffer++; + } + SPDIF_WriteLeftData(base, data); + + /* Write right channel data */ + data = 0; + for (j = 0; j < 3U; j++) + { + data |= ((uint32_t)(*buffer) << (j * 8U)); + buffer++; + } + SPDIF_WriteRightData(base, data); + + i += 6U; + } +} + +/*! + * brief Receives data using a blocking method. + * + * note This function blocks by polling until data is ready to be sent. + * + * param base SPDIF base pointer. + * param buffer Pointer to the data to be read. + * param size Bytes to be read. + */ +void SPDIF_ReadBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size) +{ + assert(buffer); + assert(size % 6U == 0U); + + uint32_t i = 0, j = 0, data = 0; + + while (i < size) + { + /* Wait until it can write data */ + while ((SPDIF_GetStatusFlag(base) & kSPDIF_RxFIFOFull) == 0U) + { + } + + /* Write left channel data */ + data = SPDIF_ReadLeftData(base); + for (j = 0; j < 3U; j++) + { + *buffer = ((data >> (j * 8U)) & 0xFFU); + buffer++; + } + + /* Write right channel data */ + data = SPDIF_ReadRightData(base); + for (j = 0; j < 3U; j++) + { + *buffer = ((data >> (j * 8U)) & 0xFFU); + buffer++; + } + + i += 6U; + } +} + +/*! + * brief Initializes the SPDIF Tx handle. + * + * This function initializes the Tx handle for the SPDIF Tx transactional APIs. Call + * this function once to get the handle initialized. + * + * param base SPDIF base pointer + * param handle SPDIF handle pointer. + * param callback Pointer to the user callback function. + * param userData User parameter passed to the callback function + */ +void SPDIF_TransferTxCreateHandle(SPDIF_Type *base, + spdif_handle_t *handle, + spdif_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + s_spdifHandle[SPDIF_GetInstance(base)][0] = handle; + + handle->callback = callback; + handle->userData = userData; + handle->watermark = + s_spdif_tx_watermark[(base->SCR & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) >> SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT]; + + /* Set the isr pointer */ + s_spdifTxIsr = SPDIF_TransferTxHandleIRQ; + + /* Enable Tx irq */ + EnableIRQ(s_spdifIRQ[SPDIF_GetInstance(base)]); +} + +/*! + * brief Initializes the SPDIF Rx handle. + * + * This function initializes the Rx handle for the SPDIF Rx transactional APIs. Call + * this function once to get the handle initialized. + * + * param base SPDIF base pointer. + * param handle SPDIF handle pointer. + * param callback Pointer to the user callback function. + * param userData User parameter passed to the callback function. + */ +void SPDIF_TransferRxCreateHandle(SPDIF_Type *base, + spdif_handle_t *handle, + spdif_transfer_callback_t callback, + void *userData) +{ + assert(handle); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + s_spdifHandle[SPDIF_GetInstance(base)][1] = handle; + + handle->callback = callback; + handle->userData = userData; + handle->watermark = + s_spdif_rx_watermark[(base->SCR & SPDIF_SCR_RXFIFOFULL_SEL_MASK) >> SPDIF_SCR_RXFIFOFULL_SEL_SHIFT]; + + /* Set the isr pointer */ + s_spdifRxIsr = SPDIF_TransferRxHandleIRQ; + + /* Enable Rx irq */ + EnableIRQ(s_spdifIRQ[SPDIF_GetInstance(base)]); +} + +/*! + * brief Performs an interrupt non-blocking send transfer on SPDIF. + * + * note This API returns immediately after the transfer initiates. + * Call the SPDIF_TxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SPDIF_Busy, the transfer + * is finished. + * + * param base SPDIF base pointer. + * param handle Pointer to the spdif_handle_t structure which stores the transfer state. + * param xfer Pointer to the spdif_transfer_t structure. + * retval kStatus_Success Successfully started the data receive. + * retval kStatus_SPDIF_TxBusy Previous receive still not finished. + * retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SPDIF_TransferSendNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->spdifQueue[handle->queueUser].data) + { + return kStatus_SPDIF_QueueFull; + } + + /* Add into queue */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->spdifQueue[handle->queueUser].data = xfer->data; + handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; + + /* Set the state to busy */ + handle->state = kSPDIF_Busy; + + /* Enable interrupt */ + SPDIF_EnableInterrupts(base, kSPDIF_TxFIFOEmpty); + + /* Enable Tx transfer */ + SPDIF_TxEnable(base, true); + + return kStatus_Success; +} + +/*! + * brief Performs an interrupt non-blocking receive transfer on SPDIF. + * + * note This API returns immediately after the transfer initiates. + * Call the SPDIF_RxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SPDIF_Busy, the transfer + * is finished. + * + * param base SPDIF base pointer + * param handle Pointer to the spdif_handle_t structure which stores the transfer state. + * param xfer Pointer to the spdif_transfer_t structure. + * retval kStatus_Success Successfully started the data receive. + * retval kStatus_SPDIF_RxBusy Previous receive still not finished. + * retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SPDIF_TransferReceiveNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer) +{ + assert(handle); + + /* Check if the queue is full */ + if (handle->spdifQueue[handle->queueUser].data) + { + return kStatus_SPDIF_QueueFull; + } + + /* Add into queue */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->spdifQueue[handle->queueUser].data = xfer->data; + handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->spdifQueue[handle->queueUser].udata = xfer->udata; + handle->spdifQueue[handle->queueUser].qdata = xfer->qdata; + handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; + + /* Set state to busy */ + handle->state = kSPDIF_Busy; + + /* Enable interrupt */ + SPDIF_EnableInterrupts(base, kSPDIF_UChannelReceiveRegisterFull | kSPDIF_QChannelReceiveRegisterFull | + kSPDIF_RxFIFOFull | kSPDIF_RxControlChannelChange); + + /* Enable Rx transfer */ + SPDIF_RxEnable(base, true); + + return kStatus_Success; +} + +/*! + * brief Gets a set byte count. + * + * param base SPDIF base pointer. + * param handle Pointer to the spdif_handle_t structure which stores the transfer state. + * param count Bytes count sent. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SPDIF_TransferGetSendCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSPDIF_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->spdifQueue[handle->queueDriver].dataSize); + } + + return status; +} + +/*! + * brief Gets a received byte count. + * + * param base SPDIF base pointer. + * param handle Pointer to the spdif_handle_t structure which stores the transfer state. + * param count Bytes count received. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SPDIF_TransferGetReceiveCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSPDIF_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - handle->spdifQueue[handle->queueDriver].dataSize); + } + + return status; +} + +/*! + * brief Aborts the current send. + * + * note This API can be called any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base SPDIF base pointer. + * param handle Pointer to the spdif_handle_t structure which stores the transfer state. + */ +void SPDIF_TransferAbortSend(SPDIF_Type *base, spdif_handle_t *handle) +{ + assert(handle); + + /* Use FIFO request interrupt and fifo error */ + SPDIF_DisableInterrupts(base, kSPDIF_TxFIFOEmpty); + + handle->state = kSPDIF_Idle; + + /* Clear the queue */ + memset(handle->spdifQueue, 0, sizeof(spdif_transfer_t) * SPDIF_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +/*! + * brief Aborts the current IRQ receive. + * + * note This API can be called when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base SPDIF base pointer + * param handle Pointer to the spdif_handle_t structure which stores the transfer state. + */ +void SPDIF_TransferAbortReceive(SPDIF_Type *base, spdif_handle_t *handle) +{ + assert(handle); + + /* Disable interrupt */ + SPDIF_DisableInterrupts(base, kSPDIF_UChannelReceiveRegisterFull | kSPDIF_QChannelReceiveRegisterFull | + kSPDIF_RxFIFOFull | kSPDIF_RxControlChannelChange); + + handle->state = kSPDIF_Idle; + + /* Clear the queue */ + memset(handle->spdifQueue, 0, sizeof(spdif_transfer_t) * SPDIF_XFER_QUEUE_SIZE); + handle->queueDriver = 0; + handle->queueUser = 0; +} + +/*! + * brief Tx interrupt handler. + * + * param base SPDIF base pointer. + * param handle Pointer to the spdif_handle_t structure. + */ +void SPDIF_TransferTxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle) +{ + assert(handle); + + uint8_t *buffer = handle->spdifQueue[handle->queueDriver].data; + uint8_t dataSize = 0; + uint32_t i = 0, j = 0, data = 0; + + /* Do Transfer */ + if ((SPDIF_GetStatusFlag(base) & kSPDIF_TxFIFOEmpty) && (base->SIE & kSPDIF_TxFIFOEmpty)) + { + dataSize = handle->watermark; + while (i < dataSize) + { + data = 0; + /* Write left channel data */ + for (j = 0; j < 3U; j++) + { + data |= ((uint32_t)(*buffer) << (j * 8U)); + buffer++; + } + SPDIF_WriteLeftData(base, data); + + /* Write right channel data */ + data = 0; + for (j = 0; j < 3U; j++) + { + data |= ((uint32_t)(*buffer) << (j * 8U)); + buffer++; + } + SPDIF_WriteRightData(base, data); + + i++; + } + handle->spdifQueue[handle->queueDriver].dataSize -= dataSize * 6U; + handle->spdifQueue[handle->queueDriver].data += dataSize * 6U; + + /* If finished a block, call the callback function */ + if (handle->spdifQueue[handle->queueDriver].dataSize == 0U) + { + memset(&handle->spdifQueue[handle->queueDriver], 0, sizeof(spdif_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % SPDIF_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SPDIF_TxIdle, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->spdifQueue[handle->queueDriver].data == NULL) + { + SPDIF_TransferAbortSend(base, handle); + } + } +} + +/*! + * brief Tx interrupt handler. + * + * param base SPDIF base pointer. + * param handle Pointer to the spdif_handle_t structure. + */ +void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle) +{ + assert(handle); + + uint8_t *buffer = NULL; + uint8_t dataSize = 0; + uint32_t i = 0, j = 0, data = 0; + + /* Handle Cnew flag */ + if (SPDIF_GetStatusFlag(base) & kSPDIF_RxControlChannelChange) + { + /* Clear the interrupt flag */ + SPDIF_ClearStatusFlags(base, SPDIF_SIE_CNEW_MASK); + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SPDIF_RxCnew, handle->userData); + } + } + + /* Handle illegal symbol */ + if (SPDIF_GetStatusFlag(base) & kSPDIF_RxIllegalSymbol) + { + SPDIF_ClearStatusFlags(base, kSPDIF_RxIllegalSymbol); + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SPDIF_RxIllegalSymbol, handle->userData); + } + } + + /* Handle Parity Bit Error */ + if (SPDIF_GetStatusFlag(base) & kSPDIF_RxParityBitError) + { + SPDIF_ClearStatusFlags(base, kSPDIF_RxParityBitError); + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SPDIF_RxParityBitError, handle->userData); + } + } + + /* Handle DPlocked */ + if (SPDIF_GetStatusFlag(base) & kSPDIF_RxDPLLLocked) + { + SPDIF_ClearStatusFlags(base, kSPDIF_RxDPLLLocked); + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SPDIF_RxDPLLLocked, handle->userData); + } + } + + /* Handle Q channel full flag */ + if ((SPDIF_GetStatusFlag(base) & kSPDIF_QChannelReceiveRegisterFull) && + (base->SIE & kSPDIF_QChannelReceiveRegisterFull)) + { + buffer = handle->spdifQueue[handle->queueDriver].qdata; + data = SPDIF_ReadQChannel(base); + buffer[0] = data & 0xFFU; + buffer[1] = (data >> 8U) & 0xFFU; + buffer[2] = (data >> 16U) & 0xFFU; + } + + /* Handle U channel full flag */ + if ((SPDIF_GetStatusFlag(base) & kSPDIF_UChannelReceiveRegisterFull) && + (base->SIE & kSPDIF_UChannelReceiveRegisterFull)) + { + buffer = handle->spdifQueue[handle->queueDriver].udata; + data = SPDIF_ReadUChannel(base); + buffer[0] = data & 0xFFU; + buffer[1] = (data >> 8U) & 0xFFU; + buffer[2] = (data >> 16U) & 0xFFU; + } + + /* Handle audio data transfer */ + if ((SPDIF_GetStatusFlag(base) & kSPDIF_RxFIFOFull) && (base->SIE & kSPDIF_RxFIFOFull)) + { + dataSize = handle->watermark; + buffer = handle->spdifQueue[handle->queueDriver].data; + while (i < dataSize) + { + /* Read left channel data */ + data = SPDIF_ReadLeftData(base); + for (j = 0; j < 3U; j++) + { + *buffer = ((data >> (j * 8U)) & 0xFFU); + buffer++; + } + + /* Read right channel data */ + data = SPDIF_ReadRightData(base); + for (j = 0; j < 3U; j++) + { + *buffer = ((data >> (j * 8U)) & 0xFFU); + buffer++; + } + + i++; + } + handle->spdifQueue[handle->queueDriver].dataSize -= dataSize * 6U; + handle->spdifQueue[handle->queueDriver].data += dataSize * 6U; + + /* If finished a block, call the callback function */ + if (handle->spdifQueue[handle->queueDriver].dataSize == 0U) + { + memset(&handle->spdifQueue[handle->queueDriver], 0, sizeof(spdif_transfer_t)); + handle->queueDriver = (handle->queueDriver + 1) % SPDIF_XFER_QUEUE_SIZE; + if (handle->callback) + { + (handle->callback)(base, handle, kStatus_SPDIF_RxIdle, handle->userData); + } + } + + /* If all data finished, just stop the transfer */ + if (handle->spdifQueue[handle->queueDriver].data == NULL) + { + SPDIF_TransferAbortReceive(base, handle); + } + } +} + +#if defined(SPDIF) +void SPDIF_DriverIRQHandler(void) +{ + if ((s_spdifHandle[0][0]) && s_spdifTxIsr) + { + s_spdifTxIsr(SPDIF, s_spdifHandle[0][0]); + } + + if ((s_spdifHandle[0][1]) && s_spdifRxIsr) + { + s_spdifRxIsr(SPDIF, s_spdifHandle[0][1]); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_spdif.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_spdif.h new file mode 100644 index 0000000000..2b4a23ad18 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_spdif.h @@ -0,0 +1,741 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SPDIF_H_ +#define _FSL_SPDIF_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup spdif + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SPDIF_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */ +/*@}*/ + +/*! @brief SPDIF return status*/ +enum _spdif_status_t +{ + kStatus_SPDIF_RxDPLLLocked = MAKE_STATUS(kStatusGroup_SPDIF, 0), /*!< SPDIF Rx PLL locked. */ + kStatus_SPDIF_TxFIFOError = MAKE_STATUS(kStatusGroup_SPDIF, 1), /*!< SPDIF Tx FIFO error. */ + kStatus_SPDIF_TxFIFOResync = MAKE_STATUS(kStatusGroup_SPDIF, 2), /*!< SPDIF Tx left and right FIFO resync. */ + kStatus_SPDIF_RxCnew = MAKE_STATUS(kStatusGroup_SPDIF, 3), /*!< SPDIF Rx status channel value updated. */ + kStatus_SPDIF_ValidatyNoGood = MAKE_STATUS(kStatusGroup_SPDIF, 4), /*!< SPDIF validaty flag not good. */ + kStatus_SPDIF_RxIllegalSymbol = MAKE_STATUS(kStatusGroup_SPDIF, 5), /*!< SPDIF Rx receive illegal symbol. */ + kStatus_SPDIF_RxParityBitError = MAKE_STATUS(kStatusGroup_SPDIF, 6), /*!< SPDIF Rx parity bit error. */ + kStatus_SPDIF_UChannelOverrun = MAKE_STATUS(kStatusGroup_SPDIF, 7), /*!< SPDIF receive U channel overrun. */ + kStatus_SPDIF_QChannelOverrun = MAKE_STATUS(kStatusGroup_SPDIF, 8), /*!< SPDIF receive Q channel overrun. */ + kStatus_SPDIF_UQChannelSync = MAKE_STATUS(kStatusGroup_SPDIF, 9), /*!< SPDIF U/Q channel sync found. */ + kStatus_SPDIF_UQChannelFrameError = MAKE_STATUS(kStatusGroup_SPDIF, 10), /*!< SPDIF U/Q channel frame error. */ + kStatus_SPDIF_RxFIFOError = MAKE_STATUS(kStatusGroup_SPDIF, 11), /*!< SPDIF Rx FIFO error. */ + kStatus_SPDIF_RxFIFOResync = MAKE_STATUS(kStatusGroup_SPDIF, 12), /*!< SPDIF Rx left and right FIFO resync. */ + kStatus_SPDIF_LockLoss = MAKE_STATUS(kStatusGroup_SPDIF, 13), /*!< SPDIF Rx PLL clock lock loss. */ + kStatus_SPDIF_TxIdle = MAKE_STATUS(kStatusGroup_SPDIF, 14), /*!< SPDIF Tx is idle */ + kStatus_SPDIF_RxIdle = MAKE_STATUS(kStatusGroup_SPDIF, 15), /*!< SPDIF Rx is idle */ + kStatus_SPDIF_QueueFull = MAKE_STATUS(kStatusGroup_SPDIF, 16) /*!< SPDIF queue full */ +}; + +/*! @brief SPDIF Rx FIFO full falg select, it decides when assert the rx full flag */ +typedef enum _spdif_rxfull_select +{ + kSPDIF_RxFull1Sample = 0x0u, /*!< Rx full at least 1 sample in left and right FIFO */ + kSPDIF_RxFull4Samples, /*!< Rx full at least 4 sample in left and right FIFO*/ + kSPDIF_RxFull8Samples, /*!< Rx full at least 8 sample in left and right FIFO*/ + kSPDIF_RxFull16Samples, /*!< Rx full at least 16 sample in left and right FIFO*/ +} spdif_rxfull_select_t; + +/*! @brief SPDIF tx FIFO EMPTY falg select, it decides when assert the tx empty flag */ +typedef enum _spdif_txempty_select +{ + kSPDIF_TxEmpty0Sample = 0x0u, /*!< Tx empty at most 0 sample in left and right FIFO */ + kSPDIF_TxEmpty4Samples, /*!< Tx empty at most 4 sample in left and right FIFO*/ + kSPDIF_TxEmpty8Samples, /*!< Tx empty at most 8 sample in left and right FIFO*/ + kSPDIF_TxEmpty12Samples, /*!< Tx empty at most 12 sample in left and right FIFO*/ +} spdif_txempty_select_t; + +/*! @brief SPDIF U channel source */ +typedef enum _spdif_uchannel_source +{ + kSPDIF_NoUChannel = 0x0U, /*!< No embedded U channel */ + kSPDIF_UChannelFromRx = 0x1U, /*!< U channel from receiver, it is CD mode */ + kSPDIF_UChannelFromTx = 0x3U, /*!< U channel from on chip tx */ +} spdif_uchannel_source_t; + +/*! @brief SPDIF clock gain*/ +typedef enum _spdif_gain_select +{ + kSPDIF_GAIN_24 = 0x0U, /*!< Gain select is 24 */ + kSPDIF_GAIN_16, /*!< Gain select is 16 */ + kSPDIF_GAIN_12, /*!< Gain select is 12 */ + kSPDIF_GAIN_8, /*!< Gain select is 8 */ + kSPDIF_GAIN_6, /*!< Gain select is 6 */ + kSPDIF_GAIN_4, /*!< Gain select is 4 */ + kSPDIF_GAIN_3, /*!< Gain select is 3 */ +} spdif_gain_select_t; + +/*! @brief SPDIF tx data source */ +typedef enum _spdif_tx_source +{ + kSPDIF_txFromReceiver = 0x1U, /*!< Tx data directly through SPDIF receiver */ + kSPDIF_txNormal = 0x5U, /*!< Normal operation, data from processor */ +} spdif_tx_source_t; + +/*! @brief SPDIF tx data source */ +typedef enum _spdif_validity_config +{ + kSPDIF_validityFlagAlwaysSet = 0x0U, /*!< Outgoing validity flags always set */ + kSPDIF_validityFlagAlwaysClear, /*!< Outgoing validity flags always clear */ +} spdif_validity_config_t; + +/*! @brief The SPDIF interrupt enable flag */ +enum _spdif_interrupt_enable_t +{ + kSPDIF_RxDPLLLocked = SPDIF_SIE_LOCK_MASK, /*!< SPDIF DPLL locked */ + kSPDIF_TxFIFOError = SPDIF_SIE_TXUNOV_MASK, /*!< Tx FIFO underrun or overrun */ + kSPDIF_TxFIFOResync = SPDIF_SIE_TXRESYN_MASK, /*!< Tx FIFO left and right channel resync */ + kSPDIF_RxControlChannelChange = SPDIF_SIE_CNEW_MASK, /*!< SPDIF Rx control channel value changed */ + kSPDIF_ValidityFlagNoGood = SPDIF_SIE_VALNOGOOD_MASK, /*!< SPDIF validity flag no good */ + kSPDIF_RxIllegalSymbol = SPDIF_SIE_SYMERR_MASK, /*!< SPDIF receiver found illegal symbol */ + kSPDIF_RxParityBitError = SPDIF_SIE_BITERR_MASK, /*!< SPDIF receiver found parity bit error */ + kSPDIF_UChannelReceiveRegisterFull = SPDIF_SIE_URXFUL_MASK, /*!< SPDIF U channel revceive register full */ + kSPDIF_UChannelReceiveRegisterOverrun = SPDIF_SIE_URXOV_MASK, /*!< SPDIF U channel receive register overrun */ + kSPDIF_QChannelReceiveRegisterFull = SPDIF_SIE_QRXFUL_MASK, /*!< SPDIF Q channel receive reigster full */ + kSPDIF_QChannelReceiveRegisterOverrun = SPDIF_SIE_QRXOV_MASK, /*!< SPDIF Q channel receive register overrun */ + kSPDIF_UQChannelSync = SPDIF_SIE_UQSYNC_MASK, /*!< SPDIF U/Q channel sync found */ + kSPDIF_UQChannelFrameError = SPDIF_SIE_UQERR_MASK, /*!< SPDIF U/Q channel frame error */ + kSPDIF_RxFIFOError = SPDIF_SIE_RXFIFOUNOV_MASK, /*!< SPDIF Rx FIFO underrun/overrun */ + kSPDIF_RxFIFOResync = SPDIF_SIE_RXFIFORESYN_MASK, /*!< SPDIF Rx left and right FIFO resync */ + kSPDIF_LockLoss = SPDIF_SIE_LOCKLOSS_MASK, /*!< SPDIF receiver loss of lock */ + kSPDIF_TxFIFOEmpty = SPDIF_SIE_TXEM_MASK, /*!< SPDIF Tx FIFO empty */ + kSPDIF_RxFIFOFull = SPDIF_SIE_RXFIFOFUL_MASK /*!< SPDIF Rx FIFO full */ +}; + +/*! @brief The DMA request sources */ +enum _spdif_dma_enable_t +{ + kSPDIF_RxDMAEnable = SPDIF_SCR_DMA_RX_EN_MASK, /*!< Rx FIFO full */ + kSPDIF_TxDMAEnable = SPDIF_SCR_DMA_TX_EN_MASK, /*!< Tx FIFO empty */ +}; + +/*! @brief SPDIF user configuration structure */ +typedef struct _spdif_config +{ + bool isTxAutoSync; /*!< If auto sync mechanism open */ + bool isRxAutoSync; /*!< If auto sync mechanism open */ + uint8_t DPLLClkSource; /*!< SPDIF DPLL clock source, range from 0~15, meaning is chip-specific */ + uint8_t txClkSource; /*!< SPDIF tx clock source, range from 0~7, meaning is chip-specific */ + spdif_rxfull_select_t rxFullSelect; /*!< SPDIF rx buffer full select */ + spdif_txempty_select_t txFullSelect; /*!< SPDIF tx buffer empty select */ + spdif_uchannel_source_t uChannelSrc; /*!< U channel source */ + spdif_tx_source_t txSource; /*!< SPDIF tx data source */ + spdif_validity_config_t validityConfig; /*!< Validity flag config */ + spdif_gain_select_t gain; /*!< Rx receive clock measure gain parameter. */ +} spdif_config_t; + +/*!@brief SPDIF transfer queue size, user can refine it according to use case. */ +#define SPDIF_XFER_QUEUE_SIZE (4) + +/*! @brief SPDIF transfer structure */ +typedef struct _spdif_transfer +{ + uint8_t *data; /*!< Data start address to transfer. */ + uint8_t *qdata; /*!< Data buffer for Q channel */ + uint8_t *udata; /*!< Data buffer for C channel */ + size_t dataSize; /*!< Transfer size. */ +} spdif_transfer_t; + +typedef struct _spdif_handle spdif_handle_t; + +/*! @brief SPDIF transfer callback prototype */ +typedef void (*spdif_transfer_callback_t)(SPDIF_Type *base, spdif_handle_t *handle, status_t status, void *userData); + +/*! @brief SPDIF handle structure */ +struct _spdif_handle +{ + uint32_t state; /*!< Transfer status */ + spdif_transfer_callback_t callback; /*!< Callback function called at transfer event*/ + void *userData; /*!< Callback parameter passed to callback function*/ + spdif_transfer_t spdifQueue[SPDIF_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */ + size_t transferSize[SPDIF_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ + uint8_t watermark; /*!< Watermark value */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the SPDIF peripheral. + * + * Ungates the SPDIF clock, resets the module, and configures SPDIF with a configuration structure. + * The configuration structure can be custom filled or set with default values by + * SPDIF_GetDefaultConfig(). + * + * @note This API should be called at the beginning of the application to use + * the SPDIF driver. Otherwise, accessing the SPDIF module can cause a hard fault + * because the clock is not enabled. + * + * @param base SPDIF base pointer + * @param config SPDIF configuration structure. + */ +void SPDIF_Init(SPDIF_Type *base, const spdif_config_t *config); + +/*! + * @brief Sets the SPDIF configuration structure to default values. + * + * This API initializes the configuration structure for use in SPDIF_Init. + * The initialized structure can remain unchanged in SPDIF_Init, or it can be modified + * before calling SPDIF_Init. + * This is an example. + @code + spdif_config_t config; + SPDIF_GetDefaultConfig(&config); + @endcode + * + * @param config pointer to master configuration structure + */ +void SPDIF_GetDefaultConfig(spdif_config_t *config); + +/*! + * @brief De-initializes the SPDIF peripheral. + * + * This API gates the SPDIF clock. The SPDIF module can't operate unless SPDIF_Init is called to enable the clock. + * + * @param base SPDIF base pointer + */ +void SPDIF_Deinit(SPDIF_Type *base); + +/*! + * @brief Resets the SPDIF Tx. + * + * This function makes Tx FIFO in reset mode. + * + * @param base SPDIF base pointer + */ +static inline void SPDIF_TxFIFOReset(SPDIF_Type *base) +{ + base->SCR |= SPDIF_SCR_RXFIFO_RST_MASK; +} + +/*! + * @brief Resets the SPDIF Rx. + * + * This function enables the software reset and FIFO reset of SPDIF Rx. After reset, clear the reset bit. + * + * @param base SPDIF base pointer + */ +static inline void SPDIF_RxFIFOReset(SPDIF_Type *base) +{ + base->SCR |= SPDIF_SCR_RXFIFO_RST_MASK; +} + +/*! + * @brief Enables/disables the SPDIF Tx. + * + * @param base SPDIF base pointer + * @param enable True means enable SPDIF Tx, false means disable. + */ +void SPDIF_TxEnable(SPDIF_Type *base, bool enable); + +/*! + * @brief Enables/disables the SPDIF Rx. + * + * @param base SPDIF base pointer + * @param enable True means enable SPDIF Rx, false means disable. + */ +static inline void SPDIF_RxEnable(SPDIF_Type *base, bool enable) +{ + if (enable) + { + /* Open Rx FIFO */ + base->SCR &= ~(SPDIF_SCR_RXFIFO_CTRL_MASK | SPDIF_SCR_RXFIFO_OFF_ON_MASK); + } + else + { + base->SCR |= SPDIF_SCR_RXFIFO_OFF_ON_MASK; + } +} + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the SPDIF status flag state. + * + * @param base SPDIF base pointer + * @return SPDIF status flag value. Use the _spdif_interrupt_enable_t to get the status value needed. + */ +static inline uint32_t SPDIF_GetStatusFlag(SPDIF_Type *base) +{ + return base->SIS; +} + +/*! + * @brief Clears the SPDIF status flag state. + * + * @param base SPDIF base pointer + * @param mask State mask. It can be a combination of the _spdif_interrupt_enable_t member. Notice these members + * cannot be included, as these flags cannot be cleared by writing 1 to these bits: + * @arg kSPDIF_UChannelReceiveRegisterFull + * @arg kSPDIF_QChannelReceiveRegisterFull + * @arg kSPDIF_TxFIFOEmpty + * @arg kSPDIF_RxFIFOFull + */ +static inline void SPDIF_ClearStatusFlags(SPDIF_Type *base, uint32_t mask) +{ + base->SIC = mask; +} + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the SPDIF Tx interrupt requests. + * + * @param base SPDIF base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSPDIF_WordStartInterruptEnable + * @arg kSPDIF_SyncErrorInterruptEnable + * @arg kSPDIF_FIFOWarningInterruptEnable + * @arg kSPDIF_FIFORequestInterruptEnable + * @arg kSPDIF_FIFOErrorInterruptEnable + */ +static inline void SPDIF_EnableInterrupts(SPDIF_Type *base, uint32_t mask) +{ + base->SIE |= mask; +} + +/*! + * @brief Disables the SPDIF Tx interrupt requests. + * + * @param base SPDIF base pointer + * @param mask interrupt source + * The parameter can be a combination of the following sources if defined. + * @arg kSPDIF_WordStartInterruptEnable + * @arg kSPDIF_SyncErrorInterruptEnable + * @arg kSPDIF_FIFOWarningInterruptEnable + * @arg kSPDIF_FIFORequestInterruptEnable + * @arg kSPDIF_FIFOErrorInterruptEnable + */ +static inline void SPDIF_DisableInterrupts(SPDIF_Type *base, uint32_t mask) +{ + base->SIE &= ~mask; +} + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables the SPDIF DMA requests. + * @param base SPDIF base pointer + * @param mask SPDIF DMA enable mask, The parameter can be a combination of the following sources if defined + * @arg kSPDIF_RxDMAEnable + * @arg kSPDIF_TxDMAEnable + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void SPDIF_EnableDMA(SPDIF_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->SCR |= mask; + } + else + { + base->SCR &= ~mask; + } +} + +/*! + * @brief Gets the SPDIF Tx left data register address. + * + * This API is used to provide a transfer address for the SPDIF DMA transfer configuration. + * + * @param base SPDIF base pointer. + * @return data register address. + */ +static inline uint32_t SPDIF_TxGetLeftDataRegisterAddress(SPDIF_Type *base) +{ + return (uint32_t)(&(base->STL)); +} + +/*! + * @brief Gets the SPDIF Tx right data register address. + * + * This API is used to provide a transfer address for the SPDIF DMA transfer configuration. + * + * @param base SPDIF base pointer. + * @return data register address. + */ +static inline uint32_t SPDIF_TxGetRightDataRegisterAddress(SPDIF_Type *base) +{ + return (uint32_t)(&(base->STR)); +} + +/*! + * @brief Gets the SPDIF Rx left data register address. + * + * This API is used to provide a transfer address for the SPDIF DMA transfer configuration. + * + * @param base SPDIF base pointer. + * @return data register address. + */ +static inline uint32_t SPDIF_RxGetLeftDataRegisterAddress(SPDIF_Type *base) +{ + return (uint32_t)(&(base->SRL)); +} + +/*! + * @brief Gets the SPDIF Rx right data register address. + * + * This API is used to provide a transfer address for the SPDIF DMA transfer configuration. + * + * @param base SPDIF base pointer. + * @return data register address. + */ +static inline uint32_t SPDIF_RxGetRightDataRegisterAddress(SPDIF_Type *base) +{ + return (uint32_t)(&(base->SRR)); +} + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Configures the SPDIF Tx sample rate. + * + * The audio format can be changed at run-time. This function configures the sample rate. + * + * @param base SPDIF base pointer. + * @param sampleRate_Hz SPDIF sample rate frequency in Hz. + * @param sourceClockFreq_Hz SPDIF tx clock source frequency in Hz. + */ +void SPDIF_TxSetSampleRate(SPDIF_Type *base, uint32_t sampleRate_Hz, uint32_t sourceClockFreq_Hz); + +/*! + * @brief Configures the SPDIF Rx audio format. + * + * The audio format can be changed at run-time. This function configures the sample rate and audio data + * format to be transferred. + * + * @param base SPDIF base pointer. + * @param clockSourceFreq_Hz SPDIF system clock frequency in hz. + */ +uint32_t SPDIF_GetRxSampleRate(SPDIF_Type *base, uint32_t clockSourceFreq_Hz); + +/*! + * @brief Sends data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SPDIF base pointer. + * @param buffer Pointer to the data to be written. + * @param size Bytes to be written. + */ +void SPDIF_WriteBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size); + +/*! + * @brief Writes data into SPDIF FIFO. + * + * @param base SPDIF base pointer. + * @param data Data needs to be written. + */ +static inline void SPDIF_WriteLeftData(SPDIF_Type *base, uint32_t data) +{ + base->STL = data; +} + +/*! + * @brief Writes data into SPDIF FIFO. + * + * @param base SPDIF base pointer. + * @param data Data needs to be written. + */ +static inline void SPDIF_WriteRightData(SPDIF_Type *base, uint32_t data) +{ + base->STR = data; +} + +/*! + * @brief Writes data into SPDIF FIFO. + * + * @param base SPDIF base pointer. + * @param data Data needs to be written. + */ +static inline void SPDIF_WriteChannelStatusHigh(SPDIF_Type *base, uint32_t data) +{ + base->STCSCH = data; +} + +/*! + * @brief Writes data into SPDIF FIFO. + * + * @param base SPDIF base pointer. + * @param data Data needs to be written. + */ +static inline void SPDIF_WriteChannelStatusLow(SPDIF_Type *base, uint32_t data) +{ + base->STCSCL = data; +} + +/*! + * @brief Receives data using a blocking method. + * + * @note This function blocks by polling until data is ready to be sent. + * + * @param base SPDIF base pointer. + * @param buffer Pointer to the data to be read. + * @param size Bytes to be read. + */ +void SPDIF_ReadBlocking(SPDIF_Type *base, uint8_t *buffer, uint32_t size); + +/*! + * @brief Reads data from the SPDIF FIFO. + * + * @param base SPDIF base pointer. + * @return Data in SPDIF FIFO. + */ +static inline uint32_t SPDIF_ReadLeftData(SPDIF_Type *base) +{ + return base->SRL; +} + +/*! + * @brief Reads data from the SPDIF FIFO. + *. + + * @param base SPDIF base pointer. + * @return Data in SPDIF FIFO. + */ +static inline uint32_t SPDIF_ReadRightData(SPDIF_Type *base) +{ + return base->SRR; +} + +/*! + * @brief Reads data from the SPDIF FIFO. + * + * @param base SPDIF base pointer. + * @return Data in SPDIF FIFO. + */ +static inline uint32_t SPDIF_ReadChannelStatusHigh(SPDIF_Type *base) +{ + return base->SRCSH; +} + +/*! + * @brief Reads data from the SPDIF FIFO. + *. + + * @param base SPDIF base pointer. + * @return Data in SPDIF FIFO. + */ +static inline uint32_t SPDIF_ReadChannelStatusLow(SPDIF_Type *base) +{ + return base->SRCSL; +} + +/*! + * @brief Reads data from the SPDIF FIFO. + * + * @param base SPDIF base pointer. + * @return Data in SPDIF FIFO. + */ +static inline uint32_t SPDIF_ReadQChannel(SPDIF_Type *base) +{ + return base->SRQ; +} + +/*! + * @brief Reads data from the SPDIF FIFO. + *. + + * @param base SPDIF base pointer. + * @return Data in SPDIF FIFO. + */ +static inline uint32_t SPDIF_ReadUChannel(SPDIF_Type *base) +{ + return base->SRU; +} + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the SPDIF Tx handle. + * + * This function initializes the Tx handle for the SPDIF Tx transactional APIs. Call + * this function once to get the handle initialized. + * + * @param base SPDIF base pointer + * @param handle SPDIF handle pointer. + * @param callback Pointer to the user callback function. + * @param userData User parameter passed to the callback function + */ +void SPDIF_TransferTxCreateHandle(SPDIF_Type *base, + spdif_handle_t *handle, + spdif_transfer_callback_t callback, + void *userData); + +/*! + * @brief Initializes the SPDIF Rx handle. + * + * This function initializes the Rx handle for the SPDIF Rx transactional APIs. Call + * this function once to get the handle initialized. + * + * @param base SPDIF base pointer. + * @param handle SPDIF handle pointer. + * @param callback Pointer to the user callback function. + * @param userData User parameter passed to the callback function. + */ +void SPDIF_TransferRxCreateHandle(SPDIF_Type *base, + spdif_handle_t *handle, + spdif_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs an interrupt non-blocking send transfer on SPDIF. + * + * @note This API returns immediately after the transfer initiates. + * Call the SPDIF_TxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SPDIF_Busy, the transfer + * is finished. + * + * @param base SPDIF base pointer. + * @param handle Pointer to the spdif_handle_t structure which stores the transfer state. + * @param xfer Pointer to the spdif_transfer_t structure. + * @retval kStatus_Success Successfully started the data receive. + * @retval kStatus_SPDIF_TxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SPDIF_TransferSendNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer); + +/*! + * @brief Performs an interrupt non-blocking receive transfer on SPDIF. + * + * @note This API returns immediately after the transfer initiates. + * Call the SPDIF_RxGetTransferStatusIRQ to poll the transfer status and check whether + * the transfer is finished. If the return status is not kStatus_SPDIF_Busy, the transfer + * is finished. + * + * @param base SPDIF base pointer + * @param handle Pointer to the spdif_handle_t structure which stores the transfer state. + * @param xfer Pointer to the spdif_transfer_t structure. + * @retval kStatus_Success Successfully started the data receive. + * @retval kStatus_SPDIF_RxBusy Previous receive still not finished. + * @retval kStatus_InvalidArgument The input parameter is invalid. + */ +status_t SPDIF_TransferReceiveNonBlocking(SPDIF_Type *base, spdif_handle_t *handle, spdif_transfer_t *xfer); + +/*! + * @brief Gets a set byte count. + * + * @param base SPDIF base pointer. + * @param handle Pointer to the spdif_handle_t structure which stores the transfer state. + * @param count Bytes count sent. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SPDIF_TransferGetSendCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count); + +/*! + * @brief Gets a received byte count. + * + * @param base SPDIF base pointer. + * @param handle Pointer to the spdif_handle_t structure which stores the transfer state. + * @param count Bytes count received. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t SPDIF_TransferGetReceiveCount(SPDIF_Type *base, spdif_handle_t *handle, size_t *count); + +/*! + * @brief Aborts the current send. + * + * @note This API can be called any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base SPDIF base pointer. + * @param handle Pointer to the spdif_handle_t structure which stores the transfer state. + */ +void SPDIF_TransferAbortSend(SPDIF_Type *base, spdif_handle_t *handle); + +/*! + * @brief Aborts the current IRQ receive. + * + * @note This API can be called when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base SPDIF base pointer + * @param handle Pointer to the spdif_handle_t structure which stores the transfer state. + */ +void SPDIF_TransferAbortReceive(SPDIF_Type *base, spdif_handle_t *handle); + +/*! + * @brief Tx interrupt handler. + * + * @param base SPDIF base pointer. + * @param handle Pointer to the spdif_handle_t structure. + */ +void SPDIF_TransferTxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle); + +/*! + * @brief Tx interrupt handler. + * + * @param base SPDIF base pointer. + * @param handle Pointer to the spdif_handle_t structure. + */ +void SPDIF_TransferRxHandleIRQ(SPDIF_Type *base, spdif_handle_t *handle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ + +/*! @} */ + +#endif /* _FSL_SPDIF_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_spdif_edma.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_spdif_edma.c new file mode 100644 index 0000000000..8504a25ec9 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_spdif_edma.c @@ -0,0 +1,578 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_spdif_edma.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.spdif_edma" +#endif + +/******************************************************************************* + * Definitations + ******************************************************************************/ +/* Used for 32byte aligned */ +#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)address + 32) & ~0x1FU) + +/*handle; + + /* If finished a block, call the callback function */ + memset(&spdifHandle->spdifQueue[spdifHandle->queueDriver], 0, sizeof(spdif_edma_transfer_t)); + spdifHandle->queueDriver = (spdifHandle->queueDriver + 1) % SPDIF_XFER_QUEUE_SIZE; + if (spdifHandle->callback) + { + (spdifHandle->callback)(privHandle->base, spdifHandle, kStatus_SPDIF_TxIdle, spdifHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (spdifHandle->spdifQueue[spdifHandle->queueDriver].rightData == NULL) + { + SPDIF_TransferAbortSendEDMA(privHandle->base, spdifHandle); + } +} + +static void SPDIF_RxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds) +{ + spdif_edma_private_handle_t *privHandle = (spdif_edma_private_handle_t *)userData; + spdif_edma_handle_t *spdifHandle = privHandle->handle; + + /* If finished a block, call the callback function */ + memset(&spdifHandle->spdifQueue[spdifHandle->queueDriver], 0, sizeof(spdif_edma_transfer_t)); + spdifHandle->queueDriver = (spdifHandle->queueDriver + 1) % SPDIF_XFER_QUEUE_SIZE; + if (spdifHandle->callback) + { + (spdifHandle->callback)(privHandle->base, spdifHandle, kStatus_SPDIF_RxIdle, spdifHandle->userData); + } + + /* If all data finished, just stop the transfer */ + if (spdifHandle->spdifQueue[spdifHandle->queueDriver].rightData == NULL) + { + SPDIF_TransferAbortReceiveEDMA(privHandle->base, spdifHandle); + } +} + +static status_t SPDIF_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config, uint32_t rightChannel) +{ + edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel]; + uint32_t primask; + uint32_t csr; + int8_t currentTcd; + int8_t previousTcd; + int8_t nextTcd; + + /* Check if tcd pool is full. */ + primask = DisableGlobalIRQ(); + if (handle->tcdUsed >= handle->tcdSize) + { + EnableGlobalIRQ(primask); + + return kStatus_EDMA_QueueFull; + } + currentTcd = handle->tail; + handle->tcdUsed++; + /* Calculate index of next TCD */ + nextTcd = currentTcd + 1U; + if (nextTcd == handle->tcdSize) + { + nextTcd = 0U; + } + /* Advance queue tail index */ + handle->tail = nextTcd; + EnableGlobalIRQ(primask); + /* Calculate index of previous TCD */ + previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U; + /* Configure current TCD block. */ + EDMA_TcdReset(&handle->tcdPool[currentTcd]); + EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL); + /* Set channel link */ + EDMA_TcdSetChannelLink(&handle->tcdPool[currentTcd], kEDMA_MinorLink, rightChannel); + EDMA_TcdSetChannelLink(&handle->tcdPool[currentTcd], kEDMA_MajorLink, rightChannel); + /* Enable major interrupt */ + handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK; + /* Link current TCD with next TCD for identification of current TCD */ + handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd]; + /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ + if (currentTcd != previousTcd) + { + /* Enable scatter/gather feature in the previous TCD block. */ + csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + handle->tcdPool[previousTcd].CSR = csr; + /* + Check if the TCD block in the registers is the previous one (points to current TCD block). It + is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to + link the TCD register in case link the current TCD with the dead chain when TCD loading occurs + before link the previous TCD block. + */ + if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd]) + { + /* Enable scatter/gather also in the TCD registers. */ + csr = (tcdRegs->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK; + /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ + tcdRegs->CSR = csr; + /* + It is very important to check the ESG bit! + Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can + be used to check if the dynamic TCD link operation is successful. If ESG bit is not set + and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and + the current TCD block has been loaded into TCD registers), it means transfer finished + and TCD link operation fail, so must install TCD content into TCD registers and enable + transfer again. And if ESG is set, it means transfer has notfinished, so TCD dynamic + link succeed. + */ + if (tcdRegs->CSR & DMA_CSR_ESG_MASK) + { + return kStatus_Success; + } + /* + Check whether the current TCD block is already loaded in the TCD registers. It is another + condition when ESG bit is not set: it means the dynamic TCD link succeed and the current + TCD block has been loaded into TCD registers. + */ + if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd]) + { + return kStatus_Success; + } + /* + If go to this, means the previous transfer finished, and the DONE bit is set. + So shall configure TCD registers. + */ + } + else if (tcdRegs->DLAST_SGA != 0) + { + /* The current TCD block has been linked successfully. */ + return kStatus_Success; + } + else + { + /* + DLAST_SGA is 0 and it means the first submit transfer, so shall configure + TCD registers. + */ + } + } + /* There is no live chain, TCD block need to be installed in TCD registers. */ + EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); + /* Enable channel request again. */ + if (handle->flags & 0x80) + { + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + + return kStatus_Success; +} + +/*! + * brief Initializes the SPDIF eDMA handle. + * + * This function initializes the SPDIF master DMA handle, which can be used for other SPDIF master transactional APIs. + * Usually, for a specified SPDIF instance, call this API once to get the initialized handle. + * + * param base SPDIF base pointer. + * param handle SPDIF eDMA handle pointer. + * param base SPDIF peripheral base address. + * param callback Pointer to user callback function. + * param userData User parameter passed to the callback function. + * param dmaLeftHandle eDMA handle pointer for left channel, this handle shall be static allocated by users. + * param dmaRightHandle eDMA handle pointer for right channel, this handle shall be static allocated by users. + */ +void SPDIF_TransferTxCreateHandleEDMA(SPDIF_Type *base, + spdif_edma_handle_t *handle, + spdif_edma_callback_t callback, + void *userData, + edma_handle_t *dmaLeftHandle, + edma_handle_t *dmaRightHandle) +{ + assert(handle && dmaLeftHandle && dmaRightHandle); + + uint32_t instance = SPDIF_GetInstance(base); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + /* Set spdif base to handle */ + handle->dmaLeftHandle = dmaLeftHandle; + handle->dmaRightHandle = dmaRightHandle; + handle->callback = callback; + handle->userData = userData; + handle->count = + s_spdif_tx_watermark[(base->SCR & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) >> SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT]; + + /* Set SPDIF state to idle */ + handle->state = kSPDIF_Idle; + + s_edmaPrivateHandle[instance][0].base = base; + s_edmaPrivateHandle[instance][0].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(dmaLeftHandle, STCD_ADDR(handle->leftTcd), SPDIF_XFER_QUEUE_SIZE); + EDMA_InstallTCDMemory(dmaRightHandle, STCD_ADDR(handle->rightTcd), SPDIF_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel, only right channel finished, a transfer finished */ + EDMA_SetCallback(dmaRightHandle, SPDIF_TxEDMACallback, &s_edmaPrivateHandle[instance][0]); +} + +/*! + * brief Initializes the SPDIF Rx eDMA handle. + * + * This function initializes the SPDIF slave DMA handle, which can be used for other SPDIF master transactional APIs. + * Usually, for a specified SPDIF instance, call this API once to get the initialized handle. + * + * param base SPDIF base pointer. + * param handle SPDIF eDMA handle pointer. + * param base SPDIF peripheral base address. + * param callback Pointer to user callback function. + * param userData User parameter passed to the callback function. + * param dmaLeftHandle eDMA handle pointer for left channel, this handle shall be static allocated by users. + * param dmaRightHandle eDMA handle pointer for right channel, this handle shall be static allocated by users. + */ +void SPDIF_TransferRxCreateHandleEDMA(SPDIF_Type *base, + spdif_edma_handle_t *handle, + spdif_edma_callback_t callback, + void *userData, + edma_handle_t *dmaLeftHandle, + edma_handle_t *dmaRightHandle) +{ + assert(handle && dmaLeftHandle && dmaRightHandle); + + uint32_t instance = SPDIF_GetInstance(base); + + /* Zero the handle */ + memset(handle, 0, sizeof(*handle)); + + /* Set spdif base to handle */ + handle->dmaLeftHandle = dmaLeftHandle; + handle->dmaRightHandle = dmaRightHandle; + handle->callback = callback; + handle->userData = userData; + handle->count = s_spdif_rx_watermark[(base->SCR & SPDIF_SCR_RXFIFOFULL_SEL_MASK) >> SPDIF_SCR_RXFIFOFULL_SEL_SHIFT]; + + /* Set SPDIF state to idle */ + handle->state = kSPDIF_Idle; + + s_edmaPrivateHandle[instance][1].base = base; + s_edmaPrivateHandle[instance][1].handle = handle; + + /* Need to use scatter gather */ + EDMA_InstallTCDMemory(dmaLeftHandle, STCD_ADDR(handle->leftTcd), SPDIF_XFER_QUEUE_SIZE); + EDMA_InstallTCDMemory(dmaRightHandle, STCD_ADDR(handle->rightTcd), SPDIF_XFER_QUEUE_SIZE); + + /* Install callback for Tx dma channel */ + EDMA_SetCallback(dmaRightHandle, SPDIF_RxEDMACallback, &s_edmaPrivateHandle[instance][1]); +} + +/*! + * brief Performs a non-blocking SPDIF transfer using DMA. + * + * note This interface returns immediately after the transfer initiates. Call + * SPDIF_GetTransferStatus to poll the transfer status and check whether the SPDIF transfer is finished. + * + * param base SPDIF base pointer. + * param handle SPDIF eDMA handle pointer. + * param xfer Pointer to the DMA transfer structure. + * retval kStatus_Success Start a SPDIF eDMA send successfully. + * retval kStatus_InvalidArgument The input argument is invalid. + * retval kStatus_TxBusy SPDIF is busy sending data. + */ +status_t SPDIF_TransferSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer) +{ + assert(handle && xfer); + + edma_transfer_config_t config = {0}; + uint32_t destAddr = SPDIF_TxGetLeftDataRegisterAddress(base); + + /* Check if input parameter invalid */ + if ((xfer->leftData == NULL) || (xfer->dataSize == 0U) || (xfer->rightData == NULL)) + { + return kStatus_InvalidArgument; + } + + if ((handle->spdifQueue[handle->queueUser].leftData) || (handle->spdifQueue[handle->queueUser].rightData)) + { + return kStatus_SPDIF_QueueFull; + } + + /* Change the state of handle */ + handle->state = kSPDIF_Busy; + + /* Update the queue state */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->spdifQueue[handle->queueUser].leftData = xfer->leftData; + handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->spdifQueue[handle->queueUser].rightData = xfer->rightData; + handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; + + /* Store the initially configured eDMA minor byte transfer count into the SPDIF handle */ + handle->nbytes = handle->count * 8U; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, xfer->leftData, 4U, (void *)destAddr, 4U, handle->count * 4U, xfer->dataSize, + kEDMA_MemoryToPeripheral); + SPDIF_SubmitTransfer(handle->dmaLeftHandle, &config, handle->dmaRightHandle->channel); + + /* Prepare right channel */ + destAddr = SPDIF_TxGetRightDataRegisterAddress(base); + EDMA_PrepareTransfer(&config, xfer->rightData, 4U, (void *)destAddr, 4U, handle->count * 4U, xfer->dataSize, + kEDMA_MemoryToPeripheral); + EDMA_SubmitTransfer(handle->dmaRightHandle, &config); + + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaLeftHandle); + EDMA_StartTransfer(handle->dmaRightHandle); + + /* Enable DMA enable bit */ + SPDIF_EnableDMA(base, kSPDIF_TxDMAEnable, true); + + /* Enable SPDIF Tx clock */ + SPDIF_TxEnable(base, true); + + return kStatus_Success; +} + +/*! + * brief Performs a non-blocking SPDIF receive using eDMA. + * + * note This interface returns immediately after the transfer initiates. Call + * the SPDIF_GetReceiveRemainingBytes to poll the transfer status and check whether the SPDIF transfer is finished. + * + * param base SPDIF base pointer + * param handle SPDIF eDMA handle pointer. + * param xfer Pointer to DMA transfer structure. + * retval kStatus_Success Start a SPDIF eDMA receive successfully. + * retval kStatus_InvalidArgument The input argument is invalid. + * retval kStatus_RxBusy SPDIF is busy receiving data. + */ +status_t SPDIF_TransferReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer) +{ + assert(handle && xfer); + + edma_transfer_config_t config = {0}; + uint32_t srcAddr = SPDIF_RxGetLeftDataRegisterAddress(base); + + /* Check if input parameter invalid */ + if ((xfer->leftData == NULL) || (xfer->dataSize == 0U) || (xfer->rightData == NULL)) + { + return kStatus_InvalidArgument; + } + + if ((handle->spdifQueue[handle->queueUser].leftData) || (handle->spdifQueue[handle->queueUser].rightData)) + { + return kStatus_SPDIF_QueueFull; + } + + /* Change the state of handle */ + handle->state = kSPDIF_Busy; + + /* Update the queue state */ + handle->transferSize[handle->queueUser] = xfer->dataSize; + handle->spdifQueue[handle->queueUser].leftData = xfer->leftData; + handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize; + handle->spdifQueue[handle->queueUser].rightData = xfer->rightData; + handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE; + + /* Store the initially configured eDMA minor byte transfer count into the SPDIF handle */ + handle->nbytes = handle->count * 8U; + + /* Prepare edma configure */ + EDMA_PrepareTransfer(&config, (void *)srcAddr, 4U, xfer->leftData, 4U, handle->count * 4U, xfer->dataSize, + kEDMA_PeripheralToMemory); + /* Use specific submit function to enable channel link */ + SPDIF_SubmitTransfer(handle->dmaLeftHandle, &config, handle->dmaRightHandle->channel); + + /* Prepare right channel */ + srcAddr = SPDIF_RxGetRightDataRegisterAddress(base); + EDMA_PrepareTransfer(&config, (void *)srcAddr, 4U, xfer->rightData, 4U, handle->count * 4U, xfer->dataSize, + kEDMA_PeripheralToMemory); + EDMA_SubmitTransfer(handle->dmaRightHandle, &config); + + /* Start DMA transfer */ + EDMA_StartTransfer(handle->dmaLeftHandle); + EDMA_StartTransfer(handle->dmaRightHandle); + + /* Enable DMA enable bit */ + SPDIF_EnableDMA(base, kSPDIF_RxDMAEnable, true); + + /* Enable SPDIF Rx clock */ + SPDIF_RxEnable(base, true); + + return kStatus_Success; +} + +/*! + * brief Aborts a SPDIF transfer using eDMA. + * + * param base SPDIF base pointer. + * param handle SPDIF eDMA handle pointer. + */ +void SPDIF_TransferAbortSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaLeftHandle); + EDMA_AbortTransfer(handle->dmaRightHandle); + + /* Disable DMA enable bit */ + SPDIF_EnableDMA(base, kSPDIF_TxDMAEnable, false); + + /* Set internal state */ + memset(handle->spdifQueue, 0U, sizeof(handle->spdifQueue)); + memset(handle->transferSize, 0U, sizeof(handle->transferSize)); + handle->queueUser = 0U; + handle->queueDriver = 0U; + + /* Set the handle state */ + handle->state = kSPDIF_Idle; +} + +/*! + * brief Aborts a SPDIF receive using eDMA. + * + * param base SPDIF base pointer + * param handle SPDIF eDMA handle pointer. + */ +void SPDIF_TransferAbortReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle) +{ + assert(handle); + + /* Disable dma */ + EDMA_AbortTransfer(handle->dmaLeftHandle); + EDMA_AbortTransfer(handle->dmaRightHandle); + + /* Disable DMA enable bit */ + SPDIF_EnableDMA(base, kSPDIF_RxDMAEnable, false); + + /* Set internal state */ + memset(handle->spdifQueue, 0U, sizeof(handle->spdifQueue)); + memset(handle->transferSize, 0U, sizeof(handle->transferSize)); + handle->queueUser = 0U; + handle->queueDriver = 0U; + + /* Set the handle state */ + handle->state = kSPDIF_Idle; +} + +/*! + * brief Gets byte count sent by SPDIF. + * + * param base SPDIF base pointer. + * param handle SPDIF eDMA handle pointer. + * param count Bytes count sent by SPDIF. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SPDIF_TransferGetSendCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSPDIF_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->dmaRightHandle->base, handle->dmaRightHandle->channel)); + } + + return status; +} + +/*! + * brief Gets byte count received by SPDIF. + * + * param base SPDIF base pointer + * param handle SPDIF eDMA handle pointer. + * param count Bytes count received by SPDIF. + * retval kStatus_Success Succeed get the transfer count. + * retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SPDIF_TransferGetReceiveCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count) +{ + assert(handle); + + status_t status = kStatus_Success; + + if (handle->state != kSPDIF_Busy) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = (handle->transferSize[handle->queueDriver] - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->dmaRightHandle->base, handle->dmaRightHandle->channel)); + } + + return status; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_spdif_edma.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_spdif_edma.h new file mode 100644 index 0000000000..b39c202671 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_spdif_edma.h @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SPDIF_EDMA_H_ +#define _FSL_SPDIF_EDMA_H_ + +#include "fsl_spdif.h" +#include "fsl_edma.h" + +/*! + * @addtogroup spdif_edma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_SPDIF_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ +/*@}*/ + +typedef struct _spdif_edma_handle spdif_edma_handle_t; + +/*! @brief SPDIF eDMA transfer callback function for finish and error */ +typedef void (*spdif_edma_callback_t)(SPDIF_Type *base, spdif_edma_handle_t *handle, status_t status, void *userData); + +/*! @brief SPDIF transfer structure */ +typedef struct _spdif_edma_transfer +{ + uint8_t *leftData; /*!< Data start address to transfer. */ + uint8_t *rightData; /*!< Data start address to transfer. */ + size_t dataSize; /*!< Transfer size. */ +} spdif_edma_transfer_t; + +/*! @brief SPDIF DMA transfer handle, users should not touch the content of the handle.*/ +struct _spdif_edma_handle +{ + edma_handle_t *dmaLeftHandle; /*!< DMA handler for SPDIF left channel */ + edma_handle_t *dmaRightHandle; /*!< DMA handler for SPDIF right channel */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + uint8_t count; /*!< The transfer data count in a DMA request */ + uint32_t state; /*!< Internal state for SPDIF eDMA transfer */ + spdif_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurs */ + void *userData; /*!< User callback parameter */ + edma_tcd_t leftTcd[SPDIF_XFER_QUEUE_SIZE + 1U]; /*!< TCD pool for eDMA transfer. */ + edma_tcd_t rightTcd[SPDIF_XFER_QUEUE_SIZE + 1U]; /*!< TCD pool for eDMA transfer. */ + spdif_edma_transfer_t spdifQueue[SPDIF_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ + size_t transferSize[SPDIF_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer, left and right are the same, so use + one */ + volatile uint8_t queueUser; /*!< Index for user to queue transfer. */ + volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA Transactional + * @{ + */ + +/*! + * @brief Initializes the SPDIF eDMA handle. + * + * This function initializes the SPDIF master DMA handle, which can be used for other SPDIF master transactional APIs. + * Usually, for a specified SPDIF instance, call this API once to get the initialized handle. + * + * @param base SPDIF base pointer. + * @param handle SPDIF eDMA handle pointer. + * @param base SPDIF peripheral base address. + * @param callback Pointer to user callback function. + * @param userData User parameter passed to the callback function. + * @param dmaLeftHandle eDMA handle pointer for left channel, this handle shall be static allocated by users. + * @param dmaRightHandle eDMA handle pointer for right channel, this handle shall be static allocated by users. + */ +void SPDIF_TransferTxCreateHandleEDMA(SPDIF_Type *base, + spdif_edma_handle_t *handle, + spdif_edma_callback_t callback, + void *userData, + edma_handle_t *dmaLeftHandle, + edma_handle_t *dmaRightHandle); + +/*! + * @brief Initializes the SPDIF Rx eDMA handle. + * + * This function initializes the SPDIF slave DMA handle, which can be used for other SPDIF master transactional APIs. + * Usually, for a specified SPDIF instance, call this API once to get the initialized handle. + * + * @param base SPDIF base pointer. + * @param handle SPDIF eDMA handle pointer. + * @param base SPDIF peripheral base address. + * @param callback Pointer to user callback function. + * @param userData User parameter passed to the callback function. + * @param dmaLeftHandle eDMA handle pointer for left channel, this handle shall be static allocated by users. + * @param dmaRightHandle eDMA handle pointer for right channel, this handle shall be static allocated by users. + */ +void SPDIF_TransferRxCreateHandleEDMA(SPDIF_Type *base, + spdif_edma_handle_t *handle, + spdif_edma_callback_t callback, + void *userData, + edma_handle_t *dmaLeftHandle, + edma_handle_t *dmaRightHandle); + +/*! + * @brief Performs a non-blocking SPDIF transfer using DMA. + * + * @note This interface returns immediately after the transfer initiates. Call + * SPDIF_GetTransferStatus to poll the transfer status and check whether the SPDIF transfer is finished. + * + * @param base SPDIF base pointer. + * @param handle SPDIF eDMA handle pointer. + * @param xfer Pointer to the DMA transfer structure. + * @retval kStatus_Success Start a SPDIF eDMA send successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + * @retval kStatus_TxBusy SPDIF is busy sending data. + */ +status_t SPDIF_TransferSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer); + +/*! + * @brief Performs a non-blocking SPDIF receive using eDMA. + * + * @note This interface returns immediately after the transfer initiates. Call + * the SPDIF_GetReceiveRemainingBytes to poll the transfer status and check whether the SPDIF transfer is finished. + * + * @param base SPDIF base pointer + * @param handle SPDIF eDMA handle pointer. + * @param xfer Pointer to DMA transfer structure. + * @retval kStatus_Success Start a SPDIF eDMA receive successfully. + * @retval kStatus_InvalidArgument The input argument is invalid. + * @retval kStatus_RxBusy SPDIF is busy receiving data. + */ +status_t SPDIF_TransferReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer); + +/*! + * @brief Aborts a SPDIF transfer using eDMA. + * + * @param base SPDIF base pointer. + * @param handle SPDIF eDMA handle pointer. + */ +void SPDIF_TransferAbortSendEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle); + +/*! + * @brief Aborts a SPDIF receive using eDMA. + * + * @param base SPDIF base pointer + * @param handle SPDIF eDMA handle pointer. + */ +void SPDIF_TransferAbortReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle); + +/*! + * @brief Gets byte count sent by SPDIF. + * + * @param base SPDIF base pointer. + * @param handle SPDIF eDMA handle pointer. + * @param count Bytes count sent by SPDIF. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SPDIF_TransferGetSendCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count); + +/*! + * @brief Gets byte count received by SPDIF. + * + * @param base SPDIF base pointer + * @param handle SPDIF eDMA handle pointer. + * @param count Bytes count received by SPDIF. + * @retval kStatus_Success Succeed get the transfer count. + * @retval kStatus_NoTransferInProgress There is no non-blocking transaction in progress. + */ +status_t SPDIF_TransferGetReceiveCountEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, size_t *count); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_src.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_src.c new file mode 100644 index 0000000000..10af22893a --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_src.c @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_src.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.src" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Clear the status flags of SRC. + * + * param base SRC peripheral base address. + * param Mask value of status flags to be cleared, see to #_src_reset_status_flags. + */ +void SRC_ClearResetStatusFlags(SRC_Type *base, uint32_t flags) +{ + uint32_t tmp32 = base->SRSR; + + if (0U != (SRC_SRSR_TSR_MASK & flags)) + { + tmp32 &= ~SRC_SRSR_TSR_MASK; /* Write 0 to clear. */ + } + + if (0U != (SRC_SRSR_W1C_BITS_MASK & flags)) + { + tmp32 |= (SRC_SRSR_W1C_BITS_MASK & flags); /* Write 1 to clear. */ + } + + base->SRSR = tmp32; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_src.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_src.h new file mode 100644 index 0000000000..5a8830f69d --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_src.h @@ -0,0 +1,602 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SRC_H_ +#define _FSL_SRC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup src + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SRC driver version 2.0.1. */ +#define FSL_SRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @brief SRC reset status flags. + */ +enum _src_reset_status_flags +{ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT) && FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT) + kSRC_ResetOutputEnableFlag = SRC_SRSR_RESET_OUT_MASK, /*!< This bit indicates if RESET status is + driven out on PTE0 pin. */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_RESET_OUT */ +#if !(defined(FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) && FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) + kSRC_WarmBootIndicationFlag = SRC_SRSR_WBI_MASK, /*!< WARM boot indication shows that WARM boot + was initiated by software. */ +#endif /* FSL_FEATURE_SRC_HAS_NO_SRSR_WBI */ + kSRC_TemperatureSensorResetFlag = SRC_SRSR_TSR_MASK, /*!< Indicates whether the reset was the + result of software reset from on-chip + Temperature Sensor. Temperature Sensor + Interrupt needs to be served before this + bit can be cleaned.*/ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B) && FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B) + kSRC_Wdog3ResetFlag = SRC_SRSR_WDOG3_RST_B_MASK, /*!< IC Watchdog3 Time-out reset. Indicates + whether the reset was the result of the + watchdog3 time-out event. */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_WDOG3_RST_B */ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_SW) && FSL_FEATURE_SRC_HAS_SRSR_SW) + kSRC_SoftwareResetFlag = SRC_SRSR_SW_MASK, /*!< Indicates a reset has been caused by software + setting of SYSRESETREQ bit in Application + Interrupt and Reset Control Register in the + ARM core. */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_SW */ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST) && FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST) + kSRC_JTAGSystemResetFlag = + SRC_SRSR_JTAG_SW_RST_MASK, /*!< Indicates whether the reset was the result of software reset form JTAG */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_JTAG_SW_RST */ + kSRC_JTAGSoftwareResetFlag = SRC_SRSR_SJC_MASK, /*!< Indicates whether the reset was the result of + setting SJC_GPCCR bit 31. */ + kSRC_JTAGGeneratedResetFlag = SRC_SRSR_JTAG_MASK, /*!< Indicates a reset has been caused by JTAG + selection of certain IR codes: EXTEST or + HIGHZ. */ + kSRC_WatchdogResetFlag = SRC_SRSR_WDOG_MASK, /*!< Indicates a reset has been caused by the + watchdog timer timing out. This reset source + can be blocked by disabling the watchdog. */ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B) + kSRC_IppUserResetFlag = SRC_SRSR_IPP_USER_RESET_B_MASK, /*!< Indicates whether the reset was the + result of the ipp_user_reset_b + qualified reset. */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_IPP_USER_RESET_B */ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_SNVS) && FSL_FEATURE_SRC_HAS_SRSR_SNVS) + kSRC_SNVSFailResetFlag = SRC_SRSR_SNVS_MASK, /*!< SNVS hardware failure will always cause a cold + reset. This flag indicates whether the reset + is a result of SNVS hardware failure. */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_SNVS */ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B) + kSRC_CsuResetFlag = SRC_SRSR_CSU_RESET_B_MASK, /*!< Indicates whether the reset was the result + of the csu_reset_b input. */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_CSU_RESET_B */ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP) && FSL_FEATURE_SRC_HAS_SRSR_LOCKUP) + kSRC_CoreLockupResetFlag = SRC_SRSR_LOCKUP_MASK, /*!< Indicates a reset has been caused by the + ARM core indication of a LOCKUP event. */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_LOCKUP */ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_POR) && FSL_FEATURE_SRC_HAS_SRSR_POR) + kSRC_PowerOnResetFlag = SRC_SRSR_POR_MASK, /*!< Indicates a reset has been caused by the + power-on detection logic. */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_POR */ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ) && FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ) + kSRC_LockupSysResetFlag = + SRC_SRSR_LOCKUP_SYSRESETREQ_MASK, /*!< Indicates a reset has been caused by CPU lockup or software + setting of SYSRESETREQ bit in Application Interrupt and + Reset Control Register of the ARM core. */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_LOCKUP_SYSRESETREQ */ +#if (defined(FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) && FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B) + kSRC_IppResetPinFlag = SRC_SRSR_IPP_RESET_B_MASK, /*!< Indicates whether reset was the result of + ipp_reset_b pin (Power-up sequence). */ +#endif /* FSL_FEATURE_SRC_HAS_SRSR_IPP_RESET_B */ +}; + +#if (defined(FSL_FEATURE_SRC_HAS_SISR) && FSL_FEATURE_SRC_HAS_SISR) +/*! + * @brief SRC interrupt status flag. + */ +enum _src_status_flags +{ + kSRC_Core0WdogResetReqFlag = + SRC_SISR_CORE0_WDOG_RST_REQ_MASK, /*!< WDOG reset request from core0. Read-only status bit. */ +}; +#endif /* FSL_FEATURE_SRC_HAS_SISR */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH) && FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH) +/*! + * @brief Selection of SoC mix power reset stretch. + * + * This type defines the SoC mix (Audio, ENET, uSDHC, EIM, QSPI, OCRAM, MMDC, etc) power up reset + * stretch mix reset width with the optional count of cycles + */ +typedef enum _src_mix_reset_stretch_cycles +{ + kSRC_MixResetStretchCycleAlt0 = 0U, /*!< mix reset width is 1 x 88 ipg_cycle cycles. */ + kSRC_MixResetStretchCycleAlt1 = 1U, /*!< mix reset width is 2 x 88 ipg_cycle cycles. */ + kSRC_MixResetStretchCycleAlt2 = 2U, /*!< mix reset width is 3 x 88 ipg_cycle cycles. */ + kSRC_MixResetStretchCycleAlt3 = 3U, /*!< mix reset width is 4 x 88 ipg_cycle cycles. */ +} src_mix_reset_stretch_cycles_t; +#endif /* FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN) && FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN) +/*! + * @brief Selection of WDOG3 reset option. + */ +typedef enum _src_wdog3_reset_option +{ + kSRC_Wdog3ResetOptionAlt0 = 0U, /*!< Wdog3_rst_b asserts M4 reset (default). */ + kSRC_Wdog3ResetOptionAlt1 = 1U, /*!< Wdog3_rst_b asserts global reset. */ +} src_wdog3_reset_option_t; +#endif /* FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN */ + +/*! + * @brief Selection of WARM reset bypass count. + * + * This type defines the 32KHz clock cycles to count before bypassing the MMDC acknowledge for WARM + * reset. If the MMDC acknowledge is not asserted before this counter is elapsed, a COLD reset will + * be initiated. + */ +typedef enum _src_warm_reset_bypass_count +{ + kSRC_WarmResetWaitAlways = 0U, /*!< System will wait until MMDC acknowledge is asserted. */ + kSRC_WarmResetWaitClk16 = 1U, /*!< Wait 16 32KHz clock cycles before switching the reset. */ + kSRC_WarmResetWaitClk32 = 2U, /*!< Wait 32 32KHz clock cycles before switching the reset. */ + kSRC_WarmResetWaitClk64 = 3U, /*!< Wait 64 32KHz clock cycles before switching the reset. */ +} src_warm_reset_bypass_count_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST) && FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST) +/*! + * @brief Enable the WDOG3 reset. + * + * The WDOG3 reset is enabled by default. + * + * @param base SRC peripheral base address. + * @param enable Enable the reset or not. + */ +static inline void SRC_EnableWDOG3Reset(SRC_Type *base, bool enable) +{ + if (enable) + { + base->SCR = (base->SCR & ~SRC_SCR_MASK_WDOG3_RST_MASK) | SRC_SCR_MASK_WDOG3_RST(0xA); + } + else + { + base->SCR = (base->SCR & ~SRC_SCR_MASK_WDOG3_RST_MASK) | SRC_SCR_MASK_WDOG3_RST(0x5); + } +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_MASK_WDOG3_RST */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH) && FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH) +/*! + * @brief Set the mix power up reset stretch mix reset width. + * + * @param base SRC peripheral base address. + * @param option Setting option, see to #src_mix_reset_stretch_cycles_t. + */ +static inline void SRC_SetMixResetStretchCycles(SRC_Type *base, src_mix_reset_stretch_cycles_t option) +{ + base->SCR = (base->SCR & ~SRC_SCR_MIX_RST_STRCH_MASK) | SRC_SCR_MIX_RST_STRCH(option); +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_MIX_RST_STRCH */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG) && FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG) +/*! + * @brief Debug reset would be asserted after power gating event. + * + * @param base SRC peripheral base address. + * @param enable Enable the reset or not. + */ +static inline void SRC_EnableCoreDebugResetAfterPowerGate(SRC_Type *base, bool enable) +{ + if (enable) + { + base->SCR &= ~SRC_SCR_DBG_RST_MSK_PG_MASK; + } + else + { + base->SCR |= SRC_SCR_DBG_RST_MSK_PG_MASK; + } +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_DBG_RST_MSK_PG */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN) && FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN) +/*! + * @brief Set the Wdog3_rst_b option. + * + * @param base SRC peripheral base address. + * @param option Setting option, see to #src_wdog3_reset_option_t. + */ +static inline void SRC_SetWdog3ResetOption(SRC_Type *base, src_wdog3_reset_option_t option) +{ + base->SCR = (base->SCR & ~SRC_SCR_WDOG3_RST_OPTN_MASK) | SRC_SCR_WDOG3_RST_OPTN(option); +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_WDOG3_RST_OPTN */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST) && FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST) +/*! + * @brief Software reset for debug of arm platform only. + * + * @param base SRC peripheral base address. + */ +static inline void SRC_DoSoftwareResetARMCoreDebug(SRC_Type *base) +{ + base->SCR |= SRC_SCR_CORES_DBG_RST_MASK; +} + +/*! + * @brief Check if the software reset for debug of arm platform only is done. + * + * @param base SRC peripheral base address. + */ +static inline bool SRC_GetSoftwareResetARMCoreDebugDone(SRC_Type *base) +{ + return (0U == (base->SCR & SRC_SCR_CORES_DBG_RST_MASK)); +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_CORES_DBG_RST */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_MTSR) && FSL_FEATURE_SRC_HAS_SCR_MTSR) +/*! + * @brief Enable the temperature sensor reset. + * + * The temperature sersor reset is enabled by default. When the sensor reset happens, an flag bit + * would be asserted. This flag bit can be cleared only by the hardware reset. + * + * @param base SRC peripheral base address. + * @param enable Enable the reset or not. + */ +static inline void SRC_EnableTemperatureSensorReset(SRC_Type *base, bool enable) +{ + if (enable) /* Temperature sensor reset is not masked. (default) */ + { + base->SCR = (base->SCR & ~SRC_SCR_MTSR_MASK) | SRC_SCR_MTSR(0x2); + } + else /* The on-chip temperature sensor interrupt will not create a reset to the chip. */ + { + base->SCR = (base->SCR & ~SRC_SCR_MTSR_MASK) | SRC_SCR_MTSR(0x5); + } +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_MTSR */ + +#if (defined(FSL_FEATURE_SCR_HAS_SCR_CORE0_DBG_RST) && FSL_FEATURE_SCR_HAS_SCR_CORE0_DBG_RST) +/*! + * @brief Do assert the core0 debug reset. + * + * @param base SRC peripheral base address. + */ +static inline void SRC_DoAssertCore0DebugReset(SRC_Type *base) +{ + base->SCR |= SRC_SCR_CORE0_DBG_RST_MASK; +} + +/*! + * @brief Check if the core0 debug reset is done. + * + * @param base SRC peripheral base address. + */ +static inline bool SRC_GetAssertCore0DebugResetDone(SRC_Type *base) +{ + return (0U == (base->SCR & SRC_SCR_CORE0_DBG_RST_MASK)); +} +#endif /* FSL_FEATURE_SCR_HAS_SCR_CORE0_DBG_RST */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_CORE0_RST) && FSL_FEATURE_SRC_HAS_SCR_CORE0_RST) +/*! + * @brief Do software reset the ARM core0 only. + * + * @param base SRC peripheral base address. + */ +static inline void SRC_DoSoftwareResetARMCore0(SRC_Type *base) +{ + base->SCR |= SRC_SCR_CORE0_RST_MASK; +} + +/*! + * @brief Check if the software for ARM core0 is done. + * + * @param base SRC peripheral base address. + * @return If the reset is done. + */ +static inline bool SRC_GetSoftwareResetARMCore0Done(SRC_Type *base) +{ + return (0U == (base->SCR & SRC_SCR_CORE0_RST_MASK)); +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_CORE0_RST */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_SWRC) && FSL_FEATURE_SRC_HAS_SCR_SWRC) +/*! + * @brief Do software reset for ARM core. + * + * This function can be used to assert the ARM core reset. Once it is called, the reset process will + * begin. After the reset process is finished, the command bit would be self cleared. + * + * @param base SRC peripheral base address. + */ +static inline void SRC_DoSoftwareResetARMCore(SRC_Type *base) +{ + base->SCR |= SRC_SCR_SWRC_MASK; +} + +/*! + * @brief Check if the software for ARM core is done. + * + * @param base SRC peripheral base address. + * @return If the reset is done. + */ +static inline bool SRC_GetSoftwareResetARMCoreDone(SRC_Type *base) +{ + return (0U == (base->SCR & SRC_SCR_SWRC_MASK)); +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_SWRC */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_EIM_RST) && FSL_FEATURE_SRC_HAS_SCR_EIM_RST) +/*! + * @brief Assert the EIM reset. + * + * EIM reset is needed in order to reconfigure the EIM chip select. + * The software reset bit must de-asserted since this is not self-refresh. + * + * @param base SRC peripheral base address. + * @param enable Make the assertion or not. + */ +static inline void SRC_AssertEIMReset(SRC_Type *base, bool enable) +{ + if (enable) + { + base->SCR |= SRC_SCR_EIM_RST_MASK; + } + else + { + base->SCR &= ~SRC_SCR_EIM_RST_MASK; + } +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_EIM_RST */ + +/*! + * @brief Enable the WDOG Reset in SRC. + * + * WDOG Reset is enabled in SRC by default. If the WDOG event to SRC is masked, it would not create + * a reset to the chip. During the time the WDOG event is masked, when the WDOG event flag is + * asserted, it would remain asserted regardless of servicing the WDOG module. The only way to clear + * that bit is the hardware reset. + * + * @param base SRC peripheral base address. + * @param enable Enable the reset or not. + */ +static inline void SRC_EnableWDOGReset(SRC_Type *base, bool enable) +{ + if (enable) /* WDOG Reset is not masked in SRC (default). */ + { + base->SCR = (base->SCR & ~SRC_SCR_MWDR_MASK) | SRC_SCR_MWDR(0xA); + } + else /* WDOG Reset is masked in SRC. */ + { + base->SCR = (base->SCR & ~SRC_SCR_MWDR_MASK) | SRC_SCR_MWDR(0x5); + } +} + +#if !(defined(FSL_FEATURE_SRC_HAS_NO_SCR_WRBC) && FSL_FEATURE_SRC_HAS_NO_SCR_WRBC) +/*! + * @brief Set the delay count of waiting MMDC's acknowledge. + * + * This function would define the 32KHz clock cycles to count before bypassing the MMDC acknowledge + * for WARM reset. If the MMDC acknowledge is not asserted before this counter is elapsed, a COLD + * reset will be initiated. + * + * @param base SRC peripheral base address. + * @param option The option of setting mode, see to #src_warm_reset_bypass_count_t. + */ +static inline void SRC_SetWarmResetBypassCount(SRC_Type *base, src_warm_reset_bypass_count_t option) +{ + base->SCR = (base->SCR & ~SRC_SCR_WRBC_MASK) | SRC_SCR_WRBC(option); +} +#endif /* FSL_FEATURE_SRC_HAS_NO_SCR_WRBC */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST) && FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST) +/*! + * @brief Enable the lockup reset. + * + * @param base SRC peripheral base address. + * @param enable Enable the reset or not. + */ +static inline void SRC_EnableLockupReset(SRC_Type *base, bool enable) +{ + if (enable) /* Enable lockup reset. */ + { + base->SCR |= SRC_SCR_LOCKUP_RST_MASK; + } + else /* Disable lockup reset. */ + { + base->SCR &= ~SRC_SCR_LOCKUP_RST_MASK; + } +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST */ + +#if (defined(FSL_FEATURE_SRC_HAS_SCR_LUEN) && FSL_FEATURE_SRC_HAS_SCR_LUEN) +/*! + * @brief Enable the core lockup reset. + * + * When enable the core luckup reset, the system would be reset when core luckup event happens. + * + * @param base SRC peripheral base address. + * @param enable Enable the reset or not. + */ +static inline void SRC_EnableCoreLockupReset(SRC_Type *base, bool enable) +{ + if (enable) /* Core lockup will cause system reset. */ + { + base->SCR |= SRC_SCR_LUEN_MASK; + } + else /* Core lockup will not cause system reset. */ + { + base->SCR &= ~SRC_SCR_LUEN_MASK; + } +} +#endif /* FSL_FEATURE_SRC_HAS_SCR_LUEN */ + +#if !(defined(FSL_FEATURE_SRC_HAS_NO_SCR_WRE) && FSL_FEATURE_SRC_HAS_NO_SCR_WRE) +/*! + * @brief Enable the WARM reset. + * + * Only when the WARM reset is enabled, the WARM reset requests would be served by WARM reset. + * Otherwise, all the WARM reset sources would generate COLD reset. + * + * @param base SRC peripheral base address. + * @param enable Enable the WARM reset or not. + */ +static inline void SRC_EnableWarmReset(SRC_Type *base, bool enable) +{ + if (enable) + { + base->SCR |= SRC_SCR_WRE_MASK; + } + else + { + base->SCR &= ~SRC_SCR_WRE_MASK; + } +} +#endif /* FSL_FEATURE_SRC_HAS_NO_SCR_WRE */ + +#if (defined(FSL_FEATURE_SRC_HAS_SISR) && FSL_FEATURE_SRC_HAS_SISR) +/*! + * @brief Get interrupt status flags. + * + * @param base SRC peripheral base address. + * @return Mask value of status flags. See to $_src_status_flags. + */ +static inline uint32_t SRC_GetStatusFlags(SRC_Type *base) +{ + return base->SISR; +} +#endif /* FSL_FEATURE_SRC_HAS_SISR */ + +/*! + * @brief Get the boot mode register 1 value. + * + * The Boot Mode register contains bits that reflect the status of BOOT_CFGx pins of the chip. + * See to chip-specific document for detail information about value. + * + * @param base SRC peripheral base address. + * @return status of BOOT_CFGx pins of the chip. + */ +static inline uint32_t SRC_GetBootModeWord1(SRC_Type *base) +{ + return base->SBMR1; +} + +/*! + * @brief Get the boot mode register 2 value. + * + * The Boot Mode register contains bits that reflect the status of BOOT_MODEx Pins and fuse values + * that controls boot of the chip. See to chip-specific document for detail information about value. + * + * @param base SRC peripheral base address. + * @return status of BOOT_MODEx Pins and fuse values that controls boot of the chip. + */ +static inline uint32_t SRC_GetBootModeWord2(SRC_Type *base) +{ + return base->SBMR2; +} + +#if !(defined(FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) && FSL_FEATURE_SRC_HAS_NO_SRSR_WBI) +/*! + * @brief Set the warm boot indication flag. + * + * WARM boot indication shows that WARM boot was initiated by software. This indicates to the + * software that it saved the needed information in the memory before initiating the WARM reset. + * In this case, software will set this bit to '1', before initiating the WARM reset. The warm_boot + * bit should be used as indication only after a warm_reset sequence. Software should clear this bit + * after warm_reset to indicate that the next warm_reset is not performed with warm_boot. + * + * @param base SRC peripheral base address. + * @param enable Assert the flag or not. + */ +static inline void SRC_SetWarmBootIndication(SRC_Type *base, bool enable) +{ + if (enable) + { + base->SRSR = (base->SRSR & ~SRC_SRSR_W1C_BITS_MASK) | SRC_SRSR_WBI_MASK; + } + else + { + base->SRSR = (base->SRSR & ~SRC_SRSR_W1C_BITS_MASK) & ~SRC_SRSR_WBI_MASK; + } +} +#endif /* FSL_FEATURE_SRC_HAS_NO_SRSR_WBI */ + +/*! + * @brief Get the status flags of SRC. + * + * @param base SRC peripheral base address. + * @return Mask value of status flags, see to #_src_reset_status_flags. + */ +static inline uint32_t SRC_GetResetStatusFlags(SRC_Type *base) +{ + return base->SRSR; +} + +/*! + * @brief Clear the status flags of SRC. + * + * @param base SRC peripheral base address. + * @param Mask value of status flags to be cleared, see to #_src_reset_status_flags. + */ +void SRC_ClearResetStatusFlags(SRC_Type *base, uint32_t flags); + +/*! + * @brief Set value to general purpose registers. + * + * General purpose registers (GPRx) would hold the value during reset process. Wakeup function could + * be kept in these register. For example, the GPR1 holds the entry function for waking-up from + * Partial SLEEP mode while the GPR2 holds the argument. Other GPRx register would store the + * arbitray values. + * + * @param base SRC peripheral base address. + * @param index The index of GPRx register array. Note index 0 reponses the GPR1 register. + * @param value Setting value for GPRx register. + */ +static inline void SRC_SetGeneralPurposeRegister(SRC_Type *base, uint32_t index, uint32_t value) +{ + assert(index < SRC_GPR_COUNT); + + base->GPR[index] = value; +} + +/*! + * @brief Get the value from general purpose registers. + * + * @param base SRC peripheral base address. + * @param index The index of GPRx register array. Note index 0 reponses the GPR1 register. + * @return The setting value for GPRx register. + */ +static inline uint32_t SRC_GetGeneralPurposeRegister(SRC_Type *base, uint32_t index) +{ + assert(index < SRC_GPR_COUNT); + + return base->GPR[index]; +} + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_SRC_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_tempmon.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_tempmon.c new file mode 100644 index 0000000000..2d110547df --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_tempmon.c @@ -0,0 +1,185 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_tempmon.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.tempmon" +#endif + +/*! @brief TEMPMON calibration data mask. */ +#define TEMPMON_HOTTEMPMASK 0xFFU +#define TEMPMON_HOTTEMPSHIFT 0x00U +#define TEMPMON_HOTCOUNTMASK 0xFFF00U +#define TEMPMON_HOTCOUNTSHIFT 0X08U +#define TEMPMON_ROOMCOUNTMASK 0xFFF00000U +#define TEMPMON_ROOMCOUNTSHIFT 0x14U + +/*! @brief the room temperature. */ +#define TEMPMON_ROOMTEMP 25.0 + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +static uint32_t s_hotTemp; /*!< The value of TEMPMON_TEMPSENSE0[TEMP_VALUE] at room temperature .*/ +static uint32_t s_hotCount; /*!< The value of TEMPMON_TEMPSENSE0[TEMP_VALUE] at the hot temperature.*/ +static float s_hotT_ROOM; /*!< The value of s_hotTemp minus room temperature(25¡æ).*/ +static uint32_t s_roomC_hotC; /*!< The value of s_roomCount minus s_hotCount.*/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Initializes the TEMPMON module. + * + * param base TEMPMON base pointer + * param config Pointer to configuration structure. + */ +void TEMPMON_Init(TEMPMON_Type *base, const tempmon_config_t *config) +{ + assert(NULL != config); + + uint32_t calibrationData; + uint32_t roomCount; + + /* Power on the temperature sensor*/ + base->TEMPSENSE0 &= ~TEMPMON_TEMPSENSE0_POWER_DOWN_MASK; + + /* Set temperature monitor frequency */ + base->TEMPSENSE1 = TEMPMON_TEMPSENSE1_MEASURE_FREQ(config->frequency); + + /* ready to read calibration data */ + calibrationData = OCOTP->ANA1; + s_hotTemp = (uint32_t)(calibrationData & TEMPMON_HOTTEMPMASK) >> TEMPMON_HOTTEMPSHIFT; + s_hotCount = (uint32_t)(calibrationData & TEMPMON_HOTCOUNTMASK) >> TEMPMON_HOTCOUNTSHIFT; + roomCount = (uint32_t)(calibrationData & TEMPMON_ROOMCOUNTMASK) >> TEMPMON_ROOMCOUNTSHIFT; + + s_hotT_ROOM = s_hotTemp - TEMPMON_ROOMTEMP; + s_roomC_hotC = roomCount - s_hotCount; + + /* Set alarm temperature */ + TEMPMON_SetTempAlarm(base, config->highAlarmTemp, kTEMPMON_HighAlarmMode); + TEMPMON_SetTempAlarm(base, config->panicAlarmTemp, kTEMPMON_PanicAlarmMode); + TEMPMON_SetTempAlarm(base, config->lowAlarmTemp, kTEMPMON_LowAlarmMode); +} + +/*! + * brief Deinitializes the TEMPMON module. + * + * param base TEMPMON base pointer + */ +void TEMPMON_Deinit(TEMPMON_Type *base) +{ + base->TEMPSENSE0 |= TEMPMON_TEMPSENSE0_POWER_DOWN_MASK; +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the TEMPMON configuration structure to a default value. The default + * values are: + * tempmonConfig->frequency = 0x02U; + * tempmonConfig->highAlarmTemp = 44U; + * tempmonConfig->panicAlarmTemp = 90U; + * tempmonConfig->lowAlarmTemp = 39U; + * + * param config Pointer to a configuration structure. + */ +void TEMPMON_GetDefaultConfig(tempmon_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + /* Default measure frequency */ + config->frequency = 0x03U; + /* Default high alarm temperature */ + config->highAlarmTemp = 40U; + /* Default panic alarm temperature */ + config->panicAlarmTemp = 90U; + /* Default low alarm temperature */ + config->lowAlarmTemp = 20U; +} + +/*! + * brief Get current temperature with the fused temperature calibration data. + * + * param base TEMPMON base pointer + * return current temperature with degrees Celsius. + */ +float TEMPMON_GetCurrentTemperature(TEMPMON_Type *base) +{ + /* Check arguments */ + assert(NULL != base); + + uint32_t nmeas; + float tmeas; + + while (!(base->TEMPSENSE0 & TEMPMON_TEMPSENSE0_FINISHED_MASK)) + { + } + + /* ready to read temperature code value */ + nmeas = (base->TEMPSENSE0 & TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) >> TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT; + + /* Calculate temperature */ + tmeas = s_hotTemp - (float)((nmeas - s_hotCount) * s_hotT_ROOM / s_roomC_hotC); + + return tmeas; +} + +/*! + * brief Set the temperature count (raw sensor output) that will generate an alarm interrupt. + * + * param base TEMPMON base pointer + * param tempVal The alarm temperature with degrees Celsius + * param alarmMode The alarm mode. + */ +void TEMPMON_SetTempAlarm(TEMPMON_Type *base, uint32_t tempVal, tempmon_alarm_mode alarmMode) +{ + /* Check arguments */ + assert(NULL != base); + + uint32_t tempCodeVal; + + /* Calculate alarm temperature code value */ + tempCodeVal = (uint32_t)(s_hotCount + (s_hotTemp - tempVal) * s_roomC_hotC / s_hotT_ROOM); + + switch (alarmMode) + { + case kTEMPMON_HighAlarmMode: + /* Set high alarm temperature code value */ + base->TEMPSENSE0 |= TEMPMON_TEMPSENSE0_ALARM_VALUE(tempCodeVal); + break; + + case kTEMPMON_PanicAlarmMode: + /* Set panic alarm temperature code value */ + base->TEMPSENSE2 |= TEMPMON_TEMPSENSE2_PANIC_ALARM_VALUE(tempCodeVal); + break; + + case kTEMPMON_LowAlarmMode: + /* Set low alarm temperature code value */ + base->TEMPSENSE2 |= TEMPMON_TEMPSENSE2_LOW_ALARM_VALUE(tempCodeVal); + break; + + default: + assert(false); + break; + } +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_tempmon.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_tempmon.h new file mode 100644 index 0000000000..eaa5be67dd --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_tempmon.h @@ -0,0 +1,126 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_TEMPMON_H_ +#define _FSL_TEMPMON_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup tempmon + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_TEMPMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +/*@}*/ + +/*! @brief TEMPMON temperature structure. */ +typedef struct _tempmon_config +{ + uint16_t frequency; /*!< The temperature measure frequency.*/ + uint32_t highAlarmTemp; /*!< The high alarm temperature.*/ + uint32_t panicAlarmTemp; /*!< The panic alarm temperature.*/ + uint32_t lowAlarmTemp; /*!< The low alarm temperature.*/ +} tempmon_config_t; + +/*! @brief TEMPMON alarm mode. */ +typedef enum _tempmon_alarm_mode +{ + kTEMPMON_HighAlarmMode = 0U, /*!< The high alarm temperature interrupt mode.*/ + kTEMPMON_PanicAlarmMode = 1U, /*!< The panic alarm temperature interrupt mode.*/ + kTEMPMON_LowAlarmMode = 2U, /*!< The low alarm temperature interrupt mode.*/ +} tempmon_alarm_mode; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes the TEMPMON module. + * + * @param base TEMPMON base pointer + * @param config Pointer to configuration structure. + */ +void TEMPMON_Init(TEMPMON_Type *base, const tempmon_config_t *config); + +/*! + * @brief Deinitializes the TEMPMON module. + * + * @param base TEMPMON base pointer + */ +void TEMPMON_Deinit(TEMPMON_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the TEMPMON configuration structure to a default value. The default + * values are: + * tempmonConfig->frequency = 0x02U; + * tempmonConfig->highAlarmTemp = 44U; + * tempmonConfig->panicAlarmTemp = 90U; + * tempmonConfig->lowAlarmTemp = 39U; + * + * @param config Pointer to a configuration structure. + */ +void TEMPMON_GetDefaultConfig(tempmon_config_t *config); + +/*! + * @brief start the temperature measurement process. + * + * @param base TEMPMON base pointer. + */ +static inline void TEMPMON_StartMeasure(TEMPMON_Type *base) +{ + base->TEMPSENSE0 |= TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK; +} + +/*! + * @brief stop the measurement process. + * + * @param base TEMPMON base pointer + */ +static inline void TEMPMON_StopMeasure(TEMPMON_Type *base) +{ + base->TEMPSENSE0 &= ~TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK; +} + +/*! + * @brief Get current temperature with the fused temperature calibration data. + * + * @param base TEMPMON base pointer + * @return current temperature with degrees Celsius. + */ +float TEMPMON_GetCurrentTemperature(TEMPMON_Type *base); + +/*! + * @brief Set the temperature count (raw sensor output) that will generate an alarm interrupt. + * + * @param base TEMPMON base pointer + * @param tempVal The alarm temperature with degrees Celsius + * @param alarmMode The alarm mode. + */ +void TEMPMON_SetTempAlarm(TEMPMON_Type *base, uint32_t tempVal, tempmon_alarm_mode alarmMode); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_TEMPMON_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_trng.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_trng.c new file mode 100644 index 0000000000..28e02887dd --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_trng.c @@ -0,0 +1,1762 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_trng.h" + +#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && FSL_FEATURE_SOC_TRNG_COUNT + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.trng" +#endif + +/* Default values for user configuration structure.*/ +#if (defined(KW40Z4_SERIES) || defined(KW41Z4_SERIES) || defined(KW31Z4_SERIES) || defined(KW21Z4_SERIES) || \ + defined(MCIMX7U5_M4_SERIES) || defined(KW36Z4_SERIES) || defined(KW37A4_SERIES) || defined(KW37Z4_SERIES) ||\ + defined(KW38A4_SERIES) || defined(KW38Z4_SERIES) || defined(KW39A4_SERIES)) +#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv8 +#elif (defined(KV56F24_SERIES) || defined(KV58F24_SERIES) || defined(KL28Z7_SERIES) || defined(KL81Z7_SERIES) || \ + defined(KL82Z7_SERIES)) +#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv4 +#elif defined(K81F25615_SERIES) +#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv2 +#else +#define TRNG_USER_CONFIG_DEFAULT_OSC_DIV kTRNG_RingOscDiv0 +#endif + +#define TRNG_USER_CONFIG_DEFAULT_LOCK 0 +#define TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY 3200 +#define TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE 2500 +#define TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT 63 +#define TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT 1 +#define TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT 34 + +#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM 1384 +#define TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM (TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM - 268) +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM 405 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM - 178) +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM 220 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM - 122) +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM 125 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM - 88) +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM 75 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM - 64) +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM 47 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM - 46) +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM 47 +#define TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM (TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM - 46) +#define TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM 26912 +#define TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM (TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM - 2467) +#define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM 25600 +#define TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM 1600 + +/*! @brief TRNG work mode */ +typedef enum _trng_work_mode +{ + kTRNG_WorkModeRun = 0U, /*!< Run Mode. */ + kTRNG_WorkModeProgram = 1U /*!< Program Mode. */ +} trng_work_mode_t; + +/*! @brief TRNG statistical check type*/ +typedef enum _trng_statistical_check +{ + kTRNG_StatisticalCheckMonobit = + 1U, /*!< Statistical check of number of ones/zero detected during entropy generation. */ + kTRNG_StatisticalCheckRunBit1, /*!< Statistical check of number of runs of length 1 detected during entropy + generation. */ + kTRNG_StatisticalCheckRunBit2, /*!< Statistical check of number of runs of length 2 detected during entropy + generation. */ + kTRNG_StatisticalCheckRunBit3, /*!< Statistical check of number of runs of length 3 detected during entropy + generation. */ + kTRNG_StatisticalCheckRunBit4, /*!< Statistical check of number of runs of length 4 detected during entropy + generation. */ + kTRNG_StatisticalCheckRunBit5, /*!< Statistical check of number of runs of length 5 detected during entropy + generation. */ + kTRNG_StatisticalCheckRunBit6Plus, /*!< Statistical check of number of runs of length 6 or more detected during + entropy generation. */ + kTRNG_StatisticalCheckPoker, /*!< Statistical check of "Poker Test". */ + kTRNG_StatisticalCheckFrequencyCount /*!< Statistical check of entropy sample frequency count. */ +} trng_statistical_check_t; + +/******************************************************************************* + * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register + ******************************************************************************/ +/*! + * @name Register TRNG_SCMISC, field RTY_CT[19:16] (RW) + * + * RETRY COUNT. If a statistical check fails during the TRNG Entropy Generation, + * the RTY_CT value indicates the number of times a retry should occur before + * generating an error. This field is writable only if MCTL[PRGM] bit is 1. This + * field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 1h by writing + * the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCMISC_RTY_CT field. */ +#define TRNG_RD_SCMISC_RTY_CT(base) ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_RTY_CT_MASK) >> TRNG_SCMISC_RTY_CT_SHIFT) + +/*! @brief Set the RTY_CT field to a new value. */ +#define TRNG_WR_SCMISC_RTY_CT(base, value) (TRNG_RMW_SCMISC(base, TRNG_SCMISC_RTY_CT_MASK, TRNG_SCMISC_RTY_CT(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SCML - RNG Statistical Check Monobit Limit Register + ******************************************************************************/ +/*! + * @brief TRNG_SCML - RNG Statistical Check Monobit Limit Register (RW) + * + * Reset value: 0x010C0568U + * + * The RNG Statistical Check Monobit Limit Register defines the allowable + * maximum and minimum number of ones/zero detected during entropy generation. To pass + * the test, the number of ones/zeroes generated must be less than the programmed + * maximum value, and the number of ones/zeroes generated must be greater than + * (maximum - range). If this test fails, the Retry Counter in SCMISC will be + * decremented, and a retry will occur if the Retry Count has not reached zero. If + * the Retry Count has reached zero, an error will be generated. Note that this + * offset (0xBASE_0620) is used as SCML only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, + * this offset is used as SCMC readback register. + */ +/*! + * @name Constants and macros for entire TRNG_SCML register + */ +/*@{*/ +#define TRNG_SCML_REG(base) ((base)->SCML) +#define TRNG_RD_SCML(base) (TRNG_SCML_REG(base)) +#define TRNG_WR_SCML(base, value) (TRNG_SCML_REG(base) = (value)) +#define TRNG_RMW_SCML(base, mask, value) (TRNG_WR_SCML(base, (TRNG_RD_SCML(base) & ~(mask)) | (value))) +/*@}*/ +/*! + * @name Register TRNG_SCML, field MONO_MAX[15:0] (RW) + * + * Monobit Maximum Limit. Defines the maximum allowable count taken during + * entropy generation. The number of ones/zeroes detected during entropy generation + * must be less than MONO_MAX, else a retry or error will occur. This register is + * cleared to 00056Bh (decimal 1387) by writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCML_MONO_MAX field. */ +#define TRNG_RD_SCML_MONO_MAX(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_MAX_MASK) >> TRNG_SCML_MONO_MAX_SHIFT) + +/*! @brief Set the MONO_MAX field to a new value. */ +#define TRNG_WR_SCML_MONO_MAX(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_MAX_MASK, TRNG_SCML_MONO_MAX(value))) +/*@}*/ +/*! + * @name Register TRNG_SCML, field MONO_RNG[31:16] (RW) + * + * Monobit Range. The number of ones/zeroes detected during entropy generation + * must be greater than MONO_MAX - MONO_RNG, else a retry or error will occur. + * This register is cleared to 000112h (decimal 274) by writing the MCTL[RST_DEF] + * bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCML_MONO_RNG field. */ +#define TRNG_RD_SCML_MONO_RNG(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_RNG_MASK) >> TRNG_SCML_MONO_RNG_SHIFT) + +/*! @brief Set the MONO_RNG field to a new value. */ +#define TRNG_WR_SCML_MONO_RNG(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_RNG_MASK, TRNG_SCML_MONO_RNG(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register (RW) + * + * Reset value: 0x00B20195U + * + * The RNG Statistical Check Run Length 1 Limit Register defines the allowable + * maximum and minimum number of runs of length 1 detected during entropy + * generation. To pass the test, the number of runs of length 1 (for samples of both 0 + * and 1) must be less than the programmed maximum value, and the number of runs of + * length 1 must be greater than (maximum - range). If this test fails, the + * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry + * Count has not reached zero. If the Retry Count has reached zero, an error will + * be generated. Note that this address (0xBASE_0624) is used as SCR1L only if + * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR1C readback + * register. + */ +/*! + * @name Constants and macros for entire TRNG_SCR1L register + */ +/*@{*/ +#define TRNG_SCR1L_REG(base) ((base)->SCR1L) +#define TRNG_RD_SCR1L(base) (TRNG_SCR1L_REG(base)) +#define TRNG_WR_SCR1L(base, value) (TRNG_SCR1L_REG(base) = (value)) +#define TRNG_RMW_SCR1L(base, mask, value) (TRNG_WR_SCR1L(base, (TRNG_RD_SCR1L(base) & ~(mask)) | (value))) +/*@}*/ + +/*! + * @name Register TRNG_SCR1L, field RUN1_MAX[14:0] (RW) + * + * Run Length 1 Maximum Limit. Defines the maximum allowable runs of length 1 + * (for both 0 and 1) detected during entropy generation. The number of runs of + * length 1 detected during entropy generation must be less than RUN1_MAX, else a + * retry or error will occur. This register is cleared to 01E5h (decimal 485) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR1L_RUN1_MAX field. */ +#define TRNG_RD_SCR1L_RUN1_MAX(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_MAX_MASK) >> TRNG_SCR1L_RUN1_MAX_SHIFT) + +/*! @brief Set the RUN1_MAX field to a new value. */ +#define TRNG_WR_SCR1L_RUN1_MAX(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_MAX_MASK, TRNG_SCR1L_RUN1_MAX(value))) +/*@}*/ + +/*! + * @name Register TRNG_SCR1L, field RUN1_RNG[30:16] (RW) + * + * Run Length 1 Range. The number of runs of length 1 (for both 0 and 1) + * detected during entropy generation must be greater than RUN1_MAX - RUN1_RNG, else a + * retry or error will occur. This register is cleared to 0102h (decimal 258) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR1L_RUN1_RNG field. */ +#define TRNG_RD_SCR1L_RUN1_RNG(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_RNG_MASK) >> TRNG_SCR1L_RUN1_RNG_SHIFT) + +/*! @brief Set the RUN1_RNG field to a new value. */ +#define TRNG_WR_SCR1L_RUN1_RNG(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_RNG_MASK, TRNG_SCR1L_RUN1_RNG(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register (RW) + * + * Reset value: 0x007A00DCU + * + * The RNG Statistical Check Run Length 2 Limit Register defines the allowable + * maximum and minimum number of runs of length 2 detected during entropy + * generation. To pass the test, the number of runs of length 2 (for samples of both 0 + * and 1) must be less than the programmed maximum value, and the number of runs of + * length 2 must be greater than (maximum - range). If this test fails, the + * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry + * Count has not reached zero. If the Retry Count has reached zero, an error will + * be generated. Note that this address (0xBASE_0628) is used as SCR2L only if + * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR2C readback + * register. + */ +/*! + * @name Constants and macros for entire TRNG_SCR2L register + */ +/*@{*/ +#define TRNG_SCR2L_REG(base) ((base)->SCR2L) +#define TRNG_RD_SCR2L(base) (TRNG_SCR2L_REG(base)) +#define TRNG_WR_SCR2L(base, value) (TRNG_SCR2L_REG(base) = (value)) +#define TRNG_RMW_SCR2L(base, mask, value) (TRNG_WR_SCR2L(base, (TRNG_RD_SCR2L(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_SCR2L bitfields + */ + +/*! + * @name Register TRNG_SCR2L, field RUN2_MAX[13:0] (RW) + * + * Run Length 2 Maximum Limit. Defines the maximum allowable runs of length 2 + * (for both 0 and 1) detected during entropy generation. The number of runs of + * length 2 detected during entropy generation must be less than RUN2_MAX, else a + * retry or error will occur. This register is cleared to 00DCh (decimal 220) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR2L_RUN2_MAX field. */ +#define TRNG_RD_SCR2L_RUN2_MAX(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_MAX_MASK) >> TRNG_SCR2L_RUN2_MAX_SHIFT) + +/*! @brief Set the RUN2_MAX field to a new value. */ +#define TRNG_WR_SCR2L_RUN2_MAX(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_MAX_MASK, TRNG_SCR2L_RUN2_MAX(value))) +/*@}*/ + +/*! + * @name Register TRNG_SCR2L, field RUN2_RNG[29:16] (RW) + * + * Run Length 2 Range. The number of runs of length 2 (for both 0 and 1) + * detected during entropy generation must be greater than RUN2_MAX - RUN2_RNG, else a + * retry or error will occur. This register is cleared to 007Ah (decimal 122) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR2L_RUN2_RNG field. */ +#define TRNG_RD_SCR2L_RUN2_RNG(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_RNG_MASK) >> TRNG_SCR2L_RUN2_RNG_SHIFT) + +/*! @brief Set the RUN2_RNG field to a new value. */ +#define TRNG_WR_SCR2L_RUN2_RNG(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_RNG_MASK, TRNG_SCR2L_RUN2_RNG(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register (RW) + * + * Reset value: 0x0058007DU + * + * The RNG Statistical Check Run Length 3 Limit Register defines the allowable + * maximum and minimum number of runs of length 3 detected during entropy + * generation. To pass the test, the number of runs of length 3 (for samples of both 0 + * and 1) must be less than the programmed maximum value, and the number of runs of + * length 3 must be greater than (maximum - range). If this test fails, the + * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry + * Count has not reached zero. If the Retry Count has reached zero, an error will + * be generated. Note that this address (0xBASE_062C) is used as SCR3L only if + * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR3C readback + * register. + */ +/*! + * @name Constants and macros for entire TRNG_SCR3L register + */ +/*@{*/ +#define TRNG_SCR3L_REG(base) ((base)->SCR3L) +#define TRNG_RD_SCR3L(base) (TRNG_SCR3L_REG(base)) +#define TRNG_WR_SCR3L(base, value) (TRNG_SCR3L_REG(base) = (value)) +#define TRNG_RMW_SCR3L(base, mask, value) (TRNG_WR_SCR3L(base, (TRNG_RD_SCR3L(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_SCR3L bitfields + */ + +/*! + * @name Register TRNG_SCR3L, field RUN3_MAX[12:0] (RW) + * + * Run Length 3 Maximum Limit. Defines the maximum allowable runs of length 3 + * (for both 0 and 1) detected during entropy generation. The number of runs of + * length 3 detected during entropy generation must be less than RUN3_MAX, else a + * retry or error will occur. This register is cleared to 007Dh (decimal 125) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR3L_RUN3_MAX field. */ +#define TRNG_RD_SCR3L_RUN3_MAX(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_MAX_MASK) >> TRNG_SCR3L_RUN3_MAX_SHIFT) + +/*! @brief Set the RUN3_MAX field to a new value. */ +#define TRNG_WR_SCR3L_RUN3_MAX(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_MAX_MASK, TRNG_SCR3L_RUN3_MAX(value))) +/*@}*/ + +/*! + * @name Register TRNG_SCR3L, field RUN3_RNG[28:16] (RW) + * + * Run Length 3 Range. The number of runs of length 3 (for both 0 and 1) + * detected during entropy generation must be greater than RUN3_MAX - RUN3_RNG, else a + * retry or error will occur. This register is cleared to 0058h (decimal 88) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR3L_RUN3_RNG field. */ +#define TRNG_RD_SCR3L_RUN3_RNG(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_RNG_MASK) >> TRNG_SCR3L_RUN3_RNG_SHIFT) + +/*! @brief Set the RUN3_RNG field to a new value. */ +#define TRNG_WR_SCR3L_RUN3_RNG(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_RNG_MASK, TRNG_SCR3L_RUN3_RNG(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register (RW) + * + * Reset value: 0x0040004BU + * + * The RNG Statistical Check Run Length 4 Limit Register defines the allowable + * maximum and minimum number of runs of length 4 detected during entropy + * generation. To pass the test, the number of runs of length 4 (for samples of both 0 + * and 1) must be less than the programmed maximum value, and the number of runs of + * length 4 must be greater than (maximum - range). If this test fails, the + * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry + * Count has not reached zero. If the Retry Count has reached zero, an error will + * be generated. Note that this address (0xBASE_0630) is used as SCR4L only if + * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR4C readback + * register. + */ +/*! + * @name Constants and macros for entire TRNG_SCR4L register + */ +/*@{*/ +#define TRNG_SCR4L_REG(base) ((base)->SCR4L) +#define TRNG_RD_SCR4L(base) (TRNG_SCR4L_REG(base)) +#define TRNG_WR_SCR4L(base, value) (TRNG_SCR4L_REG(base) = (value)) +#define TRNG_RMW_SCR4L(base, mask, value) (TRNG_WR_SCR4L(base, (TRNG_RD_SCR4L(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_SCR4L bitfields + */ + +/*! + * @name Register TRNG_SCR4L, field RUN4_MAX[11:0] (RW) + * + * Run Length 4 Maximum Limit. Defines the maximum allowable runs of length 4 + * (for both 0 and 1) detected during entropy generation. The number of runs of + * length 4 detected during entropy generation must be less than RUN4_MAX, else a + * retry or error will occur. This register is cleared to 004Bh (decimal 75) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR4L_RUN4_MAX field. */ +#define TRNG_RD_SCR4L_RUN4_MAX(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_MAX_MASK) >> TRNG_SCR4L_RUN4_MAX_SHIFT) + +/*! @brief Set the RUN4_MAX field to a new value. */ +#define TRNG_WR_SCR4L_RUN4_MAX(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_MAX_MASK, TRNG_SCR4L_RUN4_MAX(value))) +/*@}*/ + +/*! + * @name Register TRNG_SCR4L, field RUN4_RNG[27:16] (RW) + * + * Run Length 4 Range. The number of runs of length 4 (for both 0 and 1) + * detected during entropy generation must be greater than RUN4_MAX - RUN4_RNG, else a + * retry or error will occur. This register is cleared to 0040h (decimal 64) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR4L_RUN4_RNG field. */ +#define TRNG_RD_SCR4L_RUN4_RNG(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_RNG_MASK) >> TRNG_SCR4L_RUN4_RNG_SHIFT) + +/*! @brief Set the RUN4_RNG field to a new value. */ +#define TRNG_WR_SCR4L_RUN4_RNG(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_RNG_MASK, TRNG_SCR4L_RUN4_RNG(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register (RW) + * + * Reset value: 0x002E002FU + * + * The RNG Statistical Check Run Length 5 Limit Register defines the allowable + * maximum and minimum number of runs of length 5 detected during entropy + * generation. To pass the test, the number of runs of length 5 (for samples of both 0 + * and 1) must be less than the programmed maximum value, and the number of runs of + * length 5 must be greater than (maximum - range). If this test fails, the + * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry + * Count has not reached zero. If the Retry Count has reached zero, an error will + * be generated. Note that this address (0xBASE_0634) is used as SCR5L only if + * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR5C readback + * register. + */ +/*! + * @name Constants and macros for entire TRNG_SCR5L register + */ +/*@{*/ +#define TRNG_SCR5L_REG(base) ((base)->SCR5L) +#define TRNG_RD_SCR5L(base) (TRNG_SCR5L_REG(base)) +#define TRNG_WR_SCR5L(base, value) (TRNG_SCR5L_REG(base) = (value)) +#define TRNG_RMW_SCR5L(base, mask, value) (TRNG_WR_SCR5L(base, (TRNG_RD_SCR5L(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_SCR5L bitfields + */ + +/*! + * @name Register TRNG_SCR5L, field RUN5_MAX[10:0] (RW) + * + * Run Length 5 Maximum Limit. Defines the maximum allowable runs of length 5 + * (for both 0 and 1) detected during entropy generation. The number of runs of + * length 5 detected during entropy generation must be less than RUN5_MAX, else a + * retry or error will occur. This register is cleared to 002Fh (decimal 47) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR5L_RUN5_MAX field. */ +#define TRNG_RD_SCR5L_RUN5_MAX(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_MAX_MASK) >> TRNG_SCR5L_RUN5_MAX_SHIFT) + +/*! @brief Set the RUN5_MAX field to a new value. */ +#define TRNG_WR_SCR5L_RUN5_MAX(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_MAX_MASK, TRNG_SCR5L_RUN5_MAX(value))) +/*@}*/ + +/*! + * @name Register TRNG_SCR5L, field RUN5_RNG[26:16] (RW) + * + * Run Length 5 Range. The number of runs of length 5 (for both 0 and 1) + * detected during entropy generation must be greater than RUN5_MAX - RUN5_RNG, else a + * retry or error will occur. This register is cleared to 002Eh (decimal 46) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR5L_RUN5_RNG field. */ +#define TRNG_RD_SCR5L_RUN5_RNG(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_RNG_MASK) >> TRNG_SCR5L_RUN5_RNG_SHIFT) + +/*! @brief Set the RUN5_RNG field to a new value. */ +#define TRNG_WR_SCR5L_RUN5_RNG(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_RNG_MASK, TRNG_SCR5L_RUN5_RNG(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register (RW) + * + * Reset value: 0x002E002FU + * + * The RNG Statistical Check Run Length 6+ Limit Register defines the allowable + * maximum and minimum number of runs of length 6 or more detected during entropy + * generation. To pass the test, the number of runs of length 6 or more (for + * samples of both 0 and 1) must be less than the programmed maximum value, and the + * number of runs of length 6 or more must be greater than (maximum - range). If + * this test fails, the Retry Counter in SCMISC will be decremented, and a retry + * will occur if the Retry Count has not reached zero. If the Retry Count has + * reached zero, an error will be generated. Note that this offset (0xBASE_0638) is + * used as SCR6PL only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is + * used as SCR6PC readback register. + */ +/*! + * @name Constants and macros for entire TRNG_SCR6PL register + */ +/*@{*/ +#define TRNG_SCR6PL_REG(base) ((base)->SCR6PL) +#define TRNG_RD_SCR6PL(base) (TRNG_SCR6PL_REG(base)) +#define TRNG_WR_SCR6PL(base, value) (TRNG_SCR6PL_REG(base) = (value)) +#define TRNG_RMW_SCR6PL(base, mask, value) (TRNG_WR_SCR6PL(base, (TRNG_RD_SCR6PL(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_SCR6PL bitfields + */ + +/*! + * @name Register TRNG_SCR6PL, field RUN6P_MAX[10:0] (RW) + * + * Run Length 6+ Maximum Limit. Defines the maximum allowable runs of length 6 + * or more (for both 0 and 1) detected during entropy generation. The number of + * runs of length 6 or more detected during entropy generation must be less than + * RUN6P_MAX, else a retry or error will occur. This register is cleared to 002Fh + * (decimal 47) by writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR6PL_RUN6P_MAX field. */ +#define TRNG_RD_SCR6PL_RUN6P_MAX(base) \ + ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_MAX_MASK) >> TRNG_SCR6PL_RUN6P_MAX_SHIFT) + +/*! @brief Set the RUN6P_MAX field to a new value. */ +#define TRNG_WR_SCR6PL_RUN6P_MAX(base, value) \ + (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_MAX_MASK, TRNG_SCR6PL_RUN6P_MAX(value))) +/*@}*/ + +/*! + * @name Register TRNG_SCR6PL, field RUN6P_RNG[26:16] (RW) + * + * Run Length 6+ Range. The number of runs of length 6 or more (for both 0 and + * 1) detected during entropy generation must be greater than RUN6P_MAX - + * RUN6P_RNG, else a retry or error will occur. This register is cleared to 002Eh + * (decimal 46) by writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCR6PL_RUN6P_RNG field. */ +#define TRNG_RD_SCR6PL_RUN6P_RNG(base) \ + ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_RNG_MASK) >> TRNG_SCR6PL_RUN6P_RNG_SHIFT) + +/*! @brief Set the RUN6P_RNG field to a new value. */ +#define TRNG_WR_SCR6PL_RUN6P_RNG(base, value) \ + (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_RNG_MASK, TRNG_SCR6PL_RUN6P_RNG(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_PKRMAX - RNG Poker Maximum Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_PKRMAX - RNG Poker Maximum Limit Register (RW) + * + * Reset value: 0x00006920U + * + * The RNG Poker Maximum Limit Register defines Maximum Limit allowable during + * the TRNG Statistical Check Poker Test. Note that this offset (0xBASE_060C) is + * used as PKRMAX only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is used + * as the PKRSQ readback register. + */ +/*! + * @name Constants and macros for entire TRNG_PKRMAX register + */ +/*@{*/ +#define TRNG_PKRMAX_REG(base) ((base)->PKRMAX) +#define TRNG_RD_PKRMAX(base) (TRNG_PKRMAX_REG(base)) +#define TRNG_WR_PKRMAX(base, value) (TRNG_PKRMAX_REG(base) = (value)) +#define TRNG_RMW_PKRMAX(base, mask, value) (TRNG_WR_PKRMAX(base, (TRNG_RD_PKRMAX(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_PKRMAX bitfields + */ + +/*! + * @name Register TRNG_PKRMAX, field PKR_MAX[23:0] (RW) + * + * Poker Maximum Limit. During the TRNG Statistical Checks, a "Poker Test" is + * run which requires a maximum and minimum limit. The maximum allowable result is + * programmed in the PKRMAX[PKR_MAX] register. This field is writable only if + * MCTL[PRGM] bit is 1. This register is cleared to 006920h (decimal 26912) by + * writing the MCTL[RST_DEF] bit to 1. Note that the PKRMAX and PKRRNG registers + * combined are used to define the minimum allowable Poker result, which is PKR_MAX - + * PKR_RNG + 1. Note that if MCTL[PRGM] bit is 0, this register address is used + * to read the Poker Test Square Calculation result in register PKRSQ, as defined + * in the following section. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_PKRMAX_PKR_MAX field. */ +#define TRNG_RD_PKRMAX_PKR_MAX(base) ((TRNG_PKRMAX_REG(base) & TRNG_PKRMAX_PKR_MAX_MASK) >> TRNG_PKRMAX_PKR_MAX_SHIFT) + +/*! @brief Set the PKR_MAX field to a new value. */ +#define TRNG_WR_PKRMAX_PKR_MAX(base, value) \ + (TRNG_RMW_PKRMAX(base, TRNG_PKRMAX_PKR_MAX_MASK, TRNG_PKRMAX_PKR_MAX(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_PKRRNG - RNG Poker Range Register + ******************************************************************************/ + +/*! + * @brief TRNG_PKRRNG - RNG Poker Range Register (RW) + * + * Reset value: 0x000009A3U + * + * The RNG Poker Range Register defines the difference between the TRNG Poker + * Maximum Limit and the minimum limit. These limits are used during the TRNG + * Statistical Check Poker Test. + */ +/*! + * @name Constants and macros for entire TRNG_PKRRNG register + */ +/*@{*/ +#define TRNG_PKRRNG_REG(base) ((base)->PKRRNG) +#define TRNG_RD_PKRRNG(base) (TRNG_PKRRNG_REG(base)) +#define TRNG_WR_PKRRNG(base, value) (TRNG_PKRRNG_REG(base) = (value)) +#define TRNG_RMW_PKRRNG(base, mask, value) (TRNG_WR_PKRRNG(base, (TRNG_RD_PKRRNG(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_PKRRNG bitfields + */ + +/*! + * @name Register TRNG_PKRRNG, field PKR_RNG[15:0] (RW) + * + * Poker Range. During the TRNG Statistical Checks, a "Poker Test" is run which + * requires a maximum and minimum limit. The maximum is programmed in the + * RTPKRMAX[PKR_MAX] register, and the minimum is derived by subtracting the PKR_RNG + * value from the programmed maximum value. This field is writable only if + * MCTL[PRGM] bit is 1. This field will read zeroes if MCTL[PRGM] = 0. This field is + * cleared to 09A3h (decimal 2467) by writing the MCTL[RST_DEF] bit to 1. Note that + * the minimum allowable Poker result is PKR_MAX - PKR_RNG + 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_PKRRNG_PKR_RNG field. */ +#define TRNG_RD_PKRRNG_PKR_RNG(base) ((TRNG_PKRRNG_REG(base) & TRNG_PKRRNG_PKR_RNG_MASK) >> TRNG_PKRRNG_PKR_RNG_SHIFT) + +/*! @brief Set the PKR_RNG field to a new value. */ +#define TRNG_WR_PKRRNG_PKR_RNG(base, value) \ + (TRNG_RMW_PKRRNG(base, TRNG_PKRRNG_PKR_RNG_MASK, TRNG_PKRRNG_PKR_RNG(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register (RW) + * + * Reset value: 0x00006400U + * + * The RNG Frequency Count Maximum Limit Register defines the maximum allowable + * count taken by the Entropy sample counter during each Entropy sample. During + * any sample period, if the count is greater than this programmed maximum, a + * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated. Note + * that this address (061C) is used as FRQMAX only if MCTL[PRGM] is 1. If + * MCTL[PRGM] is 0, this address is used as FRQCNT readback register. + */ +/*! + * @name Constants and macros for entire TRNG_FRQMAX register + */ +/*@{*/ +#define TRNG_FRQMAX_REG(base) ((base)->FRQMAX) +#define TRNG_RD_FRQMAX(base) (TRNG_FRQMAX_REG(base)) +#define TRNG_WR_FRQMAX(base, value) (TRNG_FRQMAX_REG(base) = (value)) +#define TRNG_RMW_FRQMAX(base, mask, value) (TRNG_WR_FRQMAX(base, (TRNG_RD_FRQMAX(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_FRQMAX bitfields + */ + +/*! + * @name Register TRNG_FRQMAX, field FRQ_MAX[21:0] (RW) + * + * Frequency Counter Maximum Limit. Defines the maximum allowable count taken + * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1. + * This register is cleared to 000640h by writing the MCTL[RST_DEF] bit to 1. + * Note that if MCTL[PRGM] bit is 0, this register address is used to read the + * Frequency Count result in register FRQCNT, as defined in the following section. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_FRQMAX_FRQ_MAX field. */ +#define TRNG_RD_FRQMAX_FRQ_MAX(base) ((TRNG_FRQMAX_REG(base) & TRNG_FRQMAX_FRQ_MAX_MASK) >> TRNG_FRQMAX_FRQ_MAX_SHIFT) + +/*! @brief Set the FRQ_MAX field to a new value. */ +#define TRNG_WR_FRQMAX_FRQ_MAX(base, value) \ + (TRNG_RMW_FRQMAX(base, TRNG_FRQMAX_FRQ_MAX_MASK, TRNG_FRQMAX_FRQ_MAX(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register (RW) + * + * Reset value: 0x00000640U + * + * The RNG Frequency Count Minimum Limit Register defines the minimum allowable + * count taken by the Entropy sample counter during each Entropy sample. During + * any sample period, if the count is less than this programmed minimum, a + * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated. + */ +/*! + * @name Constants and macros for entire TRNG_FRQMIN register + */ +/*@{*/ +#define TRNG_FRQMIN_REG(base) ((base)->FRQMIN) +#define TRNG_RD_FRQMIN(base) (TRNG_FRQMIN_REG(base)) +#define TRNG_WR_FRQMIN(base, value) (TRNG_FRQMIN_REG(base) = (value)) +#define TRNG_RMW_FRQMIN(base, mask, value) (TRNG_WR_FRQMIN(base, (TRNG_RD_FRQMIN(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_FRQMIN bitfields + */ + +/*! + * @name Register TRNG_FRQMIN, field FRQ_MIN[21:0] (RW) + * + * Frequency Count Minimum Limit. Defines the minimum allowable count taken + * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1. + * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 0000h64 + * by writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_FRQMIN_FRQ_MIN field. */ +#define TRNG_RD_FRQMIN_FRQ_MIN(base) ((TRNG_FRQMIN_REG(base) & TRNG_FRQMIN_FRQ_MIN_MASK) >> TRNG_FRQMIN_FRQ_MIN_SHIFT) + +/*! @brief Set the FRQ_MIN field to a new value. */ +#define TRNG_WR_FRQMIN_FRQ_MIN(base, value) \ + (TRNG_RMW_FRQMIN(base, TRNG_FRQMIN_FRQ_MIN_MASK, TRNG_FRQMIN_FRQ_MIN(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_MCTL - RNG Miscellaneous Control Register + ******************************************************************************/ + +/*! + * @brief TRNG_MCTL - RNG Miscellaneous Control Register (RW) + * + * Reset value: 0x00012001U + * + * This register is intended to be used for programming, configuring and testing + * the RNG. It is the main register to read/write, in order to enable Entropy + * generation, to stop entropy generation and to block access to entropy registers. + * This is done via the special TRNG_ACC and PRGM bits below. The RNG + * Miscellaneous Control Register is a read/write register used to control the RNG's True + * Random Number Generator (TRNG) access, operation and test. Note that in many + * cases two RNG registers share the same address, and a particular register at the + * shared address is selected based upon the value in the PRGM field of the MCTL + * register. + */ +/*! + * @name Constants and macros for entire TRNG_MCTL register + */ +/*@{*/ +#define TRNG_MCTL_REG(base) ((base)->MCTL) +#define TRNG_RD_MCTL(base) (TRNG_MCTL_REG(base)) +#define TRNG_WR_MCTL(base, value) (TRNG_MCTL_REG(base) = (value)) +#define TRNG_RMW_MCTL(base, mask, value) (TRNG_WR_MCTL(base, (TRNG_RD_MCTL(base) & ~(mask)) | (value))) +/*@}*/ + +/*! + * @name Register TRNG_MCTL, field FOR_SCLK[7] (RW) + * + * Force System Clock. If set, the system clock is used to operate the TRNG, + * instead of the ring oscillator. This is for test use only, and indeterminate + * results may occur. This bit is writable only if PRGM bit is 1, or PRGM bit is + * being written to 1 simultaneously to writing this bit. This bit is cleared by + * writing the RST_DEF bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_MCTL_FOR_SCLK field. */ +#define TRNG_RD_MCTL_FOR_SCLK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_FOR_SCLK_MASK) >> TRNG_MCTL_FOR_SCLK_SHIFT) + +/*! @brief Set the FOR_SCLK field to a new value. */ +#define TRNG_WR_MCTL_FOR_SCLK(base, value) \ + (TRNG_RMW_MCTL(base, (TRNG_MCTL_FOR_SCLK_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_FOR_SCLK(value))) +/*@}*/ + +/*! + * @name Register TRNG_MCTL, field OSC_DIV[3:2] (RW) + * + * Oscillator Divide. Determines the amount of dividing done to the ring + * oscillator before it is used by the TRNG.This field is writable only if PRGM bit is + * 1, or PRGM bit is being written to 1 simultaneously to writing this field. This + * field is cleared to 00 by writing the RST_DEF bit to 1. + * + * Values: + * - 0b00 - use ring oscillator with no divide + * - 0b01 - use ring oscillator divided-by-2 + * - 0b10 - use ring oscillator divided-by-4 + * - 0b11 - use ring oscillator divided-by-8 + */ +/*@{*/ +/*! @brief Read current value of the TRNG_MCTL_OSC_DIV field. */ +#define TRNG_RD_MCTL_OSC_DIV(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_OSC_DIV_MASK) >> TRNG_MCTL_OSC_DIV_SHIFT) + +/*! @brief Set the OSC_DIV field to a new value. */ +#define TRNG_WR_MCTL_OSC_DIV(base, value) \ + (TRNG_RMW_MCTL(base, (TRNG_MCTL_OSC_DIV_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_OSC_DIV(value))) +/*@}*/ + +/*! + * @name Register TRNG_MCTL, field SAMP_MODE[1:0] (RW) + * + * Sample Mode. Determines the method of sampling the ring oscillator while + * generating the Entropy value:This field is writable only if PRGM bit is 1, or PRGM + * bit is being written to 1 simultaneously with writing this field. This field + * is cleared to 01 by writing the RST_DEF bit to 1. + * + * Values: + * - 0b00 - use Von Neumann data into both Entropy shifter and Statistical + * Checker + * - 0b01 - use raw data into both Entropy shifter and Statistical Checker + * - 0b10 - use Von Neumann data into Entropy shifter. Use raw data into + * Statistical Checker + * - 0b11 - reserved. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_MCTL_SAMP_MODE field. */ +#define TRNG_RD_MCTL_SAMP_MODE(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_SAMP_MODE_MASK) >> TRNG_MCTL_SAMP_MODE_SHIFT) + +/*! @brief Set the SAMP_MODE field to a new value. */ +#define TRNG_WR_MCTL_SAMP_MODE(base, value) \ + (TRNG_RMW_MCTL(base, (TRNG_MCTL_SAMP_MODE_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_SAMP_MODE(value))) +/*@}*/ + +/*! + * @name Register TRNG_MCTL, field PRGM[16] (RW) + * + * Programming Mode Select. When this bit is 1, the TRNG is in Program Mode, + * otherwise it is in Run Mode. No Entropy value will be generated while the TRNG is + * in Program Mode. Note that different RNG registers are accessible at the same + * address depending on whether PRGM is set to 1 or 0. This is noted in the RNG + * register descriptions. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_MCTL_PRGM field. */ +#define TRNG_RD_MCTL_PRGM(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_PRGM_MASK) >> TRNG_MCTL_PRGM_SHIFT) + +/*! @brief Set the PRGM field to a new value. */ +#define TRNG_WR_MCTL_PRGM(base, value) \ + (TRNG_RMW_MCTL(base, (TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_PRGM(value))) +/*@}*/ + +/*! + * @name Register TRNG_MCTL, field RST_DEF[6] (WO) + * + * Reset Defaults. Writing a 1 to this bit clears various TRNG registers, and + * bits within registers, to their default state. This bit is writable only if PRGM + * bit is 1, or PRGM bit is being written to 1 simultaneously to writing this + * bit. Reading this bit always produces a 0. + */ +/*@{*/ +/*! @brief Set the RST_DEF field to a new value. */ +#define TRNG_WR_MCTL_RST_DEF(base, value) \ + (TRNG_RMW_MCTL(base, (TRNG_MCTL_RST_DEF_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_RST_DEF(value))) +/*@}*/ + +#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC > 0)) +/*! + * @name Register TRNG_MCTL, field TRNG_ACC[5] (RW) + * + * TRNG Access Mode. If this bit is set to 1, the TRNG will generate an Entropy + * value that can be read via the ENT0-ENT15 registers. The Entropy value may be + * read once the ENT VAL bit is asserted. Also see ENTa register descriptions + * (For a = 0 to 15). + */ +/*@{*/ +/*! @brief Read current value of the TRNG_MCTL_TRNG_ACC field. */ +#define TRNG_RD_MCTL_TRNG_ACC(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TRNG_ACC_MASK) >> TRNG_MCTL_TRNG_ACC_SHIFT) + +/*! @brief Set the TRNG_ACC field to a new value. */ +#define TRNG_WR_MCTL_TRNG_ACC(base, value) \ + (TRNG_RMW_MCTL(base, (TRNG_MCTL_TRNG_ACC_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_TRNG_ACC(value))) +/*@}*/ +#endif + +/*! + * @name Register TRNG_MCTL, field TSTOP_OK[13] (RO) + * + * TRNG_OK_TO_STOP. Software should check that this bit is a 1 before + * transitioning RNG to low power mode (RNG clock stopped). RNG turns on the TRNG + * free-running ring oscillator whenever new entropy is being generated and turns off the + * ring oscillator when entropy generation is complete. If the RNG clock is + * stopped while the TRNG ring oscillator is running, the oscillator will continue + * running even though the RNG clock is stopped. TSTOP_OK is asserted when the TRNG + * ring oscillator is not running. and therefore it is ok to stop the RNG clock. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_MCTL_TSTOP_OK field. */ +#define TRNG_RD_MCTL_TSTOP_OK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TSTOP_OK_MASK) >> TRNG_MCTL_TSTOP_OK_SHIFT) +/*@}*/ + +/*! + * @name Register TRNG_MCTL, field ENT_VAL[10] (RO) + * + * Read only: Entropy Valid. Will assert only if TRNG ACC bit is set, and then + * after an entropy value is generated. Will be cleared when ENT15 is read. (ENT0 + * through ENT14 should be read before reading ENT15). + */ +/*@{*/ +/*! @brief Read current value of the TRNG_MCTL_ENT_VAL field. */ +#define TRNG_RD_MCTL_ENT_VAL(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ENT_VAL_MASK) >> TRNG_MCTL_ENT_VAL_SHIFT) +/*@}*/ + +/*! + * @name Register TRNG_MCTL, field ERR[12] (W1C) + * + * Read: Error status. 1 = error detected. 0 = no error.Write: Write 1 to clear + * errors. Writing 0 has no effect. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_MCTL_ERR field. */ +#define TRNG_RD_MCTL_ERR(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ERR_MASK) >> TRNG_MCTL_ERR_SHIFT) + +/*! @brief Set the ERR field to a new value. */ +#define TRNG_WR_MCTL_ERR(base, value) (TRNG_RMW_MCTL(base, TRNG_MCTL_ERR_MASK, TRNG_MCTL_ERR(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SDCTL - RNG Seed Control Register + ******************************************************************************/ + +/*! + * @brief TRNG_SDCTL - RNG Seed Control Register (RW) + * + * Reset value: 0x0C8009C4U + * + * The RNG Seed Control Register contains two fields. One field defines the + * length (in system clocks) of each Entropy sample (ENT_DLY), and the other field + * indicates the number of samples that will taken during each TRNG Entropy + * generation (SAMP_SIZE). + */ +/*! + * @name Constants and macros for entire TRNG_SDCTL register + */ +/*@{*/ +#define TRNG_SDCTL_REG(base) ((base)->SDCTL) +#define TRNG_RD_SDCTL(base) (TRNG_SDCTL_REG(base)) +#define TRNG_WR_SDCTL(base, value) (TRNG_SDCTL_REG(base) = (value)) +#define TRNG_RMW_SDCTL(base, mask, value) (TRNG_WR_SDCTL(base, (TRNG_RD_SDCTL(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_SDCTL bitfields + */ + +/*! + * @name Register TRNG_SDCTL, field SAMP_SIZE[15:0] (RW) + * + * Sample Size. Defines the total number of Entropy samples that will be taken + * during Entropy generation. This field is writable only if MCTL[PRGM] bit is 1. + * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 09C4h + * (decimal 2500) by writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SDCTL_SAMP_SIZE field. */ +#define TRNG_RD_SDCTL_SAMP_SIZE(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_SAMP_SIZE_MASK) >> TRNG_SDCTL_SAMP_SIZE_SHIFT) + +/*! @brief Set the SAMP_SIZE field to a new value. */ +#define TRNG_WR_SDCTL_SAMP_SIZE(base, value) \ + (TRNG_RMW_SDCTL(base, TRNG_SDCTL_SAMP_SIZE_MASK, TRNG_SDCTL_SAMP_SIZE(value))) +/*@}*/ + +/*! + * @name Register TRNG_SDCTL, field ENT_DLY[31:16] (RW) + * + * Entropy Delay. Defines the length (in system clocks) of each Entropy sample + * taken. This field is writable only if MCTL[PRGM] bit is 1. This field will read + * zeroes if MCTL[PRGM] = 0. This field is cleared to 0C80h (decimal 3200) by + * writing the MCTL[RST_DEF] bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SDCTL_ENT_DLY field. */ +#define TRNG_RD_SDCTL_ENT_DLY(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_ENT_DLY_MASK) >> TRNG_SDCTL_ENT_DLY_SHIFT) + +/*! @brief Set the ENT_DLY field to a new value. */ +#define TRNG_WR_SDCTL_ENT_DLY(base, value) (TRNG_RMW_SDCTL(base, TRNG_SDCTL_ENT_DLY_MASK, TRNG_SDCTL_ENT_DLY(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SBLIM - RNG Sparse Bit Limit Register + ******************************************************************************/ + +/*! + * @brief TRNG_SBLIM - RNG Sparse Bit Limit Register (RW) + * + * Reset value: 0x0000003FU + * + * The RNG Sparse Bit Limit Register is used when Von Neumann sampling is + * selected during Entropy Generation. It defines the maximum number of consecutive Von + * Neumann samples which may be discarded before an error is generated. Note + * that this address (0xBASE_0614) is used as SBLIM only if MCTL[PRGM] is 1. If + * MCTL[PRGM] is 0, this address is used as TOTSAM readback register. + */ +/*! + * @name Constants and macros for entire TRNG_SBLIM register + */ +/*@{*/ +#define TRNG_SBLIM_REG(base) ((base)->SBLIM) +#define TRNG_RD_SBLIM(base) (TRNG_SBLIM_REG(base)) +#define TRNG_WR_SBLIM(base, value) (TRNG_SBLIM_REG(base) = (value)) +#define TRNG_RMW_SBLIM(base, mask, value) (TRNG_WR_SBLIM(base, (TRNG_RD_SBLIM(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_SBLIM bitfields + */ + +/*! + * @name Register TRNG_SBLIM, field SB_LIM[9:0] (RW) + * + * Sparse Bit Limit. During Von Neumann sampling (if enabled by MCTL[SAMP_MODE], + * samples are discarded if two consecutive raw samples are both 0 or both 1. If + * this discarding occurs for a long period of time, it indicates that there is + * insufficient Entropy. The Sparse Bit Limit defines the maximum number of + * consecutive samples that may be discarded before an error is generated. This field + * is writable only if MCTL[PRGM] bit is 1. This register is cleared to 03hF by + * writing the MCTL[RST_DEF] bit to 1. Note that if MCTL[PRGM] bit is 0, this + * register address is used to read the Total Samples count in register TOTSAM, as + * defined in the following section. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SBLIM_SB_LIM field. */ +#define TRNG_RD_SBLIM_SB_LIM(base) ((TRNG_SBLIM_REG(base) & TRNG_SBLIM_SB_LIM_MASK) >> TRNG_SBLIM_SB_LIM_SHIFT) + +/*! @brief Set the SB_LIM field to a new value. */ +#define TRNG_WR_SBLIM_SB_LIM(base, value) (TRNG_RMW_SBLIM(base, TRNG_SBLIM_SB_LIM_MASK, TRNG_SBLIM_SB_LIM(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register + ******************************************************************************/ + +/*! + * @brief TRNG_SCMISC - RNG Statistical Check Miscellaneous Register (RW) + * + * Reset value: 0x0001001FU + * + * The RNG Statistical Check Miscellaneous Register contains the Long Run + * Maximum Limit value and the Retry Count value. This register is accessible only when + * the MCTL[PRGM] bit is 1, otherwise this register will read zeroes, and cannot + * be written. + */ +/*! + * @name Constants and macros for entire TRNG_SCMISC register + */ +/*@{*/ +#define TRNG_SCMISC_REG(base) ((base)->SCMISC) +#define TRNG_RD_SCMISC(base) (TRNG_SCMISC_REG(base)) +#define TRNG_WR_SCMISC(base, value) (TRNG_SCMISC_REG(base) = (value)) +#define TRNG_RMW_SCMISC(base, mask, value) (TRNG_WR_SCMISC(base, (TRNG_RD_SCMISC(base) & ~(mask)) | (value))) +/*@}*/ + +/* + * Constants & macros for individual TRNG_SCMISC bitfields + */ + +/*! + * @name Register TRNG_SCMISC, field LRUN_MAX[7:0] (RW) + * + * LONG RUN MAX LIMIT. This value is the largest allowable number of consecutive + * samples of all 1, or all 0, that is allowed during the Entropy generation. + * This field is writable only if MCTL[PRGM] bit is 1. This field will read zeroes + * if MCTL[PRGM] = 0. This field is cleared to 22h by writing the MCTL[RST_DEF] + * bit to 1. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SCMISC_LRUN_MAX field. */ +#define TRNG_RD_SCMISC_LRUN_MAX(base) \ + ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_LRUN_MAX_MASK) >> TRNG_SCMISC_LRUN_MAX_SHIFT) + +/*! @brief Set the LRUN_MAX field to a new value. */ +#define TRNG_WR_SCMISC_LRUN_MAX(base, value) \ + (TRNG_RMW_SCMISC(base, TRNG_SCMISC_LRUN_MAX_MASK, TRNG_SCMISC_LRUN_MAX(value))) +/*@}*/ + +/******************************************************************************* + * TRNG_ENT - RNG TRNG Entropy Read Register + ******************************************************************************/ + +/*! + * @brief TRNG_ENT - RNG TRNG Entropy Read Register (RO) + * + * Reset value: 0x00000000U + * + * The RNG TRNG can be programmed to generate an entropy value that is readable + * via the SkyBlue bus. To do this, set the MCTL[TRNG_ACC] bit to 1. Once the + * entropy value has been generated, the MCTL[ENT_VAL] bit will be set to 1. At this + * point, ENT0 through ENT15 may be read to retrieve the 512-bit entropy value. + * Note that once ENT15 is read, the entropy value will be cleared and a new + * value will begin generation, so it is important that ENT15 be read last. These + * registers are readable only when MCTL[PRGM] = 0 (Run Mode), MCTL[TRNG_ACC] = 1 + * (TRNG access mode) and MCTL[ENT_VAL] = 1, otherwise zeroes will be read. + */ +/*! + * @name Constants and macros for entire TRNG_ENT register + */ +/*@{*/ +#define TRNG_ENT_REG(base, index) ((base)->ENT[index]) +#define TRNG_RD_ENT(base, index) (TRNG_ENT_REG(base, index)) +/*@}*/ + +/******************************************************************************* + * TRNG_SEC_CFG - RNG Security Configuration Register + ******************************************************************************/ + +/*! + * @brief TRNG_SEC_CFG - RNG Security Configuration Register (RW) + * + * Reset value: 0x00000000U + * + * The RNG Security Configuration Register is a read/write register used to + * control the test mode, programmability and state modes of the RNG. Many bits are + * place holders for this version. More configurability will be added here. Clears + * on asynchronous reset. For SA-TRNG releases before 2014/July/01, offsets 0xA0 + * to 0xAC used to be 0xB0 to 0xBC respectively. So, update newer tests that use + * these registers, if hard coded. + */ +/*! + * @name Constants and macros for entire TRNG_SEC_CFG register + */ +/*@{*/ +#define TRNG_SEC_CFG_REG(base) ((base)->SEC_CFG) +#define TRNG_RD_SEC_CFG(base) (TRNG_SEC_CFG_REG(base)) +#define TRNG_WR_SEC_CFG(base, value) (TRNG_SEC_CFG_REG(base) = (value)) +#define TRNG_RMW_SEC_CFG(base, mask, value) (TRNG_WR_SEC_CFG(base, (TRNG_RD_SEC_CFG(base) & ~(mask)) | (value))) +/*@}*/ + +/*! + * @name Register TRNG_SEC_CFG, field NO_PRGM[1] (RW) + * + * If set the TRNG registers cannot be programmed. That is, regardless of the + * TRNG access mode in the SA-TRNG Miscellaneous Control Register. + * + * Values: + * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous + * Control Register's access mode bit. + * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents + * TRNG register programming. + */ +/*@{*/ +/*! @brief Read current value of the TRNG_SEC_CFG_NO_PRGM field. */ +#define TRNG_RD_SEC_CFG_NO_PRGM(base) \ + ((TRNG_SEC_CFG_REG(base) & TRNG_SEC_CFG_NO_PRGM_MASK) >> TRNG_SEC_CFG_NO_PRGM_SHIFT) + +/*! @brief Set the NO_PRGM field to a new value. */ +#define TRNG_WR_SEC_CFG_NO_PRGM(base, value) \ + (TRNG_RMW_SEC_CFG(base, TRNG_SEC_CFG_NO_PRGM_MASK, TRNG_SEC_CFG_NO_PRGM(value))) +/*@}*/ + +/*! @brief Array to map TRNG instance number to base pointer. */ +static TRNG_Type *const s_trngBases[] = TRNG_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Clock array name */ +static const clock_ip_name_t s_trngClock[] = TRNG_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Prototypes + *******************************************************************************/ +static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig); +static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count); +static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base, + trng_statistical_check_t statistical_check, + const trng_statistical_check_limit_t *limit); +static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index); +static uint32_t trng_GetInstance(TRNG_Type *base); + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t trng_GetInstance(TRNG_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_trngBases); instance++) + { + if (s_trngBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_trngBases)); + + return instance; +} + +/*FUNCTION********************************************************************* + * + * Function Name : TRNG_InitUserConfigDefault + * Description : Initializes user configuration structure to default settings. + * + *END*************************************************************************/ +/*! + * brief Initializes the user configuration structure to default values. + * + * This function initializes the configuration structure to default values. The default + * values are as follows. + * code + * user_config->lock = 0; + * user_config->clockMode = kTRNG_ClockModeRingOscillator; + * user_config->ringOscDiv = kTRNG_RingOscDiv0; Or to other kTRNG_RingOscDiv[2|8] depending on the platform. + * user_config->sampleMode = kTRNG_SampleModeRaw; + * user_config->entropyDelay = 3200; + * user_config->sampleSize = 2500; + * user_config->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT; + * user_config->retryCount = 63; + * user_config->longRunMaxLimit = 34; + * user_config->monobitLimit.maximum = 1384; + * user_config->monobitLimit.minimum = 1116; + * user_config->runBit1Limit.maximum = 405; + * user_config->runBit1Limit.minimum = 227; + * user_config->runBit2Limit.maximum = 220; + * user_config->runBit2Limit.minimum = 98; + * user_config->runBit3Limit.maximum = 125; + * user_config->runBit3Limit.minimum = 37; + * user_config->runBit4Limit.maximum = 75; + * user_config->runBit4Limit.minimum = 11; + * user_config->runBit5Limit.maximum = 47; + * user_config->runBit5Limit.minimum = 1; + * user_config->runBit6PlusLimit.maximum = 47; + * user_config->runBit6PlusLimit.minimum = 1; + * user_config->pokerLimit.maximum = 26912; + * user_config->pokerLimit.minimum = 24445; + * user_config->frequencyCountLimit.maximum = 25600; + * user_config->frequencyCountLimit.minimum = 1600; + * endcode + * + * param user_config User configuration structure. + * return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error. + */ +status_t TRNG_GetDefaultConfig(trng_config_t *userConfig) +{ + status_t result; + + if (userConfig != NULL) + { + userConfig->lock = (bool)TRNG_USER_CONFIG_DEFAULT_LOCK; + userConfig->clockMode = kTRNG_ClockModeRingOscillator; + userConfig->ringOscDiv = TRNG_USER_CONFIG_DEFAULT_OSC_DIV; + userConfig->sampleMode = kTRNG_SampleModeRaw; + userConfig->entropyDelay = TRNG_USER_CONFIG_DEFAULT_ENTROPY_DELAY; + userConfig->sampleSize = TRNG_USER_CONFIG_DEFAULT_SAMPLE_SIZE; + userConfig->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT; + + /* Statistical Check Parameters.*/ + userConfig->retryCount = TRNG_USER_CONFIG_DEFAULT_RETRY_COUNT; + userConfig->longRunMaxLimit = TRNG_USER_CONFIG_DEFAULT_RUN_MAX_LIMIT; + + userConfig->monobitLimit.maximum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MAXIMUM; + userConfig->monobitLimit.minimum = TRNG_USER_CONFIG_DEFAULT_MONOBIT_MINIMUM; + userConfig->runBit1Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MAXIMUM; + userConfig->runBit1Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT1_MINIMUM; + userConfig->runBit2Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MAXIMUM; + userConfig->runBit2Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT2_MINIMUM; + userConfig->runBit3Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MAXIMUM; + userConfig->runBit3Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT3_MINIMUM; + userConfig->runBit4Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MAXIMUM; + userConfig->runBit4Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT4_MINIMUM; + userConfig->runBit5Limit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MAXIMUM; + userConfig->runBit5Limit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT5_MINIMUM; + userConfig->runBit6PlusLimit.maximum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MAXIMUM; + userConfig->runBit6PlusLimit.minimum = TRNG_USER_CONFIG_DEFAULT_RUNBIT6PLUS_MINIMUM; + userConfig->pokerLimit.maximum = TRNG_USER_CONFIG_DEFAULT_POKER_MAXIMUM; + userConfig->pokerLimit.minimum = TRNG_USER_CONFIG_DEFAULT_POKER_MINIMUM; + userConfig->frequencyCountLimit.maximum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MAXIMUM; + userConfig->frequencyCountLimit.minimum = TRNG_USER_CONFIG_DEFAULT_FREQUENCY_MINIMUM; + + result = kStatus_Success; + } + else + { + result = kStatus_InvalidArgument; + } + + return result; +} + +/*! + * @brief Sets the TRNG retry count. + * + * This function sets the retry counter which defines the number of times a + * statistical check may fails during the TRNG Entropy Generation before + * generating an error. + */ +static status_t trng_SetRetryCount(TRNG_Type *base, uint8_t retry_count) +{ + status_t status; + + if ((retry_count >= 1u) && (retry_count <= 15u)) + { + /* Set retry count.*/ + TRNG_WR_SCMISC_RTY_CT(base, retry_count); + status = kStatus_Success; + } + else + { + status = kStatus_InvalidArgument; + } + return status; +} + +/*! + * @brief Sets statistical check limits. + * + * This function is used to set minimum and maximum limits of statistical checks. + * + */ +static status_t trng_SetStatisticalCheckLimit(TRNG_Type *base, + trng_statistical_check_t statistical_check, + const trng_statistical_check_limit_t *limit) +{ + uint32_t range; + status_t status = kStatus_Success; + + if ((NULL != limit) && (limit->maximum > limit->minimum)) + { + range = limit->maximum - limit->minimum; /* Registers use range instead of minimum value.*/ + + if (statistical_check == kTRNG_StatisticalCheckMonobit) /* Allowable maximum and minimum number of ones/zero + detected during entropy generation. */ + { + if ((range <= 0xffffu) && (limit->maximum <= 0xffffu)) + { + TRNG_WR_SCML_MONO_MAX(base, limit->maximum); + TRNG_WR_SCML_MONO_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + } + else if (statistical_check == kTRNG_StatisticalCheckRunBit1) /* Allowable maximum and minimum number of runs of + length 1 detected during entropy generation. */ + { + if ((range <= 0x7fffu) && (limit->maximum <= 0x7fffu)) + { + TRNG_WR_SCR1L_RUN1_MAX(base, limit->maximum); + TRNG_WR_SCR1L_RUN1_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + } + else if (statistical_check == kTRNG_StatisticalCheckRunBit2) /* Allowable maximum and minimum number of runs of + length 2 detected during entropy generation. */ + { + if ((range <= 0x3fffu) && (limit->maximum <= 0x3fffu)) + { + TRNG_WR_SCR2L_RUN2_MAX(base, limit->maximum); + TRNG_WR_SCR2L_RUN2_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + } + else if (statistical_check == kTRNG_StatisticalCheckRunBit3) /* Allowable maximum and minimum number of runs of + length 3 detected during entropy generation. */ + { + if ((range <= 0x1fffu) && (limit->maximum <= 0x1fffu)) + { + TRNG_WR_SCR3L_RUN3_MAX(base, limit->maximum); + TRNG_WR_SCR3L_RUN3_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + } + else if (statistical_check == kTRNG_StatisticalCheckRunBit4) /* Allowable maximum and minimum number of runs of + length 4 detected during entropy generation. */ + { + if ((range <= 0xfffu) && (limit->maximum <= 0xfffu)) + { + TRNG_WR_SCR4L_RUN4_MAX(base, limit->maximum); + TRNG_WR_SCR4L_RUN4_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + } + else if (statistical_check == kTRNG_StatisticalCheckRunBit5) /* Allowable maximum and minimum number of runs of + length 5 detected during entropy generation. */ + { + if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu)) + { + TRNG_WR_SCR5L_RUN5_MAX(base, limit->maximum); + TRNG_WR_SCR5L_RUN5_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + } + else if (statistical_check == kTRNG_StatisticalCheckRunBit6Plus) /* Allowable maximum and minimum number of + length 6 or more detected during entropy + generation */ + { + if ((range <= 0x7ffu) && (limit->maximum <= 0x7ffu)) + { + TRNG_WR_SCR6PL_RUN6P_MAX(base, limit->maximum); + TRNG_WR_SCR6PL_RUN6P_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + } + else if (statistical_check == kTRNG_StatisticalCheckPoker) /* Allowable maximum and minimum limit of "Poker + Test" detected during entropy generation . */ + { + if ((range <= 0xffffu) && (limit->maximum <= 0xffffffu)) + { + TRNG_WR_PKRMAX_PKR_MAX(base, limit->maximum); + TRNG_WR_PKRRNG_PKR_RNG(base, range); + } + else + { + status = kStatus_InvalidArgument; + } + } + else if (statistical_check == kTRNG_StatisticalCheckFrequencyCount) /* Allowable maximum and minimum limit of + entropy sample frquency count during + entropy generation . */ + { + if ((limit->minimum <= 0x3fffffu) && (limit->maximum <= 0x3fffffu)) + { + TRNG_WR_FRQMAX_FRQ_MAX(base, limit->maximum); + TRNG_WR_FRQMIN_FRQ_MIN(base, limit->minimum); + } + else + { + status = kStatus_InvalidArgument; + } + } + else + { + status = kStatus_InvalidArgument; + } + } + + return status; +} + +/*FUNCTION********************************************************************* + * + * Function Name : trng_ApplyUserConfig + * Description : Apply user configuration settings to TRNG module. + * + *END*************************************************************************/ +static status_t trng_ApplyUserConfig(TRNG_Type *base, const trng_config_t *userConfig) +{ + status_t status; + + status = trng_SetRetryCount(base, userConfig->retryCount); + if (kStatus_Success != status) + { + return status; + } + + status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckMonobit, &userConfig->monobitLimit); + if (kStatus_Success != status) + { + return status; + } + + status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit1, &userConfig->runBit1Limit); + if (kStatus_Success != status) + { + return status; + } + + status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit2, &userConfig->runBit2Limit); + if (kStatus_Success != status) + { + return status; + } + + status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit3, &userConfig->runBit3Limit); + if (kStatus_Success != status) + { + return status; + } + + status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit4, &userConfig->runBit4Limit); + if (kStatus_Success != status) + { + return status; + } + + status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit5, &userConfig->runBit5Limit); + if (kStatus_Success != status) + { + return status; + } + + status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckRunBit6Plus, &userConfig->runBit6PlusLimit); + if (kStatus_Success != status) + { + return status; + } + + status = trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckPoker, &userConfig->pokerLimit); + if (kStatus_Success != status) + { + return status; + } + + status = + trng_SetStatisticalCheckLimit(base, kTRNG_StatisticalCheckFrequencyCount, &userConfig->frequencyCountLimit); + if (kStatus_Success != status) + { + return status; + } + + TRNG_WR_MCTL_FOR_SCLK(base, userConfig->clockMode); + TRNG_WR_MCTL_OSC_DIV(base, userConfig->ringOscDiv); + TRNG_WR_MCTL_SAMP_MODE(base, userConfig->sampleMode); + TRNG_WR_SDCTL_ENT_DLY(base, userConfig->entropyDelay); + TRNG_WR_SDCTL_SAMP_SIZE(base, userConfig->sampleSize); + TRNG_WR_SBLIM_SB_LIM(base, userConfig->sparseBitLimit); + TRNG_WR_SCMISC_LRUN_MAX(base, userConfig->longRunMaxLimit); + + return status; +} + +/*! + * @brief Gets a entry data from the TRNG. + * + * This function gets an entropy data from TRNG. + * Entropy data is spread over TRNG_ENT_COUNT registers. + * Read register number is defined by index parameter. + */ +static uint32_t trng_ReadEntropy(TRNG_Type *base, uint32_t index) +{ + uint32_t data; + + index = index % TRNG_ENT_COUNT; /* This way we can use incremental index without limit control from application.*/ + + data = TRNG_RD_ENT(base, index); + + if (index == (TRNG_ENT_COUNT - 1u)) + { + /* Dummy read. Defect workaround. + * TRNG could not clear ENT_VAL flag automatically, application + * had to do a dummy reading operation for anyone TRNG register + * to clear it firstly, then to read the RTENT0 to RTENT15 again */ + index = TRNG_RD_ENT(base, 0); + } + + return data; +} + +/*! + * brief Initializes the TRNG. + * + * This function initializes the TRNG. + * When called, the TRNG entropy generation starts immediately. + * + * param base TRNG base address + * param userConfig Pointer to the initialization configuration structure. + * return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error. + */ +status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig) +{ + status_t result; + + /* Check input parameters.*/ + if ((base != NULL) && (userConfig != NULL)) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock gate. */ + CLOCK_EnableClock(s_trngClock[trng_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset the registers of TRNG module to reset state. */ + /* Must be in program mode.*/ + TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram); + /* Reset Defaults.*/ + TRNG_WR_MCTL_RST_DEF(base, 1); + + /* Set configuration.*/ + if ((result = trng_ApplyUserConfig(base, userConfig)) == kStatus_Success) + { + /* Start entropy generation.*/ + /* Set to Run mode.*/ + TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeRun); +#if !(defined(FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC) && (FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC > 0)) + /* Enable TRNG Access Mode. To generate an Entropy + * value that can be read via the true0-true15 registers.*/ + TRNG_WR_MCTL_TRNG_ACC(base, 1); +#endif /* !FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC */ + + (void)trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1u)); + + if (true == userConfig->lock) /* Disable programmability of TRNG registers. */ + { + TRNG_WR_SEC_CFG_NO_PRGM(base, 1); + } + + result = kStatus_Success; + } + } + else + { + result = kStatus_InvalidArgument; + } + + return result; +} + +/*! + * brief Shuts down the TRNG. + * + * This function shuts down the TRNG. + * + * param base TRNG base address. + */ +void TRNG_Deinit(TRNG_Type *base) +{ + /* Check input parameters.*/ + if (NULL != base) + { + /* Move to program mode. Stop entropy generation.*/ + TRNG_WR_MCTL_PRGM(base, kTRNG_WorkModeProgram); + + /* Check before clock stop. + TRNG turns on the TRNG free-running ring oscillator whenever new entropy + is being generated and turns off the ring oscillator when entropy generation + is complete. If the TRNG clock is stopped while the TRNG ring oscillator + is running, the oscillator continues running though the RNG clock. + is stopped. */ + while (TRNG_RD_MCTL_TSTOP_OK(base) == 0u) + { + } + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable Clock*/ + CLOCK_DisableClock(s_trngClock[trng_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + } +} + +/*! + * brief Gets random data. + * + * This function gets random data from the TRNG. + * + * param base TRNG base address. + * param data Pointer address used to store random data. + * param dataSize Size of the buffer pointed by the data parameter. + * return random data + */ +status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize) +{ + status_t result = kStatus_Success; + uint32_t random_32; + uint8_t *random_p; + uint32_t random_size; + uint8_t *data_p = (uint8_t *)data; + uint32_t i; + uint32_t tmpValidFlag; + uint32_t tmpErrorFlag; + + int index = 0; + + /* Check input parameters.*/ + if ((NULL != base) && (NULL != data) && (0U != dataSize)) + { + do + { + /* Wait for Valid or Error flag*/ + tmpValidFlag = TRNG_RD_MCTL_ENT_VAL(base); + tmpErrorFlag = TRNG_RD_MCTL_ERR(base); + while (tmpValidFlag == 0u && tmpErrorFlag == 0u) + { + tmpValidFlag = TRNG_RD_MCTL_ENT_VAL(base); + tmpErrorFlag = TRNG_RD_MCTL_ERR(base); + } + + /* Check HW error.*/ + if (0U != TRNG_RD_MCTL_ERR(base)) + { + result = kStatus_Fail; /* TRNG module error occurred */ + /* Clear error.*/ + TRNG_WR_MCTL_ERR(base, 1); + break; /* No sense stay here.*/ + } + + /* Read Entropy.*/ + random_32 = trng_ReadEntropy(base, (uint32_t)index++); + + random_p = (uint8_t *)&random_32; + + if (dataSize < sizeof(random_32)) + { + random_size = dataSize; + } + else + { + random_size = sizeof(random_32); + } + + for (i = 0U; i < random_size; i++) + { + *data_p++ = *random_p++; + } + + dataSize -= random_size; + } while (dataSize > 0u); + + /* Start a new entropy generation. + It is done by reading of the last entropy register.*/ + if (((unsigned)index % TRNG_ENT_COUNT) != (TRNG_ENT_COUNT - 1u)) + { + (void)trng_ReadEntropy(base, (TRNG_ENT_COUNT - 1u)); + } + } + else + { + result = kStatus_InvalidArgument; + } + + return result; +} + +#endif /* FSL_FEATURE_SOC_TRNG_COUNT */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_trng.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_trng.h new file mode 100644 index 0000000000..a2c3911428 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_trng.h @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_TRNG_DRIVER_H_ +#define _FSL_TRNG_DRIVER_H_ + +#include "fsl_common.h" + +#if defined(FSL_FEATURE_SOC_TRNG_COUNT) && FSL_FEATURE_SOC_TRNG_COUNT + +/*! + * @addtogroup trng + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief TRNG driver version 2.0.4. + * + * Current version: 2.0.4 + * + * Change log: + * - version 2.0.4 + * - Fix MISRA-2012 issues. + * - Version 2.0.3 + * - update TRNG_Init to restart entropy generation + * - Version 2.0.2 + * - fix MISRA issues + * - Version 2.0.1 + * - add support for KL8x and KL28Z + * - update default OSCDIV for K81 to divide by 2 + */ +#define FSL_TRNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*@}*/ + +/*! @brief TRNG sample mode. Used by trng_config_t. */ +typedef enum _trng_sample_mode +{ + kTRNG_SampleModeVonNeumann = 0U, /*!< Use von Neumann data in both Entropy shifter and Statistical Checker. */ + kTRNG_SampleModeRaw = 1U, /*!< Use raw data into both Entropy shifter and Statistical Checker. */ + kTRNG_SampleModeVonNeumannRaw = + 2U /*!< Use von Neumann data in Entropy shifter. Use raw data into Statistical Checker. */ +} trng_sample_mode_t; + +/*! @brief TRNG clock mode. Used by trng_config_t. */ +typedef enum _trng_clock_mode +{ + kTRNG_ClockModeRingOscillator = 0U, /*!< Ring oscillator is used to operate the TRNG (default). */ + kTRNG_ClockModeSystem = 1U /*!< System clock is used to operate the TRNG. This is for test use only, and + indeterminate results may occur. */ +} trng_clock_mode_t; + +/*! @brief TRNG ring oscillator divide. Used by trng_config_t. */ +typedef enum _trng_ring_osc_div +{ + kTRNG_RingOscDiv0 = 0U, /*!< Ring oscillator with no divide */ + kTRNG_RingOscDiv2 = 1U, /*!< Ring oscillator divided-by-2. */ + kTRNG_RingOscDiv4 = 2U, /*!< Ring oscillator divided-by-4. */ + kTRNG_RingOscDiv8 = 3U /*!< Ring oscillator divided-by-8. */ +} trng_ring_osc_div_t; + +/*! @brief Data structure for definition of statistical check limits. Used by trng_config_t. */ +typedef struct _trng_statistical_check_limit +{ + uint32_t maximum; /*!< Maximum limit.*/ + uint32_t minimum; /*!< Minimum limit.*/ +} trng_statistical_check_limit_t; + +/*! + * @brief Data structure for the TRNG initialization + * + * This structure initializes the TRNG by calling the TRNG_Init() function. + * It contains all TRNG configurations. + */ +typedef struct _trng_user_config +{ + bool lock; /*!< @brief Disable programmability of TRNG registers. */ + trng_clock_mode_t clockMode; /*!< @brief Clock mode used to operate TRNG.*/ + trng_ring_osc_div_t ringOscDiv; /*!< @brief Ring oscillator divide used by TRNG. */ + trng_sample_mode_t sampleMode; /*!< @brief Sample mode of the TRNG ring oscillator. */ + /* Seed Control*/ + uint16_t + entropyDelay; /*!< @brief Entropy Delay. Defines the length (in system clocks) of each Entropy sample taken. */ + uint16_t sampleSize; /*!< @brief Sample Size. Defines the total number of Entropy samples that will be taken during + Entropy generation. */ + uint16_t sparseBitLimit; /*!< @brief Sparse Bit Limit which defines the maximum number of + * consecutive samples that may be discarded before an error is generated. + * This limit is used only for during von Neumann sampling (enabled by + * TRNG_HAL_SetSampleMode()). Samples are discarded if two consecutive raw samples are both + * 0 or both 1. If this discarding occurs for a long period of time, it indicates that + * there is insufficient Entropy. */ + /* Statistical Check Parameters.*/ + uint8_t retryCount; /*!< @brief Retry count. It defines the number of times a statistical check may fails + * during the TRNG Entropy Generation before generating an error. */ + uint8_t longRunMaxLimit; /*!< @brief Largest allowable number of consecutive samples of all 1, or all 0, + * that is allowed during the Entropy generation. */ + trng_statistical_check_limit_t monobitLimit; /*!< @brief Maximum and minimum limits for statistical check of number + of ones/zero detected during entropy generation. */ + trng_statistical_check_limit_t runBit1Limit; /*!< @brief Maximum and minimum limits for statistical check of number + of runs of length 1 detected during entropy generation. */ + trng_statistical_check_limit_t runBit2Limit; /*!< @brief Maximum and minimum limits for statistical check of number + of runs of length 2 detected during entropy generation. */ + trng_statistical_check_limit_t runBit3Limit; /*!< @brief Maximum and minimum limits for statistical check of number + of runs of length 3 detected during entropy generation. */ + trng_statistical_check_limit_t runBit4Limit; /*!< @brief Maximum and minimum limits for statistical check of number + of runs of length 4 detected during entropy generation. */ + trng_statistical_check_limit_t runBit5Limit; /*!< @brief Maximum and minimum limits for statistical check of number + of runs of length 5 detected during entropy generation. */ + trng_statistical_check_limit_t runBit6PlusLimit; /*!< @brief Maximum and minimum limits for statistical check of + number of runs of length 6 or more detected during entropy + generation. */ + trng_statistical_check_limit_t + pokerLimit; /*!< @brief Maximum and minimum limits for statistical check of "Poker Test". */ + trng_statistical_check_limit_t frequencyCountLimit; /*!< @brief Maximum and minimum limits for statistical check of + entropy sample frequency count. */ +} trng_config_t; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes the user configuration structure to default values. + * + * This function initializes the configuration structure to default values. The default + * values are as follows. + * @code + * user_config->lock = 0; + * user_config->clockMode = kTRNG_ClockModeRingOscillator; + * user_config->ringOscDiv = kTRNG_RingOscDiv0; Or to other kTRNG_RingOscDiv[2|8] depending on the platform. + * user_config->sampleMode = kTRNG_SampleModeRaw; + * user_config->entropyDelay = 3200; + * user_config->sampleSize = 2500; + * user_config->sparseBitLimit = TRNG_USER_CONFIG_DEFAULT_SPARSE_BIT_LIMIT; + * user_config->retryCount = 63; + * user_config->longRunMaxLimit = 34; + * user_config->monobitLimit.maximum = 1384; + * user_config->monobitLimit.minimum = 1116; + * user_config->runBit1Limit.maximum = 405; + * user_config->runBit1Limit.minimum = 227; + * user_config->runBit2Limit.maximum = 220; + * user_config->runBit2Limit.minimum = 98; + * user_config->runBit3Limit.maximum = 125; + * user_config->runBit3Limit.minimum = 37; + * user_config->runBit4Limit.maximum = 75; + * user_config->runBit4Limit.minimum = 11; + * user_config->runBit5Limit.maximum = 47; + * user_config->runBit5Limit.minimum = 1; + * user_config->runBit6PlusLimit.maximum = 47; + * user_config->runBit6PlusLimit.minimum = 1; + * user_config->pokerLimit.maximum = 26912; + * user_config->pokerLimit.minimum = 24445; + * user_config->frequencyCountLimit.maximum = 25600; + * user_config->frequencyCountLimit.minimum = 1600; + * @endcode + * + * @param user_config User configuration structure. + * @return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error. + */ +status_t TRNG_GetDefaultConfig(trng_config_t *userConfig); + +/*! + * @brief Initializes the TRNG. + * + * This function initializes the TRNG. + * When called, the TRNG entropy generation starts immediately. + * + * @param base TRNG base address + * @param userConfig Pointer to the initialization configuration structure. + * @return If successful, returns the kStatus_TRNG_Success. Otherwise, it returns an error. + */ +status_t TRNG_Init(TRNG_Type *base, const trng_config_t *userConfig); + +/*! + * @brief Shuts down the TRNG. + * + * This function shuts down the TRNG. + * + * @param base TRNG base address. + */ +void TRNG_Deinit(TRNG_Type *base); + +/*! + * @brief Gets random data. + * + * This function gets random data from the TRNG. + * + * @param base TRNG base address. + * @param data Pointer address used to store random data. + * @param dataSize Size of the buffer pointed by the data parameter. + * @return random data + */ +status_t TRNG_GetRandomData(TRNG_Type *base, void *data, size_t dataSize); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_FEATURE_SOC_TRNG_COUNT */ +#endif /*_FSL_TRNG_H_*/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_tsc.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_tsc.c new file mode 100644 index 0000000000..47f52b3db0 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_tsc.c @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_tsc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.tsc" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for TSC module. + * + * @param base TSC peripheral base address + */ +static uint32_t TSC_GetInstance(TSC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to TSC bases for each instance. */ +static TSC_Type *const s_tscBases[] = TSC_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to ADC clocks for each instance. */ +static const clock_ip_name_t s_tscClocks[] = TSC_CLOCKS; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t TSC_GetInstance(TSC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_tscBases); instance++) + { + if (s_tscBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_tscBases)); + + return instance; +} + +/*! + * brief Initialize the TSC module. + * + * param base TSC peripheral base address. + * param config Pointer to "tsc_config_t" structure. + */ +void TSC_Init(TSC_Type *base, const tsc_config_t *config) +{ + assert(NULL != config); + assert(config->measureDelayTime <= 0xFFFFFFU); + + uint32_t tmp32; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the TSC clock. */ + CLOCK_EnableClock(s_tscClocks[TSC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + /* Configure TSC_BASIC_SETTING register. */ + tmp32 = TSC_BASIC_SETTING_MEASURE_DELAY_TIME(config->measureDelayTime) | + TSC_BASIC_SETTING__4_5_WIRE(config->detectionMode); + if (config->enableAutoMeasure) + { + tmp32 |= TSC_BASIC_SETTING_AUTO_MEASURE_MASK; + } + base->BASIC_SETTING = tmp32; + /* Configure TSC_PS_INPUT_BUFFER_ADDR register. */ + base->PRE_CHARGE_TIME = TSC_PRE_CHARGE_TIME_PRE_CHARGE_TIME(config->prechargeTime); +} + +/*! + * brief De-initializes the TSC module. + * + * param base TSC peripheral base address. + */ +void TSC_Deinit(TSC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the TSC clcok. */ + CLOCK_DisableClock(s_tscClocks[TSC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets an available pre-defined settings for the controller's configuration. + * + * This function initializes the converter configuration structure with available settings. + * The default values of measureDelayTime and prechargeTime is tested on LCD8000-43T screen and work normally. + * The default values are: + * code + * config->enableAutoMeausre = false; + * config->measureDelayTime = 0xFFFFU; + * config->prechargeTime = 0xFFFFU; + * config->detectionMode = kTSC_4WireDetectionMode; + * endCode + * param config Pointer to "tsc_config_t" structure. + */ +void TSC_GetDefaultConfig(tsc_config_t *config) +{ + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->enableAutoMeasure = false; + config->measureDelayTime = 0xFFFFU; + config->prechargeTime = 0xFFFFU; + config->detectionMode = kTSC_Detection4WireMode; +} + +/*! + * brief Get Y coordinate value or X coordinate value. The value is an ADC conversion value. + * + * param base TSC peripheral base address. + * param selection Select alternative measure value which is Y coordinate value or X coordinate value. + * See "tsc_corrdinate_value_selection_t". + * return If selection is "kTSC_XCoordinateValueSelection", the API returns x-coordinate vlaue. + * If selection is "kTSC_YCoordinateValueSelection", the API returns y-coordinate vlaue. + */ +uint32_t TSC_GetMeasureValue(TSC_Type *base, tsc_corrdinate_value_selection_t selection) +{ + uint32_t tmp32 = 0; + + if (selection == kTSC_XCoordinateValueSelection) + { + tmp32 = ((base->MEASEURE_VALUE) & TSC_MEASEURE_VALUE_X_VALUE_MASK) >> TSC_MEASEURE_VALUE_X_VALUE_SHIFT; + } + else if (selection == kTSC_YCoordinateValueSelection) + { + tmp32 = ((base->MEASEURE_VALUE) & TSC_MEASEURE_VALUE_Y_VALUE_MASK) >> TSC_MEASEURE_VALUE_Y_VALUE_SHIFT; + } + else + { + } + return tmp32; +} + +/*! + * brief Send hardware trigger signal to ADC in debug mode. The trigger signal must last at least 1 ips clock period. + * + * param base TSC peripheral base address. + * param hwts Hardware trigger select signal, select which channel to start conversion. See "tsc_trigger_signal_t". + * On ADC side, HWTS = 1 << x indicates the x logic channel is selected to start hardware ADC conversion. + * param enable Switcher of the trigger signal. "true" means generate trigger signal, "false" means don't generate + * trigger signal. + */ +void TSC_DebugTriggerSignalToADC(TSC_Type *base, tsc_trigger_signal_t hwts, bool enable) +{ + if (enable) + { + /* TSC_DEBUG_MODE_EXT_HWTS field should be writed before writing TSC_DEBUG_MODE_TRIGGER field. + If the two fields are writed at the same time, the trigger couldn't work as expect. */ + base->DEBUG_MODE &= ~TSC_DEBUG_MODE_EXT_HWTS_MASK; + base->DEBUG_MODE |= TSC_DEBUG_MODE_EXT_HWTS(hwts); + base->DEBUG_MODE |= TSC_DEBUG_MODE_TRIGGER_MASK; + } + else + { + base->DEBUG_MODE &= ~TSC_DEBUG_MODE_TRIGGER_MASK; + } +} + +/*! + * brief Enable/Disable detection in debug mode. + * + * param base TSC peripheral base address. + * param detectionMode Set detect mode. See "tsc_detection_mode_t" + * param enable Switcher of detect enable. "true" means enable detection, "false" means disable detection. + */ +void TSC_DebugEnableDetection(TSC_Type *base, tsc_detection_mode_t detectionMode, bool enable) +{ + if (detectionMode == kTSC_Detection4WireMode) + { + if (enable) + { + base->DEBUG_MODE2 |= TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK; + } + else + { + base->DEBUG_MODE2 &= ~TSC_DEBUG_MODE2_DETECT_ENABLE_FOUR_WIRE_MASK; + } + } + else if (detectionMode == kTSC_Detection5WireMode) + { + if (enable) + { + base->DEBUG_MODE2 |= TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK; + } + else + { + base->DEBUG_MODE2 &= ~TSC_DEBUG_MODE2_DETECT_ENABLE_FIVE_WIRE_MASK; + } + } + else + { + } +} + +/*! + * brief Set TSC port mode in debug mode.(pull down, pull up and 200k-pull up) + * + * param base TSC peripheral base address. + * param port TSC controller ports. + * param mode TSC port mode.(pull down, pull up and 200k-pull up) + */ +void TSC_DebugSetPortMode(TSC_Type *base, tsc_port_source_t port, tsc_port_mode_t mode) +{ + uint32_t tmp32; + + tmp32 = base->DEBUG_MODE2; + switch (port) + { + case kTSC_WiperPortSource: + tmp32 &= ~(TSC_DEBUG_MODE2_WIPER_200K_PULL_UP_MASK | TSC_DEBUG_MODE2_WIPER_PULL_UP_MASK | + TSC_DEBUG_MODE2_WIPER_PULL_DOWN_MASK); + tmp32 |= ((uint32_t)mode << TSC_DEBUG_MODE2_WIPER_PULL_DOWN_SHIFT); + break; + case kTSC_YnlrPortSource: + tmp32 &= ~(TSC_DEBUG_MODE2_YNLR_200K_PULL_UP_MASK | TSC_DEBUG_MODE2_YNLR_PULL_UP_MASK | + TSC_DEBUG_MODE2_YNLR_PULL_DOWN_MASK); + tmp32 |= ((uint32_t)mode << TSC_DEBUG_MODE2_YNLR_PULL_DOWN_SHIFT); + break; + case kTSC_YpllPortSource: + tmp32 &= ~(TSC_DEBUG_MODE2_YPLL_200K_PULL_UP_MASK | TSC_DEBUG_MODE2_YPLL_PULL_UP_MASK | + TSC_DEBUG_MODE2_YPLL_PULL_DOWN_MASK); + tmp32 |= ((uint32_t)mode << TSC_DEBUG_MODE2_YPLL_PULL_DOWN_SHIFT); + break; + case kTSC_XnurPortSource: + tmp32 &= ~(TSC_DEBUG_MODE2_XNUR_200K_PULL_UP_MASK | TSC_DEBUG_MODE2_XNUR_PULL_UP_MASK | + TSC_DEBUG_MODE2_XNUR_PULL_DOWN_MASK); + tmp32 |= ((uint32_t)mode << TSC_DEBUG_MODE2_XNUR_PULL_DOWN_SHIFT); + break; + case kTSC_XpulPortSource: + tmp32 &= ~(TSC_DEBUG_MODE2_XPUL_200K_PULL_UP_MASK | TSC_DEBUG_MODE2_XPUL_PULL_UP_MASK | + TSC_DEBUG_MODE2_XPUL_PULL_DOWN_MASK); + tmp32 |= ((uint32_t)mode << TSC_DEBUG_MODE2_XPUL_PULL_DOWN_SHIFT); + break; + default: + break; + } + base->DEBUG_MODE2 = tmp32; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_tsc.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_tsc.h new file mode 100644 index 0000000000..bb94af4308 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_tsc.h @@ -0,0 +1,522 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_TSC_H_ +#define _FSL_TSC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup tsc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief TSC driver version */ +#define FSL_TSC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2. */ + +/*! + * @ Controller detection mode. + */ +typedef enum _tsc_detection_mode +{ + kTSC_Detection4WireMode = 0U, /*!< 4-Wire Detection Mode. */ + kTSC_Detection5WireMode = 1U, /*!< 5-Wire Detection Mode. */ +} tsc_detection_mode_t; + +/*! + * @ Coordinate value mask. + */ +typedef enum _tsc_corrdinate_value_selection +{ + kTSC_XCoordinateValueSelection = 0U, /*!< X coordinate value is selected. */ + kTSC_YCoordinateValueSelection = 1U, /*!< Y coordinate value is selected. */ +} tsc_corrdinate_value_selection_t; + +/*! + * @ Interrupt signal enable/disable mask. + */ +enum _tsc_interrupt_signal_mask +{ + kTSC_IdleSoftwareSignalEnable = TSC_INT_SIG_EN_IDLE_SW_SIG_EN_MASK, /*!< Enable the interrupt signal when the + controller has return to idle status. + The signal is only valid after using + TSC_ReturnToIdleStatus API. */ + kTSC_ValidSignalEnable = TSC_INT_SIG_EN_VALID_SIG_EN_MASK, /*!< Enable the interrupt signal when controller receives + a detect signal after measurement. */ + kTSC_DetectSignalEnable = + TSC_INT_SIG_EN_DETECT_SIG_EN_MASK, /*!< Enable the interrupt signal when controller receives a detect signal. */ + kTSC_MeasureSignalEnable = TSC_INT_SIG_EN_MEASURE_SIG_EN_MASK, /*!< Enable the interrupt signal after the touch + detection which follows measurement. */ +}; + +/*! + * @ Interrupt enable/disable mask. + */ +enum _tsc_interrupt_mask +{ + kTSC_IdleSoftwareInterruptEnable = + TSC_INT_EN_IDLE_SW_INT_EN_MASK, /*!< Enable the interrupt when the controller has return to idle status. + The interrupt is only valid after using TSC_ReturnToIdleStatus API. */ + kTSC_DetectInterruptEnable = + TSC_INT_EN_DETECT_INT_EN_MASK, /*!< Enable the interrupt when controller receive a detect signal. */ + kTSC_MeasureInterruptEnable = TSC_INT_EN_MEASURE_INT_EN_MASK, /*!< Enable the interrupt after the touch detection + which follows measurement. */ +}; + +/*! + * @ Interrupt Status flag mask. + */ +enum _tsc_interrupt_status_flag_mask +{ + kTSC_IdleSoftwareFlag = + TSC_INT_STATUS_IDLE_SW_MASK, /*!< This flag is set if the controller has return to idle status. + The flag is only valid after using TSC_ReturnToIdleStatus API. */ + kTSC_ValidSignalFlag = + TSC_INT_STATUS_VALID_MASK, /*!< This flag is set if controller receives a detect signal after measurement. */ + kTSC_DetectSignalFlag = TSC_INT_STATUS_DETECT_MASK, /*!< This flag is set if controller receives a detect signal. */ + kTSC_MeasureSignalFlag = + TSC_INT_STATUS_MEASURE_MASK, /*!< This flag is set after the touch detection which follows measurement. + Note: Valid signal falg will be cleared along with measure signal flag. */ +}; + +/*! + * @ ADC status flag mask. + */ +enum _tsc_adc_status_flag_mask +{ + kTSC_ADCCOCOSignalFlag = + TSC_DEBUG_MODE_ADC_COCO_MASK, /*!< This signal is generated by ADC when a conversion is completed. */ + kTSC_ADCConversionValueFlag = TSC_DEBUG_MODE_ADC_CONV_VALUE_MASK, /*!< This signal is generated by ADC and indicates + the result of an ADC conversion. */ +}; + +/*! + * @ TSC status flag mask. + */ +enum _tsc_status_flag_mask +{ + kTSC_IntermediateStateFlag = TSC_DEBUG_MODE2_INTERMEDIATE_MASK, /*!< This flag is set if TSC is in intermediate + state, between two state machine states. */ + kTSC_DetectFiveWireFlag = TSC_DEBUG_MODE2_DETECT_FIVE_WIRE_MASK, /*!< This flag is set if TSC receives a 5-wire + detect signal. It is only valid when the TSC in + detect state and DETECT_ENABLE_FIVE_WIRE bit is + set. */ + kTSC_DetectFourWireFlag = TSC_DEBUG_MODE2_DETECT_FOUR_WIRE_MASK, /*!< This flag is set if TSC receives a 4-wire + detect signal. It is only valid when the TSC in + detect state and DETECT_ENABLE_FOUR_WIRE bit is + set. */ + kTSC_GlitchThresholdFlag = TSC_DEBUG_MODE2_DE_GLITCH_MASK, /*!< This field indicates glitch threshold.The threshold + is defined by number of clock cycles. See + "tsc_glitch_threshold_t". + If value = 00, Normal function: 0x1fff ipg clock + cycles, Low power mode: 0x9 low power clock cycles. + If value = 01, Normal function: 0xfff ipg clock + cycles, Low power mode: :0x7 low power clock cycles. + If value = 10, Normal function: 0x7ff ipg clock + cycles, Low power mode:0x5 low power clock cycles. + If value = 11, Normal function: 0x3 ipg clock + cycles, Low power mode:0x3 low power clock cycles. */ + kTSC_StateMachineFlag = + TSC_DEBUG_MODE2_STATE_MACHINE_MASK, /*!< This field indicates the state of TSC. See "tsc_state_machine_t"; + if value = 000, Controller is in idle state. + if value = 001, Controller is in 1st-Pre-charge state. + if value = 010, Controller is in 1st-detect state. + if value = 011, Controller is in x-measure state. + if value = 100, Controller is in y-measure state. + if value = 101, Controller is in 2nd-Pre-charge state. + if value = 110, Controller is in 2nd-detect state. */ +}; + +/*! + * @brief TSC state machine. These seven states are TSC complete workflow. + */ +typedef enum _tsc_state_machine +{ + kTSC_IdleState = 0U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in idle state. */ + kTSC_1stPreChargeState = 1U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in 1st-Pre-charge state. */ + kTSC_1stDetectState = 2U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in 1st-detect state. */ + kTSC_XMeasureState = 3U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in x-measure state. */ + kTSC_YMeasureState = 4U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in y-measure state. */ + kTSC_2ndPreChargeState = 5U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in 2nd-Pre-charge state. */ + kTSC_2ndDetectState = 6U << TSC_DEBUG_MODE2_STATE_MACHINE_SHIFT, /*!< Controller is in 2nd-detect state. */ +} tsc_state_machine_t; + +/*! + * @brief TSC glitch threshold. + */ +typedef enum _tsc_glitch_threshold +{ + kTSC_glitchThresholdALT0 = 0U << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT, /*!< Normal function: 0x1fff ipg clock cycles, Low + power mode: 0x9 low power clock cycles. */ + kTSC_glitchThresholdALT1 = 1U << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT, /*!< Normal function: 0xfff ipg clock cycles, Low + power mode: :0x7 low power clock cycles. */ + kTSC_glitchThresholdALT2 = 2U << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT, /*!< Normal function: 0x7ff ipg clock cycles, Low + power mode: :0x5 low power clock cycles. */ + kTSC_glitchThresholdALT3 = + 3U << TSC_DEBUG_MODE2_DE_GLITCH_SHIFT, /*!< Normal function: 0x3 ipg clock cycles, Low + power mode: :0x3 low power clock cycles. */ +} tsc_glitch_threshold_t; + +/*! + * @ Hardware trigger select signal, select which ADC channel to start conversion. + */ +typedef enum _tsc_trigger_signal +{ + kTSC_TriggerToChannel0 = 1U << 0U, /*!< Trigger to ADC channel0. ADC_HC0 register will be used to conversion. */ + kTSC_TriggerToChannel1 = 1U << 1U, /*!< Trigger to ADC channel1. ADC_HC1 register will be used to conversion. */ + kTSC_TriggerToChannel2 = 1U << 2U, /*!< Trigger to ADC channel2. ADC_HC2 register will be used to conversion. */ + kTSC_TriggerToChannel3 = 1U << 3U, /*!< Trigger to ADC channel3. ADC_HC3 register will be used to conversion. */ + kTSC_TriggerToChannel4 = 1U << 4U, /*!< Trigger to ADC channel4. ADC_HC4 register will be used to conversion. */ +} tsc_trigger_signal_t; + +/*! + * @ TSC controller ports. + */ +typedef enum _tsc_port_source +{ + kTSC_WiperPortSource = 0U, /*!< TSC controller wiper port. */ + kTSC_YnlrPortSource = 1U, /*!< TSC controller ynlr port. */ + kTSC_YpllPortSource = 2U, /*!< TSC controller ypll port. */ + kTSC_XnurPortSource = 3U, /*!< TSC controller xnur port. */ + kTSC_XpulPortSource = 4U, /*!< TSC controller xpul port. */ +} tsc_port_source_t; + +/*! + * @ TSC port mode. + */ +typedef enum _tsc_port_mode +{ + kTSC_PortOffMode = 0U, /*!< Disable pull up/down mode. */ + kTSC_Port200k_PullUpMode = 1U << 2U, /*!< 200k-pull up mode. */ + kTSC_PortPullUpMode = 1U << 1U, /*!< Pull up mode. */ + kTSC_PortPullDownMode = 1U << 0U, /*!< Pull down mode. */ +} tsc_port_mode_t; + +/*! + * @ Controller configuration. + */ +typedef struct _tsc_config +{ + bool enableAutoMeasure; /*!< Enable the auto-measure. It indicates after detect touch, whether automatic start + measurement */ + uint32_t measureDelayTime; /*!< Set delay time(0U~0xFFFFFFU) to even potential distribution ready.It is a + preparation for measure stage. If measure dalay time is too short, maybe it would + have an undesired effect on measure value. */ + uint32_t prechargeTime; /*!< Set pre-charge time(1U~0xFFFFFFFFU) to make the upper layer of + screen to charge to positive high. It is a preparation for detection stage. + Pre-charge time must is greater than 0U, otherwise TSC could not work normally. + If pre-charge dalay time is too short, maybe it would have an undesired effect on + generation of valid signal(kTSC_ValidSignalFlag).*/ + tsc_detection_mode_t detectionMode; /*!< Select the detection mode. See "tsc_detection_mode_t". */ +} tsc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize the TSC module. + * + * @param base TSC peripheral base address. + * @param config Pointer to "tsc_config_t" structure. + */ +void TSC_Init(TSC_Type *base, const tsc_config_t *config); + +/*! + * @brief De-initializes the TSC module. + * + * @param base TSC peripheral base address. + */ +void TSC_Deinit(TSC_Type *base); + +/*! + * @brief Gets an available pre-defined settings for the controller's configuration. + * + * This function initializes the converter configuration structure with available settings. + * The default values of measureDelayTime and prechargeTime is tested on LCD8000-43T screen and work normally. + * The default values are: + * @code + * config->enableAutoMeausre = false; + * config->measureDelayTime = 0xFFFFU; + * config->prechargeTime = 0xFFFFU; + * config->detectionMode = kTSC_4WireDetectionMode; + * @endCode + * @param config Pointer to "tsc_config_t" structure. + */ +void TSC_GetDefaultConfig(tsc_config_t *config); + +/*! + * @brief Make the TSC module return to idle status after finish the current state operation. + * Application could check TSC status to confirm that the controller has return to idle status. + * + * @param base TSC peripheral base address. + */ +static inline void TSC_ReturnToIdleStatus(TSC_Type *base) +{ + /* TSC_FLOW_CONTROL_DISABLE_MASK is a HW self-clean bit. */ + base->FLOW_CONTROL |= TSC_FLOW_CONTROL_DISABLE_MASK; +} + +/*! + * @brief Start sense detection and (if work in auto-measure mode) measure after detect a touch. + * + * @param base TSC peripheral base address. + */ +static inline void TSC_StartSenseDetection(TSC_Type *base) +{ + /* TSC_FLOW_CONTROL_START_SENSE_MASK is a HW self-clean bit. */ + base->FLOW_CONTROL |= TSC_FLOW_CONTROL_START_SENSE_MASK; +} + +/*! + * @brief start measure X/Y coordinate value after detect a touch. + * + * @param base TSC peripheral base address. + */ +static inline void TSC_StartMeasure(TSC_Type *base) +{ + /* TSC_FLOW_CONTROL_START_MEASURE_MASK is a HW self-clean bit. */ + base->FLOW_CONTROL |= TSC_FLOW_CONTROL_START_MEASURE_MASK; +} + +/*! + * @brief Drop measure X/Y coordinate value after detect a touch and controller return to idle status. + * + * @param base TSC peripheral base address. + */ +static inline void TSC_DropMeasure(TSC_Type *base) +{ + /* TSC_FLOW_CONTROL_DROP_MEASURE_MASK is a HW self-clean bit. */ + base->FLOW_CONTROL |= TSC_FLOW_CONTROL_DROP_MEASURE_MASK; +} + +/*! + * @brief This is a synchronization reset, which resets every register except IPS directly access ones. + * + * @param base TSC peripheral base address. + */ +static inline void TSC_SoftwareReset(TSC_Type *base) +{ + /* TSC_FLOW_CONTROL_SW_RST_MASK is a HW self-clean bit. */ + base->FLOW_CONTROL |= TSC_FLOW_CONTROL_SW_RST_MASK; +} + +/*! + * @brief Get Y coordinate value or X coordinate value. The value is an ADC conversion value. + * + * @param base TSC peripheral base address. + * @param selection Select alternative measure value which is Y coordinate value or X coordinate value. + * See "tsc_corrdinate_value_selection_t". + * @return If selection is "kTSC_XCoordinateValueSelection", the API returns x-coordinate vlaue. + * If selection is "kTSC_YCoordinateValueSelection", the API returns y-coordinate vlaue. + */ +uint32_t TSC_GetMeasureValue(TSC_Type *base, tsc_corrdinate_value_selection_t selection); + +/*! + * @brief Enable the interrupt signals. Interrupt signal will be set when corresponding event happens. + * Specific events point to "_tsc_interrupt_signal_mask" . + * Specific interrupt signal point to "_tsc_interrupt_status_flag_mask"; + * + * @param base TSC peripheral base address. + * @param mask Interrupt signals mask. See "_tsc_interrupt_signal_mask". + */ +static inline void TSC_EnableInterruptSignals(TSC_Type *base, uint32_t mask) +{ + base->INT_SIG_EN |= mask; +} + +/*! + * @brief Disable the interrupt signals. Interrupt signal will be set when corresponding event happens. + * Specific events point to "_tsc_interrupt_signal_mask". + * Specific interrupt signal point to "_tsc_interrupt_status_flag_mask"; + * + * @param base TSC peripheral base address. + * @param mask Interrupt signals mask. See "_tsc_interrupt_signal_mask". + */ +static inline void TSC_DisableInterruptSignals(TSC_Type *base, uint32_t mask) +{ + base->INT_SIG_EN &= ~mask; +} + +/*! + * @brief Enable the interrupts. Notice: Only interrupts and signals are all enabled, interrupts + * could work normally. + * + * @param base TSC peripheral base address. + * @param mask Interrupts mask. See "_tsc_interrupt_mask". + */ +static inline void TSC_EnableInterrupts(TSC_Type *base, uint32_t mask) +{ + base->INT_EN |= mask; +} + +/*! + * @brief Disable the interrupts. + * + * @param base TSC peripheral base address. + * @param mask Interrupts mask. See "_tsc_interrupt_mask". + */ +static inline void TSC_DisableInterrupts(TSC_Type *base, uint32_t mask) +{ + base->INT_EN &= ~mask; +} + +/*! + * @brief Get interrupt status flags. Interrupt status falgs are valid when corresponding + * interrupt signals are enabled. + * + * @param base TSC peripheral base address. + * @return Status flags asserted mask. See "_tsc_interrupt_status_flag_mask". + */ +static inline uint32_t TSC_GetInterruptStatusFlags(TSC_Type *base) +{ + return base->INT_STATUS; +} + +/*! + * @brief Clear interrupt status flags. Interrupt status falgs are valid when corresponding + * interrupt signals are enabled. + * + * @param base TSC peripheral base address. + * @param mask Status flags mask. See "_tsc_interrupt_status_flag_mask". + */ +static inline void TSC_ClearInterruptStatusFlags(TSC_Type *base, uint32_t mask) +{ + base->INT_STATUS = mask; +} + +/*! + * @brief Get the status flags of ADC working with TSC. + * + * @param base TSC peripheral base address. + * @return Status flags asserted mask. See "_tsc_adc_status_flag_mask". + */ +static inline uint32_t TSC_GetADCStatusFlags(TSC_Type *base) +{ + return base->DEBUG_MODE; +} + +/*! + * @brief Get the status flags of TSC. + * + * @param base TSC peripheral base address. + * @return Status flags asserted mask. See "_tsc_status_flag_mask". + */ +static inline uint32_t TSC_GetStatusFlags(TSC_Type *base) +{ + return base->DEBUG_MODE2; +} + +/*! + *@} + */ + +/******************************************************************************* + * Debug API + ******************************************************************************/ + +/*! + * @brief Enable/Disable debug mode. Once work in debug mode, then all + * TSC outputs will be controlled by software. Software can also observe all TSC inputs + * through debug interface. Furthermore, the debug registers also provides current state + * machine states. Software can always check the current hardware state. + * + * @param base TSC peripheral base address. + * @param enable Switcher of the debug mode. "true" means debug mode,"false" means non-debug mode. + */ +static inline void TSC_EnableDebugMode(TSC_Type *base, bool enable) +{ + if (enable) + { + base->DEBUG_MODE |= TSC_DEBUG_MODE_DEBUG_EN_MASK; + } + else + { + base->DEBUG_MODE &= ~TSC_DEBUG_MODE_DEBUG_EN_MASK; + } +} + +/*! + * @brief Send hardware trigger signal to ADC in debug mode. The trigger signal must last at least 1 ips clock period. + * + * @param base TSC peripheral base address. + * @param hwts Hardware trigger select signal, select which channel to start conversion. See "tsc_trigger_signal_t". + * On ADC side, HWTS = 1 << x indicates the x logic channel is selected to start hardware ADC conversion. + * @param enable Switcher of the trigger signal. "true" means generate trigger signal, "false" means don't generate + * trigger signal. + */ +void TSC_DebugTriggerSignalToADC(TSC_Type *base, tsc_trigger_signal_t hwts, bool enable); + +/*! + * @brief Enable/Disable hardware generates an ADC COCO clear signal in debug mode. + * + * @param base TSC peripheral base address. + * @param enable Switcher of the function of hardware generating an ADC COCO clear signal. + * "true" means prevent TSC from generate ADC COCO clear signal. + * "false" means allow TSC hardware generates ADC COCO clear. + */ +static inline void TSC_DebugDisableHWClear(TSC_Type *base, bool enable) +{ + if (enable) + { + base->DEBUG_MODE |= TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK; + } + else + { + base->DEBUG_MODE &= ~TSC_DEBUG_MODE_ADC_COCO_CLEAR_DISABLE_MASK; + } +} + +/*! + * @brief Send clear ADC COCO signal to ADC in debug mode. The signal must hold a while. + * + * @param base TSC peripheral base address. + * @param enable Switcher of the clear signal."true" means generate clear signal, "false" means don't generate + * clear signal. + */ +static inline void TSC_DebugClearSignalToADC(TSC_Type *base, bool enable) +{ + if (enable) + { + base->DEBUG_MODE |= TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK; + } + else + { + base->DEBUG_MODE &= ~TSC_DEBUG_MODE_ADC_COCO_CLEAR_MASK; + } +} + +/*! + * @brief Enable/Disable detection in debug mode. + * + * @param base TSC peripheral base address. + * @param detectionMode Set detect mode. See "tsc_detection_mode_t" + * @param enable Switcher of detect enable. "true" means enable detection, "false" means disable detection. + */ +void TSC_DebugEnableDetection(TSC_Type *base, tsc_detection_mode_t detectionMode, bool enable); + +/*! + * @brief Set TSC port mode in debug mode.(pull down, pull up and 200k-pull up) + * + * @param base TSC peripheral base address. + * @param port TSC controller ports. + * @param mode TSC port mode.(pull down, pull up and 200k-pull up) + */ +void TSC_DebugSetPortMode(TSC_Type *base, tsc_port_source_t port, tsc_port_mode_t mode); + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_TSC_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_usdhc.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_usdhc.c new file mode 100644 index 0000000000..7a3015d584 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_usdhc.c @@ -0,0 +1,2016 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_usdhc.h" +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL +#include "fsl_cache.h" +#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.usdhc" +#endif + +/*! @brief Clock setting */ +/* Max SD clock divisor from base clock */ +#define USDHC_MAX_DVS ((USDHC_SYS_CTRL_DVS_MASK >> USDHC_SYS_CTRL_DVS_SHIFT) + 1U) +#define USDHC_MAX_CLKFS ((USDHC_SYS_CTRL_SDCLKFS_MASK >> USDHC_SYS_CTRL_SDCLKFS_SHIFT) + 1U) +#define USDHC_PREV_DVS(x) ((x) -= 1U) +#define USDHC_PREV_CLKFS(x, y) ((x) >>= (y)) +/*! @brief USDHC ADMA table address align size */ +#define USDHC_ADMA_TABLE_ADDRESS_ALIGN (4U) + +/* Typedef for interrupt handler. */ +typedef void (*usdhc_isr_t)(USDHC_Type *base, usdhc_handle_t *handle); +/*! @brief Dummy data buffer for mmc boot mode */ +AT_NONCACHEABLE_SECTION_ALIGN(uint32_t s_usdhcBootDummy, USDHC_ADMA2_ADDRESS_ALIGN); +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance. + * + * @param base USDHC peripheral base address. + * @return Instance number. + */ +static uint32_t USDHC_GetInstance(USDHC_Type *base); + +/*! + * @brief Set transfer interrupt. + * + * @param base USDHC peripheral base address. + * @param usingInterruptSignal True to use IRQ signal. + */ +static void USDHC_SetTransferInterrupt(USDHC_Type *base, bool usingInterruptSignal); + +/*! + * @brief Start transfer according to current transfer state + * + * @param base USDHC peripheral base address. + * @param data Data to be transferred. + * @param flag data present flag + * @param enDMA DMA enable flag + */ +static status_t USDHC_SetDataTransferConfig(USDHC_Type *base, + usdhc_data_t *data, + uint32_t *dataPresentFlag, + bool enDMA); + +/*! + * @brief Receive command response + * + * @param base USDHC peripheral base address. + * @param command Command to be sent. + */ +static status_t USDHC_ReceiveCommandResponse(USDHC_Type *base, usdhc_command_t *command); + +/*! + * @brief Read DATAPORT when buffer enable bit is set. + * + * @param base USDHC peripheral base address. + * @param data Data to be read. + * @param transferredWords The number of data words have been transferred last time transaction. + * @return The number of total data words have been transferred after this time transaction. + */ +static uint32_t USDHC_ReadDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords); + +/*! + * @brief Read data by using DATAPORT polling way. + * + * @param base USDHC peripheral base address. + * @param data Data to be read. + * @retval kStatus_Fail Read DATAPORT failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t USDHC_ReadByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data); + +/*! + * @brief Write DATAPORT when buffer enable bit is set. + * + * @param base USDHC peripheral base address. + * @param data Data to be read. + * @param transferredWords The number of data words have been transferred last time. + * @return The number of total data words have been transferred after this time transaction. + */ +static uint32_t USDHC_WriteDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords); + +/*! + * @brief Write data by using DATAPORT polling way. + * + * @param base USDHC peripheral base address. + * @param data Data to be transferred. + * @retval kStatus_Fail Write DATAPORT failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t USDHC_WriteByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data); + +/*! + * @brief Transfer data by polling way. + * + * @param base USDHC peripheral base address. + * @param data Data to be transferred. + * @param use DMA flag. + * @retval kStatus_Fail Transfer data failed. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_Success Operate successfully. + */ +static status_t USDHC_TransferDataBlocking(USDHC_Type *base, usdhc_data_t *data, bool enDMA); + +/*! + * @brief Handle card detect interrupt. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + * @param interruptFlags Card detect related interrupt flags. + */ +static void USDHC_TransferHandleCardDetect(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); + +/*! + * @brief Handle command interrupt. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + * @param interruptFlags Command related interrupt flags. + */ +static void USDHC_TransferHandleCommand(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); + +/*! + * @brief Handle data interrupt. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + * @param interruptFlags Data related interrupt flags. + */ +static void USDHC_TransferHandleData(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); + +/*! + * @brief Handle SDIO card interrupt signal. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + */ +static void USDHC_TransferHandleSdioInterrupt(USDHC_Type *base, usdhc_handle_t *handle); + +/*! + * @brief Handle SDIO block gap event. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + */ +static void USDHC_TransferHandleBlockGap(USDHC_Type *base, usdhc_handle_t *handle); + +/*! + * @brief Handle retuning + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + * @param interrupt flags + */ +static void USDHC_TransferHandleReTuning(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags); + +/*! + * @brief wait command done + * + * @param base USDHC peripheral base address. + * @param command configuration + * @param pollingCmdDone polling command done flag + */ +static status_t USDHC_WaitCommandDone(USDHC_Type *base, usdhc_command_t *command, bool pollingCmdDone); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief USDHC base pointer array */ +static USDHC_Type *const s_usdhcBase[] = USDHC_BASE_PTRS; + +/*! @brief USDHC internal handle pointer array */ +static usdhc_handle_t *s_usdhcHandle[ARRAY_SIZE(s_usdhcBase)] = {NULL}; + +/*! @brief USDHC IRQ name array */ +static const IRQn_Type s_usdhcIRQ[] = USDHC_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief USDHC clock array name */ +static const clock_ip_name_t s_usdhcClock[] = USDHC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* USDHC ISR for transactional APIs. */ +static usdhc_isr_t s_usdhcIsr; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t USDHC_GetInstance(USDHC_Type *base) +{ + uint8_t instance = 0; + + while ((instance < ARRAY_SIZE(s_usdhcBase)) && (s_usdhcBase[instance] != base)) + { + instance++; + } + + assert(instance < ARRAY_SIZE(s_usdhcBase)); + + return instance; +} + +static void USDHC_SetTransferInterrupt(USDHC_Type *base, bool usingInterruptSignal) +{ + uint32_t interruptEnabled; /* The Interrupt status flags to be enabled */ + + /* Disable all interrupts */ + USDHC_DisableInterruptStatus(base, (uint32_t)kUSDHC_AllInterruptFlags); + USDHC_DisableInterruptSignal(base, (uint32_t)kUSDHC_AllInterruptFlags); + DisableIRQ(s_usdhcIRQ[USDHC_GetInstance(base)]); + + interruptEnabled = (kUSDHC_CommandFlag | kUSDHC_CardInsertionFlag | kUSDHC_DataFlag | kUSDHC_CardRemovalFlag | + kUSDHC_SDR104TuningFlag | kUSDHC_BlockGapEventFlag); + + USDHC_EnableInterruptStatus(base, interruptEnabled); + + if (usingInterruptSignal) + { + USDHC_EnableInterruptSignal(base, interruptEnabled); + } +} + +static status_t USDHC_SetDataTransferConfig(USDHC_Type *base, usdhc_data_t *data, uint32_t *dataPresentFlag, bool enDMA) +{ + uint32_t mixCtrl = base->MIX_CTRL; + + if (data != NULL) + { + /* if transfer boot continous, only need set the CREQ bit, leave others as it is */ + if (data->dataType == kUSDHC_TransferDataBootcontinous) + { + /* clear stop at block gap request */ + base->PROT_CTRL &= ~USDHC_PROT_CTRL_SABGREQ_MASK; + /* continous transfer data */ + base->PROT_CTRL |= USDHC_PROT_CTRL_CREQ_MASK; + return kStatus_Success; + } + + /* check data inhibit flag */ + if (base->PRES_STATE & kUSDHC_DataInhibitFlag) + { + return kStatus_USDHC_BusyTransferring; + } + /* check transfer block count */ + if ((data->blockCount > USDHC_MAX_BLOCK_COUNT) || ((data->txData == NULL) && (data->rxData == NULL))) + { + return kStatus_InvalidArgument; + } + + /* config mix parameter */ + mixCtrl &= ~(USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK | USDHC_MIX_CTRL_DTDSEL_MASK | + USDHC_MIX_CTRL_AC12EN_MASK); + + if (data->rxData) + { + mixCtrl |= USDHC_MIX_CTRL_DTDSEL_MASK; + } + if (data->blockCount > 1U) + { + mixCtrl |= USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK; + /* auto command 12 */ + if (data->enableAutoCommand12) + { + mixCtrl |= USDHC_MIX_CTRL_AC12EN_MASK; + } + } + + /* auto command 23, auto send set block count cmd before multiple read/write */ + if ((data->enableAutoCommand23)) + { + mixCtrl |= USDHC_MIX_CTRL_AC23EN_MASK; + base->VEND_SPEC2 |= USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK; + /* config the block count to DS_ADDR */ + base->DS_ADDR = data->blockCount; + } + else + { + mixCtrl &= ~USDHC_MIX_CTRL_AC23EN_MASK; + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK; + } + + /* if transfer boot data, leave the block count to USDHC_SetMmcBootConfig function */ + if (data->dataType != kUSDHC_TransferDataBoot) + { + /* config data block size/block count */ + base->BLK_ATT = ((base->BLK_ATT & ~(USDHC_BLK_ATT_BLKSIZE_MASK | USDHC_BLK_ATT_BLKCNT_MASK)) | + (USDHC_BLK_ATT_BLKSIZE(data->blockSize) | USDHC_BLK_ATT_BLKCNT(data->blockCount))); + } + else + { + mixCtrl |= USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK; + base->PROT_CTRL |= USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK; + } + + /* data present flag */ + *dataPresentFlag |= kUSDHC_DataPresentFlag; + /* Disable useless interrupt */ + if (enDMA) + { + base->INT_SIGNAL_EN &= ~(kUSDHC_BufferWriteReadyFlag | kUSDHC_BufferReadReadyFlag | kUSDHC_DmaCompleteFlag); + base->INT_STATUS_EN &= ~(kUSDHC_BufferWriteReadyFlag | kUSDHC_BufferReadReadyFlag | kUSDHC_DmaCompleteFlag); + } + else + { + base->INT_SIGNAL_EN |= kUSDHC_BufferWriteReadyFlag | kUSDHC_BufferReadReadyFlag; + base->INT_STATUS_EN |= kUSDHC_BufferWriteReadyFlag | kUSDHC_BufferReadReadyFlag; + } + } + else + { + /* clear data flags */ + mixCtrl &= ~(USDHC_MIX_CTRL_MSBSEL_MASK | USDHC_MIX_CTRL_BCEN_MASK | USDHC_MIX_CTRL_DTDSEL_MASK | + USDHC_MIX_CTRL_AC12EN_MASK | USDHC_MIX_CTRL_AC23EN_MASK); + + if (base->PRES_STATE & kUSDHC_CommandInhibitFlag) + { + return kStatus_USDHC_BusyTransferring; + } + } + + /* config the mix parameter */ + base->MIX_CTRL = mixCtrl; + + return kStatus_Success; +} + +static status_t USDHC_ReceiveCommandResponse(USDHC_Type *base, usdhc_command_t *command) +{ + assert(command != NULL); + + if (command->responseType != kCARD_ResponseTypeNone) + { + command->response[0U] = base->CMD_RSP0; + if (command->responseType == kCARD_ResponseTypeR2) + { + /* R3-R2-R1-R0(lowest 8 bit is invalid bit) has the same format as R2 format in SD specification document + after removed internal CRC7 and end bit. */ + command->response[0U] <<= 8U; + command->response[1U] = (base->CMD_RSP1 << 8U) | ((base->CMD_RSP0 & 0xFF000000U) >> 24U); + command->response[2U] = (base->CMD_RSP2 << 8U) | ((base->CMD_RSP1 & 0xFF000000U) >> 24U); + command->response[3U] = (base->CMD_RSP3 << 8U) | ((base->CMD_RSP2 & 0xFF000000U) >> 24U); + } + } + + /* check response error flag */ + if ((command->responseErrorFlags != 0U) && + ((command->responseType == kCARD_ResponseTypeR1) || (command->responseType == kCARD_ResponseTypeR1b) || + (command->responseType == kCARD_ResponseTypeR6) || (command->responseType == kCARD_ResponseTypeR5))) + { + if (((command->responseErrorFlags) & (command->response[0U])) != 0U) + { + return kStatus_USDHC_SendCommandFailed; + } + } + + return kStatus_Success; +} + +static uint32_t USDHC_ReadDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords) +{ + uint32_t i; + uint32_t totalWords; + uint32_t wordsCanBeRead; /* The words can be read at this time. */ + uint32_t readWatermark = ((base->WTMK_LVL & USDHC_WTMK_LVL_RD_WML_MASK) >> USDHC_WTMK_LVL_RD_WML_SHIFT); + + /* If DMA is enable, do not need to polling data port */ + if ((base->MIX_CTRL & USDHC_MIX_CTRL_DMAEN_MASK) == 0U) + { + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + /* If watermark level is equal or bigger than totalWords, transfers totalWords data. */ + if (readWatermark >= totalWords) + { + wordsCanBeRead = totalWords; + } + /* If watermark level is less than totalWords and left words to be sent is equal or bigger than readWatermark, + transfers watermark level words. */ + else if ((readWatermark < totalWords) && ((totalWords - transferredWords) >= readWatermark)) + { + wordsCanBeRead = readWatermark; + } + /* If watermark level is less than totalWords and left words to be sent is less than readWatermark, transfers + left + words. */ + else + { + wordsCanBeRead = (totalWords - transferredWords); + } + + i = 0U; + while (i < wordsCanBeRead) + { + data->rxData[transferredWords++] = USDHC_ReadData(base); + i++; + } + } + + return transferredWords; +} + +static status_t USDHC_ReadByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data) +{ + uint32_t totalWords; + uint32_t transferredWords = 0U, interruptStatus = 0U; + status_t error = kStatus_Success; + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + while ((error == kStatus_Success) && (transferredWords < totalWords)) + { + while (!(interruptStatus & (kUSDHC_BufferReadReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_TuningErrorFlag))) + { + interruptStatus = USDHC_GetInterruptStatusFlags(base); + } + + /* during std tuning process, software do not need to read data, but wait BRR is enough */ + if ((data->dataType == kUSDHC_TransferDataTuning) && (interruptStatus & kUSDHC_BufferReadReadyFlag)) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferReadReadyFlag | kUSDHC_TuningPassFlag); + + return kStatus_Success; + } + else if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_TuningErrorFlag); + /* if tuning error occur ,return directly */ + error = kStatus_USDHC_TuningError; + } + else if ((interruptStatus & kUSDHC_DataErrorFlag) != 0U) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + /* clear data error flag */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_DataErrorFlag); + } + else + { + } + + if (error == kStatus_Success) + { + transferredWords = USDHC_ReadDataPort(base, data, transferredWords); + /* clear buffer read ready */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferReadReadyFlag); + interruptStatus = 0U; + } + } + + /* Clear data complete flag after the last read operation. */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_DataCompleteFlag); + + return error; +} + +static uint32_t USDHC_WriteDataPort(USDHC_Type *base, usdhc_data_t *data, uint32_t transferredWords) +{ + uint32_t i; + uint32_t totalWords; + uint32_t wordsCanBeWrote; /* Words can be wrote at this time. */ + uint32_t writeWatermark = ((base->WTMK_LVL & USDHC_WTMK_LVL_WR_WML_MASK) >> USDHC_WTMK_LVL_WR_WML_SHIFT); + + /* If DMA is enable, do not need to polling data port */ + if ((base->MIX_CTRL & USDHC_MIX_CTRL_DMAEN_MASK) == 0U) + { + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = ((data->blockCount * data->blockSize) / sizeof(uint32_t)); + + /* If watermark level is equal or bigger than totalWords, transfers totalWords data.*/ + if (writeWatermark >= totalWords) + { + wordsCanBeWrote = totalWords; + } + /* If watermark level is less than totalWords and left words to be sent is equal or bigger than watermark, + transfers watermark level words. */ + else if ((writeWatermark < totalWords) && ((totalWords - transferredWords) >= writeWatermark)) + { + wordsCanBeWrote = writeWatermark; + } + /* If watermark level is less than totalWords and left words to be sent is less than watermark, transfers left + words. */ + else + { + wordsCanBeWrote = (totalWords - transferredWords); + } + + i = 0U; + while (i < wordsCanBeWrote) + { + USDHC_WriteData(base, data->txData[transferredWords++]); + i++; + } + } + + return transferredWords; +} + +static status_t USDHC_WriteByDataPortBlocking(USDHC_Type *base, usdhc_data_t *data) +{ + uint32_t totalWords; + + uint32_t transferredWords = 0U, interruptStatus = 0U; + status_t error = kStatus_Success; + + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (data->blockSize % sizeof(uint32_t) != 0U) + { + data->blockSize += + sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ + } + + totalWords = (data->blockCount * data->blockSize) / sizeof(uint32_t); + + while ((error == kStatus_Success) && (transferredWords < totalWords)) + { + while (!(interruptStatus & (kUSDHC_BufferWriteReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_TuningErrorFlag))) + { + interruptStatus = USDHC_GetInterruptStatusFlags(base); + } + + if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_TuningErrorFlag); + /* if tuning error occur ,return directly */ + return kStatus_USDHC_TuningError; + } + else if ((interruptStatus & kUSDHC_DataErrorFlag) != 0U) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + /* clear data error flag */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_DataErrorFlag); + } + else + { + } + + if (error == kStatus_Success) + { + transferredWords = USDHC_WriteDataPort(base, data, transferredWords); + /* clear buffer write ready */ + USDHC_ClearInterruptStatusFlags(base, kUSDHC_BufferWriteReadyFlag); + interruptStatus = 0U; + } + } + + /* Wait write data complete or data transfer error after the last writing operation. */ + while (!(interruptStatus & (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag))) + { + interruptStatus = USDHC_GetInterruptStatusFlags(base); + } + + if ((interruptStatus & kUSDHC_DataErrorFlag) != 0U) + { + if (!(data->enableIgnoreError)) + { + error = kStatus_Fail; + } + } + USDHC_ClearInterruptStatusFlags(base, (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag)); + + return error; +} + +/*! + * brief send command function + * + * param base USDHC peripheral base address. + * param command configuration + */ +void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command) +{ + assert(NULL != command); + + uint32_t xferType = base->CMD_XFR_TYP, flags = command->flags; + + if (((base->PRES_STATE & kUSDHC_CommandInhibitFlag) == 0U) && (command->type != kCARD_CommandTypeEmpty)) + { + /* Define the flag corresponding to each response type. */ + switch (command->responseType) + { + case kCARD_ResponseTypeNone: + break; + case kCARD_ResponseTypeR1: /* Response 1 */ + case kCARD_ResponseTypeR5: /* Response 5 */ + case kCARD_ResponseTypeR6: /* Response 6 */ + case kCARD_ResponseTypeR7: /* Response 7 */ + flags |= (kUSDHC_ResponseLength48Flag | kUSDHC_EnableCrcCheckFlag | kUSDHC_EnableIndexCheckFlag); + break; + + case kCARD_ResponseTypeR1b: /* Response 1 with busy */ + case kCARD_ResponseTypeR5b: /* Response 5 with busy */ + flags |= (kUSDHC_ResponseLength48BusyFlag | kUSDHC_EnableCrcCheckFlag | kUSDHC_EnableIndexCheckFlag); + break; + + case kCARD_ResponseTypeR2: /* Response 2 */ + flags |= (kUSDHC_ResponseLength136Flag | kUSDHC_EnableCrcCheckFlag); + break; + + case kCARD_ResponseTypeR3: /* Response 3 */ + case kCARD_ResponseTypeR4: /* Response 4 */ + flags |= (kUSDHC_ResponseLength48Flag); + break; + + default: + break; + } + + if (command->type == kCARD_CommandTypeAbort) + { + flags |= kUSDHC_CommandTypeAbortFlag; + } + + /* config cmd index */ + xferType &= ~(USDHC_CMD_XFR_TYP_CMDINX_MASK | USDHC_CMD_XFR_TYP_CMDTYP_MASK | USDHC_CMD_XFR_TYP_CICEN_MASK | + USDHC_CMD_XFR_TYP_CCCEN_MASK | USDHC_CMD_XFR_TYP_RSPTYP_MASK | USDHC_CMD_XFR_TYP_DPSEL_MASK); + + xferType |= + (((command->index << USDHC_CMD_XFR_TYP_CMDINX_SHIFT) & USDHC_CMD_XFR_TYP_CMDINX_MASK) | + ((flags) & (USDHC_CMD_XFR_TYP_CMDTYP_MASK | USDHC_CMD_XFR_TYP_CICEN_MASK | USDHC_CMD_XFR_TYP_CCCEN_MASK | + USDHC_CMD_XFR_TYP_RSPTYP_MASK | USDHC_CMD_XFR_TYP_DPSEL_MASK))); + + /* config the command xfertype and argument */ + base->CMD_ARG = command->argument; + base->CMD_XFR_TYP = xferType; + } + + if (command->type == kCARD_CommandTypeEmpty) + { + /* disable CMD done interrupt for empty command */ + base->INT_SIGNAL_EN &= ~USDHC_INT_SIGNAL_EN_CCIEN_MASK; + } +} + +static status_t USDHC_WaitCommandDone(USDHC_Type *base, usdhc_command_t *command, bool pollingCmdDone) +{ + assert(NULL != command); + + status_t error = kStatus_Success; + uint32_t interruptStatus = 0U; + /* check if need polling command done or not */ + if (pollingCmdDone) + { + /* Wait command complete or USDHC encounters error. */ + while (!(interruptStatus & (kUSDHC_CommandCompleteFlag | kUSDHC_CommandErrorFlag))) + { + interruptStatus = USDHC_GetInterruptStatusFlags(base); + } + + if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) + { + error = kStatus_USDHC_TuningError; + } + else if ((interruptStatus & kUSDHC_CommandErrorFlag) != 0U) + { + error = kStatus_Fail; + } + else + { + } + /* Receive response when command completes successfully. */ + if (error == kStatus_Success) + { + error = USDHC_ReceiveCommandResponse(base, command); + } + + USDHC_ClearInterruptStatusFlags( + base, (kUSDHC_CommandCompleteFlag | kUSDHC_CommandErrorFlag | kUSDHC_TuningErrorFlag)); + } + + return error; +} + +static status_t USDHC_TransferDataBlocking(USDHC_Type *base, usdhc_data_t *data, bool enDMA) +{ + status_t error = kStatus_Success; + uint32_t interruptStatus = 0U; + + if (enDMA) + { + /* Wait data complete or USDHC encounters error. */ + while (!((interruptStatus & + (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag | kUSDHC_TuningErrorFlag)))) + { + interruptStatus = USDHC_GetInterruptStatusFlags(base); + } + + if ((interruptStatus & kUSDHC_TuningErrorFlag) != 0U) + { + error = kStatus_USDHC_TuningError; + } + else if (((interruptStatus & (kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag)) != 0U)) + { + if ((!(data->enableIgnoreError)) || (interruptStatus & kUSDHC_DataTimeoutFlag)) + { + error = kStatus_Fail; + } + } + else + { + } + /* load dummy data */ + if ((data->dataType == kUSDHC_TransferDataBootcontinous) && (error == kStatus_Success)) + { + *(data->rxData) = s_usdhcBootDummy; + } + + USDHC_ClearInterruptStatusFlags(base, (kUSDHC_DataCompleteFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag | + kUSDHC_TuningPassFlag | kUSDHC_TuningErrorFlag)); + } + else + { + if (data->rxData) + { + error = USDHC_ReadByDataPortBlocking(base, data); + } + else + { + error = USDHC_WriteByDataPortBlocking(base, data); + } + } + + return error; +} + +/*! + * brief USDHC module initialization function. + * + * Configures the USDHC according to the user configuration. + * + * Example: + code + usdhc_config_t config; + config.cardDetectDat3 = false; + config.endianMode = kUSDHC_EndianModeLittle; + config.dmaMode = kUSDHC_DmaModeAdma2; + config.readWatermarkLevel = 128U; + config.writeWatermarkLevel = 128U; + USDHC_Init(USDHC, &config); + endcode + * + * param base USDHC peripheral base address. + * param config USDHC configuration information. + * retval kStatus_Success Operate successfully. + */ +void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config) +{ + assert(config); + assert((config->writeWatermarkLevel >= 1U) && (config->writeWatermarkLevel <= 128U)); + assert((config->readWatermarkLevel >= 1U) && (config->readWatermarkLevel <= 128U)); + assert(config->writeBurstLen <= 16U); + + uint32_t proctl, sysctl, wml; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable USDHC clock. */ + CLOCK_EnableClock(s_usdhcClock[USDHC_GetInstance(base)]); +#endif + + /* Reset USDHC. */ + USDHC_Reset(base, kUSDHC_ResetAll, 100U); + + proctl = base->PROT_CTRL; + wml = base->WTMK_LVL; + sysctl = base->SYS_CTRL; + + proctl &= ~(USDHC_PROT_CTRL_EMODE_MASK | USDHC_PROT_CTRL_DMASEL_MASK); + /* Endian mode*/ + proctl |= USDHC_PROT_CTRL_EMODE(config->endianMode); + + /* Watermark level */ + wml &= ~(USDHC_WTMK_LVL_RD_WML_MASK | USDHC_WTMK_LVL_WR_WML_MASK | USDHC_WTMK_LVL_RD_BRST_LEN_MASK | + USDHC_WTMK_LVL_WR_BRST_LEN_MASK); + wml |= (USDHC_WTMK_LVL_RD_WML(config->readWatermarkLevel) | USDHC_WTMK_LVL_WR_WML(config->writeWatermarkLevel) | + USDHC_WTMK_LVL_RD_BRST_LEN(config->readBurstLen) | USDHC_WTMK_LVL_WR_BRST_LEN(config->writeBurstLen)); + + /* config the data timeout value */ + sysctl &= ~USDHC_SYS_CTRL_DTOCV_MASK; + sysctl |= USDHC_SYS_CTRL_DTOCV(config->dataTimeout); + + base->SYS_CTRL = sysctl; + base->WTMK_LVL = wml; + base->PROT_CTRL = proctl; + +#if FSL_FEATURE_USDHC_HAS_EXT_DMA + /* disable external DMA */ + base->VEND_SPEC &= ~USDHC_VEND_SPEC_EXT_DMA_EN_MASK; +#endif + /* disable internal DMA and DDR mode */ + base->MIX_CTRL &= ~(USDHC_MIX_CTRL_DMAEN_MASK | USDHC_MIX_CTRL_DDR_EN_MASK); + /* Enable interrupt status but doesn't enable interrupt signal. */ + USDHC_SetTransferInterrupt(base, false); +} + +/*! + * brief Deinitializes the USDHC. + * + * param base USDHC peripheral base address. + */ +void USDHC_Deinit(USDHC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable clock. */ + CLOCK_DisableClock(s_usdhcClock[USDHC_GetInstance(base)]); +#endif +} + +/*! + * brief Resets the USDHC. + * + * param base USDHC peripheral base address. + * param mask The reset type mask(_usdhc_reset). + * param timeout Timeout for reset. + * retval true Reset successfully. + * retval false Reset failed. + */ +bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout) +{ + base->SYS_CTRL |= (mask & (USDHC_SYS_CTRL_RSTA_MASK | USDHC_SYS_CTRL_RSTC_MASK | USDHC_SYS_CTRL_RSTD_MASK)); + /* Delay some time to wait reset success. */ + while ((base->SYS_CTRL & mask) != 0U) + { + if (timeout == 0U) + { + break; + } + timeout--; + } + + return ((!timeout) ? false : true); +} + +/*! + * brief Gets the capability information. + * + * param base USDHC peripheral base address. + * param capability Structure to save capability information. + */ +void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability) +{ + assert(capability); + + uint32_t htCapability; + uint32_t maxBlockLength; + + htCapability = base->HOST_CTRL_CAP; + + /* Get the capability of USDHC. */ + maxBlockLength = ((htCapability & USDHC_HOST_CTRL_CAP_MBL_MASK) >> USDHC_HOST_CTRL_CAP_MBL_SHIFT); + capability->maxBlockLength = (512U << maxBlockLength); + /* Other attributes not in HTCAPBLT register. */ + capability->maxBlockCount = USDHC_MAX_BLOCK_COUNT; + capability->flags = (htCapability & (kUSDHC_SupportAdmaFlag | kUSDHC_SupportHighSpeedFlag | kUSDHC_SupportDmaFlag | + kUSDHC_SupportSuspendResumeFlag | kUSDHC_SupportV330Flag)); + capability->flags |= (htCapability & kUSDHC_SupportV300Flag); + capability->flags |= (htCapability & kUSDHC_SupportV180Flag); + capability->flags |= + (htCapability & (kUSDHC_SupportDDR50Flag | kUSDHC_SupportSDR104Flag | kUSDHC_SupportSDR50Flag)); + /* USDHC support 4/8 bit data bus width. */ + capability->flags |= (kUSDHC_Support4BitFlag | kUSDHC_Support8BitFlag); +} + +/*! + * brief Sets the SD bus clock frequency. + * + * param base USDHC peripheral base address. + * param srcClock_Hz USDHC source clock frequency united in Hz. + * param busClock_Hz SD bus clock frequency united in Hz. + * + * return The nearest frequency of busClock_Hz configured to SD bus. + */ +uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz) +{ + assert(srcClock_Hz != 0U); + assert((busClock_Hz != 0U) && (busClock_Hz <= srcClock_Hz)); + + uint32_t totalDiv = 0U; + uint32_t divisor = 0U; + uint32_t prescaler = 0U; + uint32_t sysctl = 0U; + uint32_t nearestFrequency = 0U; + + /* calucate total divisor first */ + if ((totalDiv = srcClock_Hz / busClock_Hz) > (USDHC_MAX_CLKFS * USDHC_MAX_DVS)) + { + return 0U; + } + + if (totalDiv != 0U) + { + /* calucate the divisor (srcClock_Hz / divisor) <= busClock_Hz */ + if ((srcClock_Hz / totalDiv) > busClock_Hz) + { + totalDiv++; + } + + /* divide the total divisor to div and prescaler */ + if (totalDiv > USDHC_MAX_DVS) + { + prescaler = totalDiv / USDHC_MAX_DVS; + /* prescaler must be a value which equal 2^n and smaller than SDHC_MAX_CLKFS */ + while (((USDHC_MAX_CLKFS % prescaler) != 0U) || (prescaler == 1U)) + { + prescaler++; + } + /* calucate the divisor */ + divisor = totalDiv / prescaler; + /* fine tuning the divisor until divisor * prescaler >= totalDiv */ + while ((divisor * prescaler) < totalDiv) + { + divisor++; + if (divisor > USDHC_MAX_DVS) + { + if ((prescaler <<= 1U) > USDHC_MAX_CLKFS) + { + return 0; + } + divisor = totalDiv / prescaler; + } + } + } + else + { + /* in this situation , divsior and SDCLKFS can generate same clock + use SDCLKFS*/ + if (((totalDiv % 2U) != 0U) & (totalDiv != 1U)) + { + divisor = totalDiv; + prescaler = 1U; + } + else + { + divisor = 1U; + prescaler = totalDiv; + } + } + nearestFrequency = srcClock_Hz / (divisor == 0U ? 1U : divisor) / prescaler; + } + /* in this condition , srcClock_Hz = busClock_Hz, */ + else + { + /* in DDR mode , set SDCLKFS to 0, divisor = 0, actually the + totoal divider = 2U */ + divisor = 0U; + prescaler = 0U; + nearestFrequency = srcClock_Hz; + } + + /* calucate the value write to register */ + if (divisor != 0U) + { + USDHC_PREV_DVS(divisor); + } + /* calucate the value write to register */ + if (prescaler != 0U) + { + USDHC_PREV_CLKFS(prescaler, 1U); + } + + /* Set the SD clock frequency divisor, SD clock frequency select, data timeout counter value. */ + sysctl = base->SYS_CTRL; + sysctl &= ~(USDHC_SYS_CTRL_DVS_MASK | USDHC_SYS_CTRL_SDCLKFS_MASK); + sysctl |= (USDHC_SYS_CTRL_DVS(divisor) | USDHC_SYS_CTRL_SDCLKFS(prescaler)); + base->SYS_CTRL = sysctl; + + /* Wait until the SD clock is stable. */ + while (!(base->PRES_STATE & USDHC_PRES_STATE_SDSTB_MASK)) + { + } + + return nearestFrequency; +} + +/*! + * brief Sends 80 clocks to the card to set it to the active state. + * + * This function must be called each time the card is inserted to ensure that the card can receive the command + * correctly. + * + * param base USDHC peripheral base address. + * param timeout Timeout to initialize card. + * retval true Set card active successfully. + * retval false Set card active failed. + */ +bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout) +{ + base->SYS_CTRL |= USDHC_SYS_CTRL_INITA_MASK; + /* Delay some time to wait card become active state. */ + while ((base->SYS_CTRL & USDHC_SYS_CTRL_INITA_MASK) == USDHC_SYS_CTRL_INITA_MASK) + { + if (!timeout) + { + break; + } + timeout--; + } + + return ((!timeout) ? false : true); +} + +/*! + * brief the enable/disable DDR mode + * + * param base USDHC peripheral base address. + * param enable/disable flag + * param nibble position + */ +void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos) +{ + uint32_t prescaler = (base->SYS_CTRL & USDHC_SYS_CTRL_SDCLKFS_MASK) >> USDHC_SYS_CTRL_SDCLKFS_SHIFT; + + if (enable) + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_NIBBLE_POS_MASK; + base->MIX_CTRL |= (USDHC_MIX_CTRL_DDR_EN_MASK | USDHC_MIX_CTRL_NIBBLE_POS(nibblePos)); + prescaler >>= 1U; + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DDR_EN_MASK; + + if (prescaler == 0U) + { + prescaler += 1U; + } + else + { + prescaler <<= 1U; + } + } + + base->SYS_CTRL = (base->SYS_CTRL & (~USDHC_SYS_CTRL_SDCLKFS_MASK)) | USDHC_SYS_CTRL_SDCLKFS(prescaler); +} + +/*! + * brief Configures the MMC boot feature. + * + * Example: + code + usdhc_boot_config_t config; + config.ackTimeoutCount = 4; + config.bootMode = kUSDHC_BootModeNormal; + config.blockCount = 5; + config.enableBootAck = true; + config.enableBoot = true; + config.enableAutoStopAtBlockGap = true; + USDHC_SetMmcBootConfig(USDHC, &config); + endcode + * + * param base USDHC peripheral base address. + * param config The MMC boot configuration information. + */ +void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config) +{ + assert(config); + assert(config->ackTimeoutCount <= (USDHC_MMC_BOOT_DTOCV_ACK_MASK >> USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)); + assert(config->blockCount <= (USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK >> USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)); + + uint32_t mmcboot = base->MMC_BOOT; + + mmcboot &= ~(USDHC_MMC_BOOT_DTOCV_ACK_MASK | USDHC_MMC_BOOT_BOOT_MODE_MASK | USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK); + mmcboot |= USDHC_MMC_BOOT_DTOCV_ACK(config->ackTimeoutCount) | USDHC_MMC_BOOT_BOOT_MODE(config->bootMode); + + if (config->enableBootAck) + { + mmcboot |= USDHC_MMC_BOOT_BOOT_ACK_MASK; + } + if (config->enableAutoStopAtBlockGap) + { + mmcboot |= + USDHC_MMC_BOOT_AUTO_SABG_EN_MASK | USDHC_MMC_BOOT_BOOT_BLK_CNT(USDHC_MAX_BLOCK_COUNT - config->blockCount); + /* always set the block count to USDHC_MAX_BLOCK_COUNT to use auto stop at block gap feature */ + base->BLK_ATT = ((base->BLK_ATT & ~(USDHC_BLK_ATT_BLKSIZE_MASK | USDHC_BLK_ATT_BLKCNT_MASK)) | + (USDHC_BLK_ATT_BLKSIZE(config->blockSize) | USDHC_BLK_ATT_BLKCNT(USDHC_MAX_BLOCK_COUNT))); + } + else + { + base->BLK_ATT = ((base->BLK_ATT & ~(USDHC_BLK_ATT_BLKSIZE_MASK | USDHC_BLK_ATT_BLKCNT_MASK)) | + (USDHC_BLK_ATT_BLKSIZE(config->blockSize) | USDHC_BLK_ATT_BLKCNT(config->blockCount))); + } + + base->MMC_BOOT = mmcboot; +} + +/*! + * brief Sets the ADMA1 descriptor table configuration. + * + * param admaTable Adma table address. + * param admaTableWords Adma table length. + * param dataBufferAddr Data buffer address. + * param dataBytes Data length. + * param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please + * reference _usdhc_adma_flag. + * retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * retval kStatus_Success Operate successfully. + */ +status_t USDHC_SetADMA1Descriptor( + uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags) +{ + assert(NULL != admaTable); + assert(NULL != dataBufferAddr); + + uint32_t miniEntries, startEntries = 0U, + maxEntries = (admaTableWords * sizeof(uint32_t)) / sizeof(usdhc_adma1_descriptor_t); + usdhc_adma1_descriptor_t *adma1EntryAddress = (usdhc_adma1_descriptor_t *)(admaTable); + uint32_t i, dmaBufferLen = 0U; + const uint32_t *data = dataBufferAddr; + + if (((uint32_t)data % USDHC_ADMA1_ADDRESS_ALIGN) != 0U) + { + return kStatus_USDHC_DMADataAddrNotAlign; + } + + if (flags == kUSDHC_AdmaDescriptorMultipleFlag) + { + return kStatus_USDHC_NotSupport; + } + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (dataBytes % sizeof(uint32_t) != 0U) + { + /* make the data length as word-aligned */ + dataBytes += sizeof(uint32_t) - (dataBytes % sizeof(uint32_t)); + } + + /* Check if ADMA descriptor's number is enough. */ + if ((dataBytes % USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) == 0U) + { + miniEntries = dataBytes / USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; + } + else + { + miniEntries = ((dataBytes / USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U); + } + + /* ADMA1 needs two descriptors to finish a transfer */ + miniEntries <<= 1U; + + if (miniEntries + startEntries > maxEntries) + { + return kStatus_OutOfRange; + } + + for (i = startEntries; i < (miniEntries + startEntries); i += 2U) + { + if (dataBytes > USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + { + dmaBufferLen = USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; + } + else + { + dmaBufferLen = dataBytes; + } + + adma1EntryAddress[i] = (dmaBufferLen << USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT); + adma1EntryAddress[i] |= kUSDHC_Adma1DescriptorTypeSetLength; + adma1EntryAddress[i + 1U] = (uint32_t)(data); + adma1EntryAddress[i + 1U] |= kUSDHC_Adma1DescriptorTypeTransfer; + data += dmaBufferLen / sizeof(uint32_t); + dataBytes -= dmaBufferLen; + } + /* the end of the descriptor */ + adma1EntryAddress[i - 1U] |= kUSDHC_Adma1DescriptorEndFlag; + + return kStatus_Success; +} + +/*! + * brief Sets the ADMA2 descriptor table configuration. + * + * param admaTable Adma table address. + * param admaTableWords Adma table length. + * param dataBufferAddr Data buffer address. + * param dataBytes Data Data length. + * param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please + * reference _usdhc_adma_flag. + * retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * retval kStatus_Success Operate successfully. + */ +status_t USDHC_SetADMA2Descriptor( + uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags) +{ + assert(NULL != admaTable); + assert(NULL != dataBufferAddr); + + uint32_t miniEntries, startEntries = 0U, + maxEntries = (admaTableWords * sizeof(uint32_t)) / sizeof(usdhc_adma2_descriptor_t); + usdhc_adma2_descriptor_t *adma2EntryAddress = (usdhc_adma2_descriptor_t *)(admaTable); + uint32_t i, dmaBufferLen = 0U; + const uint32_t *data = dataBufferAddr; + + if (((uint32_t)data % USDHC_ADMA2_ADDRESS_ALIGN) != 0U) + { + return kStatus_USDHC_DMADataAddrNotAlign; + } + /* + * Add non aligned access support ,user need make sure your buffer size is big + * enough to hold the data,in other words,user need make sure the buffer size + * is 4 byte aligned + */ + if (dataBytes % sizeof(uint32_t) != 0U) + { + /* make the data length as word-aligned */ + dataBytes += sizeof(uint32_t) - (dataBytes % sizeof(uint32_t)); + } + + /* Check if ADMA descriptor's number is enough. */ + if ((dataBytes % USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) == 0U) + { + miniEntries = dataBytes / USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; + } + else + { + miniEntries = ((dataBytes / USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U); + } + /* calucate the start entry for multiple descriptor mode, ADMA engine is not stop, so update the descriptor + data adress and data size is enough */ + if (flags == kUSDHC_AdmaDescriptorMultipleFlag) + { + for (i = 0U; i < maxEntries; i++) + { + if ((adma2EntryAddress[i].attribute & kUSDHC_Adma2DescriptorValidFlag) == 0U) + { + break; + } + } + startEntries = i; + /* add one entry for dummy entry */ + miniEntries += 1U; + } + + if ((miniEntries + startEntries) > maxEntries) + { + return kStatus_OutOfRange; + } + + for (i = startEntries; i < (miniEntries + startEntries); i++) + { + if (dataBytes > USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + { + dmaBufferLen = USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY; + } + else + { + dmaBufferLen = (dataBytes == 0U ? sizeof(uint32_t) : + dataBytes); /* adma don't support 0 data length transfer descriptor */ + } + + /* Each descriptor for ADMA2 is 64-bit in length */ + adma2EntryAddress[i].address = (dataBytes == 0U) ? &s_usdhcBootDummy : data; + adma2EntryAddress[i].attribute = (dmaBufferLen << USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT); + adma2EntryAddress[i].attribute |= + (dataBytes == 0U) ? 0U : (kUSDHC_Adma2DescriptorTypeTransfer | kUSDHC_Adma2DescriptorInterruptFlag); + data += (dmaBufferLen / sizeof(uint32_t)); + + if (dataBytes != 0U) + { + dataBytes -= dmaBufferLen; + } + } + + /* add a dummy valid ADMA descriptor for multiple descriptor mode, this is useful when transfer boot data, the ADMA + engine + will not stop at block gap */ + if (flags == kUSDHC_AdmaDescriptorMultipleFlag) + { + adma2EntryAddress[startEntries + 1U].attribute |= kUSDHC_Adma2DescriptorTypeTransfer; + } + else + { + /* set the end bit */ + adma2EntryAddress[i - 1U].attribute |= kUSDHC_Adma2DescriptorEndFlag; + } + + return kStatus_Success; +} + +/*! + * brief Internal DMA configuration. + * This function is used to config the USDHC DMA related registers. + * param base USDHC peripheral base address. + * param adma configuration + * param dataAddr transfer data address, a simple DMA parameter, if ADMA is used, leave it to NULL. + * param enAutoCmd23 flag to indicate Auto CMD23 is enable or not, a simple DMA parameter,if ADMA is used, leave it to + * false. + * retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * retval kStatus_Success Operate successfully. + */ +status_t USDHC_SetInternalDmaConfig(USDHC_Type *base, + usdhc_adma_config_t *dmaConfig, + const uint32_t *dataAddr, + bool enAutoCmd23) +{ + assert(dmaConfig); + assert(dataAddr); + assert((NULL != dmaConfig->admaTable) && + (((USDHC_ADMA_TABLE_ADDRESS_ALIGN - 1U) & (uint32_t)dmaConfig->admaTable) == 0U)); + +#if FSL_FEATURE_USDHC_HAS_EXT_DMA + /* disable the external DMA if support */ + base->VEND_SPEC &= ~USDHC_VEND_SPEC_EXT_DMA_EN_MASK; +#endif + + if (dmaConfig->dmaMode == kUSDHC_DmaModeSimple) + { + /* check DMA data buffer address align or not */ + if (((uint32_t)dataAddr % USDHC_ADMA2_ADDRESS_ALIGN) != 0U) + { + return kStatus_USDHC_DMADataAddrNotAlign; + } + /* in simple DMA mode if use auto CMD23, address should load to ADMA addr, + and block count should load to DS_ADDR*/ + if (enAutoCmd23) + { + base->ADMA_SYS_ADDR = (uint32_t)dataAddr; + } + else + { + base->DS_ADDR = (uint32_t)dataAddr; + } + } + else + { + /* When use ADMA, disable simple DMA */ + base->DS_ADDR = 0U; + base->ADMA_SYS_ADDR = (uint32_t)(dmaConfig->admaTable); + } + + /* select DMA mode and config the burst length */ + base->PROT_CTRL &= ~(USDHC_PROT_CTRL_DMASEL_MASK | USDHC_PROT_CTRL_BURST_LEN_EN_MASK); + base->PROT_CTRL |= USDHC_PROT_CTRL_DMASEL(dmaConfig->dmaMode) | USDHC_PROT_CTRL_BURST_LEN_EN(dmaConfig->burstLen); + /* enable DMA */ + base->MIX_CTRL |= USDHC_MIX_CTRL_DMAEN_MASK; + + return kStatus_Success; +} + +/*! + * brief Sets the DMA descriptor table configuration. + * A high level DMA descriptor configuration function. + * param base USDHC peripheral base address. + * param adma configuration + * param data Data descriptor + * param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please + * reference _usdhc_adma_flag + * retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * retval kStatus_Success Operate successfully. + */ +status_t USDHC_SetAdmaTableConfig(USDHC_Type *base, + usdhc_adma_config_t *dmaConfig, + usdhc_data_t *dataConfig, + uint32_t flags) +{ + assert(NULL != dmaConfig); + assert((NULL != dmaConfig->admaTable) && + (((USDHC_ADMA_TABLE_ADDRESS_ALIGN - 1U) & (uint32_t)dmaConfig->admaTable) == 0U)); + assert(NULL != dataConfig); + + status_t error = kStatus_Fail; + uint32_t bootDummyOffset = dataConfig->dataType == kUSDHC_TransferDataBootcontinous ? sizeof(uint32_t) : 0U; + const uint32_t *data = + (const uint32_t *)((uint32_t)((dataConfig->rxData == NULL) ? dataConfig->txData : dataConfig->rxData) + + bootDummyOffset); + uint32_t blockSize = dataConfig->blockSize * dataConfig->blockCount - bootDummyOffset; + + switch (dmaConfig->dmaMode) + { +#if FSL_FEATURE_USDHC_HAS_EXT_DMA + case kUSDHC_ExternalDMA: + /* enable the external DMA */ + base->VEND_SPEC |= USDHC_VEND_SPEC_EXT_DMA_EN_MASK; + break; +#endif + case kUSDHC_DmaModeSimple: + error = kStatus_Success; + break; + + case kUSDHC_DmaModeAdma1: + error = USDHC_SetADMA1Descriptor(dmaConfig->admaTable, dmaConfig->admaTableWords, data, blockSize, flags); + break; + + case kUSDHC_DmaModeAdma2: + error = USDHC_SetADMA2Descriptor(dmaConfig->admaTable, dmaConfig->admaTableWords, data, blockSize, flags); + break; + default: + return kStatus_USDHC_PrepareAdmaDescriptorFailed; + } + + /* for internal dma, internal DMA configurations should not update the configurations when continous transfer the + * boot data, only the DMA descriptor need update */ + if ((dmaConfig->dmaMode != kUSDHC_ExternalDMA) && (error == kStatus_Success) && + (dataConfig->dataType != kUSDHC_TransferDataBootcontinous)) + { + error = USDHC_SetInternalDmaConfig(base, dmaConfig, data, dataConfig->enableAutoCommand23); + } + + return error; +} + +/*! + * brief Transfers the command/data using a blocking method. + * + * This function waits until the command response/data is received or the USDHC encounters an error by polling the + * status + * flag. + * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support + * the re-entry mechanism. + * + * note There is no need to call the API 'USDHC_TransferCreateHandle' when calling this API. + * + * param base USDHC peripheral base address. + * param adma configuration + * param transfer Transfer content. + * retval kStatus_InvalidArgument Argument is invalid. + * retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * retval kStatus_USDHC_SendCommandFailed Send command failed. + * retval kStatus_USDHC_TransferDataFailed Transfer data failed. + * retval kStatus_Success Operate successfully. + */ +status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer) +{ + assert(transfer); + + status_t error = kStatus_Fail; + usdhc_command_t *command = transfer->command; + usdhc_data_t *data = transfer->data; + bool enDMA = true; + bool executeTuning = ((data == NULL) ? false : data->dataType == kUSDHC_TransferDataTuning); + + /*check re-tuning request*/ + if ((USDHC_GetInterruptStatusFlags(base) & kUSDHC_ReTuningEventFlag) != 0U) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_ReTuningEventFlag); + return kStatus_USDHC_ReTuningRequest; + } + + /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/ + if ((data != NULL) && (dmaConfig != NULL) && (!executeTuning)) + { + error = + USDHC_SetAdmaTableConfig(base, dmaConfig, data, + (data->dataType & kUSDHC_TransferDataBoot) ? kUSDHC_AdmaDescriptorMultipleFlag : + kUSDHC_AdmaDescriptorSingleFlag); + } + + /* if the DMA desciptor configure fail or not needed , disable it */ + if (error != kStatus_Success) + { + enDMA = false; + /* disable DMA, using polling mode in this situation */ + USDHC_EnableInternalDMA(base, false); + } +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + else + { + if (data->txData != NULL) + { + /* clear the DCACHE */ + DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount)); + } + else + { + /* clear the DCACHE */ + DCACHE_CleanInvalidateByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); + } + } +#endif + + /* config the data transfer parameter */ + error = USDHC_SetDataTransferConfig(base, data, &(command->flags), enDMA); + if (kStatus_Success != error) + { + return error; + } + /* send command first */ + USDHC_SendCommand(base, command); + /* wait command done */ + error = USDHC_WaitCommandDone(base, command, (data == NULL) || (data->dataType == kUSDHC_TransferDataNormal)); + + /* wait transfer data finsih */ + if ((data != NULL) && (error == kStatus_Success)) + { + return USDHC_TransferDataBlocking(base, data, enDMA); + } + + return error; +} + +/*! + * brief Transfers the command/data using an interrupt and an asynchronous method. + * + * This function sends a command and data and returns immediately. It doesn't wait the transfer complete or encounter an + * error. + * The application must not call this API in multiple threads at the same time. Because of that this API doesn't support + * the re-entry mechanism. + * + * note Call the API 'USDHC_TransferCreateHandle' when calling this API. + * + * param base USDHC peripheral base address. + * param handle USDHC handle. + * param adma configuration. + * param transfer Transfer content. + * retval kStatus_InvalidArgument Argument is invalid. + * retval kStatus_USDHC_BusyTransferring Busy transferring. + * retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * retval kStatus_Success Operate successfully. + */ +status_t USDHC_TransferNonBlocking(USDHC_Type *base, + usdhc_handle_t *handle, + usdhc_adma_config_t *dmaConfig, + usdhc_transfer_t *transfer) +{ + assert(handle); + assert(transfer); + + status_t error = kStatus_Fail; + usdhc_command_t *command = transfer->command; + usdhc_data_t *data = transfer->data; + bool executeTuning = ((data == NULL) ? false : data->dataType == kUSDHC_TransferDataTuning); + bool enDMA = true; + + /*check re-tuning request*/ + if ((USDHC_GetInterruptStatusFlags(base) & (kUSDHC_ReTuningEventFlag)) != 0U) + { + USDHC_ClearInterruptStatusFlags(base, kUSDHC_ReTuningEventFlag); + return kStatus_USDHC_ReTuningRequest; + } + + /* Save command and data into handle before transferring. */ + + handle->command = command; + handle->data = data; + /* transferredWords will only be updated in ISR when transfer way is DATAPORT. */ + handle->transferredWords = 0U; + + /* Update ADMA descriptor table according to different DMA mode(no DMA, ADMA1, ADMA2).*/ + if ((data != NULL) && (dmaConfig != NULL) && (!executeTuning)) + { + error = + USDHC_SetAdmaTableConfig(base, dmaConfig, data, + (data->dataType & kUSDHC_TransferDataBoot) ? kUSDHC_AdmaDescriptorMultipleFlag : + kUSDHC_AdmaDescriptorSingleFlag); + } + + /* if the DMA desciptor configure fail or not needed , disable it */ + if (error != kStatus_Success) + { + /* disable DMA, using polling mode in this situation */ + USDHC_EnableInternalDMA(base, false); + enDMA = false; + } +#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + else + { + if (data->txData != NULL) + { + /* clear the DCACHE */ + DCACHE_CleanByRange((uint32_t)data->txData, (data->blockSize) * (data->blockCount)); + } + else + { + /* clear the DCACHE */ + DCACHE_CleanInvalidateByRange((uint32_t)data->rxData, (data->blockSize) * (data->blockCount)); + } + } +#endif + + error = USDHC_SetDataTransferConfig(base, data, &(command->flags), enDMA); + if (kStatus_Success != error) + { + return error; + } + + /* send command first */ + USDHC_SendCommand(base, command); + + return kStatus_Success; +} + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (FSL_FEATURE_USDHC_HAS_SDR50_MODE) +/*! + * brief manual tuning trigger or abort + * User should handle the tuning cmd and find the boundary of the delay + * then calucate a average value which will be config to the CLK_TUNE_CTRL_STATUS + * This function should called before USDHC_AdjustDelayforSDR104 function + * param base USDHC peripheral base address. + * param tuning enable flag + */ +void USDHC_EnableManualTuning(USDHC_Type *base, bool enable) +{ + if (enable) + { + /* make sure std_tun_en bit is clear */ + base->TUNING_CTRL &= ~USDHC_TUNING_CTRL_STD_TUNING_EN_MASK; + /* disable auto tuning here */ + base->MIX_CTRL &= ~USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; + /* execute tuning for SDR104 mode */ + base->MIX_CTRL |= + USDHC_MIX_CTRL_EXE_TUNE_MASK | USDHC_MIX_CTRL_SMP_CLK_SEL_MASK | USDHC_MIX_CTRL_FBCLK_SEL_MASK; + } + else + { /* abort the tuning */ + base->MIX_CTRL &= ~(USDHC_MIX_CTRL_EXE_TUNE_MASK | USDHC_MIX_CTRL_SMP_CLK_SEL_MASK); + } +} + +/*! + * brief the SDR104 mode delay setting adjust + * This function should called after USDHC_ManualTuningForSDR104 + * param base USDHC peripheral base address. + * param delay setting configuration + * retval kStatus_Fail config the delay setting fail + * retval kStatus_Success config the delay setting success + */ +status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay) +{ + uint32_t clkTuneCtrl = 0U; + + clkTuneCtrl = base->CLK_TUNE_CTRL_STATUS; + + clkTuneCtrl &= ~USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK; + + clkTuneCtrl |= USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(delay); + + /* load the delay setting */ + base->CLK_TUNE_CTRL_STATUS = clkTuneCtrl; + /* check delat setting error */ + if (base->CLK_TUNE_CTRL_STATUS & + (USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK | USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)) + { + return kStatus_Fail; + } + + return kStatus_Success; +} + +/*! + * brief the enable standard tuning function + * The standard tuning window and tuning counter use the default config + * tuning cmd is send by the software, user need to check the tuning result + * can be used for SDR50,SDR104,HS200 mode tuning + * param base USDHC peripheral base address. + * param tuning start tap + * param tuning step + * param enable/disable flag + */ +void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enable) +{ + uint32_t tuningCtrl = 0U; + + if (enable) + { + /* feedback clock */ + base->MIX_CTRL |= USDHC_MIX_CTRL_FBCLK_SEL_MASK; + /* config tuning start and step */ + tuningCtrl = base->TUNING_CTRL; + tuningCtrl &= ~(USDHC_TUNING_CTRL_TUNING_START_TAP_MASK | USDHC_TUNING_CTRL_TUNING_STEP_MASK); + tuningCtrl |= (USDHC_TUNING_CTRL_TUNING_START_TAP(tuningStartTap) | USDHC_TUNING_CTRL_TUNING_STEP(step) | + USDHC_TUNING_CTRL_STD_TUNING_EN_MASK); + base->TUNING_CTRL = tuningCtrl; + + /* excute tuning */ + base->AUTOCMD12_ERR_STATUS |= + (USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK); + } + else + { + /* disable the standard tuning */ + base->TUNING_CTRL &= ~USDHC_TUNING_CTRL_STD_TUNING_EN_MASK; + /* clear excute tuning */ + base->AUTOCMD12_ERR_STATUS &= + ~(USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK | USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK); + } +} + +/*! + * brief the auto tuning enbale for CMD/DATA line + * + * param base USDHC peripheral base address. + */ +void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base) +{ + uint32_t busWidth = 0U; + + base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK; + busWidth = (base->PROT_CTRL & USDHC_PROT_CTRL_DTW_MASK) >> USDHC_PROT_CTRL_DTW_SHIFT; + if (busWidth == kUSDHC_DataBusWidth1Bit) + { + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK; + base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK; + } + else if (busWidth == kUSDHC_DataBusWidth4Bit) + { + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK; + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK; + } + else if (busWidth == kUSDHC_DataBusWidth8Bit) + { + base->VEND_SPEC2 |= USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK; + base->VEND_SPEC2 &= ~USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK; + } + else + { + } +} +#endif /* FSL_FEATURE_USDHC_HAS_SDR50_MODE */ + +static void USDHC_TransferHandleCardDetect(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) +{ + if (interruptFlags & kUSDHC_CardInsertionFlag) + { + if (handle->callback.CardInserted) + { + handle->callback.CardInserted(base, handle->userData); + } + } + else + { + if (handle->callback.CardRemoved) + { + handle->callback.CardRemoved(base, handle->userData); + } + } +} + +static void USDHC_TransferHandleCommand(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) +{ + assert(handle->command); + + if (interruptFlags & kUSDHC_CommandErrorFlag) + { + if (handle->callback.TransferComplete) + { + handle->callback.TransferComplete(base, handle, kStatus_USDHC_SendCommandFailed, handle->userData); + } + } + else + { + /* Receive response */ + if (kStatus_Success != USDHC_ReceiveCommandResponse(base, handle->command)) + { + if (handle->callback.TransferComplete) + { + handle->callback.TransferComplete(base, handle, kStatus_USDHC_SendCommandFailed, handle->userData); + } + } + else if ((!(handle->data)) && (handle->callback.TransferComplete)) + { + if (handle->callback.TransferComplete) + { + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } + } + else + { + } + } +} + +static void USDHC_TransferHandleData(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) +{ + assert(handle->data); + + if ((!(handle->data->enableIgnoreError)) && ((interruptFlags & (kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag)))) + { + if (handle->callback.TransferComplete) + { + handle->callback.TransferComplete(base, handle, kStatus_USDHC_TransferDataFailed, handle->userData); + } + } + else + { + if (interruptFlags & kUSDHC_BufferReadReadyFlag) + { + /* std tuning process only need to wait BRR */ + if (handle->data->dataType == kUSDHC_TransferDataTuning) + { + if (handle->callback.TransferComplete) + { + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } + } + else + { + handle->transferredWords = USDHC_ReadDataPort(base, handle->data, handle->transferredWords); + } + } + else if (interruptFlags & kUSDHC_BufferWriteReadyFlag) + { + handle->transferredWords = USDHC_WriteDataPort(base, handle->data, handle->transferredWords); + } + else + { + if ((interruptFlags & kUSDHC_DmaCompleteFlag) && + (handle->data->dataType == kUSDHC_TransferDataBootcontinous)) + { + *(handle->data->rxData) = s_usdhcBootDummy; + } + + if ((handle->callback.TransferComplete) && (interruptFlags & kUSDHC_DataCompleteFlag)) + { + handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + } + } + } +} + +static void USDHC_TransferHandleSdioInterrupt(USDHC_Type *base, usdhc_handle_t *handle) +{ + if (handle->callback.SdioInterrupt) + { + handle->callback.SdioInterrupt(base, handle->userData); + } +} + +static void USDHC_TransferHandleReTuning(USDHC_Type *base, usdhc_handle_t *handle, uint32_t interruptFlags) +{ + assert(handle->callback.ReTuning); + /* retuning request */ + if ((interruptFlags & kUSDHC_TuningErrorFlag) == kUSDHC_TuningErrorFlag) + { + handle->callback.ReTuning(base, handle->userData); /* retuning fail */ + } +} + +static void USDHC_TransferHandleBlockGap(USDHC_Type *base, usdhc_handle_t *handle) +{ + if (handle->callback.BlockGap) + { + handle->callback.BlockGap(base, handle->userData); + } +} + +/*! + * brief Creates the USDHC handle. + * + * param base USDHC peripheral base address. + * param handle USDHC handle pointer. + * param callback Structure pointer to contain all callback functions. + * param userData Callback function parameter. + */ +void USDHC_TransferCreateHandle(USDHC_Type *base, + usdhc_handle_t *handle, + const usdhc_transfer_callback_t *callback, + void *userData) +{ + assert(handle); + assert(callback); + + /* Zero the handle. */ + memset(handle, 0, sizeof(*handle)); + + /* Set the callback. */ + handle->callback.CardInserted = callback->CardInserted; + handle->callback.CardRemoved = callback->CardRemoved; + handle->callback.SdioInterrupt = callback->SdioInterrupt; + handle->callback.BlockGap = callback->BlockGap; + handle->callback.TransferComplete = callback->TransferComplete; + handle->callback.ReTuning = callback->ReTuning; + handle->userData = userData; + + /* Save the handle in global variables to support the double weak mechanism. */ + s_usdhcHandle[USDHC_GetInstance(base)] = handle; + + /* Enable interrupt in NVIC. */ + USDHC_SetTransferInterrupt(base, true); + /* save IRQ handler */ + s_usdhcIsr = USDHC_TransferHandleIRQ; + + EnableIRQ(s_usdhcIRQ[USDHC_GetInstance(base)]); +} + +/*! + * brief IRQ handler for the USDHC. + * + * This function deals with the IRQs on the given host controller. + * + * param base USDHC peripheral base address. + * param handle USDHC handle. + */ +void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle) +{ + assert(handle); + + uint32_t interruptFlags; + + interruptFlags = USDHC_GetEnabledInterruptStatusFlags(base); + + if (interruptFlags & kUSDHC_CardDetectFlag) + { + USDHC_TransferHandleCardDetect(base, handle, (interruptFlags & kUSDHC_CardDetectFlag)); + } + if (interruptFlags & kUSDHC_CommandFlag) + { + USDHC_TransferHandleCommand(base, handle, (interruptFlags & kUSDHC_CommandFlag)); + } + if (interruptFlags & kUSDHC_DataFlag) + { + USDHC_TransferHandleData(base, handle, (interruptFlags & kUSDHC_DataFlag)); + } + if (interruptFlags & kUSDHC_CardInterruptFlag) + { + USDHC_TransferHandleSdioInterrupt(base, handle); + } + if (interruptFlags & kUSDHC_BlockGapEventFlag) + { + USDHC_TransferHandleBlockGap(base, handle); + } + if (interruptFlags & kUSDHC_SDR104TuningFlag) + { + USDHC_TransferHandleReTuning(base, handle, (interruptFlags & kUSDHC_SDR104TuningFlag)); + } + USDHC_ClearInterruptStatusFlags(base, interruptFlags); +} + +#ifdef USDHC0 +void USDHC0_DriverIRQHandler(void) +{ + s_usdhcIsr(s_usdhcBase[0U], s_usdhcHandle[0U]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#ifdef USDHC1 +void USDHC1_DriverIRQHandler(void) +{ + s_usdhcIsr(s_usdhcBase[1U], s_usdhcHandle[1U]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#ifdef USDHC2 +void USDHC2_DriverIRQHandler(void) +{ + s_usdhcIsr(s_usdhcBase[2U], s_usdhcHandle[2U]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#endif diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_usdhc.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_usdhc.h new file mode 100644 index 0000000000..acf33a1f0b --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_usdhc.h @@ -0,0 +1,1493 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_USDHC_H_ +#define _FSL_USDHC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup usdhc + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.2.8. */ +#define FSL_USDHC_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 8U)) +/*@}*/ + +/*! @brief Maximum block count can be set one time */ +#define USDHC_MAX_BLOCK_COUNT (USDHC_BLK_ATT_BLKCNT_MASK >> USDHC_BLK_ATT_BLKCNT_SHIFT) + +/*! @brief USDHC status */ +enum _usdhc_status +{ + kStatus_USDHC_BusyTransferring = MAKE_STATUS(kStatusGroup_USDHC, 0U), /*!< Transfer is on-going */ + kStatus_USDHC_PrepareAdmaDescriptorFailed = MAKE_STATUS(kStatusGroup_USDHC, 1U), /*!< Set DMA descriptor failed */ + kStatus_USDHC_SendCommandFailed = MAKE_STATUS(kStatusGroup_USDHC, 2U), /*!< Send command failed */ + kStatus_USDHC_TransferDataFailed = MAKE_STATUS(kStatusGroup_USDHC, 3U), /*!< Transfer data failed */ + kStatus_USDHC_DMADataAddrNotAlign = MAKE_STATUS(kStatusGroup_USDHC, 4U), /*!< data address not align */ + kStatus_USDHC_ReTuningRequest = MAKE_STATUS(kStatusGroup_USDHC, 5U), /*!< re-tuning request */ + kStatus_USDHC_TuningError = MAKE_STATUS(kStatusGroup_USDHC, 6U), /*!< tuning error */ + kStatus_USDHC_NotSupport = MAKE_STATUS(kStatusGroup_USDHC, 7U), /*!< not support */ +}; + +/*! @brief Host controller capabilities flag mask */ +enum _usdhc_capability_flag +{ + kUSDHC_SupportAdmaFlag = USDHC_HOST_CTRL_CAP_ADMAS_MASK, /*!< Support ADMA */ + kUSDHC_SupportHighSpeedFlag = USDHC_HOST_CTRL_CAP_HSS_MASK, /*!< Support high-speed */ + kUSDHC_SupportDmaFlag = USDHC_HOST_CTRL_CAP_DMAS_MASK, /*!< Support DMA */ + kUSDHC_SupportSuspendResumeFlag = USDHC_HOST_CTRL_CAP_SRS_MASK, /*!< Support suspend/resume */ + kUSDHC_SupportV330Flag = USDHC_HOST_CTRL_CAP_VS33_MASK, /*!< Support voltage 3.3V */ + kUSDHC_SupportV300Flag = USDHC_HOST_CTRL_CAP_VS30_MASK, /*!< Support voltage 3.0V */ + kUSDHC_SupportV180Flag = USDHC_HOST_CTRL_CAP_VS18_MASK, /*!< Support voltage 1.8V */ + /* Put additional two flags in HTCAPBLT_MBL's position. */ + kUSDHC_Support4BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 0U), /*!< Support 4 bit mode */ + kUSDHC_Support8BitFlag = (USDHC_HOST_CTRL_CAP_MBL_SHIFT << 1U), /*!< Support 8 bit mode */ + /* sd version 3.0 new feature */ + kUSDHC_SupportDDR50Flag = USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK, /*!< support DDR50 mode */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR104_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR104_MODE) + kUSDHC_SupportSDR104Flag = 0, /*!< not support SDR104 mode */ +#else + kUSDHC_SupportSDR104Flag = USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK, /*!< support SDR104 mode */ +#endif +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_SupportSDR50Flag = 0U, /*!< not support SDR50 mode */ +#else + kUSDHC_SupportSDR50Flag = USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK, /*!< support SDR50 mode */ +#endif +}; + +/*! @brief Wakeup event mask */ +enum _usdhc_wakeup_event +{ + kUSDHC_WakeupEventOnCardInt = USDHC_PROT_CTRL_WECINT_MASK, /*!< Wakeup on card interrupt */ + kUSDHC_WakeupEventOnCardInsert = USDHC_PROT_CTRL_WECINS_MASK, /*!< Wakeup on card insertion */ + kUSDHC_WakeupEventOnCardRemove = USDHC_PROT_CTRL_WECRM_MASK, /*!< Wakeup on card removal */ + + kUSDHC_WakeupEventsAll = (kUSDHC_WakeupEventOnCardInt | kUSDHC_WakeupEventOnCardInsert | + kUSDHC_WakeupEventOnCardRemove), /*!< All wakeup events */ +}; + +/*! @brief Reset type mask */ +enum _usdhc_reset +{ + kUSDHC_ResetAll = USDHC_SYS_CTRL_RSTA_MASK, /*!< Reset all except card detection */ + kUSDHC_ResetCommand = USDHC_SYS_CTRL_RSTC_MASK, /*!< Reset command line */ + kUSDHC_ResetData = USDHC_SYS_CTRL_RSTD_MASK, /*!< Reset data line */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ResetTuning = 0U, /*!< no reset tuning circuit bit */ +#else + kUSDHC_ResetTuning = USDHC_SYS_CTRL_RSTT_MASK, /*!< reset tuning circuit */ +#endif + + kUSDHC_ResetsAll = + (kUSDHC_ResetAll | kUSDHC_ResetCommand | kUSDHC_ResetData | kUSDHC_ResetTuning), /*!< All reset types */ +}; + +/*! @brief Transfer flag mask */ +enum _usdhc_transfer_flag +{ + kUSDHC_EnableDmaFlag = USDHC_MIX_CTRL_DMAEN_MASK, /*!< Enable DMA */ + + kUSDHC_CommandTypeSuspendFlag = (USDHC_CMD_XFR_TYP_CMDTYP(1U)), /*!< Suspend command */ + kUSDHC_CommandTypeResumeFlag = (USDHC_CMD_XFR_TYP_CMDTYP(2U)), /*!< Resume command */ + kUSDHC_CommandTypeAbortFlag = (USDHC_CMD_XFR_TYP_CMDTYP(3U)), /*!< Abort command */ + + kUSDHC_EnableBlockCountFlag = USDHC_MIX_CTRL_BCEN_MASK, /*!< Enable block count */ + kUSDHC_EnableAutoCommand12Flag = USDHC_MIX_CTRL_AC12EN_MASK, /*!< Enable auto CMD12 */ + kUSDHC_DataReadFlag = USDHC_MIX_CTRL_DTDSEL_MASK, /*!< Enable data read */ + kUSDHC_MultipleBlockFlag = USDHC_MIX_CTRL_MSBSEL_MASK, /*!< Multiple block data read/write */ + kUSDHC_EnableAutoCommand23Flag = USDHC_MIX_CTRL_AC23EN_MASK, /*!< Enable auto CMD23 */ + + kUSDHC_ResponseLength136Flag = USDHC_CMD_XFR_TYP_RSPTYP(1U), /*!< 136 bit response length */ + kUSDHC_ResponseLength48Flag = USDHC_CMD_XFR_TYP_RSPTYP(2U), /*!< 48 bit response length */ + kUSDHC_ResponseLength48BusyFlag = USDHC_CMD_XFR_TYP_RSPTYP(3U), /*!< 48 bit response length with busy status */ + + kUSDHC_EnableCrcCheckFlag = USDHC_CMD_XFR_TYP_CCCEN_MASK, /*!< Enable CRC check */ + kUSDHC_EnableIndexCheckFlag = USDHC_CMD_XFR_TYP_CICEN_MASK, /*!< Enable index check */ + kUSDHC_DataPresentFlag = USDHC_CMD_XFR_TYP_DPSEL_MASK, /*!< Data present flag */ +}; + +/*! @brief Present status flag mask */ +enum _usdhc_present_status_flag +{ + kUSDHC_CommandInhibitFlag = USDHC_PRES_STATE_CIHB_MASK, /*!< Command inhibit */ + kUSDHC_DataInhibitFlag = USDHC_PRES_STATE_CDIHB_MASK, /*!< Data inhibit */ + kUSDHC_DataLineActiveFlag = USDHC_PRES_STATE_DLA_MASK, /*!< Data line active */ + kUSDHC_SdClockStableFlag = USDHC_PRES_STATE_SDSTB_MASK, /*!< SD bus clock stable */ + kUSDHC_WriteTransferActiveFlag = USDHC_PRES_STATE_WTA_MASK, /*!< Write transfer active */ + kUSDHC_ReadTransferActiveFlag = USDHC_PRES_STATE_RTA_MASK, /*!< Read transfer active */ + kUSDHC_BufferWriteEnableFlag = USDHC_PRES_STATE_BWEN_MASK, /*!< Buffer write enable */ + kUSDHC_BufferReadEnableFlag = USDHC_PRES_STATE_BREN_MASK, /*!< Buffer read enable */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_DelaySettingFinishedFlag = 0U, /*!< not support */ + kUSDHC_ReTuningRequestFlag = 0U, /*!< not support */ +#else + kUSDHC_ReTuningRequestFlag = USDHC_PRES_STATE_RTR_MASK, /*!< re-tuning request flag ,only used for SDR104 mode */ + kUSDHC_DelaySettingFinishedFlag = USDHC_PRES_STATE_TSCD_MASK, /*!< delay setting finished flag */ +#endif + + kUSDHC_CardInsertedFlag = USDHC_PRES_STATE_CINST_MASK, /*!< Card inserted */ + kUSDHC_CommandLineLevelFlag = USDHC_PRES_STATE_CLSL_MASK, /*!< Command line signal level */ + + kUSDHC_Data0LineLevelFlag = 1U << USDHC_PRES_STATE_DLSL_SHIFT, /*!< Data0 line signal level */ + kUSDHC_Data1LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 1U), /*!< Data1 line signal level */ + kUSDHC_Data2LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 2U), /*!< Data2 line signal level */ + kUSDHC_Data3LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 3U), /*!< Data3 line signal level */ + kUSDHC_Data4LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 4U), /*!< Data4 line signal level */ + kUSDHC_Data5LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 5U), /*!< Data5 line signal level */ + kUSDHC_Data6LineLevelFlag = 1U << (USDHC_PRES_STATE_DLSL_SHIFT + 6U), /*!< Data6 line signal level */ + kUSDHC_Data7LineLevelFlag = (int)(1U << (USDHC_PRES_STATE_DLSL_SHIFT + 7U)), /*!< Data7 line signal level */ +}; + +/*! @brief Interrupt status flag mask */ +enum _usdhc_interrupt_status_flag +{ + kUSDHC_CommandCompleteFlag = USDHC_INT_STATUS_CC_MASK, /*!< Command complete */ + kUSDHC_DataCompleteFlag = USDHC_INT_STATUS_TC_MASK, /*!< Data complete */ + kUSDHC_BlockGapEventFlag = USDHC_INT_STATUS_BGE_MASK, /*!< Block gap event */ + kUSDHC_DmaCompleteFlag = USDHC_INT_STATUS_DINT_MASK, /*!< DMA interrupt */ + kUSDHC_BufferWriteReadyFlag = USDHC_INT_STATUS_BWR_MASK, /*!< Buffer write ready */ + kUSDHC_BufferReadReadyFlag = USDHC_INT_STATUS_BRR_MASK, /*!< Buffer read ready */ + kUSDHC_CardInsertionFlag = USDHC_INT_STATUS_CINS_MASK, /*!< Card inserted */ + kUSDHC_CardRemovalFlag = USDHC_INT_STATUS_CRM_MASK, /*!< Card removed */ + kUSDHC_CardInterruptFlag = USDHC_INT_STATUS_CINT_MASK, /*!< Card interrupt */ + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ReTuningEventFlag = 0U, /*!< Re-Tuning event,only for SD3.0 SDR104 mode */ + kUSDHC_TuningPassFlag = 0U, /*!< SDR104 mode tuning pass flag */ + kUSDHC_TuningErrorFlag = 0U, /*!< SDR104 tuning error flag */ +#else + kUSDHC_ReTuningEventFlag = USDHC_INT_STATUS_RTE_MASK, /*!< Re-Tuning event,only for SD3.0 SDR104 mode */ + kUSDHC_TuningPassFlag = USDHC_INT_STATUS_TP_MASK, /*!< SDR104 mode tuning pass flag */ + kUSDHC_TuningErrorFlag = USDHC_INT_STATUS_TNE_MASK, /*!< SDR104 tuning error flag */ +#endif + + kUSDHC_CommandTimeoutFlag = USDHC_INT_STATUS_CTOE_MASK, /*!< Command timeout error */ + kUSDHC_CommandCrcErrorFlag = USDHC_INT_STATUS_CCE_MASK, /*!< Command CRC error */ + kUSDHC_CommandEndBitErrorFlag = USDHC_INT_STATUS_CEBE_MASK, /*!< Command end bit error */ + kUSDHC_CommandIndexErrorFlag = USDHC_INT_STATUS_CIE_MASK, /*!< Command index error */ + kUSDHC_DataTimeoutFlag = USDHC_INT_STATUS_DTOE_MASK, /*!< Data timeout error */ + kUSDHC_DataCrcErrorFlag = USDHC_INT_STATUS_DCE_MASK, /*!< Data CRC error */ + kUSDHC_DataEndBitErrorFlag = USDHC_INT_STATUS_DEBE_MASK, /*!< Data end bit error */ + kUSDHC_AutoCommand12ErrorFlag = USDHC_INT_STATUS_AC12E_MASK, /*!< Auto CMD12 error */ + kUSDHC_DmaErrorFlag = USDHC_INT_STATUS_DMAE_MASK, /*!< DMA error */ + + kUSDHC_CommandErrorFlag = (kUSDHC_CommandTimeoutFlag | kUSDHC_CommandCrcErrorFlag | kUSDHC_CommandEndBitErrorFlag | + kUSDHC_CommandIndexErrorFlag), /*!< Command error */ + kUSDHC_DataErrorFlag = (kUSDHC_DataTimeoutFlag | kUSDHC_DataCrcErrorFlag | kUSDHC_DataEndBitErrorFlag | + kUSDHC_AutoCommand12ErrorFlag), /*!< Data error */ + kUSDHC_ErrorFlag = (kUSDHC_CommandErrorFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), /*!< All error */ + kUSDHC_DataFlag = (kUSDHC_DataCompleteFlag | kUSDHC_DmaCompleteFlag | kUSDHC_BufferWriteReadyFlag | + kUSDHC_BufferReadReadyFlag | kUSDHC_DataErrorFlag | kUSDHC_DmaErrorFlag), /*!< Data interrupts */ + kUSDHC_CommandFlag = (kUSDHC_CommandErrorFlag | kUSDHC_CommandCompleteFlag), /*!< Command interrupts */ + kUSDHC_CardDetectFlag = (kUSDHC_CardInsertionFlag | kUSDHC_CardRemovalFlag), /*!< Card detection interrupts */ + kUSDHC_SDR104TuningFlag = (kUSDHC_TuningErrorFlag | kUSDHC_TuningPassFlag | kUSDHC_ReTuningEventFlag), + + kUSDHC_AllInterruptFlags = (kUSDHC_BlockGapEventFlag | kUSDHC_CardInterruptFlag | kUSDHC_CommandFlag | + kUSDHC_DataFlag | kUSDHC_ErrorFlag | kUSDHC_SDR104TuningFlag), /*!< All flags mask */ +}; + +/*! @brief Auto CMD12 error status flag mask */ +enum _usdhc_auto_command12_error_status_flag +{ + kUSDHC_AutoCommand12NotExecutedFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK, /*!< Not executed error */ + kUSDHC_AutoCommand12TimeoutFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK, /*!< Timeout error */ + kUSDHC_AutoCommand12EndBitErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK, /*!< End bit error */ + kUSDHC_AutoCommand12CrcErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK, /*!< CRC error */ + kUSDHC_AutoCommand12IndexErrorFlag = USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK, /*!< Index error */ + kUSDHC_AutoCommand12NotIssuedFlag = USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK, /*!< Not issued error */ +}; + +/*! @brief standard tuning flag */ +enum _usdhc_standard_tuning +{ +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ExecuteTuning = 0U, /*!< not support */ + kUSDHC_TuningSampleClockSel = 0U, /*!< not support */ +#else + kUSDHC_ExecuteTuning = USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK, /*!< used to start tuning procedure */ + kUSDHC_TuningSampleClockSel = USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK, /*!< when std_tuning_en bit is set, this + bit is used select sampleing clock */ +#endif +}; + +/*! @brief ADMA error status flag mask */ +enum _usdhc_adma_error_status_flag +{ + kUSDHC_AdmaLenghMismatchFlag = USDHC_ADMA_ERR_STATUS_ADMALME_MASK, /*!< Length mismatch error */ + kUSDHC_AdmaDescriptorErrorFlag = USDHC_ADMA_ERR_STATUS_ADMADCE_MASK, /*!< Descriptor error */ +}; + +/*! + * @brief ADMA error state + * + * This state is the detail state when ADMA error has occurred. + */ +enum _usdhc_adma_error_state +{ + kUSDHC_AdmaErrorStateStopDma = + 0x00U, /*!< Stop DMA, previous location set in the ADMA system address is error address */ + kUSDHC_AdmaErrorStateFetchDescriptor = + 0x01U, /*!< Fetch descriptor, current location set in the ADMA system address is error address */ + kUSDHC_AdmaErrorStateChangeAddress = 0x02U, /*!< Change address, no DMA error is occurred */ + kUSDHC_AdmaErrorStateTransferData = + 0x03U, /*!< Transfer data, previous location set in the ADMA system address is error address */ + kUSDHC_AdmaErrorStateInvalidLength = 0x04U, /*!< Invalid length in ADMA descriptor */ + kUSDHC_AdmaErrorStateInvalidDescriptor = 0x08U, /*!< Invalid descriptor fetched by ADMA */ + + kUSDHC_AdmaErrorState = kUSDHC_AdmaErrorStateInvalidLength | kUSDHC_AdmaErrorStateInvalidDescriptor | + kUSDHC_AdmaErrorStateFetchDescriptor, /*!< ADMA error state */ +}; + +/*! @brief Force event bit position */ +enum _usdhc_force_event +{ + kUSDHC_ForceEventAutoCommand12NotExecuted = USDHC_FORCE_EVENT_FEVTAC12NE_MASK, /*!< Auto CMD12 not executed error */ + kUSDHC_ForceEventAutoCommand12Timeout = USDHC_FORCE_EVENT_FEVTAC12TOE_MASK, /*!< Auto CMD12 timeout error */ + kUSDHC_ForceEventAutoCommand12CrcError = USDHC_FORCE_EVENT_FEVTAC12CE_MASK, /*!< Auto CMD12 CRC error */ + kUSDHC_ForceEventEndBitError = USDHC_FORCE_EVENT_FEVTAC12EBE_MASK, /*!< Auto CMD12 end bit error */ + kUSDHC_ForceEventAutoCommand12IndexError = USDHC_FORCE_EVENT_FEVTAC12IE_MASK, /*!< Auto CMD12 index error */ + kUSDHC_ForceEventAutoCommand12NotIssued = USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK, /*!< Auto CMD12 not issued error */ + kUSDHC_ForceEventCommandTimeout = USDHC_FORCE_EVENT_FEVTCTOE_MASK, /*!< Command timeout error */ + kUSDHC_ForceEventCommandCrcError = USDHC_FORCE_EVENT_FEVTCCE_MASK, /*!< Command CRC error */ + kUSDHC_ForceEventCommandEndBitError = USDHC_FORCE_EVENT_FEVTCEBE_MASK, /*!< Command end bit error */ + kUSDHC_ForceEventCommandIndexError = USDHC_FORCE_EVENT_FEVTCIE_MASK, /*!< Command index error */ + kUSDHC_ForceEventDataTimeout = USDHC_FORCE_EVENT_FEVTDTOE_MASK, /*!< Data timeout error */ + kUSDHC_ForceEventDataCrcError = USDHC_FORCE_EVENT_FEVTDCE_MASK, /*!< Data CRC error */ + kUSDHC_ForceEventDataEndBitError = USDHC_FORCE_EVENT_FEVTDEBE_MASK, /*!< Data end bit error */ + kUSDHC_ForceEventAutoCommand12Error = USDHC_FORCE_EVENT_FEVTAC12E_MASK, /*!< Auto CMD12 error */ + kUSDHC_ForceEventCardInt = (int)USDHC_FORCE_EVENT_FEVTCINT_MASK, /*!< Card interrupt */ + kUSDHC_ForceEventDmaError = USDHC_FORCE_EVENT_FEVTDMAE_MASK, /*!< Dma error */ +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) + kUSDHC_ForceEventTuningError = 0U, /*!< not support */ +#else + kUSDHC_ForceEventTuningError = USDHC_FORCE_EVENT_FEVTTNE_MASK, /*!< Tuning error */ +#endif + + kUSDHC_ForceEventsAll = + (int)(USDHC_FORCE_EVENT_FEVTAC12NE_MASK | USDHC_FORCE_EVENT_FEVTAC12TOE_MASK | + USDHC_FORCE_EVENT_FEVTAC12CE_MASK | USDHC_FORCE_EVENT_FEVTAC12EBE_MASK | + USDHC_FORCE_EVENT_FEVTAC12IE_MASK | USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK | + USDHC_FORCE_EVENT_FEVTCTOE_MASK | USDHC_FORCE_EVENT_FEVTCCE_MASK | USDHC_FORCE_EVENT_FEVTCEBE_MASK | + USDHC_FORCE_EVENT_FEVTCIE_MASK | USDHC_FORCE_EVENT_FEVTDTOE_MASK | USDHC_FORCE_EVENT_FEVTDCE_MASK | + USDHC_FORCE_EVENT_FEVTDEBE_MASK | USDHC_FORCE_EVENT_FEVTAC12E_MASK | USDHC_FORCE_EVENT_FEVTCINT_MASK | + USDHC_FORCE_EVENT_FEVTDMAE_MASK | kUSDHC_ForceEventTuningError), /*!< All force event flags mask */ +}; + +/*! @brief Data transfer width */ +typedef enum _usdhc_data_bus_width +{ + kUSDHC_DataBusWidth1Bit = 0U, /*!< 1-bit mode */ + kUSDHC_DataBusWidth4Bit = 1U, /*!< 4-bit mode */ + kUSDHC_DataBusWidth8Bit = 2U, /*!< 8-bit mode */ +} usdhc_data_bus_width_t; + +/*! @brief Endian mode */ +typedef enum _usdhc_endian_mode +{ + kUSDHC_EndianModeBig = 0U, /*!< Big endian mode */ + kUSDHC_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */ + kUSDHC_EndianModeLittle = 2U, /*!< Little endian mode */ +} usdhc_endian_mode_t; + +/*! @brief DMA mode */ +typedef enum _usdhc_dma_mode +{ + kUSDHC_DmaModeSimple = 0U, /*!< external DMA */ + kUSDHC_DmaModeAdma1 = 1U, /*!< ADMA1 is selected */ + kUSDHC_DmaModeAdma2 = 2U, /*!< ADMA2 is selected */ + kUSDHC_ExternalDMA = 3U, /*!< external dma mode select */ +} usdhc_dma_mode_t; + +/*! @brief SDIO control flag mask */ +enum _usdhc_sdio_control_flag +{ + kUSDHC_StopAtBlockGapFlag = USDHC_PROT_CTRL_SABGREQ_MASK, /*!< Stop at block gap */ + kUSDHC_ReadWaitControlFlag = USDHC_PROT_CTRL_RWCTL_MASK, /*!< Read wait control */ + kUSDHC_InterruptAtBlockGapFlag = USDHC_PROT_CTRL_IABG_MASK, /*!< Interrupt at block gap */ + kUSDHC_ReadDoneNo8CLK = USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK, /*!< read done without 8 clk for block gap */ + kUSDHC_ExactBlockNumberReadFlag = USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK, /*!< Exact block number read */ +}; + +/*! @brief MMC card boot mode */ +typedef enum _usdhc_boot_mode +{ + kUSDHC_BootModeNormal = 0U, /*!< Normal boot */ + kUSDHC_BootModeAlternative = 1U, /*!< Alternative boot */ +} usdhc_boot_mode_t; + +/*! @brief The command type */ +typedef enum _usdhc_card_command_type +{ + kCARD_CommandTypeNormal = 0U, /*!< Normal command */ + kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */ + kCARD_CommandTypeResume = 2U, /*!< Resume command */ + kCARD_CommandTypeAbort = 3U, /*!< Abort command */ + kCARD_CommandTypeEmpty = 4U, /*!< Empty command */ +} usdhc_card_command_type_t; + +/*! + * @brief The command response type. + * + * Define the command response type from card to host controller. + */ +typedef enum _usdhc_card_response_type +{ + kCARD_ResponseTypeNone = 0U, /*!< Response type: none */ + kCARD_ResponseTypeR1 = 1U, /*!< Response type: R1 */ + kCARD_ResponseTypeR1b = 2U, /*!< Response type: R1b */ + kCARD_ResponseTypeR2 = 3U, /*!< Response type: R2 */ + kCARD_ResponseTypeR3 = 4U, /*!< Response type: R3 */ + kCARD_ResponseTypeR4 = 5U, /*!< Response type: R4 */ + kCARD_ResponseTypeR5 = 6U, /*!< Response type: R5 */ + kCARD_ResponseTypeR5b = 7U, /*!< Response type: R5b */ + kCARD_ResponseTypeR6 = 8U, /*!< Response type: R6 */ + kCARD_ResponseTypeR7 = 9U, /*!< Response type: R7 */ +} usdhc_card_response_type_t; + +/*! @brief The alignment size for ADDRESS filed in ADMA1's descriptor */ +#define USDHC_ADMA1_ADDRESS_ALIGN (4096U) +/*! @brief The alignment size for LENGTH field in ADMA1's descriptor */ +#define USDHC_ADMA1_LENGTH_ALIGN (4096U) +/*! @brief The alignment size for ADDRESS field in ADMA2's descriptor */ +#define USDHC_ADMA2_ADDRESS_ALIGN (4U) +/*! @brief The alignment size for LENGTH filed in ADMA2's descriptor */ +#define USDHC_ADMA2_LENGTH_ALIGN (4U) + +/* ADMA1 descriptor table + * |------------------------|---------|--------------------------| + * | Address/page field |Reserved | Attribute | + * |------------------------|---------|--------------------------| + * |31 12|11 6|05 |04 |03|02 |01 |00 | + * |------------------------|---------|----|----|--|---|---|-----| + * | address or data length | 000000 |Act2|Act1| 0|Int|End|Valid| + * |------------------------|---------|----|----|--|---|---|-----| + * + * + * |------|------|-----------------|-------|-------------| + * | Act2 | Act1 | Comment | 31-28 | 27 - 12 | + * |------|------|-----------------|---------------------| + * | 0 | 0 | No op | Don't care | + * |------|------|-----------------|-------|-------------| + * | 0 | 1 | Set data length | 0000 | Data Length | + * |------|------|-----------------|-------|-------------| + * | 1 | 0 | Transfer data | Data address | + * |------|------|-----------------|---------------------| + * | 1 | 1 | Link descriptor | Descriptor address | + * |------|------|-----------------|---------------------| + */ +/*! @brief The bit shift for ADDRESS filed in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_ADDRESS_SHIFT (12U) +/*! @brief The bit mask for ADDRESS field in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_ADDRESS_MASK (0xFFFFFU) +/*! @brief The bit shift for LENGTH filed in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_LENGTH_SHIFT (12U) +/*! @brief The mask for LENGTH field in ADMA1's descriptor */ +#define USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK (0xFFFFU) +/*! @brief The maximum value of LENGTH filed in ADMA1's descriptor + * Since the ADMA1 support max transfer size is 65535 which is not divisible by + * 4096, so to make sure a large data load transfer(>64KB) continuously(require the data + * address should be alwawys align with 4096), software will set the maximum data length + * for ADMA1 to (64 - 4)KB. + */ +#define USDHC_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA1_DESCRIPTOR_LENGTH_MASK + 1U - 4096U) + +/*! @brief The mask for the control/status field in ADMA1 descriptor */ +enum _usdhc_adma1_descriptor_flag +{ + kUSDHC_Adma1DescriptorValidFlag = (1U << 0U), /*!< Valid flag */ + kUSDHC_Adma1DescriptorEndFlag = (1U << 1U), /*!< End flag */ + kUSDHC_Adma1DescriptorInterrupFlag = (1U << 2U), /*!< Interrupt flag */ + kUSDHC_Adma1DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 flag */ + kUSDHC_Adma1DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 flag */ + kUSDHC_Adma1DescriptorTypeNop = (kUSDHC_Adma1DescriptorValidFlag), /*!< No operation */ + kUSDHC_Adma1DescriptorTypeTransfer = + (kUSDHC_Adma1DescriptorActivity2Flag | kUSDHC_Adma1DescriptorValidFlag), /*!< Transfer data */ + kUSDHC_Adma1DescriptorTypeLink = (kUSDHC_Adma1DescriptorActivity1Flag | kUSDHC_Adma1DescriptorActivity2Flag | + kUSDHC_Adma1DescriptorValidFlag), /*!< Link descriptor */ + kUSDHC_Adma1DescriptorTypeSetLength = + (kUSDHC_Adma1DescriptorActivity1Flag | kUSDHC_Adma1DescriptorValidFlag), /*!< Set data length */ +}; + +/* ADMA2 descriptor table + * |----------------|---------------|-------------|--------------------------| + * | Address field | Length | Reserved | Attribute | + * |----------------|---------------|-------------|--------------------------| + * |63 32|31 16|15 06|05 |04 |03|02 |01 |00 | + * |----------------|---------------|-------------|----|----|--|---|---|-----| + * | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid| + * |----------------|---------------|-------------|----|----|--|---|---|-----| + * + * + * | Act2 | Act1 | Comment | Operation | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 0 | 0 | No op | Don't care | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 0 | 1 | Reserved | Read this line and go to next one | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 1 | 1 | Link descriptor | Link to another descriptor | + * |------|------|-----------------|-------------------------------------------------------------------| + */ +/*! @brief The bit shift for LENGTH field in ADMA2's descriptor */ +#define USDHC_ADMA2_DESCRIPTOR_LENGTH_SHIFT (16U) +/*! @brief The bit mask for LENGTH field in ADMA2's descriptor */ +#define USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK (0xFFFFU) +/*! @brief The maximum value of LENGTH field in ADMA2's descriptor */ +#define USDHC_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (USDHC_ADMA2_DESCRIPTOR_LENGTH_MASK - 3U) + +/*! @brief ADMA1 descriptor control and status mask */ +enum _usdhc_adma2_descriptor_flag +{ + kUSDHC_Adma2DescriptorValidFlag = (1U << 0U), /*!< Valid flag */ + kUSDHC_Adma2DescriptorEndFlag = (1U << 1U), /*!< End flag */ + kUSDHC_Adma2DescriptorInterruptFlag = (1U << 2U), /*!< Interrupt flag */ + kUSDHC_Adma2DescriptorActivity1Flag = (1U << 4U), /*!< Activity 1 mask */ + kUSDHC_Adma2DescriptorActivity2Flag = (1U << 5U), /*!< Activity 2 mask */ + + kUSDHC_Adma2DescriptorTypeNop = (kUSDHC_Adma2DescriptorValidFlag), /*!< No operation */ + kUSDHC_Adma2DescriptorTypeReserved = + (kUSDHC_Adma2DescriptorActivity1Flag | kUSDHC_Adma2DescriptorValidFlag), /*!< Reserved */ + kUSDHC_Adma2DescriptorTypeTransfer = + (kUSDHC_Adma2DescriptorActivity2Flag | kUSDHC_Adma2DescriptorValidFlag), /*!< Transfer type */ + kUSDHC_Adma2DescriptorTypeLink = (kUSDHC_Adma2DescriptorActivity1Flag | kUSDHC_Adma2DescriptorActivity2Flag | + kUSDHC_Adma2DescriptorValidFlag), /*!< Link type */ +}; + +/*! @brief ADMA descriptor configuration flag */ +enum _usdhc_adma_flag +{ + kUSDHC_AdmaDescriptorSingleFlag = + 0U, /*!< try to finish the transfer in a single ADMA descriptor, if transfer size is bigger than one + ADMA descriptor's ability, new another descriptor for data transfer */ + kUSDHC_AdmaDescriptorMultipleFlag = 1U, /*!< create multiple ADMA descriptor within the ADMA table, this is used for + mmc boot mode specifically, which need + to modify the ADMA descriptor on the fly, so the flag should be used + combine with stop at block gap feature */ +}; + +/*! @brief dma transfer burst len config. */ +typedef enum _usdhc_burst_len +{ + kUSDHC_EnBurstLenForINCR = 0x01U, /*!< enable burst len for INCR */ + kUSDHC_EnBurstLenForINCR4816 = 0x02U, /*!< enable burst len for INCR4/INCR8/INCR16 */ + kUSDHC_EnBurstLenForINCR4816WRAP = 0x04U, /*!< enable burst len for INCR4/8/16 WRAP */ +} usdhc_burst_len_t; + +/*! @brief transfer data type definition. */ +enum _usdhc_transfer_data_type +{ + kUSDHC_TransferDataNormal = 0U, /*!< transfer normal read/write data */ + kUSDHC_TransferDataTuning = 1U, /*!< transfer tuning data */ + kUSDHC_TransferDataBoot = 2U, /*!< transfer boot data */ + kUSDHC_TransferDataBootcontinous = 3U, /*!< transfer boot data continous */ +}; + +/*! @brief Defines the adma1 descriptor structure. */ +typedef uint32_t usdhc_adma1_descriptor_t; + +/*! @brief Defines the ADMA2 descriptor structure. */ +typedef struct _usdhc_adma2_descriptor +{ + uint32_t attribute; /*!< The control and status field */ + const uint32_t *address; /*!< The address field */ +} usdhc_adma2_descriptor_t; + +/*! + * @brief USDHC capability information. + * + * Defines a structure to save the capability information of USDHC. + */ +typedef struct _usdhc_capability +{ + uint32_t sdVersion; /*!< support SD card/sdio version */ + uint32_t mmcVersion; /*!< support emmc card version */ + uint32_t maxBlockLength; /*!< Maximum block length united as byte */ + uint32_t maxBlockCount; /*!< Maximum block count can be set one time */ + uint32_t flags; /*!< Capability flags to indicate the support information(_usdhc_capability_flag) */ +} usdhc_capability_t; + +/*! @brief Data structure to configure the MMC boot feature */ +typedef struct _usdhc_boot_config +{ + uint32_t ackTimeoutCount; /*!< Timeout value for the boot ACK. The available range is 0 ~ 15. */ + usdhc_boot_mode_t bootMode; /*!< Boot mode selection. */ + uint32_t blockCount; /*!< Stop at block gap value of automatic mode. Available range is 0 ~ 65535. */ + size_t blockSize; /*!< Block size */ + bool enableBootAck; /*!< Enable or disable boot ACK */ + bool enableAutoStopAtBlockGap; /*!< Enable or disable auto stop at block gap function in boot period */ +} usdhc_boot_config_t; + +/*! @brief Data structure to initialize the USDHC */ +typedef struct _usdhc_config +{ + uint32_t dataTimeout; /*!< Data timeout value */ + usdhc_endian_mode_t endianMode; /*!< Endian mode */ + uint8_t readWatermarkLevel; /*!< Watermark level for DMA read operation. Available range is 1 ~ 128. */ + uint8_t writeWatermarkLevel; /*!< Watermark level for DMA write operation. Available range is 1 ~ 128. */ + uint8_t readBurstLen; /*!< Read burst len */ + uint8_t writeBurstLen; /*!< Write burst len */ +} usdhc_config_t; + +/*! + * @brief Card data descriptor + * + * Defines a structure to contain data-related attribute. 'enableIgnoreError' is used for the case that upper card + * driver + * want to ignore the error event to read/write all the data not to stop read/write immediately when error event + * happen for example bus testing procedure for MMC card. + */ +typedef struct _usdhc_data +{ + bool enableAutoCommand12; /*!< Enable auto CMD12 */ + bool enableAutoCommand23; /*!< Enable auto CMD23 */ + bool enableIgnoreError; /*!< Enable to ignore error event to read/write all the data */ + uint8_t dataType; /*!< this is used to distinguish the normal/tuning/boot data */ + size_t blockSize; /*!< Block size */ + uint32_t blockCount; /*!< Block count */ + uint32_t *rxData; /*!< Buffer to save data read */ + const uint32_t *txData; /*!< Data buffer to write */ +} usdhc_data_t; + +/*! + * @brief Card command descriptor + * + * Define card command-related attribute. + */ +typedef struct _usdhc_command +{ + uint32_t index; /*!< Command index */ + uint32_t argument; /*!< Command argument */ + usdhc_card_command_type_t type; /*!< Command type */ + usdhc_card_response_type_t responseType; /*!< Command response type */ + uint32_t response[4U]; /*!< Response for this command */ + uint32_t responseErrorFlags; /*!< response error flag, the flag which need to check + the command reponse*/ + uint32_t flags; /*!< Cmd flags */ +} usdhc_command_t; + +/*! @brief ADMA configuration */ +typedef struct _usdhc_adma_config +{ + usdhc_dma_mode_t dmaMode; /*!< DMA mode */ + + usdhc_burst_len_t burstLen; /*!< burst len config */ + + uint32_t *admaTable; /*!< ADMA table address, can't be null if transfer way is ADMA1/ADMA2 */ + uint32_t admaTableWords; /*!< ADMA table length united as words, can't be 0 if transfer way is ADMA1/ADMA2 */ +} usdhc_adma_config_t; + +/*! @brief Transfer state */ +typedef struct _usdhc_transfer +{ + usdhc_data_t *data; /*!< Data to transfer */ + usdhc_command_t *command; /*!< Command to send */ +} usdhc_transfer_t; + +/*! @brief USDHC handle typedef */ +typedef struct _usdhc_handle usdhc_handle_t; + +/*! @brief USDHC callback functions. */ +typedef struct _usdhc_transfer_callback +{ + void (*CardInserted)(USDHC_Type *base, + void *userData); /*!< Card inserted occurs when DAT3/CD pin is for card detect */ + void (*CardRemoved)(USDHC_Type *base, void *userData); /*!< Card removed occurs */ + void (*SdioInterrupt)(USDHC_Type *base, void *userData); /*!< SDIO card interrupt occurs */ + void (*BlockGap)(USDHC_Type *base, void *userData); /*!< stopped at block gap event */ + void (*TransferComplete)(USDHC_Type *base, + usdhc_handle_t *handle, + status_t status, + void *userData); /*!< Transfer complete callback */ + void (*ReTuning)(USDHC_Type *base, void *userData); /*!< handle the re-tuning */ +} usdhc_transfer_callback_t; + +/*! + * @brief USDHC handle + * + * Defines the structure to save the USDHC state information and callback function. The detailed interrupt status when + * sending a command or transfering data can be obtained from the interruptFlags field by using the mask defined in + * usdhc_interrupt_flag_t. + * + * @note All the fields except interruptFlags and transferredWords must be allocated by the user. + */ +struct _usdhc_handle +{ + /* Transfer parameter */ + usdhc_data_t *volatile data; /*!< Data to transfer */ + usdhc_command_t *volatile command; /*!< Command to send */ + + /* Transfer status */ + volatile uint32_t transferredWords; /*!< Words transferred by DATAPORT way */ + + /* Callback functions */ + usdhc_transfer_callback_t callback; /*!< Callback function */ + void *userData; /*!< Parameter for transfer complete callback */ +}; + +/*! @brief USDHC transfer function. */ +typedef status_t (*usdhc_transfer_function_t)(USDHC_Type *base, usdhc_transfer_t *content); + +/*! @brief USDHC host descriptor */ +typedef struct _usdhc_host +{ + USDHC_Type *base; /*!< USDHC peripheral base address */ + uint32_t sourceClock_Hz; /*!< USDHC source clock frequency united in Hz */ + usdhc_config_t config; /*!< USDHC configuration */ + usdhc_capability_t capability; /*!< USDHC capability information */ + usdhc_transfer_function_t transfer; /*!< USDHC transfer function */ +} usdhc_host_t; + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief USDHC module initialization function. + * + * Configures the USDHC according to the user configuration. + * + * Example: + @code + usdhc_config_t config; + config.cardDetectDat3 = false; + config.endianMode = kUSDHC_EndianModeLittle; + config.dmaMode = kUSDHC_DmaModeAdma2; + config.readWatermarkLevel = 128U; + config.writeWatermarkLevel = 128U; + USDHC_Init(USDHC, &config); + @endcode + * + * @param base USDHC peripheral base address. + * @param config USDHC configuration information. + * @retval kStatus_Success Operate successfully. + */ +void USDHC_Init(USDHC_Type *base, const usdhc_config_t *config); + +/*! + * @brief Deinitializes the USDHC. + * + * @param base USDHC peripheral base address. + */ +void USDHC_Deinit(USDHC_Type *base); + +/*! + * @brief Resets the USDHC. + * + * @param base USDHC peripheral base address. + * @param mask The reset type mask(_usdhc_reset). + * @param timeout Timeout for reset. + * @retval true Reset successfully. + * @retval false Reset failed. + */ +bool USDHC_Reset(USDHC_Type *base, uint32_t mask, uint32_t timeout); + +/* @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Sets the DMA descriptor table configuration. + * A high level DMA descriptor configuration function. + * @param base USDHC peripheral base address. + * @param adma configuration + * @param data Data descriptor + * @param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please + * reference _usdhc_adma_flag + * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_SetAdmaTableConfig(USDHC_Type *base, + usdhc_adma_config_t *dmaConfig, + usdhc_data_t *dataConfig, + uint32_t flags); + +/*! + * @brief Internal DMA configuration. + * This function is used to config the USDHC DMA related registers. + * @param base USDHC peripheral base address. + * @param adma configuration + * @param dataAddr transfer data address, a simple DMA parameter, if ADMA is used, leave it to NULL. + * @param enAutoCmd23 flag to indicate Auto CMD23 is enable or not, a simple DMA parameter,if ADMA is used, leave it + * to false. + * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_SetInternalDmaConfig(USDHC_Type *base, + usdhc_adma_config_t *dmaConfig, + const uint32_t *dataAddr, + bool enAutoCmd23); + +/*! + * @brief Sets the ADMA2 descriptor table configuration. + * + * @param admaTable Adma table address. + * @param admaTableWords Adma table length. + * @param dataBufferAddr Data buffer address. + * @param dataBytes Data Data length. + * @param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please + * reference _usdhc_adma_flag. + * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_SetADMA2Descriptor( + uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags); + +/*! + * @brief Sets the ADMA1 descriptor table configuration. + * + * @param admaTable Adma table address. + * @param admaTableWords Adma table length. + * @param dataBufferAddr Data buffer address. + * @param dataBytes Data length. + * @param flags ADAM descriptor flag, used to indicate to create multiple or single descriptor, please + * reference _usdhc_adma_flag. + * @retval kStatus_OutOfRange ADMA descriptor table length isn't enough to describe data. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_SetADMA1Descriptor( + uint32_t *admaTable, uint32_t admaTableWords, const uint32_t *dataBufferAddr, uint32_t dataBytes, uint32_t flags); + +/*! + * @brief enable internal DMA. + * + * @param base USDHC peripheral base address. + * @param enable enable or disable flag + */ +static inline void USDHC_EnableInternalDMA(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->MIX_CTRL |= USDHC_MIX_CTRL_DMAEN_MASK; + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_DMAEN_MASK; + base->PROT_CTRL &= ~USDHC_PROT_CTRL_DMASEL_MASK; + } +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the interrupt status. + * + * @param base USDHC peripheral base address. + * @param mask Interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_EnableInterruptStatus(USDHC_Type *base, uint32_t mask) +{ + base->INT_STATUS_EN |= mask; +} + +/*! + * @brief Disables the interrupt status. + * + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_DisableInterruptStatus(USDHC_Type *base, uint32_t mask) +{ + base->INT_STATUS_EN &= ~mask; +} + +/*! + * @brief Enables the interrupt signal corresponding to the interrupt status flag. + * + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_EnableInterruptSignal(USDHC_Type *base, uint32_t mask) +{ + base->INT_SIGNAL_EN |= mask; +} + +/*! + * @brief Disables the interrupt signal corresponding to the interrupt status flag. + * + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_DisableInterruptSignal(USDHC_Type *base, uint32_t mask) +{ + base->INT_SIGNAL_EN &= ~mask; +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the enabled interrupt status. + * + * @param base USDHC peripheral base address. + * @return Current interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline uint32_t USDHC_GetEnabledInterruptStatusFlags(USDHC_Type *base) +{ + return (base->INT_STATUS) & (base->INT_SIGNAL_EN); +} + +/*! + * @brief Gets the current interrupt status. + * + * @param base USDHC peripheral base address. + * @return Current interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline uint32_t USDHC_GetInterruptStatusFlags(USDHC_Type *base) +{ + return base->INT_STATUS; +} + +/*! + * @brief Clears a specified interrupt status. + * write 1 clears + * @param base USDHC peripheral base address. + * @param mask The interrupt status flags mask(_usdhc_interrupt_status_flag). + */ +static inline void USDHC_ClearInterruptStatusFlags(USDHC_Type *base, uint32_t mask) +{ + base->INT_STATUS = mask; +} + +/*! + * @brief Gets the status of auto command 12 error. + * + * @param base USDHC peripheral base address. + * @return Auto command 12 error status flags mask(_usdhc_auto_command12_error_status_flag). + */ +static inline uint32_t USDHC_GetAutoCommand12ErrorStatusFlags(USDHC_Type *base) +{ + return base->AUTOCMD12_ERR_STATUS; +} + +/*! + * @brief Gets the status of the ADMA error. + * + * @param base USDHC peripheral base address. + * @return ADMA error status flags mask(_usdhc_adma_error_status_flag). + */ +static inline uint32_t USDHC_GetAdmaErrorStatusFlags(USDHC_Type *base) +{ + return base->ADMA_ERR_STATUS & 0xFU; +} + +/*! + * @brief Gets a present status. + * + * This function gets the present USDHC's status except for an interrupt status and an error status. + * + * @param base USDHC peripheral base address. + * @return Present USDHC's status flags mask(_usdhc_present_status_flag). + */ +static inline uint32_t USDHC_GetPresentStatusFlags(USDHC_Type *base) +{ + return base->PRES_STATE; +} + +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Gets the capability information. + * + * @param base USDHC peripheral base address. + * @param capability Structure to save capability information. + */ +void USDHC_GetCapability(USDHC_Type *base, usdhc_capability_t *capability); + +/*! + * @brief force the card clock on. + * + * @param base USDHC peripheral base address. + * @param enable/disable flag. + */ +static inline void USDHC_ForceClockOn(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->VEND_SPEC |= USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK; + } + else + { + base->VEND_SPEC &= ~USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK; + } +} + +/*! + * @brief Sets the SD bus clock frequency. + * + * @param base USDHC peripheral base address. + * @param srcClock_Hz USDHC source clock frequency united in Hz. + * @param busClock_Hz SD bus clock frequency united in Hz. + * + * @return The nearest frequency of busClock_Hz configured to SD bus. + */ +uint32_t USDHC_SetSdClock(USDHC_Type *base, uint32_t srcClock_Hz, uint32_t busClock_Hz); + +/*! + * @brief Sends 80 clocks to the card to set it to the active state. + * + * This function must be called each time the card is inserted to ensure that the card can receive the command + * correctly. + * + * @param base USDHC peripheral base address. + * @param timeout Timeout to initialize card. + * @retval true Set card active successfully. + * @retval false Set card active failed. + */ +bool USDHC_SetCardActive(USDHC_Type *base, uint32_t timeout); + +/*! + * @brief trigger a hardware reset. + * + * @param base USDHC peripheral base address. + * @param 1 or 0 level + */ +static inline void USDHC_AssertHardwareReset(USDHC_Type *base, bool high) +{ + if (high) + { + base->SYS_CTRL |= USDHC_SYS_CTRL_IPP_RST_N_MASK; + } + else + { + base->SYS_CTRL &= ~USDHC_SYS_CTRL_IPP_RST_N_MASK; + } +} + +/*! + * @brief Sets the data transfer width. + * + * @param base USDHC peripheral base address. + * @param width Data transfer width. + */ +static inline void USDHC_SetDataBusWidth(USDHC_Type *base, usdhc_data_bus_width_t width) +{ + base->PROT_CTRL = ((base->PROT_CTRL & ~USDHC_PROT_CTRL_DTW_MASK) | USDHC_PROT_CTRL_DTW(width)); +} + +/*! + * @brief Fills the data port. + * + * This function is used to implement the data transfer by Data Port instead of DMA. + * + * @param base USDHC peripheral base address. + * @param data The data about to be sent. + */ +static inline void USDHC_WriteData(USDHC_Type *base, uint32_t data) +{ + base->DATA_BUFF_ACC_PORT = data; +} + +/*! + * @brief Retrieves the data from the data port. + * + * This function is used to implement the data transfer by Data Port instead of DMA. + * + * @param base USDHC peripheral base address. + * @return The data has been read. + */ +static inline uint32_t USDHC_ReadData(USDHC_Type *base) +{ + return base->DATA_BUFF_ACC_PORT; +} + +/*! + * @brief send command function + * + * @param base USDHC peripheral base address. + * @param command configuration + */ +void USDHC_SendCommand(USDHC_Type *base, usdhc_command_t *command); + +/*! + * @brief Enables or disables a wakeup event in low-power mode. + * + * @param base USDHC peripheral base address. + * @param mask Wakeup events mask(_usdhc_wakeup_event). + * @param enable True to enable, false to disable. + */ +static inline void USDHC_EnableWakeupEvent(USDHC_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->PROT_CTRL |= mask; + } + else + { + base->PROT_CTRL &= ~mask; + } +} + +/*! + * @brief detect card insert status. + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +static inline void USDHC_CardDetectByData3(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->PROT_CTRL |= USDHC_PROT_CTRL_D3CD_MASK; + } + else + { + base->PROT_CTRL &= ~USDHC_PROT_CTRL_D3CD_MASK; + } +} + +/*! + * @brief detect card insert status. + * + * @param base USDHC peripheral base address. + */ +static inline bool USDHC_DetectCardInsert(USDHC_Type *base) +{ + return (base->PRES_STATE & kUSDHC_CardInsertedFlag) ? true : false; +} + +/*! + * @brief Enables or disables the SDIO card control. + * + * @param base USDHC peripheral base address. + * @param mask SDIO card control flags mask(_usdhc_sdio_control_flag). + * @param enable True to enable, false to disable. + */ +static inline void USDHC_EnableSdioControl(USDHC_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->PROT_CTRL |= mask; + } + else + { + base->PROT_CTRL &= ~mask; + } +} + +/*! + * @brief Restarts a transaction which has stopped at the block GAP for the SDIO card. + * + * @param base USDHC peripheral base address. + */ +static inline void USDHC_SetContinueRequest(USDHC_Type *base) +{ + base->PROT_CTRL |= USDHC_PROT_CTRL_CREQ_MASK; +} + +/*! + * @brief Request stop at block gap function. + * + * @param base USDHC peripheral base address. + * @param enable true to stop at block gap, false to normal transfer + */ +static inline void USDHC_RequestStopAtBlockGap(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->PROT_CTRL |= USDHC_PROT_CTRL_SABGREQ_MASK; + } + else + { + base->PROT_CTRL &= ~USDHC_PROT_CTRL_SABGREQ_MASK; + } +} + +/*! + * @brief Configures the MMC boot feature. + * + * Example: + @code + usdhc_boot_config_t config; + config.ackTimeoutCount = 4; + config.bootMode = kUSDHC_BootModeNormal; + config.blockCount = 5; + config.enableBootAck = true; + config.enableBoot = true; + config.enableAutoStopAtBlockGap = true; + USDHC_SetMmcBootConfig(USDHC, &config); + @endcode + * + * @param base USDHC peripheral base address. + * @param config The MMC boot configuration information. + */ +void USDHC_SetMmcBootConfig(USDHC_Type *base, const usdhc_boot_config_t *config); + +/*! + * @brief Enables or disables the mmc boot mode. + * + * @param base USDHC peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void USDHC_EnableMmcBoot(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->MMC_BOOT |= USDHC_MMC_BOOT_BOOT_EN_MASK; + } + else + { + base->MMC_BOOT &= ~USDHC_MMC_BOOT_BOOT_EN_MASK; + } +} + +/*! + * @brief Forces generating events according to the given mask. + * + * @param base USDHC peripheral base address. + * @param mask The force events bit posistion (_usdhc_force_event). + */ +static inline void USDHC_SetForceEvent(USDHC_Type *base, uint32_t mask) +{ + base->FORCE_EVENT = mask; +} + +/*! + * @brief select the usdhc output voltage + * + * @param base USDHC peripheral base address. + * @param true 1.8V, false 3.0V + */ +static inline void UDSHC_SelectVoltage(USDHC_Type *base, bool en18v) +{ + if (en18v) + { + base->VEND_SPEC |= USDHC_VEND_SPEC_VSELECT_MASK; + } + else + { + base->VEND_SPEC &= ~USDHC_VEND_SPEC_VSELECT_MASK; + } +} + +#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (FSL_FEATURE_USDHC_HAS_SDR50_MODE) +/*! + * @brief check the SDR50 mode request tuning bit + * When this bit set, user should call USDHC_StandardTuning function + * @param base USDHC peripheral base address. + */ +static inline bool USDHC_RequestTuningForSDR50(USDHC_Type *base) +{ + return base->HOST_CTRL_CAP & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK ? true : false; +} + +/*! + * @brief check the request re-tuning bit + * When this bit is set, user should do manual tuning or standard tuning function + * @param base USDHC peripheral base address. + */ +static inline bool USDHC_RequestReTuning(USDHC_Type *base) +{ + return base->PRES_STATE & USDHC_PRES_STATE_RTR_MASK ? true : false; +} + +/*! + * @brief the SDR104 mode auto tuning enable and disable + * This function should call after tuning function execute pass, auto tuning will handle + * by hardware + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +static inline void USDHC_EnableAutoTuning(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->MIX_CTRL |= USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK; + } +} + +/*! + * @brief the config the re-tuning timer for mode 1 and mode 3 + * This timer is used for standard tuning auto re-tuning, + * @param base USDHC peripheral base address. + * @param timer counter value + */ +static inline void USDHC_SetRetuningTimer(USDHC_Type *base, uint32_t counter) +{ + base->HOST_CTRL_CAP &= ~USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK; + base->HOST_CTRL_CAP |= USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(counter); +} + +/*! + * @brief the auto tuning enbale for CMD/DATA line + * + * @param base USDHC peripheral base address. + */ +void USDHC_EnableAutoTuningForCmdAndData(USDHC_Type *base); + +/*! + * @brief manual tuning trigger or abort + * User should handle the tuning cmd and find the boundary of the delay + * then calucate a average value which will be config to the CLK_TUNE_CTRL_STATUS + * This function should called before USDHC_AdjustDelayforSDR104 function + * @param base USDHC peripheral base address. + * @param tuning enable flag + */ +void USDHC_EnableManualTuning(USDHC_Type *base, bool enable); + +/*! + * @brief the SDR104 mode delay setting adjust + * This function should called after USDHC_ManualTuningForSDR104 + * @param base USDHC peripheral base address. + * @param delay setting configuration + * @retval kStatus_Fail config the delay setting fail + * @retval kStatus_Success config the delay setting success + */ +status_t USDHC_AdjustDelayForManualTuning(USDHC_Type *base, uint32_t delay); + +/*! + * @brief the enable standard tuning function + * The standard tuning window and tuning counter use the default config + * tuning cmd is send by the software, user need to check the tuning result + * can be used for SDR50,SDR104,HS200 mode tuning + * @param base USDHC peripheral base address. + * @param tuning start tap + * @param tuning step + * @param enable/disable flag + */ +void USDHC_EnableStandardTuning(USDHC_Type *base, uint32_t tuningStartTap, uint32_t step, bool enable); + +/*! + * @brief Get execute std tuning status + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_GetExecuteStdTuningStatus(USDHC_Type *base) +{ + return (base->AUTOCMD12_ERR_STATUS & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK); +} + +/*! + * @brief check std tuning result + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_CheckStdTuningResult(USDHC_Type *base) +{ + return (base->AUTOCMD12_ERR_STATUS & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK); +} + +/*! + * @brief check tuning error + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_CheckTuningError(USDHC_Type *base) +{ + return (base->CLK_TUNE_CTRL_STATUS & + (USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK | USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)); +} + +#endif +/*! + * @brief the enable/disable DDR mode + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + * @param nibble position + */ +void USDHC_EnableDDRMode(USDHC_Type *base, bool enable, uint32_t nibblePos); + +/*! + * @brief the enable/disable HS400 mode + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +#if FSL_FEATURE_USDHC_HAS_HS400_MODE +static inline void USDHC_EnableHS400Mode(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->MIX_CTRL |= USDHC_MIX_CTRL_HS400_MODE_MASK; + } + else + { + base->MIX_CTRL &= ~USDHC_MIX_CTRL_HS400_MODE_MASK; + } +} + +/*! + * @brief reset the strobe DLL + * + * @param base USDHC peripheral base address. + */ +static inline void USDHC_ResetStrobeDLL(USDHC_Type *base) +{ + base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK; +} + +/*! + * @brief enable/disable the strobe DLL + * + * @param base USDHC peripheral base address. + * @param enable/disable flag + */ +static inline void USDHC_EnableStrobeDLL(USDHC_Type *base, bool enable) +{ + if (enable) + { + base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK; + } + else + { + base->STROBE_DLL_CTRL &= ~USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK; + } +} + +/*! + * @brief config the strobe DLL delay target and update interval + * + * @param base USDHC peripheral base address. + * @param delay target + * @param update interval + */ +static inline void USDHC_ConfigStrobeDLL(USDHC_Type *base, uint32_t delayTarget, uint32_t updateInterval) +{ + base->STROBE_DLL_CTRL &= (USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK | + USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK); + + base->STROBE_DLL_CTRL |= USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(updateInterval) | + USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(delayTarget); +} + +/*! + * @brief get the strobe DLL status + * + * @param base USDHC peripheral base address. + */ +static inline uint32_t USDHC_GetStrobeDLLStatus(USDHC_Type *base) +{ + return base->STROBE_DLL_STATUS; +} + +#endif + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Transfers the command/data using a blocking method. + * + * This function waits until the command response/data is received or the USDHC encounters an error by polling the + * status + * flag. + * The application must not call this API in multiple threads at the same time. Because of that this API doesn't + * support the re-entry mechanism. + * + * @note There is no need to call the API 'USDHC_TransferCreateHandle' when calling this API. + * + * @param base USDHC peripheral base address. + * @param adma configuration + * @param transfer Transfer content. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * @retval kStatus_USDHC_SendCommandFailed Send command failed. + * @retval kStatus_USDHC_TransferDataFailed Transfer data failed. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_TransferBlocking(USDHC_Type *base, usdhc_adma_config_t *dmaConfig, usdhc_transfer_t *transfer); + +/*! + * @brief Creates the USDHC handle. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle pointer. + * @param callback Structure pointer to contain all callback functions. + * @param userData Callback function parameter. + */ +void USDHC_TransferCreateHandle(USDHC_Type *base, + usdhc_handle_t *handle, + const usdhc_transfer_callback_t *callback, + void *userData); + +/*! + * @brief Transfers the command/data using an interrupt and an asynchronous method. + * + * This function sends a command and data and returns immediately. It doesn't wait the transfer complete or + * encounter an error. The application must not call this API in multiple threads at the same time. Because of that + * this API doesn't support the re-entry mechanism. + * + * @note Call the API 'USDHC_TransferCreateHandle' when calling this API. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + * @param adma configuration. + * @param transfer Transfer content. + * @retval kStatus_InvalidArgument Argument is invalid. + * @retval kStatus_USDHC_BusyTransferring Busy transferring. + * @retval kStatus_USDHC_PrepareAdmaDescriptorFailed Prepare ADMA descriptor failed. + * @retval kStatus_Success Operate successfully. + */ +status_t USDHC_TransferNonBlocking(USDHC_Type *base, + usdhc_handle_t *handle, + usdhc_adma_config_t *dmaConfig, + usdhc_transfer_t *transfer); + +/*! + * @brief IRQ handler for the USDHC. + * + * This function deals with the IRQs on the given host controller. + * + * @param base USDHC peripheral base address. + * @param handle USDHC handle. + */ +void USDHC_TransferHandleIRQ(USDHC_Type *base, usdhc_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! @} */ + +#endif /* _FSL_USDHC_H_*/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_wdog.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_wdog.c new file mode 100644 index 0000000000..54ee7e6194 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_wdog.c @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_wdog.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.wdog01" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +static WDOG_Type *const s_wdogBases[] = WDOG_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of WDOG clock name. */ +static const clock_ip_name_t s_wdogClock[] = WDOG_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +static const IRQn_Type s_wdogIRQ[] = WDOG_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t WDOG_GetInstance(WDOG_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_wdogBases); instance++) + { + if (s_wdogBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_wdogBases)); + + return instance; +} + +/*! + * brief Initializes the WDOG configuration structure. + * + * This function initializes the WDOG configuration structure to default values. The default + * values are as follows. + * code + * wdogConfig->enableWdog = true; + * wdogConfig->workMode.enableWait = true; + * wdogConfig->workMode.enableStop = false; + * wdogConfig->workMode.enableDebug = false; + * wdogConfig->enableInterrupt = false; + * wdogConfig->enablePowerdown = false; + * wdogConfig->resetExtension = flase; + * wdogConfig->timeoutValue = 0xFFU; + * wdogConfig->interruptTimeValue = 0x04u; + * endcode + * + * param config Pointer to the WDOG configuration structure. + * see wdog_config_t + */ +void WDOG_GetDefaultConfig(wdog_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + config->enableWdog = true; + config->workMode.enableWait = false; + config->workMode.enableStop = false; + config->workMode.enableDebug = false; + config->enableInterrupt = false; + config->softwareResetExtension = false; + config->enablePowerDown = false; + config->timeoutValue = 0xffu; + config->interruptTimeValue = 0x04u; + config->enableTimeOutAssert = false; +} + +/*! + * brief Initializes the WDOG. + * + * This function initializes the WDOG. When called, the WDOG runs according to the configuration. + * + * This is an example. + * code + * wdog_config_t config; + * WDOG_GetDefaultConfig(&config); + * config.timeoutValue = 0xffU; + * config->interruptTimeValue = 0x04u; + * WDOG_Init(wdog_base,&config); + * endcode + * + * param base WDOG peripheral base address + * param config The configuration of WDOG + */ +void WDOG_Init(WDOG_Type *base, const wdog_config_t *config) +{ + assert(config); + + uint16_t value = 0u; + + value = WDOG_WCR_WDE(config->enableWdog) | WDOG_WCR_WDW(config->workMode.enableWait) | + WDOG_WCR_WDZST(config->workMode.enableStop) | WDOG_WCR_WDBG(config->workMode.enableDebug) | + WDOG_WCR_SRE(config->softwareResetExtension) | WDOG_WCR_WT(config->timeoutValue) | + WDOG_WCR_WDT(config->enableTimeOutAssert) | WDOG_WCR_SRS_MASK | WDOG_WCR_WDA_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Set configuration */ + CLOCK_EnableClock(s_wdogClock[WDOG_GetInstance(base)]); +#endif + + base->WICR = WDOG_WICR_WICT(config->interruptTimeValue) | WDOG_WICR_WIE(config->enableInterrupt); + base->WMCR = WDOG_WMCR_PDE(config->enablePowerDown); + base->WCR = value; + if (config->enableInterrupt) + { + EnableIRQ(s_wdogIRQ[WDOG_GetInstance(base)]); + } +} + +/*! + * brief Shuts down the WDOG. + * + * This function shuts down the WDOG. + * Watchdog Enable bit is a write one once only bit. It is not + * possible to clear this bit by a software write, once the bit is set. + * This bit(WDE) can be set/reset only in debug mode(exception). + */ +void WDOG_Deinit(WDOG_Type *base) +{ + if (base->WCR & WDOG_WCR_WDBG_MASK) + { + WDOG_Disable(base); + } +} + +/*! + * brief Gets the WDOG all reset status flags. + * + * This function gets all reset status flags. + * + * code + * uint16_t status; + * status = WDOG_GetStatusFlags (wdog_base); + * endcode + * param base WDOG peripheral base address + * return State of the status flag: asserted (true) or not-asserted (false).see _wdog_status_flags + * - true: a related status flag has been set. + * - false: a related status flag is not set. + */ +uint16_t WDOG_GetStatusFlags(WDOG_Type *base) +{ + uint16_t status_flag = 0U; + + status_flag |= (base->WCR & WDOG_WCR_WDE_MASK); + status_flag |= (base->WRSR & WDOG_WRSR_POR_MASK); + status_flag |= (base->WRSR & WDOG_WRSR_TOUT_MASK); + status_flag |= (base->WRSR & WDOG_WRSR_SFTW_MASK); + status_flag |= (base->WICR & WDOG_WICR_WTIS_MASK); + + return status_flag; +} + +/*! + * brief Clears the WDOG flag. + * + * This function clears the WDOG status flag. + * + * This is an example for clearing the interrupt flag. + * code + * WDOG_ClearStatusFlags(wdog_base,KWDOG_InterruptFlag); + * endcode + * param base WDOG peripheral base address + * param mask The status flags to clear. + * The parameter could be any combination of the following values. + * kWDOG_TimeoutFlag + */ +void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask) +{ + if (mask & kWDOG_InterruptFlag) + { + base->WICR |= WDOG_WICR_WTIS_MASK; + } +} + +/*! + * brief Refreshes the WDOG timer. + * + * This function feeds the WDOG. + * This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted. + * + * param base WDOG peripheral base address + */ +void WDOG_Refresh(WDOG_Type *base) +{ + base->WSR = WDOG_REFRESH_KEY & 0xFFFFU; + base->WSR = (WDOG_REFRESH_KEY >> 16U) & 0xFFFFU; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_wdog.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_wdog.h new file mode 100644 index 0000000000..d8e0628a3e --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_wdog.h @@ -0,0 +1,305 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_WDOG_H_ +#define _FSL_WDOG_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup wdog + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines WDOG driver version */ +#define FSL_WDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ +/*! @name Refresh sequence */ +/*@{*/ +#define WDOG_REFRESH_KEY (0xAAAA5555U) +/*@}*/ + +/*! @brief Defines WDOG work mode. */ +typedef struct _wdog_work_mode +{ + bool enableWait; /*!< continue or suspend WDOG in wait mode */ + bool enableStop; /*!< continue or suspend WDOG in stop mode */ + bool enableDebug; /*!< continue or suspend WDOG in debug mode */ +} wdog_work_mode_t; + +/*! @brief Describes WDOG configuration structure. */ +typedef struct _wdog_config +{ + bool enableWdog; /*!< Enables or disables WDOG */ + wdog_work_mode_t workMode; /*!< Configures WDOG work mode in debug stop and wait mode */ + bool enableInterrupt; /*!< Enables or disables WDOG interrupt */ + uint16_t timeoutValue; /*!< Timeout value */ + uint16_t interruptTimeValue; /*!< Interrupt count timeout value */ + bool softwareResetExtension; /*!< software reset extension */ + bool enablePowerDown; /*!< power down enable bit */ + bool enableTimeOutAssert; /*!< Enable WDOG_B timeout assertion. */ +} wdog_config_t; + +/*! + * @brief WDOG interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all of the WDOG interrupt configurations. + */ +enum _wdog_interrupt_enable +{ + kWDOG_InterruptEnable = WDOG_WICR_WIE_MASK /*!< WDOG timeout generates an interrupt before reset*/ +}; + +/*! + * @brief WDOG status flags. + * + * This structure contains the WDOG status flags for use in the WDOG functions. + */ +enum _wdog_status_flags +{ + kWDOG_RunningFlag = WDOG_WCR_WDE_MASK, /*!< Running flag, set when WDOG is enabled*/ + kWDOG_PowerOnResetFlag = WDOG_WRSR_POR_MASK, /*!< Power On flag, set when reset is the result of a powerOnReset*/ + kWDOG_TimeoutResetFlag = WDOG_WRSR_TOUT_MASK, /*!< Timeout flag, set when reset is the result of a timeout*/ + kWDOG_SoftwareResetFlag = WDOG_WRSR_SFTW_MASK, /*!< Software flag, set when reset is the result of a software*/ + kWDOG_InterruptFlag = WDOG_WICR_WTIS_MASK /*!< interrupt flag,whether interrupt has occurred or not*/ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name WDOG Initialization and De-initialization. + * @{ + */ + +/*! + * @brief Initializes the WDOG configuration structure. + * + * This function initializes the WDOG configuration structure to default values. The default + * values are as follows. + * @code + * wdogConfig->enableWdog = true; + * wdogConfig->workMode.enableWait = true; + * wdogConfig->workMode.enableStop = false; + * wdogConfig->workMode.enableDebug = false; + * wdogConfig->enableInterrupt = false; + * wdogConfig->enablePowerdown = false; + * wdogConfig->resetExtension = flase; + * wdogConfig->timeoutValue = 0xFFU; + * wdogConfig->interruptTimeValue = 0x04u; + * @endcode + * + * @param config Pointer to the WDOG configuration structure. + * @see wdog_config_t + */ +void WDOG_GetDefaultConfig(wdog_config_t *config); + +/*! + * @brief Initializes the WDOG. + * + * This function initializes the WDOG. When called, the WDOG runs according to the configuration. + * + * This is an example. + * @code + * wdog_config_t config; + * WDOG_GetDefaultConfig(&config); + * config.timeoutValue = 0xffU; + * config->interruptTimeValue = 0x04u; + * WDOG_Init(wdog_base,&config); + * @endcode + * + * @param base WDOG peripheral base address + * @param config The configuration of WDOG + */ +void WDOG_Init(WDOG_Type *base, const wdog_config_t *config); + +/*! + * @brief Shuts down the WDOG. + * + * This function shuts down the WDOG. + * Watchdog Enable bit is a write one once only bit. It is not + * possible to clear this bit by a software write, once the bit is set. + * This bit(WDE) can be set/reset only in debug mode(exception). + */ +void WDOG_Deinit(WDOG_Type *base); + +/*! + * @brief Enables the WDOG module. + * + * This function writes a value into the WDOG_WCR register to enable the WDOG. + * This is a write one once only bit. It is not possible to clear this bit by a software write, + * once the bit is set. only debug mode exception. + * @param base WDOG peripheral base address + */ +static inline void WDOG_Enable(WDOG_Type *base) +{ + base->WCR |= WDOG_WCR_WDE_MASK; +} + +/*! + * @brief Disables the WDOG module. + * + * This function writes a value into the WDOG_WCR register to disable the WDOG. + * This is a write one once only bit. It is not possible to clear this bit by a software write,once the bit is set. + * only debug mode exception + * @param base WDOG peripheral base address + */ +static inline void WDOG_Disable(WDOG_Type *base) +{ + base->WCR &= ~WDOG_WCR_WDE_MASK; +} + +/*! + * @brief Trigger the system software reset. + * + * This function will write to the WCR[SRS] bit to trigger a software system reset. + * This bit will automatically resets to "1" after it has been asserted to "0". + * Note: Calling this API will reset the system right now, please using it with more attention. + * + * @param base WDOG peripheral base address + */ +static inline void WDOG_TriggerSystemSoftwareReset(WDOG_Type *base) +{ + base->WCR &= ~WDOG_WCR_SRS_MASK; +} + +/*! + * @brief Trigger an output assertion. + * + * This function will write to the WCR[WDA] bit to trigger WDOG_B signal assertion. + * The WDOG_B signal can be routed to external pin of the chip, the output pin will turn to + * assertion along with WDOG_B signal. + * Note: The WDOG_B signal will remain assert until a power on reset occurred, so, please + * take more attention while calling it. + * + * @param base WDOG peripheral base address + */ +static inline void WDOG_TriggerSoftwareSignal(WDOG_Type *base) +{ + base->WCR &= ~WDOG_WCR_WDA_MASK; +} + +/*! + * @brief Enables the WDOG interrupt. + * + *This bit is a write once only bit. Once the software does a write access to this bit, it will get + *locked and cannot be reprogrammed until the next system reset assertion + * + * @param base WDOG peripheral base address + * @param mask The interrupts to enable + * The parameter can be combination of the following source if defined. + * @arg kWDOG_InterruptEnable + */ +static inline void WDOG_EnableInterrupts(WDOG_Type *base, uint16_t mask) +{ + base->WICR |= mask; +} + +/*! + * @brief Gets the WDOG all reset status flags. + * + * This function gets all reset status flags. + * + * @code + * uint16_t status; + * status = WDOG_GetStatusFlags (wdog_base); + * @endcode + * @param base WDOG peripheral base address + * @return State of the status flag: asserted (true) or not-asserted (false).@see _wdog_status_flags + * - true: a related status flag has been set. + * - false: a related status flag is not set. + */ +uint16_t WDOG_GetStatusFlags(WDOG_Type *base); + +/*! + * @brief Clears the WDOG flag. + * + * This function clears the WDOG status flag. + * + * This is an example for clearing the interrupt flag. + * @code + * WDOG_ClearStatusFlags(wdog_base,KWDOG_InterruptFlag); + * @endcode + * @param base WDOG peripheral base address + * @param mask The status flags to clear. + * The parameter could be any combination of the following values. + * kWDOG_TimeoutFlag + */ +void WDOG_ClearInterruptStatus(WDOG_Type *base, uint16_t mask); + +/*! + * @brief Sets the WDOG timeout value. + * + * This function sets the timeout value. + * This function writes a value into WCR registers. + * The time-out value can be written at any point of time but it is loaded to the counter at the time + * when WDOG is enabled or after the service routine has been performed. + * + * @param base WDOG peripheral base address + * @param timeoutCount WDOG timeout value; count of WDOG clock tick. + */ +static inline void WDOG_SetTimeoutValue(WDOG_Type *base, uint16_t timeoutCount) +{ + base->WCR = (base->WCR & ~WDOG_WCR_WT_MASK) | WDOG_WCR_WT(timeoutCount); +} + +/*! + * @brief Sets the WDOG interrupt count timeout value. + * + * This function sets the interrupt count timeout value. + * This function writes a value into WIC registers which are wirte-once. + * This field is write once only. Once the software does a write access to this field, it will get locked + * and cannot be reprogrammed until the next system reset assertion. + * @param base WDOG peripheral base address + * @param timeoutCount WDOG timeout value; count of WDOG clock tick. + */ +static inline void WDOG_SetInterrputTimeoutValue(WDOG_Type *base, uint16_t timeoutCount) +{ + base->WICR = (base->WICR & ~WDOG_WICR_WICT_MASK) | WDOG_WICR_WICT(timeoutCount); +} + +/*! + * @brief Disable the WDOG power down enable bit. + * + * This function disable the WDOG power down enable(PDE). + * This function writes a value into WMCR registers which are wirte-once. + * This field is write once only. Once software sets this bit it cannot be reset until the next system reset. + * @param base WDOG peripheral base address + */ +static inline void WDOG_DisablePowerDownEnable(WDOG_Type *base) +{ + base->WMCR &= ~WDOG_WMCR_PDE_MASK; +} + +/*! + * @brief Refreshes the WDOG timer. + * + * This function feeds the WDOG. + * This function should be called before the WDOG timer is in timeout. Otherwise, a reset is asserted. + * + * @param base WDOG peripheral base address + */ +void WDOG_Refresh(WDOG_Type *base); +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_WDOG_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_xbara.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_xbara.c new file mode 100644 index 0000000000..ab39eb738f --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_xbara.c @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_xbara.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xbara" +#endif + +/* Macros for entire XBARA_CTRL register. */ +#define XBARA_CTRLx(base, index) ((&(base->CTRL0))[index]) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the XBARA instance from peripheral base address. + * + * @param base XBARA peripheral base address. + * @return XBARA instance. + */ +static uint32_t XBARA_GetInstance(XBARA_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Array of XBARA peripheral base address. */ +static XBARA_Type *const s_xbaraBases[] = XBARA_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of XBARA clock name. */ +static const clock_ip_name_t s_xbaraClock[] = XBARA_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t XBARA_GetInstance(XBARA_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_xbaraBases); instance++) + { + if (s_xbaraBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_xbaraBases)); + + return instance; +} + +/*! + * brief Initializes the XBARA module. + * + * This function un-gates the XBARA clock. + * + * param base XBARA peripheral address. + */ +void XBARA_Init(XBARA_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable XBARA module clock. */ + CLOCK_EnableClock(s_xbaraClock[XBARA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Shuts down the XBARA module. + * + * This function disables XBARA clock. + * + * param base XBARA peripheral address. + */ +void XBARA_Deinit(XBARA_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable XBARA module clock. */ + CLOCK_DisableClock(s_xbaraClock[XBARA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Sets a connection between the selected XBARA_IN[*] input and the XBARA_OUT[*] output signal. + * + * This function connects the XBARA input to the selected XBARA output. + * If more than one XBARA module is available, only the inputs and outputs from the same module + * can be connected. + * + * Example: + code + XBARA_SetSignalsConnection(XBARA, kXBARA_InputPIT_TRG0, kXBARA_OutputDMAMUX18); + endcode + * + * param base XBARA peripheral address. + * param input XBARA input signal. + * param output XBARA output signal. + */ +void XBARA_SetSignalsConnection(XBARA_Type *base, xbar_input_signal_t input, xbar_output_signal_t output) +{ + XBARA_WR_SELx_SELx(base, (((uint16_t)input) & 0xFFU), (((uint16_t)output) & 0xFFU)); +} + +/*! + * brief Gets the active edge detection status. + * + * This function gets the active edge detect status of all XBARA_OUTs. If the + * active edge occurs, the return value is asserted. When the interrupt or the DMA + * functionality is enabled for the XBARA_OUTx, this field is 1 when the interrupt + * or DMA request is asserted and 0 when the interrupt or DMA request has been + * cleared. + * + * param base XBARA peripheral address. + * return the mask of these status flag bits. + */ +uint32_t XBARA_GetStatusFlags(XBARA_Type *base) +{ + uint32_t status_flag; + + status_flag = ((base->CTRL0 & (XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK)) | + ((base->CTRL1 & (XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK)) << 16U)); + + return status_flag; +} + +/*! + * brief Clears the edge detection status flags of relative mask. + * + * param base XBARA peripheral address. + * param mask the status flags to clear. + */ +void XBARA_ClearStatusFlags(XBARA_Type *base, uint32_t mask) +{ + uint16_t regVal; + + /* Assign regVal to CTRL0 register's value */ + regVal = (base->CTRL0); + /* Perform this command to avoid writing 1 into interrupt flag bits */ + regVal &= (uint16_t)(~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK)); + /* Write 1 to interrupt flag bits corresponding to mask */ + regVal |= (uint16_t)(mask & (XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK)); + /* Write regVal value into CTRL0 register */ + base->CTRL0 = regVal; + + /* Assign regVal to CTRL1 register's value */ + regVal = (base->CTRL1); + /* Perform this command to avoid writing 1 into interrupt flag bits */ + regVal &= (uint16_t)(~(XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK)); + /* Write 1 to interrupt flag bits corresponding to mask */ + regVal |= (uint16_t)((mask >> 16U) & (XBARA_CTRL1_STS2_MASK | XBARA_CTRL1_STS3_MASK)); + /* Write regVal value into CTRL1 register */ + base->CTRL1 = regVal; +} + +/*! + * brief Configures the XBARA control register. + * + * This function configures an XBARA control register. The active edge detection + * and the DMA/IRQ function on the corresponding XBARA output can be set. + * + * Example: + code + xbara_control_config_t userConfig; + userConfig.activeEdge = kXBARA_EdgeRising; + userConfig.requestType = kXBARA_RequestInterruptEnalbe; + XBARA_SetOutputSignalConfig(XBARA, kXBARA_OutputDMAMUX18, &userConfig); + endcode + * + * param base XBARA peripheral address. + * param output XBARA output number. + * param controlConfig Pointer to structure that keeps configuration of control register. + */ +void XBARA_SetOutputSignalConfig(XBARA_Type *base, + xbar_output_signal_t output, + const xbara_control_config_t *controlConfig) +{ + uint16_t regVal; + uint8_t outputIndex = (uint8_t)output & 0xFFU; + uint8_t regIndex; + uint8_t shiftInReg; + + assert(outputIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT); + + regIndex = outputIndex / 2; + + if ((outputIndex & 0x01U) != 0U) + { + shiftInReg = 8; + } + else + { + shiftInReg = 0; + } + + regVal = XBARA_CTRLx(base, regIndex); + + /* Don't clear the status flags. */ + regVal &= (uint16_t)(~(XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK)); + + regVal &= (uint16_t)(~((XBARA_CTRL0_DEN0_MASK | XBARA_CTRL0_IEN0_MASK | XBARA_CTRL0_EDGE0_MASK) << shiftInReg)); + regVal |= (uint16_t)( + (XBARA_CTRL0_EDGE0(controlConfig->activeEdge) | ((controlConfig->requestType) << XBARA_CTRL0_DEN0_SHIFT)) + << shiftInReg); + + XBARA_CTRLx(base, regIndex) = regVal; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_xbara.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_xbara.h new file mode 100644 index 0000000000..5fd6945600 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_xbara.h @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_XBARA_H_ +#define _FSL_XBARA_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup xbara + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define FSL_XBARA_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) /*!< Version 2.0.4. */ + +/* Macros for entire XBARA_SELx register. */ +#define XBARA_SELx(base, output) (*(volatile uint16_t *)((uintptr_t) & (base->SEL0) + ((output) / 2U) * 2U)) +/* Set the XBARA_SELx_SELx field to a new value. */ +#define XBARA_WR_SELx_SELx(base, input, output) \ + (XBARA_SELx((base), (output)) = \ + ((XBARA_SELx((base), (output)) & ~(0xFFU << (XBARA_SEL0_SEL1_SHIFT * ((output) % 2U)))) | \ + ((input) << (XBARA_SEL0_SEL1_SHIFT * ((output) % 2U))))) + +/*! + * @brief XBARA active edge for detection + */ +typedef enum _xbara_active_edge +{ + kXBARA_EdgeNone = 0U, /*!< Edge detection status bit never asserts. */ + kXBARA_EdgeRising = 1U, /*!< Edge detection status bit asserts on rising edges. */ + kXBARA_EdgeFalling = 2U, /*!< Edge detection status bit asserts on falling edges. */ + kXBARA_EdgeRisingAndFalling = 3U /*!< Edge detection status bit asserts on rising and falling edges. */ +} xbara_active_edge_t; + +/*! + * @brief Defines the XBARA DMA and interrupt configurations. + */ +typedef enum _xbar_request +{ + kXBARA_RequestDisable = 0U, /*!< Interrupt and DMA are disabled. */ + kXBARA_RequestDMAEnable = 1U, /*!< DMA enabled, interrupt disabled. */ + kXBARA_RequestInterruptEnalbe = 2U /*!< Interrupt enabled, DMA disabled. */ +} xbara_request_t; + +/*! + * @brief XBARA status flags. + * + * This provides constants for the XBARA status flags for use in the XBARA functions. + */ +typedef enum _xbara_status_flag_t +{ + kXBARA_EdgeDetectionOut0 = + (XBARA_CTRL0_STS0_MASK), /*!< XBAR_OUT0 active edge interrupt flag, sets when active edge detected. */ + kXBARA_EdgeDetectionOut1 = + (XBARA_CTRL0_STS1_MASK), /*!< XBAR_OUT1 active edge interrupt flag, sets when active edge detected. */ + kXBARA_EdgeDetectionOut2 = + (XBARA_CTRL1_STS2_MASK << 16U), /*!< XBAR_OUT2 active edge interrupt flag, sets when active edge detected. */ + kXBARA_EdgeDetectionOut3 = + (XBARA_CTRL1_STS3_MASK << 16U), /*!< XBAR_OUT3 active edge interrupt flag, sets when active edge detected. */ +} xbara_status_flag_t; + +/*! + * @brief Defines the configuration structure of the XBARA control register. + * + * This structure keeps the configuration of XBARA control register for one output. + * Control registers are available only for a few outputs. Not every XBARA module has + * control registers. + */ +typedef struct XBARAControlConfig +{ + xbara_active_edge_t activeEdge; /*!< Active edge to be detected. */ + xbara_request_t requestType; /*!< Selects DMA/Interrupt request. */ +} xbara_control_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name XBARA functional Operation. + * @{ + */ + +/*! + * @brief Initializes the XBARA module. + * + * This function un-gates the XBARA clock. + * + * @param base XBARA peripheral address. + */ +void XBARA_Init(XBARA_Type *base); + +/*! + * @brief Shuts down the XBARA module. + * + * This function disables XBARA clock. + * + * @param base XBARA peripheral address. + */ +void XBARA_Deinit(XBARA_Type *base); + +/*! + * @brief Sets a connection between the selected XBARA_IN[*] input and the XBARA_OUT[*] output signal. + * + * This function connects the XBARA input to the selected XBARA output. + * If more than one XBARA module is available, only the inputs and outputs from the same module + * can be connected. + * + * Example: + @code + XBARA_SetSignalsConnection(XBARA, kXBARA_InputPIT_TRG0, kXBARA_OutputDMAMUX18); + @endcode + * + * @param base XBARA peripheral address. + * @param input XBARA input signal. + * @param output XBARA output signal. + */ +void XBARA_SetSignalsConnection(XBARA_Type *base, xbar_input_signal_t input, xbar_output_signal_t output); + +/*! + * @brief Gets the active edge detection status. + * + * This function gets the active edge detect status of all XBARA_OUTs. If the + * active edge occurs, the return value is asserted. When the interrupt or the DMA + * functionality is enabled for the XBARA_OUTx, this field is 1 when the interrupt + * or DMA request is asserted and 0 when the interrupt or DMA request has been + * cleared. + * + * @param base XBARA peripheral address. + * @return the mask of these status flag bits. + */ +uint32_t XBARA_GetStatusFlags(XBARA_Type *base); + +/*! + * @brief Clears the edge detection status flags of relative mask. + * + * @param base XBARA peripheral address. + * @param mask the status flags to clear. + */ +void XBARA_ClearStatusFlags(XBARA_Type *base, uint32_t mask); + +/*! + * @brief Configures the XBARA control register. + * + * This function configures an XBARA control register. The active edge detection + * and the DMA/IRQ function on the corresponding XBARA output can be set. + * + * Example: + @code + xbara_control_config_t userConfig; + userConfig.activeEdge = kXBARA_EdgeRising; + userConfig.requestType = kXBARA_RequestInterruptEnalbe; + XBARA_SetOutputSignalConfig(XBARA, kXBARA_OutputDMAMUX18, &userConfig); + @endcode + * + * @param base XBARA peripheral address. + * @param output XBARA output number. + * @param controlConfig Pointer to structure that keeps configuration of control register. + */ +void XBARA_SetOutputSignalConfig(XBARA_Type *base, + xbar_output_signal_t output, + const xbara_control_config_t *controlConfig); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +/*!* @} */ + +#endif /* _FSL_XBARA_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_xbarb.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_xbarb.c new file mode 100644 index 0000000000..ec8c05f1a5 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_xbarb.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_xbarb.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xbarb" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Get the XBARB instance from peripheral base address. + * + * @param base XBARB peripheral base address. + * @return XBARB instance. + */ +static uint32_t XBARB_GetInstance(XBARB_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Array of XBARB peripheral base address. */ +static XBARB_Type *const s_xbarbBases[] = XBARB_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of XBARB clock name. */ +static const clock_ip_name_t s_xbarbClock[] = XBARB_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t XBARB_GetInstance(XBARB_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_xbarbBases); instance++) + { + if (s_xbarbBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_xbarbBases)); + + return instance; +} + +/*! + * brief Initializes the XBARB module. + * + * This function un-gates the XBARB clock. + * + * param base XBARB peripheral address. + */ +void XBARB_Init(XBARB_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable XBARB module clock. */ + CLOCK_EnableClock(s_xbarbClock[XBARB_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Shuts down the XBARB module. + * + * This function disables XBARB clock. + * + * param base XBARB peripheral address. + */ +void XBARB_Deinit(XBARB_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable XBARB module clock. */ + CLOCK_DisableClock(s_xbarbClock[XBARB_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Configures a connection between the selected XBARB_IN[*] input and the XBARB_OUT[*] output signal. + * + * This function configures which XBARB input is connected to the selected XBARB output. + * If more than one XBARB module is available, only the inputs and outputs from the same module + * can be connected. + * + * param base XBARB peripheral address. + * param input XBARB input signal. + * param output XBARB output signal. + */ +void XBARB_SetSignalsConnection(XBARB_Type *base, xbar_input_signal_t input, xbar_output_signal_t output) +{ + XBARB_WR_SELx_SELx(base, (((uint16_t)input) & 0xFFU), (((uint16_t)output) & 0xFFU)); +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_xbarb.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_xbarb.h new file mode 100644 index 0000000000..b459880605 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/fsl_xbarb.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_XBARB_H_ +#define _FSL_XBARB_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup xbarb + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define FSL_XBARB_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ + +/* Macros for entire XBARB_SELx register. */ +#define XBARB_SELx(base, output) (*(volatile uint16_t *)((uintptr_t) & (base->SEL0) + ((output) / 2U) * 2U)) +/* Set the SELx field to a new value. */ +#define XBARB_WR_SELx_SELx(base, input, output) \ + (XBARB_SELx((base), (output)) = \ + ((XBARB_SELx((base), (output)) & ~(0xFFU << (XBARB_SEL0_SEL1_SHIFT * ((output) % 2U)))) | \ + ((input) << (XBARB_SEL0_SEL1_SHIFT * ((output) % 2U))))) + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name XBARB functional Operation. + * @{ + */ + +/*! + * @brief Initializes the XBARB module. + * + * This function un-gates the XBARB clock. + * + * @param base XBARB peripheral address. + */ +void XBARB_Init(XBARB_Type *base); + +/*! + * @brief Shuts down the XBARB module. + * + * This function disables XBARB clock. + * + * @param base XBARB peripheral address. + */ +void XBARB_Deinit(XBARB_Type *base); + +/*! + * @brief Configures a connection between the selected XBARB_IN[*] input and the XBARB_OUT[*] output signal. + * + * This function configures which XBARB input is connected to the selected XBARB output. + * If more than one XBARB module is available, only the inputs and outputs from the same module + * can be connected. + * + * @param base XBARB peripheral address. + * @param input XBARB input signal. + * @param output XBARB output signal. + */ +void XBARB_SetSignalsConnection(XBARB_Type *base, xbar_input_signal_t input, xbar_output_signal_t output); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +/*!* @} */ + +#endif /* _FSL_XBARB_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/generic_list.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/generic_list.c new file mode 100644 index 0000000000..80dd21425d --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/generic_list.c @@ -0,0 +1,475 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*! ********************************************************************************* +************************************************************************************* +* Include +************************************************************************************* +********************************************************************************** */ +#include "generic_list.h" + +static list_status_t LIST_Error_Check(list_handle_t list, list_element_handle_t newElement) +{ + list_status_t listStatus = kLIST_Ok; + list_element_handle_t element = list->head; + + if ((list->max != 0U) && (list->max == list->size)) + { + listStatus = kLIST_Full; /*List is full*/ + } + else + { + while (element != NULL) /*Scan list*/ + { + /* Determine if element is duplicated */ + if (element == newElement) + { + listStatus = kLIST_DuplicateError; + break; + } + element = element->next; + } + } + + return listStatus; +} + +/*! ********************************************************************************* +************************************************************************************* +* Public functions +************************************************************************************* +********************************************************************************** */ +/*! ********************************************************************************* + * \brief Initialises the list descriptor. + * + * \param[in] list - LIST_ handle to init. + * max - Maximum number of elements in list. 0 for unlimited. + * + * \return void. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +void LIST_Init(list_handle_t list, uint32_t max) +{ + list->head = NULL; + list->tail = NULL; + list->max = (uint16_t)max; + list->size = 0; +} + +/*! ********************************************************************************* + * \brief Gets the list that contains the given element. + * + * \param[in] element - Handle of the element. + * + * \return NULL if element is orphan. + * Handle of the list the element is inserted into. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_handle_t LIST_GetList(list_element_handle_t element) +{ + return element->list; +} + +/*! ********************************************************************************* + * \brief Links element to the tail of the list. + * + * \param[in] list - ID of list to insert into. + * element - element to add + * + * \return kLIST_Full if list is full. + * kLIST_Ok if insertion was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element) +{ + uint32_t regPrimask = DisableGlobalIRQ(); + list_status_t listStatus = kLIST_Ok; + + listStatus = LIST_Error_Check(list, element); + if (listStatus == kLIST_Ok) /* Avoiding list status error */ + { + if (list->size == 0U) + { + list->head = element; + } + else + { + list->tail->next = element; + } +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#else + element->prev = list->tail; +#endif + element->list = list; + element->next = NULL; + list->tail = element; + list->size++; + } + + EnableGlobalIRQ(regPrimask); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Links element to the head of the list. + * + * \param[in] list - ID of list to insert into. + * element - element to add + * + * \return kLIST_Full if list is full. + * kLIST_Ok if insertion was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element) +{ + uint32_t regPrimask = DisableGlobalIRQ(); + list_status_t listStatus = kLIST_Ok; + + listStatus = LIST_Error_Check(list, element); + if (listStatus == kLIST_Ok) /* Avoiding list status error */ + { + /* Links element to the head of the list */ + if (list->size == 0U) + { + list->tail = element; + } +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#else + else + { + list->head->prev = element; + } + element->prev = NULL; +#endif + element->list = list; + element->next = list->head; + list->head = element; + list->size++; + } + + EnableGlobalIRQ(regPrimask); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Unlinks element from the head of the list. + * + * \param[in] list - ID of list to remove from. + * + * \return NULL if list is empty. + * ID of removed element(pointer) if removal was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_RemoveHead(list_handle_t list) +{ + list_element_handle_t element; + + uint32_t regPrimask = DisableGlobalIRQ(); + + if ((NULL == list) || (list->size == 0U)) + { + element = NULL; /*LIST_ is empty*/ + } + else + { + element = list->head; + list->size--; + if (list->size == 0U) + { + list->tail = NULL; + } +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +#else + else + { + element->next->prev = NULL; + } +#endif + element->list = NULL; + list->head = element->next; /*Is NULL if element is head*/ + } + + EnableGlobalIRQ(regPrimask); + return element; +} + +/*! ********************************************************************************* + * \brief Gets head element ID. + * + * \param[in] list - ID of list. + * + * \return NULL if list is empty. + * ID of head element if list is not empty. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_GetHead(list_handle_t list) +{ + return list->head; +} + +/*! ********************************************************************************* + * \brief Gets next element ID. + * + * \param[in] element - ID of the element. + * + * \return NULL if element is tail. + * ID of next element if exists. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_GetNext(list_element_handle_t element) +{ + return element->next; +} + +/*! ********************************************************************************* + * \brief Gets previous element ID. + * + * \param[in] element - ID of the element. + * + * \return NULL if element is head. + * ID of previous element if exists. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_GetPrev(list_element_handle_t element) +{ +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + return NULL; +#else + return element->prev; +#endif +} + +/*! ********************************************************************************* + * \brief Unlinks an element from its list. + * + * \param[in] element - ID of the element to remove. + * + * \return kLIST_OrphanElement if element is not part of any list. + * kLIST_Ok if removal was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_RemoveElement(list_element_handle_t element) +{ + list_status_t listStatus = kLIST_Ok; + uint32_t regPrimask = DisableGlobalIRQ(); + + if (element->list == NULL) + { + listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/ + } + else + { +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + list_element_handle_t element_list = element->list->head; + while (element_list) + { + if (element->list->head == element) + { + element->list->head = element_list->next; + break; + } + if (element_list->next == element) + { + element_list->next = element->next; + break; + } + element_list = element_list->next; + } +#else + if (element->prev == NULL) /*Element is head or solo*/ + { + element->list->head = element->next; /*is null if solo*/ + } + if (element->next == NULL) /*Element is tail or solo*/ + { + element->list->tail = element->prev; /*is null if solo*/ + } + if (element->prev != NULL) /*Element is not head*/ + { + element->prev->next = element->next; + } + if (element->next != NULL) /*Element is not tail*/ + { + element->next->prev = element->prev; + } +#endif + element->list->size--; + element->list = NULL; + } + + EnableGlobalIRQ(regPrimask); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Links an element in the previous position relative to a given member + * of a list. + * + * \param[in] element - ID of a member of a list. + * newElement - new element to insert before the given member. + * + * \return kLIST_OrphanElement if element is not part of any list. + * kLIST_Full if list is full. + * kLIST_Ok if insertion was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement) +{ + list_status_t listStatus = kLIST_Ok; + uint32_t regPrimask = DisableGlobalIRQ(); + + if (element->list == NULL) + { + listStatus = kLIST_OrphanElement; /*Element was previusly removed or never added*/ + } + else + { + listStatus = LIST_Error_Check(element->list, newElement); + if (listStatus == kLIST_Ok) + { +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) + list_element_handle_t element_list = element->list->head; + while (element_list) + { + if ((element_list->next == element) || (element_list == element)) + { + if (element_list == element) + { + element->list->head = newElement; + } + else + { + element_list->next = newElement; + } + newElement->list = element->list; + newElement->next = element; + element->list->size++; + break; + } + element_list = element_list->next; + } + +#else + if (element->prev == NULL) /*Element is list head*/ + { + element->list->head = newElement; + } + else + { + element->prev->next = newElement; + } + newElement->list = element->list; + element->list->size++; + newElement->next = element; + newElement->prev = element->prev; + element->prev = newElement; +#endif + } + } + + EnableGlobalIRQ(regPrimask); + return listStatus; +} + +/*! ********************************************************************************* + * \brief Gets the current size of a list. + * + * \param[in] list - ID of the list. + * + * \return Current size of the list. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +uint32_t LIST_GetSize(list_handle_t list) +{ + return list->size; +} + +/*! ********************************************************************************* + * \brief Gets the number of free places in the list. + * + * \param[in] list - ID of the list. + * + * \return Available size of the list. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +uint32_t LIST_GetAvailableSize(list_handle_t list) +{ + return ((uint32_t)list->max - (uint32_t)list->size); /*Gets the number of free places in the list*/ +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/generic_list.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/generic_list.h new file mode 100644 index 0000000000..def00efe8e --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/drivers/generic_list.h @@ -0,0 +1,203 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _GENERIC_LIST_H_ +#define _GENERIC_LIST_H_ + +#include "fsl_common.h" +/*! + * @addtogroup GenericList + * @{ + */ + +/*!********************************************************************************* +************************************************************************************* +* Include +************************************************************************************* +********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Public macro definitions +************************************************************************************* +********************************************************************************** */ +#ifndef GENERIC_LIST_LIGHT +#define GENERIC_LIST_LIGHT (0) +#endif +/*! ********************************************************************************* +************************************************************************************* +* Public type definitions +************************************************************************************* +********************************************************************************** */ +/*! @brief The list status */ +typedef enum _list_status +{ + kLIST_Ok = kStatus_Success, /*!< Success */ + kLIST_DuplicateError = MAKE_STATUS(kStatusGroup_LIST, 1), /*!< Duplicate Error */ + kLIST_Full = MAKE_STATUS(kStatusGroup_LIST, 2), /*!< FULL */ + kLIST_Empty = MAKE_STATUS(kStatusGroup_LIST, 3), /*!< Empty */ + kLIST_OrphanElement = MAKE_STATUS(kStatusGroup_LIST, 4), /*!< Orphan Element */ + kLIST_NotSupport = MAKE_STATUS(kStatusGroup_LIST, 5), /*!< Not Support */ +} list_status_t; + +/*! @brief The list structure*/ +typedef struct list_label +{ + struct list_element_tag *head; /*!< list head */ + struct list_element_tag *tail; /*!< list tail */ + uint16_t size; /*!< list size */ + uint16_t max; /*!< list max number of elements */ +} list_label_t, *list_handle_t; +#if (defined(GENERIC_LIST_LIGHT) && (GENERIC_LIST_LIGHT > 0U)) +/*! @brief The list element*/ +typedef struct list_element_tag +{ + struct list_element_tag *next; /*!< next list element */ + struct list_label *list; /*!< pointer to the list */ +} list_element_t, *list_element_handle_t; +#else +/*! @brief The list element*/ +typedef struct list_element_tag +{ + struct list_element_tag *next; /*!< next list element */ + struct list_element_tag *prev; /*!< previous list element */ + struct list_label *list; /*!< pointer to the list */ +} list_element_t, *list_element_handle_t; +#endif +/*! ********************************************************************************* +************************************************************************************* +* Public prototypes +************************************************************************************* +********************************************************************************** */ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ +/*! + * @brief Initialize the list. + * + * This function initialize the list. + * + * @param list - List handle to initialize. + * @param max - Maximum number of elements in list. 0 for unlimited. + */ +void LIST_Init(list_handle_t list, uint32_t max); + +/*! + * @brief Gets the list that contains the given element. + * + * + * @param element - Handle of the element. + * @retval NULL if element is orphan, Handle of the list the element is inserted into. + */ +list_handle_t LIST_GetList(list_element_handle_t element); + +/*! + * @brief Links element to the head of the list. + * + * @param list - Handle of the list. + * @param element - Handle of the element. + * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful. + */ +list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element); + +/*! + * @brief Links element to the tail of the list. + * + * @param list - Handle of the list. + * @param element - Handle of the element. + * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful. + */ +list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element); + +/*! + * @brief Unlinks element from the head of the list. + * + * @param list - Handle of the list. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_RemoveHead(list_handle_t list); + +/*! + * @brief Gets head element handle. + * + * @param list - Handle of the list. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_GetHead(list_handle_t list); + +/*! + * @brief Gets next element handle for given element handle. + * + * @param element - Handle of the element. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_GetNext(list_element_handle_t element); + +/*! + * @brief Gets previous element handle for given element handle. + * + * @param element - Handle of the element. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_GetPrev(list_element_handle_t element); + +/*! + * @brief Unlinks an element from its list. + * + * @param element - Handle of the element. + * + * @retval kLIST_OrphanElement if element is not part of any list. + * @retval kLIST_Ok if removal was successful. + */ +list_status_t LIST_RemoveElement(list_element_handle_t element); + +/*! + * @brief Links an element in the previous position relative to a given member of a list. + * + * @param list - Handle of the list. + * @param element - Handle of the element. + * @param newElement - New element to insert before the given member. + * + * @retval kLIST_OrphanElement if element is not part of any list. + * @retval kLIST_Ok if removal was successful. + */ +list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement); + +/*! + * @brief Gets the current size of a list. + * + * @param list - Handle of the list. + * + * @retval Current size of the list. + */ +uint32_t LIST_GetSize(list_handle_t list); + +/*! + * @brief Gets the number of free places in the list. + * + * @param list - Handle of the list. + * + * @retval Available size of the list. + */ +uint32_t LIST_GetAvailableSize(list_handle_t list); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! @}*/ +#endif /*_GENERIC_LIST_H_*/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/fsl_device_registers.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/fsl_device_registers.h new file mode 100644 index 0000000000..70810a49d7 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/fsl_device_registers.h @@ -0,0 +1,36 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MIMXRT1061CVJ5A) || defined(CPU_MIMXRT1061CVL5A) || defined(CPU_MIMXRT1061DVJ6A) || \ + defined(CPU_MIMXRT1061DVL6A)) + +#define MIMXRT1061_SERIES + +/* CMSIS-style register definitions */ +#include "MIMXRT1061.h" +/* CPU specific feature definitions */ +#include "MIMXRT1061_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/gcc/MIMXRT1061xxxxx_flexspi_nor.ld b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/gcc/MIMXRT1061xxxxx_flexspi_nor.ld new file mode 100644 index 0000000000..1463e33d7c --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/gcc/MIMXRT1061xxxxx_flexspi_nor.ld @@ -0,0 +1,243 @@ +/* +** ################################################################### +** Processors: MIMXRT1061CVJ5A +** MIMXRT1061CVL5A +** MIMXRT1061DVJ6A +** MIMXRT1061DVL6A +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1060RM Rev.1, 12/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b190312 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_flash_config (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x007FDC00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x000C0000 +} + +/* Define output sections */ +SECTIONS +{ + .flash_config : + { + . = ALIGN(4); + __FLASH_BASE = .; + KEEP(* (.boot_hdr.conf)) /* flash config section */ + . = ALIGN(4); + } > m_flash_config + + ivt_begin= ORIGIN(m_flash_config) + LENGTH(m_flash_config); + + .ivt : AT(ivt_begin) + { + . = ALIGN(4); + KEEP(* (.boot_hdr.ivt)) /* ivt section */ + KEEP(* (.boot_hdr.boot_data)) /* boot section */ + KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ + . = ALIGN(4); + } > m_ivt + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/gcc/MIMXRT1061xxxxx_flexspi_nor_sdram.ld b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/gcc/MIMXRT1061xxxxx_flexspi_nor_sdram.ld new file mode 100644 index 0000000000..7cd6f51c54 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/gcc/MIMXRT1061xxxxx_flexspi_nor_sdram.ld @@ -0,0 +1,245 @@ +/* +** ################################################################### +** Processors: MIMXRT1061CVJ5A +** MIMXRT1061CVL5A +** MIMXRT1061DVJ6A +** MIMXRT1061DVL6A +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1060RM Rev.1, 12/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b190312 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_flash_config (RX) : ORIGIN = 0x60000000, LENGTH = 0x00001000 + m_ivt (RX) : ORIGIN = 0x60001000, LENGTH = 0x00001000 + m_interrupts (RX) : ORIGIN = 0x60002000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x60002400, LENGTH = 0x007FDC00 + m_data (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 + m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data3 (RW) : ORIGIN = 0x20200000, LENGTH = 0x000C0000 +} + +/* Define output sections */ +SECTIONS +{ + .flash_config : + { + . = ALIGN(4); + __FLASH_BASE = .; + KEEP(* (.boot_hdr.conf)) /* flash config section */ + . = ALIGN(4); + } > m_flash_config + + ivt_begin= ORIGIN(m_flash_config) + LENGTH(m_flash_config); + + .ivt : AT(ivt_begin) + { + . = ALIGN(4); + KEEP(* (.boot_hdr.ivt)) /* ivt section */ + KEEP(* (.boot_hdr.boot_data)) /* boot section */ + KEEP(* (.boot_hdr.dcd_data)) /* dcd section */ + . = ALIGN(4); + } > m_ivt + + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_ncache + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_ncache + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/gcc/MIMXRT1061xxxxx_ram.ld b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/gcc/MIMXRT1061xxxxx_ram.ld new file mode 100644 index 0000000000..5f5e346db1 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/gcc/MIMXRT1061xxxxx_ram.ld @@ -0,0 +1,222 @@ +/* +** ################################################################### +** Processors: MIMXRT1061CVJ5A +** MIMXRT1061CVL5A +** MIMXRT1061DVJ6A +** MIMXRT1061DVL6A +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1060RM Rev.1, 12/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b190312 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0001FC00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data2 (RW) : ORIGIN = 0x20200000, LENGTH = 0x000C0000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_data + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_data + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/gcc/MIMXRT1061xxxxx_sdram.ld b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/gcc/MIMXRT1061xxxxx_sdram.ld new file mode 100644 index 0000000000..c73fbcd316 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/gcc/MIMXRT1061xxxxx_sdram.ld @@ -0,0 +1,224 @@ +/* +** ################################################################### +** Processors: MIMXRT1061CVJ5A +** MIMXRT1061CVL5A +** MIMXRT1061DVJ6A +** MIMXRT1061DVL6A +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1060RM Rev.1, 12/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b190312 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0001FC00 + m_data (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000 + m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 + m_data2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data3 (RW) : ORIGIN = 0x20200000, LENGTH = 0x000C0000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_ncache + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_ncache + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/gcc/MIMXRT1061xxxxx_sdram_txt.ld b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/gcc/MIMXRT1061xxxxx_sdram_txt.ld new file mode 100644 index 0000000000..d870c3b89d --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/gcc/MIMXRT1061xxxxx_sdram_txt.ld @@ -0,0 +1,224 @@ +/* +** ################################################################### +** Processors: MIMXRT1061CVJ5A +** MIMXRT1061CVL5A +** MIMXRT1061DVJ6A +** MIMXRT1061DVL6A +** +** Compiler: GNU C Compiler +** Reference manual: IMXRT1060RM Rev.1, 12/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b190312 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x00000400 + m_text (RX) : ORIGIN = 0x80000400, LENGTH = 0x001FFC00 + m_data (RW) : ORIGIN = 0x20200000, LENGTH = 0x000C0000 + m_data2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + m_data3 (RW) : ORIGIN = 0x80200000, LENGTH = 0x01C00000 + m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal RAM */ + .interrupts : + { + __VECTOR_TABLE = .; + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + __VECTOR_RAM = __VECTOR_TABLE; + __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0; + + /* The program code and other data goes into internal RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(m_usb_dma_init_data) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__); + .ncache.init : AT(__NDATA_ROM) + { + __noncachedata_start__ = .; /* create a global symbol at ncache data start */ + *(NonCacheable.init) + . = ALIGN(4); + __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */ + } > m_ncache + . = __noncachedata_init_end__; + .ncache : + { + *(NonCacheable) + . = ALIGN(4); + __noncachedata_end__ = .; /* define a global symbol at ncache data end */ + } > m_ncache + + __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(m_usb_dma_noninit_data) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} + diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/gcc/startup_MIMXRT1061.S b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/gcc/startup_MIMXRT1061.S new file mode 100644 index 0000000000..ea25d6ffb5 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/gcc/startup_MIMXRT1061.S @@ -0,0 +1,1128 @@ +/* ------------------------------------------------------------------------- */ +/* @file: startup_MIMXRT1061.s */ +/* @purpose: CMSIS Cortex-M7 Core Device Startup File */ +/* MIMXRT1061 */ +/* @version: 1.1 */ +/* @date: 2018-11-27 */ +/* @build: b190124 */ +/* ------------------------------------------------------------------------- */ +/* */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2019 NXP */ +/* All rights reserved. */ +/* */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long DMA0_DMA16_IRQHandler /* DMA channel 0/16 transfer complete*/ + .long DMA1_DMA17_IRQHandler /* DMA channel 1/17 transfer complete*/ + .long DMA2_DMA18_IRQHandler /* DMA channel 2/18 transfer complete*/ + .long DMA3_DMA19_IRQHandler /* DMA channel 3/19 transfer complete*/ + .long DMA4_DMA20_IRQHandler /* DMA channel 4/20 transfer complete*/ + .long DMA5_DMA21_IRQHandler /* DMA channel 5/21 transfer complete*/ + .long DMA6_DMA22_IRQHandler /* DMA channel 6/22 transfer complete*/ + .long DMA7_DMA23_IRQHandler /* DMA channel 7/23 transfer complete*/ + .long DMA8_DMA24_IRQHandler /* DMA channel 8/24 transfer complete*/ + .long DMA9_DMA25_IRQHandler /* DMA channel 9/25 transfer complete*/ + .long DMA10_DMA26_IRQHandler /* DMA channel 10/26 transfer complete*/ + .long DMA11_DMA27_IRQHandler /* DMA channel 11/27 transfer complete*/ + .long DMA12_DMA28_IRQHandler /* DMA channel 12/28 transfer complete*/ + .long DMA13_DMA29_IRQHandler /* DMA channel 13/29 transfer complete*/ + .long DMA14_DMA30_IRQHandler /* DMA channel 14/30 transfer complete*/ + .long DMA15_DMA31_IRQHandler /* DMA channel 15/31 transfer complete*/ + .long DMA_ERROR_IRQHandler /* DMA error interrupt channels 0-15 / 16-31*/ + .long CTI0_ERROR_IRQHandler /* CTI0_Error*/ + .long CTI1_ERROR_IRQHandler /* CTI1_Error*/ + .long CORE_IRQHandler /* CorePlatform exception IRQ*/ + .long LPUART1_IRQHandler /* LPUART1 TX interrupt and RX interrupt*/ + .long LPUART2_IRQHandler /* LPUART2 TX interrupt and RX interrupt*/ + .long LPUART3_IRQHandler /* LPUART3 TX interrupt and RX interrupt*/ + .long LPUART4_IRQHandler /* LPUART4 TX interrupt and RX interrupt*/ + .long LPUART5_IRQHandler /* LPUART5 TX interrupt and RX interrupt*/ + .long LPUART6_IRQHandler /* LPUART6 TX interrupt and RX interrupt*/ + .long LPUART7_IRQHandler /* LPUART7 TX interrupt and RX interrupt*/ + .long LPUART8_IRQHandler /* LPUART8 TX interrupt and RX interrupt*/ + .long LPI2C1_IRQHandler /* LPI2C1 interrupt*/ + .long LPI2C2_IRQHandler /* LPI2C2 interrupt*/ + .long LPI2C3_IRQHandler /* LPI2C3 interrupt*/ + .long LPI2C4_IRQHandler /* LPI2C4 interrupt*/ + .long LPSPI1_IRQHandler /* LPSPI1 single interrupt vector for all sources*/ + .long LPSPI2_IRQHandler /* LPSPI2 single interrupt vector for all sources*/ + .long LPSPI3_IRQHandler /* LPSPI3 single interrupt vector for all sources*/ + .long LPSPI4_IRQHandler /* LPSPI4 single interrupt vector for all sources*/ + .long CAN1_IRQHandler /* CAN1 interrupt*/ + .long CAN2_IRQHandler /* CAN2 interrupt*/ + .long FLEXRAM_IRQHandler /* FlexRAM address out of range Or access hit IRQ*/ + .long KPP_IRQHandler /* Keypad nterrupt*/ + .long TSC_DIG_IRQHandler /* TSC interrupt*/ + .long GPR_IRQ_IRQHandler /* GPR interrupt*/ + .long Reserved58_IRQHandler /* Reserved interrupt*/ + .long Reserved59_IRQHandler /* Reserved interrupt*/ + .long Reserved60_IRQHandler /* Reserved interrupt*/ + .long WDOG2_IRQHandler /* WDOG2 interrupt*/ + .long SNVS_HP_WRAPPER_IRQHandler /* SRTC Consolidated Interrupt. Non TZ*/ + .long SNVS_HP_WRAPPER_TZ_IRQHandler /* SRTC Security Interrupt. TZ*/ + .long SNVS_LP_WRAPPER_IRQHandler /* ON-OFF button press shorter than 5 secs (pulse event)*/ + .long CSU_IRQHandler /* CSU interrupt*/ + .long DCP_IRQHandler /* DCP_IRQ interrupt*/ + .long DCP_VMI_IRQHandler /* DCP_VMI_IRQ interrupt*/ + .long Reserved68_IRQHandler /* Reserved interrupt*/ + .long TRNG_IRQHandler /* TRNG interrupt*/ + .long SJC_IRQHandler /* SJC interrupt*/ + .long BEE_IRQHandler /* BEE interrupt*/ + .long SAI1_IRQHandler /* SAI1 interrupt*/ + .long SAI2_IRQHandler /* SAI1 interrupt*/ + .long SAI3_RX_IRQHandler /* SAI3 interrupt*/ + .long SAI3_TX_IRQHandler /* SAI3 interrupt*/ + .long SPDIF_IRQHandler /* SPDIF interrupt*/ + .long PMU_EVENT_IRQHandler /* Brown-out event interrupt*/ + .long Reserved78_IRQHandler /* Reserved interrupt*/ + .long TEMP_LOW_HIGH_IRQHandler /* TempSensor low/high interrupt*/ + .long TEMP_PANIC_IRQHandler /* TempSensor panic interrupt*/ + .long USB_PHY1_IRQHandler /* USBPHY (UTMI0), Interrupt*/ + .long USB_PHY2_IRQHandler /* USBPHY (UTMI1), Interrupt*/ + .long ADC1_IRQHandler /* ADC1 interrupt*/ + .long ADC2_IRQHandler /* ADC2 interrupt*/ + .long DCDC_IRQHandler /* DCDC interrupt*/ + .long Reserved86_IRQHandler /* Reserved interrupt*/ + .long Reserved87_IRQHandler /* Reserved interrupt*/ + .long GPIO1_INT0_IRQHandler /* Active HIGH Interrupt from INT0 from GPIO*/ + .long GPIO1_INT1_IRQHandler /* Active HIGH Interrupt from INT1 from GPIO*/ + .long GPIO1_INT2_IRQHandler /* Active HIGH Interrupt from INT2 from GPIO*/ + .long GPIO1_INT3_IRQHandler /* Active HIGH Interrupt from INT3 from GPIO*/ + .long GPIO1_INT4_IRQHandler /* Active HIGH Interrupt from INT4 from GPIO*/ + .long GPIO1_INT5_IRQHandler /* Active HIGH Interrupt from INT5 from GPIO*/ + .long GPIO1_INT6_IRQHandler /* Active HIGH Interrupt from INT6 from GPIO*/ + .long GPIO1_INT7_IRQHandler /* Active HIGH Interrupt from INT7 from GPIO*/ + .long GPIO1_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO1 signal 0 throughout 15*/ + .long GPIO1_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO1 signal 16 throughout 31*/ + .long GPIO2_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO2 signal 0 throughout 15*/ + .long GPIO2_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO2 signal 16 throughout 31*/ + .long GPIO3_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO3 signal 0 throughout 15*/ + .long GPIO3_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO3 signal 16 throughout 31*/ + .long GPIO4_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO4 signal 0 throughout 15*/ + .long GPIO4_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO4 signal 16 throughout 31*/ + .long GPIO5_Combined_0_15_IRQHandler /* Combined interrupt indication for GPIO5 signal 0 throughout 15*/ + .long GPIO5_Combined_16_31_IRQHandler /* Combined interrupt indication for GPIO5 signal 16 throughout 31*/ + .long FLEXIO1_IRQHandler /* FLEXIO1 interrupt*/ + .long FLEXIO2_IRQHandler /* FLEXIO2 interrupt*/ + .long WDOG1_IRQHandler /* WDOG1 interrupt*/ + .long RTWDOG_IRQHandler /* RTWDOG interrupt*/ + .long EWM_IRQHandler /* EWM interrupt*/ + .long CCM_1_IRQHandler /* CCM IRQ1 interrupt*/ + .long CCM_2_IRQHandler /* CCM IRQ2 interrupt*/ + .long GPC_IRQHandler /* GPC interrupt*/ + .long SRC_IRQHandler /* SRC interrupt*/ + .long Reserved115_IRQHandler /* Reserved interrupt*/ + .long GPT1_IRQHandler /* GPT1 interrupt*/ + .long GPT2_IRQHandler /* GPT2 interrupt*/ + .long PWM1_0_IRQHandler /* PWM1 capture 0, compare 0, or reload 0 interrupt*/ + .long PWM1_1_IRQHandler /* PWM1 capture 1, compare 1, or reload 0 interrupt*/ + .long PWM1_2_IRQHandler /* PWM1 capture 2, compare 2, or reload 0 interrupt*/ + .long PWM1_3_IRQHandler /* PWM1 capture 3, compare 3, or reload 0 interrupt*/ + .long PWM1_FAULT_IRQHandler /* PWM1 fault or reload error interrupt*/ + .long FLEXSPI2_IRQHandler /* FlexSPI2 interrupt*/ + .long FLEXSPI_IRQHandler /* FlexSPI0 interrupt*/ + .long SEMC_IRQHandler /* Reserved interrupt*/ + .long USDHC1_IRQHandler /* USDHC1 interrupt*/ + .long USDHC2_IRQHandler /* USDHC2 interrupt*/ + .long USB_OTG2_IRQHandler /* USBO2 USB OTG2*/ + .long USB_OTG1_IRQHandler /* USBO2 USB OTG1*/ + .long ENET_IRQHandler /* ENET interrupt*/ + .long ENET_1588_Timer_IRQHandler /* ENET_1588_Timer interrupt*/ + .long XBAR1_IRQ_0_1_IRQHandler /* XBAR1 interrupt*/ + .long XBAR1_IRQ_2_3_IRQHandler /* XBAR1 interrupt*/ + .long ADC_ETC_IRQ0_IRQHandler /* ADCETC IRQ0 interrupt*/ + .long ADC_ETC_IRQ1_IRQHandler /* ADCETC IRQ1 interrupt*/ + .long ADC_ETC_IRQ2_IRQHandler /* ADCETC IRQ2 interrupt*/ + .long ADC_ETC_ERROR_IRQ_IRQHandler /* ADCETC Error IRQ interrupt*/ + .long PIT_IRQHandler /* PIT interrupt*/ + .long ACMP1_IRQHandler /* ACMP interrupt*/ + .long ACMP2_IRQHandler /* ACMP interrupt*/ + .long ACMP3_IRQHandler /* ACMP interrupt*/ + .long ACMP4_IRQHandler /* ACMP interrupt*/ + .long Reserved143_IRQHandler /* Reserved interrupt*/ + .long Reserved144_IRQHandler /* Reserved interrupt*/ + .long ENC1_IRQHandler /* ENC1 interrupt*/ + .long ENC2_IRQHandler /* ENC2 interrupt*/ + .long ENC3_IRQHandler /* ENC3 interrupt*/ + .long ENC4_IRQHandler /* ENC4 interrupt*/ + .long TMR1_IRQHandler /* TMR1 interrupt*/ + .long TMR2_IRQHandler /* TMR2 interrupt*/ + .long TMR3_IRQHandler /* TMR3 interrupt*/ + .long TMR4_IRQHandler /* TMR4 interrupt*/ + .long PWM2_0_IRQHandler /* PWM2 capture 0, compare 0, or reload 0 interrupt*/ + .long PWM2_1_IRQHandler /* PWM2 capture 1, compare 1, or reload 0 interrupt*/ + .long PWM2_2_IRQHandler /* PWM2 capture 2, compare 2, or reload 0 interrupt*/ + .long PWM2_3_IRQHandler /* PWM2 capture 3, compare 3, or reload 0 interrupt*/ + .long PWM2_FAULT_IRQHandler /* PWM2 fault or reload error interrupt*/ + .long PWM3_0_IRQHandler /* PWM3 capture 0, compare 0, or reload 0 interrupt*/ + .long PWM3_1_IRQHandler /* PWM3 capture 1, compare 1, or reload 0 interrupt*/ + .long PWM3_2_IRQHandler /* PWM3 capture 2, compare 2, or reload 0 interrupt*/ + .long PWM3_3_IRQHandler /* PWM3 capture 3, compare 3, or reload 0 interrupt*/ + .long PWM3_FAULT_IRQHandler /* PWM3 fault or reload error interrupt*/ + .long PWM4_0_IRQHandler /* PWM4 capture 0, compare 0, or reload 0 interrupt*/ + .long PWM4_1_IRQHandler /* PWM4 capture 1, compare 1, or reload 0 interrupt*/ + .long PWM4_2_IRQHandler /* PWM4 capture 2, compare 2, or reload 0 interrupt*/ + .long PWM4_3_IRQHandler /* PWM4 capture 3, compare 3, or reload 0 interrupt*/ + .long PWM4_FAULT_IRQHandler /* PWM4 fault or reload error interrupt*/ + .long ENET2_IRQHandler /* ENET2 interrupt*/ + .long ENET2_1588_Timer_IRQHandler /* ENET2_1588_Timer interrupt*/ + .long CAN3_IRQHandler /* CAN3 interrupt*/ + .long Reserved171_IRQHandler /* Reserved interrupt*/ + .long FLEXIO3_IRQHandler /* FLEXIO3 interrupt*/ + .long GPIO6_7_8_9_IRQHandler /* GPIO6, GPIO7, GPIO8, GPIO9 interrupt*/ + .long DefaultISR /* 174*/ + .long DefaultISR /* 175*/ + .long DefaultISR /* 176*/ + .long DefaultISR /* 177*/ + .long DefaultISR /* 178*/ + .long DefaultISR /* 179*/ + .long DefaultISR /* 180*/ + .long DefaultISR /* 181*/ + .long DefaultISR /* 182*/ + .long DefaultISR /* 183*/ + .long DefaultISR /* 184*/ + .long DefaultISR /* 185*/ + .long DefaultISR /* 186*/ + .long DefaultISR /* 187*/ + .long DefaultISR /* 188*/ + .long DefaultISR /* 189*/ + .long DefaultISR /* 190*/ + .long DefaultISR /* 191*/ + .long DefaultISR /* 192*/ + .long DefaultISR /* 193*/ + .long DefaultISR /* 194*/ + .long DefaultISR /* 195*/ + .long DefaultISR /* 196*/ + .long DefaultISR /* 197*/ + .long DefaultISR /* 198*/ + .long DefaultISR /* 199*/ + .long DefaultISR /* 200*/ + .long DefaultISR /* 201*/ + .long DefaultISR /* 202*/ + .long DefaultISR /* 203*/ + .long DefaultISR /* 204*/ + .long DefaultISR /* 205*/ + .long DefaultISR /* 206*/ + .long DefaultISR /* 207*/ + .long DefaultISR /* 208*/ + .long DefaultISR /* 209*/ + .long DefaultISR /* 210*/ + .long DefaultISR /* 211*/ + .long DefaultISR /* 212*/ + .long DefaultISR /* 213*/ + .long DefaultISR /* 214*/ + .long DefaultISR /* 215*/ + .long DefaultISR /* 216*/ + .long DefaultISR /* 217*/ + .long DefaultISR /* 218*/ + .long DefaultISR /* 219*/ + .long DefaultISR /* 220*/ + .long DefaultISR /* 221*/ + .long DefaultISR /* 222*/ + .long DefaultISR /* 223*/ + .long DefaultISR /* 224*/ + .long DefaultISR /* 225*/ + .long DefaultISR /* 226*/ + .long DefaultISR /* 227*/ + .long DefaultISR /* 228*/ + .long DefaultISR /* 229*/ + .long DefaultISR /* 230*/ + .long DefaultISR /* 231*/ + .long DefaultISR /* 232*/ + .long DefaultISR /* 233*/ + .long DefaultISR /* 234*/ + .long DefaultISR /* 235*/ + .long DefaultISR /* 236*/ + .long DefaultISR /* 237*/ + .long DefaultISR /* 238*/ + .long DefaultISR /* 239*/ + .long DefaultISR /* 240*/ + .long DefaultISR /* 241*/ + .long DefaultISR /* 242*/ + .long DefaultISR /* 243*/ + .long DefaultISR /* 244*/ + .long DefaultISR /* 245*/ + .long DefaultISR /* 246*/ + .long DefaultISR /* 247*/ + .long DefaultISR /* 248*/ + .long DefaultISR /* 249*/ + .long DefaultISR /* 250*/ + .long DefaultISR /* 251*/ + .long DefaultISR /* 252*/ + .long DefaultISR /* 253*/ + .long DefaultISR /* 254*/ + .long 0xFFFFFFFF /* Reserved for user TRIM value*/ + + .size __isr_vector, . - __isr_vector + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__isr_vector + str r1, [r0] + ldr r2, [r1] + msr msp, r2 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * __noncachedata_start__/__noncachedata_end__ : none cachable region + * __ram_function_start__/__ram_function_end__ : ramfunction region + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#ifdef __PERFORMANCE_IMPLEMENTATION +/* Here are two copies of loop implementations. First one favors performance + * and the second one favors code size. Default uses the second one. + * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */ + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#else /* code size implemenation */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#endif +#ifdef __STARTUP_INITIALIZE_RAMFUNCTION + ldr r2, =__ram_function_start__ + ldr r3, =__ram_function_end__ +#ifdef __PERFORMANCE_IMPLEMENTATION +/* Here are two copies of loop implementations. First one favors performance + * and the second one favors code size. Default uses the second one. + * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */ + subs r3, r2 + ble .LC_ramfunc_copy_end +.LC_ramfunc_copy_start: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC_ramfunc_copy_start +.LC_ramfunc_copy_end: +#else /* code size implemenation */ +.LC_ramfunc_copy_start: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC_ramfunc_copy_start +#endif +#endif /* __STARTUP_INITIALIZE_RAMFUNCTION */ +#ifdef __STARTUP_INITIALIZE_NONCACHEDATA + ldr r2, =__noncachedata_start__ + ldr r3, =__noncachedata_init_end__ +#ifdef __PERFORMANCE_IMPLEMENTATION +/* Here are two copies of loop implementations. First one favors performance + * and the second one favors code size. Default uses the second one. + * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */ + subs r3, r2 + ble .LC3 +.LC2: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC2 +.LC3: +#else /* code size implemenation */ +.LC2: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC2 +#endif +/* zero inited ncache section initialization */ + ldr r3, =__noncachedata_end__ + movs r0,0 +.LC4: + cmp r2,r3 + itt lt + strlt r0,[r2],#4 + blt .LC4 +#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */ + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC5: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC5 +#endif /* __STARTUP_CLEAR_BSS */ + + cpsie i /* Unmask interrupts */ +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak DMA0_DMA16_IRQHandler + .type DMA0_DMA16_IRQHandler, %function +DMA0_DMA16_IRQHandler: + ldr r0,=DMA0_DMA16_DriverIRQHandler + bx r0 + .size DMA0_DMA16_IRQHandler, . - DMA0_DMA16_IRQHandler + + .align 1 + .thumb_func + .weak DMA1_DMA17_IRQHandler + .type DMA1_DMA17_IRQHandler, %function +DMA1_DMA17_IRQHandler: + ldr r0,=DMA1_DMA17_DriverIRQHandler + bx r0 + .size DMA1_DMA17_IRQHandler, . - DMA1_DMA17_IRQHandler + + .align 1 + .thumb_func + .weak DMA2_DMA18_IRQHandler + .type DMA2_DMA18_IRQHandler, %function +DMA2_DMA18_IRQHandler: + ldr r0,=DMA2_DMA18_DriverIRQHandler + bx r0 + .size DMA2_DMA18_IRQHandler, . - DMA2_DMA18_IRQHandler + + .align 1 + .thumb_func + .weak DMA3_DMA19_IRQHandler + .type DMA3_DMA19_IRQHandler, %function +DMA3_DMA19_IRQHandler: + ldr r0,=DMA3_DMA19_DriverIRQHandler + bx r0 + .size DMA3_DMA19_IRQHandler, . - DMA3_DMA19_IRQHandler + + .align 1 + .thumb_func + .weak DMA4_DMA20_IRQHandler + .type DMA4_DMA20_IRQHandler, %function +DMA4_DMA20_IRQHandler: + ldr r0,=DMA4_DMA20_DriverIRQHandler + bx r0 + .size DMA4_DMA20_IRQHandler, . - DMA4_DMA20_IRQHandler + + .align 1 + .thumb_func + .weak DMA5_DMA21_IRQHandler + .type DMA5_DMA21_IRQHandler, %function +DMA5_DMA21_IRQHandler: + ldr r0,=DMA5_DMA21_DriverIRQHandler + bx r0 + .size DMA5_DMA21_IRQHandler, . - DMA5_DMA21_IRQHandler + + .align 1 + .thumb_func + .weak DMA6_DMA22_IRQHandler + .type DMA6_DMA22_IRQHandler, %function +DMA6_DMA22_IRQHandler: + ldr r0,=DMA6_DMA22_DriverIRQHandler + bx r0 + .size DMA6_DMA22_IRQHandler, . - DMA6_DMA22_IRQHandler + + .align 1 + .thumb_func + .weak DMA7_DMA23_IRQHandler + .type DMA7_DMA23_IRQHandler, %function +DMA7_DMA23_IRQHandler: + ldr r0,=DMA7_DMA23_DriverIRQHandler + bx r0 + .size DMA7_DMA23_IRQHandler, . - DMA7_DMA23_IRQHandler + + .align 1 + .thumb_func + .weak DMA8_DMA24_IRQHandler + .type DMA8_DMA24_IRQHandler, %function +DMA8_DMA24_IRQHandler: + ldr r0,=DMA8_DMA24_DriverIRQHandler + bx r0 + .size DMA8_DMA24_IRQHandler, . - DMA8_DMA24_IRQHandler + + .align 1 + .thumb_func + .weak DMA9_DMA25_IRQHandler + .type DMA9_DMA25_IRQHandler, %function +DMA9_DMA25_IRQHandler: + ldr r0,=DMA9_DMA25_DriverIRQHandler + bx r0 + .size DMA9_DMA25_IRQHandler, . - DMA9_DMA25_IRQHandler + + .align 1 + .thumb_func + .weak DMA10_DMA26_IRQHandler + .type DMA10_DMA26_IRQHandler, %function +DMA10_DMA26_IRQHandler: + ldr r0,=DMA10_DMA26_DriverIRQHandler + bx r0 + .size DMA10_DMA26_IRQHandler, . - DMA10_DMA26_IRQHandler + + .align 1 + .thumb_func + .weak DMA11_DMA27_IRQHandler + .type DMA11_DMA27_IRQHandler, %function +DMA11_DMA27_IRQHandler: + ldr r0,=DMA11_DMA27_DriverIRQHandler + bx r0 + .size DMA11_DMA27_IRQHandler, . - DMA11_DMA27_IRQHandler + + .align 1 + .thumb_func + .weak DMA12_DMA28_IRQHandler + .type DMA12_DMA28_IRQHandler, %function +DMA12_DMA28_IRQHandler: + ldr r0,=DMA12_DMA28_DriverIRQHandler + bx r0 + .size DMA12_DMA28_IRQHandler, . - DMA12_DMA28_IRQHandler + + .align 1 + .thumb_func + .weak DMA13_DMA29_IRQHandler + .type DMA13_DMA29_IRQHandler, %function +DMA13_DMA29_IRQHandler: + ldr r0,=DMA13_DMA29_DriverIRQHandler + bx r0 + .size DMA13_DMA29_IRQHandler, . - DMA13_DMA29_IRQHandler + + .align 1 + .thumb_func + .weak DMA14_DMA30_IRQHandler + .type DMA14_DMA30_IRQHandler, %function +DMA14_DMA30_IRQHandler: + ldr r0,=DMA14_DMA30_DriverIRQHandler + bx r0 + .size DMA14_DMA30_IRQHandler, . - DMA14_DMA30_IRQHandler + + .align 1 + .thumb_func + .weak DMA15_DMA31_IRQHandler + .type DMA15_DMA31_IRQHandler, %function +DMA15_DMA31_IRQHandler: + ldr r0,=DMA15_DMA31_DriverIRQHandler + bx r0 + .size DMA15_DMA31_IRQHandler, . - DMA15_DMA31_IRQHandler + + .align 1 + .thumb_func + .weak DMA_ERROR_IRQHandler + .type DMA_ERROR_IRQHandler, %function +DMA_ERROR_IRQHandler: + ldr r0,=DMA_ERROR_DriverIRQHandler + bx r0 + .size DMA_ERROR_IRQHandler, . - DMA_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak LPUART1_IRQHandler + .type LPUART1_IRQHandler, %function +LPUART1_IRQHandler: + ldr r0,=LPUART1_DriverIRQHandler + bx r0 + .size LPUART1_IRQHandler, . - LPUART1_IRQHandler + + .align 1 + .thumb_func + .weak LPUART2_IRQHandler + .type LPUART2_IRQHandler, %function +LPUART2_IRQHandler: + ldr r0,=LPUART2_DriverIRQHandler + bx r0 + .size LPUART2_IRQHandler, . - LPUART2_IRQHandler + + .align 1 + .thumb_func + .weak LPUART3_IRQHandler + .type LPUART3_IRQHandler, %function +LPUART3_IRQHandler: + ldr r0,=LPUART3_DriverIRQHandler + bx r0 + .size LPUART3_IRQHandler, . - LPUART3_IRQHandler + + .align 1 + .thumb_func + .weak LPUART4_IRQHandler + .type LPUART4_IRQHandler, %function +LPUART4_IRQHandler: + ldr r0,=LPUART4_DriverIRQHandler + bx r0 + .size LPUART4_IRQHandler, . - LPUART4_IRQHandler + + .align 1 + .thumb_func + .weak LPUART5_IRQHandler + .type LPUART5_IRQHandler, %function +LPUART5_IRQHandler: + ldr r0,=LPUART5_DriverIRQHandler + bx r0 + .size LPUART5_IRQHandler, . - LPUART5_IRQHandler + + .align 1 + .thumb_func + .weak LPUART6_IRQHandler + .type LPUART6_IRQHandler, %function +LPUART6_IRQHandler: + ldr r0,=LPUART6_DriverIRQHandler + bx r0 + .size LPUART6_IRQHandler, . - LPUART6_IRQHandler + + .align 1 + .thumb_func + .weak LPUART7_IRQHandler + .type LPUART7_IRQHandler, %function +LPUART7_IRQHandler: + ldr r0,=LPUART7_DriverIRQHandler + bx r0 + .size LPUART7_IRQHandler, . - LPUART7_IRQHandler + + .align 1 + .thumb_func + .weak LPUART8_IRQHandler + .type LPUART8_IRQHandler, %function +LPUART8_IRQHandler: + ldr r0,=LPUART8_DriverIRQHandler + bx r0 + .size LPUART8_IRQHandler, . - LPUART8_IRQHandler + + .align 1 + .thumb_func + .weak LPI2C1_IRQHandler + .type LPI2C1_IRQHandler, %function +LPI2C1_IRQHandler: + ldr r0,=LPI2C1_DriverIRQHandler + bx r0 + .size LPI2C1_IRQHandler, . - LPI2C1_IRQHandler + + .align 1 + .thumb_func + .weak LPI2C2_IRQHandler + .type LPI2C2_IRQHandler, %function +LPI2C2_IRQHandler: + ldr r0,=LPI2C2_DriverIRQHandler + bx r0 + .size LPI2C2_IRQHandler, . - LPI2C2_IRQHandler + + .align 1 + .thumb_func + .weak LPI2C3_IRQHandler + .type LPI2C3_IRQHandler, %function +LPI2C3_IRQHandler: + ldr r0,=LPI2C3_DriverIRQHandler + bx r0 + .size LPI2C3_IRQHandler, . - LPI2C3_IRQHandler + + .align 1 + .thumb_func + .weak LPI2C4_IRQHandler + .type LPI2C4_IRQHandler, %function +LPI2C4_IRQHandler: + ldr r0,=LPI2C4_DriverIRQHandler + bx r0 + .size LPI2C4_IRQHandler, . - LPI2C4_IRQHandler + + .align 1 + .thumb_func + .weak LPSPI1_IRQHandler + .type LPSPI1_IRQHandler, %function +LPSPI1_IRQHandler: + ldr r0,=LPSPI1_DriverIRQHandler + bx r0 + .size LPSPI1_IRQHandler, . - LPSPI1_IRQHandler + + .align 1 + .thumb_func + .weak LPSPI2_IRQHandler + .type LPSPI2_IRQHandler, %function +LPSPI2_IRQHandler: + ldr r0,=LPSPI2_DriverIRQHandler + bx r0 + .size LPSPI2_IRQHandler, . - LPSPI2_IRQHandler + + .align 1 + .thumb_func + .weak LPSPI3_IRQHandler + .type LPSPI3_IRQHandler, %function +LPSPI3_IRQHandler: + ldr r0,=LPSPI3_DriverIRQHandler + bx r0 + .size LPSPI3_IRQHandler, . - LPSPI3_IRQHandler + + .align 1 + .thumb_func + .weak LPSPI4_IRQHandler + .type LPSPI4_IRQHandler, %function +LPSPI4_IRQHandler: + ldr r0,=LPSPI4_DriverIRQHandler + bx r0 + .size LPSPI4_IRQHandler, . - LPSPI4_IRQHandler + + .align 1 + .thumb_func + .weak CAN1_IRQHandler + .type CAN1_IRQHandler, %function +CAN1_IRQHandler: + ldr r0,=CAN1_DriverIRQHandler + bx r0 + .size CAN1_IRQHandler, . - CAN1_IRQHandler + + .align 1 + .thumb_func + .weak CAN2_IRQHandler + .type CAN2_IRQHandler, %function +CAN2_IRQHandler: + ldr r0,=CAN2_DriverIRQHandler + bx r0 + .size CAN2_IRQHandler, . - CAN2_IRQHandler + + .align 1 + .thumb_func + .weak SAI1_IRQHandler + .type SAI1_IRQHandler, %function +SAI1_IRQHandler: + ldr r0,=SAI1_DriverIRQHandler + bx r0 + .size SAI1_IRQHandler, . - SAI1_IRQHandler + + .align 1 + .thumb_func + .weak SAI2_IRQHandler + .type SAI2_IRQHandler, %function +SAI2_IRQHandler: + ldr r0,=SAI2_DriverIRQHandler + bx r0 + .size SAI2_IRQHandler, . - SAI2_IRQHandler + + .align 1 + .thumb_func + .weak SAI3_RX_IRQHandler + .type SAI3_RX_IRQHandler, %function +SAI3_RX_IRQHandler: + ldr r0,=SAI3_RX_DriverIRQHandler + bx r0 + .size SAI3_RX_IRQHandler, . - SAI3_RX_IRQHandler + + .align 1 + .thumb_func + .weak SAI3_TX_IRQHandler + .type SAI3_TX_IRQHandler, %function +SAI3_TX_IRQHandler: + ldr r0,=SAI3_TX_DriverIRQHandler + bx r0 + .size SAI3_TX_IRQHandler, . - SAI3_TX_IRQHandler + + .align 1 + .thumb_func + .weak SPDIF_IRQHandler + .type SPDIF_IRQHandler, %function +SPDIF_IRQHandler: + ldr r0,=SPDIF_DriverIRQHandler + bx r0 + .size SPDIF_IRQHandler, . - SPDIF_IRQHandler + + .align 1 + .thumb_func + .weak FLEXIO1_IRQHandler + .type FLEXIO1_IRQHandler, %function +FLEXIO1_IRQHandler: + ldr r0,=FLEXIO1_DriverIRQHandler + bx r0 + .size FLEXIO1_IRQHandler, . - FLEXIO1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXIO2_IRQHandler + .type FLEXIO2_IRQHandler, %function +FLEXIO2_IRQHandler: + ldr r0,=FLEXIO2_DriverIRQHandler + bx r0 + .size FLEXIO2_IRQHandler, . - FLEXIO2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXSPI2_IRQHandler + .type FLEXSPI2_IRQHandler, %function +FLEXSPI2_IRQHandler: + ldr r0,=FLEXSPI2_DriverIRQHandler + bx r0 + .size FLEXSPI2_IRQHandler, . - FLEXSPI2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXSPI_IRQHandler + .type FLEXSPI_IRQHandler, %function +FLEXSPI_IRQHandler: + ldr r0,=FLEXSPI_DriverIRQHandler + bx r0 + .size FLEXSPI_IRQHandler, . - FLEXSPI_IRQHandler + + .align 1 + .thumb_func + .weak USDHC1_IRQHandler + .type USDHC1_IRQHandler, %function +USDHC1_IRQHandler: + ldr r0,=USDHC1_DriverIRQHandler + bx r0 + .size USDHC1_IRQHandler, . - USDHC1_IRQHandler + + .align 1 + .thumb_func + .weak USDHC2_IRQHandler + .type USDHC2_IRQHandler, %function +USDHC2_IRQHandler: + ldr r0,=USDHC2_DriverIRQHandler + bx r0 + .size USDHC2_IRQHandler, . - USDHC2_IRQHandler + + .align 1 + .thumb_func + .weak ENET_IRQHandler + .type ENET_IRQHandler, %function +ENET_IRQHandler: + ldr r0,=ENET_DriverIRQHandler + bx r0 + .size ENET_IRQHandler, . - ENET_IRQHandler + + .align 1 + .thumb_func + .weak ENET_1588_Timer_IRQHandler + .type ENET_1588_Timer_IRQHandler, %function +ENET_1588_Timer_IRQHandler: + ldr r0,=ENET_1588_Timer_DriverIRQHandler + bx r0 + .size ENET_1588_Timer_IRQHandler, . - ENET_1588_Timer_IRQHandler + + .align 1 + .thumb_func + .weak ENET2_IRQHandler + .type ENET2_IRQHandler, %function +ENET2_IRQHandler: + ldr r0,=ENET2_DriverIRQHandler + bx r0 + .size ENET2_IRQHandler, . - ENET2_IRQHandler + + .align 1 + .thumb_func + .weak ENET2_1588_Timer_IRQHandler + .type ENET2_1588_Timer_IRQHandler, %function +ENET2_1588_Timer_IRQHandler: + ldr r0,=ENET2_1588_Timer_DriverIRQHandler + bx r0 + .size ENET2_1588_Timer_IRQHandler, . - ENET2_1588_Timer_IRQHandler + + .align 1 + .thumb_func + .weak CAN3_IRQHandler + .type CAN3_IRQHandler, %function +CAN3_IRQHandler: + ldr r0,=CAN3_DriverIRQHandler + bx r0 + .size CAN3_IRQHandler, . - CAN3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXIO3_IRQHandler + .type FLEXIO3_IRQHandler, %function +FLEXIO3_IRQHandler: + ldr r0,=FLEXIO3_DriverIRQHandler + bx r0 + .size FLEXIO3_IRQHandler, . - FLEXIO3_IRQHandler + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler DMA0_DMA16_DriverIRQHandler + def_irq_handler DMA1_DMA17_DriverIRQHandler + def_irq_handler DMA2_DMA18_DriverIRQHandler + def_irq_handler DMA3_DMA19_DriverIRQHandler + def_irq_handler DMA4_DMA20_DriverIRQHandler + def_irq_handler DMA5_DMA21_DriverIRQHandler + def_irq_handler DMA6_DMA22_DriverIRQHandler + def_irq_handler DMA7_DMA23_DriverIRQHandler + def_irq_handler DMA8_DMA24_DriverIRQHandler + def_irq_handler DMA9_DMA25_DriverIRQHandler + def_irq_handler DMA10_DMA26_DriverIRQHandler + def_irq_handler DMA11_DMA27_DriverIRQHandler + def_irq_handler DMA12_DMA28_DriverIRQHandler + def_irq_handler DMA13_DMA29_DriverIRQHandler + def_irq_handler DMA14_DMA30_DriverIRQHandler + def_irq_handler DMA15_DMA31_DriverIRQHandler + def_irq_handler DMA_ERROR_DriverIRQHandler + def_irq_handler CTI0_ERROR_IRQHandler + def_irq_handler CTI1_ERROR_IRQHandler + def_irq_handler CORE_IRQHandler + def_irq_handler LPUART1_DriverIRQHandler + def_irq_handler LPUART2_DriverIRQHandler + def_irq_handler LPUART3_DriverIRQHandler + def_irq_handler LPUART4_DriverIRQHandler + def_irq_handler LPUART5_DriverIRQHandler + def_irq_handler LPUART6_DriverIRQHandler + def_irq_handler LPUART7_DriverIRQHandler + def_irq_handler LPUART8_DriverIRQHandler + def_irq_handler LPI2C1_DriverIRQHandler + def_irq_handler LPI2C2_DriverIRQHandler + def_irq_handler LPI2C3_DriverIRQHandler + def_irq_handler LPI2C4_DriverIRQHandler + def_irq_handler LPSPI1_DriverIRQHandler + def_irq_handler LPSPI2_DriverIRQHandler + def_irq_handler LPSPI3_DriverIRQHandler + def_irq_handler LPSPI4_DriverIRQHandler + def_irq_handler CAN1_DriverIRQHandler + def_irq_handler CAN2_DriverIRQHandler + def_irq_handler FLEXRAM_IRQHandler + def_irq_handler KPP_IRQHandler + def_irq_handler TSC_DIG_IRQHandler + def_irq_handler GPR_IRQ_IRQHandler + def_irq_handler Reserved58_IRQHandler + def_irq_handler Reserved59_IRQHandler + def_irq_handler Reserved60_IRQHandler + def_irq_handler WDOG2_IRQHandler + def_irq_handler SNVS_HP_WRAPPER_IRQHandler + def_irq_handler SNVS_HP_WRAPPER_TZ_IRQHandler + def_irq_handler SNVS_LP_WRAPPER_IRQHandler + def_irq_handler CSU_IRQHandler + def_irq_handler DCP_IRQHandler + def_irq_handler DCP_VMI_IRQHandler + def_irq_handler Reserved68_IRQHandler + def_irq_handler TRNG_IRQHandler + def_irq_handler SJC_IRQHandler + def_irq_handler BEE_IRQHandler + def_irq_handler SAI1_DriverIRQHandler + def_irq_handler SAI2_DriverIRQHandler + def_irq_handler SAI3_RX_DriverIRQHandler + def_irq_handler SAI3_TX_DriverIRQHandler + def_irq_handler SPDIF_DriverIRQHandler + def_irq_handler PMU_EVENT_IRQHandler + def_irq_handler Reserved78_IRQHandler + def_irq_handler TEMP_LOW_HIGH_IRQHandler + def_irq_handler TEMP_PANIC_IRQHandler + def_irq_handler USB_PHY1_IRQHandler + def_irq_handler USB_PHY2_IRQHandler + def_irq_handler ADC1_IRQHandler + def_irq_handler ADC2_IRQHandler + def_irq_handler DCDC_IRQHandler + def_irq_handler Reserved86_IRQHandler + def_irq_handler Reserved87_IRQHandler + def_irq_handler GPIO1_INT0_IRQHandler + def_irq_handler GPIO1_INT1_IRQHandler + def_irq_handler GPIO1_INT2_IRQHandler + def_irq_handler GPIO1_INT3_IRQHandler + def_irq_handler GPIO1_INT4_IRQHandler + def_irq_handler GPIO1_INT5_IRQHandler + def_irq_handler GPIO1_INT6_IRQHandler + def_irq_handler GPIO1_INT7_IRQHandler + def_irq_handler GPIO1_Combined_0_15_IRQHandler + def_irq_handler GPIO1_Combined_16_31_IRQHandler + def_irq_handler GPIO2_Combined_0_15_IRQHandler + def_irq_handler GPIO2_Combined_16_31_IRQHandler + def_irq_handler GPIO3_Combined_0_15_IRQHandler + def_irq_handler GPIO3_Combined_16_31_IRQHandler + def_irq_handler GPIO4_Combined_0_15_IRQHandler + def_irq_handler GPIO4_Combined_16_31_IRQHandler + def_irq_handler GPIO5_Combined_0_15_IRQHandler + def_irq_handler GPIO5_Combined_16_31_IRQHandler + def_irq_handler FLEXIO1_DriverIRQHandler + def_irq_handler FLEXIO2_DriverIRQHandler + def_irq_handler WDOG1_IRQHandler + def_irq_handler RTWDOG_IRQHandler + def_irq_handler EWM_IRQHandler + def_irq_handler CCM_1_IRQHandler + def_irq_handler CCM_2_IRQHandler + def_irq_handler GPC_IRQHandler + def_irq_handler SRC_IRQHandler + def_irq_handler Reserved115_IRQHandler + def_irq_handler GPT1_IRQHandler + def_irq_handler GPT2_IRQHandler + def_irq_handler PWM1_0_IRQHandler + def_irq_handler PWM1_1_IRQHandler + def_irq_handler PWM1_2_IRQHandler + def_irq_handler PWM1_3_IRQHandler + def_irq_handler PWM1_FAULT_IRQHandler + def_irq_handler FLEXSPI2_DriverIRQHandler + def_irq_handler FLEXSPI_DriverIRQHandler + def_irq_handler SEMC_IRQHandler + def_irq_handler USDHC1_DriverIRQHandler + def_irq_handler USDHC2_DriverIRQHandler + def_irq_handler USB_OTG2_IRQHandler + def_irq_handler USB_OTG1_IRQHandler + def_irq_handler ENET_DriverIRQHandler + def_irq_handler ENET_1588_Timer_DriverIRQHandler + def_irq_handler XBAR1_IRQ_0_1_IRQHandler + def_irq_handler XBAR1_IRQ_2_3_IRQHandler + def_irq_handler ADC_ETC_IRQ0_IRQHandler + def_irq_handler ADC_ETC_IRQ1_IRQHandler + def_irq_handler ADC_ETC_IRQ2_IRQHandler + def_irq_handler ADC_ETC_ERROR_IRQ_IRQHandler + def_irq_handler PIT_IRQHandler + def_irq_handler ACMP1_IRQHandler + def_irq_handler ACMP2_IRQHandler + def_irq_handler ACMP3_IRQHandler + def_irq_handler ACMP4_IRQHandler + def_irq_handler Reserved143_IRQHandler + def_irq_handler Reserved144_IRQHandler + def_irq_handler ENC1_IRQHandler + def_irq_handler ENC2_IRQHandler + def_irq_handler ENC3_IRQHandler + def_irq_handler ENC4_IRQHandler + def_irq_handler TMR1_IRQHandler + def_irq_handler TMR2_IRQHandler + def_irq_handler TMR3_IRQHandler + def_irq_handler TMR4_IRQHandler + def_irq_handler PWM2_0_IRQHandler + def_irq_handler PWM2_1_IRQHandler + def_irq_handler PWM2_2_IRQHandler + def_irq_handler PWM2_3_IRQHandler + def_irq_handler PWM2_FAULT_IRQHandler + def_irq_handler PWM3_0_IRQHandler + def_irq_handler PWM3_1_IRQHandler + def_irq_handler PWM3_2_IRQHandler + def_irq_handler PWM3_3_IRQHandler + def_irq_handler PWM3_FAULT_IRQHandler + def_irq_handler PWM4_0_IRQHandler + def_irq_handler PWM4_1_IRQHandler + def_irq_handler PWM4_2_IRQHandler + def_irq_handler PWM4_3_IRQHandler + def_irq_handler PWM4_FAULT_IRQHandler + def_irq_handler ENET2_DriverIRQHandler + def_irq_handler ENET2_1588_Timer_DriverIRQHandler + def_irq_handler CAN3_DriverIRQHandler + def_irq_handler Reserved171_IRQHandler + def_irq_handler FLEXIO3_DriverIRQHandler + def_irq_handler GPIO6_7_8_9_IRQHandler + + .end diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/iar/MIMXRT1061xxxxx_flexspi_nor.icf b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/iar/MIMXRT1061xxxxx_flexspi_nor.icf new file mode 100644 index 0000000000..c8b8a4c8b5 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/iar/MIMXRT1061xxxxx_flexspi_nor.icf @@ -0,0 +1,94 @@ +/* +** ################################################################### +** Processors: MIMXRT1061CVJ5A +** MIMXRT1061CVL5A +** MIMXRT1061DVJ6A +** MIMXRT1061DVL6A +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1060RM Rev.1, 12/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b190312 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x60002000; +define symbol m_interrupts_end = 0x600023FF; + +define symbol m_text_start = 0x60002400; +define symbol m_text_end = 0x607FFFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2001FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x202BFFFF; + +define exported symbol m_boot_hdr_conf_start = 0x60000000; +define symbol m_boot_hdr_ivt_start = 0x60001000; +define symbol m_boot_hdr_boot_data_start = 0x60001020; +define symbol m_boot_hdr_dcd_data_start = 0x60001030; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; +place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; +place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; +place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; + +keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; + +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in DATA_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; + diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/iar/MIMXRT1061xxxxx_flexspi_nor_sdram.icf b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/iar/MIMXRT1061xxxxx_flexspi_nor_sdram.icf new file mode 100644 index 0000000000..7d3670fde1 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/iar/MIMXRT1061xxxxx_flexspi_nor_sdram.icf @@ -0,0 +1,102 @@ +/* +** ################################################################### +** Processors: MIMXRT1061CVJ5A +** MIMXRT1061CVL5A +** MIMXRT1061DVJ6A +** MIMXRT1061DVL6A +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1060RM Rev.1, 12/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b190312 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x60002000; +define symbol m_interrupts_end = 0x600023FF; + +define symbol m_text_start = 0x60002400; +define symbol m_text_end = 0x607FFFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2001FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x202BFFFF; + +define symbol m_data3_start = 0x80000000; +define symbol m_data3_end = 0x81DFFFFF; + +define symbol m_ncache_start = 0x81E00000; +define symbol m_ncache_end = 0x81FFFFFF; + +define exported symbol m_boot_hdr_conf_start = 0x60000000; +define symbol m_boot_hdr_ivt_start = 0x60001000; +define symbol m_boot_hdr_boot_data_start = 0x60001020; +define symbol m_boot_hdr_dcd_data_start = 0x60001030; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { first readwrite, section m_usb_dma_init_data }; +define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; +define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf }; +place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt }; +place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data }; +place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data }; + +keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; + +place in TEXT_region { readonly }; +place in DATA3_region { block RW }; +place in DATA3_region { block ZI }; +place in DATA3_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in NCACHE_region { block NCACHE_VAR }; + diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/iar/MIMXRT1061xxxxx_ram.icf b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/iar/MIMXRT1061xxxxx_ram.icf new file mode 100644 index 0000000000..57b4011a8a --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/iar/MIMXRT1061xxxxx_ram.icf @@ -0,0 +1,82 @@ +/* +** ################################################################### +** Processors: MIMXRT1061CVJ5A +** MIMXRT1061CVL5A +** MIMXRT1061DVJ6A +** MIMXRT1061DVL6A +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1060RM Rev.1, 12/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b190312 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_text_start = 0x00000400; +define symbol m_text_end = 0x0001FFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2001FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x202BFFFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; +define block NCACHE_VAR { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in DATA_region { block NCACHE_VAR }; +place in CSTACK_region { block CSTACK }; + diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/iar/MIMXRT1061xxxxx_sdram.icf b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/iar/MIMXRT1061xxxxx_sdram.icf new file mode 100644 index 0000000000..3b56109cd1 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/iar/MIMXRT1061xxxxx_sdram.icf @@ -0,0 +1,90 @@ +/* +** ################################################################### +** Processors: MIMXRT1061CVJ5A +** MIMXRT1061CVL5A +** MIMXRT1061DVJ6A +** MIMXRT1061DVL6A +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1060RM Rev.1, 12/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b190312 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000003FF; + +define symbol m_text_start = 0x00000400; +define symbol m_text_end = 0x0001FFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2001FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x202BFFFF; + +define symbol m_data3_start = 0x80000000; +define symbol m_data3_end = 0x81DFFFFF; + +define symbol m_ncache_start = 0x81E00000; +define symbol m_ncache_end = 0x81FFFFFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end]; +define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__]; +define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { first readwrite, section m_usb_dma_init_data }; +define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; +define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in DATA3_region { block RW }; +place in DATA3_region { block ZI }; +place in DATA3_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in NCACHE_region { block NCACHE_VAR }; + diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/iar/MIMXRT1061xxxxx_sdram_txt.icf b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/iar/MIMXRT1061xxxxx_sdram_txt.icf new file mode 100644 index 0000000000..a2d7b8c967 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/iar/MIMXRT1061xxxxx_sdram_txt.icf @@ -0,0 +1,90 @@ +/* +** ################################################################### +** Processors: MIMXRT1061CVJ5A +** MIMXRT1061CVL5A +** MIMXRT1061DVJ6A +** MIMXRT1061DVL6A +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: IMXRT1060RM Rev.1, 12/2018 +** Version: rev. 0.1, 2017-01-10 +** Build: b190312 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + +define symbol m_interrupts_start = 0x80000000; +define symbol m_interrupts_end = 0x800003FF; + +define symbol m_text_start = 0x80000400; +define symbol m_text_end = 0x801FFFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2001FFFF; + +define symbol m_data2_start = 0x20200000; +define symbol m_data2_end = 0x202BFFFF; + +define symbol m_data3_start = 0x80200000; +define symbol m_data3_end = 0x81DFFFFF; + +define symbol m_ncache_start = 0x81E00000; +define symbol m_ncache_end = 0x81FFFFFF; + +/* Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define exported symbol __VECTOR_TABLE = m_interrupts_start; +define exported symbol __VECTOR_RAM = m_interrupts_start; +define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0; + +define memory mem with size = 4G; +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; + +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region DATA2_region = mem:[from m_data2_start to m_data2_end-__size_cstack__]; +define region DATA3_region = mem:[from m_data3_start to m_data3_end]; +define region CSTACK_region = mem:[from m_data2_end-__size_cstack__+1 to m_data2_end]; +define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { first readwrite, section m_usb_dma_init_data }; +define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; +define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; + +initialize by copy { readwrite, section .textrw }; +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; + +place in TEXT_region { readonly }; +place in DATA2_region { block RW }; +place in DATA2_region { block ZI }; +place in DATA2_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in NCACHE_region { block NCACHE_VAR }; + diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/iar/startup_MIMXRT1061.s b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/iar/startup_MIMXRT1061.s new file mode 100644 index 0000000000..ad3483a07f --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/iar/startup_MIMXRT1061.s @@ -0,0 +1,1014 @@ +; ------------------------------------------------------------------------- +; @file: startup_MIMXRT1061.s +; @purpose: CMSIS Cortex-M7 Core Device Startup File +; MIMXRT1061 +; @version: 1.1 +; @date: 2018-11-27 +; @build: b190124 +; ------------------------------------------------------------------------- +; +; Copyright 1997-2016 Freescale Semiconductor, Inc. +; Copyright 2016-2019 NXP +; All rights reserved. +; +; SPDX-License-Identifier: BSD-3-Clause +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_DMA16_IRQHandler ;DMA channel 0/16 transfer complete + DCD DMA1_DMA17_IRQHandler ;DMA channel 1/17 transfer complete + DCD DMA2_DMA18_IRQHandler ;DMA channel 2/18 transfer complete + DCD DMA3_DMA19_IRQHandler ;DMA channel 3/19 transfer complete + DCD DMA4_DMA20_IRQHandler ;DMA channel 4/20 transfer complete + DCD DMA5_DMA21_IRQHandler ;DMA channel 5/21 transfer complete + DCD DMA6_DMA22_IRQHandler ;DMA channel 6/22 transfer complete + DCD DMA7_DMA23_IRQHandler ;DMA channel 7/23 transfer complete + DCD DMA8_DMA24_IRQHandler ;DMA channel 8/24 transfer complete + DCD DMA9_DMA25_IRQHandler ;DMA channel 9/25 transfer complete + DCD DMA10_DMA26_IRQHandler ;DMA channel 10/26 transfer complete + DCD DMA11_DMA27_IRQHandler ;DMA channel 11/27 transfer complete + DCD DMA12_DMA28_IRQHandler ;DMA channel 12/28 transfer complete + DCD DMA13_DMA29_IRQHandler ;DMA channel 13/29 transfer complete + DCD DMA14_DMA30_IRQHandler ;DMA channel 14/30 transfer complete + DCD DMA15_DMA31_IRQHandler ;DMA channel 15/31 transfer complete + DCD DMA_ERROR_IRQHandler ;DMA error interrupt channels 0-15 / 16-31 + DCD CTI0_ERROR_IRQHandler ;CTI0_Error + DCD CTI1_ERROR_IRQHandler ;CTI1_Error + DCD CORE_IRQHandler ;CorePlatform exception IRQ + DCD LPUART1_IRQHandler ;LPUART1 TX interrupt and RX interrupt + DCD LPUART2_IRQHandler ;LPUART2 TX interrupt and RX interrupt + DCD LPUART3_IRQHandler ;LPUART3 TX interrupt and RX interrupt + DCD LPUART4_IRQHandler ;LPUART4 TX interrupt and RX interrupt + DCD LPUART5_IRQHandler ;LPUART5 TX interrupt and RX interrupt + DCD LPUART6_IRQHandler ;LPUART6 TX interrupt and RX interrupt + DCD LPUART7_IRQHandler ;LPUART7 TX interrupt and RX interrupt + DCD LPUART8_IRQHandler ;LPUART8 TX interrupt and RX interrupt + DCD LPI2C1_IRQHandler ;LPI2C1 interrupt + DCD LPI2C2_IRQHandler ;LPI2C2 interrupt + DCD LPI2C3_IRQHandler ;LPI2C3 interrupt + DCD LPI2C4_IRQHandler ;LPI2C4 interrupt + DCD LPSPI1_IRQHandler ;LPSPI1 single interrupt vector for all sources + DCD LPSPI2_IRQHandler ;LPSPI2 single interrupt vector for all sources + DCD LPSPI3_IRQHandler ;LPSPI3 single interrupt vector for all sources + DCD LPSPI4_IRQHandler ;LPSPI4 single interrupt vector for all sources + DCD CAN1_IRQHandler ;CAN1 interrupt + DCD CAN2_IRQHandler ;CAN2 interrupt + DCD FLEXRAM_IRQHandler ;FlexRAM address out of range Or access hit IRQ + DCD KPP_IRQHandler ;Keypad nterrupt + DCD TSC_DIG_IRQHandler ;TSC interrupt + DCD GPR_IRQ_IRQHandler ;GPR interrupt + DCD Reserved58_IRQHandler ;Reserved interrupt + DCD Reserved59_IRQHandler ;Reserved interrupt + DCD Reserved60_IRQHandler ;Reserved interrupt + DCD WDOG2_IRQHandler ;WDOG2 interrupt + DCD SNVS_HP_WRAPPER_IRQHandler ;SRTC Consolidated Interrupt. Non TZ + DCD SNVS_HP_WRAPPER_TZ_IRQHandler ;SRTC Security Interrupt. TZ + DCD SNVS_LP_WRAPPER_IRQHandler ;ON-OFF button press shorter than 5 secs (pulse event) + DCD CSU_IRQHandler ;CSU interrupt + DCD DCP_IRQHandler ;DCP_IRQ interrupt + DCD DCP_VMI_IRQHandler ;DCP_VMI_IRQ interrupt + DCD Reserved68_IRQHandler ;Reserved interrupt + DCD TRNG_IRQHandler ;TRNG interrupt + DCD SJC_IRQHandler ;SJC interrupt + DCD BEE_IRQHandler ;BEE interrupt + DCD SAI1_IRQHandler ;SAI1 interrupt + DCD SAI2_IRQHandler ;SAI1 interrupt + DCD SAI3_RX_IRQHandler ;SAI3 interrupt + DCD SAI3_TX_IRQHandler ;SAI3 interrupt + DCD SPDIF_IRQHandler ;SPDIF interrupt + DCD PMU_EVENT_IRQHandler ;Brown-out event interrupt + DCD Reserved78_IRQHandler ;Reserved interrupt + DCD TEMP_LOW_HIGH_IRQHandler ;TempSensor low/high interrupt + DCD TEMP_PANIC_IRQHandler ;TempSensor panic interrupt + DCD USB_PHY1_IRQHandler ;USBPHY (UTMI0), Interrupt + DCD USB_PHY2_IRQHandler ;USBPHY (UTMI1), Interrupt + DCD ADC1_IRQHandler ;ADC1 interrupt + DCD ADC2_IRQHandler ;ADC2 interrupt + DCD DCDC_IRQHandler ;DCDC interrupt + DCD Reserved86_IRQHandler ;Reserved interrupt + DCD Reserved87_IRQHandler ;Reserved interrupt + DCD GPIO1_INT0_IRQHandler ;Active HIGH Interrupt from INT0 from GPIO + DCD GPIO1_INT1_IRQHandler ;Active HIGH Interrupt from INT1 from GPIO + DCD GPIO1_INT2_IRQHandler ;Active HIGH Interrupt from INT2 from GPIO + DCD GPIO1_INT3_IRQHandler ;Active HIGH Interrupt from INT3 from GPIO + DCD GPIO1_INT4_IRQHandler ;Active HIGH Interrupt from INT4 from GPIO + DCD GPIO1_INT5_IRQHandler ;Active HIGH Interrupt from INT5 from GPIO + DCD GPIO1_INT6_IRQHandler ;Active HIGH Interrupt from INT6 from GPIO + DCD GPIO1_INT7_IRQHandler ;Active HIGH Interrupt from INT7 from GPIO + DCD GPIO1_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO1 signal 0 throughout 15 + DCD GPIO1_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO1 signal 16 throughout 31 + DCD GPIO2_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO2 signal 0 throughout 15 + DCD GPIO2_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO2 signal 16 throughout 31 + DCD GPIO3_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO3 signal 0 throughout 15 + DCD GPIO3_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO3 signal 16 throughout 31 + DCD GPIO4_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO4 signal 0 throughout 15 + DCD GPIO4_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO4 signal 16 throughout 31 + DCD GPIO5_Combined_0_15_IRQHandler ;Combined interrupt indication for GPIO5 signal 0 throughout 15 + DCD GPIO5_Combined_16_31_IRQHandler ;Combined interrupt indication for GPIO5 signal 16 throughout 31 + DCD FLEXIO1_IRQHandler ;FLEXIO1 interrupt + DCD FLEXIO2_IRQHandler ;FLEXIO2 interrupt + DCD WDOG1_IRQHandler ;WDOG1 interrupt + DCD RTWDOG_IRQHandler ;RTWDOG interrupt + DCD EWM_IRQHandler ;EWM interrupt + DCD CCM_1_IRQHandler ;CCM IRQ1 interrupt + DCD CCM_2_IRQHandler ;CCM IRQ2 interrupt + DCD GPC_IRQHandler ;GPC interrupt + DCD SRC_IRQHandler ;SRC interrupt + DCD Reserved115_IRQHandler ;Reserved interrupt + DCD GPT1_IRQHandler ;GPT1 interrupt + DCD GPT2_IRQHandler ;GPT2 interrupt + DCD PWM1_0_IRQHandler ;PWM1 capture 0, compare 0, or reload 0 interrupt + DCD PWM1_1_IRQHandler ;PWM1 capture 1, compare 1, or reload 0 interrupt + DCD PWM1_2_IRQHandler ;PWM1 capture 2, compare 2, or reload 0 interrupt + DCD PWM1_3_IRQHandler ;PWM1 capture 3, compare 3, or reload 0 interrupt + DCD PWM1_FAULT_IRQHandler ;PWM1 fault or reload error interrupt + DCD FLEXSPI2_IRQHandler ;FlexSPI2 interrupt + DCD FLEXSPI_IRQHandler ;FlexSPI0 interrupt + DCD SEMC_IRQHandler ;Reserved interrupt + DCD USDHC1_IRQHandler ;USDHC1 interrupt + DCD USDHC2_IRQHandler ;USDHC2 interrupt + DCD USB_OTG2_IRQHandler ;USBO2 USB OTG2 + DCD USB_OTG1_IRQHandler ;USBO2 USB OTG1 + DCD ENET_IRQHandler ;ENET interrupt + DCD ENET_1588_Timer_IRQHandler ;ENET_1588_Timer interrupt + DCD XBAR1_IRQ_0_1_IRQHandler ;XBAR1 interrupt + DCD XBAR1_IRQ_2_3_IRQHandler ;XBAR1 interrupt + DCD ADC_ETC_IRQ0_IRQHandler ;ADCETC IRQ0 interrupt + DCD ADC_ETC_IRQ1_IRQHandler ;ADCETC IRQ1 interrupt + DCD ADC_ETC_IRQ2_IRQHandler ;ADCETC IRQ2 interrupt + DCD ADC_ETC_ERROR_IRQ_IRQHandler ;ADCETC Error IRQ interrupt + DCD PIT_IRQHandler ;PIT interrupt + DCD ACMP1_IRQHandler ;ACMP interrupt + DCD ACMP2_IRQHandler ;ACMP interrupt + DCD ACMP3_IRQHandler ;ACMP interrupt + DCD ACMP4_IRQHandler ;ACMP interrupt + DCD Reserved143_IRQHandler ;Reserved interrupt + DCD Reserved144_IRQHandler ;Reserved interrupt + DCD ENC1_IRQHandler ;ENC1 interrupt + DCD ENC2_IRQHandler ;ENC2 interrupt + DCD ENC3_IRQHandler ;ENC3 interrupt + DCD ENC4_IRQHandler ;ENC4 interrupt + DCD TMR1_IRQHandler ;TMR1 interrupt + DCD TMR2_IRQHandler ;TMR2 interrupt + DCD TMR3_IRQHandler ;TMR3 interrupt + DCD TMR4_IRQHandler ;TMR4 interrupt + DCD PWM2_0_IRQHandler ;PWM2 capture 0, compare 0, or reload 0 interrupt + DCD PWM2_1_IRQHandler ;PWM2 capture 1, compare 1, or reload 0 interrupt + DCD PWM2_2_IRQHandler ;PWM2 capture 2, compare 2, or reload 0 interrupt + DCD PWM2_3_IRQHandler ;PWM2 capture 3, compare 3, or reload 0 interrupt + DCD PWM2_FAULT_IRQHandler ;PWM2 fault or reload error interrupt + DCD PWM3_0_IRQHandler ;PWM3 capture 0, compare 0, or reload 0 interrupt + DCD PWM3_1_IRQHandler ;PWM3 capture 1, compare 1, or reload 0 interrupt + DCD PWM3_2_IRQHandler ;PWM3 capture 2, compare 2, or reload 0 interrupt + DCD PWM3_3_IRQHandler ;PWM3 capture 3, compare 3, or reload 0 interrupt + DCD PWM3_FAULT_IRQHandler ;PWM3 fault or reload error interrupt + DCD PWM4_0_IRQHandler ;PWM4 capture 0, compare 0, or reload 0 interrupt + DCD PWM4_1_IRQHandler ;PWM4 capture 1, compare 1, or reload 0 interrupt + DCD PWM4_2_IRQHandler ;PWM4 capture 2, compare 2, or reload 0 interrupt + DCD PWM4_3_IRQHandler ;PWM4 capture 3, compare 3, or reload 0 interrupt + DCD PWM4_FAULT_IRQHandler ;PWM4 fault or reload error interrupt + DCD ENET2_IRQHandler ;ENET2 interrupt + DCD ENET2_1588_Timer_IRQHandler ;ENET2_1588_Timer interrupt + DCD CAN3_IRQHandler ;CAN3 interrupt + DCD Reserved171_IRQHandler ;Reserved interrupt + DCD FLEXIO3_IRQHandler ;FLEXIO3 interrupt + DCD GPIO6_7_8_9_IRQHandler ;GPIO6, GPIO7, GPIO8, GPIO9 interrupt + DCD DefaultISR ;174 + DCD DefaultISR ;175 + DCD DefaultISR ;176 + DCD DefaultISR ;177 + DCD DefaultISR ;178 + DCD DefaultISR ;179 + DCD DefaultISR ;180 + DCD DefaultISR ;181 + DCD DefaultISR ;182 + DCD DefaultISR ;183 + DCD DefaultISR ;184 + DCD DefaultISR ;185 + DCD DefaultISR ;186 + DCD DefaultISR ;187 + DCD DefaultISR ;188 + DCD DefaultISR ;189 + DCD DefaultISR ;190 + DCD DefaultISR ;191 + DCD DefaultISR ;192 + DCD DefaultISR ;193 + DCD DefaultISR ;194 + DCD DefaultISR ;195 + DCD DefaultISR ;196 + DCD DefaultISR ;197 + DCD DefaultISR ;198 + DCD DefaultISR ;199 + DCD DefaultISR ;200 + DCD DefaultISR ;201 + DCD DefaultISR ;202 + DCD DefaultISR ;203 + DCD DefaultISR ;204 + DCD DefaultISR ;205 + DCD DefaultISR ;206 + DCD DefaultISR ;207 + DCD DefaultISR ;208 + DCD DefaultISR ;209 + DCD DefaultISR ;210 + DCD DefaultISR ;211 + DCD DefaultISR ;212 + DCD DefaultISR ;213 + DCD DefaultISR ;214 + DCD DefaultISR ;215 + DCD DefaultISR ;216 + DCD DefaultISR ;217 + DCD DefaultISR ;218 + DCD DefaultISR ;219 + DCD DefaultISR ;220 + DCD DefaultISR ;221 + DCD DefaultISR ;222 + DCD DefaultISR ;223 + DCD DefaultISR ;224 + DCD DefaultISR ;225 + DCD DefaultISR ;226 + DCD DefaultISR ;227 + DCD DefaultISR ;228 + DCD DefaultISR ;229 + DCD DefaultISR ;230 + DCD DefaultISR ;231 + DCD DefaultISR ;232 + DCD DefaultISR ;233 + DCD DefaultISR ;234 + DCD DefaultISR ;235 + DCD DefaultISR ;236 + DCD DefaultISR ;237 + DCD DefaultISR ;238 + DCD DefaultISR ;239 + DCD DefaultISR ;240 + DCD DefaultISR ;241 + DCD DefaultISR ;242 + DCD DefaultISR ;243 + DCD DefaultISR ;244 + DCD DefaultISR ;245 + DCD DefaultISR ;246 + DCD DefaultISR ;247 + DCD DefaultISR ;248 + DCD DefaultISR ;249 + DCD DefaultISR ;250 + DCD DefaultISR ;251 + DCD DefaultISR ;252 + DCD DefaultISR ;253 + DCD DefaultISR ;254 + DCD 0xFFFFFFFF ; Reserved for user TRIM value +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R2, [R1] + MSR MSP, R2 + LDR R0, =SystemInit + BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_DMA16_IRQHandler + PUBWEAK DMA0_DMA16_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_DMA16_IRQHandler + LDR R0, =DMA0_DMA16_DriverIRQHandler + BX R0 + + PUBWEAK DMA1_DMA17_IRQHandler + PUBWEAK DMA1_DMA17_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA1_DMA17_IRQHandler + LDR R0, =DMA1_DMA17_DriverIRQHandler + BX R0 + + PUBWEAK DMA2_DMA18_IRQHandler + PUBWEAK DMA2_DMA18_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA2_DMA18_IRQHandler + LDR R0, =DMA2_DMA18_DriverIRQHandler + BX R0 + + PUBWEAK DMA3_DMA19_IRQHandler + PUBWEAK DMA3_DMA19_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA3_DMA19_IRQHandler + LDR R0, =DMA3_DMA19_DriverIRQHandler + BX R0 + + PUBWEAK DMA4_DMA20_IRQHandler + PUBWEAK DMA4_DMA20_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA4_DMA20_IRQHandler + LDR R0, =DMA4_DMA20_DriverIRQHandler + BX R0 + + PUBWEAK DMA5_DMA21_IRQHandler + PUBWEAK DMA5_DMA21_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA5_DMA21_IRQHandler + LDR R0, =DMA5_DMA21_DriverIRQHandler + BX R0 + + PUBWEAK DMA6_DMA22_IRQHandler + PUBWEAK DMA6_DMA22_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA6_DMA22_IRQHandler + LDR R0, =DMA6_DMA22_DriverIRQHandler + BX R0 + + PUBWEAK DMA7_DMA23_IRQHandler + PUBWEAK DMA7_DMA23_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA7_DMA23_IRQHandler + LDR R0, =DMA7_DMA23_DriverIRQHandler + BX R0 + + PUBWEAK DMA8_DMA24_IRQHandler + PUBWEAK DMA8_DMA24_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA8_DMA24_IRQHandler + LDR R0, =DMA8_DMA24_DriverIRQHandler + BX R0 + + PUBWEAK DMA9_DMA25_IRQHandler + PUBWEAK DMA9_DMA25_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA9_DMA25_IRQHandler + LDR R0, =DMA9_DMA25_DriverIRQHandler + BX R0 + + PUBWEAK DMA10_DMA26_IRQHandler + PUBWEAK DMA10_DMA26_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA10_DMA26_IRQHandler + LDR R0, =DMA10_DMA26_DriverIRQHandler + BX R0 + + PUBWEAK DMA11_DMA27_IRQHandler + PUBWEAK DMA11_DMA27_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA11_DMA27_IRQHandler + LDR R0, =DMA11_DMA27_DriverIRQHandler + BX R0 + + PUBWEAK DMA12_DMA28_IRQHandler + PUBWEAK DMA12_DMA28_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA12_DMA28_IRQHandler + LDR R0, =DMA12_DMA28_DriverIRQHandler + BX R0 + + PUBWEAK DMA13_DMA29_IRQHandler + PUBWEAK DMA13_DMA29_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA13_DMA29_IRQHandler + LDR R0, =DMA13_DMA29_DriverIRQHandler + BX R0 + + PUBWEAK DMA14_DMA30_IRQHandler + PUBWEAK DMA14_DMA30_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA14_DMA30_IRQHandler + LDR R0, =DMA14_DMA30_DriverIRQHandler + BX R0 + + PUBWEAK DMA15_DMA31_IRQHandler + PUBWEAK DMA15_DMA31_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA15_DMA31_IRQHandler + LDR R0, =DMA15_DMA31_DriverIRQHandler + BX R0 + + PUBWEAK DMA_ERROR_IRQHandler + PUBWEAK DMA_ERROR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA_ERROR_IRQHandler + LDR R0, =DMA_ERROR_DriverIRQHandler + BX R0 + + PUBWEAK CTI0_ERROR_IRQHandler + PUBWEAK CTI1_ERROR_IRQHandler + PUBWEAK CORE_IRQHandler + PUBWEAK LPUART1_IRQHandler + PUBWEAK LPUART1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART1_IRQHandler + LDR R0, =LPUART1_DriverIRQHandler + BX R0 + + PUBWEAK LPUART2_IRQHandler + PUBWEAK LPUART2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART2_IRQHandler + LDR R0, =LPUART2_DriverIRQHandler + BX R0 + + PUBWEAK LPUART3_IRQHandler + PUBWEAK LPUART3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART3_IRQHandler + LDR R0, =LPUART3_DriverIRQHandler + BX R0 + + PUBWEAK LPUART4_IRQHandler + PUBWEAK LPUART4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART4_IRQHandler + LDR R0, =LPUART4_DriverIRQHandler + BX R0 + + PUBWEAK LPUART5_IRQHandler + PUBWEAK LPUART5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART5_IRQHandler + LDR R0, =LPUART5_DriverIRQHandler + BX R0 + + PUBWEAK LPUART6_IRQHandler + PUBWEAK LPUART6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART6_IRQHandler + LDR R0, =LPUART6_DriverIRQHandler + BX R0 + + PUBWEAK LPUART7_IRQHandler + PUBWEAK LPUART7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART7_IRQHandler + LDR R0, =LPUART7_DriverIRQHandler + BX R0 + + PUBWEAK LPUART8_IRQHandler + PUBWEAK LPUART8_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART8_IRQHandler + LDR R0, =LPUART8_DriverIRQHandler + BX R0 + + PUBWEAK LPI2C1_IRQHandler + PUBWEAK LPI2C1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPI2C1_IRQHandler + LDR R0, =LPI2C1_DriverIRQHandler + BX R0 + + PUBWEAK LPI2C2_IRQHandler + PUBWEAK LPI2C2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPI2C2_IRQHandler + LDR R0, =LPI2C2_DriverIRQHandler + BX R0 + + PUBWEAK LPI2C3_IRQHandler + PUBWEAK LPI2C3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPI2C3_IRQHandler + LDR R0, =LPI2C3_DriverIRQHandler + BX R0 + + PUBWEAK LPI2C4_IRQHandler + PUBWEAK LPI2C4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPI2C4_IRQHandler + LDR R0, =LPI2C4_DriverIRQHandler + BX R0 + + PUBWEAK LPSPI1_IRQHandler + PUBWEAK LPSPI1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPSPI1_IRQHandler + LDR R0, =LPSPI1_DriverIRQHandler + BX R0 + + PUBWEAK LPSPI2_IRQHandler + PUBWEAK LPSPI2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPSPI2_IRQHandler + LDR R0, =LPSPI2_DriverIRQHandler + BX R0 + + PUBWEAK LPSPI3_IRQHandler + PUBWEAK LPSPI3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPSPI3_IRQHandler + LDR R0, =LPSPI3_DriverIRQHandler + BX R0 + + PUBWEAK LPSPI4_IRQHandler + PUBWEAK LPSPI4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPSPI4_IRQHandler + LDR R0, =LPSPI4_DriverIRQHandler + BX R0 + + PUBWEAK CAN1_IRQHandler + PUBWEAK CAN1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN1_IRQHandler + LDR R0, =CAN1_DriverIRQHandler + BX R0 + + PUBWEAK CAN2_IRQHandler + PUBWEAK CAN2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN2_IRQHandler + LDR R0, =CAN2_DriverIRQHandler + BX R0 + + PUBWEAK FLEXRAM_IRQHandler + PUBWEAK KPP_IRQHandler + PUBWEAK TSC_DIG_IRQHandler + PUBWEAK GPR_IRQ_IRQHandler + PUBWEAK Reserved58_IRQHandler + PUBWEAK Reserved59_IRQHandler + PUBWEAK Reserved60_IRQHandler + PUBWEAK WDOG2_IRQHandler + PUBWEAK SNVS_HP_WRAPPER_IRQHandler + PUBWEAK SNVS_HP_WRAPPER_TZ_IRQHandler + PUBWEAK SNVS_LP_WRAPPER_IRQHandler + PUBWEAK CSU_IRQHandler + PUBWEAK DCP_IRQHandler + PUBWEAK DCP_VMI_IRQHandler + PUBWEAK Reserved68_IRQHandler + PUBWEAK TRNG_IRQHandler + PUBWEAK SJC_IRQHandler + PUBWEAK BEE_IRQHandler + PUBWEAK SAI1_IRQHandler + PUBWEAK SAI1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SAI1_IRQHandler + LDR R0, =SAI1_DriverIRQHandler + BX R0 + + PUBWEAK SAI2_IRQHandler + PUBWEAK SAI2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SAI2_IRQHandler + LDR R0, =SAI2_DriverIRQHandler + BX R0 + + PUBWEAK SAI3_RX_IRQHandler + PUBWEAK SAI3_RX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SAI3_RX_IRQHandler + LDR R0, =SAI3_RX_DriverIRQHandler + BX R0 + + PUBWEAK SAI3_TX_IRQHandler + PUBWEAK SAI3_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SAI3_TX_IRQHandler + LDR R0, =SAI3_TX_DriverIRQHandler + BX R0 + + PUBWEAK SPDIF_IRQHandler + PUBWEAK SPDIF_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPDIF_IRQHandler + LDR R0, =SPDIF_DriverIRQHandler + BX R0 + + PUBWEAK PMU_EVENT_IRQHandler + PUBWEAK Reserved78_IRQHandler + PUBWEAK TEMP_LOW_HIGH_IRQHandler + PUBWEAK TEMP_PANIC_IRQHandler + PUBWEAK USB_PHY1_IRQHandler + PUBWEAK USB_PHY2_IRQHandler + PUBWEAK ADC1_IRQHandler + PUBWEAK ADC2_IRQHandler + PUBWEAK DCDC_IRQHandler + PUBWEAK Reserved86_IRQHandler + PUBWEAK Reserved87_IRQHandler + PUBWEAK GPIO1_INT0_IRQHandler + PUBWEAK GPIO1_INT1_IRQHandler + PUBWEAK GPIO1_INT2_IRQHandler + PUBWEAK GPIO1_INT3_IRQHandler + PUBWEAK GPIO1_INT4_IRQHandler + PUBWEAK GPIO1_INT5_IRQHandler + PUBWEAK GPIO1_INT6_IRQHandler + PUBWEAK GPIO1_INT7_IRQHandler + PUBWEAK GPIO1_Combined_0_15_IRQHandler + PUBWEAK GPIO1_Combined_16_31_IRQHandler + PUBWEAK GPIO2_Combined_0_15_IRQHandler + PUBWEAK GPIO2_Combined_16_31_IRQHandler + PUBWEAK GPIO3_Combined_0_15_IRQHandler + PUBWEAK GPIO3_Combined_16_31_IRQHandler + PUBWEAK GPIO4_Combined_0_15_IRQHandler + PUBWEAK GPIO4_Combined_16_31_IRQHandler + PUBWEAK GPIO5_Combined_0_15_IRQHandler + PUBWEAK GPIO5_Combined_16_31_IRQHandler + PUBWEAK FLEXIO1_IRQHandler + PUBWEAK FLEXIO1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXIO1_IRQHandler + LDR R0, =FLEXIO1_DriverIRQHandler + BX R0 + + PUBWEAK FLEXIO2_IRQHandler + PUBWEAK FLEXIO2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXIO2_IRQHandler + LDR R0, =FLEXIO2_DriverIRQHandler + BX R0 + + PUBWEAK WDOG1_IRQHandler + PUBWEAK RTWDOG_IRQHandler + PUBWEAK EWM_IRQHandler + PUBWEAK CCM_1_IRQHandler + PUBWEAK CCM_2_IRQHandler + PUBWEAK GPC_IRQHandler + PUBWEAK SRC_IRQHandler + PUBWEAK Reserved115_IRQHandler + PUBWEAK GPT1_IRQHandler + PUBWEAK GPT2_IRQHandler + PUBWEAK PWM1_0_IRQHandler + PUBWEAK PWM1_1_IRQHandler + PUBWEAK PWM1_2_IRQHandler + PUBWEAK PWM1_3_IRQHandler + PUBWEAK PWM1_FAULT_IRQHandler + PUBWEAK FLEXSPI2_IRQHandler + PUBWEAK FLEXSPI2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXSPI2_IRQHandler + LDR R0, =FLEXSPI2_DriverIRQHandler + BX R0 + + PUBWEAK FLEXSPI_IRQHandler + PUBWEAK FLEXSPI_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXSPI_IRQHandler + LDR R0, =FLEXSPI_DriverIRQHandler + BX R0 + + PUBWEAK SEMC_IRQHandler + PUBWEAK USDHC1_IRQHandler + PUBWEAK USDHC1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USDHC1_IRQHandler + LDR R0, =USDHC1_DriverIRQHandler + BX R0 + + PUBWEAK USDHC2_IRQHandler + PUBWEAK USDHC2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USDHC2_IRQHandler + LDR R0, =USDHC2_DriverIRQHandler + BX R0 + + PUBWEAK USB_OTG2_IRQHandler + PUBWEAK USB_OTG1_IRQHandler + PUBWEAK ENET_IRQHandler + PUBWEAK ENET_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ENET_IRQHandler + LDR R0, =ENET_DriverIRQHandler + BX R0 + + PUBWEAK ENET_1588_Timer_IRQHandler + PUBWEAK ENET_1588_Timer_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ENET_1588_Timer_IRQHandler + LDR R0, =ENET_1588_Timer_DriverIRQHandler + BX R0 + + PUBWEAK XBAR1_IRQ_0_1_IRQHandler + PUBWEAK XBAR1_IRQ_2_3_IRQHandler + PUBWEAK ADC_ETC_IRQ0_IRQHandler + PUBWEAK ADC_ETC_IRQ1_IRQHandler + PUBWEAK ADC_ETC_IRQ2_IRQHandler + PUBWEAK ADC_ETC_ERROR_IRQ_IRQHandler + PUBWEAK PIT_IRQHandler + PUBWEAK ACMP1_IRQHandler + PUBWEAK ACMP2_IRQHandler + PUBWEAK ACMP3_IRQHandler + PUBWEAK ACMP4_IRQHandler + PUBWEAK Reserved143_IRQHandler + PUBWEAK Reserved144_IRQHandler + PUBWEAK ENC1_IRQHandler + PUBWEAK ENC2_IRQHandler + PUBWEAK ENC3_IRQHandler + PUBWEAK ENC4_IRQHandler + PUBWEAK TMR1_IRQHandler + PUBWEAK TMR2_IRQHandler + PUBWEAK TMR3_IRQHandler + PUBWEAK TMR4_IRQHandler + PUBWEAK PWM2_0_IRQHandler + PUBWEAK PWM2_1_IRQHandler + PUBWEAK PWM2_2_IRQHandler + PUBWEAK PWM2_3_IRQHandler + PUBWEAK PWM2_FAULT_IRQHandler + PUBWEAK PWM3_0_IRQHandler + PUBWEAK PWM3_1_IRQHandler + PUBWEAK PWM3_2_IRQHandler + PUBWEAK PWM3_3_IRQHandler + PUBWEAK PWM3_FAULT_IRQHandler + PUBWEAK PWM4_0_IRQHandler + PUBWEAK PWM4_1_IRQHandler + PUBWEAK PWM4_2_IRQHandler + PUBWEAK PWM4_3_IRQHandler + PUBWEAK PWM4_FAULT_IRQHandler + PUBWEAK ENET2_IRQHandler + PUBWEAK ENET2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ENET2_IRQHandler + LDR R0, =ENET2_DriverIRQHandler + BX R0 + + PUBWEAK ENET2_1588_Timer_IRQHandler + PUBWEAK ENET2_1588_Timer_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ENET2_1588_Timer_IRQHandler + LDR R0, =ENET2_1588_Timer_DriverIRQHandler + BX R0 + + PUBWEAK CAN3_IRQHandler + PUBWEAK CAN3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN3_IRQHandler + LDR R0, =CAN3_DriverIRQHandler + BX R0 + + PUBWEAK Reserved171_IRQHandler + PUBWEAK FLEXIO3_IRQHandler + PUBWEAK FLEXIO3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXIO3_IRQHandler + LDR R0, =FLEXIO3_DriverIRQHandler + BX R0 + + PUBWEAK GPIO6_7_8_9_IRQHandler + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(1) +DMA0_DMA16_DriverIRQHandler +DMA1_DMA17_DriverIRQHandler +DMA2_DMA18_DriverIRQHandler +DMA3_DMA19_DriverIRQHandler +DMA4_DMA20_DriverIRQHandler +DMA5_DMA21_DriverIRQHandler +DMA6_DMA22_DriverIRQHandler +DMA7_DMA23_DriverIRQHandler +DMA8_DMA24_DriverIRQHandler +DMA9_DMA25_DriverIRQHandler +DMA10_DMA26_DriverIRQHandler +DMA11_DMA27_DriverIRQHandler +DMA12_DMA28_DriverIRQHandler +DMA13_DMA29_DriverIRQHandler +DMA14_DMA30_DriverIRQHandler +DMA15_DMA31_DriverIRQHandler +DMA_ERROR_DriverIRQHandler +CTI0_ERROR_IRQHandler +CTI1_ERROR_IRQHandler +CORE_IRQHandler +LPUART1_DriverIRQHandler +LPUART2_DriverIRQHandler +LPUART3_DriverIRQHandler +LPUART4_DriverIRQHandler +LPUART5_DriverIRQHandler +LPUART6_DriverIRQHandler +LPUART7_DriverIRQHandler +LPUART8_DriverIRQHandler +LPI2C1_DriverIRQHandler +LPI2C2_DriverIRQHandler +LPI2C3_DriverIRQHandler +LPI2C4_DriverIRQHandler +LPSPI1_DriverIRQHandler +LPSPI2_DriverIRQHandler +LPSPI3_DriverIRQHandler +LPSPI4_DriverIRQHandler +CAN1_DriverIRQHandler +CAN2_DriverIRQHandler +FLEXRAM_IRQHandler +KPP_IRQHandler +TSC_DIG_IRQHandler +GPR_IRQ_IRQHandler +Reserved58_IRQHandler +Reserved59_IRQHandler +Reserved60_IRQHandler +WDOG2_IRQHandler +SNVS_HP_WRAPPER_IRQHandler +SNVS_HP_WRAPPER_TZ_IRQHandler +SNVS_LP_WRAPPER_IRQHandler +CSU_IRQHandler +DCP_IRQHandler +DCP_VMI_IRQHandler +Reserved68_IRQHandler +TRNG_IRQHandler +SJC_IRQHandler +BEE_IRQHandler +SAI1_DriverIRQHandler +SAI2_DriverIRQHandler +SAI3_RX_DriverIRQHandler +SAI3_TX_DriverIRQHandler +SPDIF_DriverIRQHandler +PMU_EVENT_IRQHandler +Reserved78_IRQHandler +TEMP_LOW_HIGH_IRQHandler +TEMP_PANIC_IRQHandler +USB_PHY1_IRQHandler +USB_PHY2_IRQHandler +ADC1_IRQHandler +ADC2_IRQHandler +DCDC_IRQHandler +Reserved86_IRQHandler +Reserved87_IRQHandler +GPIO1_INT0_IRQHandler +GPIO1_INT1_IRQHandler +GPIO1_INT2_IRQHandler +GPIO1_INT3_IRQHandler +GPIO1_INT4_IRQHandler +GPIO1_INT5_IRQHandler +GPIO1_INT6_IRQHandler +GPIO1_INT7_IRQHandler +GPIO1_Combined_0_15_IRQHandler +GPIO1_Combined_16_31_IRQHandler +GPIO2_Combined_0_15_IRQHandler +GPIO2_Combined_16_31_IRQHandler +GPIO3_Combined_0_15_IRQHandler +GPIO3_Combined_16_31_IRQHandler +GPIO4_Combined_0_15_IRQHandler +GPIO4_Combined_16_31_IRQHandler +GPIO5_Combined_0_15_IRQHandler +GPIO5_Combined_16_31_IRQHandler +FLEXIO1_DriverIRQHandler +FLEXIO2_DriverIRQHandler +WDOG1_IRQHandler +RTWDOG_IRQHandler +EWM_IRQHandler +CCM_1_IRQHandler +CCM_2_IRQHandler +GPC_IRQHandler +SRC_IRQHandler +Reserved115_IRQHandler +GPT1_IRQHandler +GPT2_IRQHandler +PWM1_0_IRQHandler +PWM1_1_IRQHandler +PWM1_2_IRQHandler +PWM1_3_IRQHandler +PWM1_FAULT_IRQHandler +FLEXSPI2_DriverIRQHandler +FLEXSPI_DriverIRQHandler +SEMC_IRQHandler +USDHC1_DriverIRQHandler +USDHC2_DriverIRQHandler +USB_OTG2_IRQHandler +USB_OTG1_IRQHandler +ENET_DriverIRQHandler +ENET_1588_Timer_DriverIRQHandler +XBAR1_IRQ_0_1_IRQHandler +XBAR1_IRQ_2_3_IRQHandler +ADC_ETC_IRQ0_IRQHandler +ADC_ETC_IRQ1_IRQHandler +ADC_ETC_IRQ2_IRQHandler +ADC_ETC_ERROR_IRQ_IRQHandler +PIT_IRQHandler +ACMP1_IRQHandler +ACMP2_IRQHandler +ACMP3_IRQHandler +ACMP4_IRQHandler +Reserved143_IRQHandler +Reserved144_IRQHandler +ENC1_IRQHandler +ENC2_IRQHandler +ENC3_IRQHandler +ENC4_IRQHandler +TMR1_IRQHandler +TMR2_IRQHandler +TMR3_IRQHandler +TMR4_IRQHandler +PWM2_0_IRQHandler +PWM2_1_IRQHandler +PWM2_2_IRQHandler +PWM2_3_IRQHandler +PWM2_FAULT_IRQHandler +PWM3_0_IRQHandler +PWM3_1_IRQHandler +PWM3_2_IRQHandler +PWM3_3_IRQHandler +PWM3_FAULT_IRQHandler +PWM4_0_IRQHandler +PWM4_1_IRQHandler +PWM4_2_IRQHandler +PWM4_3_IRQHandler +PWM4_FAULT_IRQHandler +ENET2_DriverIRQHandler +ENET2_1588_Timer_DriverIRQHandler +CAN3_DriverIRQHandler +Reserved171_IRQHandler +FLEXIO3_DriverIRQHandler +GPIO6_7_8_9_IRQHandler +DefaultISR + B DefaultISR + + END diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/mcuxpresso/startup_mimxrt1061.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/mcuxpresso/startup_mimxrt1061.c new file mode 100644 index 0000000000..e56cbeff7c --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/mcuxpresso/startup_mimxrt1061.c @@ -0,0 +1,1411 @@ +//***************************************************************************** +// MIMXRT1061 startup code for use with MCUXpresso IDE +// +// Version : 240119 +//***************************************************************************** +// +// Copyright 2016-2019 NXP +// All rights reserved. +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC push_options +#pragma GCC optimize ("Og") +#endif // (DEBUG) + +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { + extern void __libc_init_array(void); +} +#endif +#endif + +#define WEAK __attribute__ ((weak)) +#define WEAK_AV __attribute__ ((weak, section(".after_vectors"))) +#define ALIAS(f) __attribute__ ((weak, alias (#f))) + +//***************************************************************************** +#if defined (__cplusplus) +extern "C" { +#endif + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +#if defined (__USE_CMSIS) +extern void SystemInit(void); +#endif // (__USE_CMSIS) + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** + void ResetISR(void); +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void IntDefaultHandler(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void DMA0_DMA16_IRQHandler(void); +WEAK void DMA1_DMA17_IRQHandler(void); +WEAK void DMA2_DMA18_IRQHandler(void); +WEAK void DMA3_DMA19_IRQHandler(void); +WEAK void DMA4_DMA20_IRQHandler(void); +WEAK void DMA5_DMA21_IRQHandler(void); +WEAK void DMA6_DMA22_IRQHandler(void); +WEAK void DMA7_DMA23_IRQHandler(void); +WEAK void DMA8_DMA24_IRQHandler(void); +WEAK void DMA9_DMA25_IRQHandler(void); +WEAK void DMA10_DMA26_IRQHandler(void); +WEAK void DMA11_DMA27_IRQHandler(void); +WEAK void DMA12_DMA28_IRQHandler(void); +WEAK void DMA13_DMA29_IRQHandler(void); +WEAK void DMA14_DMA30_IRQHandler(void); +WEAK void DMA15_DMA31_IRQHandler(void); +WEAK void DMA_ERROR_IRQHandler(void); +WEAK void CTI0_ERROR_IRQHandler(void); +WEAK void CTI1_ERROR_IRQHandler(void); +WEAK void CORE_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void LPUART5_IRQHandler(void); +WEAK void LPUART6_IRQHandler(void); +WEAK void LPUART7_IRQHandler(void); +WEAK void LPUART8_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void LPI2C4_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void LPSPI2_IRQHandler(void); +WEAK void LPSPI3_IRQHandler(void); +WEAK void LPSPI4_IRQHandler(void); +WEAK void CAN1_IRQHandler(void); +WEAK void CAN2_IRQHandler(void); +WEAK void FLEXRAM_IRQHandler(void); +WEAK void KPP_IRQHandler(void); +WEAK void TSC_DIG_IRQHandler(void); +WEAK void GPR_IRQ_IRQHandler(void); +WEAK void Reserved58_IRQHandler(void); +WEAK void Reserved59_IRQHandler(void); +WEAK void Reserved60_IRQHandler(void); +WEAK void WDOG2_IRQHandler(void); +WEAK void SNVS_HP_WRAPPER_IRQHandler(void); +WEAK void SNVS_HP_WRAPPER_TZ_IRQHandler(void); +WEAK void SNVS_LP_WRAPPER_IRQHandler(void); +WEAK void CSU_IRQHandler(void); +WEAK void DCP_IRQHandler(void); +WEAK void DCP_VMI_IRQHandler(void); +WEAK void Reserved68_IRQHandler(void); +WEAK void TRNG_IRQHandler(void); +WEAK void SJC_IRQHandler(void); +WEAK void BEE_IRQHandler(void); +WEAK void SAI1_IRQHandler(void); +WEAK void SAI2_IRQHandler(void); +WEAK void SAI3_RX_IRQHandler(void); +WEAK void SAI3_TX_IRQHandler(void); +WEAK void SPDIF_IRQHandler(void); +WEAK void PMU_EVENT_IRQHandler(void); +WEAK void Reserved78_IRQHandler(void); +WEAK void TEMP_LOW_HIGH_IRQHandler(void); +WEAK void TEMP_PANIC_IRQHandler(void); +WEAK void USB_PHY1_IRQHandler(void); +WEAK void USB_PHY2_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void ADC2_IRQHandler(void); +WEAK void DCDC_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void Reserved87_IRQHandler(void); +WEAK void GPIO1_INT0_IRQHandler(void); +WEAK void GPIO1_INT1_IRQHandler(void); +WEAK void GPIO1_INT2_IRQHandler(void); +WEAK void GPIO1_INT3_IRQHandler(void); +WEAK void GPIO1_INT4_IRQHandler(void); +WEAK void GPIO1_INT5_IRQHandler(void); +WEAK void GPIO1_INT6_IRQHandler(void); +WEAK void GPIO1_INT7_IRQHandler(void); +WEAK void GPIO1_Combined_0_15_IRQHandler(void); +WEAK void GPIO1_Combined_16_31_IRQHandler(void); +WEAK void GPIO2_Combined_0_15_IRQHandler(void); +WEAK void GPIO2_Combined_16_31_IRQHandler(void); +WEAK void GPIO3_Combined_0_15_IRQHandler(void); +WEAK void GPIO3_Combined_16_31_IRQHandler(void); +WEAK void GPIO4_Combined_0_15_IRQHandler(void); +WEAK void GPIO4_Combined_16_31_IRQHandler(void); +WEAK void GPIO5_Combined_0_15_IRQHandler(void); +WEAK void GPIO5_Combined_16_31_IRQHandler(void); +WEAK void FLEXIO1_IRQHandler(void); +WEAK void FLEXIO2_IRQHandler(void); +WEAK void WDOG1_IRQHandler(void); +WEAK void RTWDOG_IRQHandler(void); +WEAK void EWM_IRQHandler(void); +WEAK void CCM_1_IRQHandler(void); +WEAK void CCM_2_IRQHandler(void); +WEAK void GPC_IRQHandler(void); +WEAK void SRC_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void GPT1_IRQHandler(void); +WEAK void GPT2_IRQHandler(void); +WEAK void PWM1_0_IRQHandler(void); +WEAK void PWM1_1_IRQHandler(void); +WEAK void PWM1_2_IRQHandler(void); +WEAK void PWM1_3_IRQHandler(void); +WEAK void PWM1_FAULT_IRQHandler(void); +WEAK void FLEXSPI2_IRQHandler(void); +WEAK void FLEXSPI_IRQHandler(void); +WEAK void SEMC_IRQHandler(void); +WEAK void USDHC1_IRQHandler(void); +WEAK void USDHC2_IRQHandler(void); +WEAK void USB_OTG2_IRQHandler(void); +WEAK void USB_OTG1_IRQHandler(void); +WEAK void ENET_IRQHandler(void); +WEAK void ENET_1588_Timer_IRQHandler(void); +WEAK void XBAR1_IRQ_0_1_IRQHandler(void); +WEAK void XBAR1_IRQ_2_3_IRQHandler(void); +WEAK void ADC_ETC_IRQ0_IRQHandler(void); +WEAK void ADC_ETC_IRQ1_IRQHandler(void); +WEAK void ADC_ETC_IRQ2_IRQHandler(void); +WEAK void ADC_ETC_ERROR_IRQ_IRQHandler(void); +WEAK void PIT_IRQHandler(void); +WEAK void ACMP1_IRQHandler(void); +WEAK void ACMP2_IRQHandler(void); +WEAK void ACMP3_IRQHandler(void); +WEAK void ACMP4_IRQHandler(void); +WEAK void Reserved143_IRQHandler(void); +WEAK void Reserved144_IRQHandler(void); +WEAK void ENC1_IRQHandler(void); +WEAK void ENC2_IRQHandler(void); +WEAK void ENC3_IRQHandler(void); +WEAK void ENC4_IRQHandler(void); +WEAK void TMR1_IRQHandler(void); +WEAK void TMR2_IRQHandler(void); +WEAK void TMR3_IRQHandler(void); +WEAK void TMR4_IRQHandler(void); +WEAK void PWM2_0_IRQHandler(void); +WEAK void PWM2_1_IRQHandler(void); +WEAK void PWM2_2_IRQHandler(void); +WEAK void PWM2_3_IRQHandler(void); +WEAK void PWM2_FAULT_IRQHandler(void); +WEAK void PWM3_0_IRQHandler(void); +WEAK void PWM3_1_IRQHandler(void); +WEAK void PWM3_2_IRQHandler(void); +WEAK void PWM3_3_IRQHandler(void); +WEAK void PWM3_FAULT_IRQHandler(void); +WEAK void PWM4_0_IRQHandler(void); +WEAK void PWM4_1_IRQHandler(void); +WEAK void PWM4_2_IRQHandler(void); +WEAK void PWM4_3_IRQHandler(void); +WEAK void PWM4_FAULT_IRQHandler(void); +WEAK void ENET2_IRQHandler(void); +WEAK void ENET2_1588_Timer_IRQHandler(void); +WEAK void CAN3_IRQHandler(void); +WEAK void Reserved171_IRQHandler(void); +WEAK void FLEXIO3_IRQHandler(void); +WEAK void GPIO6_7_8_9_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the IntDefaultHandler, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void DMA0_DMA16_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA1_DMA17_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA2_DMA18_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA3_DMA19_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA4_DMA20_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA5_DMA21_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA6_DMA22_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA7_DMA23_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA8_DMA24_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA9_DMA25_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA10_DMA26_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA11_DMA27_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA12_DMA28_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA13_DMA29_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA14_DMA30_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA15_DMA31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTI0_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTI1_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CORE_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART8_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPI2C1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPI2C2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPI2C3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPI2C4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPSPI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPSPI2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPSPI3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPSPI4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CAN1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CAN2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXRAM_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void KPP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TSC_DIG_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPR_IRQ_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved58_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved59_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved60_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WDOG2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SNVS_HP_WRAPPER_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SNVS_HP_WRAPPER_TZ_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SNVS_LP_WRAPPER_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CSU_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DCP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DCP_VMI_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved68_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TRNG_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SJC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void BEE_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI3_RX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI3_TX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SPDIF_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PMU_EVENT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved78_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TEMP_LOW_HIGH_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TEMP_PANIC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB_PHY1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB_PHY2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DCDC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved86_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved87_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO2_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO2_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO3_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO3_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO4_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO4_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO5_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO5_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXIO1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXIO2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WDOG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void RTWDOG_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EWM_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CCM_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CCM_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SRC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved115_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXSPI2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXSPI_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEMC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USDHC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USDHC2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB_OTG2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB_OTG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENET_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENET_1588_Timer_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void XBAR1_IRQ_0_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void XBAR1_IRQ_2_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_ETC_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_ETC_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_ETC_IRQ2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_ETC_ERROR_IRQ_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved143_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved144_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENC2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENC3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENC4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TMR1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TMR2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TMR3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TMR4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENET2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENET2_1588_Timer_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CAN3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved171_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXIO3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO6_7_8_9_DriverIRQHandler(void) ALIAS(IntDefaultHandler); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined (__REDLIB__) +extern void __main(void); +#endif +extern int main(void); + +//***************************************************************************** +// External declaration for the pointer to the stack top from the Linker Script +//***************************************************************************** +extern void _vStackTop(void); +//***************************************************************************** +#if defined (__cplusplus) +} // extern "C" +#endif +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +extern void (* const g_pfnVectors[])(void); +extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); + +__attribute__ ((used, section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = { + // Core Level - CM7 + &_vStackTop, // The initial stack pointer + ResetISR, // The reset handler + NMI_Handler, // The NMI handler + HardFault_Handler, // The hard fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall handler + 0, // Reserved + 0, // Reserved + PendSV_Handler, // The PendSV handler + SysTick_Handler, // The SysTick handler + + // Chip Level - MIMXRT1061 + DMA0_DMA16_IRQHandler, // 16 : DMA channel 0/16 transfer complete + DMA1_DMA17_IRQHandler, // 17 : DMA channel 1/17 transfer complete + DMA2_DMA18_IRQHandler, // 18 : DMA channel 2/18 transfer complete + DMA3_DMA19_IRQHandler, // 19 : DMA channel 3/19 transfer complete + DMA4_DMA20_IRQHandler, // 20 : DMA channel 4/20 transfer complete + DMA5_DMA21_IRQHandler, // 21 : DMA channel 5/21 transfer complete + DMA6_DMA22_IRQHandler, // 22 : DMA channel 6/22 transfer complete + DMA7_DMA23_IRQHandler, // 23 : DMA channel 7/23 transfer complete + DMA8_DMA24_IRQHandler, // 24 : DMA channel 8/24 transfer complete + DMA9_DMA25_IRQHandler, // 25 : DMA channel 9/25 transfer complete + DMA10_DMA26_IRQHandler, // 26 : DMA channel 10/26 transfer complete + DMA11_DMA27_IRQHandler, // 27 : DMA channel 11/27 transfer complete + DMA12_DMA28_IRQHandler, // 28 : DMA channel 12/28 transfer complete + DMA13_DMA29_IRQHandler, // 29 : DMA channel 13/29 transfer complete + DMA14_DMA30_IRQHandler, // 30 : DMA channel 14/30 transfer complete + DMA15_DMA31_IRQHandler, // 31 : DMA channel 15/31 transfer complete + DMA_ERROR_IRQHandler, // 32 : DMA error interrupt channels 0-15 / 16-31 + CTI0_ERROR_IRQHandler, // 33 : CTI0_Error + CTI1_ERROR_IRQHandler, // 34 : CTI1_Error + CORE_IRQHandler, // 35 : CorePlatform exception IRQ + LPUART1_IRQHandler, // 36 : LPUART1 TX interrupt and RX interrupt + LPUART2_IRQHandler, // 37 : LPUART2 TX interrupt and RX interrupt + LPUART3_IRQHandler, // 38 : LPUART3 TX interrupt and RX interrupt + LPUART4_IRQHandler, // 39 : LPUART4 TX interrupt and RX interrupt + LPUART5_IRQHandler, // 40 : LPUART5 TX interrupt and RX interrupt + LPUART6_IRQHandler, // 41 : LPUART6 TX interrupt and RX interrupt + LPUART7_IRQHandler, // 42 : LPUART7 TX interrupt and RX interrupt + LPUART8_IRQHandler, // 43 : LPUART8 TX interrupt and RX interrupt + LPI2C1_IRQHandler, // 44 : LPI2C1 interrupt + LPI2C2_IRQHandler, // 45 : LPI2C2 interrupt + LPI2C3_IRQHandler, // 46 : LPI2C3 interrupt + LPI2C4_IRQHandler, // 47 : LPI2C4 interrupt + LPSPI1_IRQHandler, // 48 : LPSPI1 single interrupt vector for all sources + LPSPI2_IRQHandler, // 49 : LPSPI2 single interrupt vector for all sources + LPSPI3_IRQHandler, // 50 : LPSPI3 single interrupt vector for all sources + LPSPI4_IRQHandler, // 51 : LPSPI4 single interrupt vector for all sources + CAN1_IRQHandler, // 52 : CAN1 interrupt + CAN2_IRQHandler, // 53 : CAN2 interrupt + FLEXRAM_IRQHandler, // 54 : FlexRAM address out of range Or access hit IRQ + KPP_IRQHandler, // 55 : Keypad nterrupt + TSC_DIG_IRQHandler, // 56 : TSC interrupt + GPR_IRQ_IRQHandler, // 57 : GPR interrupt + Reserved58_IRQHandler, // 58 : Reserved interrupt + Reserved59_IRQHandler, // 59 : Reserved interrupt + Reserved60_IRQHandler, // 60 : Reserved interrupt + WDOG2_IRQHandler, // 61 : WDOG2 interrupt + SNVS_HP_WRAPPER_IRQHandler, // 62 : SRTC Consolidated Interrupt. Non TZ + SNVS_HP_WRAPPER_TZ_IRQHandler, // 63 : SRTC Security Interrupt. TZ + SNVS_LP_WRAPPER_IRQHandler, // 64 : ON-OFF button press shorter than 5 secs (pulse event) + CSU_IRQHandler, // 65 : CSU interrupt + DCP_IRQHandler, // 66 : DCP_IRQ interrupt + DCP_VMI_IRQHandler, // 67 : DCP_VMI_IRQ interrupt + Reserved68_IRQHandler, // 68 : Reserved interrupt + TRNG_IRQHandler, // 69 : TRNG interrupt + SJC_IRQHandler, // 70 : SJC interrupt + BEE_IRQHandler, // 71 : BEE interrupt + SAI1_IRQHandler, // 72 : SAI1 interrupt + SAI2_IRQHandler, // 73 : SAI1 interrupt + SAI3_RX_IRQHandler, // 74 : SAI3 interrupt + SAI3_TX_IRQHandler, // 75 : SAI3 interrupt + SPDIF_IRQHandler, // 76 : SPDIF interrupt + PMU_EVENT_IRQHandler, // 77 : Brown-out event interrupt + Reserved78_IRQHandler, // 78 : Reserved interrupt + TEMP_LOW_HIGH_IRQHandler, // 79 : TempSensor low/high interrupt + TEMP_PANIC_IRQHandler, // 80 : TempSensor panic interrupt + USB_PHY1_IRQHandler, // 81 : USBPHY (UTMI0), Interrupt + USB_PHY2_IRQHandler, // 82 : USBPHY (UTMI1), Interrupt + ADC1_IRQHandler, // 83 : ADC1 interrupt + ADC2_IRQHandler, // 84 : ADC2 interrupt + DCDC_IRQHandler, // 85 : DCDC interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + Reserved87_IRQHandler, // 87 : Reserved interrupt + GPIO1_INT0_IRQHandler, // 88 : Active HIGH Interrupt from INT0 from GPIO + GPIO1_INT1_IRQHandler, // 89 : Active HIGH Interrupt from INT1 from GPIO + GPIO1_INT2_IRQHandler, // 90 : Active HIGH Interrupt from INT2 from GPIO + GPIO1_INT3_IRQHandler, // 91 : Active HIGH Interrupt from INT3 from GPIO + GPIO1_INT4_IRQHandler, // 92 : Active HIGH Interrupt from INT4 from GPIO + GPIO1_INT5_IRQHandler, // 93 : Active HIGH Interrupt from INT5 from GPIO + GPIO1_INT6_IRQHandler, // 94 : Active HIGH Interrupt from INT6 from GPIO + GPIO1_INT7_IRQHandler, // 95 : Active HIGH Interrupt from INT7 from GPIO + GPIO1_Combined_0_15_IRQHandler, // 96 : Combined interrupt indication for GPIO1 signal 0 throughout 15 + GPIO1_Combined_16_31_IRQHandler, // 97 : Combined interrupt indication for GPIO1 signal 16 throughout 31 + GPIO2_Combined_0_15_IRQHandler, // 98 : Combined interrupt indication for GPIO2 signal 0 throughout 15 + GPIO2_Combined_16_31_IRQHandler, // 99 : Combined interrupt indication for GPIO2 signal 16 throughout 31 + GPIO3_Combined_0_15_IRQHandler, // 100: Combined interrupt indication for GPIO3 signal 0 throughout 15 + GPIO3_Combined_16_31_IRQHandler, // 101: Combined interrupt indication for GPIO3 signal 16 throughout 31 + GPIO4_Combined_0_15_IRQHandler, // 102: Combined interrupt indication for GPIO4 signal 0 throughout 15 + GPIO4_Combined_16_31_IRQHandler, // 103: Combined interrupt indication for GPIO4 signal 16 throughout 31 + GPIO5_Combined_0_15_IRQHandler, // 104: Combined interrupt indication for GPIO5 signal 0 throughout 15 + GPIO5_Combined_16_31_IRQHandler, // 105: Combined interrupt indication for GPIO5 signal 16 throughout 31 + FLEXIO1_IRQHandler, // 106: FLEXIO1 interrupt + FLEXIO2_IRQHandler, // 107: FLEXIO2 interrupt + WDOG1_IRQHandler, // 108: WDOG1 interrupt + RTWDOG_IRQHandler, // 109: RTWDOG interrupt + EWM_IRQHandler, // 110: EWM interrupt + CCM_1_IRQHandler, // 111: CCM IRQ1 interrupt + CCM_2_IRQHandler, // 112: CCM IRQ2 interrupt + GPC_IRQHandler, // 113: GPC interrupt + SRC_IRQHandler, // 114: SRC interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + GPT1_IRQHandler, // 116: GPT1 interrupt + GPT2_IRQHandler, // 117: GPT2 interrupt + PWM1_0_IRQHandler, // 118: PWM1 capture 0, compare 0, or reload 0 interrupt + PWM1_1_IRQHandler, // 119: PWM1 capture 1, compare 1, or reload 0 interrupt + PWM1_2_IRQHandler, // 120: PWM1 capture 2, compare 2, or reload 0 interrupt + PWM1_3_IRQHandler, // 121: PWM1 capture 3, compare 3, or reload 0 interrupt + PWM1_FAULT_IRQHandler, // 122: PWM1 fault or reload error interrupt + FLEXSPI2_IRQHandler, // 123: FlexSPI2 interrupt + FLEXSPI_IRQHandler, // 124: FlexSPI0 interrupt + SEMC_IRQHandler, // 125: Reserved interrupt + USDHC1_IRQHandler, // 126: USDHC1 interrupt + USDHC2_IRQHandler, // 127: USDHC2 interrupt + USB_OTG2_IRQHandler, // 128: USBO2 USB OTG2 + USB_OTG1_IRQHandler, // 129: USBO2 USB OTG1 + ENET_IRQHandler, // 130: ENET interrupt + ENET_1588_Timer_IRQHandler, // 131: ENET_1588_Timer interrupt + XBAR1_IRQ_0_1_IRQHandler, // 132: XBAR1 interrupt + XBAR1_IRQ_2_3_IRQHandler, // 133: XBAR1 interrupt + ADC_ETC_IRQ0_IRQHandler, // 134: ADCETC IRQ0 interrupt + ADC_ETC_IRQ1_IRQHandler, // 135: ADCETC IRQ1 interrupt + ADC_ETC_IRQ2_IRQHandler, // 136: ADCETC IRQ2 interrupt + ADC_ETC_ERROR_IRQ_IRQHandler, // 137: ADCETC Error IRQ interrupt + PIT_IRQHandler, // 138: PIT interrupt + ACMP1_IRQHandler, // 139: ACMP interrupt + ACMP2_IRQHandler, // 140: ACMP interrupt + ACMP3_IRQHandler, // 141: ACMP interrupt + ACMP4_IRQHandler, // 142: ACMP interrupt + Reserved143_IRQHandler, // 143: Reserved interrupt + Reserved144_IRQHandler, // 144: Reserved interrupt + ENC1_IRQHandler, // 145: ENC1 interrupt + ENC2_IRQHandler, // 146: ENC2 interrupt + ENC3_IRQHandler, // 147: ENC3 interrupt + ENC4_IRQHandler, // 148: ENC4 interrupt + TMR1_IRQHandler, // 149: TMR1 interrupt + TMR2_IRQHandler, // 150: TMR2 interrupt + TMR3_IRQHandler, // 151: TMR3 interrupt + TMR4_IRQHandler, // 152: TMR4 interrupt + PWM2_0_IRQHandler, // 153: PWM2 capture 0, compare 0, or reload 0 interrupt + PWM2_1_IRQHandler, // 154: PWM2 capture 1, compare 1, or reload 0 interrupt + PWM2_2_IRQHandler, // 155: PWM2 capture 2, compare 2, or reload 0 interrupt + PWM2_3_IRQHandler, // 156: PWM2 capture 3, compare 3, or reload 0 interrupt + PWM2_FAULT_IRQHandler, // 157: PWM2 fault or reload error interrupt + PWM3_0_IRQHandler, // 158: PWM3 capture 0, compare 0, or reload 0 interrupt + PWM3_1_IRQHandler, // 159: PWM3 capture 1, compare 1, or reload 0 interrupt + PWM3_2_IRQHandler, // 160: PWM3 capture 2, compare 2, or reload 0 interrupt + PWM3_3_IRQHandler, // 161: PWM3 capture 3, compare 3, or reload 0 interrupt + PWM3_FAULT_IRQHandler, // 162: PWM3 fault or reload error interrupt + PWM4_0_IRQHandler, // 163: PWM4 capture 0, compare 0, or reload 0 interrupt + PWM4_1_IRQHandler, // 164: PWM4 capture 1, compare 1, or reload 0 interrupt + PWM4_2_IRQHandler, // 165: PWM4 capture 2, compare 2, or reload 0 interrupt + PWM4_3_IRQHandler, // 166: PWM4 capture 3, compare 3, or reload 0 interrupt + PWM4_FAULT_IRQHandler, // 167: PWM4 fault or reload error interrupt + ENET2_IRQHandler, // 168: ENET2 interrupt + ENET2_1588_Timer_IRQHandler, // 169: ENET2_1588_Timer interrupt + CAN3_IRQHandler, // 170: CAN3 interrupt + Reserved171_IRQHandler, // 171: Reserved interrupt + FLEXIO3_IRQHandler, // 172: FLEXIO3 interrupt + GPIO6_7_8_9_IRQHandler, // 173: GPIO6, GPIO7, GPIO8, GPIO9 interrupt + +}; /* End of g_pfnVectors */ + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__ ((section(".after_vectors.init_data"))) +void data_init(unsigned int romstart, unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int *pulSrc = (unsigned int*) romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__ ((section(".after_vectors.init_bss"))) +void bss_init(unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +__attribute__ ((section(".after_vectors.reset"))) +void ResetISR(void) { + + // Disable interrupts + __asm volatile ("cpsid i"); + + +#if defined (__USE_CMSIS) +// If __USE_CMSIS defined, then call CMSIS SystemInit code + SystemInit(); +#else + // Disable Watchdog + volatile unsigned int *WDOG1_WCR = (unsigned int *) 0x400B8000; + *WDOG1_WCR = *WDOG1_WCR & ~(1 << 2); + volatile unsigned int *WDOG2_WCR = (unsigned int *) 0x400D0000; + *WDOG2_WCR = *WDOG2_WCR & ~(1 << 2); + // Write watchdog update key to unlock + *((volatile unsigned int *)0x400BC004) = 0xD928C520; + // Set timeout value + *((volatile unsigned int *)0x400BC008) = 0xFFFF; + // Now disable watchdog via control register + volatile unsigned int *RTWDOG_CS = (unsigned int *) 0x400BC000; + *RTWDOG_CS = (*RTWDOG_CS & ~(1 << 7)) | (1 << 5); + +#endif // (__USE_CMSIS) + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + + +#if !defined (__USE_CMSIS) +// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code +// will setup the VTOR register + + // Check to see if we are running the code from a non-zero + // address (eg RAM, external flash), in which case we need + // to modify the VTOR register to tell the CPU that the + // vector table is located at a non-0x0 address. + unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; + if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) { + *pSCB_VTOR = (unsigned int)g_pfnVectors; + } +#endif // (__USE_CMSIS) +#if defined (__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif + + // Reenable interrupts + __asm volatile ("cpsie i"); + +#if defined (__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // + while (1) { + ; + } +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ while(1) {} +} + +WEAK_AV void HardFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SVC_Handler(void) +{ while(1) {} +} + +WEAK_AV void PendSV_Handler(void) +{ while(1) {} +} + +WEAK_AV void SysTick_Handler(void) +{ while(1) {} +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void IntDefaultHandler(void) +{ while(1) {} +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or IntDefaultHandler() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void DMA0_DMA16_IRQHandler(void) +{ DMA0_DMA16_DriverIRQHandler(); +} + +WEAK void DMA1_DMA17_IRQHandler(void) +{ DMA1_DMA17_DriverIRQHandler(); +} + +WEAK void DMA2_DMA18_IRQHandler(void) +{ DMA2_DMA18_DriverIRQHandler(); +} + +WEAK void DMA3_DMA19_IRQHandler(void) +{ DMA3_DMA19_DriverIRQHandler(); +} + +WEAK void DMA4_DMA20_IRQHandler(void) +{ DMA4_DMA20_DriverIRQHandler(); +} + +WEAK void DMA5_DMA21_IRQHandler(void) +{ DMA5_DMA21_DriverIRQHandler(); +} + +WEAK void DMA6_DMA22_IRQHandler(void) +{ DMA6_DMA22_DriverIRQHandler(); +} + +WEAK void DMA7_DMA23_IRQHandler(void) +{ DMA7_DMA23_DriverIRQHandler(); +} + +WEAK void DMA8_DMA24_IRQHandler(void) +{ DMA8_DMA24_DriverIRQHandler(); +} + +WEAK void DMA9_DMA25_IRQHandler(void) +{ DMA9_DMA25_DriverIRQHandler(); +} + +WEAK void DMA10_DMA26_IRQHandler(void) +{ DMA10_DMA26_DriverIRQHandler(); +} + +WEAK void DMA11_DMA27_IRQHandler(void) +{ DMA11_DMA27_DriverIRQHandler(); +} + +WEAK void DMA12_DMA28_IRQHandler(void) +{ DMA12_DMA28_DriverIRQHandler(); +} + +WEAK void DMA13_DMA29_IRQHandler(void) +{ DMA13_DMA29_DriverIRQHandler(); +} + +WEAK void DMA14_DMA30_IRQHandler(void) +{ DMA14_DMA30_DriverIRQHandler(); +} + +WEAK void DMA15_DMA31_IRQHandler(void) +{ DMA15_DMA31_DriverIRQHandler(); +} + +WEAK void DMA_ERROR_IRQHandler(void) +{ DMA_ERROR_DriverIRQHandler(); +} + +WEAK void CTI0_ERROR_IRQHandler(void) +{ CTI0_ERROR_DriverIRQHandler(); +} + +WEAK void CTI1_ERROR_IRQHandler(void) +{ CTI1_ERROR_DriverIRQHandler(); +} + +WEAK void CORE_IRQHandler(void) +{ CORE_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ LPUART4_DriverIRQHandler(); +} + +WEAK void LPUART5_IRQHandler(void) +{ LPUART5_DriverIRQHandler(); +} + +WEAK void LPUART6_IRQHandler(void) +{ LPUART6_DriverIRQHandler(); +} + +WEAK void LPUART7_IRQHandler(void) +{ LPUART7_DriverIRQHandler(); +} + +WEAK void LPUART8_IRQHandler(void) +{ LPUART8_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ LPI2C1_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ LPI2C3_DriverIRQHandler(); +} + +WEAK void LPI2C4_IRQHandler(void) +{ LPI2C4_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ LPSPI1_DriverIRQHandler(); +} + +WEAK void LPSPI2_IRQHandler(void) +{ LPSPI2_DriverIRQHandler(); +} + +WEAK void LPSPI3_IRQHandler(void) +{ LPSPI3_DriverIRQHandler(); +} + +WEAK void LPSPI4_IRQHandler(void) +{ LPSPI4_DriverIRQHandler(); +} + +WEAK void CAN1_IRQHandler(void) +{ CAN1_DriverIRQHandler(); +} + +WEAK void CAN2_IRQHandler(void) +{ CAN2_DriverIRQHandler(); +} + +WEAK void FLEXRAM_IRQHandler(void) +{ FLEXRAM_DriverIRQHandler(); +} + +WEAK void KPP_IRQHandler(void) +{ KPP_DriverIRQHandler(); +} + +WEAK void TSC_DIG_IRQHandler(void) +{ TSC_DIG_DriverIRQHandler(); +} + +WEAK void GPR_IRQ_IRQHandler(void) +{ GPR_IRQ_DriverIRQHandler(); +} + +WEAK void Reserved58_IRQHandler(void) +{ Reserved58_DriverIRQHandler(); +} + +WEAK void Reserved59_IRQHandler(void) +{ Reserved59_DriverIRQHandler(); +} + +WEAK void Reserved60_IRQHandler(void) +{ Reserved60_DriverIRQHandler(); +} + +WEAK void WDOG2_IRQHandler(void) +{ WDOG2_DriverIRQHandler(); +} + +WEAK void SNVS_HP_WRAPPER_IRQHandler(void) +{ SNVS_HP_WRAPPER_DriverIRQHandler(); +} + +WEAK void SNVS_HP_WRAPPER_TZ_IRQHandler(void) +{ SNVS_HP_WRAPPER_TZ_DriverIRQHandler(); +} + +WEAK void SNVS_LP_WRAPPER_IRQHandler(void) +{ SNVS_LP_WRAPPER_DriverIRQHandler(); +} + +WEAK void CSU_IRQHandler(void) +{ CSU_DriverIRQHandler(); +} + +WEAK void DCP_IRQHandler(void) +{ DCP_DriverIRQHandler(); +} + +WEAK void DCP_VMI_IRQHandler(void) +{ DCP_VMI_DriverIRQHandler(); +} + +WEAK void Reserved68_IRQHandler(void) +{ Reserved68_DriverIRQHandler(); +} + +WEAK void TRNG_IRQHandler(void) +{ TRNG_DriverIRQHandler(); +} + +WEAK void SJC_IRQHandler(void) +{ SJC_DriverIRQHandler(); +} + +WEAK void BEE_IRQHandler(void) +{ BEE_DriverIRQHandler(); +} + +WEAK void SAI1_IRQHandler(void) +{ SAI1_DriverIRQHandler(); +} + +WEAK void SAI2_IRQHandler(void) +{ SAI2_DriverIRQHandler(); +} + +WEAK void SAI3_RX_IRQHandler(void) +{ SAI3_RX_DriverIRQHandler(); +} + +WEAK void SAI3_TX_IRQHandler(void) +{ SAI3_TX_DriverIRQHandler(); +} + +WEAK void SPDIF_IRQHandler(void) +{ SPDIF_DriverIRQHandler(); +} + +WEAK void PMU_EVENT_IRQHandler(void) +{ PMU_EVENT_DriverIRQHandler(); +} + +WEAK void Reserved78_IRQHandler(void) +{ Reserved78_DriverIRQHandler(); +} + +WEAK void TEMP_LOW_HIGH_IRQHandler(void) +{ TEMP_LOW_HIGH_DriverIRQHandler(); +} + +WEAK void TEMP_PANIC_IRQHandler(void) +{ TEMP_PANIC_DriverIRQHandler(); +} + +WEAK void USB_PHY1_IRQHandler(void) +{ USB_PHY1_DriverIRQHandler(); +} + +WEAK void USB_PHY2_IRQHandler(void) +{ USB_PHY2_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ ADC1_DriverIRQHandler(); +} + +WEAK void ADC2_IRQHandler(void) +{ ADC2_DriverIRQHandler(); +} + +WEAK void DCDC_IRQHandler(void) +{ DCDC_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ Reserved86_DriverIRQHandler(); +} + +WEAK void Reserved87_IRQHandler(void) +{ Reserved87_DriverIRQHandler(); +} + +WEAK void GPIO1_INT0_IRQHandler(void) +{ GPIO1_INT0_DriverIRQHandler(); +} + +WEAK void GPIO1_INT1_IRQHandler(void) +{ GPIO1_INT1_DriverIRQHandler(); +} + +WEAK void GPIO1_INT2_IRQHandler(void) +{ GPIO1_INT2_DriverIRQHandler(); +} + +WEAK void GPIO1_INT3_IRQHandler(void) +{ GPIO1_INT3_DriverIRQHandler(); +} + +WEAK void GPIO1_INT4_IRQHandler(void) +{ GPIO1_INT4_DriverIRQHandler(); +} + +WEAK void GPIO1_INT5_IRQHandler(void) +{ GPIO1_INT5_DriverIRQHandler(); +} + +WEAK void GPIO1_INT6_IRQHandler(void) +{ GPIO1_INT6_DriverIRQHandler(); +} + +WEAK void GPIO1_INT7_IRQHandler(void) +{ GPIO1_INT7_DriverIRQHandler(); +} + +WEAK void GPIO1_Combined_0_15_IRQHandler(void) +{ GPIO1_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO1_Combined_16_31_IRQHandler(void) +{ GPIO1_Combined_16_31_DriverIRQHandler(); +} + +WEAK void GPIO2_Combined_0_15_IRQHandler(void) +{ GPIO2_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO2_Combined_16_31_IRQHandler(void) +{ GPIO2_Combined_16_31_DriverIRQHandler(); +} + +WEAK void GPIO3_Combined_0_15_IRQHandler(void) +{ GPIO3_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO3_Combined_16_31_IRQHandler(void) +{ GPIO3_Combined_16_31_DriverIRQHandler(); +} + +WEAK void GPIO4_Combined_0_15_IRQHandler(void) +{ GPIO4_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO4_Combined_16_31_IRQHandler(void) +{ GPIO4_Combined_16_31_DriverIRQHandler(); +} + +WEAK void GPIO5_Combined_0_15_IRQHandler(void) +{ GPIO5_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO5_Combined_16_31_IRQHandler(void) +{ GPIO5_Combined_16_31_DriverIRQHandler(); +} + +WEAK void FLEXIO1_IRQHandler(void) +{ FLEXIO1_DriverIRQHandler(); +} + +WEAK void FLEXIO2_IRQHandler(void) +{ FLEXIO2_DriverIRQHandler(); +} + +WEAK void WDOG1_IRQHandler(void) +{ WDOG1_DriverIRQHandler(); +} + +WEAK void RTWDOG_IRQHandler(void) +{ RTWDOG_DriverIRQHandler(); +} + +WEAK void EWM_IRQHandler(void) +{ EWM_DriverIRQHandler(); +} + +WEAK void CCM_1_IRQHandler(void) +{ CCM_1_DriverIRQHandler(); +} + +WEAK void CCM_2_IRQHandler(void) +{ CCM_2_DriverIRQHandler(); +} + +WEAK void GPC_IRQHandler(void) +{ GPC_DriverIRQHandler(); +} + +WEAK void SRC_IRQHandler(void) +{ SRC_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ Reserved115_DriverIRQHandler(); +} + +WEAK void GPT1_IRQHandler(void) +{ GPT1_DriverIRQHandler(); +} + +WEAK void GPT2_IRQHandler(void) +{ GPT2_DriverIRQHandler(); +} + +WEAK void PWM1_0_IRQHandler(void) +{ PWM1_0_DriverIRQHandler(); +} + +WEAK void PWM1_1_IRQHandler(void) +{ PWM1_1_DriverIRQHandler(); +} + +WEAK void PWM1_2_IRQHandler(void) +{ PWM1_2_DriverIRQHandler(); +} + +WEAK void PWM1_3_IRQHandler(void) +{ PWM1_3_DriverIRQHandler(); +} + +WEAK void PWM1_FAULT_IRQHandler(void) +{ PWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXSPI2_IRQHandler(void) +{ FLEXSPI2_DriverIRQHandler(); +} + +WEAK void FLEXSPI_IRQHandler(void) +{ FLEXSPI_DriverIRQHandler(); +} + +WEAK void SEMC_IRQHandler(void) +{ SEMC_DriverIRQHandler(); +} + +WEAK void USDHC1_IRQHandler(void) +{ USDHC1_DriverIRQHandler(); +} + +WEAK void USDHC2_IRQHandler(void) +{ USDHC2_DriverIRQHandler(); +} + +WEAK void USB_OTG2_IRQHandler(void) +{ USB_OTG2_DriverIRQHandler(); +} + +WEAK void USB_OTG1_IRQHandler(void) +{ USB_OTG1_DriverIRQHandler(); +} + +WEAK void ENET_IRQHandler(void) +{ ENET_DriverIRQHandler(); +} + +WEAK void ENET_1588_Timer_IRQHandler(void) +{ ENET_1588_Timer_DriverIRQHandler(); +} + +WEAK void XBAR1_IRQ_0_1_IRQHandler(void) +{ XBAR1_IRQ_0_1_DriverIRQHandler(); +} + +WEAK void XBAR1_IRQ_2_3_IRQHandler(void) +{ XBAR1_IRQ_2_3_DriverIRQHandler(); +} + +WEAK void ADC_ETC_IRQ0_IRQHandler(void) +{ ADC_ETC_IRQ0_DriverIRQHandler(); +} + +WEAK void ADC_ETC_IRQ1_IRQHandler(void) +{ ADC_ETC_IRQ1_DriverIRQHandler(); +} + +WEAK void ADC_ETC_IRQ2_IRQHandler(void) +{ ADC_ETC_IRQ2_DriverIRQHandler(); +} + +WEAK void ADC_ETC_ERROR_IRQ_IRQHandler(void) +{ ADC_ETC_ERROR_IRQ_DriverIRQHandler(); +} + +WEAK void PIT_IRQHandler(void) +{ PIT_DriverIRQHandler(); +} + +WEAK void ACMP1_IRQHandler(void) +{ ACMP1_DriverIRQHandler(); +} + +WEAK void ACMP2_IRQHandler(void) +{ ACMP2_DriverIRQHandler(); +} + +WEAK void ACMP3_IRQHandler(void) +{ ACMP3_DriverIRQHandler(); +} + +WEAK void ACMP4_IRQHandler(void) +{ ACMP4_DriverIRQHandler(); +} + +WEAK void Reserved143_IRQHandler(void) +{ Reserved143_DriverIRQHandler(); +} + +WEAK void Reserved144_IRQHandler(void) +{ Reserved144_DriverIRQHandler(); +} + +WEAK void ENC1_IRQHandler(void) +{ ENC1_DriverIRQHandler(); +} + +WEAK void ENC2_IRQHandler(void) +{ ENC2_DriverIRQHandler(); +} + +WEAK void ENC3_IRQHandler(void) +{ ENC3_DriverIRQHandler(); +} + +WEAK void ENC4_IRQHandler(void) +{ ENC4_DriverIRQHandler(); +} + +WEAK void TMR1_IRQHandler(void) +{ TMR1_DriverIRQHandler(); +} + +WEAK void TMR2_IRQHandler(void) +{ TMR2_DriverIRQHandler(); +} + +WEAK void TMR3_IRQHandler(void) +{ TMR3_DriverIRQHandler(); +} + +WEAK void TMR4_IRQHandler(void) +{ TMR4_DriverIRQHandler(); +} + +WEAK void PWM2_0_IRQHandler(void) +{ PWM2_0_DriverIRQHandler(); +} + +WEAK void PWM2_1_IRQHandler(void) +{ PWM2_1_DriverIRQHandler(); +} + +WEAK void PWM2_2_IRQHandler(void) +{ PWM2_2_DriverIRQHandler(); +} + +WEAK void PWM2_3_IRQHandler(void) +{ PWM2_3_DriverIRQHandler(); +} + +WEAK void PWM2_FAULT_IRQHandler(void) +{ PWM2_FAULT_DriverIRQHandler(); +} + +WEAK void PWM3_0_IRQHandler(void) +{ PWM3_0_DriverIRQHandler(); +} + +WEAK void PWM3_1_IRQHandler(void) +{ PWM3_1_DriverIRQHandler(); +} + +WEAK void PWM3_2_IRQHandler(void) +{ PWM3_2_DriverIRQHandler(); +} + +WEAK void PWM3_3_IRQHandler(void) +{ PWM3_3_DriverIRQHandler(); +} + +WEAK void PWM3_FAULT_IRQHandler(void) +{ PWM3_FAULT_DriverIRQHandler(); +} + +WEAK void PWM4_0_IRQHandler(void) +{ PWM4_0_DriverIRQHandler(); +} + +WEAK void PWM4_1_IRQHandler(void) +{ PWM4_1_DriverIRQHandler(); +} + +WEAK void PWM4_2_IRQHandler(void) +{ PWM4_2_DriverIRQHandler(); +} + +WEAK void PWM4_3_IRQHandler(void) +{ PWM4_3_DriverIRQHandler(); +} + +WEAK void PWM4_FAULT_IRQHandler(void) +{ PWM4_FAULT_DriverIRQHandler(); +} + +WEAK void ENET2_IRQHandler(void) +{ ENET2_DriverIRQHandler(); +} + +WEAK void ENET2_1588_Timer_IRQHandler(void) +{ ENET2_1588_Timer_DriverIRQHandler(); +} + +WEAK void CAN3_IRQHandler(void) +{ CAN3_DriverIRQHandler(); +} + +WEAK void Reserved171_IRQHandler(void) +{ Reserved171_DriverIRQHandler(); +} + +WEAK void FLEXIO3_IRQHandler(void) +{ FLEXIO3_DriverIRQHandler(); +} + +WEAK void GPIO6_7_8_9_IRQHandler(void) +{ GPIO6_7_8_9_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC pop_options +#endif // (DEBUG) diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/mcuxpresso/startup_mimxrt1061.cpp b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/mcuxpresso/startup_mimxrt1061.cpp new file mode 100644 index 0000000000..e56cbeff7c --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/mcuxpresso/startup_mimxrt1061.cpp @@ -0,0 +1,1411 @@ +//***************************************************************************** +// MIMXRT1061 startup code for use with MCUXpresso IDE +// +// Version : 240119 +//***************************************************************************** +// +// Copyright 2016-2019 NXP +// All rights reserved. +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC push_options +#pragma GCC optimize ("Og") +#endif // (DEBUG) + +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { + extern void __libc_init_array(void); +} +#endif +#endif + +#define WEAK __attribute__ ((weak)) +#define WEAK_AV __attribute__ ((weak, section(".after_vectors"))) +#define ALIAS(f) __attribute__ ((weak, alias (#f))) + +//***************************************************************************** +#if defined (__cplusplus) +extern "C" { +#endif + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +#if defined (__USE_CMSIS) +extern void SystemInit(void); +#endif // (__USE_CMSIS) + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** + void ResetISR(void); +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void IntDefaultHandler(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void DMA0_DMA16_IRQHandler(void); +WEAK void DMA1_DMA17_IRQHandler(void); +WEAK void DMA2_DMA18_IRQHandler(void); +WEAK void DMA3_DMA19_IRQHandler(void); +WEAK void DMA4_DMA20_IRQHandler(void); +WEAK void DMA5_DMA21_IRQHandler(void); +WEAK void DMA6_DMA22_IRQHandler(void); +WEAK void DMA7_DMA23_IRQHandler(void); +WEAK void DMA8_DMA24_IRQHandler(void); +WEAK void DMA9_DMA25_IRQHandler(void); +WEAK void DMA10_DMA26_IRQHandler(void); +WEAK void DMA11_DMA27_IRQHandler(void); +WEAK void DMA12_DMA28_IRQHandler(void); +WEAK void DMA13_DMA29_IRQHandler(void); +WEAK void DMA14_DMA30_IRQHandler(void); +WEAK void DMA15_DMA31_IRQHandler(void); +WEAK void DMA_ERROR_IRQHandler(void); +WEAK void CTI0_ERROR_IRQHandler(void); +WEAK void CTI1_ERROR_IRQHandler(void); +WEAK void CORE_IRQHandler(void); +WEAK void LPUART1_IRQHandler(void); +WEAK void LPUART2_IRQHandler(void); +WEAK void LPUART3_IRQHandler(void); +WEAK void LPUART4_IRQHandler(void); +WEAK void LPUART5_IRQHandler(void); +WEAK void LPUART6_IRQHandler(void); +WEAK void LPUART7_IRQHandler(void); +WEAK void LPUART8_IRQHandler(void); +WEAK void LPI2C1_IRQHandler(void); +WEAK void LPI2C2_IRQHandler(void); +WEAK void LPI2C3_IRQHandler(void); +WEAK void LPI2C4_IRQHandler(void); +WEAK void LPSPI1_IRQHandler(void); +WEAK void LPSPI2_IRQHandler(void); +WEAK void LPSPI3_IRQHandler(void); +WEAK void LPSPI4_IRQHandler(void); +WEAK void CAN1_IRQHandler(void); +WEAK void CAN2_IRQHandler(void); +WEAK void FLEXRAM_IRQHandler(void); +WEAK void KPP_IRQHandler(void); +WEAK void TSC_DIG_IRQHandler(void); +WEAK void GPR_IRQ_IRQHandler(void); +WEAK void Reserved58_IRQHandler(void); +WEAK void Reserved59_IRQHandler(void); +WEAK void Reserved60_IRQHandler(void); +WEAK void WDOG2_IRQHandler(void); +WEAK void SNVS_HP_WRAPPER_IRQHandler(void); +WEAK void SNVS_HP_WRAPPER_TZ_IRQHandler(void); +WEAK void SNVS_LP_WRAPPER_IRQHandler(void); +WEAK void CSU_IRQHandler(void); +WEAK void DCP_IRQHandler(void); +WEAK void DCP_VMI_IRQHandler(void); +WEAK void Reserved68_IRQHandler(void); +WEAK void TRNG_IRQHandler(void); +WEAK void SJC_IRQHandler(void); +WEAK void BEE_IRQHandler(void); +WEAK void SAI1_IRQHandler(void); +WEAK void SAI2_IRQHandler(void); +WEAK void SAI3_RX_IRQHandler(void); +WEAK void SAI3_TX_IRQHandler(void); +WEAK void SPDIF_IRQHandler(void); +WEAK void PMU_EVENT_IRQHandler(void); +WEAK void Reserved78_IRQHandler(void); +WEAK void TEMP_LOW_HIGH_IRQHandler(void); +WEAK void TEMP_PANIC_IRQHandler(void); +WEAK void USB_PHY1_IRQHandler(void); +WEAK void USB_PHY2_IRQHandler(void); +WEAK void ADC1_IRQHandler(void); +WEAK void ADC2_IRQHandler(void); +WEAK void DCDC_IRQHandler(void); +WEAK void Reserved86_IRQHandler(void); +WEAK void Reserved87_IRQHandler(void); +WEAK void GPIO1_INT0_IRQHandler(void); +WEAK void GPIO1_INT1_IRQHandler(void); +WEAK void GPIO1_INT2_IRQHandler(void); +WEAK void GPIO1_INT3_IRQHandler(void); +WEAK void GPIO1_INT4_IRQHandler(void); +WEAK void GPIO1_INT5_IRQHandler(void); +WEAK void GPIO1_INT6_IRQHandler(void); +WEAK void GPIO1_INT7_IRQHandler(void); +WEAK void GPIO1_Combined_0_15_IRQHandler(void); +WEAK void GPIO1_Combined_16_31_IRQHandler(void); +WEAK void GPIO2_Combined_0_15_IRQHandler(void); +WEAK void GPIO2_Combined_16_31_IRQHandler(void); +WEAK void GPIO3_Combined_0_15_IRQHandler(void); +WEAK void GPIO3_Combined_16_31_IRQHandler(void); +WEAK void GPIO4_Combined_0_15_IRQHandler(void); +WEAK void GPIO4_Combined_16_31_IRQHandler(void); +WEAK void GPIO5_Combined_0_15_IRQHandler(void); +WEAK void GPIO5_Combined_16_31_IRQHandler(void); +WEAK void FLEXIO1_IRQHandler(void); +WEAK void FLEXIO2_IRQHandler(void); +WEAK void WDOG1_IRQHandler(void); +WEAK void RTWDOG_IRQHandler(void); +WEAK void EWM_IRQHandler(void); +WEAK void CCM_1_IRQHandler(void); +WEAK void CCM_2_IRQHandler(void); +WEAK void GPC_IRQHandler(void); +WEAK void SRC_IRQHandler(void); +WEAK void Reserved115_IRQHandler(void); +WEAK void GPT1_IRQHandler(void); +WEAK void GPT2_IRQHandler(void); +WEAK void PWM1_0_IRQHandler(void); +WEAK void PWM1_1_IRQHandler(void); +WEAK void PWM1_2_IRQHandler(void); +WEAK void PWM1_3_IRQHandler(void); +WEAK void PWM1_FAULT_IRQHandler(void); +WEAK void FLEXSPI2_IRQHandler(void); +WEAK void FLEXSPI_IRQHandler(void); +WEAK void SEMC_IRQHandler(void); +WEAK void USDHC1_IRQHandler(void); +WEAK void USDHC2_IRQHandler(void); +WEAK void USB_OTG2_IRQHandler(void); +WEAK void USB_OTG1_IRQHandler(void); +WEAK void ENET_IRQHandler(void); +WEAK void ENET_1588_Timer_IRQHandler(void); +WEAK void XBAR1_IRQ_0_1_IRQHandler(void); +WEAK void XBAR1_IRQ_2_3_IRQHandler(void); +WEAK void ADC_ETC_IRQ0_IRQHandler(void); +WEAK void ADC_ETC_IRQ1_IRQHandler(void); +WEAK void ADC_ETC_IRQ2_IRQHandler(void); +WEAK void ADC_ETC_ERROR_IRQ_IRQHandler(void); +WEAK void PIT_IRQHandler(void); +WEAK void ACMP1_IRQHandler(void); +WEAK void ACMP2_IRQHandler(void); +WEAK void ACMP3_IRQHandler(void); +WEAK void ACMP4_IRQHandler(void); +WEAK void Reserved143_IRQHandler(void); +WEAK void Reserved144_IRQHandler(void); +WEAK void ENC1_IRQHandler(void); +WEAK void ENC2_IRQHandler(void); +WEAK void ENC3_IRQHandler(void); +WEAK void ENC4_IRQHandler(void); +WEAK void TMR1_IRQHandler(void); +WEAK void TMR2_IRQHandler(void); +WEAK void TMR3_IRQHandler(void); +WEAK void TMR4_IRQHandler(void); +WEAK void PWM2_0_IRQHandler(void); +WEAK void PWM2_1_IRQHandler(void); +WEAK void PWM2_2_IRQHandler(void); +WEAK void PWM2_3_IRQHandler(void); +WEAK void PWM2_FAULT_IRQHandler(void); +WEAK void PWM3_0_IRQHandler(void); +WEAK void PWM3_1_IRQHandler(void); +WEAK void PWM3_2_IRQHandler(void); +WEAK void PWM3_3_IRQHandler(void); +WEAK void PWM3_FAULT_IRQHandler(void); +WEAK void PWM4_0_IRQHandler(void); +WEAK void PWM4_1_IRQHandler(void); +WEAK void PWM4_2_IRQHandler(void); +WEAK void PWM4_3_IRQHandler(void); +WEAK void PWM4_FAULT_IRQHandler(void); +WEAK void ENET2_IRQHandler(void); +WEAK void ENET2_1588_Timer_IRQHandler(void); +WEAK void CAN3_IRQHandler(void); +WEAK void Reserved171_IRQHandler(void); +WEAK void FLEXIO3_IRQHandler(void); +WEAK void GPIO6_7_8_9_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the IntDefaultHandler, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void DMA0_DMA16_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA1_DMA17_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA2_DMA18_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA3_DMA19_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA4_DMA20_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA5_DMA21_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA6_DMA22_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA7_DMA23_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA8_DMA24_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA9_DMA25_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA10_DMA26_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA11_DMA27_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA12_DMA28_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA13_DMA29_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA14_DMA30_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA15_DMA31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTI0_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTI1_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CORE_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPUART8_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPI2C1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPI2C2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPI2C3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPI2C4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPSPI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPSPI2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPSPI3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void LPSPI4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CAN1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CAN2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXRAM_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void KPP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TSC_DIG_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPR_IRQ_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved58_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved59_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved60_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WDOG2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SNVS_HP_WRAPPER_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SNVS_HP_WRAPPER_TZ_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SNVS_LP_WRAPPER_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CSU_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DCP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DCP_VMI_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved68_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TRNG_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SJC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void BEE_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI3_RX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SAI3_TX_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SPDIF_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PMU_EVENT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved78_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TEMP_LOW_HIGH_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TEMP_PANIC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB_PHY1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB_PHY2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DCDC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved86_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved87_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO1_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO2_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO2_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO3_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO3_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO4_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO4_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO5_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO5_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXIO1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXIO2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void WDOG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void RTWDOG_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void EWM_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CCM_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CCM_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SRC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved115_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM1_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXSPI2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXSPI_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SEMC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USDHC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USDHC2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB_OTG2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB_OTG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENET_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENET_1588_Timer_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void XBAR1_IRQ_0_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void XBAR1_IRQ_2_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_ETC_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_ETC_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_ETC_IRQ2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC_ETC_ERROR_IRQ_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ACMP4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved143_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved144_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENC2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENC3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENC4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TMR1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TMR2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TMR3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void TMR4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM2_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM3_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PWM4_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENET2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ENET2_1588_Timer_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CAN3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved171_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXIO3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GPIO6_7_8_9_DriverIRQHandler(void) ALIAS(IntDefaultHandler); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined (__REDLIB__) +extern void __main(void); +#endif +extern int main(void); + +//***************************************************************************** +// External declaration for the pointer to the stack top from the Linker Script +//***************************************************************************** +extern void _vStackTop(void); +//***************************************************************************** +#if defined (__cplusplus) +} // extern "C" +#endif +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +extern void (* const g_pfnVectors[])(void); +extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); + +__attribute__ ((used, section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = { + // Core Level - CM7 + &_vStackTop, // The initial stack pointer + ResetISR, // The reset handler + NMI_Handler, // The NMI handler + HardFault_Handler, // The hard fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall handler + 0, // Reserved + 0, // Reserved + PendSV_Handler, // The PendSV handler + SysTick_Handler, // The SysTick handler + + // Chip Level - MIMXRT1061 + DMA0_DMA16_IRQHandler, // 16 : DMA channel 0/16 transfer complete + DMA1_DMA17_IRQHandler, // 17 : DMA channel 1/17 transfer complete + DMA2_DMA18_IRQHandler, // 18 : DMA channel 2/18 transfer complete + DMA3_DMA19_IRQHandler, // 19 : DMA channel 3/19 transfer complete + DMA4_DMA20_IRQHandler, // 20 : DMA channel 4/20 transfer complete + DMA5_DMA21_IRQHandler, // 21 : DMA channel 5/21 transfer complete + DMA6_DMA22_IRQHandler, // 22 : DMA channel 6/22 transfer complete + DMA7_DMA23_IRQHandler, // 23 : DMA channel 7/23 transfer complete + DMA8_DMA24_IRQHandler, // 24 : DMA channel 8/24 transfer complete + DMA9_DMA25_IRQHandler, // 25 : DMA channel 9/25 transfer complete + DMA10_DMA26_IRQHandler, // 26 : DMA channel 10/26 transfer complete + DMA11_DMA27_IRQHandler, // 27 : DMA channel 11/27 transfer complete + DMA12_DMA28_IRQHandler, // 28 : DMA channel 12/28 transfer complete + DMA13_DMA29_IRQHandler, // 29 : DMA channel 13/29 transfer complete + DMA14_DMA30_IRQHandler, // 30 : DMA channel 14/30 transfer complete + DMA15_DMA31_IRQHandler, // 31 : DMA channel 15/31 transfer complete + DMA_ERROR_IRQHandler, // 32 : DMA error interrupt channels 0-15 / 16-31 + CTI0_ERROR_IRQHandler, // 33 : CTI0_Error + CTI1_ERROR_IRQHandler, // 34 : CTI1_Error + CORE_IRQHandler, // 35 : CorePlatform exception IRQ + LPUART1_IRQHandler, // 36 : LPUART1 TX interrupt and RX interrupt + LPUART2_IRQHandler, // 37 : LPUART2 TX interrupt and RX interrupt + LPUART3_IRQHandler, // 38 : LPUART3 TX interrupt and RX interrupt + LPUART4_IRQHandler, // 39 : LPUART4 TX interrupt and RX interrupt + LPUART5_IRQHandler, // 40 : LPUART5 TX interrupt and RX interrupt + LPUART6_IRQHandler, // 41 : LPUART6 TX interrupt and RX interrupt + LPUART7_IRQHandler, // 42 : LPUART7 TX interrupt and RX interrupt + LPUART8_IRQHandler, // 43 : LPUART8 TX interrupt and RX interrupt + LPI2C1_IRQHandler, // 44 : LPI2C1 interrupt + LPI2C2_IRQHandler, // 45 : LPI2C2 interrupt + LPI2C3_IRQHandler, // 46 : LPI2C3 interrupt + LPI2C4_IRQHandler, // 47 : LPI2C4 interrupt + LPSPI1_IRQHandler, // 48 : LPSPI1 single interrupt vector for all sources + LPSPI2_IRQHandler, // 49 : LPSPI2 single interrupt vector for all sources + LPSPI3_IRQHandler, // 50 : LPSPI3 single interrupt vector for all sources + LPSPI4_IRQHandler, // 51 : LPSPI4 single interrupt vector for all sources + CAN1_IRQHandler, // 52 : CAN1 interrupt + CAN2_IRQHandler, // 53 : CAN2 interrupt + FLEXRAM_IRQHandler, // 54 : FlexRAM address out of range Or access hit IRQ + KPP_IRQHandler, // 55 : Keypad nterrupt + TSC_DIG_IRQHandler, // 56 : TSC interrupt + GPR_IRQ_IRQHandler, // 57 : GPR interrupt + Reserved58_IRQHandler, // 58 : Reserved interrupt + Reserved59_IRQHandler, // 59 : Reserved interrupt + Reserved60_IRQHandler, // 60 : Reserved interrupt + WDOG2_IRQHandler, // 61 : WDOG2 interrupt + SNVS_HP_WRAPPER_IRQHandler, // 62 : SRTC Consolidated Interrupt. Non TZ + SNVS_HP_WRAPPER_TZ_IRQHandler, // 63 : SRTC Security Interrupt. TZ + SNVS_LP_WRAPPER_IRQHandler, // 64 : ON-OFF button press shorter than 5 secs (pulse event) + CSU_IRQHandler, // 65 : CSU interrupt + DCP_IRQHandler, // 66 : DCP_IRQ interrupt + DCP_VMI_IRQHandler, // 67 : DCP_VMI_IRQ interrupt + Reserved68_IRQHandler, // 68 : Reserved interrupt + TRNG_IRQHandler, // 69 : TRNG interrupt + SJC_IRQHandler, // 70 : SJC interrupt + BEE_IRQHandler, // 71 : BEE interrupt + SAI1_IRQHandler, // 72 : SAI1 interrupt + SAI2_IRQHandler, // 73 : SAI1 interrupt + SAI3_RX_IRQHandler, // 74 : SAI3 interrupt + SAI3_TX_IRQHandler, // 75 : SAI3 interrupt + SPDIF_IRQHandler, // 76 : SPDIF interrupt + PMU_EVENT_IRQHandler, // 77 : Brown-out event interrupt + Reserved78_IRQHandler, // 78 : Reserved interrupt + TEMP_LOW_HIGH_IRQHandler, // 79 : TempSensor low/high interrupt + TEMP_PANIC_IRQHandler, // 80 : TempSensor panic interrupt + USB_PHY1_IRQHandler, // 81 : USBPHY (UTMI0), Interrupt + USB_PHY2_IRQHandler, // 82 : USBPHY (UTMI1), Interrupt + ADC1_IRQHandler, // 83 : ADC1 interrupt + ADC2_IRQHandler, // 84 : ADC2 interrupt + DCDC_IRQHandler, // 85 : DCDC interrupt + Reserved86_IRQHandler, // 86 : Reserved interrupt + Reserved87_IRQHandler, // 87 : Reserved interrupt + GPIO1_INT0_IRQHandler, // 88 : Active HIGH Interrupt from INT0 from GPIO + GPIO1_INT1_IRQHandler, // 89 : Active HIGH Interrupt from INT1 from GPIO + GPIO1_INT2_IRQHandler, // 90 : Active HIGH Interrupt from INT2 from GPIO + GPIO1_INT3_IRQHandler, // 91 : Active HIGH Interrupt from INT3 from GPIO + GPIO1_INT4_IRQHandler, // 92 : Active HIGH Interrupt from INT4 from GPIO + GPIO1_INT5_IRQHandler, // 93 : Active HIGH Interrupt from INT5 from GPIO + GPIO1_INT6_IRQHandler, // 94 : Active HIGH Interrupt from INT6 from GPIO + GPIO1_INT7_IRQHandler, // 95 : Active HIGH Interrupt from INT7 from GPIO + GPIO1_Combined_0_15_IRQHandler, // 96 : Combined interrupt indication for GPIO1 signal 0 throughout 15 + GPIO1_Combined_16_31_IRQHandler, // 97 : Combined interrupt indication for GPIO1 signal 16 throughout 31 + GPIO2_Combined_0_15_IRQHandler, // 98 : Combined interrupt indication for GPIO2 signal 0 throughout 15 + GPIO2_Combined_16_31_IRQHandler, // 99 : Combined interrupt indication for GPIO2 signal 16 throughout 31 + GPIO3_Combined_0_15_IRQHandler, // 100: Combined interrupt indication for GPIO3 signal 0 throughout 15 + GPIO3_Combined_16_31_IRQHandler, // 101: Combined interrupt indication for GPIO3 signal 16 throughout 31 + GPIO4_Combined_0_15_IRQHandler, // 102: Combined interrupt indication for GPIO4 signal 0 throughout 15 + GPIO4_Combined_16_31_IRQHandler, // 103: Combined interrupt indication for GPIO4 signal 16 throughout 31 + GPIO5_Combined_0_15_IRQHandler, // 104: Combined interrupt indication for GPIO5 signal 0 throughout 15 + GPIO5_Combined_16_31_IRQHandler, // 105: Combined interrupt indication for GPIO5 signal 16 throughout 31 + FLEXIO1_IRQHandler, // 106: FLEXIO1 interrupt + FLEXIO2_IRQHandler, // 107: FLEXIO2 interrupt + WDOG1_IRQHandler, // 108: WDOG1 interrupt + RTWDOG_IRQHandler, // 109: RTWDOG interrupt + EWM_IRQHandler, // 110: EWM interrupt + CCM_1_IRQHandler, // 111: CCM IRQ1 interrupt + CCM_2_IRQHandler, // 112: CCM IRQ2 interrupt + GPC_IRQHandler, // 113: GPC interrupt + SRC_IRQHandler, // 114: SRC interrupt + Reserved115_IRQHandler, // 115: Reserved interrupt + GPT1_IRQHandler, // 116: GPT1 interrupt + GPT2_IRQHandler, // 117: GPT2 interrupt + PWM1_0_IRQHandler, // 118: PWM1 capture 0, compare 0, or reload 0 interrupt + PWM1_1_IRQHandler, // 119: PWM1 capture 1, compare 1, or reload 0 interrupt + PWM1_2_IRQHandler, // 120: PWM1 capture 2, compare 2, or reload 0 interrupt + PWM1_3_IRQHandler, // 121: PWM1 capture 3, compare 3, or reload 0 interrupt + PWM1_FAULT_IRQHandler, // 122: PWM1 fault or reload error interrupt + FLEXSPI2_IRQHandler, // 123: FlexSPI2 interrupt + FLEXSPI_IRQHandler, // 124: FlexSPI0 interrupt + SEMC_IRQHandler, // 125: Reserved interrupt + USDHC1_IRQHandler, // 126: USDHC1 interrupt + USDHC2_IRQHandler, // 127: USDHC2 interrupt + USB_OTG2_IRQHandler, // 128: USBO2 USB OTG2 + USB_OTG1_IRQHandler, // 129: USBO2 USB OTG1 + ENET_IRQHandler, // 130: ENET interrupt + ENET_1588_Timer_IRQHandler, // 131: ENET_1588_Timer interrupt + XBAR1_IRQ_0_1_IRQHandler, // 132: XBAR1 interrupt + XBAR1_IRQ_2_3_IRQHandler, // 133: XBAR1 interrupt + ADC_ETC_IRQ0_IRQHandler, // 134: ADCETC IRQ0 interrupt + ADC_ETC_IRQ1_IRQHandler, // 135: ADCETC IRQ1 interrupt + ADC_ETC_IRQ2_IRQHandler, // 136: ADCETC IRQ2 interrupt + ADC_ETC_ERROR_IRQ_IRQHandler, // 137: ADCETC Error IRQ interrupt + PIT_IRQHandler, // 138: PIT interrupt + ACMP1_IRQHandler, // 139: ACMP interrupt + ACMP2_IRQHandler, // 140: ACMP interrupt + ACMP3_IRQHandler, // 141: ACMP interrupt + ACMP4_IRQHandler, // 142: ACMP interrupt + Reserved143_IRQHandler, // 143: Reserved interrupt + Reserved144_IRQHandler, // 144: Reserved interrupt + ENC1_IRQHandler, // 145: ENC1 interrupt + ENC2_IRQHandler, // 146: ENC2 interrupt + ENC3_IRQHandler, // 147: ENC3 interrupt + ENC4_IRQHandler, // 148: ENC4 interrupt + TMR1_IRQHandler, // 149: TMR1 interrupt + TMR2_IRQHandler, // 150: TMR2 interrupt + TMR3_IRQHandler, // 151: TMR3 interrupt + TMR4_IRQHandler, // 152: TMR4 interrupt + PWM2_0_IRQHandler, // 153: PWM2 capture 0, compare 0, or reload 0 interrupt + PWM2_1_IRQHandler, // 154: PWM2 capture 1, compare 1, or reload 0 interrupt + PWM2_2_IRQHandler, // 155: PWM2 capture 2, compare 2, or reload 0 interrupt + PWM2_3_IRQHandler, // 156: PWM2 capture 3, compare 3, or reload 0 interrupt + PWM2_FAULT_IRQHandler, // 157: PWM2 fault or reload error interrupt + PWM3_0_IRQHandler, // 158: PWM3 capture 0, compare 0, or reload 0 interrupt + PWM3_1_IRQHandler, // 159: PWM3 capture 1, compare 1, or reload 0 interrupt + PWM3_2_IRQHandler, // 160: PWM3 capture 2, compare 2, or reload 0 interrupt + PWM3_3_IRQHandler, // 161: PWM3 capture 3, compare 3, or reload 0 interrupt + PWM3_FAULT_IRQHandler, // 162: PWM3 fault or reload error interrupt + PWM4_0_IRQHandler, // 163: PWM4 capture 0, compare 0, or reload 0 interrupt + PWM4_1_IRQHandler, // 164: PWM4 capture 1, compare 1, or reload 0 interrupt + PWM4_2_IRQHandler, // 165: PWM4 capture 2, compare 2, or reload 0 interrupt + PWM4_3_IRQHandler, // 166: PWM4 capture 3, compare 3, or reload 0 interrupt + PWM4_FAULT_IRQHandler, // 167: PWM4 fault or reload error interrupt + ENET2_IRQHandler, // 168: ENET2 interrupt + ENET2_1588_Timer_IRQHandler, // 169: ENET2_1588_Timer interrupt + CAN3_IRQHandler, // 170: CAN3 interrupt + Reserved171_IRQHandler, // 171: Reserved interrupt + FLEXIO3_IRQHandler, // 172: FLEXIO3 interrupt + GPIO6_7_8_9_IRQHandler, // 173: GPIO6, GPIO7, GPIO8, GPIO9 interrupt + +}; /* End of g_pfnVectors */ + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__ ((section(".after_vectors.init_data"))) +void data_init(unsigned int romstart, unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int *pulSrc = (unsigned int*) romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__ ((section(".after_vectors.init_bss"))) +void bss_init(unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +__attribute__ ((section(".after_vectors.reset"))) +void ResetISR(void) { + + // Disable interrupts + __asm volatile ("cpsid i"); + + +#if defined (__USE_CMSIS) +// If __USE_CMSIS defined, then call CMSIS SystemInit code + SystemInit(); +#else + // Disable Watchdog + volatile unsigned int *WDOG1_WCR = (unsigned int *) 0x400B8000; + *WDOG1_WCR = *WDOG1_WCR & ~(1 << 2); + volatile unsigned int *WDOG2_WCR = (unsigned int *) 0x400D0000; + *WDOG2_WCR = *WDOG2_WCR & ~(1 << 2); + // Write watchdog update key to unlock + *((volatile unsigned int *)0x400BC004) = 0xD928C520; + // Set timeout value + *((volatile unsigned int *)0x400BC008) = 0xFFFF; + // Now disable watchdog via control register + volatile unsigned int *RTWDOG_CS = (unsigned int *) 0x400BC000; + *RTWDOG_CS = (*RTWDOG_CS & ~(1 << 7)) | (1 << 5); + +#endif // (__USE_CMSIS) + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + + +#if !defined (__USE_CMSIS) +// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code +// will setup the VTOR register + + // Check to see if we are running the code from a non-zero + // address (eg RAM, external flash), in which case we need + // to modify the VTOR register to tell the CPU that the + // vector table is located at a non-0x0 address. + unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; + if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) { + *pSCB_VTOR = (unsigned int)g_pfnVectors; + } +#endif // (__USE_CMSIS) +#if defined (__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif + + // Reenable interrupts + __asm volatile ("cpsie i"); + +#if defined (__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // + while (1) { + ; + } +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ while(1) {} +} + +WEAK_AV void HardFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SVC_Handler(void) +{ while(1) {} +} + +WEAK_AV void PendSV_Handler(void) +{ while(1) {} +} + +WEAK_AV void SysTick_Handler(void) +{ while(1) {} +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void IntDefaultHandler(void) +{ while(1) {} +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or IntDefaultHandler() if no driver exception +// handler is included. +//***************************************************************************** +WEAK void DMA0_DMA16_IRQHandler(void) +{ DMA0_DMA16_DriverIRQHandler(); +} + +WEAK void DMA1_DMA17_IRQHandler(void) +{ DMA1_DMA17_DriverIRQHandler(); +} + +WEAK void DMA2_DMA18_IRQHandler(void) +{ DMA2_DMA18_DriverIRQHandler(); +} + +WEAK void DMA3_DMA19_IRQHandler(void) +{ DMA3_DMA19_DriverIRQHandler(); +} + +WEAK void DMA4_DMA20_IRQHandler(void) +{ DMA4_DMA20_DriverIRQHandler(); +} + +WEAK void DMA5_DMA21_IRQHandler(void) +{ DMA5_DMA21_DriverIRQHandler(); +} + +WEAK void DMA6_DMA22_IRQHandler(void) +{ DMA6_DMA22_DriverIRQHandler(); +} + +WEAK void DMA7_DMA23_IRQHandler(void) +{ DMA7_DMA23_DriverIRQHandler(); +} + +WEAK void DMA8_DMA24_IRQHandler(void) +{ DMA8_DMA24_DriverIRQHandler(); +} + +WEAK void DMA9_DMA25_IRQHandler(void) +{ DMA9_DMA25_DriverIRQHandler(); +} + +WEAK void DMA10_DMA26_IRQHandler(void) +{ DMA10_DMA26_DriverIRQHandler(); +} + +WEAK void DMA11_DMA27_IRQHandler(void) +{ DMA11_DMA27_DriverIRQHandler(); +} + +WEAK void DMA12_DMA28_IRQHandler(void) +{ DMA12_DMA28_DriverIRQHandler(); +} + +WEAK void DMA13_DMA29_IRQHandler(void) +{ DMA13_DMA29_DriverIRQHandler(); +} + +WEAK void DMA14_DMA30_IRQHandler(void) +{ DMA14_DMA30_DriverIRQHandler(); +} + +WEAK void DMA15_DMA31_IRQHandler(void) +{ DMA15_DMA31_DriverIRQHandler(); +} + +WEAK void DMA_ERROR_IRQHandler(void) +{ DMA_ERROR_DriverIRQHandler(); +} + +WEAK void CTI0_ERROR_IRQHandler(void) +{ CTI0_ERROR_DriverIRQHandler(); +} + +WEAK void CTI1_ERROR_IRQHandler(void) +{ CTI1_ERROR_DriverIRQHandler(); +} + +WEAK void CORE_IRQHandler(void) +{ CORE_DriverIRQHandler(); +} + +WEAK void LPUART1_IRQHandler(void) +{ LPUART1_DriverIRQHandler(); +} + +WEAK void LPUART2_IRQHandler(void) +{ LPUART2_DriverIRQHandler(); +} + +WEAK void LPUART3_IRQHandler(void) +{ LPUART3_DriverIRQHandler(); +} + +WEAK void LPUART4_IRQHandler(void) +{ LPUART4_DriverIRQHandler(); +} + +WEAK void LPUART5_IRQHandler(void) +{ LPUART5_DriverIRQHandler(); +} + +WEAK void LPUART6_IRQHandler(void) +{ LPUART6_DriverIRQHandler(); +} + +WEAK void LPUART7_IRQHandler(void) +{ LPUART7_DriverIRQHandler(); +} + +WEAK void LPUART8_IRQHandler(void) +{ LPUART8_DriverIRQHandler(); +} + +WEAK void LPI2C1_IRQHandler(void) +{ LPI2C1_DriverIRQHandler(); +} + +WEAK void LPI2C2_IRQHandler(void) +{ LPI2C2_DriverIRQHandler(); +} + +WEAK void LPI2C3_IRQHandler(void) +{ LPI2C3_DriverIRQHandler(); +} + +WEAK void LPI2C4_IRQHandler(void) +{ LPI2C4_DriverIRQHandler(); +} + +WEAK void LPSPI1_IRQHandler(void) +{ LPSPI1_DriverIRQHandler(); +} + +WEAK void LPSPI2_IRQHandler(void) +{ LPSPI2_DriverIRQHandler(); +} + +WEAK void LPSPI3_IRQHandler(void) +{ LPSPI3_DriverIRQHandler(); +} + +WEAK void LPSPI4_IRQHandler(void) +{ LPSPI4_DriverIRQHandler(); +} + +WEAK void CAN1_IRQHandler(void) +{ CAN1_DriverIRQHandler(); +} + +WEAK void CAN2_IRQHandler(void) +{ CAN2_DriverIRQHandler(); +} + +WEAK void FLEXRAM_IRQHandler(void) +{ FLEXRAM_DriverIRQHandler(); +} + +WEAK void KPP_IRQHandler(void) +{ KPP_DriverIRQHandler(); +} + +WEAK void TSC_DIG_IRQHandler(void) +{ TSC_DIG_DriverIRQHandler(); +} + +WEAK void GPR_IRQ_IRQHandler(void) +{ GPR_IRQ_DriverIRQHandler(); +} + +WEAK void Reserved58_IRQHandler(void) +{ Reserved58_DriverIRQHandler(); +} + +WEAK void Reserved59_IRQHandler(void) +{ Reserved59_DriverIRQHandler(); +} + +WEAK void Reserved60_IRQHandler(void) +{ Reserved60_DriverIRQHandler(); +} + +WEAK void WDOG2_IRQHandler(void) +{ WDOG2_DriverIRQHandler(); +} + +WEAK void SNVS_HP_WRAPPER_IRQHandler(void) +{ SNVS_HP_WRAPPER_DriverIRQHandler(); +} + +WEAK void SNVS_HP_WRAPPER_TZ_IRQHandler(void) +{ SNVS_HP_WRAPPER_TZ_DriverIRQHandler(); +} + +WEAK void SNVS_LP_WRAPPER_IRQHandler(void) +{ SNVS_LP_WRAPPER_DriverIRQHandler(); +} + +WEAK void CSU_IRQHandler(void) +{ CSU_DriverIRQHandler(); +} + +WEAK void DCP_IRQHandler(void) +{ DCP_DriverIRQHandler(); +} + +WEAK void DCP_VMI_IRQHandler(void) +{ DCP_VMI_DriverIRQHandler(); +} + +WEAK void Reserved68_IRQHandler(void) +{ Reserved68_DriverIRQHandler(); +} + +WEAK void TRNG_IRQHandler(void) +{ TRNG_DriverIRQHandler(); +} + +WEAK void SJC_IRQHandler(void) +{ SJC_DriverIRQHandler(); +} + +WEAK void BEE_IRQHandler(void) +{ BEE_DriverIRQHandler(); +} + +WEAK void SAI1_IRQHandler(void) +{ SAI1_DriverIRQHandler(); +} + +WEAK void SAI2_IRQHandler(void) +{ SAI2_DriverIRQHandler(); +} + +WEAK void SAI3_RX_IRQHandler(void) +{ SAI3_RX_DriverIRQHandler(); +} + +WEAK void SAI3_TX_IRQHandler(void) +{ SAI3_TX_DriverIRQHandler(); +} + +WEAK void SPDIF_IRQHandler(void) +{ SPDIF_DriverIRQHandler(); +} + +WEAK void PMU_EVENT_IRQHandler(void) +{ PMU_EVENT_DriverIRQHandler(); +} + +WEAK void Reserved78_IRQHandler(void) +{ Reserved78_DriverIRQHandler(); +} + +WEAK void TEMP_LOW_HIGH_IRQHandler(void) +{ TEMP_LOW_HIGH_DriverIRQHandler(); +} + +WEAK void TEMP_PANIC_IRQHandler(void) +{ TEMP_PANIC_DriverIRQHandler(); +} + +WEAK void USB_PHY1_IRQHandler(void) +{ USB_PHY1_DriverIRQHandler(); +} + +WEAK void USB_PHY2_IRQHandler(void) +{ USB_PHY2_DriverIRQHandler(); +} + +WEAK void ADC1_IRQHandler(void) +{ ADC1_DriverIRQHandler(); +} + +WEAK void ADC2_IRQHandler(void) +{ ADC2_DriverIRQHandler(); +} + +WEAK void DCDC_IRQHandler(void) +{ DCDC_DriverIRQHandler(); +} + +WEAK void Reserved86_IRQHandler(void) +{ Reserved86_DriverIRQHandler(); +} + +WEAK void Reserved87_IRQHandler(void) +{ Reserved87_DriverIRQHandler(); +} + +WEAK void GPIO1_INT0_IRQHandler(void) +{ GPIO1_INT0_DriverIRQHandler(); +} + +WEAK void GPIO1_INT1_IRQHandler(void) +{ GPIO1_INT1_DriverIRQHandler(); +} + +WEAK void GPIO1_INT2_IRQHandler(void) +{ GPIO1_INT2_DriverIRQHandler(); +} + +WEAK void GPIO1_INT3_IRQHandler(void) +{ GPIO1_INT3_DriverIRQHandler(); +} + +WEAK void GPIO1_INT4_IRQHandler(void) +{ GPIO1_INT4_DriverIRQHandler(); +} + +WEAK void GPIO1_INT5_IRQHandler(void) +{ GPIO1_INT5_DriverIRQHandler(); +} + +WEAK void GPIO1_INT6_IRQHandler(void) +{ GPIO1_INT6_DriverIRQHandler(); +} + +WEAK void GPIO1_INT7_IRQHandler(void) +{ GPIO1_INT7_DriverIRQHandler(); +} + +WEAK void GPIO1_Combined_0_15_IRQHandler(void) +{ GPIO1_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO1_Combined_16_31_IRQHandler(void) +{ GPIO1_Combined_16_31_DriverIRQHandler(); +} + +WEAK void GPIO2_Combined_0_15_IRQHandler(void) +{ GPIO2_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO2_Combined_16_31_IRQHandler(void) +{ GPIO2_Combined_16_31_DriverIRQHandler(); +} + +WEAK void GPIO3_Combined_0_15_IRQHandler(void) +{ GPIO3_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO3_Combined_16_31_IRQHandler(void) +{ GPIO3_Combined_16_31_DriverIRQHandler(); +} + +WEAK void GPIO4_Combined_0_15_IRQHandler(void) +{ GPIO4_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO4_Combined_16_31_IRQHandler(void) +{ GPIO4_Combined_16_31_DriverIRQHandler(); +} + +WEAK void GPIO5_Combined_0_15_IRQHandler(void) +{ GPIO5_Combined_0_15_DriverIRQHandler(); +} + +WEAK void GPIO5_Combined_16_31_IRQHandler(void) +{ GPIO5_Combined_16_31_DriverIRQHandler(); +} + +WEAK void FLEXIO1_IRQHandler(void) +{ FLEXIO1_DriverIRQHandler(); +} + +WEAK void FLEXIO2_IRQHandler(void) +{ FLEXIO2_DriverIRQHandler(); +} + +WEAK void WDOG1_IRQHandler(void) +{ WDOG1_DriverIRQHandler(); +} + +WEAK void RTWDOG_IRQHandler(void) +{ RTWDOG_DriverIRQHandler(); +} + +WEAK void EWM_IRQHandler(void) +{ EWM_DriverIRQHandler(); +} + +WEAK void CCM_1_IRQHandler(void) +{ CCM_1_DriverIRQHandler(); +} + +WEAK void CCM_2_IRQHandler(void) +{ CCM_2_DriverIRQHandler(); +} + +WEAK void GPC_IRQHandler(void) +{ GPC_DriverIRQHandler(); +} + +WEAK void SRC_IRQHandler(void) +{ SRC_DriverIRQHandler(); +} + +WEAK void Reserved115_IRQHandler(void) +{ Reserved115_DriverIRQHandler(); +} + +WEAK void GPT1_IRQHandler(void) +{ GPT1_DriverIRQHandler(); +} + +WEAK void GPT2_IRQHandler(void) +{ GPT2_DriverIRQHandler(); +} + +WEAK void PWM1_0_IRQHandler(void) +{ PWM1_0_DriverIRQHandler(); +} + +WEAK void PWM1_1_IRQHandler(void) +{ PWM1_1_DriverIRQHandler(); +} + +WEAK void PWM1_2_IRQHandler(void) +{ PWM1_2_DriverIRQHandler(); +} + +WEAK void PWM1_3_IRQHandler(void) +{ PWM1_3_DriverIRQHandler(); +} + +WEAK void PWM1_FAULT_IRQHandler(void) +{ PWM1_FAULT_DriverIRQHandler(); +} + +WEAK void FLEXSPI2_IRQHandler(void) +{ FLEXSPI2_DriverIRQHandler(); +} + +WEAK void FLEXSPI_IRQHandler(void) +{ FLEXSPI_DriverIRQHandler(); +} + +WEAK void SEMC_IRQHandler(void) +{ SEMC_DriverIRQHandler(); +} + +WEAK void USDHC1_IRQHandler(void) +{ USDHC1_DriverIRQHandler(); +} + +WEAK void USDHC2_IRQHandler(void) +{ USDHC2_DriverIRQHandler(); +} + +WEAK void USB_OTG2_IRQHandler(void) +{ USB_OTG2_DriverIRQHandler(); +} + +WEAK void USB_OTG1_IRQHandler(void) +{ USB_OTG1_DriverIRQHandler(); +} + +WEAK void ENET_IRQHandler(void) +{ ENET_DriverIRQHandler(); +} + +WEAK void ENET_1588_Timer_IRQHandler(void) +{ ENET_1588_Timer_DriverIRQHandler(); +} + +WEAK void XBAR1_IRQ_0_1_IRQHandler(void) +{ XBAR1_IRQ_0_1_DriverIRQHandler(); +} + +WEAK void XBAR1_IRQ_2_3_IRQHandler(void) +{ XBAR1_IRQ_2_3_DriverIRQHandler(); +} + +WEAK void ADC_ETC_IRQ0_IRQHandler(void) +{ ADC_ETC_IRQ0_DriverIRQHandler(); +} + +WEAK void ADC_ETC_IRQ1_IRQHandler(void) +{ ADC_ETC_IRQ1_DriverIRQHandler(); +} + +WEAK void ADC_ETC_IRQ2_IRQHandler(void) +{ ADC_ETC_IRQ2_DriverIRQHandler(); +} + +WEAK void ADC_ETC_ERROR_IRQ_IRQHandler(void) +{ ADC_ETC_ERROR_IRQ_DriverIRQHandler(); +} + +WEAK void PIT_IRQHandler(void) +{ PIT_DriverIRQHandler(); +} + +WEAK void ACMP1_IRQHandler(void) +{ ACMP1_DriverIRQHandler(); +} + +WEAK void ACMP2_IRQHandler(void) +{ ACMP2_DriverIRQHandler(); +} + +WEAK void ACMP3_IRQHandler(void) +{ ACMP3_DriverIRQHandler(); +} + +WEAK void ACMP4_IRQHandler(void) +{ ACMP4_DriverIRQHandler(); +} + +WEAK void Reserved143_IRQHandler(void) +{ Reserved143_DriverIRQHandler(); +} + +WEAK void Reserved144_IRQHandler(void) +{ Reserved144_DriverIRQHandler(); +} + +WEAK void ENC1_IRQHandler(void) +{ ENC1_DriverIRQHandler(); +} + +WEAK void ENC2_IRQHandler(void) +{ ENC2_DriverIRQHandler(); +} + +WEAK void ENC3_IRQHandler(void) +{ ENC3_DriverIRQHandler(); +} + +WEAK void ENC4_IRQHandler(void) +{ ENC4_DriverIRQHandler(); +} + +WEAK void TMR1_IRQHandler(void) +{ TMR1_DriverIRQHandler(); +} + +WEAK void TMR2_IRQHandler(void) +{ TMR2_DriverIRQHandler(); +} + +WEAK void TMR3_IRQHandler(void) +{ TMR3_DriverIRQHandler(); +} + +WEAK void TMR4_IRQHandler(void) +{ TMR4_DriverIRQHandler(); +} + +WEAK void PWM2_0_IRQHandler(void) +{ PWM2_0_DriverIRQHandler(); +} + +WEAK void PWM2_1_IRQHandler(void) +{ PWM2_1_DriverIRQHandler(); +} + +WEAK void PWM2_2_IRQHandler(void) +{ PWM2_2_DriverIRQHandler(); +} + +WEAK void PWM2_3_IRQHandler(void) +{ PWM2_3_DriverIRQHandler(); +} + +WEAK void PWM2_FAULT_IRQHandler(void) +{ PWM2_FAULT_DriverIRQHandler(); +} + +WEAK void PWM3_0_IRQHandler(void) +{ PWM3_0_DriverIRQHandler(); +} + +WEAK void PWM3_1_IRQHandler(void) +{ PWM3_1_DriverIRQHandler(); +} + +WEAK void PWM3_2_IRQHandler(void) +{ PWM3_2_DriverIRQHandler(); +} + +WEAK void PWM3_3_IRQHandler(void) +{ PWM3_3_DriverIRQHandler(); +} + +WEAK void PWM3_FAULT_IRQHandler(void) +{ PWM3_FAULT_DriverIRQHandler(); +} + +WEAK void PWM4_0_IRQHandler(void) +{ PWM4_0_DriverIRQHandler(); +} + +WEAK void PWM4_1_IRQHandler(void) +{ PWM4_1_DriverIRQHandler(); +} + +WEAK void PWM4_2_IRQHandler(void) +{ PWM4_2_DriverIRQHandler(); +} + +WEAK void PWM4_3_IRQHandler(void) +{ PWM4_3_DriverIRQHandler(); +} + +WEAK void PWM4_FAULT_IRQHandler(void) +{ PWM4_FAULT_DriverIRQHandler(); +} + +WEAK void ENET2_IRQHandler(void) +{ ENET2_DriverIRQHandler(); +} + +WEAK void ENET2_1588_Timer_IRQHandler(void) +{ ENET2_1588_Timer_DriverIRQHandler(); +} + +WEAK void CAN3_IRQHandler(void) +{ CAN3_DriverIRQHandler(); +} + +WEAK void Reserved171_IRQHandler(void) +{ Reserved171_DriverIRQHandler(); +} + +WEAK void FLEXIO3_IRQHandler(void) +{ FLEXIO3_DriverIRQHandler(); +} + +WEAK void GPIO6_7_8_9_IRQHandler(void) +{ GPIO6_7_8_9_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC pop_options +#endif // (DEBUG) diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/board.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/board.c new file mode 100644 index 0000000000..efbf55c5db --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/board.c @@ -0,0 +1,452 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "board.h" +#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED +#include "fsl_lpi2c.h" +#endif /* SDK_I2C_BASED_COMPONENT_USED */ +#if defined BOARD_USE_CODEC +#include "fsl_wm8960.h" +#endif +#include "fsl_iomuxc.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if defined BOARD_USE_CODEC +codec_config_t boardCodecConfig = {.I2C_SendFunc = BOARD_Codec_I2C_Send, + .I2C_ReceiveFunc = BOARD_Codec_I2C_Receive, + .op.Init = WM8960_Init, + .op.Deinit = WM8960_Deinit, + .op.SetFormat = WM8960_ConfigDataFormat}; +#endif +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Get debug console frequency. */ +uint32_t BOARD_DebugConsoleSrcFreq(void) +{ + uint32_t freq; + + /* To make it simple, we assume default PLL and divider settings, and the only variable + from application is use PLL3 source or OSC source */ + if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ + { + freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); + } + else + { + freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U); + } + + return freq; +} + +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq(); + + DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} + +#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED +void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz) +{ + lpi2c_master_config_t lpi2cConfig = {0}; + + /* + * lpi2cConfig.debugEnable = false; + * lpi2cConfig.ignoreAck = false; + * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain; + * lpi2cConfig.baudRate_Hz = 100000U; + * lpi2cConfig.busIdleTimeout_ns = 0; + * lpi2cConfig.pinLowTimeout_ns = 0; + * lpi2cConfig.sdaGlitchFilterWidth_ns = 0; + * lpi2cConfig.sclGlitchFilterWidth_ns = 0; + */ + LPI2C_MasterGetDefaultConfig(&lpi2cConfig); + LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz); +} + +status_t BOARD_LPI2C_Send(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *txBuff, + uint8_t txBuffSize) +{ + status_t reVal; + + /* Send master blocking data to slave */ + reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write); + if (kStatus_Success == reVal) + { + while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag) + { + } + + reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize); + if (reVal != kStatus_Success) + { + return reVal; + } + + reVal = LPI2C_MasterSend(base, txBuff, txBuffSize); + if (reVal != kStatus_Success) + { + return reVal; + } + + reVal = LPI2C_MasterStop(base); + if (reVal != kStatus_Success) + { + return reVal; + } + } + + return reVal; +} + +status_t BOARD_LPI2C_Receive(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *rxBuff, + uint8_t rxBuffSize) +{ + status_t reVal; + + reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write); + if (kStatus_Success == reVal) + { + while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag) + { + } + + reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize); + if (reVal != kStatus_Success) + { + return reVal; + } + + reVal = LPI2C_MasterRepeatedStart(base, deviceAddress, kLPI2C_Read); + + if (reVal != kStatus_Success) + { + return reVal; + } + + reVal = LPI2C_MasterReceive(base, rxBuff, rxBuffSize); + if (reVal != kStatus_Success) + { + return reVal; + } + + reVal = LPI2C_MasterStop(base); + if (reVal != kStatus_Success) + { + return reVal; + } + } + return reVal; +} + +status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *txBuff, + uint8_t txBuffSize) +{ + return BOARD_LPI2C_Send(base, deviceAddress, subAddress, subAddressSize, txBuff, txBuffSize); +} + +status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subAddressSize, + uint8_t *rxBuff, + uint8_t rxBuffSize) +{ + status_t reVal; + + reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write); + if (kStatus_Success == reVal) + { + while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag) + { + } + + reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize); + if (reVal != kStatus_Success) + { + return reVal; + } + + /* SCCB does not support LPI2C repeat start, must stop then start. */ + reVal = LPI2C_MasterStop(base); + + if (reVal != kStatus_Success) + { + return reVal; + } + + reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Read); + + if (reVal != kStatus_Success) + { + return reVal; + } + + reVal = LPI2C_MasterReceive(base, rxBuff, rxBuffSize); + if (reVal != kStatus_Success) + { + return reVal; + } + + reVal = LPI2C_MasterStop(base); + if (reVal != kStatus_Success) + { + return reVal; + } + } + return reVal; +} + +void BOARD_Accel_I2C_Init(void) +{ + BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ); +} + +status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff) +{ + uint8_t data = (uint8_t)txBuff; + + return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1); +} + +status_t BOARD_Accel_I2C_Receive( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) +{ + return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize); +} + +void BOARD_Codec_I2C_Init(void) +{ + BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ); +} + +status_t BOARD_Codec_I2C_Send( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize) +{ + return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, + txBuffSize); +} + +status_t BOARD_Codec_I2C_Receive( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) +{ + return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize); +} + +void BOARD_Camera_I2C_Init(void) +{ + CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT); + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER); + BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ); +} + +status_t BOARD_Camera_I2C_Send( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize) +{ + return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, + txBuffSize); +} + +status_t BOARD_Camera_I2C_Receive( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) +{ + return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, + rxBuffSize); +} + +status_t BOARD_Camera_I2C_SendSCCB( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize) +{ + return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff, + txBuffSize); +} + +status_t BOARD_Camera_I2C_ReceiveSCCB( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize) +{ + return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, + rxBuffSize); +} +#endif /* SDK_I2C_BASED_COMPONENT_USED */ + +/* MPU configuration. */ +void BOARD_ConfigMPU(void) +{ + /* Disable I cache and D cache */ + if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) + { + SCB_DisableICache(); + } + if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) + { + SCB_DisableDCache(); + } + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* MPU configure: + * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, + * SubRegionDisable, Size) + * API in core_cm7.h. + * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches + * disabled. + * param AccessPermission Data access permissions, allows you to configure read/write access for User and + * Privileged mode. + * Use MACROS defined in core_cm7.h: + * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO + * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. + * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache + * 0 x 0 0 Strongly Ordered shareable + * 0 x 0 1 Device shareable + * 0 0 1 0 Normal not shareable Outer and inner write + * through no write allocate + * 0 0 1 1 Normal not shareable Outer and inner write + * back no write allocate + * 0 1 1 0 Normal shareable Outer and inner write + * through no write allocate + * 0 1 1 1 Normal shareable Outer and inner write + * back no write allocate + * 1 0 0 0 Normal not shareable outer and inner + * noncache + * 1 1 0 0 Normal shareable outer and inner + * noncache + * 1 0 1 1 Normal not shareable outer and inner write + * back write/read acllocate + * 1 1 1 1 Normal shareable outer and inner write + * back write/read acllocate + * 2 x 0 0 Device not shareable + * Above are normal use settings, if your want to see more details or want to config different inner/outter cache + * policy. + * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide + * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. + * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in + * core_cm7.h. + */ + + /* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + +/* Region 2 setting */ +#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) + /* Setting Memory with Normal type, not shareable, outer/inner write back. */ + MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB); +#else + /* Setting Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_8MB); +#endif + + /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + + /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB); + + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB); + + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x20280000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + +/* The define sets the cacheable memory to shareable, + * this suggestion is referred from chapter 2.2.1 Memory regions, + * types and attributes in Cortex-M7 Devices, Generic User Guide */ +#if defined(SDRAM_IS_SHAREABLE) + /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); +#else + /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB); +#endif + + /* Region 9 setting, set last 2MB of SDRAM can't be accessed by cache, glocal variables which are not expected to be + * accessed by cache can be put here */ + /* Memory with Normal type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(9, 0x81E00000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk); + + /* Enable I cache and D cache */ + SCB_EnableDCache(); + SCB_EnableICache(); +} + +void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength) +{ + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, + IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | + IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, + IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) | + IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, + IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | + IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, + IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | + IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, + IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | + IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); + IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, + IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | + IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | + IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | + IOMUXC_SW_PAD_CTL_PAD_DSE(strength)); +} + +void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength) +{ +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/board.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/board.h new file mode 100644 index 0000000000..862b48eef3 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/board.h @@ -0,0 +1,271 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "clock_config.h" +#include "fsl_common.h" +#include "fsl_gpio.h" +#include "fsl_clock.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "MIMXRT1060-EVK" + +/* The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1 +#define BOARD_DEBUG_UART_INSTANCE 1U + +#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq() + +#define BOARD_UART_IRQ LPUART1_IRQn +#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler + +#ifndef BOARD_DEBUG_UART_BAUDRATE +#define BOARD_DEBUG_UART_BAUDRATE (115200U) +#endif /* BOARD_DEBUG_UART_BAUDRATE */ + +/*! @brief The USER_LED used for board */ +#define LOGIC_LED_ON (0U) +#define LOGIC_LED_OFF (1U) +#ifndef BOARD_USER_LED_GPIO +#define BOARD_USER_LED_GPIO GPIO1 +#endif +#ifndef BOARD_USER_LED_GPIO_PIN +#define BOARD_USER_LED_GPIO_PIN (9U) +#endif + +#define USER_LED_INIT(output) \ + GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \ + BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */ +#define USER_LED_ON() \ + GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */ +#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; + /* Use free 1MHz clock output. */ + XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; + /* Set XTAL 24MHz clock frequency. */ + CLOCK_SetXtalFreq(24000000U); + /* Enable XTAL 24MHz clock source. */ + CLOCK_InitExternalClk(0); + /* Enable internal RC. */ + CLOCK_InitRcOsc24M(); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); + /* Set Oscillator ready counter value. */ + CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); + /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) + { + } + /* Set AHB_PODF. */ + CLOCK_SetDiv(kCLOCK_AhbDiv, 0); + /* Disable IPG clock gate. */ + CLOCK_DisableClock(kCLOCK_Adc1); + CLOCK_DisableClock(kCLOCK_Adc2); + CLOCK_DisableClock(kCLOCK_Xbar1); + CLOCK_DisableClock(kCLOCK_Xbar2); + CLOCK_DisableClock(kCLOCK_Xbar3); + /* Set IPG_PODF. */ + CLOCK_SetDiv(kCLOCK_IpgDiv, 3); + /* Set ARM_PODF. */ + CLOCK_SetDiv(kCLOCK_ArmDiv, 1); + /* Set PERIPH_CLK2_PODF. */ + CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); + /* Disable PERCLK clock gate. */ + CLOCK_DisableClock(kCLOCK_Gpt1); + CLOCK_DisableClock(kCLOCK_Gpt1S); + CLOCK_DisableClock(kCLOCK_Gpt2); + CLOCK_DisableClock(kCLOCK_Gpt2S); + CLOCK_DisableClock(kCLOCK_Pit); + /* Set PERCLK_PODF. */ + CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); + /* Disable USDHC1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc1); + /* Set USDHC1_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); + /* Set Usdhc1 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); + /* Disable USDHC2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Usdhc2); + /* Set USDHC2_PODF. */ + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); + /* Set Usdhc2 clock source. */ + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left + * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as + * well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Disable Semc clock gate. */ + CLOCK_DisableClock(kCLOCK_Semc); + /* Set SEMC_PODF. */ + CLOCK_SetDiv(kCLOCK_SemcDiv, 7); + /* Set Semc alt clock source. */ + CLOCK_SetMux(kCLOCK_SemcAltMux, 0); + /* Set Semc clock source. */ + CLOCK_SetMux(kCLOCK_SemcMux, 0); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left + * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as + * well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Disable Flexspi clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi); + /* Set FLEXSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); + /* Set Flexspi clock source. */ + CLOCK_SetMux(kCLOCK_FlexspiMux, 3); +#endif + /* Disable Flexspi2 clock gate. */ + CLOCK_DisableClock(kCLOCK_FlexSpi2); + /* Set FLEXSPI2_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1); + /* Set Flexspi2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1); + /* Disable LPSPI clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpspi1); + CLOCK_DisableClock(kCLOCK_Lpspi2); + CLOCK_DisableClock(kCLOCK_Lpspi3); + CLOCK_DisableClock(kCLOCK_Lpspi4); + /* Set LPSPI_PODF. */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); + /* Set Lpspi clock source. */ + CLOCK_SetMux(kCLOCK_LpspiMux, 2); + /* Disable TRACE clock gate. */ + CLOCK_DisableClock(kCLOCK_Trace); + /* Set TRACE_PODF. */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 2); + /* Set Trace clock source. */ + CLOCK_SetMux(kCLOCK_TraceMux, 2); + /* Disable SAI1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai1); + /* Set SAI1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); + /* Set SAI1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai1Div, 1); + /* Set Sai1 clock source. */ + CLOCK_SetMux(kCLOCK_Sai1Mux, 0); + /* Disable SAI2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai2); + /* Set SAI2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); + /* Set SAI2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai2Div, 1); + /* Set Sai2 clock source. */ + CLOCK_SetMux(kCLOCK_Sai2Mux, 0); + /* Disable SAI3 clock gate. */ + CLOCK_DisableClock(kCLOCK_Sai3); + /* Set SAI3_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); + /* Set SAI3_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Sai3Div, 1); + /* Set Sai3 clock source. */ + CLOCK_SetMux(kCLOCK_Sai3Mux, 0); + /* Disable Lpi2c clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpi2c1); + CLOCK_DisableClock(kCLOCK_Lpi2c2); + CLOCK_DisableClock(kCLOCK_Lpi2c3); + /* Set LPI2C_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); + /* Set Lpi2c clock source. */ + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); + /* Disable CAN clock gate. */ + CLOCK_DisableClock(kCLOCK_Can1); + CLOCK_DisableClock(kCLOCK_Can2); + CLOCK_DisableClock(kCLOCK_Can3); + CLOCK_DisableClock(kCLOCK_Can1S); + CLOCK_DisableClock(kCLOCK_Can2S); + CLOCK_DisableClock(kCLOCK_Can3S); + /* Set CAN_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_CanDiv, 1); + /* Set Can clock source. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); + /* Disable UART clock gate. */ + CLOCK_DisableClock(kCLOCK_Lpuart1); + CLOCK_DisableClock(kCLOCK_Lpuart2); + CLOCK_DisableClock(kCLOCK_Lpuart3); + CLOCK_DisableClock(kCLOCK_Lpuart4); + CLOCK_DisableClock(kCLOCK_Lpuart5); + CLOCK_DisableClock(kCLOCK_Lpuart6); + CLOCK_DisableClock(kCLOCK_Lpuart7); + CLOCK_DisableClock(kCLOCK_Lpuart8); + /* Set UART_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); + /* Set Uart clock source. */ + CLOCK_SetMux(kCLOCK_UartMux, 0); + /* Disable SPDIF clock gate. */ + CLOCK_DisableClock(kCLOCK_Spdif); + /* Set SPDIF0_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); + /* Set SPDIF0_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); + /* Set Spdif clock source. */ + CLOCK_SetMux(kCLOCK_SpdifMux, 3); + /* Disable Flexio1 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio1); + /* Set FLEXIO1_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); + /* Set FLEXIO1_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); + /* Set Flexio1 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); + /* Disable Flexio2 clock gate. */ + CLOCK_DisableClock(kCLOCK_Flexio2); + /* Set FLEXIO2_CLK_PRED. */ + CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); + /* Set FLEXIO2_CLK_PODF. */ + CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); + /* Set Flexio2 clock source. */ + CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); + /* Set Pll3 sw clock source. */ + CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); + /* Init ARM PLL. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. + * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left + * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as + * well.*/ +#ifndef SKIP_SYSCLK_INIT + /* Init System PLL. */ + CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); + /* Init System pfd0. */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); + /* Init System pfd1. */ + CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); + /* Init System pfd2. */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + /* Init System pfd3. */ + CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); +#endif + /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. + * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left + * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as + * well.*/ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + /* Init Usb1 PLL. */ + CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); + /* Init Usb1 pfd0. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); + /* Init Usb1 pfd1. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); + /* Init Usb1 pfd2. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); + /* Init Usb1 pfd3. */ + CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); + /* Disable Usb1 PLL output for USBPHY1. */ + CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; +#endif + /* DeInit Audio PLL. */ + CLOCK_DeinitAudioPll(); + /* Bypass Audio PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); + /* Set divider for Audio PLL. */ + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; + CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; + /* Enable Audio PLL output. */ + CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; + /* DeInit Video PLL. */ + CLOCK_DeinitVideoPll(); + /* Bypass Video PLL. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; + /* Set divider for Video PLL. */ + CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); + /* Enable Video PLL output. */ + CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; + /* DeInit Enet PLL. */ + CLOCK_DeinitEnetPll(); + /* Bypass Enet PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); + /* Set Enet output divider. */ + CCM_ANALOG->PLL_ENET = + (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); + /* Enable Enet output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; + /* Set Enet2 output divider. */ + CCM_ANALOG->PLL_ENET = + (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); + /* Enable Enet2 output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; + /* Enable Enet25M output. */ + CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; + /* DeInit Usb2 PLL. */ + CLOCK_DeinitUsb2Pll(); + /* Bypass Usb2 PLL. */ + CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); + /* Enable Usb2 PLL output. */ + CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; + /* Set preperiph clock source. */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); + /* Set periph clock source. */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0); + /* Set periph clock2 clock source. */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); + /* Set per clock source. */ + CLOCK_SetMux(kCLOCK_PerclkMux, 0); + /* Set lvds1 clock source. */ + CCM_ANALOG->MISC1 = + (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); + /* Set clock out1 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); + /* Set clock out1 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); + /* Set clock out2 divider. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); + /* Set clock out2 source. */ + CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); + /* Set clock out1 drives clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; + /* Disable clock out1. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; + /* Disable clock out2. */ + CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET1 Tx clock source. */ + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false); + /* Set ENET2 Tx clock source. */ +#if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0))) + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false); +#else + IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false); +#endif + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/clock_config.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/clock_config.h new file mode 100644 index 0000000000..32e8ed4144 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/clock_config.h @@ -0,0 +1,120 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ + +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ + +/* Clock outputs (values are in Hz): */ +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL +#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL + +/*! @brief Arm PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN; +/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. + */ +extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN; +/*! @brief Sys PLL for BOARD_BootClockRUN configuration. + */ +extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN; + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/peripherals.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/peripherals.c new file mode 100644 index 0000000000..53a5d88fd4 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/peripherals.c @@ -0,0 +1,51 @@ +/* + * Copyright 2019 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v6.0 +processor: MIMXRT1061xxxxA +mcu_data: ksdk2_0 +processor_version: 0.0.20 +functionalGroups: +- name: BOARD_InitPeripherals + called_from_default_init: true + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +component: +- type: 'system' +- type_id: 'system_54b53072540eeeb8f8e9343e71f28176' +- global_system_definitions: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/*********************************************************************************************************************** + * Included files + **********************************************************************************************************************/ +#include "peripherals.h" + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ +void BOARD_InitPeripherals(void) +{ +} + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ + BOARD_InitPeripherals(); +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/peripherals.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/peripherals.h new file mode 100644 index 0000000000..1503606377 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/peripherals.h @@ -0,0 +1,34 @@ +/* + * Copyright 2019 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*********************************************************************************************************************** + * Initialization functions + **********************************************************************************************************************/ +void BOARD_InitPeripherals(void); + +/*********************************************************************************************************************** + * BOARD_InitBootPeripherals function + **********************************************************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif + +#endif /* _PERIPHERALS_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/pin_mux.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/pin_mux.c new file mode 100644 index 0000000000..12de3f2b1f --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/pin_mux.c @@ -0,0 +1,55 @@ +/* + * Copyright 2019 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v6.0 +processor: MIMXRT1061xxxxA +mcu_data: ksdk2_0 +processor_version: 0.0.20 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', enableClock: 'true'} +- pin_list: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) { +} + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/pin_mux.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/pin_mux.h new file mode 100644 index 0000000000..3ce8fab853 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/project_template/pin_mux.h @@ -0,0 +1,65 @@ +/* + * Copyright 2019 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/system_MIMXRT1061.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/system_MIMXRT1061.c new file mode 100644 index 0000000000..fb6c157c49 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/system_MIMXRT1061.c @@ -0,0 +1,232 @@ +/* +** ################################################################### +** Processors: MIMXRT1061CVJ5A +** MIMXRT1061CVL5A +** MIMXRT1061DVJ6A +** MIMXRT1061DVL6A +** +** Compilers: Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: IMXRT1060RM Rev.1, 12/2018 +** Version: rev. 1.1, 2018-11-27 +** Build: b190329 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 0.1 (2017-01-10) +** Initial version. +** - rev. 1.0 (2018-11-16) +** Update header files to align with IMXRT1060RM Rev.0. +** - rev. 1.1 (2018-11-27) +** Update header files to align with IMXRT1060RM Rev.1. +** +** ################################################################### +*/ + +/*! + * @file MIMXRT1061 + * @version 1.1 + * @date 2018-11-27 + * @brief Device specific configuration file for MIMXRT1061 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + +#if defined(__MCUXPRESSO) + extern uint32_t g_pfnVectors[]; // Vector table defined in startup code + SCB->VTOR = (uint32_t)g_pfnVectors; +#endif + +/* Disable Watchdog Power Down Counter */ +WDOG1->WMCR &= ~WDOG_WMCR_PDE_MASK; +WDOG2->WMCR &= ~WDOG_WMCR_PDE_MASK; + +/* Watchdog disable */ + +#if (DISABLE_WDOG) + if (WDOG1->WCR & WDOG_WCR_WDE_MASK) + { + WDOG1->WCR &= ~WDOG_WCR_WDE_MASK; + } + if (WDOG2->WCR & WDOG_WCR_WDE_MASK) + { + WDOG2->WCR &= ~WDOG_WCR_WDE_MASK; + } + RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */ + RTWDOG->TOVAL = 0xFFFF; + RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK; +#endif /* (DISABLE_WDOG) */ + + /* Disable Systick which might be enabled by bootrom */ + if (SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) + { + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + } + +/* Enable instruction and data caches */ +#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT + if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) { + SCB_EnableICache(); + } +#endif +#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT + if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) { + SCB_EnableDCache(); + } +#endif + + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + + uint32_t freq; + uint32_t PLL1MainClock; + uint32_t PLL2MainClock; + + /* Periph_clk2_clk ---> Periph_clk */ + if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) + { + switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) + { + /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(0U): + if(CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) + { + freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + } + else + { + freq = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U)); + } + break; + + /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ + case CCM_CBCMR_PERIPH_CLK2_SEL(1U): + freq = CPU_XTAL_CLK_HZ; + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(2U): + freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + break; + + case CCM_CBCMR_PERIPH_CLK2_SEL(3U): + default: + freq = 0U; + break; + } + + freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U); + } + /* Pre_Periph_clk ---> Periph_clk */ + else + { + /* check if pll is bypassed */ + if(CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK) + { + PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + } + else + { + PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U); + } + + /* check if pll is bypassed */ + if(CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) + { + PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ? + CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; + } + else + { + PLL2MainClock = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) ? 22U : 20U)); + } + PLL2MainClock += ((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)); + + + switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) + { + /* PLL2 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): + freq = PLL2MainClock; + break; + + /* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): + freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) * 18U; + break; + + /* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): + freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) * 18U; + break; + + /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */ + case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): + freq = PLL1MainClock / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U); + break; + + default: + freq = 0U; + break; + } + } + + SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U)); + +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/system_MIMXRT1061.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/system_MIMXRT1061.h new file mode 100644 index 0000000000..65de08cf6e --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/system_MIMXRT1061.h @@ -0,0 +1,123 @@ +/* +** ################################################################### +** Processors: MIMXRT1061CVJ5A +** MIMXRT1061CVL5A +** MIMXRT1061DVJ6A +** MIMXRT1061DVL6A +** +** Compilers: Freescale C/C++ for Embedded ARM +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: IMXRT1060RM Rev.1, 12/2018 +** Version: rev. 1.1, 2018-11-27 +** Build: b190312 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 0.1 (2017-01-10) +** Initial version. +** - rev. 1.0 (2018-11-16) +** Update header files to align with IMXRT1060RM Rev.0. +** - rev. 1.1 (2018-11-27) +** Update header files to align with IMXRT1060RM Rev.1. +** +** ################################################################### +*/ + +/*! + * @file MIMXRT1061 + * @version 1.1 + * @date 2018-11-27 + * @brief Device specific configuration file for MIMXRT1061 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MIMXRT1061_H_ +#define _SYSTEM_MIMXRT1061_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +#ifndef DISABLE_WDOG + #define DISABLE_WDOG 1 +#endif + +/* Define clock source values */ + +#define CPU_XTAL_CLK_HZ 24000000UL /* Value of the external crystal or oscillator clock frequency in Hz */ + +#define CPU_CLK1_HZ 0UL /* Value of the CLK1 (select the CLK1_N/CLK1_P as source) frequency in Hz */ + /* If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0 will be returned. */ + +#define DEFAULT_SYSTEM_CLOCK 528000000UL /* Default System clock value */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MIMXRT1061_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/debug_console/fsl_debug_console.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/debug_console/fsl_debug_console.c new file mode 100644 index 0000000000..bb91a37a45 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/debug_console/fsl_debug_console.c @@ -0,0 +1,1123 @@ +/* + * This is a modified version of the file printf.c, which was distributed + * by Motorola as part of the M5407C3BOOT.zip package used to initialize + * the M5407C3 evaluation board. + * + * Copyright: + * 1999-2000 MOTOROLA, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Motorola, Inc. This + * software is provided on an "AS IS" basis and without warranty. + * + * To the maximum extent permitted by applicable law, MOTOROLA + * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING + * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR + * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE + * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY + * ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING + * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS + * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY + * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Motorola assumes no responsibility for the maintenance and support + * of this software + + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +#include +#endif + +#ifdef FSL_RTOS_FREE_RTOS +#include "FreeRTOS.h" +#include "semphr.h" +#include "task.h" +#endif + +#include "fsl_debug_console_conf.h" +#include "fsl_str.h" + +#include "fsl_common.h" +#include "serial_manager.h" + +#include "fsl_debug_console.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef NDEBUG +#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) +#undef assert +#define assert(n) +#endif +#endif + +#if SDK_DEBUGCONSOLE +#define DEBUG_CONSOLE_FUNCTION_PREFIX +#else +#define DEBUG_CONSOLE_FUNCTION_PREFIX static +#endif + +/*! @brief character backspace ASCII value */ +#define DEBUG_CONSOLE_BACKSPACE 127U + +/* lock definition */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + +static SemaphoreHandle_t s_debugConsoleReadSemaphore; +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) +static SemaphoreHandle_t s_debugConsoleReadWaitSemaphore; +#endif + +#elif (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) + +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) +static volatile uint8_t s_debugConsoleReadWaitSemaphore; +#endif + +#else + +#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */ + +/*! @brief get current runing environment is ISR or not */ +#ifdef __CA7_REV +#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel() +#else +#define IS_RUNNING_IN_ISR() __get_IPSR() +#endif /* __CA7_REV */ + +/* semaphore definition */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + +/* mutex semaphore */ +#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) ((mutex) = xSemaphoreCreateMutex()) + +/* clang-format off */ +#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + (void)xSemaphoreGive(mutex); \ + } \ +} + +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + (void)xSemaphoreTake(mutex, portMAX_DELAY); \ + } \ +} + +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + result = xSemaphoreTake(mutex, 0U); \ + } \ + else \ + { \ + result = 1U; \ + } \ +} +/* clang-format on */ + +/* Binary semaphore */ +#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) ((binary) = xSemaphoreCreateBinary()) +#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) ((void)xSemaphoreTake(binary, portMAX_DELAY)) +#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) ((void)xSemaphoreGiveFromISR(binary, NULL)) + +#elif (DEBUG_CONSOLE_SYNCHRONIZATION_BM == DEBUG_CONSOLE_SYNCHRONIZATION_MODE) + +#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) +#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U) + +#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \ + { \ + while (!binary) \ + { \ + } \ + binary = false; \ + } +#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (binary = true) +#else +#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) +#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/* add other implementation here + *such as : + * #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DDEBUG_CONSOLE_SYNCHRONIZATION_xxx) + */ + +#else + +#error RTOS type is not defined by DEBUG_CONSOLE_SYNCHRONIZATION_MODE. + +#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */ + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/* receive state structure */ +typedef struct _debug_console_write_ring_buffer +{ + uint32_t ringBufferSize; + volatile uint32_t ringHead; + volatile uint32_t ringTail; + uint8_t ringBuffer[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN]; +} debug_console_write_ring_buffer_t; +#endif + +typedef struct _debug_console_state_struct +{ + uint8_t serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE]; + serial_handle_t serialHandle; /*!< serial manager handle */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + debug_console_write_ring_buffer_t writeRingBuffer; + uint8_t readRingBuffer[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN]; +#endif + uint8_t serialWriteHandleBuffer[SERIAL_MANAGER_WRITE_HANDLE_SIZE]; + uint8_t serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE]; +} debug_console_state_struct_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Debug console state information. */ +static debug_console_state_struct_t s_debugConsoleState; +serial_handle_t g_serialHandle; /*!< serial manager handle */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief This is a printf call back function which is used to relocate the log to buffer + * or print the log immediately when the local buffer is full. + * + * @param[in] buf Buffer to store log. + * @param[in] indicator Buffer index. + * @param[in] val Target character to store. + * @param[in] len length of the character + * + */ +#if SDK_DEBUGCONSOLE +static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len); +#endif + +status_t DbgConsole_ReadOneCharacter(uint8_t *ch); +int DbgConsole_SendData(uint8_t *ch, size_t size); +int DbgConsole_SendDataReliable(uint8_t *ch, size_t size); +int DbgConsole_ReadLine(uint8_t *buf, size_t size); +int DbgConsole_ReadCharacter(uint8_t *ch); + +#if ((SDK_DEBUGCONSOLE > 0U) || \ + ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ + (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)))) +DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void); +#endif +/******************************************************************************* + * Code + ******************************************************************************/ + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + +static void DbgConsole_SerialManagerTxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + debug_console_state_struct_t *ioState; + uint32_t sendDataLength; + + if ((NULL == callbackParam) || (NULL == message)) + { + return; + } + + ioState = (debug_console_state_struct_t *)callbackParam; + + ioState->writeRingBuffer.ringTail += message->length; + if (ioState->writeRingBuffer.ringTail >= ioState->writeRingBuffer.ringBufferSize) + { + ioState->writeRingBuffer.ringTail = 0U; + } + + if (kStatus_SerialManager_Success == status) + { + if (ioState->writeRingBuffer.ringTail != ioState->writeRingBuffer.ringHead) + { + if (ioState->writeRingBuffer.ringHead > ioState->writeRingBuffer.ringTail) + { + sendDataLength = ioState->writeRingBuffer.ringHead - ioState->writeRingBuffer.ringTail; + } + else + { + sendDataLength = ioState->writeRingBuffer.ringBufferSize - ioState->writeRingBuffer.ringTail; + } + + (void)SerialManager_WriteNonBlocking( + ((serial_write_handle_t)&ioState->serialWriteHandleBuffer[0]), + &ioState->writeRingBuffer.ringBuffer[ioState->writeRingBuffer.ringTail], sendDataLength); + } + } + else if (kStatus_SerialManager_Canceled == status) + { + ioState->writeRingBuffer.ringTail = 0U; + ioState->writeRingBuffer.ringHead = 0U; + } + else + { + /*MISRA rule 16.4*/ + } +} + +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + +static void DbgConsole_SerialManagerRxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + if ((NULL == callbackParam) || (NULL == message)) + { + return; + } + + if (kStatus_SerialManager_Notify == status) + { + } + else if (kStatus_SerialManager_Success == status) + { + /* release s_debugConsoleReadWaitSemaphore from RX callback */ + DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_debugConsoleReadWaitSemaphore); + } + else + { + /*MISRA rule 16.4*/ + } +} +#endif + +#endif + +status_t DbgConsole_ReadOneCharacter(uint8_t *ch) +{ +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ + (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED) + return kStatus_Fail; +#else + status_t status = (status_t)kStatus_SerialManager_Error; + +/* recieve one char every time */ +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + status = (status_t)SerialManager_ReadNonBlocking( + ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1); +#else + status = (status_t)SerialManager_ReadBlocking( + ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1); +#endif + if ((status_t)kStatus_SerialManager_Success != status) + { + return (status_t)kStatus_Fail; + } + /* wait s_debugConsoleReadWaitSemaphore from RX callback */ + DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(s_debugConsoleReadWaitSemaphore); + + return (status_t)kStatus_Success; +#endif + +#else + + return (status_t)kStatus_Fail; + +#endif +} + +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION +static status_t DbgConsole_EchoCharacter(uint8_t *ch, bool isGetChar, int *index) +{ + /* Due to scanf take \n and \r as end of string,should not echo */ + if (((*ch != (uint8_t)'\r') && (*ch != (uint8_t)'\n')) || (isGetChar)) + { + /* recieve one char every time */ + if (1 != DbgConsole_SendDataReliable(ch, 1U)) + { + return (status_t)kStatus_Fail; + } + } + + if ((!isGetChar) && (index != NULL)) + { + if (DEBUG_CONSOLE_BACKSPACE == *ch) + { + if ((*index >= 2)) + { + *index -= 2; + } + else + { + *index = 0; + } + } + } + + return (status_t)kStatus_Success; +} +#endif + +int DbgConsole_SendData(uint8_t *ch, size_t size) +{ + status_t status = (status_t)kStatus_SerialManager_Error; +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + uint32_t sendDataLength; + int txBusy = 0; +#endif + assert(NULL != ch); + assert(0 != size); + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + uint32_t regPrimask = DisableGlobalIRQ(); + if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { + txBusy = 1; + sendDataLength = + (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize - + s_debugConsoleState.writeRingBuffer.ringTail) % + s_debugConsoleState.writeRingBuffer.ringBufferSize; + } + else + { + sendDataLength = 0U; + } + sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1; + if (sendDataLength <= size) + { + EnableGlobalIRQ(regPrimask); + return -1; + } + for (int i = 0; i < (int)size; i++) + { + s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringHead++] = ch[i]; + if (s_debugConsoleState.writeRingBuffer.ringHead >= s_debugConsoleState.writeRingBuffer.ringBufferSize) + { + s_debugConsoleState.writeRingBuffer.ringHead = 0U; + } + } + + status = (status_t)kStatus_SerialManager_Success; + + if (txBusy == 0) + { + if (s_debugConsoleState.writeRingBuffer.ringHead > s_debugConsoleState.writeRingBuffer.ringTail) + { + sendDataLength = + s_debugConsoleState.writeRingBuffer.ringHead - s_debugConsoleState.writeRingBuffer.ringTail; + } + else + { + sendDataLength = + s_debugConsoleState.writeRingBuffer.ringBufferSize - s_debugConsoleState.writeRingBuffer.ringTail; + } + + status = (status_t)SerialManager_WriteNonBlocking( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), + &s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringTail], + sendDataLength); + } + EnableGlobalIRQ(regPrimask); +#else + status = (status_t)SerialManager_WriteBlocking( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size); +#endif + return (((status_t)kStatus_Success == status) ? (int)size : -1); +} + +int DbgConsole_SendDataReliable(uint8_t *ch, size_t size) +{ +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) +#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)) + status_t status = kStatus_SerialManager_Error; + uint32_t sendDataLength; + uint32_t totalLength = size; + int sentLength; +#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ +#else + status_t status = kStatus_SerialManager_Error; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + + assert(NULL != ch); + assert(0 != size); + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + +#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)) + do + { + uint32_t regPrimask = DisableGlobalIRQ(); + if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { + sendDataLength = + (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize - + s_debugConsoleState.writeRingBuffer.ringTail) % + s_debugConsoleState.writeRingBuffer.ringBufferSize; + } + else + { + sendDataLength = 0U; + } + sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U; + + if (sendDataLength > 0U) + { + if (sendDataLength > totalLength) + { + sendDataLength = totalLength; + } + + sentLength = DbgConsole_SendData(&ch[size - totalLength], sendDataLength); + if (sentLength > 0) + { + totalLength = totalLength - (uint32_t)sentLength; + } + } + EnableGlobalIRQ(regPrimask); + + if (totalLength != 0U) + { + status = DbgConsole_Flush(); + if ((status_t)kStatus_Success != status) + { + break; + } + } + } while (totalLength != 0U); + return (status_t)(uint32_t)((uint32_t)size - totalLength); +#else + return DbgConsole_SendData(ch, size); +#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ + +#else + status = (status_t)SerialManager_WriteBlocking( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size); + return (((status_t)kStatus_Success == status) ? (int)size : -1); +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +} + +int DbgConsole_ReadLine(uint8_t *buf, size_t size) +{ + int i = 0; + + assert(buf != NULL); + + /* take mutex lock function */ + DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); + + do + { + /* recieve one char every time */ + if ((status_t)kStatus_Success != DbgConsole_ReadOneCharacter(&buf[i])) + { + /* release mutex lock function */ + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); + i = -1; + break; + } +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + (void)DbgConsole_EchoCharacter(&buf[i], false, &i); +#endif + /* analysis data */ + if (((uint8_t)'\r' == buf[i]) || ((uint8_t)'\n' == buf[i])) + { + /* End of Line. */ + if (0 == i) + { + buf[i] = (uint8_t)'\0'; + continue; + } + else + { + break; + } + } + i++; + } while (i < (int)size); + + /* get char should not add '\0'*/ + if (i == (int)size) + { + buf[i] = (uint8_t)'\0'; + } + else + { + buf[i + 1] = (uint8_t)'\0'; + } + + /* release mutex lock function */ + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); + + return i; +} + +int DbgConsole_ReadCharacter(uint8_t *ch) +{ + int ret; + + assert(ch); + + /* take mutex lock function */ + DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); + /* read one character */ + if ((status_t)kStatus_Success == DbgConsole_ReadOneCharacter(ch)) + { + ret = 1; +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + (void)DbgConsole_EchoCharacter(ch, true, NULL); +#endif + } + else + { + ret = -1; + } + + /* release mutex lock function */ + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); + + return ret; +} + +#if SDK_DEBUGCONSOLE +static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len) +{ + int i = 0; + + for (i = 0; i < len; i++) + { + if (((uint32_t)*indicator + 1UL) >= DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN) + { + (void)DbgConsole_SendDataReliable((uint8_t *)buf, (uint32_t)(*indicator)); + *indicator = 0; + } + + buf[*indicator] = dbgVal; + (*indicator)++; + } +} +#endif + +/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/ + +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq) +{ + serial_manager_config_t serialConfig; + status_t status = (status_t)kStatus_SerialManager_Error; + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + serial_port_uart_config_t uartConfig = { + .instance = instance, + .clockRate = clkSrcFreq, + .baudRate = baudRate, + .parityMode = kSerialManager_UartParityDisabled, + .stopBitCount = kSerialManager_UartOneStopBit, + .enableRx = 1, + .enableTx = 1, + }; +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + serial_port_usb_cdc_config_t usbCdcConfig = { + .controllerIndex = (serial_port_usb_cdc_controller_index_t)instance, + }; +#endif + +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + serial_port_swo_config_t swoConfig = { + .clockRate = clkSrcFreq, + .baudRate = baudRate, + .port = instance, + .protocol = kSerialManager_SwoProtocolNrz, + }; +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) + serial_port_usb_cdc_virtual_config_t usbCdcVirtualConfig = { + .controllerIndex = (serial_port_usb_cdc_virtual_controller_index_t)instance, + }; +#endif + serialConfig.type = device; +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + serialConfig.ringBuffer = &s_debugConsoleState.readRingBuffer[0]; + serialConfig.ringBufferSize = DEBUG_CONSOLE_RECEIVE_BUFFER_LEN; +#endif + + if (kSerialPort_Uart == device) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + serialConfig.portConfig = &uartConfig; +#else + return status; +#endif + } + else if (kSerialPort_UsbCdc == device) + { +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + serialConfig.portConfig = &usbCdcConfig; +#else + return status; +#endif + } + else if (kSerialPort_Swo == device) + { +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + serialConfig.portConfig = &swoConfig; +#else + return status; +#endif + } + else if (kSerialPort_UsbCdcVirtual == device) + { +#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) + serialConfig.portConfig = &usbCdcVirtualConfig; +#else + return status; +#endif + } + else + { + return status; + } + + (void)memset(&s_debugConsoleState, 0, sizeof(s_debugConsoleState)); + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + s_debugConsoleState.writeRingBuffer.ringBufferSize = DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN; +#endif + + s_debugConsoleState.serialHandle = (serial_handle_t)&s_debugConsoleState.serialHandleBuffer[0]; + status = (status_t)SerialManager_Init(s_debugConsoleState.serialHandle, &serialConfig); + + assert(kStatus_SerialManager_Success == status); + + DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore); +#endif + + { + status = (status_t)SerialManager_OpenWriteHandle( + s_debugConsoleState.serialHandle, ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0])); + assert(kStatus_SerialManager_Success == status); +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + (void)SerialManager_InstallTxCallback(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), + DbgConsole_SerialManagerTxCallback, &s_debugConsoleState); +#endif + } + +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + { + status = (status_t)SerialManager_OpenReadHandle( + s_debugConsoleState.serialHandle, ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0])); + assert(kStatus_SerialManager_Success == status); +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + (void)SerialManager_InstallRxCallback(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), + DbgConsole_SerialManagerRxCallback, &s_debugConsoleState); +#endif + } +#endif + + g_serialHandle = s_debugConsoleState.serialHandle; + + return kStatus_Success; +} + +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Deinit(void) +{ + { + if (s_debugConsoleState.serialHandle != NULL) + { + (void)SerialManager_CloseWriteHandle( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0])); + } + } +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + { + if (s_debugConsoleState.serialHandle != NULL) + { + (void)SerialManager_CloseReadHandle(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0])); + } + } +#endif + return (status_t)kStatus_Success; +} + +#if ((SDK_DEBUGCONSOLE > 0U) || \ + ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ + (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)))) +DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void) +{ +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED) + + if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { + return (status_t)kStatus_Fail; + } + +#else + + while (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + if (0U == IS_RUNNING_IN_ISR()) + { + if (taskSCHEDULER_RUNNING == xTaskGetSchedulerState()) + { + vTaskDelay(1); + } + } + else + { + return (status_t)kStatus_Fail; + } +#endif + } + +#endif + +#endif + return (status_t)kStatus_Success; +} +#endif + +#if SDK_DEBUGCONSOLE +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Printf(const char *formatString, ...) +{ + va_list ap; + int logLength = 0, dbgResult = 0; + char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'}; + + if (NULL == g_serialHandle) + { + return 0; + } + + va_start(ap, formatString); + /* format print log first */ + logLength = StrFormatPrintf(formatString, ap, printBuf, DbgConsole_PrintCallback); + /* print log */ + dbgResult = DbgConsole_SendDataReliable((uint8_t *)printBuf, (size_t)logLength); + + va_end(ap); + + return dbgResult; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Putchar(int ch) +{ + /* print char */ + return DbgConsole_SendDataReliable((uint8_t *)&ch, 1U); +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Scanf(char *formatString, ...) +{ + va_list ap; + int formatResult; + char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {'\0'}; + + /* scanf log */ + (void)DbgConsole_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN); + /* get va_list */ + va_start(ap, formatString); + /* format scanf log */ + formatResult = StrFormatScanf(scanfBuf, formatString, ap); + + va_end(ap); + + return formatResult; +} + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +status_t DbgConsole_TryGetchar(char *ch) +{ +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + uint32_t length = 0; + status_t status = (status_t)kStatus_Fail; + + assert(ch); + + /* take mutex lock function */ + DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); + + if (kStatus_SerialManager_Success == + SerialManager_TryRead(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), (uint8_t *)ch, 1, + &length)) + { + if (length != 0U) + { +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + (void)DbgConsole_EchoCharacter((uint8_t *)ch, true, NULL); +#endif + status = (status_t)kStatus_Success; + } + } + /* release mutex lock function */ + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); + return status; +#else + return (status_t)kStatus_Fail; +#endif +} +#endif + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Getchar(void) +{ + uint8_t ch = 0U; + + /* Get char */ + (void)DbgConsole_ReadCharacter(&ch); + + return (int)ch; +} + +#endif /* SDK_DEBUGCONSOLE */ + +/*************Code to support toolchain's printf, scanf *******************************/ +/* These function __write and __read is used to support IAR toolchain to printf and scanf*/ +#if (defined(__ICCARM__)) +#if defined(SDK_DEBUGCONSOLE_UART) +#pragma weak __write +size_t __write(int handle, const unsigned char *buffer, size_t size) +{ + if (buffer == 0) + { + /* + * This means that we should flush internal buffers. Since we don't we just return. + * (Remember, "handle" == -1 means that all handles should be flushed.) + */ + return 0; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return ((size_t)-1); + } + + /* Send data. */ + DbgConsole_SendDataReliable((uint8_t *)buffer, size); + + return size; +} + +#pragma weak __read +size_t __read(int handle, unsigned char *buffer, size_t size) +{ + uint8_t ch = 0U; + int actualSize = 0U; + + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (handle != 0) + { + return ((size_t)-1); + } + + /* Receive data.*/ + for (; size > 0; size--) + { + DbgConsole_ReadCharacter(&ch); + if (ch == 0) + { + break; + } + + *buffer++ = ch; + actualSize++; + } + + return actualSize; +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* support LPC Xpresso with RedLib */ +#elif (defined(__REDLIB__)) + +#if (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART)) +int __attribute__((weak)) __sys_write(int handle, char *buffer, int size) +{ + if (buffer == 0) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Send data. */ + DbgConsole_SendDataReliable((uint8_t *)buffer, size); + + return 0; +} + +int __attribute__((weak)) __sys_readc(void) +{ + char tmp; + + /* Receive data. */ + DbgConsole_ReadCharacter((uint8_t *)&tmp); + + return tmp; +} +#endif + +/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/ +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +#if defined(SDK_DEBUGCONSOLE_UART) +#if defined(__CC_ARM) +struct __FILE +{ + int handle; + /* + * Whatever you require here. If the only file you are using is standard output using printf() for debugging, + * no file handling is required. + */ +}; +#endif + +/* FILE is typedef in stdio.h. */ +#pragma weak __stdout +#pragma weak __stdin +FILE __stdout; +FILE __stdin; + +#pragma weak fputc +int fputc(int ch, FILE *f) +{ + /* Send data. */ + return DbgConsole_SendDataReliable((uint8_t *)(&ch), 1); +} + +#pragma weak fgetc +int fgetc(FILE *f) +{ + char ch; + + /* Receive data. */ + DbgConsole_ReadCharacter((uint8_t *)&ch); + + return ch; +} + +/* + * Terminate the program, passing a return code back to the user. + * This function may not return. + */ +void _sys_exit(int returncode) +{ + while (1) + { + } +} + +/* + * Writes a character to the output channel. This function is used + * for last-resort error message output. + */ +void _ttywrch(int ch) +{ + char ench = ch; + DbgConsole_SendDataReliable((uint8_t *)(&ench), 1); +} + +char *_sys_command_string(char *cmd, int len) +{ + return (cmd); +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/ +#elif (defined(__GNUC__)) + +#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \ + (defined(__MCUXPRESSO) && (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART)))) +int __attribute__((weak)) _write(int handle, char *buffer, int size); +int __attribute__((weak)) _write(int handle, char *buffer, int size) +{ + if (buffer == NULL) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Send data. */ + (void)DbgConsole_SendDataReliable((uint8_t *)buffer, (size_t)size); + + return size; +} + +int __attribute__((weak)) _read(int handle, char *buffer, int size); +int __attribute__((weak)) _read(int handle, char *buffer, int size) +{ + uint8_t ch = 0U; + int actualSize = 0; + + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (handle != 0) + { + return -1; + } + + /* Receive data. */ + for (; size > 0; size--) + { + if (DbgConsole_ReadCharacter(&ch) < 0) + { + break; + } + + *buffer++ = (char)ch; + actualSize++; + + if ((ch == 0U) || (ch == (uint8_t)'\n') || (ch == (uint8_t)'\r')) + { + break; + } + } + + return (actualSize > 0) ? actualSize : -1; +} +#endif + +#endif /* __ICCARM__ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/debug_console/fsl_debug_console.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/debug_console/fsl_debug_console.h new file mode 100644 index 0000000000..986da32347 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/debug_console/fsl_debug_console.h @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Debug console shall provide input and output functions to scan and print formatted data. + * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier" + * - [flags] :'-', '+', '#', ' ', '0' + * - [width]: number (0,1...) + * - [.precision]: number (0,1...) + * - [length]: do not support + * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n' + * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier" + * - [*]: is supported. + * - [width]: number (0,1...) + * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t') + * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's' + */ + +#ifndef _FSL_DEBUGCONSOLE_H_ +#define _FSL_DEBUGCONSOLE_H_ + +#include "fsl_common.h" +#include "serial_manager.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +extern serial_handle_t g_serialHandle; /*!< serial manager handle */ + +/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */ +#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */ +#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */ +#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */ + +/*! @brief Definition to select sdk or toolchain printf, scanf. The macro only support + * to be redefined in project setting. + */ +#ifndef SDK_DEBUGCONSOLE +#define SDK_DEBUGCONSOLE 1U +#endif + +/*! @brief Definition to select redirect toolchain printf, scanf to uart or not. */ +#ifndef SDK_DEBUGCONSOLE_UART +/* mcux will handle this macro, not define it here */ +#if (!defined(__MCUXPRESSO)) +#define SDK_DEBUGCONSOLE_UART +#endif +#endif + +#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE) +#include +#endif + +/*! @brief Definition to select redirect toolchain printf, scanf to uart or not. + * + * if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf. + * if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf. + * if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function. + */ +#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */ +#define PRINTF +#define SCANF +#define PUTCHAR +#define GETCHAR +#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */ +#define PRINTF DbgConsole_Printf +#define SCANF DbgConsole_Scanf +#define PUTCHAR DbgConsole_Putchar +#define GETCHAR DbgConsole_Getchar +#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \ + */ +#define PRINTF printf +#define SCANF scanf +#define PUTCHAR putchar +#define GETCHAR getchar +#endif /* SDK_DEBUGCONSOLE */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! @name Initialization*/ +/* @{ */ + +/*! + * @brief Initializes the peripheral used for debug messages. + * + * Call this function to enable debug log messages to be output via the specified peripheral + * initialized by the serial manager module. + * After this function has returned, stdout and stdin are connected to the selected peripheral. + * + * @param instance The instance of the module. + * @param baudRate The desired baud rate in bits per second. + * @param device Low level device type for the debug console, can be one of the following. + * @arg kSerialPort_Uart, + * @arg kSerialPort_UsbCdc + * @arg kSerialPort_UsbCdcVirtual. + * @param clkSrcFreq Frequency of peripheral source clock. + * + * @return Indicates whether initialization was successful or not. + * @retval kStatus_Success Execution successfully + */ +status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq); + +/*! + * @brief De-initializes the peripheral used for debug messages. + * + * Call this function to disable debug log messages to be output via the specified peripheral + * initialized by the serial manager module. + * + * @return Indicates whether de-initialization was successful or not. + */ +status_t DbgConsole_Deinit(void); + +#if SDK_DEBUGCONSOLE +/*! + * @brief Writes formatted output to the standard output stream. + * + * Call this function to write a formatted output to the standard output stream. + * + * @param formatString Format control string. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_Printf(const char *formatString, ...); + +/*! + * @brief Writes a character to stdout. + * + * Call this function to write a character to stdout. + * + * @param ch Character to be written. + * @return Returns the character written. + */ +int DbgConsole_Putchar(int ch); + +/*! + * @brief Reads formatted data from the standard input stream. + * + * Call this function to read formatted data from the standard input stream. + * + * @note Due the limitation in the BM OSA environment (CPU is blocked in the function, + * other tasks will not be scheduled), the function cannot be used when the + * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment. + * And an error is returned when the function called in this case. The suggestion + * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char. + * + * @param formatString Format control string. + * @return Returns the number of fields successfully converted and assigned. + */ +int DbgConsole_Scanf(char *formatString, ...); + +/*! + * @brief Reads a character from standard input. + * + * Call this function to read a character from standard input. + * + * @note Due the limitation in the BM OSA environment (CPU is blocked in the function, + * other tasks will not be scheduled), the function cannot be used when the + * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment. + * And an error is returned when the function called in this case. The suggestion + * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char. + * + * @return Returns the character read. + */ +int DbgConsole_Getchar(void); + +/*! + * @brief Debug console flush. + * + * Call this function to wait the tx buffer empty. + * If interrupt transfer is using, make sure the global IRQ is enable before call this function + * This function should be called when + * 1, before enter power down mode + * 2, log is required to print to terminal immediately + * @return Indicates whether wait idle was successful or not. + */ +status_t DbgConsole_Flush(void); + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! + * @brief Debug console try to get char + * This function provides a API which will not block current task, if character is + * available return it, otherwise return fail. + * @param ch the address of char to receive + * @return Indicates get char was successful or not. + */ +status_t DbgConsole_TryGetchar(char *ch); +#endif + +#endif /* SDK_DEBUGCONSOLE */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_DEBUGCONSOLE_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/debug_console/fsl_debug_console_conf.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/debug_console/fsl_debug_console_conf.h new file mode 100644 index 0000000000..366c6cdc21 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/debug_console/fsl_debug_console_conf.h @@ -0,0 +1,158 @@ +/* + * Copyright 2017 - 2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_DEBUG_CONSOLE_CONF_H_ +#define _FSL_DEBUG_CONSOLE_CONF_H_ + +/****************Debug console configuration********************/ + +/*! @brief If Non-blocking mode is needed, please define it at project setting, + * otherwise blocking mode is the default transfer mode. + * Warning: If you want to use non-blocking transfer,please make sure the corresponding + * IO interrupt is enable, otherwise there is no output. + * And non-blocking is combine with buffer, no matter bare-metal or rtos. + * Below shows how to configure in your project if you want to use non-blocking mode. + * For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols". + * For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define". + * For ARMGCC, open CmakeLists.txt and add the following lines, + * "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target. + * "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target. + * For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C + * Complier->Preprocessor". + * + */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically + * when + * non-blocking transfer is using, + * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. + * If it is configured too small, log maybe missed , because the log will not be + * buffered if the buffer is full, and the print will return immediately with -1. + * And this value should be multiple of 4 to meet memory alignment. + * + */ +#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN +#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U) +#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */ + +/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when + * non-blocking transfer is using, + * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. + * If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small. + * And this value should be multiple of 4 to meet memory alignment. + * + */ +#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN +#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U) +#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */ + +/*!@ brief Whether enable the reliable TX function + * If the macro is zero, the reliable TX function of the debug console is disabled. + * When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full. + */ +#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE +#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U) +#endif /* DEBUG_CONSOLE_RX_ENABLE */ + +#else +#define DEBUG_CONSOLE_TRANSFER_BLOCKING +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/*!@ brief Whether enable the RX function + * If the macro is zero, the receive function of the debug console is disabled. + */ +#ifndef DEBUG_CONSOLE_RX_ENABLE +#define DEBUG_CONSOLE_RX_ENABLE (1U) +#endif /* DEBUG_CONSOLE_RX_ENABLE */ + +/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log + * length can not bigger than this value. + * This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if + * the buffer is too big and current task stack size not big enough. + */ +#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN +#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U) +#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */ + +/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log + * length can not bigger than this value. + * As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN. + */ +#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN +#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U) +#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */ + +/*! @brief Debug console synchronization + * User should not change these macro for synchronization mode, but add the + * corresponding synchronization mechanism per different software environment. + * Such as, if another RTOS is used, + * add: + * #define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3 + * in this configuration file and implement the synchronization in fsl.log.c. + */ +/*! @brief synchronization for baremetal software */ +#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0 +/*! @brief synchronization for freertos software */ +#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1 + +/*! @brief RTOS synchronization mechanism disable + * If not defined, default is enable, to avoid multitask log print mess. + * If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c + * If synchronization is disabled, log maybe messed on terminal. + */ +#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#ifdef FSL_RTOS_FREE_RTOS +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS +#else +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM +#endif /* FSL_RTOS_FREE_RTOS */ +#else +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */ + +/*! @brief echo function support + * If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO + * at your project setting. + */ +#ifndef DEBUG_CONSOLE_ENABLE_ECHO +#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0 +#else +#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1 +#endif /* DEBUG_CONSOLE_ENABLE_ECHO */ + +/*********************************************************************/ + +/***************Debug console other configuration*********************/ +/*! @brief Definition to printf the float number. */ +#ifndef PRINTF_FLOAT_ENABLE +#define PRINTF_FLOAT_ENABLE 0U +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! @brief Definition to scanf the float number. */ +#ifndef SCANF_FLOAT_ENABLE +#define SCANF_FLOAT_ENABLE 0U +#endif /* SCANF_FLOAT_ENABLE */ + +/*! @brief Definition to support advanced format specifier for printf. */ +#ifndef PRINTF_ADVANCED_ENABLE +#define PRINTF_ADVANCED_ENABLE 0U +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Definition to support advanced format specifier for scanf. */ +#ifndef SCANF_ADVANCED_ENABLE +#define SCANF_ADVANCED_ENABLE 0U +#endif /* SCANF_ADVANCED_ENABLE */ + +/*! @brief Definition to select virtual com(USB CDC) as the debug console. */ +#ifndef BOARD_USE_VIRTUALCOM +#define BOARD_USE_VIRTUALCOM 0U +#endif +/*******************************************************************/ + +#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/fsl_assert.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/fsl_assert.c new file mode 100644 index 0000000000..9052faf9cb --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/fsl_assert.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" + +#ifndef NDEBUG +#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__)) +void __aeabi_assert(const char *failedExpr, const char *file, int line) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); + for (;;) + { + __BKPT(0); + } +} +#elif (defined(__GNUC__)) +void __assert_func(const char *file, int line, const char *func, const char *failedExpr) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func); + for (;;) + { + __BKPT(0); + } +} +#endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */ +#endif /* NDEBUG */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/fsl_notifier.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/fsl_notifier.c new file mode 100644 index 0000000000..393c83a797 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/fsl_notifier.c @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_notifier.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Creates a Notifier handle. + * + * param notifierHandle A pointer to the notifier handle. + * param configs A pointer to an array with references to all configurations which is handled by the Notifier. + * param configsNumber Number of configurations. Size of the configuration array. + * param callbacks A pointer to an array of callback configurations. + * If there are no callbacks to register during Notifier initialization, use NULL value. + * param callbacksNumber Number of registered callbacks. Size of the callbacks array. + * param userFunction User function. + * param userData User data passed to user function. + * return An error Code or kStatus_Success. + */ +status_t NOTIFIER_CreateHandle(notifier_handle_t *notifierHandle, + notifier_user_config_t **configs, + uint8_t configsNumber, + notifier_callback_config_t *callbacks, + uint8_t callbacksNumber, + notifier_user_function_t userFunction, + void *userData) +{ + /* Check input parameter - at least one configuration is required and userFunction must exist */ + if ((configs == NULL) || (configsNumber == 0U) || (userFunction == NULL)) + { + return kStatus_Fail; + } + /* Initialize handle structure */ + memset(notifierHandle, 0, sizeof(notifier_handle_t)); + /* Store references to user-defined configurations */ + notifierHandle->configsTable = configs; + notifierHandle->configsNumber = configsNumber; + /* Store references to user-defined callback configurations */ + if (callbacks != NULL) + { + notifierHandle->callbacksTable = callbacks; + notifierHandle->callbacksNumber = callbacksNumber; + /* If all callbacks return success, then the errorCallbackIndex is callbacksNumber */ + notifierHandle->errorCallbackIndex = callbacksNumber; + } + notifierHandle->userFunction = userFunction; + notifierHandle->userData = userData; + + return kStatus_Success; +} + +/*! + * brief Switches the configuration according to a pre-defined structure. + * + * This function sets the system to the target configuration. Before transition, + * the Notifier sends notifications to all callbacks registered to the callback table. + * Callbacks are invoked in the following order: All registered callbacks are notified + * ordered by index in the callbacks array. The same order is used for before and after switch notifications. + * The notifications before the configuration switch can be used to obtain confirmation about + * the change from registered callbacks. If any registered callback denies the + * configuration change, further execution of this function depends on the notifier policy: the + * configuration change is either forced (kNOTIFIER_PolicyForcible) or exited (kNOTIFIER_PolicyAgreement). + * When configuration change is forced, the result of the before switch notifications are ignored. If an + * agreement is required, if any callback returns an error code, further notifications + * before switch notifications are cancelled and all already notified callbacks are re-invoked. + * The index of the callback which returned error code during pre-switch notifications is stored + * (any error codes during callbacks re-invocation are ignored) and NOTIFIER_GetErrorCallback() can be used to get it. + * Regardless of the policies, if any callback returns an error code, an error code indicating in which phase + * the error occurred is returned when NOTIFIER_SwitchConfig() exits. + * param notifierHandle pointer to notifier handle + * param configIndex Index of the target configuration. + * param policy Transaction policy, kNOTIFIER_PolicyAgreement or kNOTIFIER_PolicyForcible. + * + * return An error code or kStatus_Success. + * + */ +status_t NOTIFIER_SwitchConfig(notifier_handle_t *notifierHandle, uint8_t configIndex, notifier_policy_t policy) +{ + uint8_t currentStaticCallback = 0U; /* Index to array of statically registered call-backs */ + status_t returnCode = kStatus_Success; /* Function return */ + + notifier_notification_block_t notifyBlock; /* Callback notification block */ + notifier_callback_config_t *callbackConfig; /* Pointer to callback configuration */ + + /* Set errorcallbackindex as callbacksNumber, which means no callback error now */ + notifierHandle->errorCallbackIndex = notifierHandle->callbacksNumber; + + /* Requested configuration availability check */ + if (configIndex >= notifierHandle->configsNumber) + { + return kStatus_OutOfRange; + } + + /* Initialization of local variables from the Notifier handle structure */ + + notifyBlock.policy = policy; + notifyBlock.targetConfig = notifierHandle->configsTable[configIndex]; + notifyBlock.notifyType = kNOTIFIER_NotifyBefore; + + /* From all statically registered call-backs... */ + for (currentStaticCallback = 0U; currentStaticCallback < notifierHandle->callbacksNumber; currentStaticCallback++) + { + callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]); + /* ...notify only those which asked to be called before the configuration switch */ + if (((uint32_t)callbackConfig->callbackType) & kNOTIFIER_CallbackBefore) + { + /* In case that call-back returned error code mark it, store the call-back handle and eventually cancel + * the configuration switch */ + if (callbackConfig->callback(¬ifyBlock, callbackConfig->callbackData) != kStatus_Success) + { + returnCode = kStatus_NOTIFIER_ErrorNotificationBefore; + notifierHandle->errorCallbackIndex = currentStaticCallback; + /* If not forcing configuration switch, call all already notified call-backs to revert their state + * as the switch is canceled */ + if (policy != kNOTIFIER_PolicyForcible) + { + break; + } + } + } + } + + /* Set configuration */ + + /* In case that any call-back returned error code and policy doesn't force the configuration set, go to after + * switch call-backs */ + if ((policy == kNOTIFIER_PolicyForcible) || (returnCode == kStatus_Success)) + { + returnCode = notifierHandle->userFunction(notifierHandle->configsTable[configIndex], notifierHandle->userData); + if (returnCode != kStatus_Success) + { + return returnCode; + } + /* Update current configuration index */ + notifierHandle->currentConfigIndex = configIndex; + notifyBlock.notifyType = kNOTIFIER_NotifyAfter; + /* From all statically registered call-backs... */ + for (currentStaticCallback = 0U; currentStaticCallback < notifierHandle->callbacksNumber; + currentStaticCallback++) + { + callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]); + /* ...notify only those which asked to be called after the configuration switch */ + if (((uint32_t)callbackConfig->callbackType) & kNOTIFIER_CallbackAfter) + { + /* In case that call-back returned error code mark it and store the call-back handle */ + if (callbackConfig->callback(¬ifyBlock, callbackConfig->callbackData) != kStatus_Success) + { + returnCode = kStatus_NOTIFIER_ErrorNotificationAfter; + notifierHandle->errorCallbackIndex = currentStaticCallback; + if (policy != kNOTIFIER_PolicyForcible) + { + break; + } + } + } + } + } + else + { + /* End of unsuccessful switch */ + notifyBlock.notifyType = kNOTIFIER_NotifyRecover; + while (currentStaticCallback--) + { + callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]); + if (((uint32_t)callbackConfig->callbackType) & kNOTIFIER_CallbackBefore) + { + callbackConfig->callback(¬ifyBlock, callbackConfig->callbackData); + } + } + } + + return returnCode; +} + +/*! + * brief This function returns the last failed notification callback. + * + * This function returns an index of the last callback that failed during the configuration switch while + * the last NOTIFIER_SwitchConfig() was called. If the last NOTIFIER_SwitchConfig() call ended successfully + * value equal to callbacks number is returned. The returned value represents an index in the array of + * static call-backs. + * + * param notifierHandle Pointer to the notifier handle + * return Callback Index of the last failed callback or value equal to callbacks count. + */ +uint8_t NOTIFIER_GetErrorCallbackIndex(notifier_handle_t *notifierHandle) +{ + return notifierHandle->errorCallbackIndex; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/fsl_notifier.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/fsl_notifier.h new file mode 100644 index 0000000000..d93578c13f --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/fsl_notifier.h @@ -0,0 +1,237 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_NOTIFIER_H_ +#define _FSL_NOTIFIER_H_ + +#include "fsl_common.h" +/*! + * @addtogroup notifier + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Notifier error codes. + * + * Used as return value of Notifier functions. + */ +enum _notifier_status +{ + kStatus_NOTIFIER_ErrorNotificationBefore = + MAKE_STATUS(kStatusGroup_NOTIFIER, 0), /*!< An error occurs during send "BEFORE" notification. */ + kStatus_NOTIFIER_ErrorNotificationAfter = + MAKE_STATUS(kStatusGroup_NOTIFIER, 1), /*!< An error occurs during send "AFTER" notification. */ +}; + +/*! + * @brief Notifier policies. + * + * Defines whether the user function execution is forced or not. + * For kNOTIFIER_PolicyForcible, the user function is executed regardless of the callback results, + * while kNOTIFIER_PolicyAgreement policy is used to exit NOTIFIER_SwitchConfig() + * when any of the callbacks returns error code. + * See also NOTIFIER_SwitchConfig() description. + */ +typedef enum _notifier_policy +{ + kNOTIFIER_PolicyAgreement, /*!< NOTIFIER_SwitchConfig() method is exited when any of the callbacks returns error + code. */ + kNOTIFIER_PolicyForcible, /*!< The user function is executed regardless of the results. */ +} notifier_policy_t; + +/*! @brief Notification type. Used to notify registered callbacks */ +typedef enum _notifier_notification_type +{ + kNOTIFIER_NotifyRecover = 0x00U, /*!< Notify IP to recover to previous work state. */ + kNOTIFIER_NotifyBefore = 0x01U, /*!< Notify IP that configuration setting is going to change. */ + kNOTIFIER_NotifyAfter = 0x02U, /*!< Notify IP that configuration setting has been changed. */ +} notifier_notification_type_t; + +/*! + * @brief The callback type, which indicates kinds of notification the callback handles. + * + * Used in the callback configuration structure (notifier_callback_config_t) + * to specify when the registered callback is called during configuration switch initiated by the + * NOTIFIER_SwitchConfig(). + * Callback can be invoked in following situations. + * - Before the configuration switch (Callback return value can affect NOTIFIER_SwitchConfig() + * execution. See the NOTIFIER_SwitchConfig() and notifier_policy_t documentation). + * - After an unsuccessful attempt to switch configuration + * - After a successful configuration switch + */ +typedef enum _notifier_callback_type +{ + kNOTIFIER_CallbackBefore = 0x01U, /*!< Callback handles BEFORE notification. */ + kNOTIFIER_CallbackAfter = 0x02U, /*!< Callback handles AFTER notification. */ + kNOTIFIER_CallbackBeforeAfter = 0x03U, /*!< Callback handles BEFORE and AFTER notification. */ +} notifier_callback_type_t; + +/*! @brief Notifier user configuration type. + * + * Reference of the user defined configuration is stored in an array; the notifier switches between these configurations + * based on this array. + */ +typedef void notifier_user_config_t; + +/*! @brief Notifier user function prototype + * Use this function to execute specific operations in configuration switch. + * Before and after this function execution, different notification is sent to registered callbacks. + * If this function returns any error code, NOTIFIER_SwitchConfig() exits. + * + * @param targetConfig target Configuration. + * @param userData Refers to other specific data passed to user function. + * @return An error code or kStatus_Success. + */ +typedef status_t (*notifier_user_function_t)(notifier_user_config_t *targetConfig, void *userData); + +/*! @brief notification block passed to the registered callback function. */ +typedef struct _notifier_notification_block +{ + notifier_user_config_t *targetConfig; /*!< Pointer to target configuration. */ + notifier_policy_t policy; /*!< Configure transition policy. */ + notifier_notification_type_t notifyType; /*!< Configure notification type. */ +} notifier_notification_block_t; + +/*! + * @brief Callback prototype. + * + * Declaration of a callback. It is common for registered callbacks. + * Reference to function of this type is part of the notifier_callback_config_t callback configuration structure. + * Depending on callback type, function of this prototype is called (see NOTIFIER_SwitchConfig()) + * before configuration switch, after it or in both use cases to notify about + * the switch progress (see notifier_callback_type_t). When called, the type of the notification + * is passed as a parameter along with the reference to the target configuration structure (see + * notifier_notification_block_t) and any data passed during the callback registration. When notified before the + * configuration switch, depending on the configuration switch policy (see notifier_policy_t), the callback may deny the + * execution of the user function by returning an error code different than kStatus_Success (see + * NOTIFIER_SwitchConfig()). + * + * @param notify Notification block. + * @param data Callback data. Refers to the data passed during callback registration. Intended to + * pass any driver or application data such as internal state information. + * @return An error code or kStatus_Success. + */ +typedef status_t (*notifier_callback_t)(notifier_notification_block_t *notify, void *data); + +/*! + * @brief Callback configuration structure. + * + * This structure holds the configuration of callbacks. + * Callbacks of this type are expected to be statically allocated. + * This structure contains the following application-defined data. + * callback - pointer to the callback function + * callbackType - specifies when the callback is called + * callbackData - pointer to the data passed to the callback. + */ +typedef struct _notifier_callback_config +{ + notifier_callback_t callback; /*!< Pointer to the callback function. */ + notifier_callback_type_t callbackType; /*!< Callback type. */ + void *callbackData; /*!< Pointer to the data passed to the callback. */ +} notifier_callback_config_t; + +/*! + * @brief Notifier handle structure. + * + * Notifier handle structure. Contains data necessary for the Notifier proper function. + * Stores references to registered configurations, callbacks, information about their numbers, + * user function, user data, and other internal data. + * NOTIFIER_CreateHandle() must be called to initialize this handle. + */ +typedef struct _notifier_handle +{ + notifier_user_config_t **configsTable; /*!< Pointer to configure table. */ + uint8_t configsNumber; /*!< Number of configurations. */ + notifier_callback_config_t *callbacksTable; /*!< Pointer to callback table. */ + uint8_t callbacksNumber; /*!< Maximum number of callback configurations. */ + uint8_t errorCallbackIndex; /*!< Index of callback returns error. */ + uint8_t currentConfigIndex; /*!< Index of current configuration. */ + notifier_user_function_t userFunction; /*!< User function. */ + void *userData; /*!< User data passed to user function. */ +} notifier_handle_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Creates a Notifier handle. + * + * @param notifierHandle A pointer to the notifier handle. + * @param configs A pointer to an array with references to all configurations which is handled by the Notifier. + * @param configsNumber Number of configurations. Size of the configuration array. + * @param callbacks A pointer to an array of callback configurations. + * If there are no callbacks to register during Notifier initialization, use NULL value. + * @param callbacksNumber Number of registered callbacks. Size of the callbacks array. + * @param userFunction User function. + * @param userData User data passed to user function. + * @return An error Code or kStatus_Success. + */ +status_t NOTIFIER_CreateHandle(notifier_handle_t *notifierHandle, + notifier_user_config_t **configs, + uint8_t configsNumber, + notifier_callback_config_t *callbacks, + uint8_t callbacksNumber, + notifier_user_function_t userFunction, + void *userData); + +/*! + * @brief Switches the configuration according to a pre-defined structure. + * + * This function sets the system to the target configuration. Before transition, + * the Notifier sends notifications to all callbacks registered to the callback table. + * Callbacks are invoked in the following order: All registered callbacks are notified + * ordered by index in the callbacks array. The same order is used for before and after switch notifications. + * The notifications before the configuration switch can be used to obtain confirmation about + * the change from registered callbacks. If any registered callback denies the + * configuration change, further execution of this function depends on the notifier policy: the + * configuration change is either forced (kNOTIFIER_PolicyForcible) or exited (kNOTIFIER_PolicyAgreement). + * When configuration change is forced, the result of the before switch notifications are ignored. If an + * agreement is required, if any callback returns an error code, further notifications + * before switch notifications are cancelled and all already notified callbacks are re-invoked. + * The index of the callback which returned error code during pre-switch notifications is stored + * (any error codes during callbacks re-invocation are ignored) and NOTIFIER_GetErrorCallback() can be used to get it. + * Regardless of the policies, if any callback returns an error code, an error code indicating in which phase + * the error occurred is returned when NOTIFIER_SwitchConfig() exits. + * @param notifierHandle pointer to notifier handle + * @param configIndex Index of the target configuration. + * @param policy Transaction policy, kNOTIFIER_PolicyAgreement or kNOTIFIER_PolicyForcible. + * + * @return An error code or kStatus_Success. + * + */ +status_t NOTIFIER_SwitchConfig(notifier_handle_t *notifierHandle, uint8_t configIndex, notifier_policy_t policy); + +/*! + * @brief This function returns the last failed notification callback. + * + * This function returns an index of the last callback that failed during the configuration switch while + * the last NOTIFIER_SwitchConfig() was called. If the last NOTIFIER_SwitchConfig() call ended successfully + * value equal to callbacks number is returned. The returned value represents an index in the array of + * static call-backs. + * + * @param notifierHandle Pointer to the notifier handle + * @return Callback Index of the last failed callback or value equal to callbacks count. + */ +uint8_t NOTIFIER_GetErrorCallbackIndex(notifier_handle_t *notifierHandle); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_NOTIFIER_H_ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/fsl_shell.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/fsl_shell.c new file mode 100644 index 0000000000..1f79287206 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/fsl_shell.c @@ -0,0 +1,971 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * POSIX getopt for Windows + * Code given out at the 1985 UNIFORUM conference in Dallas. + * + * From std-unix@ut-sally.UUCP (Moderator, John Quarterman) Sun Nov 3 14:34:15 1985 + * Relay-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site gatech.CSNET + * Posting-Version: version B 2.10.2 9/18/84; site ut-sally.UUCP + * Path: gatech!akgua!mhuxv!mhuxt!mhuxr!ulysses!allegra!mit-eddie!genrad!panda!talcott!harvard!seismo!ut-sally!std-unix + * From: std-unix@ut-sally.UUCP (Moderator, John Quarterman) + * Newsgroups: mod.std.unix + * Subject: public domain AT&T getopt source + * Message-ID: <3352@ut-sally.UUCP> + * Date: 3 Nov 85 19:34:15 GMT + * Date-Received: 4 Nov 85 12:25:09 GMT + * Organization: IEEE/P1003 Portable Operating System Environment Committee + * Lines: 91 + * Approved: jsq@ut-sally.UUC + * Here's something you've all been waiting for: the AT&T public domain + * source for getopt(3). It is the code which was given out at the 1985 + * UNIFORUM conference in Dallas. I obtained it by electronic mail + * directly from AT&T. The people there assure me that it is indeed + * in the public domain + * There is no manual page. That is because the one they gave out at + * UNIFORUM was slightly different from the current System V Release 2 + * manual page. The difference apparently involved a note about the + * famous rules 5 and 6, recommending using white space between an option + * and its first argument, and not grouping options that have arguments. + * Getopt itself is currently lenient about both of these things White + * space is allowed, but not mandatory, and the last option in a group can + * have an argument. That particular version of the man page evidently + * has no official existence, and my source at AT&T did not send a copy. + * The current SVR2 man page reflects the actual behavor of this getopt. + * However, I am not about to post a copy of anything licensed by AT&T. + */ + +#include +#include +#include +#include "fsl_str.h" + +#include "generic_list.h" +#include "serial_manager.h" + +#include "fsl_shell.h" + +/* + * The OSA_USED macro can only be defined when the OSA component is used. + * If the source code of the OSA component does not exist, the OSA_USED cannot be defined. + * OR, If OSA component is not added into project event the OSA source code exists, the OSA_USED + * also cannot be defined. + * The source code path of the OSA component is /components/osa. + * + */ +#if defined(OSA_USED) + +#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U)) +#include "common_task.h" +#else +#include "fsl_os_abstraction.h" +#endif + +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define KEY_ESC (0x1BU) +#define KET_DEL (0x7FU) + +#define SHELL_EVENT_DATA_ARRIVED (1U << 0) +#define SHELL_EVENT_DATA_SENT (1U << 1) + +#define SHELL_SPRINTF_BUFFER_SIZE (64U) + +/*! @brief A type for the handle special key. */ +typedef enum _fun_key_status +{ + kSHELL_Normal = 0U, /*!< Normal key */ + kSHELL_Special = 1U, /*!< Special key */ + kSHELL_Function = 2U, /*!< Function key */ +} fun_key_status_t; + +/*! @brief Data structure for Shell environment. */ +typedef struct _shell_context_handle +{ + list_t commandContextListHead; /*!< Command shellContextHandle list queue head */ + serial_handle_t serialHandle; /*!< Serial manager handle */ + uint8_t + serialWriteHandleBuffer[SERIAL_MANAGER_WRITE_HANDLE_SIZE]; /*!< The buffer for serial manager write handle */ + serial_write_handle_t serialWriteHandle; /*!< The serial manager write handle */ + uint8_t serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE]; /*!< The buffer for serial manager read handle */ + serial_read_handle_t serialReadHandle; /*!< The serial manager read handle */ + char *prompt; /*!< Prompt string */ +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U)) + common_task_message_t commontaskMsg; /*!< Message for common task */ +#else + uint8_t event[OSA_EVENT_HANDLE_SIZE]; /*!< Event instance */ + uint8_t taskId[OSA_TASK_HANDLE_SIZE]; /*!< Task handle */ +#endif + +#endif + +#endif + char line[SHELL_BUFFER_SIZE]; /*!< Consult buffer */ + char hist_buf[SHELL_HISTORY_COUNT][SHELL_BUFFER_SIZE]; /*!< History buffer*/ + char printBuffer[SHELL_SPRINTF_BUFFER_SIZE]; /*!< Buffer for print */ + uint32_t printLength; /*!< All length has been printed */ + uint16_t hist_current; /*!< Current history command in hist buff*/ + uint16_t hist_count; /*!< Total history command in hist buff*/ + enum _fun_key_status stat; /*!< Special key status */ + uint8_t cmd_num; /*!< Number of user commands */ + uint8_t l_pos; /*!< Total line position */ + uint8_t c_pos; /*!< Current line position */ + volatile uint8_t notificationPost; /*!< The serial manager notification is post */ + uint8_t exit; /*!< Exit Flag*/ + uint8_t printBusy; /*!< Print is busy */ +} shell_context_handle_t; + +#define SHELL_STRUCT_OFFSET(type, field) ((size_t) & (((type *)0)->field)) +#define SHEEL_COMMAND_POINTER(node) ((shell_command_t *)(((uint32_t)node) - SHELL_STRUCT_OFFSET(shell_command_t, link))) +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static shell_status_t SHELL_HelpCommand(shell_handle_t shellHandle, int32_t argc, char **argv); /*!< help command */ + +static shell_status_t SHELL_ExitCommand(shell_handle_t shellHandle, int32_t argc, char **argv); /*!< exit command */ + +static int32_t SHELL_ParseLine(const char *cmd, uint32_t len, char *argv[]); /*!< parse line command */ + +static int32_t SHELL_StringCompare(const char *str1, const char *str2, int32_t count); /*!< compare string command */ + +static void SHELL_ProcessCommand(shell_context_handle_t *shellContextHandle, const char *cmd); /*!< process a command */ + +static void SHELL_GetHistoryCommand(shell_context_handle_t *shellContextHandle, + uint8_t hist_pos); /*!< get commands history */ + +static void SHELL_AutoComplete(shell_context_handle_t *shellContextHandle); /*!< auto complete command */ + +static shell_status_t SHELL_GetChar(shell_context_handle_t *shellContextHandle, + uint8_t *ch); /*!< get a char from communication interface */ + +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) +static void SHELL_Task(void *param); /*!< Shell task*/ +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +static SHELL_COMMAND_DEFINE(help, "\r\n\"help\": List all the registered commands\r\n", SHELL_HelpCommand, 0); +static SHELL_COMMAND_DEFINE(exit, "\r\n\"exit\": Exit program\r\n", SHELL_ExitCommand, 0); + +static char s_paramBuffer[SHELL_BUFFER_SIZE]; + +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U)) + +#else +/* + * \brief Defines the serial manager task's stack + */ +OSA_TASK_DEFINE(SHELL_Task, SHELL_TASK_PRIORITY, 1, SHELL_TASK_STACK_SIZE, false); +#endif + +#endif + +#endif +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) +static void SHELL_SerialManagerRxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + shell_context_handle_t *shellHandle; + + assert(callbackParam); + assert(message); + + shellHandle = (shell_context_handle_t *)callbackParam; + + if (!shellHandle->notificationPost) + { + shellHandle->notificationPost = 1U; +#if defined(OSA_USED) + +#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U)) + shellHandle->commontaskMsg.callback = SHELL_Task; + shellHandle->commontaskMsg.callbackParam = shellHandle; + COMMON_TASK_post_message(&shellHandle->commontaskMsg); +#else + (void)OSA_EventSet((osa_event_handle_t)shellHandle->event, SHELL_EVENT_DATA_ARRIVED); +#endif + +#else + SHELL_Task(shellHandle); +#endif + } +} +#endif + +static void SHELL_WriteBuffer(char *buffer, int32_t *indicator, char val, int len) +{ + shell_context_handle_t *shellContextHandle; + int i = 0; + shellContextHandle = (shell_context_handle_t *)buffer; + + for (i = 0; i < len; i++) + { + if ((uint32_t)(*indicator + 1) >= SHELL_SPRINTF_BUFFER_SIZE) + { + (void)SerialManager_WriteBlocking(shellContextHandle->serialWriteHandle, + (uint8_t *)shellContextHandle->printBuffer, (uint32_t)*indicator); + shellContextHandle->printLength += (uint32_t)*indicator; + *indicator = 0; + } + + shellContextHandle->printBuffer[*indicator] = val; + (*indicator)++; + } +} + +static int SHELL_Sprintf(void *buffer, const char *formatString, va_list ap) +{ + shell_context_handle_t *shellContextHandle; + uint32_t length; + shellContextHandle = (shell_context_handle_t *)buffer; + + length = (uint32_t)StrFormatPrintf(formatString, ap, (char *)buffer, SHELL_WriteBuffer); + shellContextHandle->printLength += length; + return (int32_t)length; +} + +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) +static void SHELL_Task(void *param) +#else +void SHELL_Task(shell_handle_t shellHandle) +#endif +{ +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) + shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)param; +#else + shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)shellHandle; +#endif + uint8_t ch; + + if (NULL != shellContextHandle) + { +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U)) +#else + osa_event_flags_t ev = 0; + + do + { + if (KOSA_StatusSuccess == OSA_EventWait((osa_event_handle_t)shellContextHandle->event, osaEventFlagsAll_c, + false, osaWaitForever_c, &ev)) + { + if (ev & SHELL_EVENT_DATA_ARRIVED) +#endif + +#endif + +#endif + { + shellContextHandle->notificationPost = 0; + do + { + if ((bool)shellContextHandle->exit) + { + if (shellContextHandle->serialReadHandle != NULL) + { + (void)SerialManager_CloseReadHandle(shellContextHandle->serialReadHandle); + shellContextHandle->serialReadHandle = NULL; + } + if (shellContextHandle->serialWriteHandle != NULL) + { + (void)SerialManager_CloseWriteHandle(shellContextHandle->serialWriteHandle); + shellContextHandle->serialWriteHandle = NULL; + } + break; + } + if (kStatus_SHELL_Success != (shell_status_t)SHELL_GetChar(shellContextHandle, &ch)) + { + /* If error occurred when getting a char, exit the task and waiting the new data arriving. */ + break; + } + + /* Special key */ + if (ch == KEY_ESC) + { + shellContextHandle->stat = kSHELL_Special; + continue; + } + else if (shellContextHandle->stat == kSHELL_Special) + { + /* Function key */ + if ((char)ch == '[') + { + shellContextHandle->stat = kSHELL_Function; + continue; + } + shellContextHandle->stat = kSHELL_Normal; + } + else if (shellContextHandle->stat == kSHELL_Function) + { + shellContextHandle->stat = kSHELL_Normal; + + switch ((uint8_t)ch) + { + /* History operation here */ + case 'A': /* Up key */ + SHELL_GetHistoryCommand(shellContextHandle, (uint8_t)shellContextHandle->hist_current); + if (shellContextHandle->hist_current < (shellContextHandle->hist_count - 1U)) + { + shellContextHandle->hist_current++; + } + break; + case 'B': /* Down key */ + SHELL_GetHistoryCommand(shellContextHandle, (uint8_t)shellContextHandle->hist_current); + if (shellContextHandle->hist_current > 0U) + { + shellContextHandle->hist_current--; + } + break; + case 'D': /* Left key */ + if ((bool)shellContextHandle->c_pos) + { + (void)SHELL_Write(shellContextHandle, "\b", 1); + shellContextHandle->c_pos--; + } + break; + case 'C': /* Right key */ + if (shellContextHandle->c_pos < shellContextHandle->l_pos) + { + (void)SHELL_Write(shellContextHandle, + &shellContextHandle->line[shellContextHandle->c_pos], 1); + shellContextHandle->c_pos++; + } + break; + default: + break; + } + continue; + } + /* Handle tab key */ + else if ((char)ch == '\t') + { +#if SHELL_AUTO_COMPLETE + /* Move the cursor to the beginning of line */ + int i; + for (i = 0; i < shellContextHandle->c_pos; i++) + { + (void)SHELL_Write(shellContextHandle, "\b", 1); + } + /* Do auto complete */ + SHELL_AutoComplete(shellContextHandle); + /* Move position to end */ + shellContextHandle->c_pos = shellContextHandle->l_pos = (uint8_t)strlen(shellContextHandle->line); +#endif + continue; + } + /* Handle backspace key */ + else if ((ch == KET_DEL) || ((char)ch == '\b')) + { + /* There must be at last one char */ + if (shellContextHandle->c_pos == 0U) + { + continue; + } + + shellContextHandle->l_pos--; + shellContextHandle->c_pos--; + + if (shellContextHandle->l_pos > shellContextHandle->c_pos) + { + (void)memmove(&shellContextHandle->line[shellContextHandle->c_pos], + &shellContextHandle->line[shellContextHandle->c_pos + 1U], + shellContextHandle->l_pos - shellContextHandle->c_pos); + shellContextHandle->line[shellContextHandle->l_pos] = 0U; + (void)SHELL_Write(shellContextHandle, "\b", 1); + (void)SHELL_Write(shellContextHandle, &shellContextHandle->line[shellContextHandle->c_pos], + strlen(&shellContextHandle->line[shellContextHandle->c_pos])); + (void)SHELL_Write(shellContextHandle, " \b", 3); + + /* Reset position */ + int i; + for (i = shellContextHandle->c_pos; i <= shellContextHandle->l_pos; i++) + { + (void)SHELL_Write(shellContextHandle, "\b", 1); + } + } + else /* Normal backspace operation */ + { + (void)SHELL_Write(shellContextHandle, "\b \b", 3); + shellContextHandle->line[shellContextHandle->l_pos] = 0U; + } + continue; + } + else + { + } + + /* Input too long */ + if (shellContextHandle->l_pos >= (SHELL_BUFFER_SIZE - 1U)) + { + shellContextHandle->l_pos = 0; + } + + /* Handle end of line, break */ + if (((char)ch == '\r') || ((char)ch == '\n')) + { + static char endoflinechar = 0U; + + if (((uint8_t)endoflinechar != 0U) && ((uint8_t)endoflinechar != ch)) + { + continue; + } + else + { + endoflinechar = (char)ch; + (void)SHELL_Write(shellContextHandle, "\r\n", 2); + /* If command line is NULL, will start a new transfer */ + if (0U == strlen(shellContextHandle->line)) + { + (void)SHELL_Write(shellContextHandle, shellContextHandle->prompt, + strlen(shellContextHandle->prompt)); + continue; + } + SHELL_ProcessCommand(shellContextHandle, shellContextHandle->line); + /* Reset all params */ + shellContextHandle->c_pos = shellContextHandle->l_pos = 0; + shellContextHandle->hist_current = 0; + (void)SHELL_Write(shellContextHandle, shellContextHandle->prompt, + strlen(shellContextHandle->prompt)); + memset(shellContextHandle->line, 0, sizeof(shellContextHandle->line)); + continue; + } + } + + /* Normal character */ + if (shellContextHandle->c_pos < shellContextHandle->l_pos) + { + (void)memmove(&shellContextHandle->line[shellContextHandle->c_pos + 1U], + &shellContextHandle->line[shellContextHandle->c_pos], + shellContextHandle->l_pos - shellContextHandle->c_pos); + shellContextHandle->line[shellContextHandle->c_pos] = (char)ch; + (void)SHELL_Write(shellContextHandle, &shellContextHandle->line[shellContextHandle->c_pos], + strlen(&shellContextHandle->line[shellContextHandle->c_pos])); + /* Move the cursor to new position */ + int i; + for (i = shellContextHandle->c_pos; i < shellContextHandle->l_pos; i++) + { + (void)SHELL_Write(shellContextHandle, "\b", 1); + } + } + else + { + shellContextHandle->line[shellContextHandle->l_pos] = (char)ch; + (void)SHELL_Write(shellContextHandle, &shellContextHandle->line[shellContextHandle->l_pos], 1); + } + + ch = 0; + shellContextHandle->l_pos++; + shellContextHandle->c_pos++; + } while (!shellContextHandle->exit); + } +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U)) +#else + } + } while (gUseRtos_c); +#endif + +#endif + +#endif + } +} + +static shell_status_t SHELL_HelpCommand(shell_handle_t shellHandle, int32_t argc, char **argv) +{ + shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)shellHandle; + shell_command_t *shellCommandContextHandle; + list_element_handle_t p = LIST_GetHead(&shellContextHandle->commandContextListHead); + + while (p != NULL) + { + shellCommandContextHandle = SHEEL_COMMAND_POINTER(p); + if ((shellCommandContextHandle->pcHelpString != NULL) && (bool)strlen(shellCommandContextHandle->pcHelpString)) + { + (void)SHELL_Write(shellContextHandle, shellCommandContextHandle->pcHelpString, + strlen(shellCommandContextHandle->pcHelpString)); + } + + p = LIST_GetNext(p); + } + return kStatus_SHELL_Success; +} + +static shell_status_t SHELL_ExitCommand(shell_handle_t shellHandle, int32_t argc, char **argv) +{ + shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)shellHandle; + /* Skip warning */ + (void)SHELL_Write(shellContextHandle, "\r\nSHELL exited\r\n", strlen("\r\nSHELL exited\r\n")); + shellContextHandle->exit = (uint8_t) true; + return kStatus_SHELL_Success; +} + +static void SHELL_ProcessCommand(shell_context_handle_t *shellContextHandle, const char *cmd) +{ + shell_command_t *tmpCommand = NULL; + const char *tmpCommandString; + int32_t argc; + char *argv[SHELL_BUFFER_SIZE]; + list_element_handle_t p; + uint8_t flag = 1; + uint8_t tmpCommandLen; + uint8_t tmpLen; + uint8_t i = 0; + + tmpLen = (uint8_t)strlen(cmd); + argc = SHELL_ParseLine(cmd, tmpLen, argv); + + if ((argc > 0)) + { + p = LIST_GetHead(&shellContextHandle->commandContextListHead); + while (p != NULL) + { + tmpCommand = SHEEL_COMMAND_POINTER(p); + tmpCommandString = tmpCommand->pcCommand; + tmpCommandLen = (uint8_t)strlen(tmpCommandString); + /* Compare with space or end of string */ + if ((cmd[tmpCommandLen] == ' ') || (cmd[tmpCommandLen] == (char)0x00)) + { + if (SHELL_StringCompare(tmpCommandString, argv[0], (uint32_t)tmpCommandLen) == 0) + { + /* support commands with optional number of parameters */ + if (tmpCommand->cExpectedNumberOfParameters == (uint8_t)SHELL_IGNORE_PARAMETER_COUNT) + { + flag = 0; + } + else if ((tmpCommand->cExpectedNumberOfParameters == 0U) && (argc == 1)) + { + flag = 0; + } + else if (tmpCommand->cExpectedNumberOfParameters > 0U) + { + if ((argc - 1U) == tmpCommand->cExpectedNumberOfParameters) + { + flag = 0; + } + } + else + { + flag = 1; + } + break; + } + } + p = LIST_GetNext(p); + } + if (NULL == p) + { + tmpCommand = NULL; + } + } + + if ((tmpCommand != NULL) && (flag == 1U)) + { + (void)SHELL_Write( + shellContextHandle, + "\r\nIncorrect command parameter(s). Enter \"help\" to view a list of available commands.\r\n\r\n", + strlen( + "\r\nIncorrect command parameter(s). Enter \"help\" to view a list of available commands.\r\n\r\n")); + tmpCommand = NULL; + } + else if (tmpCommand != NULL) + { + tmpLen = (uint8_t)strlen(cmd); + /* Compare with last command. Push back to history buffer if different */ + if (tmpLen != (uint8_t)SHELL_StringCompare(cmd, shellContextHandle->hist_buf[0], (int32_t)strlen(cmd))) + { + for (i = SHELL_HISTORY_COUNT - 1U; i > 0U; i--) + { + (void)memset(shellContextHandle->hist_buf[i], '\0', SHELL_BUFFER_SIZE); + tmpLen = (uint8_t)strlen(shellContextHandle->hist_buf[i - 1U]); + (void)memcpy(shellContextHandle->hist_buf[i], shellContextHandle->hist_buf[i - 1U], tmpLen); + } + (void)memset(shellContextHandle->hist_buf[0], '\0', SHELL_BUFFER_SIZE); + tmpLen = (uint8_t)strlen(cmd); + (void)memcpy(shellContextHandle->hist_buf[0], cmd, tmpLen); + if (shellContextHandle->hist_count < SHELL_HISTORY_COUNT) + { + shellContextHandle->hist_count++; + } + } + tmpCommand->pFuncCallBack(shellContextHandle, argc, argv); + tmpCommand = NULL; + } + else + { + (void)SHELL_Write( + shellContextHandle, + "\r\nCommand not recognized. Enter 'help' to view a list of available commands.\r\n\r\n", + strlen("\r\nCommand not recognized. Enter 'help' to view a list of available commands.\r\n\r\n")); + tmpCommand = NULL; + } +} + +static void SHELL_GetHistoryCommand(shell_context_handle_t *shellContextHandle, uint8_t hist_pos) +{ + uint8_t i; + uint32_t tmp; + + if (shellContextHandle->hist_buf[0][0] == '\0') + { + shellContextHandle->hist_current = 0; + return; + } + +#if 0 /*hist_pos is passed from hist_current. And hist_current is only changed in case 'A'/'B',as hist_count is 3 \ + most, it can't be more than 3 */ + if (hist_pos >= SHELL_HISTORY_COUNT) + { + hist_pos = SHELL_HISTORY_COUNT - 1U; + } +#endif + + tmp = strlen(shellContextHandle->line); + /* Clear current if have */ + if (tmp > 0U) + { + (void)memset(shellContextHandle->line, '\0', tmp); + for (i = 0; i < tmp; i++) + { + (void)SHELL_Write(shellContextHandle, "\b \b", 3); + } + } + + shellContextHandle->l_pos = (uint8_t)strlen(shellContextHandle->hist_buf[hist_pos]); + shellContextHandle->c_pos = shellContextHandle->l_pos; + (void)memcpy(shellContextHandle->line, shellContextHandle->hist_buf[hist_pos], shellContextHandle->l_pos); + (void)SHELL_Write(shellContextHandle, shellContextHandle->hist_buf[hist_pos], + strlen(shellContextHandle->hist_buf[hist_pos])); +} + +static void SHELL_AutoComplete(shell_context_handle_t *shellContextHandle) +{ + int32_t minLen; + list_element_handle_t p; + shell_command_t *tmpCommand = NULL; + const char *namePtr; + const char *cmdName; + + minLen = SHELL_BUFFER_SIZE; + namePtr = NULL; + + /* Empty tab, list all commands */ + if (shellContextHandle->line[0] == '\0') + { + (void)SHELL_HelpCommand(shellContextHandle, 0, NULL); + return; + } + + SHELL_Write(shellContextHandle, "\r\n", 2); + + /* Do auto complete */ + p = LIST_GetHead(&shellContextHandle->commandContextListHead); + while (p != NULL) + { + tmpCommand = SHEEL_COMMAND_POINTER(p); + cmdName = tmpCommand->pcCommand; + if (SHELL_StringCompare(shellContextHandle->line, cmdName, (int32_t)strlen(shellContextHandle->line)) == 0) + { + /* Show possible matches */ + SHELL_Printf(shellContextHandle, "%s\r\n", (char *)cmdName); + if (minLen > strlen(cmdName)) + { + namePtr = cmdName; + minLen = (int32_t)strlen(namePtr); + } + } + p = LIST_GetNext(p); + } + /* Auto complete string */ + if (namePtr != NULL) + { + (void)memcpy(shellContextHandle->line, namePtr, (uint32_t)minLen); + } + (void)SHELL_Write(shellContextHandle, shellContextHandle->prompt, strlen(shellContextHandle->prompt)); + (void)SHELL_Write(shellContextHandle, shellContextHandle->line, strlen(shellContextHandle->line)); + return; +} + +static int32_t SHELL_StringCompare(const char *str1, const char *str2, int32_t count) +{ + while ((bool)(count--)) + { + if (*str1++ != *str2++) + { + return (int32_t) * (unsigned char *)(str1 - 1) - *(unsigned char *)(str2 - 1); + } + } + return 0; +} + +static int32_t SHELL_ParseLine(const char *cmd, uint32_t len, char *argv[]) +{ + uint32_t argc; + char *p; + uint32_t position; + + /* Init params */ + (void)memset(s_paramBuffer, '\0', len + 1U); + (void)memcpy(s_paramBuffer, cmd, len); + + p = s_paramBuffer; + position = 0; + argc = 0; + + while (position < len) + { + /* Skip all blanks */ + while ((position < len) && ((char)(*p) == ' ')) + { + *p = '\0'; + p++; + position++; + } + + if (position >= len) + { + break; + } + + /* Process begin of a string */ + if (*p == '"') + { + p++; + position++; + argv[argc] = p; + argc++; + /* Skip this string */ + while ((*p != '"') && (position < len)) + { + p++; + position++; + } + /* Skip '"' */ + *p = '\0'; + p++; + position++; + } + else /* Normal char */ + { + argv[argc] = p; + argc++; + while (((char)*p != ' ') && (position < len)) + { + p++; + position++; + } + } + } + return (int32_t)argc; +} + +static shell_status_t SHELL_GetChar(shell_context_handle_t *shellContextHandle, uint8_t *ch) +{ +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) + uint32_t length = 0; + + SerialManager_TryRead(shellContextHandle->serialReadHandle, ch, 1, &length); + + if (length > 0) + { + return kStatus_SHELL_Success; + } + else + { + return kStatus_SHELL_Error; + } +#else + return (shell_status_t)SerialManager_ReadBlocking(shellContextHandle->serialReadHandle, ch, 1); +#endif +} + +shell_status_t SHELL_Init(shell_handle_t shellHandle, serial_handle_t serialHandle, char *prompt) +{ + shell_context_handle_t *shellContextHandle; + serial_manager_status_t status = kStatus_SerialManager_Error; + (void)status; + + assert(shellHandle); + assert(serialHandle); + assert(prompt); + + if (SHELL_HANDLE_SIZE < sizeof(shell_context_handle_t)) + { + return kStatus_SHELL_Error; + } + + shellContextHandle = (shell_context_handle_t *)shellHandle; + + /* memory set for shellHandle */ + (void)memset(shellHandle, 0, SHELL_HANDLE_SIZE); + +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U)) + COMMON_TASK_init(); +#else + if (KOSA_StatusSuccess != OSA_EventCreate((osa_event_handle_t)shellContextHandle->event, true)) + { + return kStatus_SHELL_Error; + } + + if (KOSA_StatusSuccess != + OSA_TaskCreate((osa_task_handle_t)shellContextHandle->taskId, OSA_TASK(SHELL_Task), shellContextHandle)) + { + return kStatus_SHELL_Error; + } +#endif + +#endif + +#endif + + shellContextHandle->prompt = prompt; + shellContextHandle->serialHandle = serialHandle; + + shellContextHandle->serialWriteHandle = (serial_write_handle_t)&shellContextHandle->serialWriteHandleBuffer[0]; + status = SerialManager_OpenWriteHandle(shellContextHandle->serialHandle, shellContextHandle->serialWriteHandle); + assert(kStatus_SerialManager_Success == status); + + shellContextHandle->serialReadHandle = (serial_read_handle_t)&shellContextHandle->serialReadHandleBuffer[0]; + status = SerialManager_OpenReadHandle(shellContextHandle->serialHandle, shellContextHandle->serialReadHandle); + assert(kStatus_SerialManager_Success == status); + +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) + SerialManager_InstallRxCallback(shellContextHandle->serialReadHandle, SHELL_SerialManagerRxCallback, + shellContextHandle); +#endif + + (void)SHELL_RegisterCommand(shellContextHandle, SHELL_COMMAND(help)); + (void)SHELL_RegisterCommand(shellContextHandle, SHELL_COMMAND(exit)); + + (void)SHELL_Write(shellContextHandle, "\r\nSHELL build: ", strlen("\r\nSHELL build: ")); + (void)SHELL_Write(shellContextHandle, __DATE__, strlen(__DATE__)); + (void)SHELL_Write(shellContextHandle, "\r\nCopyright 2018 NXP\r\n", + strlen("\r\nCopyright 2018 NXP\r\n")); + (void)SHELL_Write(shellContextHandle, shellContextHandle->prompt, strlen(shellContextHandle->prompt)); + + return kStatus_SHELL_Success; +} + +shell_status_t SHELL_RegisterCommand(shell_handle_t shellHandle, shell_command_t *command) +{ + shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)shellHandle; + assert(shellHandle); + assert(command); + + /* memory set for shellHandle */ + (void)memset(&command->link, 0, sizeof(command->link)); + + (void)LIST_AddTail(&shellContextHandle->commandContextListHead, &command->link); + + return kStatus_SHELL_Success; +} + +shell_status_t SHELL_UnregisterCommand(shell_command_t *command) +{ + assert(command); + + (void)LIST_RemoveElement(&command->link); + + /* memory set for shellHandle */ + (void)memset(&command->link, 0, sizeof(command->link)); + + return kStatus_SHELL_Success; +} + +shell_status_t SHELL_Write(shell_handle_t shellHandle, char *buffer, uint32_t length) +{ + shell_context_handle_t *shellContextHandle; + uint32_t primask; + shell_status_t status = kStatus_SHELL_Error; + + assert(shellHandle); + assert(buffer); + + if (!(bool)length) + { + return kStatus_SHELL_Success; + } + + shellContextHandle = (shell_context_handle_t *)shellHandle; + + primask = DisableGlobalIRQ(); + if ((bool)shellContextHandle->printBusy) + { + EnableGlobalIRQ(primask); + return kStatus_SHELL_Error; + } + shellContextHandle->printBusy = 1U; + EnableGlobalIRQ(primask); + + status = + (shell_status_t)SerialManager_WriteBlocking(shellContextHandle->serialWriteHandle, (uint8_t *)buffer, length); + + shellContextHandle->printBusy = 0U; + + return status; +} + +int SHELL_Printf(shell_handle_t shellHandle, const char *formatString, ...) +{ + shell_context_handle_t *shellContextHandle; + uint32_t length; + uint32_t primask; + va_list ap; + + assert(shellHandle); + assert(formatString); + + shellContextHandle = (shell_context_handle_t *)shellHandle; + + primask = DisableGlobalIRQ(); + if ((bool)shellContextHandle->printBusy) + { + EnableGlobalIRQ(primask); + return -1; + } + shellContextHandle->printBusy = 1U; + EnableGlobalIRQ(primask); + + va_start(ap, formatString); + + shellContextHandle->printLength = 0U; + length = (uint32_t)SHELL_Sprintf(shellHandle, formatString, ap); + (void)SerialManager_WriteBlocking(shellContextHandle->serialWriteHandle, (uint8_t *)shellContextHandle->printBuffer, + length); + va_end(ap); + + shellContextHandle->printBusy = 0U; + return (int32_t)shellContextHandle->printLength; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/fsl_shell.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/fsl_shell.h new file mode 100644 index 0000000000..9eaf951ff0 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/fsl_shell.h @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FSL_SHELL_H__ +#define __FSL_SHELL_H__ + +/*! + * @addtogroup SHELL + * @{ + */ + +#include "fsl_common.h" +#include "serial_manager.h" +#include "generic_list.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Whether use non-blocking mode. */ +#ifndef SHELL_NON_BLOCKING_MODE +#define SHELL_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE +#endif + +/*! @brief Macro to set on/off auto-complete feature. */ +#define SHELL_AUTO_COMPLETE (1U) + +/*! @brief Macro to set console buffer size. */ +#define SHELL_BUFFER_SIZE (64U) + +/*! @brief Macro to set maximum arguments in command. */ +#define SHELL_MAX_ARGS (8U) + +/*! @brief Macro to set maximum count of history commands. */ +#define SHELL_HISTORY_COUNT (3U) + +/*! @brief Macro to bypass arguments check */ +#define SHELL_IGNORE_PARAMETER_COUNT (0xFF) + +/*! @brief The handle size of the shell module. It is the sum of the SHELL_HISTORY_COUNT * SHELL_BUFFER_SIZE + + * SHELL_BUFFER_SIZE + SERIAL_MANAGER_READ_HANDLE_SIZE + SERIAL_MANAGER_WRITE_HANDLE_SIZE*/ +#define SHELL_HANDLE_SIZE (520U) + +#define SHELL_USE_COMMON_TASK (1U) +#define SHELL_TASK_PRIORITY (2U) +#define SHELL_TASK_STACK_SIZE (1000U) + +typedef enum _shell_status +{ + kStatus_SHELL_Success = kStatus_Success, /*!< Success */ + kStatus_SHELL_Error = MAKE_STATUS(kStatusGroup_SHELL, 1), /*!< Failed */ + kStatus_SHELL_OpenWriteHandleFailed = MAKE_STATUS(kStatusGroup_SHELL, 2), /*!< Open write handle failed */ + kStatus_SHELL_OpenReadHandleFailed = MAKE_STATUS(kStatusGroup_SHELL, 3), /*!< Open read handle failed */ +} shell_status_t; + +/*! @brief The handle of the shell module */ +typedef void *shell_handle_t; + +/*! @brief User command function prototype. */ +typedef shell_status_t (*cmd_function_t)(shell_handle_t shellHandle, int32_t argc, char **argv); + +/*! @brief User command data configuration structure. */ +typedef struct _shell_command +{ + const char *pcCommand; /*!< The command that is executed. For example "help". It must be all lower case. */ + char *pcHelpString; /*!< String that describes how to use the command. It should start with the command itself, + and end with "\r\n". For example "help: Returns a list of all the commands\r\n". */ + const cmd_function_t + pFuncCallBack; /*!< A pointer to the callback function that returns the output generated by the command. */ + uint8_t cExpectedNumberOfParameters; /*!< Commands expect a fixed number of parameters, which may be zero. */ + list_element_t link; /*!< link of the element */ +} shell_command_t; + +#if defined(__ICCARM__) +/* disable misra 19.13 */ +_Pragma("diag_suppress=Pm120") +#endif +/*! + * @brief Defines the shell command structure + * + * This macro is used to define the shell command structure #shell_command_t. + * And then uses the macro SHELL_COMMAND to get the command structure pointer. + * The macro should not be used in any function. + * + * This is a example, + * @code + * SHELL_COMMAND_DEFINE(exit, "\r\n\"exit\": Exit program\r\n", SHELL_ExitCommand, 0); + * SHELL_RegisterCommand(s_shellHandle, SHELL_COMMAND(exit)); + * @endcode + * + * @param command The command string of the command. The double quotes do not need. Such as exit for "exit", + * help for "Help", read for "read". + * @param descriptor The description of the command is used for showing the command usage when "help" is typing. + * @param callback The callback of the command is used to handle the command line when the input command is matched. + * @param paramCount The max parameter count of the current command. + */ +#define SHELL_COMMAND_DEFINE(command, descriptor, callback, paramCount) \ + \ + shell_command_t g_shellCommand##command = { \ + (#command), (descriptor), (callback), (paramCount), {0}, \ + } + +/*! + * @brief Gets the shell command pointer + * + * This macro is used to get the shell command pointer. The macro should not be used before the macro + * SHELL_COMMAND_DEFINE is used. + * + * @param command The command string of the command. The double quotes do not need. Such as exit for "exit", + * help for "Help", read for "read". + */ +#define SHELL_COMMAND(command) &g_shellCommand##command + +#if defined(__ICCARM__) + _Pragma("diag_default=Pm120") +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) + extern "C" +{ +#endif /* _cplusplus */ + + /*! + * @name Shell functional operation + * @{ + */ + + /*! + * @brief Initializes the shell module + * + * This function must be called before calling all other Shell functions. + * Call operation the Shell commands with user-defined settings. + * The example below shows how to set up the Shell and + * how to call the SHELL_Init function by passing in these parameters. + * This is an example. + * @code + * static uint8_t s_shellHandleBuffer[SHELL_HANDLE_SIZE]; + * static shell_handle_t s_shellHandle = &s_shellHandleBuffer[0]; + * SHELL_Init(s_shellHandle, s_serialHandle, "Test@SHELL>"); + * @endcode + * @param shellHandle Pointer to point to a memory space of size #SHELL_HANDLE_SIZE allocated by the caller. + * @param serialHandle The serial manager module handle pointer. + * @param prompt The string prompt pointer of Shell. Only the global variable can be passed. + * @retval kStatus_SHELL_Success The shell initialization succeed. + * @retval kStatus_SHELL_Error An error occurred when the shell is initialized. + * @retval kStatus_SHELL_OpenWriteHandleFailed Open the write handle failed. + * @retval kStatus_SHELL_OpenReadHandleFailed Open the read handle failed. + */ + shell_status_t SHELL_Init(shell_handle_t shellHandle, serial_handle_t serialHandle, char *prompt); + + /*! + * @brief Registers the shell command + * + * This function is used to register the shell command by using the command configuration #shell_command_config_t. + * This is a example, + * @code + * SHELL_COMMAND_DEFINE(exit, "\r\n\"exit\": Exit program\r\n", SHELL_ExitCommand, 0); + * SHELL_RegisterCommand(s_shellHandle, SHELL_COMMAND(exit)); + * @endcode + * @param shellHandle The shell module handle pointer. + * @param command The command element. + * @retval kStatus_SHELL_Success Successfully register the command. + * @retval kStatus_SHELL_Error An error occurred. + */ + shell_status_t SHELL_RegisterCommand(shell_handle_t shellHandle, shell_command_t * shellCommand); + + /*! + * @brief Unregisters the shell command + * + * This function is used to unregister the shell command. + * + * @param command The command element. + * @retval kStatus_SHELL_Success Successfully unregister the command. + */ + shell_status_t SHELL_UnregisterCommand(shell_command_t * shellCommand); + + /*! + * @brief Sends data to the shell output stream. + * + * This function is used to send data to the shell output stream. + * + * @param shellHandle The shell module handle pointer. + * @param buffer Start address of the data to write. + * @param length Length of the data to write. + * @retval kStatus_SHELL_Success Successfully send data. + * @retval kStatus_SHELL_Error An error occurred. + */ + shell_status_t SHELL_Write(shell_handle_t shellHandle, char *buffer, uint32_t length); + + /*! + * @brief Writes formatted output to the shell output stream. + * + * Call this function to write a formatted output to the shell output stream. + * + * @param shellHandle The shell module handle pointer. + * + * @param formatString Format string. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ + int SHELL_Printf(shell_handle_t shellHandle, const char *formatString, ...); + +/*! + * @brief The task function for Shell. + * The task function for Shell; The function should be polled by upper layer. + * This function does not return until Shell command exit was called. + * + * @param shellHandle The shell module handle pointer. + */ +#if !(defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) + void SHELL_Task(shell_handle_t shellHandle); +#endif + + /* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __FSL_SHELL_H__ */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/str/fsl_str.c b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/str/fsl_str.c new file mode 100644 index 0000000000..c4d1a0c798 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/str/fsl_str.c @@ -0,0 +1,1324 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include +#include +#include +#include "fsl_str.h" +#include "fsl_debug_console_conf.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief The overflow value.*/ +#ifndef HUGE_VAL +#define HUGE_VAL (99.e99) +#endif /* HUGE_VAL */ + +#if PRINTF_ADVANCED_ENABLE +/*! @brief Specification modifier flags for printf. */ +enum _debugconsole_printf_flag +{ + kPRINTF_Minus = 0x01U, /*!< Minus FLag. */ + kPRINTF_Plus = 0x02U, /*!< Plus Flag. */ + kPRINTF_Space = 0x04U, /*!< Space Flag. */ + kPRINTF_Zero = 0x08U, /*!< Zero Flag. */ + kPRINTF_Pound = 0x10U, /*!< Pound Flag. */ + kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */ + kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */ + kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */ + kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */ +}; +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Specification modifier flags for scanf. */ +enum _debugconsole_scanf_flag +{ + kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */ + kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */ + kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */ + kSCANF_DestString = 0x8U, /*!< Destination String FLag. */ + kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */ + kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */ + kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */ + kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */ +#if SCANF_ADVANCED_ENABLE + kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */ + kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */ + kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */ + kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */ +#endif /* SCANF_ADVANCED_ENABLE */ +#if SCANF_FLOAT_ENABLE + kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */ +#endif /*PRINTF_FLOAT_ENABLE */ + kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */ +}; + +/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */ +#if defined(__CC_ARM) +#pragma diag_suppress 1256 +#endif /* __CC_ARM */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Scanline function which ignores white spaces. + * + * @param[in] s The address of the string pointer to update. + * @return String without white spaces. + */ +static uint32_t ScanIgnoreWhiteSpace(const char **s); + +/*! + * @brief Converts a radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] neg Polarity of the number. + * @param[in] radix The radix to be converted to. + * @param[in] use_caps Used to identify %x/X output format. + + * @return Length of the converted string. + */ +static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps); + +#if PRINTF_FLOAT_ENABLE +/*! + * @brief Converts a floating radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] radix The radix to be converted to. + * @param[in] precision_width Specify the precision width. + + * @return Length of the converted string. + */ +static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width); +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! + * + */ +double modf(double input_dbl, double *intpart_ptr); + +/*************Code for process formatted data*******************************/ + +static uint32_t ScanIgnoreWhiteSpace(const char **s) +{ + uint8_t count = 0; + uint8_t c; + + c = **s; + while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f')) + { + count++; + (*s)++; + c = **s; + } + return count; +} + +static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps) +{ +#if PRINTF_ADVANCED_ENABLE + int64_t a; + int64_t b; + int64_t c; + + uint64_t ua; + uint64_t ub; + uint64_t uc; +#else + int32_t a; + int32_t b; + int32_t c; + + uint32_t ua; + uint32_t ub; + uint32_t uc; +#endif /* PRINTF_ADVANCED_ENABLE */ + + int32_t nlen; + char *nstrp; + + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + + if (neg) + { +#if PRINTF_ADVANCED_ENABLE + a = *(int64_t *)nump; +#else + a = *(int32_t *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (a == 0) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (a != 0) + { +#if PRINTF_ADVANCED_ENABLE + b = (int64_t)a / (int64_t)radix; + c = (int64_t)a - ((int64_t)b * (int64_t)radix); + if (c < 0) + { + uc = (uint64_t)c; + c = (int64_t)(~uc) + 1 + '0'; + } +#else + b = a / radix; + c = a - (b * radix); + if (c < 0) + { + uc = (uint32_t)c; + c = (uint32_t)(~uc) + 1 + '0'; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + c = c + '0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + else + { +#if PRINTF_ADVANCED_ENABLE + ua = *(uint64_t *)nump; +#else + ua = *(uint32_t *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (ua == 0) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (ua != 0) + { +#if PRINTF_ADVANCED_ENABLE + ub = (uint64_t)ua / (uint64_t)radix; + uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix); +#else + ub = ua / (uint32_t)radix; + uc = ua - (ub * (uint32_t)radix); +#endif /* PRINTF_ADVANCED_ENABLE */ + + if (uc < 10) + { + uc = uc + '0'; + } + else + { + uc = uc - 10 + (use_caps ? 'A' : 'a'); + } + ua = ub; + *nstrp++ = (char)uc; + ++nlen; + } + } + return nlen; +} + +#if PRINTF_FLOAT_ENABLE +static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width) +{ + int32_t a; + int32_t b; + int32_t c; + int32_t i; + uint32_t uc; + double fa; + double dc; + double fb; + double r; + double fractpart; + double intpart; + + int32_t nlen; + char *nstrp; + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + r = *(double *)nump; + if (!r) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + fractpart = modf((double)r, (double *)&intpart); + /* Process fractional part. */ + for (i = 0; i < precision_width; i++) + { + fractpart *= radix; + } + if (r >= 0) + { + fa = fractpart + (double)0.5; + if (fa >= pow(10, precision_width)) + { + intpart++; + } + } + else + { + fa = fractpart - (double)0.5; + if (fa <= -pow(10, precision_width)) + { + intpart--; + } + } + for (i = 0; i < precision_width; i++) + { + fb = fa / (int32_t)radix; + dc = (fa - (int64_t)fb * (int32_t)radix); + c = (int32_t)dc; + if (c < 0) + { + uc = (uint32_t)c; + c = (int32_t)(~uc) + 1 + '0'; + } + else + { + c = c + '0'; + } + fa = fb; + *nstrp++ = (char)c; + ++nlen; + } + *nstrp++ = (char)'.'; + ++nlen; + a = (int32_t)intpart; + if (a == 0) + { + *nstrp++ = '0'; + ++nlen; + } + else + { + while (a != 0) + { + b = (int32_t)a / (int32_t)radix; + c = (int32_t)a - ((int32_t)b * (int32_t)radix); + if (c < 0) + { + uc = (uint32_t)c; + c = (int32_t)(~uc) + 1 + '0'; + } + else + { + c = c + '0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + return nlen; +} +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! + * brief This function outputs its parameters according to a formatted string. + * + * note I/O is performed by calling given function pointer using following + * (*func_ptr)(c); + * + * param[in] fmt_ptr Format string for printf. + * param[in] args_ptr Arguments to printf. + * param[in] buf pointer to the buffer + * param cb print callback function pointer + * + * return Number of characters to be print + */ +int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb) +{ + /* va_list ap; */ + char *p; + int32_t c; + + char vstr[33]; + char *vstrp = NULL; + int32_t vlen = 0; + + int32_t done; + int32_t count = 0; + + uint32_t field_width; + uint32_t precision_width; + char *sval; + int32_t cval; + bool use_caps; + uint8_t radix = 0; + +#if PRINTF_ADVANCED_ENABLE + uint32_t flags_used; + int32_t schar, dschar; + int64_t ival; + uint64_t uval = 0; + bool valid_precision_width; +#else + int32_t ival; + uint32_t uval = 0; +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_FLOAT_ENABLE + double fval; +#endif /* PRINTF_FLOAT_ENABLE */ + + /* Start parsing apart the format string and display appropriate formats and data. */ + for (p = (char *)fmt; (c = *p) != 0; p++) + { + /* + * All formats begin with a '%' marker. Special chars like + * '\n' or '\t' are normally converted to the appropriate + * character by the __compiler__. Thus, no need for this + * routine to account for the '\' character. + */ + if (c != '%') + { + cb(buf, &count, c, 1); + /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */ + continue; + } + + use_caps = true; + +#if PRINTF_ADVANCED_ENABLE + /* First check for specification modifier flags. */ + flags_used = 0; + done = false; + while (!done) + { + switch (*++p) + { + case '-': + flags_used |= kPRINTF_Minus; + break; + case '+': + flags_used |= kPRINTF_Plus; + break; + case ' ': + flags_used |= kPRINTF_Space; + break; + case '0': + flags_used |= kPRINTF_Zero; + break; + case '#': + flags_used |= kPRINTF_Pound; + break; + default: + /* We've gone one char too far. */ + --p; + done = true; + break; + } + } +#endif /* PRINTF_ADVANCED_ENABLE */ + + /* Next check for minimum field width. */ + field_width = 0; + done = false; + while (!done) + { + c = *++p; + if ((c >= '0') && (c <= '9')) + { + field_width = (field_width * 10) + (c - '0'); + } +#if PRINTF_ADVANCED_ENABLE + else if (c == '*') + { + field_width = (uint32_t)va_arg(ap, uint32_t); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --p; + done = true; + } + } + /* Next check for the width and precision field separator. */ + precision_width = 6; +#if PRINTF_ADVANCED_ENABLE + valid_precision_width = false; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (*++p == '.') + { + /* Must get precision field width, if present. */ + precision_width = 0; + done = false; + while (!done) + { + c = *++p; + if ((c >= '0') && (c <= '9')) + { + precision_width = (precision_width * 10) + (c - '0'); +#if PRINTF_ADVANCED_ENABLE + valid_precision_width = true; +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#if PRINTF_ADVANCED_ENABLE + else if (c == '*') + { + precision_width = (uint32_t)va_arg(ap, uint32_t); + valid_precision_width = true; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --p; + done = true; + } + } + } + else + { + /* We've gone one char too far. */ + --p; + } +#if PRINTF_ADVANCED_ENABLE + /* + * Check for the length modifier. + */ + switch (/* c = */ *++p) + { + case 'h': + if (*++p != 'h') + { + flags_used |= kPRINTF_LengthShortInt; + --p; + } + else + { + flags_used |= kPRINTF_LengthChar; + } + break; + case 'l': + if (*++p != 'l') + { + flags_used |= kPRINTF_LengthLongInt; + --p; + } + else + { + flags_used |= kPRINTF_LengthLongLongInt; + } + break; + default: + /* we've gone one char too far */ + --p; + break; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + /* Now we're ready to examine the format. */ + c = *++p; + { + if ((c == 'd') || (c == 'i') || (c == 'f') || (c == 'F') || (c == 'x') || (c == 'X') || (c == 'o') || + (c == 'b') || (c == 'p') || (c == 'u')) + { + if ((c == 'd') || (c == 'i')) + { +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_LengthLongLongInt) + { + ival = (int64_t)va_arg(ap, int64_t); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + ival = (int32_t)va_arg(ap, int32_t); + } + vlen = ConvertRadixNumToString(vstr, &ival, true, 10, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + if (ival < 0) + { + schar = '-'; + ++vlen; + } + else + { + if (flags_used & kPRINTF_Plus) + { + schar = '+'; + ++vlen; + } + else + { + if (flags_used & kPRINTF_Space) + { + schar = ' '; + ++vlen; + } + else + { + schar = 0; + } + } + } + dschar = false; + /* Do the ZERO pad. */ + if (flags_used & kPRINTF_Zero) + { + if (schar) + { + cb(buf, &count, schar, 1); + } + dschar = true; + + cb(buf, &count, '0', field_width - vlen); + vlen = field_width; + } + else + { + if (!(flags_used & kPRINTF_Minus)) + { + cb(buf, &count, ' ', field_width - vlen); + if (schar) + { + cb(buf, &count, schar, 1); + } + dschar = true; + } + } + /* The string was built in reverse order, now display in correct order. */ + if ((!dschar) && schar) + { + cb(buf, &count, schar, 1); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + +#if PRINTF_FLOAT_ENABLE + if ((c == 'f') || (c == 'F')) + { + fval = (double)va_arg(ap, double); + vlen = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width); + vstrp = &vstr[vlen]; + +#if PRINTF_ADVANCED_ENABLE + if (fval < 0) + { + schar = '-'; + ++vlen; + } + else + { + if (flags_used & kPRINTF_Plus) + { + schar = '+'; + ++vlen; + } + else + { + if (flags_used & kPRINTF_Space) + { + schar = ' '; + ++vlen; + } + else + { + schar = 0; + } + } + } + dschar = false; + if (flags_used & kPRINTF_Zero) + { + if (schar) + { + cb(buf, &count, schar, 1); + } + dschar = true; + cb(buf, &count, '0', field_width - vlen); + vlen = field_width; + } + else + { + if (!(flags_used & kPRINTF_Minus)) + { + cb(buf, &count, ' ', field_width - vlen); + if (schar) + { + cb(buf, &count, schar, 1); + } + dschar = true; + } + } + if ((!dschar) && schar) + { + cb(buf, &count, schar, 1); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#endif /* PRINTF_FLOAT_ENABLE */ + if ((c == 'X') || (c == 'x')) + { + if (c == 'x') + { + use_caps = false; + } +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_LengthLongLongInt) + { + uval = (uint64_t)va_arg(ap, uint64_t); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + uval = (uint32_t)va_arg(ap, uint32_t); + } + vlen = ConvertRadixNumToString(vstr, &uval, false, 16, use_caps); + vstrp = &vstr[vlen]; + +#if PRINTF_ADVANCED_ENABLE + dschar = false; + if (flags_used & kPRINTF_Zero) + { + if (flags_used & kPRINTF_Pound) + { + cb(buf, &count, '0', 1); + cb(buf, &count, (use_caps ? 'X' : 'x'), 1); + dschar = true; + } + cb(buf, &count, '0', field_width - vlen); + vlen = field_width; + } + else + { + if (!(flags_used & kPRINTF_Minus)) + { + if (flags_used & kPRINTF_Pound) + { + vlen += 2; + } + cb(buf, &count, ' ', field_width - vlen); + if (flags_used & kPRINTF_Pound) + { + cb(buf, &count, '0', 1); + cb(buf, &count, (use_caps ? 'X' : 'x'), 1); + dschar = true; + } + } + } + + if ((flags_used & kPRINTF_Pound) && (!dschar)) + { + cb(buf, &count, '0', 1); + cb(buf, &count, (use_caps ? 'X' : 'x'), 1); + vlen += 2; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u')) + { +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_LengthLongLongInt) + { + uval = (uint64_t)va_arg(ap, uint64_t); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + uval = (uint32_t)va_arg(ap, uint32_t); + } + + if (c == 'o') + { + radix = 8; + } + else if (c == 'b') + { + radix = 2; + } + else if (c == 'p') + { + radix = 16; + } + else + { + radix = 10; + } + + vlen = ConvertRadixNumToString(vstr, &uval, false, radix, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_Zero) + { + cb(buf, &count, '0', field_width - vlen); + vlen = field_width; + } + else + { + if (!(flags_used & kPRINTF_Minus)) + { + cb(buf, &count, ' ', field_width - vlen); + } + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#if !PRINTF_ADVANCED_ENABLE + cb(buf, &count, ' ', field_width - vlen); +#endif /* !PRINTF_ADVANCED_ENABLE */ + if (vstrp != NULL) + { + while (*vstrp) + { + cb(buf, &count, *vstrp--, 1); + } + } +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_Minus) + { + cb(buf, &count, ' ', field_width - vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + else if (c == 'c') + { + cval = (char)va_arg(ap, uint32_t); + cb(buf, &count, cval, 1); + } + else if (c == 's') + { + sval = (char *)va_arg(ap, char *); + if (sval) + { +#if PRINTF_ADVANCED_ENABLE + if (valid_precision_width) + { + vlen = precision_width; + } + else + { + vlen = strlen(sval); + } +#else + vlen = strlen(sval); +#endif /* PRINTF_ADVANCED_ENABLE */ +#if PRINTF_ADVANCED_ENABLE + if (!(flags_used & kPRINTF_Minus)) +#endif /* PRINTF_ADVANCED_ENABLE */ + { + cb(buf, &count, ' ', field_width - vlen); + } + +#if PRINTF_ADVANCED_ENABLE + if (valid_precision_width) + { + while ((*sval) && (vlen > 0)) + { + cb(buf, &count, *sval++, 1); + vlen--; + } + /* In case that vlen sval is shorter than vlen */ + vlen = precision_width - vlen; + } + else + { +#endif /* PRINTF_ADVANCED_ENABLE */ + while (*sval) + { + cb(buf, &count, *sval++, 1); + } +#if PRINTF_ADVANCED_ENABLE + } +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_Minus) + { + cb(buf, &count, ' ', field_width - vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + } + else + { + cb(buf, &count, c, 1); + } + } + } + + return count; +} + +/*! + * brief Converts an input line of ASCII characters based upon a provided + * string format. + * + * param[in] line_ptr The input line of ASCII data. + * param[in] format Format first points to the format string. + * param[in] args_ptr The list of parameters. + * + * return Number of input items converted and assigned. + * retval IO_EOF When line_ptr is empty string "". + */ +int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr) +{ + uint8_t base; + int8_t neg; + /* Identifier for the format string. */ + char *c = format; + char temp; + char *buf; + /* Flag telling the conversion specification. */ + uint32_t flag = 0; + /* Filed width for the matching input streams. */ + uint32_t field_width; + /* How many arguments are assigned except the suppress. */ + uint32_t nassigned = 0; + /* How many characters are read from the input streams. */ + uint32_t n_decode = 0; + + int32_t val; + + const char *s; + /* Identifier for the input string. */ + const char *p = line_ptr; + +#if SCANF_FLOAT_ENABLE + double fnum = 0.0; +#endif /* SCANF_FLOAT_ENABLE */ + /* Return EOF error before any conversion. */ + if (*p == '\0') + { + return -1; + } + + /* Decode directives. */ + while ((*c) && (*p)) + { + /* Ignore all white-spaces in the format strings. */ + if (ScanIgnoreWhiteSpace((const char **)&c)) + { + n_decode += ScanIgnoreWhiteSpace(&p); + } + else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%'))) + { + /* Ordinary characters. */ + c++; + if (*p == *c) + { + n_decode++; + p++; + c++; + } + else + { + /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream. + * However, it is deserted now. */ + break; + } + } + else + { + /* convernsion specification */ + c++; + /* Reset. */ + flag = 0; + field_width = 0; + base = 0; + + /* Loop to get full conversion specification. */ + while ((*c) && (!(flag & kSCANF_DestMask))) + { + switch (*c) + { +#if SCANF_ADVANCED_ENABLE + case '*': + if (flag & kSCANF_Suppress) + { + /* Match failure. */ + return nassigned; + } + flag |= kSCANF_Suppress; + c++; + break; + case 'h': + if (flag & kSCANF_LengthMask) + { + /* Match failure. */ + return nassigned; + } + + if (c[1] == 'h') + { + flag |= kSCANF_LengthChar; + c++; + } + else + { + flag |= kSCANF_LengthShortInt; + } + c++; + break; + case 'l': + if (flag & kSCANF_LengthMask) + { + /* Match failure. */ + return nassigned; + } + + if (c[1] == 'l') + { + flag |= kSCANF_LengthLongLongInt; + c++; + } + else + { + flag |= kSCANF_LengthLongInt; + } + c++; + break; +#endif /* SCANF_ADVANCED_ENABLE */ +#if SCANF_FLOAT_ENABLE + case 'L': + if (flag & kSCANF_LengthMask) + { + /* Match failure. */ + return nassigned; + } + flag |= kSCANF_LengthLongLongDouble; + c++; + break; +#endif /* SCANF_FLOAT_ENABLE */ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + if (field_width) + { + /* Match failure. */ + return nassigned; + } + do + { + field_width = field_width * 10 + *c - '0'; + c++; + } while ((*c >= '0') && (*c <= '9')); + break; + case 'd': + base = 10; + flag |= kSCANF_TypeSinged; + flag |= kSCANF_DestInt; + c++; + break; + case 'u': + base = 10; + flag |= kSCANF_DestInt; + c++; + break; + case 'o': + base = 8; + flag |= kSCANF_DestInt; + c++; + break; + case 'x': + case 'X': + base = 16; + flag |= kSCANF_DestInt; + c++; + break; + case 'i': + base = 0; + flag |= kSCANF_DestInt; + c++; + break; +#if SCANF_FLOAT_ENABLE + case 'a': + case 'A': + case 'e': + case 'E': + case 'f': + case 'F': + case 'g': + case 'G': + flag |= kSCANF_DestFloat; + c++; + break; +#endif /* SCANF_FLOAT_ENABLE */ + case 'c': + flag |= kSCANF_DestChar; + if (!field_width) + { + field_width = 1; + } + c++; + break; + case 's': + flag |= kSCANF_DestString; + c++; + break; + default: + return nassigned; + } + } + + if (!(flag & kSCANF_DestMask)) + { + /* Format strings are exhausted. */ + return nassigned; + } + + if (!field_width) + { + /* Large than length of a line. */ + field_width = 99; + } + + /* Matching strings in input streams and assign to argument. */ + switch (flag & kSCANF_DestMask) + { + case kSCANF_DestChar: + s = (const char *)p; + buf = va_arg(args_ptr, char *); + while ((field_width--) && (*p)) + { + if (!(flag & kSCANF_Suppress)) + { + *buf++ = *p++; + } + else + { + p++; + } + n_decode++; + } + + if ((!(flag & kSCANF_Suppress)) && (s != p)) + { + nassigned++; + } + break; + case kSCANF_DestString: + n_decode += ScanIgnoreWhiteSpace(&p); + s = p; + buf = va_arg(args_ptr, char *); + while ((field_width--) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') && + (*p != '\r') && (*p != '\v') && (*p != '\f')) + { + if (flag & kSCANF_Suppress) + { + p++; + } + else + { + *buf++ = *p++; + } + n_decode++; + } + + if ((!(flag & kSCANF_Suppress)) && (s != p)) + { + /* Add NULL to end of string. */ + *buf = '\0'; + nassigned++; + } + break; + case kSCANF_DestInt: + n_decode += ScanIgnoreWhiteSpace(&p); + s = p; + val = 0; + if ((base == 0) || (base == 16)) + { + if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) + { + base = 16; + if (field_width >= 1) + { + p += 2; + n_decode += 2; + field_width -= 2; + } + } + } + + if (base == 0) + { + if (s[0] == '0') + { + base = 8; + } + else + { + base = 10; + } + } + + neg = 1; + switch (*p) + { + case '-': + neg = -1; + n_decode++; + p++; + field_width--; + break; + case '+': + neg = 1; + n_decode++; + p++; + field_width--; + break; + default: + break; + } + + while ((*p) && (field_width--)) + { + if ((*p <= '9') && (*p >= '0')) + { + temp = *p - '0'; + } + else if ((*p <= 'f') && (*p >= 'a')) + { + temp = *p - 'a' + 10; + } + else if ((*p <= 'F') && (*p >= 'A')) + { + temp = *p - 'A' + 10; + } + else + { + temp = base; + } + + if (temp >= base) + { + break; + } + else + { + val = base * val + temp; + } + p++; + n_decode++; + } + val *= neg; + if (!(flag & kSCANF_Suppress)) + { +#if SCANF_ADVANCED_ENABLE + switch (flag & kSCANF_LengthMask) + { + case kSCANF_LengthChar: + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed char *) = (signed char)val; + } + else + { + *va_arg(args_ptr, unsigned char *) = (unsigned char)val; + } + break; + case kSCANF_LengthShortInt: + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed short *) = (signed short)val; + } + else + { + *va_arg(args_ptr, unsigned short *) = (unsigned short)val; + } + break; + case kSCANF_LengthLongInt: + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed long int *) = (signed long int)val; + } + else + { + *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val; + } + break; + case kSCANF_LengthLongLongInt: + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed long long int *) = (signed long long int)val; + } + else + { + *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val; + } + break; + default: + /* The default type is the type int. */ + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(args_ptr, unsigned int *) = (unsigned int)val; + } + break; + } +#else + /* The default type is the type int. */ + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(args_ptr, unsigned int *) = (unsigned int)val; + } +#endif /* SCANF_ADVANCED_ENABLE */ + nassigned++; + } + break; +#if SCANF_FLOAT_ENABLE + case kSCANF_DestFloat: + n_decode += ScanIgnoreWhiteSpace(&p); + fnum = strtod(p, (char **)&s); + + if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL)) + { + break; + } + + n_decode += (int)(s) - (int)(p); + p = s; + if (!(flag & kSCANF_Suppress)) + { + if (flag & kSCANF_LengthLongLongDouble) + { + *va_arg(args_ptr, double *) = fnum; + } + else + { + *va_arg(args_ptr, float *) = (float)fnum; + } + nassigned++; + } + break; +#endif /* SCANF_FLOAT_ENABLE */ + default: + return nassigned; + } + } + } + return nassigned; +} diff --git a/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/str/fsl_str.h b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/str/fsl_str.h new file mode 100644 index 0000000000..bf7adcc52a --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/MIMXRT1061/utilities/str/fsl_str.h @@ -0,0 +1,66 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FSL_STR_H +#define _FSL_STR_H + +#include "fsl_common.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief A function pointer which is used when format printf log. + */ +typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len); + +/*! + * @brief This function outputs its parameters according to a formatted string. + * + * @note I/O is performed by calling given function pointer using following + * (*func_ptr)(c); + * + * @param[in] fmt Format string for printf. + * @param[in] ap Arguments to printf. + * @param[in] buf pointer to the buffer + * @param cb print callbck function pointer + * + * @return Number of characters to be print + */ +int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb); + +/*! + * @brief Converts an input line of ASCII characters based upon a provided + * string format. + * + * @param[in] line_ptr The input line of ASCII data. + * @param[in] format Format first points to the format string. + * @param[in] args_ptr The list of parameters. + * + * @return Number of input items converted and assigned. + * @retval IO_EOF When line_ptr is empty string "". + */ +int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_STR_H */ diff --git a/bsp/imxrt/libraries/MIMXRT1061/SConscript b/bsp/imxrt/libraries/MIMXRT1061/SConscript new file mode 100644 index 0000000000..33f85d0e26 --- /dev/null +++ b/bsp/imxrt/libraries/MIMXRT1061/SConscript @@ -0,0 +1,95 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +path = [cwd + '/CMSIS/Include',cwd + '/MIMXRT1061', cwd + '/MIMXRT1061/drivers'] +src = Split(''' + MIMXRT1061/system_MIMXRT1061.c + MIMXRT1061/drivers/fsl_common.c + MIMXRT1061/drivers/fsl_clock.c + MIMXRT1061/drivers/fsl_cache.c + ''') + +if rtconfig.PLATFORM in ['gcc']: + src += ['MIMXRT1061/gcc/startup_MIMXRT1061.S'] +elif rtconfig.PLATFORM in ['armcc', 'armclang']: + src += ['MIMXRT1061/arm/startup_MIMXRT1061.s'] +elif rtconfig.PLATFORM in ['iccarm']: + src += ['MIMXRT1061/iar/startup_MIMXRT1061.s'] + +if GetDepend(['BSP_USING_GPIO']): + src += ['MIMXRT1061/drivers/fsl_gpio.c'] + +if GetDepend(['BSP_USING_LPUART']): + src += ['MIMXRT1061/drivers/fsl_lpuart.c'] + +if GetDepend(['BSP_USING_I2C']): + src += ['MIMXRT1061/drivers/fsl_lpi2c.c'] + +if GetDepend(['BSP_USING_SPI']): + src += ['MIMXRT1061/drivers/fsl_lpspi.c'] + +if GetDepend(['BSP_USING_HWTIMER']) or GetDepend(['BSP_USING_PWM']): + src += ['MIMXRT1061/drivers/fsl_gpt.c'] + +if GetDepend(['BSP_USING_PWM']): + src += ['MIMXRT1061/drivers/fsl_pwm.c'] + src += ['MIMXRT1061/drivers/fsl_qtmr.c'] + +if GetDepend(['BSP_USING_RTC']): + src += ['MIMXRT1061/drivers/fsl_snvs_hp.c'] + src += ['MIMXRT1061/drivers/fsl_snvs_lp.c'] + +if GetDepend(['BSP_USING_WDT']): + src += ['MIMXRT1061/drivers/fsl_wdog.c'] + src += ['MIMXRT1061/drivers/fsl_rtwdog.c'] + +if GetDepend(['BSP_USING_ADC']): + src += ['MIMXRT1061/drivers/fsl_adc.c'] + +if GetDepend(['BSP_USING_SDRAM']): + src += ['MIMXRT1061/drivers/fsl_semc.c'] + +if GetDepend(['BSP_USING_LCD']): + src += ['MIMXRT1061/drivers/fsl_elcdif.c'] + +if GetDepend(['BSP_USING_CAN']): + src += ['MIMXRT1061/drivers/fsl_flexcan.c'] + +if GetDepend(['BSP_USING_ETH']): + src += ['MIMXRT1061/drivers/fsl_enet.c'] + +if GetDepend(['BSP_USING_SDIO']): + src += ['MIMXRT1061/drivers/fsl_usdhc.c'] + +if GetDepend(['RT_USING_AUDIO']): + src += ['MIMXRT1061/drivers/fsl_sai.c'] + src += ['MIMXRT1061/drivers/fsl_sai_edma.c'] + +if GetDepend(['BSP_USING_LTDC']): + src += ['MIMXRT1061/drivers/'] + +if GetDepend(['BSP_USING_DMA']): + src += ['MIMXRT1061/drivers/fsl_dmamux.c'] + src += ['MIMXRT1061/drivers/fsl_edma.c'] + src += ['MIMXRT1061/drivers/fsl_lpuart_edma.c'] + if GetDepend(['BSP_USING_SPI']): + src += ['MIMXRT1061/drivers/fsl_lpspi_edma.c'] + +if GetDepend(['BSP_USING_PULSE_ENCODER']): + src += ['MIMXRT1061/drivers/fsl_enc.c'] + +#Adding this as XBAR is used in pin mux +src += ['MIMXRT1061/drivers/fsl_xbara.c'] +src += ['MIMXRT1061/drivers/fsl_xbarb.c'] + +#fsl os abstract files +src += ['MIMXRT1061/drivers/fsl_os_abstraction_rtthread.c'] +src += ['MIMXRT1061/drivers/generic_list.c'] + +if rtconfig.PLATFORM in ['gcc']: + group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, ASFLAGS = '$ASFLAGS -D __STARTUP_CLEAR_BSS') +else: + group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) + +Return('group')

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